Pass bus number argument.

lsst-ts · Aug 20, 2024 · 19e6245 · 19e6245
1 parent 7a8712c
commit 19e6245
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Showing 5 changed files with 8 additions and 11 deletions.
diff --git a/include/cRIO/FPGA.h b/include/cRIO/FPGA.h
@@ -125,10 +125,13 @@ class FPGA : public SimpleFPGA {
     /**
      * Commands FPGA to write to MPU commands buffer.
      *
+     * @param bus serial bus to write to. The FPGA can use either dedicated
+     * FIFO, or sends those data to a multiplexed FIFO sharing more serial
+     * ports on FPGA.
      * @param data data to write to the MPU command buffer
      * @param timeout timeout in milliseconds
      */
-    virtual void writeMPUFIFO(const std::vector<uint8_t>& data, uint32_t timeout) = 0;
+    virtual void writeMPUFIFO(uint8_t bus, const std::vector<uint8_t>& data, uint32_t timeout) = 0;
 
     /**
      * Commands FPGA to copy MPU output FIFO to FPGA-C/C++ output FIFO. This

diff --git a/src/LSST/cRIO/FPGA.cpp b/src/LSST/cRIO/FPGA.cpp
@@ -155,13 +155,7 @@ void FPGA::mpuCommands(MPU &mpu, const std::chrono::duration<double> &timeout) {
         // construct buffer to send
         std::vector<uint8_t> data;
 
-        data.push_back(mpu.getBus());
-        data.push_back(cmd.buffer.size() + 2);
-        data.push_back(MPUCommands::WRITE);
-        data.push_back(cmd.buffer.size());
-        data.insert(data.end(), cmd.buffer.begin(), cmd.buffer.end());
-
-        writeMPUFIFO(data, 0);
+        writeMPUFIFO(mpu.getBus(), cmd.buffer, 0);
 
         // read reply
         auto answer = readMPUFIFO(mpu);

diff --git a/tests/TestFPGA.h b/tests/TestFPGA.h
@@ -53,7 +53,7 @@ class TestFPGA : public LSST::cRIO::FPGA, public LSST::cRIO::PrintILC {
     uint16_t getTxCommand(uint8_t bus) override { return FPGAAddress::MODBUS_A_TX; }
     uint16_t getRxCommand(uint8_t bus) override { return FPGAAddress::MODBUS_A_RX; }
     uint32_t getIrq(uint8_t bus) override { return 1; }
-    void writeMPUFIFO(const std::vector<uint8_t>& data, uint32_t timeout) override {}
+    void writeMPUFIFO(uint8_t bus, const std::vector<uint8_t>& data, uint32_t timeout) override {}
     std::vector<uint8_t> readMPUFIFO(LSST::cRIO::MPU&) override {
         return std::vector<uint8_t>({0xff, 0x0fe});
     }

diff --git a/tests/test_CSC.cpp b/tests/test_CSC.cpp
@@ -45,7 +45,7 @@ class TestFPGA : public FPGA {
     uint16_t getTxCommand(uint8_t) override { return 0; }
     uint16_t getRxCommand(uint8_t) override { return 0; }
     uint32_t getIrq(uint8_t) override { return 0; }
-    void writeMPUFIFO(const std::vector<uint8_t>& data, uint32_t timeout) override {}
+    void writeMPUFIFO(uint8_t bus, const std::vector<uint8_t>& data, uint32_t timeout) override {}
     std::vector<uint8_t> readMPUFIFO(MPU&) override { return std::vector<uint8_t>({0x04, 0x05}); }
     void writeCommandFIFO(uint16_t*, size_t, uint32_t) override {}
     void writeRequestFIFO(uint16_t*, size_t, uint32_t) override {}

diff --git a/tests/test_FirmwareLoad.cpp b/tests/test_FirmwareLoad.cpp
@@ -54,7 +54,7 @@ class TestFPGA : public FPGA {
     uint16_t getRxCommand(uint8_t bus) override { return bus + 14; }
     uint32_t getIrq(uint8_t bus) override { return 1; }
 
-    void writeMPUFIFO(const std::vector<uint8_t>& data, uint32_t timeout) override {}
+    void writeMPUFIFO(uint8_t bus, const std::vector<uint8_t>& data, uint32_t timeout) override {}
     std::vector<uint8_t> readMPUFIFO(MPU& mpu) override { return std::vector<uint8_t>({0x01, 0x02}); }
 
     void writeCommandFIFO(uint16_t* data, size_t length, uint32_t timeout) override;