Update README.md

sgherbst · Mar 3, 2020 · cba86f0 · cba86f0
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 # svinst
 
 [![License: MIT](https://img.shields.io/badge/License-MIT-yellow.svg)](https://opensource.org/licenses/MIT)
+[![Actions Status](https://github.com/sgherbst/svinst/workflows/Regression/badge.svg)](https://github.com/sgherbst/svinst/actions)
+[![codecov](https://codecov.io/gh/sgherbst/svinst/branch/master/graph/badge.svg)](https://codecov.io/gh/sgherbst/svinst)
+[![Crates.io](https://img.shields.io/crates/v/svinst.svg)](https://crates.io/crates/svinst)
 
 This tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations.  It uses [sv-parser](https://github.com/dalance/sv-parser) and is adapted from [svlint](https://github.com/dalance/svlint).