Merge branch 'master' into fix-2625-bis

.gitlab-ci.yml

@@ -170,6 +170,7 @@ smoke-gen:
     SPIKE_TANDEM: 1
   script:
     - bash verif/regress/smoke-gen_tests.sh
+    - cp verif/sim/seedlist.yaml artifacts/logs/
     - !reference [.simu_after_script]
 
 smoke-bench:

core/csr_regfile.sv

@@ -1435,9 +1435,14 @@ module csr_regfile
                       | CVA6Cfg.XLEN'(riscv::MIP_MTIP)
                       | CVA6Cfg.XLEN'(riscv::MIP_MEIP);
             end else begin
-              mask = CVA6Cfg.XLEN'(riscv::MIP_MSIP)
-                      | CVA6Cfg.XLEN'(riscv::MIP_MTIP)
-                      | CVA6Cfg.XLEN'(riscv::MIP_MEIP);
+              if (CVA6Cfg.SoftwareInterruptEn) begin
+                mask = CVA6Cfg.XLEN'(riscv::MIP_MSIP)  // same shift as MSIE
+                | CVA6Cfg.XLEN'(riscv::MIP_MTIP)  // same shift as MTIE
+                | CVA6Cfg.XLEN'(riscv::MIP_MEIP);  // same shift as MEIE
+              end else begin
+                mask = CVA6Cfg.XLEN'(riscv::MIP_MTIP)  // same shift as MTIE
+                | CVA6Cfg.XLEN'(riscv::MIP_MEIP);  // same shift as MEIE
+              end
             end
           end
           mie_d = (mie_q & ~mask) | (csr_wdata & mask); // we only support supervisor and M-mode interrupts
@@ -1771,7 +1776,7 @@ module csr_regfile
     // Machine Mode External Interrupt Pending
     mip_d[riscv::IRQ_M_EXT] = irq_i[0];
     // Machine software interrupt
-    mip_d[riscv::IRQ_M_SOFT] = ipi_i;
+    mip_d[riscv::IRQ_M_SOFT] = CVA6Cfg.SoftwareInterruptEn && ipi_i;
     // Timer interrupt pending, coming from platform timer
     mip_d[riscv::IRQ_M_TIMER] = time_irq_i;
 

core/cvxif_example/copro_alu.sv

@@ -88,8 +88,32 @@ module copro_alu
         rd_n     = rd_i;
         we_n     = 1'b1;
       end
-      cvxif_instr_pkg::ADD_RS3_R4: begin
-        result_n = NrRgprPorts == 3 ? registers_i[2] + registers_i[1] + registers_i[0] : registers_i[1] + registers_i[0];
+      cvxif_instr_pkg::MADD_RS3_R4: begin
+        result_n = NrRgprPorts == 3 ? (registers_i[0] + registers_i[1] + registers_i[2]) : (registers_i[0] + registers_i[1]);
+        hartid_n = hartid_i;
+        id_n = id_i;
+        valid_n = 1'b1;
+        rd_n = rd_i;
+        we_n = 1'b1;
+      end
+      cvxif_instr_pkg::MSUB_RS3_R4: begin
+        result_n = NrRgprPorts == 3 ? (registers_i[0] - registers_i[1] - registers_i[2]) : (registers_i[0] - registers_i[1]);
+        hartid_n = hartid_i;
+        id_n = id_i;
+        valid_n = 1'b1;
+        rd_n = rd_i;
+        we_n = 1'b1;
+      end
+      cvxif_instr_pkg::NMADD_RS3_R4: begin
+        result_n = NrRgprPorts == 3 ? ~(registers_i[0] + registers_i[1] + registers_i[2]) : ~(registers_i[0] + registers_i[1]);
+        hartid_n = hartid_i;
+        id_n = id_i;
+        valid_n = 1'b1;
+        rd_n = rd_i;
+        we_n = 1'b1;
+      end
+      cvxif_instr_pkg::NMSUB_RS3_R4: begin
+        result_n = NrRgprPorts == 3 ? ~(registers_i[0] - registers_i[1] - registers_i[2]) : ~(registers_i[0] - registers_i[1]);
         hartid_n = hartid_i;
         id_n = id_i;
         valid_n = 1'b1;

core/cvxif_example/include/cvxif_instr_pkg.sv

@@ -18,8 +18,11 @@ package cvxif_instr_pkg;
     DOUBLE_RS1 = 4'b0011,
     DOUBLE_RS2 = 4'b0100,
     ADD_MULTI = 4'b0101,
-    ADD_RS3_R4 = 4'b0110,
-    ADD_RS3_R = 4'b0111
+    MADD_RS3_R4 = 4'b0110,
+    MSUB_RS3_R4 = 4'b0111,
+    NMADD_RS3_R4 = 4'b1000,
+    NMSUB_RS3_R4 = 4'b1001,
+    ADD_RS3_R = 4'b1111
   } opcode_t;
 
 
@@ -105,31 +108,31 @@ package cvxif_instr_pkg;
           32'b00000_00_00000_00000_0_00_00000_1000011,  // MADD opcode
           mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
           resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
-          opcode : ADD_RS3_R4
+          opcode : MADD_RS3_R4
       },
       '{
           // Custom Add Multi rs1 : cus_add rd, rs1, rs1
           instr:
           32'b00000_00_00000_00000_0_00_00000_1000111,  // MSUB opcode
           mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
           resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
-          opcode : ADD_RS3_R4
+          opcode : MSUB_RS3_R4
       },
       '{
           // Custom Add Multi rs1 : cus_add rd, rs1, rs1
           instr:
           32'b00000_00_00000_00000_0_00_00000_1001011,  // NMSUB opcode
           mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
           resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
-          opcode : ADD_RS3_R4
+          opcode : NMSUB_RS3_R4
       },
       '{
           // Custom Add Multi rs1 : cus_add rd, rs1, rs1
           instr:
           32'b00000_00_00000_00000_0_00_00000_1001111,  // NMADD opcode
           mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
           resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
-          opcode : ADD_RS3_R4
+          opcode : NMADD_RS3_R4
       }
   };
 

core/include/ariane_pkg.sv

@@ -31,8 +31,6 @@ package ariane_pkg;
   // TODO: Slowly move those parameters to the new system.
   localparam BITS_SATURATION_COUNTER = 2;
 
-  localparam ISSUE_WIDTH = 1;
-
   // depth of store-buffers, this needs to be a power of two
   localparam logic [2:0] DEPTH_SPEC = 'd4;
 

core/include/build_config_pkg.sv

@@ -95,6 +95,7 @@ package build_config_pkg;
     cfg.MmuPresent = CVA6Cfg.MmuPresent;
     cfg.RVS = CVA6Cfg.RVS;
     cfg.RVU = CVA6Cfg.RVU;
+    cfg.SoftwareInterruptEn = CVA6Cfg.SoftwareInterruptEn;
 
     cfg.HaltAddress = CVA6Cfg.HaltAddress;
     cfg.ExceptionAddress = CVA6Cfg.ExceptionAddress;

core/include/config_pkg.sv

@@ -94,6 +94,8 @@ package config_pkg;
     bit                          RVS;
     // User mode
     bit                          RVU;
+    // Software interrupts are enabled
+    bit                          SoftwareInterruptEn;
     // Debug support
     bit                          DebugEn;
     // Base address of the debug module
@@ -277,8 +279,9 @@ package config_pkg;
     bit          EnableAccelerator;
     bit          PerfCounterEn;
     bit          MmuPresent;
-    bit          RVS;                //Supervisor mode
-    bit          RVU;                //User mode
+    bit          RVS;                  //Supervisor mode
+    bit          RVU;                  //User mode
+    bit          SoftwareInterruptEn;
 
     logic [63:0] HaltAddress;
     logic [63:0] ExceptionAddress;
@@ -389,6 +392,10 @@ package config_pkg;
     assert (!(Cfg.SuperscalarEn && Cfg.RVZCMP));
     assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64)
     else $fatal(1, "[frontend] fetch width != not supported");
+    // Support for disabling MIP.MSIP and MIE.MSIE in Hypervisor and Supervisor mode is not supported
+    // Software Interrupt can be disabled when there is only M machine mode in CVA6.
+    assert (!(Cfg.RVS && !Cfg.SoftwareInterruptEn));
+    assert (!(Cfg.RVH && !Cfg.SoftwareInterruptEn));
     // pragma translate_on
   endfunction
 

core/include/cv32a60x_config_pkg.sv

@@ -55,6 +55,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(0),
       RVS: bit'(0),
       RVU: bit'(0),
+      SoftwareInterruptEn: bit'(0),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(2),

core/include/cv32a65x_config_pkg.sv

@@ -55,6 +55,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(0),
       RVS: bit'(0),
       RVU: bit'(0),
+      SoftwareInterruptEn: bit'(0),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(2),

core/include/cv32a6_embedded_config_pkg_deprecated.sv

@@ -42,6 +42,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -106,6 +109,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(0),
       RVU: bit'(0),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
@@ -139,6 +143,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
@@ -140,6 +141,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: bit'(0),
+      DcacheInvalidateOnFlush: bit'(0),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),

core/include/cv32a6_imac_sv0_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
@@ -140,6 +141,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: bit'(0),
+      DcacheInvalidateOnFlush: bit'(0),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -106,6 +106,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
@@ -136,10 +137,12 @@ package cva6_config_pkg;
       IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
       IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
       IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
+      DCacheType: CVA6ConfigDcacheType,
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
-      DCacheType: CVA6ConfigDcacheType,
+      DcacheFlushOnFence: bit'(0),
+      DcacheInvalidateOnFlush: bit'(0),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),

core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv

@@ -43,6 +43,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -107,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
@@ -140,6 +144,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv

@@ -117,6 +117,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv

@@ -117,6 +117,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv

@@ -43,6 +43,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -107,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
@@ -140,6 +144,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),

core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv

@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdch_sv39_config_pkg.sv

@@ -43,6 +43,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -107,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
@@ -140,6 +144,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),