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Threshold fixes
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@calebbiggers
calebbiggers committed May 14, 2024
1 parent d04d4e8 commit e269c6b
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Showing 14 changed files with 112 additions and 112 deletions.
12 changes: 6 additions & 6 deletions BDW/metrics/perf/broadwell_metrics_perf.json
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Expand Up @@ -570,14 +570,14 @@
"MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Ret;Retire;Metric",
"MetricName": "tma_info_thread_uoppi",
"MetricThreshold": "tma_info_thread_uoppi > 105"
"MetricThreshold": "tma_info_thread_uoppi > 1.05"
},
{
"BriefDescription": "Uops per taken branch",
"MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Metric",
"MetricName": "tma_info_thread_uptb",
"MetricThreshold": "tma_info_thread_uptb < 4 * 15"
"MetricThreshold": "tma_info_thread_uptb < 4 * 1.5"
},
{
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
Expand Down Expand Up @@ -740,7 +740,7 @@
"MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB",
"MetricName": "tma_info_frontend_dsb_coverage",
"MetricThreshold": "tma_info_frontend_dsb_coverage < 07 & ipc / 4 > 035"
"MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35"
},
{
"BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)",
Expand Down Expand Up @@ -845,7 +845,7 @@
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=0x1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=0x1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / tma_info_core_core_clks",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 05"
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
Expand Down Expand Up @@ -924,7 +924,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "OS;Metric",
"MetricName": "tma_info_system_kernel_utilization",
"MetricThreshold": "tma_info_system_kernel_utilization > 005"
"MetricThreshold": "tma_info_system_kernel_utilization > 0.05"
},
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
Expand All @@ -950,7 +950,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary;Clocks",
"MetricName": "tma_info_system_mux",
"MetricThreshold": "tma_info_system_mux > 11 | tma_info_system_mux < 09"
"MetricThreshold": "tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9"
},
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
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12 changes: 6 additions & 6 deletions BDX/metrics/perf/broadwellx_metrics_perf.json
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Expand Up @@ -832,14 +832,14 @@
"MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Ret;Retire;Metric",
"MetricName": "tma_info_thread_uoppi",
"MetricThreshold": "tma_info_thread_uoppi > 105"
"MetricThreshold": "tma_info_thread_uoppi > 1.05"
},
{
"BriefDescription": "Uops per taken branch",
"MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Metric",
"MetricName": "tma_info_thread_uptb",
"MetricThreshold": "tma_info_thread_uptb < 4 * 15"
"MetricThreshold": "tma_info_thread_uptb < 4 * 1.5"
},
{
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
Expand Down Expand Up @@ -1002,7 +1002,7 @@
"MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB",
"MetricName": "tma_info_frontend_dsb_coverage",
"MetricThreshold": "tma_info_frontend_dsb_coverage < 07 & ipc / 4 > 035"
"MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35"
},
{
"BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)",
Expand Down Expand Up @@ -1107,7 +1107,7 @@
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * tma_info_core_core_clks )",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 05"
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
Expand Down Expand Up @@ -1192,7 +1192,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "OS;Metric",
"MetricName": "tma_info_system_kernel_utilization",
"MetricThreshold": "tma_info_system_kernel_utilization > 005"
"MetricThreshold": "tma_info_system_kernel_utilization > 0.05"
},
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
Expand Down Expand Up @@ -1230,7 +1230,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary;Clocks",
"MetricName": "tma_info_system_mux",
"MetricThreshold": "tma_info_system_mux > 11 | tma_info_system_mux < 09"
"MetricThreshold": "tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9"
},
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
Expand Down
18 changes: 9 additions & 9 deletions CLX/metrics/perf/cascadelakex_metrics_perf.json
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Expand Up @@ -1126,7 +1126,7 @@
"MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0",
"MetricGroup": "Cor;SMT;Metric",
"MetricName": "tma_info_botlnk_l0_core_bound_likely",
"MetricThreshold": "tma_info_botlnk_core_bound_likely > 05"
"MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5"
},
{
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
Expand All @@ -1139,14 +1139,14 @@
"MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Ret;Retire;Metric",
"MetricName": "tma_info_thread_uoppi",
"MetricThreshold": "tma_info_thread_uoppi > 105"
"MetricThreshold": "tma_info_thread_uoppi > 1.05"
},
{
"BriefDescription": "Uops per taken branch",
"MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Metric",
"MetricName": "tma_info_thread_uptb",
"MetricThreshold": "tma_info_thread_uptb < 4 * 15"
"MetricThreshold": "tma_info_thread_uptb < 4 * 1.5"
},
{
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
Expand Down Expand Up @@ -1360,7 +1360,7 @@
"MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )",
"MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB",
"MetricName": "tma_info_frontend_dsb_coverage",
"MetricThreshold": "tma_info_frontend_dsb_coverage < 07 & ipc / 4 > 035"
"MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35"
},
{
"BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
Expand Down Expand Up @@ -1571,7 +1571,7 @@
"MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * tma_info_core_core_clks )",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 05"
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
Expand Down Expand Up @@ -1698,14 +1698,14 @@
"MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_core_clks",
"MetricGroup": "Power;Core_Metric",
"MetricName": "tma_info_system_power_license1_utilization",
"MetricThreshold": "tma_info_system_power_license1_utilization > 05"
"MetricThreshold": "tma_info_system_power_license1_utilization > 0.5"
},
{
"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions.",
"MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_core_clks",
"MetricGroup": "Power;Core_Metric",
"MetricName": "tma_info_system_power_license2_utilization",
"MetricThreshold": "tma_info_system_power_license2_utilization > 05"
"MetricThreshold": "tma_info_system_power_license2_utilization > 0.5"
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
Expand All @@ -1718,7 +1718,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "OS;Metric",
"MetricName": "tma_info_system_kernel_utilization",
"MetricThreshold": "tma_info_system_kernel_utilization > 005"
"MetricThreshold": "tma_info_system_kernel_utilization > 0.05"
},
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
Expand Down Expand Up @@ -1792,7 +1792,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary;Clocks",
"MetricName": "tma_info_system_mux",
"MetricThreshold": "tma_info_system_mux > 11 | tma_info_system_mux < 09"
"MetricThreshold": "tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9"
},
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
Expand Down
18 changes: 9 additions & 9 deletions EMR/metrics/perf/emeraldrapids_metrics_perf.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1250,7 +1250,7 @@
"MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0",
"MetricGroup": "Cor;SMT;Metric",
"MetricName": "tma_info_botlnk_l0_core_bound_likely",
"MetricThreshold": "tma_info_botlnk_core_bound_likely > 05"
"MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5"
},
{
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
Expand All @@ -1263,14 +1263,14 @@
"MetricExpr": "( tma_retiring * tma_info_thread_slots ) / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Ret;Retire;Metric",
"MetricName": "tma_info_thread_uoppi",
"MetricThreshold": "tma_info_thread_uoppi > 105"
"MetricThreshold": "tma_info_thread_uoppi > 1.05"
},
{
"BriefDescription": "Uops per taken branch",
"MetricExpr": "( tma_retiring * tma_info_thread_slots ) / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Metric",
"MetricName": "tma_info_thread_uptb",
"MetricThreshold": "tma_info_thread_uptb < 6 * 15"
"MetricThreshold": "tma_info_thread_uptb < 6 * 1.5"
},
{
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
Expand Down Expand Up @@ -1466,7 +1466,7 @@
"MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=0x1@",
"MetricGroup": "MicroSeq;Pipeline;Ret;Metric",
"MetricName": "tma_info_pipeline_strings_cycles",
"MetricThreshold": "tma_info_pipeline_strings_cycles > 01"
"MetricThreshold": "tma_info_pipeline_strings_cycles > 0.1"
},
{
"BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)",
Expand Down Expand Up @@ -1504,7 +1504,7 @@
"MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )",
"MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB",
"MetricName": "tma_info_frontend_dsb_coverage",
"MetricThreshold": "tma_info_frontend_dsb_coverage < 07 & ipc / 6 > 035"
"MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 6 > 0.35"
},
{
"BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.",
Expand Down Expand Up @@ -1748,7 +1748,7 @@
"MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_core_core_clks )",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 05"
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
Expand Down Expand Up @@ -1905,7 +1905,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "OS;Metric",
"MetricName": "tma_info_system_kernel_utilization",
"MetricThreshold": "tma_info_system_kernel_utilization > 005"
"MetricThreshold": "tma_info_system_kernel_utilization > 0.05"
},
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
Expand All @@ -1919,7 +1919,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.C0_WAIT / tma_info_thread_clks",
"MetricGroup": "C0Wait;Metric",
"MetricName": "tma_info_system_c0_wait",
"MetricThreshold": "tma_info_system_c0_wait > 005"
"MetricThreshold": "tma_info_system_c0_wait > 0.05"
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
Expand Down Expand Up @@ -1981,7 +1981,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary;Clocks",
"MetricName": "tma_info_system_mux",
"MetricThreshold": "tma_info_system_mux > 11 | tma_info_system_mux < 09"
"MetricThreshold": "tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9"
},
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
Expand Down
12 changes: 6 additions & 6 deletions HSW/metrics/perf/haswell_metrics_perf.json
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Original file line number Diff line number Diff line change
Expand Up @@ -498,14 +498,14 @@
"MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Ret;Retire;Metric",
"MetricName": "tma_info_thread_uoppi",
"MetricThreshold": "tma_info_thread_uoppi > 105"
"MetricThreshold": "tma_info_thread_uoppi > 1.05"
},
{
"BriefDescription": "Uops per taken branch",
"MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Metric",
"MetricName": "tma_info_thread_uptb",
"MetricThreshold": "tma_info_thread_uptb < 4 * 15"
"MetricThreshold": "tma_info_thread_uptb < 4 * 1.5"
},
{
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
Expand Down Expand Up @@ -602,7 +602,7 @@
"MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB",
"MetricName": "tma_info_frontend_dsb_coverage",
"MetricThreshold": "tma_info_frontend_dsb_coverage < 07 & ipc / 4 > 035"
"MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35"
},
{
"BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)",
Expand Down Expand Up @@ -683,7 +683,7 @@
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / tma_info_core_core_clks",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 05"
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
Expand Down Expand Up @@ -756,7 +756,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "OS;Metric",
"MetricName": "tma_info_system_kernel_utilization",
"MetricThreshold": "tma_info_system_kernel_utilization > 005"
"MetricThreshold": "tma_info_system_kernel_utilization > 0.05"
},
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
Expand All @@ -782,7 +782,7 @@
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary;Clocks",
"MetricName": "tma_info_system_mux",
"MetricThreshold": "tma_info_system_mux > 11 | tma_info_system_mux < 09"
"MetricThreshold": "tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9"
},
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
Expand Down
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