Merge pull request #147 from edwarddavidbaker/sync-platforms

SRF, GRR, CLX, SKX, LNL, MTL, SKL: Release event updates
intel · Mar 1, 2024 · 3cf984d · 3cf984d
2 parents 451067e + 56ab8d8
commit 3cf984d
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diff --git a/CLX/events/cascadelakex_core.json b/CLX/events/cascadelakex_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V1.20",
-    "DatePublished": "08/01/2023",
-    "Version": "1.20",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V1.21",
+    "DatePublished": "02/23/2024",
+    "Version": "1.21",
     "Legend": ""
   },
   "Events": [
@@ -1020,7 +1020,7 @@
       "UMask": "0x20",
       "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
       "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
-      "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",
+      "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture).  This includes high current AVX 512-bit instructions.",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "200003",
@@ -2579,8 +2579,8 @@
       "EventCode": "0x79",
       "UMask": "0x18",
       "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
-      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
-      "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
+      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
+      "PublicDescription": "Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -2627,8 +2627,8 @@
       "EventCode": "0x79",
       "UMask": "0x18",
       "EventName": "IDQ.DSB_CYCLES_OK",
-      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
-      "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
+      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
+      "PublicDescription": "Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -3060,7 +3060,7 @@
       "UMask": "0x10",
       "EventName": "ITLB_MISSES.WALK_PENDING",
       "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
-      "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
+      "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "100003",
@@ -4068,7 +4068,7 @@
       "UMask": "0x01",
       "EventName": "DSB2MITE_SWITCHES.COUNT",
       "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
-      "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
+      "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay.",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -4751,7 +4751,7 @@
       "Invert": "0",
       "AnyThread": "0",
       "EdgeDetect": "0",
-      "PEBS": "1",
+      "PEBS": "2",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "SKL091, SKL044",
@@ -6335,7 +6335,7 @@
       "Invert": "0",
       "AnyThread": "0",
       "EdgeDetect": "0",
-      "PEBS": "1",
+      "PEBS": "2",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",

diff --git a/CLX/events/cascadelakex_fp_arith_inst.json b/CLX/events/cascadelakex_fp_arith_inst.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V1.20",
-    "DatePublished": "08/01/2023",
-    "Version": "1.20",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V1.21",
+    "DatePublished": "02/23/2024",
+    "Version": "1.21",
     "Legend": ""
   },
   "Events": [

diff --git a/CLX/events/cascadelakex_uncore.json b/CLX/events/cascadelakex_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V1.20",
-    "DatePublished": "08/01/2023",
-    "Version": "1.20",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V1.21",
+    "DatePublished": "02/23/2024",
+    "Version": "1.21",
     "Legend": ""
   },
   "Events": [

diff --git a/CLX/events/cascadelakex_uncore_experimental.json b/CLX/events/cascadelakex_uncore_experimental.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V1.20",
-    "DatePublished": "08/01/2023",
-    "Version": "1.20",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V1.21",
+    "DatePublished": "02/23/2024",
+    "Version": "1.21",
     "Legend": ""
   },
   "Events": [
@@ -4408,7 +4408,7 @@
       "UMaskExt": "0x00",
       "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
       "BriefDescription": "Coherent Ops; PCIRdCur",
-      "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+      "PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
       "Counter": "0,1",
       "MSRValue": "0x00",
       "ELLC": "0",
@@ -4426,7 +4426,7 @@
       "UMaskExt": "0x00",
       "EventName": "UNC_I_COHERENT_OPS.CRD",
       "BriefDescription": "Coherent Ops; CRd",
-      "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+      "PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
       "Counter": "0,1",
       "MSRValue": "0x00",
       "ELLC": "0",
@@ -4444,7 +4444,7 @@
       "UMaskExt": "0x00",
       "EventName": "UNC_I_COHERENT_OPS.DRD",
       "BriefDescription": "Coherent Ops; DRd",
-      "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+      "PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
       "Counter": "0,1",
       "MSRValue": "0x00",
       "ELLC": "0",
@@ -4462,7 +4462,7 @@
       "UMaskExt": "0x00",
       "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
       "BriefDescription": "Coherent Ops; PCIDCAHin5t",
-      "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+      "PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
       "Counter": "0,1",
       "MSRValue": "0x00",
       "ELLC": "0",
@@ -4480,7 +4480,7 @@
       "UMaskExt": "0x00",
       "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
       "BriefDescription": "Coherent Ops; WbMtoI",
-      "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+      "PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
       "Counter": "0,1",
       "MSRValue": "0x00",
       "ELLC": "0",
@@ -4498,7 +4498,7 @@
       "UMaskExt": "0x00",
       "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
       "BriefDescription": "Coherent Ops; CLFlush",
-      "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+      "PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
       "Counter": "0,1",
       "MSRValue": "0x00",
       "ELLC": "0",
@@ -5182,7 +5182,7 @@
       "UMaskExt": "0x00",
       "EventName": "UNC_I_TRANSACTIONS.WRITES",
       "BriefDescription": "Inbound Transaction Count; Writes",
-      "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+      "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
       "Counter": "0,1",
       "MSRValue": "0x00",
       "ELLC": "0",