first pass fud2 support for edsl to flame graph

calyxir · Jan 14, 2025 · eeed3c7 · eeed3c7
1 parent 6719f6f
commit eeed3c7
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Showing 4 changed files with 73 additions and 7 deletions.
diff --git a/fud2/scripts/profiler.rhai b/fud2/scripts/profiler.rhai
@@ -2,10 +2,8 @@ import "calyx" as c;
 import "verilator" as v;
 import "rtl_sim" as sim;
 
-export const instrumented_verilog = state("verilog-instrumented", ["sv"]);
-export const instrumented_sim = state("sim-instrumented", ["exe"]);
-export const instrumented_vcd = state("vcd-instrumented", ["vcd"]);
 export const flamegraph = state("flamegraph", ["svg"]);
+export const edsl = state("edsl", ["py"]);
 
 fn profiling_setup(e) {
     e.var_("cells", "cells.json");
@@ -31,6 +29,62 @@ fn profiling_setup(e) {
     // Standalone Verilog testbench. copied from testbench
     e.rsrc("tb.sv");
 
+    // ---- eDSL to Calyx to flame graph.
+    e.rule("edsl-to-calyx", "python3 $in > $out");
+
+    // NOTE: this will go when we have an actual parser and tool to emit json.
+    e.var_("parse-metadata-script", "$calyx-base/tools/profiler/poc-lift-flame-graph.py");
+    e.var_("metadata-mapping-json", "metadata-map.json");
+    e.rule("parse-metadata", "python3 $parse-metadata-script $in $metadata-mapping-json");
+
+    e.rule("parse-vcd-from-adl", "python3 $parse-vcd-script $in $cells $metadata-mapping-json profiler-out $out");
+}
+
+// first pass. probably worth merging with calyx_to_flamegraph one of these days
+fn edsl_to_flamegraph(e, input, output) {
+    // create calyx file
+    let calyx = "calyx.futil";
+    e.build_cmd([calyx], "edsl-to-calyx", [input], []);
+
+    // create metatdata mapping file
+    e.build_cmd(["$metadata-mapping-json"], "parse-metadata", [calyx], []);
+
+    // instrument calyx and produce verilog
+    let instrumented_verilog = "instrumented.sv";
+    e.build_cmd(["$cells"], "component-cells", [calyx], []);
+    e.build_cmd([instrumented_verilog], "calyx", [calyx], []);
+    e.arg("backend", "verilog");
+    e.arg("args", "-p static-inline -p compile-static -p compile-repeat -p compile-invoke -p profiler-instrumentation $passes");
+
+    let instrumented_sim = "instrumented.exe";
+    // verilog --> sim; adapted from verilator::verilator_build()
+    let verilator_out_dir = "verilator-out";
+    let sim_bin = `${verilator_out_dir}/Vtoplevel`;
+    e.build_cmd(
+      [sim_bin],
+      "verilator-compile-standalone-tb",
+      [instrumented_verilog],
+      ["tb.sv"],
+    );
+    e.arg("out-dir", verilator_out_dir);
+    e.build("cp", sim_bin, instrumented_sim);
+
+    let instrumented_vcd = "instrumented.vcd";
+    // sim --> vcd; adapted from rtl_sim
+    e.build_cmd(
+        ["sim.log", instrumented_vcd],
+        "sim-run",
+        [instrumented_sim, "$datadir"],
+        [],
+    );
+    e.arg("bin", instrumented_sim);
+    e.arg("args", `+NOTRACE=0 +OUT=${instrumented_vcd}`);
+
+    // vcd --> flamegraph
+    let elems_profiled_json = "elems-profiled.json";
+    let flamegraph_folded = "flamegraph.folded";
+    e.build_cmd([flamegraph_folded], "parse-vcd-from-adl", [instrumented_vcd], ["$cells", "$metadata-mapping-json"]);
+    e.build_cmd([output], "create-visuals", [flamegraph_folded], []);
 }
 
 fn calyx_to_flamegraph(e, input, output) {
@@ -79,3 +133,10 @@ op(
     flamegraph,
     |e, input, output| calyx_to_flamegraph(e, input, output)
 );
+
+op("edsl-profiler",
+    [c::calyx_setup, profiling_setup, v::verilator_setup, sim::sim_setup],
+    edsl,
+    flamegraph,
+    |e, input, output| edsl_to_flamegraph(e, input, output)
+)
diff --git a/fud2/tests/snapshots/tests__list_ops.snap b/fud2/tests/snapshots/tests__list_ops.snap
@@ -1,5 +1,6 @@
 ---
 source: fud2/tests/tests.rs
+snapshot_kind: text
 ---
 [
     (
@@ -57,6 +58,11 @@ source: fud2/tests/tests.rs
         "cider",
         "cider-debug",
     ),
+    (
+        "edsl-profiler",
+        "edsl",
+        "flamegraph",
+    ),
     (
         "firrtl",
         "firrtl",

diff --git a/fud2/tests/snapshots/tests__list_states.snap b/fud2/tests/snapshots/tests__list_states.snap
@@ -1,5 +1,6 @@
 ---
 source: fud2/tests/tests.rs
+snapshot_kind: text
 ---
 [
     "calyx",
@@ -8,18 +9,16 @@ source: fud2/tests/tests.rs
     "cocotb-axi",
     "dahlia",
     "dat",
+    "edsl",
     "firrtl",
     "firrtl-with-primitives",
     "flamegraph",
     "jq",
     "mrxl",
     "primitive-uses-json",
     "sim",
-    "sim-instrumented",
     "vcd",
-    "vcd-instrumented",
     "verilog",
-    "verilog-instrumented",
     "verilog-noverify",
     "verilog-refmem",
     "verilog-refmem-noverify",

diff --git a/fud2/tests/snapshots/tests__test@plan_profiler.snap b/fud2/tests/snapshots/tests__test@plan_profiler.snap
@@ -26,7 +26,7 @@ rule component-cells
   command = $component_cells -l $calyx-base $in > $out
 parse-vcd-script = $calyx-base/tools/profiler/profiler-process.py
 rule parse-vcd
-  command = python3 $parse-vcd-script $in $cells profiler-out $out
+  command = python3 $parse-vcd-script $in $cells NA profiler-out $out
 
 verilator = verilator
 cycle-limit = 500000000