use chisel 6.2.0

Martoni · Mar 8, 2024 · 38e58cc · 38e58cc
1 parent 3ce7fae
commit 38e58cc
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Showing 9 changed files with 88 additions and 31 deletions.
diff --git a/build.sbt b/build.sbt
@@ -1,30 +1,27 @@
 // See README.md for license details.
 
+val majorChiselVersion = "6"
+val minorChiselVersion = "2.0"
+
+val chiselVersion = majorChiselVersion + "." + minorChiselVersion
 
 scalaVersion     := "2.13.8"
-version          := "0.1.1"
+version          := chiselVersion
 organization     := "eu.fabienm"
 
-val majorChiselVersion = "3"
-val minorChiselVersion = "5.6"
-
-val chiselVersion = majorChiselVersion + "." + minorChiselVersion
-
 lazy val root = (project in file("."))
   .settings(
     name := "hdmicore",
     libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "chisel3" % chiselVersion,
-      "edu.berkeley.cs" %% "chiseltest" % ("0." + minorChiselVersion) % "test",
-      "Martoni" %% "fpgamacro" % "0.2.2"
+      "org.chipsalliance" %% "chisel" % chiselVersion,
+      "Martoni" %% "fpgamacro" % "6.2.1"
     ),
     scalacOptions ++= Seq(
-      "-Xsource:2.11",
       "-language:reflectiveCalls",
       "-deprecation",
       "-feature",
       "-Xcheckinit",
+      "-Ymacro-annotations",
     ),
-    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full),
+    addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
   )
-
diff --git a/generate_all_verilog_sources.sh b/generate_all_verilog_sources.sh
@@ -0,0 +1,8 @@
+#!/usr/bin/bash
+
+sbt "runMain hdmicore.Rgb2Tmds"
+sbt "runMain hdmicore.TMDSEncoder"
+sbt "runMain hdmicore.platforms.TangNano4k"
+sbt "runMain hdmicore.platforms.TangNano9k"
+sbt "runMain hdmicore.platforms.Ulx3s"
+sbt "runMain hdmicore.video.HVSyncDriver"
diff --git a/src/main/scala/Rgb2Tmds.scala b/src/main/scala/Rgb2Tmds.scala
@@ -1,8 +1,8 @@
 package hdmicore
 
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 
 class Rgb2Tmds extends Module {
   val io = IO(new Bundle {
@@ -35,6 +35,14 @@ class Rgb2Tmds extends Module {
 }
 
 object Rgb2Tmds extends App {
-  (new ChiselStage).execute(args,
-    Seq(ChiselGeneratorAnnotation(() => new Rgb2Tmds())))
+  val verilog_src = ChiselStage
+    .emitSystemVerilog(new Rgb2Tmds,
+        firtoolOpts = Array(
+          "-disable-all-randomization",
+           "--lowering-options=disallowLocalVariables", // avoid 'automatic logic'
+           "-strip-debug-info"))
+  val fverilog = os.pwd / "Rgb2Tmds.v"
+  if(os.exists(fverilog))
+    os.remove(fverilog)
+  os.write(fverilog, verilog_src)
 }
diff --git a/src/main/scala/TmdsEncoder.scala b/src/main/scala/TmdsEncoder.scala
@@ -1,8 +1,8 @@
 package hdmicore
 
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 
 class TMDSEncoder extends Module {
   val io = IO(new Bundle {
@@ -93,6 +93,15 @@ class TMDSEncoder extends Module {
 }
 
 object TMDSEncoder extends App {
-  (new ChiselStage).execute(args,
-    Seq(ChiselGeneratorAnnotation(() => new TMDSEncoder())))
+  val verilog_src = ChiselStage
+    .emitSystemVerilog(
+        new TMDSEncoder,
+        firtoolOpts = Array(
+          "-disable-all-randomization",
+           "--lowering-options=disallowLocalVariables", // avoid 'automatic logic'
+           "-strip-debug-info"))
+  val fverilog = os.pwd / "TMDSEncoder.v"
+  if(os.exists(fverilog))
+    os.remove(fverilog)
+  os.write(fverilog, verilog_src)
 }
diff --git a/src/main/scala/TmdsIncludes.scala b/src/main/scala/TmdsIncludes.scala
@@ -2,7 +2,6 @@ package hdmicore
 
 import chisel3._
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 
 class RGBColors extends Bundle {
   val red = UInt(8.W)

diff --git a/src/main/scala/platforms/tangnano4k.scala b/src/main/scala/platforms/tangnano4k.scala
@@ -4,8 +4,8 @@ package hdmicore.platforms
  */
 
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 
 import fpgamacro.gowin.{CLKDIV, TMDS_PLLVR, TLVDS_OBUF}
 import hdmicore.{PatternExample, TMDSDiff, DiffPair, HdmiTx}
@@ -87,6 +87,15 @@ class TangNano4k(vmode: VideoMode = VideoConsts.m1280x720) extends RawModule {
 }
 
 object TangNano4k extends App {
-  (new ChiselStage).execute(args,
-    Seq(ChiselGeneratorAnnotation(() => new TangNano4k())))
+  val verilog_src = ChiselStage
+    .emitSystemVerilog(
+        new TangNano4k,
+        firtoolOpts = Array(
+          "-disable-all-randomization",
+           "--lowering-options=disallowLocalVariables", // avoid 'automatic logic'
+           "-strip-debug-info"))
+  val fverilog = os.pwd / "TangNano4k.v"
+  if(os.exists(fverilog))
+    os.remove(fverilog)
+  os.write(fverilog, verilog_src)
 }
diff --git a/src/main/scala/platforms/tangnano9k.scala b/src/main/scala/platforms/tangnano9k.scala
@@ -4,8 +4,8 @@ package hdmicore.platforms
  */
 
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 
 import fpgamacro.gowin.{CLKDIV, Gowin_rPLL, ELVDS_OBUF}
 import hdmicore.{PatternExample, TMDSDiff, DiffPair, HdmiTx}
@@ -87,6 +87,15 @@ class TangNano9k(vmode: VideoMode = VideoConsts.m1280x720) extends RawModule {
 }
 
 object TangNano9k extends App {
-  (new ChiselStage).execute(args,
-    Seq(ChiselGeneratorAnnotation(() => new TangNano9k())))
+  val verilog_src = ChiselStage
+    .emitSystemVerilog(
+        new TangNano9k,
+        firtoolOpts = Array(
+          "-disable-all-randomization",
+           "--lowering-options=disallowLocalVariables", // avoid 'automatic logic'
+           "-strip-debug-info"))
+  val fverilog = os.pwd / "TangNano9k.v"
+  if(os.exists(fverilog))
+    os.remove(fverilog)
+  os.write(fverilog, verilog_src)
 }
diff --git a/src/main/scala/platforms/ulx3s.scala b/src/main/scala/platforms/ulx3s.scala
@@ -4,8 +4,8 @@ package hdmicore.platforms
  */
 
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 
 import fpgamacro.gowin.{CLKDIV, TMDS_PLLVR, TLVDS_OBUF}
 import hdmicore.{PatternExample, TMDSDiff, DiffPair, HdmiTx}
@@ -86,6 +86,15 @@ class Ulx3s extends RawModule {
 }
 
 object Ulx3s extends App {
-  (new ChiselStage).execute(args,
-    Seq(ChiselGeneratorAnnotation(() => new Ulx3s())))
+  val verilog_src = ChiselStage
+    .emitSystemVerilog(
+        new Ulx3s,
+        firtoolOpts = Array(
+          "-disable-all-randomization",
+           "--lowering-options=disallowLocalVariables", // avoid 'automatic logic'
+           "-strip-debug-info"))
+  val fverilog = os.pwd / "Ulx3s.v"
+  if(os.exists(fverilog))
+    os.remove(fverilog)
+  os.write(fverilog, verilog_src)
 }
diff --git a/src/main/scala/video/hvsync.scala b/src/main/scala/video/hvsync.scala
@@ -5,8 +5,8 @@ package hdmicore.video
 * */
 
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 
 case class VideoParams(
   val H_DISPLAY: Int,// horizontal display width
@@ -87,6 +87,15 @@ class HVSync(val vp: VideoParams = VideoParams(
 }
 
 object HVSyncDriver extends App {
-  (new ChiselStage).execute(args,
-    Seq(ChiselGeneratorAnnotation(() => new HVSync())))
+  val verilog_src = ChiselStage
+    .emitSystemVerilog(
+        new HVSync,
+        firtoolOpts = Array(
+          "-disable-all-randomization",
+           "--lowering-options=disallowLocalVariables", // avoid 'automatic logic'
+           "-strip-debug-info"))
+  val fverilog = os.pwd / "HVSync.v"
+  if(os.exists(fverilog))
+    os.remove(fverilog)
+  os.write(fverilog, verilog_src)
 }