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fix parser
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@Bounti
Bounti committed Jul 2, 2024
1 parent b50fc68 commit d101206
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Showing 2 changed files with 32 additions and 47 deletions.
4 changes: 4 additions & 0 deletions libpresifuzz_feedbacks/src/csr_feedback.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -176,6 +176,10 @@ where

for trace_line in observer.trace() {

if trace_line.csr.is_none() {
continue;
}

let csr = trace_line.csr.unwrap();

// just a quick check to prune testcase achieving same csr states than previous one
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75 changes: 28 additions & 47 deletions libpresifuzz_observers/src/trace_observer.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -44,51 +44,27 @@ pub struct CSRLog {
pub medeleg: u32,
pub mcounteren: u32,
pub scounteren: u32,
pub dcsr: u32,
}

// Implement PartialEq for CSRLog
impl PartialEq for CSRLog {
fn eq(&self, other: &Self) -> bool {
//self.mstatus_xIE == other.mstatus_xIE &&
//self.mstatus_xPIE == other.mstatus_xPIE &&
//self.mstatus_xPP == other.mstatus_xPP &&
//self.mstatus_XS == other.mstatus_XS &&
//self.mstatus_FS == other.mstatus_FS &&
//self.mstatus_MPRV == other.mstatus_MPRV &&
//self.mstatus_SUM == other.mstatus_SUM &&
//self.mstatus_MXR == other.mstatus_MXR &&
//self.mstatus_TVM == other.mstatus_TVM &&
//self.mstatus_TW == other.mstatus_TW &&
//self.mstatus_TSR == other.mstatus_TSR &&
//self.mstatus_xXL == other.mstatus_xXL &&
//self.mstatus_SD == other.mstatus_SD &&
self.mstatus == other.mstatus &&
self.frm == other.frm &&
self.fflags == other.fflags &&
self.mcause == other.mcause &&
self.scause == other.scause &&
self.medeleg == other.medeleg &&
self.mcounteren == other.mcounteren &&
self.scounteren == other.scounteren
self.scounteren == other.scounteren &&
self.dcsr == other.dcsr
}
}

impl CSRLog {
pub fn from_array(values: [u32; 8]) -> Self {
pub fn from_array(values: [u32; 9]) -> Self {
CSRLog {
//mstatus_xIE: values[0],
//mstatus_xPIE: values[1],
//mstatus_xPP: values[2],
//mstatus_XS: values[3],
//mstatus_FS: values[4],
//mstatus_MPRV: values[5],
//mstatus_SUM: values[6],
//mstatus_MXR: values[7],
//mstatus_TVM: values[8],
//mstatus_TW: values[9],
//mstatus_TSR: values[10],
//mstatus_xXL: values[11],
//mstatus_SD: values[12],
mstatus: values[0],
frm: values[1],
fflags: values[2],
Expand All @@ -97,6 +73,7 @@ impl CSRLog {
medeleg: values[5],
mcounteren: values[6],
scounteren: values[7],
dcsr: values[8],
}
}
}
Expand Down Expand Up @@ -385,39 +362,43 @@ impl ExecTraceParser for ProcessorFuzzExecTraceObserver
let file = File::open(spike_file).expect("Unable to open spike trace file");
let reader = io::BufReader::new(file);

let spike_store_commit_re = Regex::new(r"core\s+\d+: \d+ 0x(\w+) \(0x(\w+)\)\s+mem\s+0x(\w+)\s+0x(\w+) [0x(\w+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+)]").unwrap();
let spike_rest_commit_re = Regex::new(r"core\s+\d+: \d+ 0x(\w+) \(0x(\w+)\)\s+(\w+)\s+0x(\w+)(\s+(\w+)\s+0x(\w+))? [0x(\w+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+)]").unwrap();
let spike_store_commit_re = Regex::new(r"core\s+\d+: \d+ 0x(\w+) \(0x(\w+)\)\s+mem\s+0x(\w+)\s+0x(\w+)").unwrap();
let spike_rest_commit_re = Regex::new(r"core\s+\d+: \d+ 0x(\w+) \(0x(\w+)\)\s+(\w+)\s+0x(\w+)(\s+(\w+)\s+0x(\w+))?").unwrap();
for line in reader.lines() {

let mut csr_values = [0u32; 8];

if let Ok(log_line) = &line {

println!("{}",log_line);
let re = Regex::new(r"\[(.*?)\]").unwrap();
let csr = if let Some(caps) = re.captures(log_line) {
let bracket_content = &caps[1];

let mut numbers = [0u32; 9];
let parsed_numbers: Vec<u32> = bracket_content
.split(',')
.filter_map(|s| u32::from_str_radix(s.trim_start_matches("0x"), 16).ok())
.collect();

if parsed_numbers.len() == 9 {
numbers.copy_from_slice(&parsed_numbers);
} else {
println!("{:?}", parsed_numbers);
panic!("Error: Processorfuzz log format not enforced by Spike");
}

Some(CSRLog::from_array(numbers))
} else {None};

if let Some(caps) = spike_store_commit_re.captures(log_line) {

for (i, cap) in caps.iter().skip(3).enumerate() {
if let Some(cap) = cap {
csr_values[i] = cap.as_str().parse().unwrap();
}
}
let ops = vec![
OpLog::MemOp(MemOp{op_type: OpType::Write, address: u64::from_str_radix(&caps[3], 16).unwrap(), value: u64::from_str_radix(&caps[4], 16).unwrap()})
];
trace.push(TraceLog {
pc: u64::from_str_radix(&caps[1], 16).unwrap(),
inst: u64::from_str_radix(&caps[2], 16).unwrap(),
ops,
csr: Some(CSRLog::from_array(csr_values))
csr: None
});
}
else if let Some(caps) = spike_rest_commit_re.captures(log_line) {
for (i, cap) in caps.iter().skip(3).enumerate() {
if let Some(cap) = cap {
csr_values[i] = cap.as_str().parse().unwrap();
}
}
let mut ops = vec![
OpLog::RegOp(RegOp{op_type: OpType::Read, name: caps[3].to_string(), value: u64::from_str_radix(&caps[4], 16).unwrap()})
];
Expand All @@ -432,7 +413,7 @@ impl ExecTraceParser for ProcessorFuzzExecTraceObserver
pc: u64::from_str_radix(&caps[1], 16).unwrap(),
inst: u64::from_str_radix(&caps[2], 16).unwrap(),
ops,
csr: Some(CSRLog::from_array(csr_values))
csr: None
});
}
}
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