[AMD] Fix redundant data masking computations for stores

[binarman]

Goal

Rework redundant data masking in store operations with help of linear layout.
Masking mechanism should be able to handle any tensor shapes.

DoD

test_convert_mma2mma tests introduced for AMD hardware in #5495 are fully functional for AMD hardware, i.e. no tests are skipped: https://github.com/triton-lang/triton/pull/5495/files#diff-ac90f00a03feff6747a9c9ac5af1f44bb67e56bf911e05db71a2c1e818e897e7R5730

Hints

See PR #5225 for Nvidia specific implementation.

Since test does not require any actual tensor/matrix cores, older hardware could be used.

For example, radeon 6xxx could be used to run WMMA tests, need to:

• hack

  triton/python/test/unit/language/test_core.py

  Line 223 in 11ef427

  if "gfx11" in target_arch:

  to if "gfx1" in target_arch:
• change smallest size https://github.com/triton-lang/triton/pull/5495/files#diff-ac90f00a03feff6747a9c9ac5af1f44bb67e56bf911e05db71a2c1e818e897e7R5726 from [16, 16] to [8, 8]
• remove this assert:

  triton/lib/Dialect/TritonGPU/IR/LinearLayoutConversions.cpp

  Line 494 in 11ef427

  assert(((shape[mIndex] == 1 || shape[mIndex] >= mDim) &&

[binarman]

@simonidaa work on this task next, please.

Before you make a PR, please wait for #5495 to land

[rajveer43]

would like to work on this

[simonidaa]

already on it