From ffd9b9d988f99331289c0a78a452e65c3c31e48e Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Wed, 26 Feb 2020 16:32:16 -0800 Subject: [PATCH] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index ab98a5a..aadaf6f 100644 --- a/README.md +++ b/README.md @@ -16,7 +16,7 @@ Download a binary from the [Releases](https://github.com/sgherbst/svinst/release ## Purpose -The Verilog language has contained features for defining configs and libraries for close to 20 years. However, these features are not well-supported by open-source tools, and even some commercial synthesis tools. By extracting a list of modules defined and instantiated in a file, a user can work around this problem by constructing their own design hierarchy outside of Verilog, and then passing that list of files back into the simulator / synthesis tool. +The Verilog language has contains features for defining configs and libraries. However, these features are not well-supported by open-source tools, and even some commercial synthesis tools. By extracting a list of modules defined and instantiated in a file, a user can work around this problem by constructing their own design hierarchy outside of Verilog, and then passing that list of files back into the simulator / synthesis tool. ## Usage