[BUG] Incorrect stval value after illegal instruction exception while mstatus.TVM flag is activated in HS-mode

[riscv914]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

In HS-mode, when mstatus.TVM flag is activated executing the HFENCE.GVMA instruction should trigger an illegal instruction exception. While this behavior is correct on CVA6 cores, after the trap is triggered, the stval register value should be set to the instruction value.

"The stval register can optionally also be used to return the faulting instruction bits on an illegal instruction exception (sepc points to the faulting instruction in memory). If stval is written with a nonzero value when an illegal-instruction exception occurs, then stval will contain the shortest of:
the actual faulting instruction
the first ILEN bits of the faulting instruction
the first SXLEN bits of the faulting instruction"

However, in the case of the HFENCE.GVMA instruction, the CVA6 core erroneously sets stval to 0x1 instead of the instruction value.

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Code for Reproducing the Bug:

int main() {
    asm volatile ("li t0, (1 << 20)"); 
    asm volatile ("csrs mstatus, t0"); // set TVM
    /// Switch to HS-mode
    asm volatile ("hfence.gvma zero, zero");
}

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Expected Behavior:

When the HFENCE.GVMA instruction causes the trap, the stval register should hold the value of the HFENCE.GVMA instruction.

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Observed Behavior:

The stval register is incorrectly set to 0x1 instead of the correct value of the HFENCE.GVMA instruction 0x62000073.

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CVA6 commit: 2155d0e
Build config : cv64a6_imafdch_sv39_wb