From 86c53c53345e17630e10e872058ffe650148a275 Mon Sep 17 00:00:00 2001
From: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Date: Thu, 16 Jan 2025 03:47:07 +1100
Subject: [PATCH 1/7] config_pkg: Update configurations with new flush
 parameter (#2704)

#2691 extended the cva6_user_cfg_t struct by two new parameters to control the cache's flush behaviour. Add these new parameters to all configs to fix compilation errors due to incomplete struct literals.
---
 core/include/cv32a6_embedded_config_pkg_deprecated.sv   | 5 +++++
 core/include/cv32a6_ima_sv32_fpga_config_pkg.sv         | 2 ++
 core/include/cv32a6_imac_sv0_config_pkg.sv              | 2 ++
 core/include/cv32a6_imafc_sv32_config_pkg.sv            | 4 +++-
 core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv   | 5 +++++
 core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 5 +++++
 core/include/cv64a6_imafdch_sv39_config_pkg.sv          | 5 +++++
 core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv       | 5 +++++
 core/include/cv64a6_imafdcv_sv39_config_pkg.sv          | 5 +++++
 core/include/cv64a6_mmu_config_pkg.sv                   | 2 ++
 10 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
index ce5e635107..bfff31d25f 100644
--- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv
+++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
@@ -42,6 +42,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -139,6 +142,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
index f459765708..7c680172fc 100644
--- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
+++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
@@ -140,6 +140,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: bit'(0),
+      DcacheInvalidateOnFlush: bit'(0),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv
index 6ab85d509d..0cc82debb8 100644
--- a/core/include/cv32a6_imac_sv0_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv0_config_pkg.sv
@@ -140,6 +140,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: bit'(0),
+      DcacheInvalidateOnFlush: bit'(0),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv
index 2575d7ac3b..3801eda239 100644
--- a/core/include/cv32a6_imafc_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv
@@ -136,10 +136,12 @@ package cva6_config_pkg;
       IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
       IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
       IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
+      DCacheType: CVA6ConfigDcacheType,
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
-      DCacheType: CVA6ConfigDcacheType,
+      DcacheFlushOnFence: bit'(0),
+      DcacheInvalidateOnFlush: bit'(0),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
index 2622377d8f..8cb0f17bad 100644
--- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
+++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
@@ -43,6 +43,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -140,6 +143,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
index 5b785232c0..82be807aab 100644
--- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
@@ -43,6 +43,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -140,6 +143,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
index dcdb20691e..87500e7124 100644
--- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
@@ -43,6 +43,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -140,6 +143,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
index 8603bb1926..09de6d9993 100644
--- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
@@ -43,6 +43,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 8;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b1;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -140,6 +143,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
index e2a9add4a6..5b0917fed2 100644
--- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
@@ -43,6 +43,9 @@ package cva6_config_pkg;
   localparam CVA6ConfigDcacheSetAssoc = 4;
   localparam CVA6ConfigDcacheLineWidth = 128;
 
+  localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
+  localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
+
   localparam CVA6ConfigDcacheIdWidth = 1;
   localparam CVA6ConfigMemTidWidth = 2;
 
@@ -139,6 +142,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
       DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
+      DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence),
+      DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv
index 50e4131d4f..603593c11f 100644
--- a/core/include/cv64a6_mmu_config_pkg.sv
+++ b/core/include/cv64a6_mmu_config_pkg.sv
@@ -95,6 +95,8 @@ package cva6_config_pkg;
       DcacheByteSize: unsigned'(32768),
       DcacheSetAssoc: unsigned'(8),
       DcacheLineWidth: unsigned'(128),
+      DcacheFlushOnFence: bit'(0),
+      DcacheInvalidateOnFlush: bit'(0),
       DataUserEn: unsigned'(0),
       WtDcacheWbufDepth: int'(2),
       FetchUserWidth: unsigned'(64),

From 21b247dca7f35a7897af28456cb3df37aaa4d87e Mon Sep 17 00:00:00 2001
From: Guillaume Chauvon <94678394+Gchauvon@users.noreply.github.com>
Date: Wed, 15 Jan 2025 17:48:01 +0100
Subject: [PATCH 2/7] CI: copy seeds in artifacts for generated tests (#2708)

Save seeds in artifacts for generated tests. It will help to reproduce the test in case of failure.
---
 .gitlab-ci.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index c3f0a6a391..cc62fda9cd 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -170,6 +170,7 @@ smoke-gen:
     SPIKE_TANDEM: 1
   script:
     - bash verif/regress/smoke-gen_tests.sh
+    - cp verif/sim/seedlist.yaml artifacts/logs/
     - !reference [.simu_after_script]
 
 smoke-bench:

From 5518a41c08a1949c606d54b9ac631e8f7635e7f3 Mon Sep 17 00:00:00 2001
From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com>
Date: Wed, 15 Jan 2025 19:57:00 +0100
Subject: [PATCH 3/7] Bump verif/core-v-verif from `464bf7a` to `19b5a3f`
 (#2703)

---
 verif/core-v-verif | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/verif/core-v-verif b/verif/core-v-verif
index 464bf7a0d7..19b5a3f94d 160000
--- a/verif/core-v-verif
+++ b/verif/core-v-verif
@@ -1 +1 @@
-Subproject commit 464bf7a0d730eaf614acac258b412829217b6465
+Subproject commit 19b5a3f94d9b091701f020146072dd214b93d34d

From 41c22069a04ac4884bf3be9f528f8da90d8f2be4 Mon Sep 17 00:00:00 2001
From: Guillaume Chauvon <94678394+Gchauvon@users.noreply.github.com>
Date: Thu, 16 Jan 2025 23:09:57 +0100
Subject: [PATCH 4/7] Add parameter to disable software interrupt. Fix issue
 #2500 (#2711)

Fix issue #2500
Add parameter to disable software interrupt.
MIP.MSIP and MIE.MSIE are now read only when this parameter is disabled.
---
 core/csr_regfile.sv                                 | 13 +++++++++----
 core/include/build_config_pkg.sv                    |  1 +
 core/include/config_pkg.sv                          | 13 ++++++++++---
 core/include/cv32a60x_config_pkg.sv                 |  1 +
 core/include/cv32a65x_config_pkg.sv                 |  1 +
 .../cv32a6_embedded_config_pkg_deprecated.sv        |  1 +
 core/include/cv32a6_ima_sv32_fpga_config_pkg.sv     |  1 +
 core/include/cv32a6_imac_sv0_config_pkg.sv          |  1 +
 core/include/cv32a6_imac_sv32_config_pkg.sv         |  1 +
 core/include/cv32a6_imafc_sv32_config_pkg.sv        |  1 +
 .../cv64a6_imadfcv_sv39_polara_config_pkg.sv        |  1 +
 core/include/cv64a6_imafdc_sv39_config_pkg.sv       |  1 +
 .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv       |  1 +
 .../cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv    |  1 +
 .../cv64a6_imafdc_sv39_openpiton_config_pkg.sv      |  1 +
 core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv    |  1 +
 core/include/cv64a6_imafdch_sv39_config_pkg.sv      |  1 +
 core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv   |  1 +
 core/include/cv64a6_imafdcv_sv39_config_pkg.sv      |  1 +
 core/include/cv64a6_mmu_config_pkg.sv               |  1 +
 verif/env/uvme/uvme_cva6_cfg.sv                     |  3 +--
 21 files changed, 38 insertions(+), 9 deletions(-)

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index d6e965f2f6..724dfed904 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -1435,9 +1435,14 @@ module csr_regfile
                       | CVA6Cfg.XLEN'(riscv::MIP_MTIP)
                       | CVA6Cfg.XLEN'(riscv::MIP_MEIP);
             end else begin
-              mask = CVA6Cfg.XLEN'(riscv::MIP_MSIP)
-                      | CVA6Cfg.XLEN'(riscv::MIP_MTIP)
-                      | CVA6Cfg.XLEN'(riscv::MIP_MEIP);
+              if (CVA6Cfg.SoftwareInterruptEn) begin
+                mask = CVA6Cfg.XLEN'(riscv::MIP_MSIP)  // same shift as MSIE
+                | CVA6Cfg.XLEN'(riscv::MIP_MTIP)  // same shift as MTIE
+                | CVA6Cfg.XLEN'(riscv::MIP_MEIP);  // same shift as MEIE
+              end else begin
+                mask = CVA6Cfg.XLEN'(riscv::MIP_MTIP)  // same shift as MTIE
+                | CVA6Cfg.XLEN'(riscv::MIP_MEIP);  // same shift as MEIE
+              end
             end
           end
           mie_d = (mie_q & ~mask) | (csr_wdata & mask); // we only support supervisor and M-mode interrupts
@@ -1771,7 +1776,7 @@ module csr_regfile
     // Machine Mode External Interrupt Pending
     mip_d[riscv::IRQ_M_EXT] = irq_i[0];
     // Machine software interrupt
-    mip_d[riscv::IRQ_M_SOFT] = ipi_i;
+    mip_d[riscv::IRQ_M_SOFT] = CVA6Cfg.SoftwareInterruptEn && ipi_i;
     // Timer interrupt pending, coming from platform timer
     mip_d[riscv::IRQ_M_TIMER] = time_irq_i;
 
diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv
index 232272d0c3..332a094356 100644
--- a/core/include/build_config_pkg.sv
+++ b/core/include/build_config_pkg.sv
@@ -95,6 +95,7 @@ package build_config_pkg;
     cfg.MmuPresent = CVA6Cfg.MmuPresent;
     cfg.RVS = CVA6Cfg.RVS;
     cfg.RVU = CVA6Cfg.RVU;
+    cfg.SoftwareInterruptEn = CVA6Cfg.SoftwareInterruptEn;
 
     cfg.HaltAddress = CVA6Cfg.HaltAddress;
     cfg.ExceptionAddress = CVA6Cfg.ExceptionAddress;
diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv
index c129c994c9..fbe25a6406 100644
--- a/core/include/config_pkg.sv
+++ b/core/include/config_pkg.sv
@@ -94,6 +94,8 @@ package config_pkg;
     bit                          RVS;
     // User mode
     bit                          RVU;
+    // Software interrupts are enabled
+    bit                          SoftwareInterruptEn;
     // Debug support
     bit                          DebugEn;
     // Base address of the debug module
@@ -277,8 +279,9 @@ package config_pkg;
     bit          EnableAccelerator;
     bit          PerfCounterEn;
     bit          MmuPresent;
-    bit          RVS;                //Supervisor mode
-    bit          RVU;                //User mode
+    bit          RVS;                  //Supervisor mode
+    bit          RVU;                  //User mode
+    bit          SoftwareInterruptEn;
 
     logic [63:0] HaltAddress;
     logic [63:0] ExceptionAddress;
@@ -388,7 +391,11 @@ package config_pkg;
     assert (!(Cfg.SuperscalarEn && Cfg.RVF));
     assert (!(Cfg.SuperscalarEn && Cfg.RVZCMP));
     assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64)
-    else $fatal(1, "[frontend] fetch width != not supported");
+      // Support for disabling MIP.MSIP and MIE.MSIE in Hypervisor and Supervisor mode is not supported
+      // Software Interrupt can be disabled when there is only M machine mode in CVA6.
+      assert (!(Cfg.RVS && !Cfg.SoftwareInterruptEn))
+        assert (!(Cfg.RVH && !Cfg.SoftwareInterruptEn))
+        else $fatal(1, "[frontend] fetch width != not supported");
     // pragma translate_on
   endfunction
 
diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv
index 55cd5e57f0..0337a8151b 100644
--- a/core/include/cv32a60x_config_pkg.sv
+++ b/core/include/cv32a60x_config_pkg.sv
@@ -55,6 +55,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(0),
       RVS: bit'(0),
       RVU: bit'(0),
+      SoftwareInterruptEn: bit'(0),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(2),
diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv
index bb0109f8c2..d64670aab2 100644
--- a/core/include/cv32a65x_config_pkg.sv
+++ b/core/include/cv32a65x_config_pkg.sv
@@ -55,6 +55,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(0),
       RVS: bit'(0),
       RVU: bit'(0),
+      SoftwareInterruptEn: bit'(0),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(2),
diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
index bfff31d25f..bcf2234819 100644
--- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv
+++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
@@ -109,6 +109,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(0),
       RVU: bit'(0),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
index 7c680172fc..199403c398 100644
--- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
+++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
@@ -107,6 +107,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv
index 0cc82debb8..72ca224f4e 100644
--- a/core/include/cv32a6_imac_sv0_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv0_config_pkg.sv
@@ -107,6 +107,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv
index 2e8d236fb5..7bf6f5dc27 100644
--- a/core/include/cv32a6_imac_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv32_config_pkg.sv
@@ -106,6 +106,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv
index 3801eda239..0b6964ea7f 100644
--- a/core/include/cv32a6_imafc_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv
@@ -107,6 +107,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
index 8cb0f17bad..1af56f698d 100644
--- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
+++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
index c8ea11d9e2..d76b757c94 100644
--- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
index d7d37a1486..df092b7370 100644
--- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
@@ -117,6 +117,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv
index 5e2773053c..88fa3f2af8 100644
--- a/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv
@@ -117,6 +117,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
index 82be807aab..3f22ee98a4 100644
--- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
index fb0e9e60ec..fbcef4e597 100644
--- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
index 87500e7124..e5551ff5c4 100644
--- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
index 09de6d9993..909987eaab 100644
--- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
index 5b0917fed2..85d25125c3 100644
--- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
@@ -110,6 +110,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv
index 603593c11f..7d7df43de4 100644
--- a/core/include/cv64a6_mmu_config_pkg.sv
+++ b/core/include/cv64a6_mmu_config_pkg.sv
@@ -62,6 +62,7 @@ package cva6_config_pkg;
       MmuPresent: bit'(1),
       RVS: bit'(1),
       RVU: bit'(1),
+      SoftwareInterruptEn: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(2),
diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv
index 946c63b4b3..1f597e49c8 100644
--- a/verif/env/uvme/uvme_cva6_cfg.sv
+++ b/verif/env/uvme/uvme_cva6_cfg.sv
@@ -131,8 +131,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
       HPDCache_supported      == (RTLCVA6Cfg.DCacheType == 2);
 
       MmuPresent              == RTLCVA6Cfg.MmuPresent;
-      // TODO : add RTL paramater related to this field fix issue#2500
-      sw_int_supported        == 0;
+      sw_int_supported        == RTLCVA6Cfg.SoftwareInterruptEn;
    }
 
    constraint ext_const {

From 7af0f2e4d1e7bd9d58ae6152d97e58469553bc6b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?C=C3=B4me?= <124148386+cathales@users.noreply.github.com>
Date: Thu, 16 Jan 2025 23:12:33 +0100
Subject: [PATCH 5/7] ariane_pkg: remove unused localparam ISSUE_WIDTH (#2710)

This localparam is not needed anymore.
---
 core/include/ariane_pkg.sv | 2 --
 1 file changed, 2 deletions(-)

diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv
index 9e2e0aa80c..254721b200 100644
--- a/core/include/ariane_pkg.sv
+++ b/core/include/ariane_pkg.sv
@@ -31,8 +31,6 @@ package ariane_pkg;
   // TODO: Slowly move those parameters to the new system.
   localparam BITS_SATURATION_COUNTER = 2;
 
-  localparam ISSUE_WIDTH = 1;
-
   // depth of store-buffers, this needs to be a power of two
   localparam logic [2:0] DEPTH_SPEC = 'd4;
 

From e840a61e80e5f6ead475128ff3adb74ad7fd051a Mon Sep 17 00:00:00 2001
From: OlivierBetschi <140494506+OlivierBetschi@users.noreply.github.com>
Date: Fri, 17 Jan 2025 12:39:05 +0100
Subject: [PATCH 6/7] Rewrite assert to avoid multi assertion (#2713)

This should fix github CI failing with verilator due to the assert combination
---
 core/include/config_pkg.sv | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv
index fbe25a6406..002e45f785 100644
--- a/core/include/config_pkg.sv
+++ b/core/include/config_pkg.sv
@@ -391,11 +391,11 @@ package config_pkg;
     assert (!(Cfg.SuperscalarEn && Cfg.RVF));
     assert (!(Cfg.SuperscalarEn && Cfg.RVZCMP));
     assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64)
-      // Support for disabling MIP.MSIP and MIE.MSIE in Hypervisor and Supervisor mode is not supported
-      // Software Interrupt can be disabled when there is only M machine mode in CVA6.
-      assert (!(Cfg.RVS && !Cfg.SoftwareInterruptEn))
-        assert (!(Cfg.RVH && !Cfg.SoftwareInterruptEn))
-        else $fatal(1, "[frontend] fetch width != not supported");
+    else $fatal(1, "[frontend] fetch width != not supported");
+    // Support for disabling MIP.MSIP and MIE.MSIE in Hypervisor and Supervisor mode is not supported
+    // Software Interrupt can be disabled when there is only M machine mode in CVA6.
+    assert (!(Cfg.RVS && !Cfg.SoftwareInterruptEn));
+    assert (!(Cfg.RVH && !Cfg.SoftwareInterruptEn));
     // pragma translate_on
   endfunction
 

From 3d2ff00b1c958bbccab9189a00cbebeda84e067b Mon Sep 17 00:00:00 2001
From: Guillaume Chauvon <94678394+Gchauvon@users.noreply.github.com>
Date: Fri, 17 Jan 2025 14:12:08 +0100
Subject: [PATCH 7/7] Modify MSUB, NMADD, NMSUB behaviour to differs from other
 instructions. (#2712)

MSUB = rs1 - rs2 - rs3
NMADD = ~(rs1 + rs2 + rs3)
NMSUB = ~(rs1 - rs2 - rs3)
---
 core/cvxif_example/copro_alu.sv               | 28 +++++++++++++++++--
 core/cvxif_example/include/cvxif_instr_pkg.sv | 15 ++++++----
 .../custom_instructions_cvxif_1_0_0.rst       | 12 ++++----
 verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv  | 12 ++++----
 4 files changed, 47 insertions(+), 20 deletions(-)

diff --git a/core/cvxif_example/copro_alu.sv b/core/cvxif_example/copro_alu.sv
index 672528454d..4e980ffea4 100644
--- a/core/cvxif_example/copro_alu.sv
+++ b/core/cvxif_example/copro_alu.sv
@@ -88,8 +88,32 @@ module copro_alu
         rd_n     = rd_i;
         we_n     = 1'b1;
       end
-      cvxif_instr_pkg::ADD_RS3_R4: begin
-        result_n = NrRgprPorts == 3 ? registers_i[2] + registers_i[1] + registers_i[0] : registers_i[1] + registers_i[0];
+      cvxif_instr_pkg::MADD_RS3_R4: begin
+        result_n = NrRgprPorts == 3 ? (registers_i[0] + registers_i[1] + registers_i[2]) : (registers_i[0] + registers_i[1]);
+        hartid_n = hartid_i;
+        id_n = id_i;
+        valid_n = 1'b1;
+        rd_n = rd_i;
+        we_n = 1'b1;
+      end
+      cvxif_instr_pkg::MSUB_RS3_R4: begin
+        result_n = NrRgprPorts == 3 ? (registers_i[0] - registers_i[1] - registers_i[2]) : (registers_i[0] - registers_i[1]);
+        hartid_n = hartid_i;
+        id_n = id_i;
+        valid_n = 1'b1;
+        rd_n = rd_i;
+        we_n = 1'b1;
+      end
+      cvxif_instr_pkg::NMADD_RS3_R4: begin
+        result_n = NrRgprPorts == 3 ? ~(registers_i[0] + registers_i[1] + registers_i[2]) : ~(registers_i[0] + registers_i[1]);
+        hartid_n = hartid_i;
+        id_n = id_i;
+        valid_n = 1'b1;
+        rd_n = rd_i;
+        we_n = 1'b1;
+      end
+      cvxif_instr_pkg::NMSUB_RS3_R4: begin
+        result_n = NrRgprPorts == 3 ? ~(registers_i[0] - registers_i[1] - registers_i[2]) : ~(registers_i[0] - registers_i[1]);
         hartid_n = hartid_i;
         id_n = id_i;
         valid_n = 1'b1;
diff --git a/core/cvxif_example/include/cvxif_instr_pkg.sv b/core/cvxif_example/include/cvxif_instr_pkg.sv
index 2c0c8a34bd..496cddba8f 100644
--- a/core/cvxif_example/include/cvxif_instr_pkg.sv
+++ b/core/cvxif_example/include/cvxif_instr_pkg.sv
@@ -18,8 +18,11 @@ package cvxif_instr_pkg;
     DOUBLE_RS1 = 4'b0011,
     DOUBLE_RS2 = 4'b0100,
     ADD_MULTI = 4'b0101,
-    ADD_RS3_R4 = 4'b0110,
-    ADD_RS3_R = 4'b0111
+    MADD_RS3_R4 = 4'b0110,
+    MSUB_RS3_R4 = 4'b0111,
+    NMADD_RS3_R4 = 4'b1000,
+    NMSUB_RS3_R4 = 4'b1001,
+    ADD_RS3_R = 4'b1111
   } opcode_t;
 
 
@@ -105,7 +108,7 @@ package cvxif_instr_pkg;
           32'b00000_00_00000_00000_0_00_00000_1000011,  // MADD opcode
           mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
           resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
-          opcode : ADD_RS3_R4
+          opcode : MADD_RS3_R4
       },
       '{
           // Custom Add Multi rs1 : cus_add rd, rs1, rs1
@@ -113,7 +116,7 @@ package cvxif_instr_pkg;
           32'b00000_00_00000_00000_0_00_00000_1000111,  // MSUB opcode
           mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
           resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
-          opcode : ADD_RS3_R4
+          opcode : MSUB_RS3_R4
       },
       '{
           // Custom Add Multi rs1 : cus_add rd, rs1, rs1
@@ -121,7 +124,7 @@ package cvxif_instr_pkg;
           32'b00000_00_00000_00000_0_00_00000_1001011,  // NMSUB opcode
           mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
           resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
-          opcode : ADD_RS3_R4
+          opcode : NMSUB_RS3_R4
       },
       '{
           // Custom Add Multi rs1 : cus_add rd, rs1, rs1
@@ -129,7 +132,7 @@ package cvxif_instr_pkg;
           32'b00000_00_00000_00000_0_00_00000_1001111,  // NMADD opcode
           mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
           resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
-          opcode : ADD_RS3_R4
+          opcode : NMADD_RS3_R4
       }
   };
 
diff --git a/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst b/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst
index ee53871c86..406dd50142 100644
--- a/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst
+++ b/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst
@@ -70,25 +70,25 @@ Except for 4 of them using opcode `MADD, MSUB, NMADD, NMSUB`
 
     **Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_0111|
 
-    **Description**: add register rs1, rs2 to rs3, and store the result in rd.
+    **Description**: subtract register rs2 and rs3 from rs1 and store the result in rd.
 
-    **Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
+    **Pseudocode**: x[rd] = x[rs1] - x[rs2] - x[rs3]
 
 - **CUS_ADD_RS3_NMADD**: Custom Add with RS3 opcode == NMADD
 
     **Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_1111|
 
-    **Description**: add register rs1, rs2 to rs3, and store the result in rd.
+    **Description**: add register rs1, rs2 to rs3, negate the sum, and store the result in rd.
 
-    **Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
+    **Pseudocode**: x[rd] = ¬(x[rs1] + x[rs2] + x[rs3])
 
 - **CUS_ADD_RS3_NMSUB**: Custom Add with RS3 opcode == NMSUB
 
     **Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_1011|
 
-    **Description**: add register rs1, rs2 to rs3, and store the result in rd.
+    **Description**: subtract register rs2 and rs3 from rs1, negate the difference, and store the result in rd.
 
-    **Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
+    **Pseudocode**: x[rd] = ¬(x[rs1] - x[rs2] - x[rs3])
 
 - **CUS_ADD_RS3_RTYPE**: Custom Add with RS3, rd is x10 (a0)
 
diff --git a/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv b/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv
index 9a9e460aee..de4da8a1d2 100644
--- a/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv
+++ b/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv
@@ -378,31 +378,31 @@ task uvme_cvxif_vseq_c::do_instr_result();
       end
       "CUS_ADD_RS3_MSUB": begin
          if (req_item.register.rs_valid == 3'b111) begin
-            resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2];
+            resp_item.result.data = req_item.register.rs[0] - req_item.register.rs[1] - req_item.register.rs[2];
             resp_item.result.rd   = req_item.issue_req.instr[11:7];
          end
          else if (req_item.register.rs_valid == 2'b11) begin
-            resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1];
+            resp_item.result.data = req_item.register.rs[0] - req_item.register.rs[1];
             resp_item.result.rd   = req_item.issue_req.instr[11:7];
          end
       end
       "CUS_ADD_RS3_NMADD": begin
          if (req_item.register.rs_valid == 3'b111) begin
-            resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2];
+            resp_item.result.data = ~(req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2]);
             resp_item.result.rd   = req_item.issue_req.instr[11:7];
          end
          else if (req_item.register.rs_valid == 2'b11) begin
-            resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1];
+            resp_item.result.data = ~(req_item.register.rs[0] + req_item.register.rs[1]);
             resp_item.result.rd   = req_item.issue_req.instr[11:7];
          end
       end
       "CUS_ADD_RS3_NMSUB": begin
          if (req_item.register.rs_valid == 3'b111) begin
-            resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2];
+            resp_item.result.data = ~(req_item.register.rs[0] - req_item.register.rs[1] - req_item.register.rs[2]);
             resp_item.result.rd   = req_item.issue_req.instr[11:7];
          end
          else if (req_item.register.rs_valid == 2'b11) begin
-            resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1];
+            resp_item.result.data = ~(req_item.register.rs[0] - req_item.register.rs[1]);
             resp_item.result.rd   = req_item.issue_req.instr[11:7];
          end
       end