diff --git a/.circleci/README.md b/.circleci/README.md deleted file mode 100644 index 0c53405..0000000 --- a/.circleci/README.md +++ /dev/null @@ -1,75 +0,0 @@ -Chipyard CI -=========== - -Website: https://circleci.com/gh/ucb-bar/chipyard - -CircleCI Brief Explanation ---------------------------- - -CircleCI is controlled by the `config.yml` script. -It consists of a *workflow* which has a series of *jobs* within it that do particular tasks. -All jobs in the workflow must pass for the CI run to be successful. - -At the bottom of the `config.yml` there is a `workflows:` section that specifies the order in which the jobs of the workflow should run. -For example: - - - prepare-rocketchip: - requires: - - install-riscv-toolchain - -This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` steps to run before it can run. - -All jobs in the CI workflow are specified at the top of `config.yml` -They specify a docker image to use (in this case a riscv-boom image since that is already available and works nicely) and an environment. -Finally, in the `steps:` section, the steps are run sequentially and state persists throughout a job. -So when you run something like `checkout` the next step has the checked out code. -Caching in the job is done by giving a file to cache on. -`restore_cache:` loads the cache into the environment if the key matches while `save_cache:` writes to the cache with the key IF IT IS NOT PRESENT. -Note, if the cache is already present for that key, the write to it is ignored. -Here the key is built from a string where the `checksum` portion converts the file given into a hash. - -.circleci directory -------------------- - -This directory contains all the collateral for the Chipyard CI to work. -The following is included: - - `build-toolchains.sh` # build either riscv-tools or esp-tools - `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work - `do-rtl-build.sh` # use verilator to build a sim executable (remotely) - `config.yml` # main circleci config script to enumerate jobs/workflows - `defaults.sh` # default variables used - `check-commit.sh` # check that submodule commits are valid - `build-extra-tests.sh` # build default chipyard tests located in tests/ - `clean-old-files.sh` # clean up build server files - `do-fpga-rtl-build.sh` # similar to `do-rtl-build` but using fpga/ - `install-verilator.sh` # install verilator on build server - `run-firesim-scala-tests.sh` # run firesim scala tests - `run-tests.sh # run tests for a specific set of designs - `images/` # docker image used in CI - -How things are setup for Chipyard ---------------------------------- - -The steps for CI to run are as follows. -1st, build the toolchains in parallel (note: `esp-tools` is currently not used in the run). -The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` is the default (currently the `env.sh` script that is created at tool build is unused). -2nd, create the simulator binary. -This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary. -This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again). -3rd, finally run the desired tests. - -Other CI Setup --------------- - -To get the CI to work correctly you need to setup CircleCI environment variables to point to the remote directory to build files and the server user/ip. -In the project settings, you can find this under "Build Settings" "Environment Variables". -You need to add two variables like the following: - -CI\_DIR = /path/to/where/you/want/to/store/remote/files -SERVER = username@myserver.coolmachine.berkeley.edu - -Additionally, you need to add under the "PERMISSIONS" "SSH Permissions" section a private key that is on the build server that you are using. -After adding a private key, it will show a fingerprint that should be added under the jobs that need to be run. - -Note: On the remote server you need to have the `*.pub` key file added to the `authorized_keys` file. diff --git a/.circleci/build-extra-tests.sh b/.circleci/build-extra-tests.sh deleted file mode 100755 index e38b50f..0000000 --- a/.circleci/build-extra-tests.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -make -C $LOCAL_CHIPYARD_DIR/tests clean -make -C $LOCAL_CHIPYARD_DIR/tests diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh deleted file mode 100755 index 160b6f5..0000000 --- a/.circleci/build-toolchains.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/bash - -# create the riscv tools/esp tools binaries -# passed in as - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -if [ ! -d "$HOME/$1-install" ]; then - cd $HOME - - # init all submodules including the tools - CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=$CI_MAKE_NPROC $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 -fi diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh deleted file mode 100755 index b52ff33..0000000 --- a/.circleci/check-commit.sh +++ /dev/null @@ -1,152 +0,0 @@ -#!/bin/bash - -# check to see that submodule commits are present on the master branch - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# enter bhd repo -cd $LOCAL_CHIPYARD_DIR - -# ignore the private vlsi submodules -git config submodule.vlsi/hammer-cadence-plugins.update none -git config submodule.vlsi/hammer-mentor-plugins.update none -git config submodule.vlsi/hammer-synopsys-plugins.update none - -# initialize submodules and get the hashes -git submodule update --init -status=$(git submodule status) - -all_names=() - - -search_submodule() { - echo "Running check on submodule $submodule in $dir" - hash=$(echo "$status" | grep "$dir.*$submodule " | awk '{print$1}' | grep -o "[[:alnum:]]*") - for branch in "${branches[@]}" - do - echo "Searching for $hash in origin/$branch of $submodule" - (git -C $dir/$submodule branch -r --contains "$hash" | grep "origin/$branch") && true # needs init'ed submodules - if [ $? -eq 0 ] - then - all_names+=("$dir/$submodule $hash 0") - return - fi - done - all_names+=("$dir/$submodule $hash 1") - return -} - -search () { - for submodule in "${submodules[@]}" - do - search_submodule - done -} - -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") -dir="generators" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] -then - branches=("master" "main") -else - branches=("master" "main" "dev") -fi -search - -submodules=("riscv-gnu-toolchain" "riscv-isa-sim" "riscv-pk" "riscv-tests") -dir="toolchains/esp-tools" -branches=("master") -search - - -submodules=("riscv-gnu-toolchain" "riscv-isa-sim" "riscv-pk" "riscv-tests") -dir="toolchains/riscv-tools" -branches=("master") -search - -# riscv-openocd doesn't use its master branch -submodules=("riscv-openocd") -dir="toolchains/riscv-tools" -branches=("riscv") -search - -submodules=("qemu" "libgloss") -dir="toolchains" -branches=("master") -search - -submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017") -dir="software" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] -then - branches=("master") -else - branches=("master" "dev") -fi -search - -submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "firrtl-interpreter" "torture" "treadle") -dir="tools" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] -then - branches=("master") -else - branches=("master" "dev") -fi -search - -submodules=("dromajo-src") -dir="tools/dromajo" -branches=("master") -search - -submodules=("firesim") -dir="sims" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] -then - branches=("master") -else - branches=("master" "dev") -fi -search - -submodules=("hammer") -dir="vlsi" -branches=("master") -search - -submodules=("fpga-shells") -dir="fpga" -branches=("master") -search - -# turn off verbose printing to make this easier to read -set +x - -# print 0's -for str in "${all_names[@]}"; -do - if [ 0 = $(echo "$str" | awk '{print$3}') ]; then - echo "$str" - fi -done - -echo "" - -# check if there was a non-zero return code and print 1's -EXIT=0 -for str in "${all_names[@]}"; -do - if [ ! 0 = $(echo "$str" | awk '{print$3}') ]; then - echo "$str" - EXIT=1 - fi -done - -echo "Done checking all submodules" -exit $EXIT diff --git a/.circleci/clean-old-files.sh b/.circleci/clean-old-files.sh deleted file mode 100755 index 5824c4b..0000000 --- a/.circleci/clean-old-files.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/bash - -# clean directories that are older than 14 days -# argument is used as the directory to look in - -age () { - local AGE_SEC - local CUR_SEC - local DIFF_SEC - local SEC_PER_DAY - - SEC_PER_DAY=86400 - - CUR_SEC=$(date +%s) - AGE_SEC=$(stat -c %Y -- "$1") - DIFF_SEC=$(expr $CUR_SEC - $AGE_SEC) - - echo $(expr $DIFF_SEC / $SEC_PER_DAY) -} - -for d in $1/*/ ; do - DIR_AGE="$(age $d)" - if [ $DIR_AGE -ge 14 ]; then - echo "Deleting $d since is it $DIR_AGE old" - rm -rf $d - else - echo "Keep $d since it is $DIR_AGE old" - fi -done diff --git a/.circleci/config.yml b/.circleci/config.yml deleted file mode 100644 index ec59d8c..0000000 --- a/.circleci/config.yml +++ /dev/null @@ -1,534 +0,0 @@ -# CircleCI Configuration File - -# version of circleci -version: 2.1 - -parameters: - tools-cache-version: - type: string - default: "v13" - -# default execution env.s -executors: - main-env: - docker: - - image: ucbbar/chipyard-ci-image:554b436 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - -# re-usable commands -commands: - toolchain-build: - description: "Build a toolchain" - parameters: - tools-version: - type: string - default: "riscv-tools" - steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} - - run: - name: Building << parameters.tools-version >> - command: | - .circleci/build-toolchains.sh << parameters.tools-version >> - no_output_timeout: 120m - - save_cache: - key: << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} - paths: - - "/root/<< parameters.tools-version >>-install" - - ssh-checkout: - description: "Add SSH key and checkout code" - steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - "32:d6:89:d2:97:fa:db:de:a8:2d:2a:f2:70:dd:80:89" - - checkout - - setup-tools: - description: "Get toolchain" - parameters: - tools-version: - type: string - default: "riscv-tools" - steps: - - ssh-checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} - - prepare-rtl: - description: "Run the prepare step of RTL" - parameters: - tools-version: - type: string - default: "riscv-tools" - group-key: - type: string - timeout: - type: string - default: "120m" - build-script: - type: string - default: "do-rtl-build.sh" - build-type: - type: string - default: "sim" - steps: - - setup-tools: - tools-version: "<< parameters.tools-version >>" - - run: - name: Building << parameters.group-key >> subproject using Verilator - command: .circleci/<< parameters.build-script >> << parameters.group-key >> << parameters.build-type >> - no_output_timeout: << parameters.timeout >> - - save_cache: - key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} - paths: - - "/root/project" - - run-tests: - description: "Run a set of tests" - parameters: - tools-version: - type: string - default: "riscv-tools" - group-key: - type: string - project-key: - type: string - run-script: - type: string - default: "run-tests.sh" - timeout: - type: string - default: "25m" - steps: - - setup-tools: - tools-version: "<< parameters.tools-version >>" - - restore_cache: - keys: - - << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} - - run: - name: Run << parameters.project-key >> subproject tests - command: .circleci/<< parameters.run-script >> << parameters.project-key >> - no_output_timeout: << parameters.timeout >> - -# set of jobs to run -jobs: - commit-on-master-check: - executor: main-env - steps: - - checkout - - run: - name: Check commits of each submodule - command: | - .circleci/check-commit.sh - tutorial-setup-check: - executor: main-env - steps: - - checkout - - run: - name: Check that the tutorial-setup patches apply - command: | - scripts/tutorial-setup.sh - documentation-check: - executor: main-env - steps: - - checkout - - run: - name: Check that documentation builds with no warnings/errors - command: | - sudo apt-get update -y - sudo apt-get install -y python3-pip - sudo pip3 install -r docs/requirements.txt - make -C docs html - - install-riscv-toolchain: - executor: main-env - steps: - - toolchain-build: - tools-version: "riscv-tools" - install-esp-toolchain: - executor: main-env - steps: - - toolchain-build: - tools-version: "esp-tools" - install-verilator: - executor: main-env - steps: - - ssh-checkout - - run: - name: Install Verilator to remote - command: | - .circleci/install-verilator.sh - build-extra-tests: - executor: main-env - steps: - - ssh-checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../riscv-tools.hash" }} - - run: - name: Build extra tests - command: .circleci/build-extra-tests.sh - no_output_timeout: 120m - - save_cache: - key: extra-tests-{{ .Branch }}-{{ .Revision }} - paths: - - "/root/project/tests" - - prepare-chipyard-cores: - executor: main-env - steps: - - prepare-rtl: - group-key: "group-cores" - prepare-chipyard-peripherals: - executor: main-env - steps: - - prepare-rtl: - group-key: "group-peripherals" - prepare-chipyard-accels: - executor: main-env - steps: - - prepare-rtl: - tools-version: "esp-tools" - group-key: "group-accels" - prepare-chipyard-tracegen: - executor: main-env - steps: - - prepare-rtl: - group-key: "group-tracegen" - prepare-chipyard-other: - executor: main-env - steps: - - prepare-rtl: - group-key: "group-other" - - chipyard-rocket-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-rocket" - chipyard-hetero-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-hetero" - timeout: "20m" - chipyard-boom-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-boom" - chipyard-cva6-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-cva6" - timeout: "30m" - chipyard-sodor-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor" - timeout: "30m" - chipyard-ibex-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-ibex" - timeout: "30m" - chipyard-multiclock-rocket-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-multiclock-rocket" - chipyard-dmirocket-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-peripherals" - project-key: "chipyard-dmirocket" - chipyard-spiflashwrite-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-peripherals" - project-key: "chipyard-spiflashwrite" - chipyard-spiflashread-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-peripherals" - project-key: "chipyard-spiflashread" - chipyard-lbwif-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-peripherals" - project-key: "chipyard-lbwif" - - chipyard-sha3-run-tests: - executor: main-env - steps: - - run-tests: - tools-version: "esp-tools" - group-key: "group-accels" - project-key: "chipyard-sha3" - chipyard-streaming-fir-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-accels" - project-key: "chipyard-streaming-fir" - chipyard-streaming-passthrough-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-accels" - project-key: "chipyard-streaming-passthrough" - chipyard-hwacha-run-tests: - executor: main-env - steps: - - run-tests: - tools-version: "esp-tools" - group-key: "group-accels" - project-key: "chipyard-hwacha" - timeout: "60m" - chipyard-gemmini-run-tests: - executor: main-env - steps: - - run-tests: - tools-version: "esp-tools" - group-key: "group-accels" - project-key: "chipyard-gemmini" - chipyard-nvdla-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-accels" - project-key: "chipyard-nvdla" - tracegen-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-tracegen" - project-key: "tracegen" - tracegen-boom-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-tracegen" - project-key: "tracegen-boom" - icenet-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-other" - project-key: "icenet" - timeout: "30m" - testchipip-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-other" - project-key: "testchipip" - timeout: "30m" - firesim-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "extra-tests" - project-key: "firesim" - run-script: "run-firesim-scala-tests.sh" - timeout: "20m" - fireboom-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "extra-tests" - project-key: "fireboom" - run-script: "run-firesim-scala-tests.sh" - timeout: "45m" - firesim-multiclock-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "extra-tests" - project-key: "firesim-multiclock" - run-script: "run-firesim-scala-tests.sh" - timeout: "20m" - prepare-chipyard-fpga: - executor: main-env - steps: - - prepare-rtl: - group-key: "group-fpga" - build-type: "fpga" - -# Order and dependencies of jobs to run -workflows: - version: 2 - submodules-on-master: - jobs: - # Check to make sure submodule commits are on master branches - - commit-on-master-check - triggers: - - schedule: - cron: "0 0 * * *" - filters: - branches: - only: - - master - - build-and-test-chipyard-integration: - jobs: - # Make the toolchains - - install-riscv-toolchain - - - install-esp-toolchain - - - install-verilator - - - commit-on-master-check - - # Attempt to apply the tutorial patches - - tutorial-setup-check - - # Check that documentation builds - - documentation-check - - # Build extra tests - - build-extra-tests: - requires: - - install-riscv-toolchain - - # Prepare the verilator builds - - prepare-chipyard-cores: - requires: - - install-riscv-toolchain - - install-verilator - - prepare-chipyard-peripherals: - requires: - - install-riscv-toolchain - - install-verilator - - prepare-chipyard-accels: - requires: - - install-esp-toolchain - - install-verilator - - prepare-chipyard-tracegen: - requires: - - install-riscv-toolchain - - install-verilator - - prepare-chipyard-other: - requires: - - install-riscv-toolchain - - install-verilator - - # Run the example tests - - chipyard-rocket-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-hetero-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-boom-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-cva6-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-sodor-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-ibex-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-dmirocket-run-tests: - requires: - - prepare-chipyard-peripherals - - chipyard-spiflashwrite-run-tests: - requires: - - prepare-chipyard-peripherals - - chipyard-spiflashread-run-tests: - requires: - - prepare-chipyard-peripherals - - chipyard-lbwif-run-tests: - requires: - - prepare-chipyard-peripherals - - - chipyard-sha3-run-tests: - requires: - - prepare-chipyard-accels - - chipyard-streaming-fir-run-tests: - requires: - - prepare-chipyard-accels - - chipyard-streaming-passthrough-run-tests: - requires: - - prepare-chipyard-accels - - chipyard-hwacha-run-tests: - requires: - - prepare-chipyard-accels - - chipyard-gemmini-run-tests: - requires: - - prepare-chipyard-accels - - chipyard-nvdla-run-tests: - requires: - - prepare-chipyard-accels - - - tracegen-run-tests: - requires: - - prepare-chipyard-tracegen - - tracegen-boom-run-tests: - requires: - - prepare-chipyard-tracegen - - - icenet-run-tests: - requires: - - prepare-chipyard-other - - testchipip-run-tests: - requires: - - prepare-chipyard-other - - # Run the firesim tests - - firesim-run-tests: - requires: - - install-riscv-toolchain - - install-verilator - - build-extra-tests - - firesim-multiclock-run-tests: - requires: - - install-riscv-toolchain - - install-verilator - - build-extra-tests - - fireboom-run-tests: - requires: - - install-riscv-toolchain - - install-verilator - - build-extra-tests - - # Prepare the fpga builds (just Verilog) - - prepare-chipyard-fpga: - requires: - - install-riscv-toolchain diff --git a/.circleci/create-hash.sh b/.circleci/create-hash.sh deleted file mode 100755 index 7a8915a..0000000 --- a/.circleci/create-hash.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -# get the hash of riscv-tools - -# turn echo on and error on earliest command -set -ex -set -o pipefail - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# enter bhd repo -cd $LOCAL_CHIPYARD_DIR - -# Use normalized output of git-submodule status as hashfile -for tools in 'riscv-tools' 'esp-tools' ; do - git submodule status "toolchains/${tools}" 'toolchains/libgloss' 'toolchains/qemu' | - while read -r line ; do - echo "${line#[!0-9a-f]}" - done > "${HOME}/${tools}.hash" -done -echo "Hashfile for riscv-tools and esp-tools created in $HOME" diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh deleted file mode 100755 index bfb63a3..0000000 --- a/.circleci/defaults.sh +++ /dev/null @@ -1,92 +0,0 @@ -#!/bin/bash - -copy () { - rsync -avzp -e 'ssh' --exclude '.git' $1 $2 -} - -run () { - ssh -o "StrictHostKeyChecking no" -t $SERVER $@ -} - -run_script () { - ssh -o "StrictHostKeyChecking no" -t $SERVER 'bash -s' < $1 "$2" -} - -clean () { - # remove remote work dir - run "rm -rf $REMOTE_WORK_DIR" -} - -# make parallelism -CI_MAKE_NPROC=8 -# chosen based on a 24c system shared with 1 other project -REMOTE_MAKE_NPROC=4 - -# verilator version -VERILATOR_VERSION=v4.034 - -# remote variables -REMOTE_PREFIX=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH -REMOTE_WORK_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-$CIRCLE_JOB -REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install -REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install -REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard -REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator -REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim -REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga -REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" -# Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI -REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" -REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install - -# local variables (aka within the docker container) -LOCAL_CHECKOUT_DIR=$HOME/project -LOCAL_RISCV_DIR=$HOME/riscv-tools-install -LOCAL_ESP_DIR=$HOME/esp-tools-install -LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR -LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator -LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim - -# key value store to get the build groups -declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad" -grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" -grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" -grouping["group-tracegen"]="tracegen tracegen-boom" -grouping["group-other"]="icenet testchipip" -grouping["group-fpga"]="arty vcu118" - -# key value store to get the build strings -declare -A mapping -mapping["chipyard-rocket"]="" -mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" -mapping["chipyard-lbwif"]=" CONFIG=LBWIFRocketConfig" -mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" -mapping["chipyard-digitaltop"]=" TOP=DigitalTop" -mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" -mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" -mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" -mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig" -mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig" -mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" -mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" -mapping["chipyard-cva6"]=" CONFIG=CVA6Config" -mapping["chipyard-ibex"]=" CONFIG=IbexConfig" -mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig" -mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig" -mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" -mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" -mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" -mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" -mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig" -mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig" -mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig" - -mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" -mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" -mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" -mapping["icenet"]="SUB_PROJECT=icenet" -mapping["testchipip"]="SUB_PROJECT=testchipip" - -mapping["arty"]="SUB_PROJECT=arty verilog" -mapping["vcu118"]="SUB_PROJECT=vcu118 verilog" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh deleted file mode 100755 index 3a537ea..0000000 --- a/.circleci/do-rtl-build.sh +++ /dev/null @@ -1,92 +0,0 @@ -#!/bin/bash - -# create the different verilator builds -# usage: -# do-rtl-build.sh sim -# run rtl build for simulations and copy back results -# do-rtl-build.sh fpga -# run rtl build for fpga and don't copy back results - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# call clean on exit -trap clean EXIT - -cd $LOCAL_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh -./scripts/init-fpga.sh - -# set stricthostkeychecking to no (must happen before rsync) -run "echo \"Ping $SERVER\"" - -clean - -# copy over riscv/esp-tools, and chipyard to remote -run "mkdir -p $REMOTE_CHIPYARD_DIR" -copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR - -run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" -run "cp -r ~/.sbt $REMOTE_WORK_DIR" - -TOOLS_DIR=$REMOTE_RISCV_DIR -LD_LIB_DIR=$REMOTE_RISCV_DIR/lib - -if [ $1 = "group-accels" ]; then - export RISCV=$LOCAL_ESP_DIR - export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib - export PATH=$RISCV/bin:$PATH - GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests - cd $LOCAL_SIM_DIR/../../generators/gemmini/software - git submodule update --init --recursive gemmini-rocc-tests - cd gemmini-rocc-tests - ./build.sh - - TOOLS_DIR=$REMOTE_ESP_DIR - LD_LIB_DIR=$REMOTE_ESP_DIR/lib - run "mkdir -p $REMOTE_ESP_DIR" - copy $LOCAL_ESP_DIR/ $SERVER:$REMOTE_ESP_DIR -else - run "mkdir -p $REMOTE_RISCV_DIR" - copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR -fi - -# choose what make dir to use -case $2 in - "sim") - REMOTE_MAKE_DIR=$REMOTE_SIM_DIR - ;; - "fpga") - REMOTE_MAKE_DIR=$REMOTE_FPGA_DIR - ;; -esac - -# enter the verilator directory and build the specific config on remote server -run "export RISCV=\"$TOOLS_DIR\"; \ - make -C $REMOTE_MAKE_DIR clean;" - -read -a keys <<< ${grouping[$1]} - -# need to set the PATH to use the new verilator (with the new verilator root) -for key in "${keys[@]}" -do - run "export RISCV=\"$TOOLS_DIR\"; \ - export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ - export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_TOOL_OPTIONS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}" -done - -run "rm -rf $REMOTE_CHIPYARD_DIR/project" - -# choose to copy back results -if [ $2 = "sim" ]; then - # copy back the final build - mkdir -p $LOCAL_CHIPYARD_DIR - copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR -fi diff --git a/.circleci/install-verilator.sh b/.circleci/install-verilator.sh deleted file mode 100755 index 2170768..0000000 --- a/.circleci/install-verilator.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/bash - -# move verilator to the remote server - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# clean older directories (delete prior directories related to this branch also) -run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR -run "rm -rf $REMOTE_PREFIX*" - -# set stricthostkeychecking to no (must happen before rsync) -run "echo \"Ping $SERVER\"" - -run "git clone http://git.veripool.org/git/verilator $REMOTE_VERILATOR_DIR; \ - cd $REMOTE_VERILATOR_DIR; \ - git checkout $VERILATOR_VERSION; \ - autoconf; \ - export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; \ - ./configure; \ - make -j$REMOTE_MAKE_NPROC;" diff --git a/.circleci/run-firesim-scala-tests.sh b/.circleci/run-firesim-scala-tests.sh deleted file mode 100755 index 022894f..0000000 --- a/.circleci/run-firesim-scala-tests.sh +++ /dev/null @@ -1,59 +0,0 @@ -#!/bin/bash - -# create the different verilator builds -# argument is the make command string - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# call clean on exit -trap clean EXIT - -# Directory locations for handling firesim-local installations of libelf/libdwarf -# This would generally be handled by build-setup.sh/firesim-setup.sh -firesim_sysroot=lib-install -local_firesim_sysroot=$LOCAL_FIRESIM_DIR/$firesim_sysroot -remote_firesim_sysroot=$REMOTE_FIRESIM_DIR/$firesim_sysroot - -cd $LOCAL_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh -cd $LOCAL_CHIPYARD_DIR/sims/firesim/sim/firesim-lib/src/main/cc/lib -git submodule update --init elfutils libdwarf -cd $LOCAL_CHIPYARD_DIR/sims/firesim -mkdir -p $local_firesim_sysroot -./scripts/build-libelf.sh $local_firesim_sysroot -./scripts/build-libdwarf.sh $local_firesim_sysroot -cd $LOCAL_CHIPYARD_DIR - -make -C $LOCAL_CHIPYARD_DIR/tools/dromajo/dromajo-src/src - -# set stricthostkeychecking to no (must happen before rsync) -run "echo \"Ping $SERVER\"" - -clean - -# copy over riscv/esp-tools, and chipyard to remote -run "mkdir -p $REMOTE_CHIPYARD_DIR" -run "mkdir -p $REMOTE_RISCV_DIR" -copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR -copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR - -run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" -run "cp -r ~/.sbt $REMOTE_WORK_DIR" - -TOOLS_DIR=$REMOTE_RISCV_DIR - -LD_LIB_DIR=$remote_firesim_sysroot/lib:$REMOTE_RISCV_DIR/lib - -# Run Firesim Scala Tests -run "export RISCV=\"$TOOLS_DIR\"; \ - export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export FIRESIM_ENV_SOURCED=1; \ - export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ - export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -C $REMOTE_FIRESIM_DIR JAVA_TOOL_OPTIONS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" testOnly ${mapping[$1]}" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh deleted file mode 100755 index 461843f..0000000 --- a/.circleci/run-tests.sh +++ /dev/null @@ -1,120 +0,0 @@ -#!/bin/bash - -# run the different tests - -# turn echo on and error on earliest command -set -ex - -# get remote exec variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -run_bmark () { - make run-bmark-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $@ -} - -run_asm () { - make run-asm-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $@ -} - -run_both () { - run_bmark $@ - run_asm $@ -} - -run_tracegen () { - make tracegen -C $LOCAL_SIM_DIR $@ -} - -# TODO BUG: the run-binary command forces a rebuild of the simulator in CI -# instead, directly run the simulator binary -case $1 in - chipyard-rocket) - run_bmark ${mapping[$1]} - ;; - chipyard-dmirocket) - run_bmark ${mapping[$1]} - ;; - chipyard-lbwif) - run_bmark ${mapping[$1]} - ;; - chipyard-boom) - run_bmark ${mapping[$1]} - ;; - chipyard-hetero) - run_bmark ${mapping[$1]} - ;; - rocketchip) - run_bmark ${mapping[$1]} - ;; - chipyard-hwacha) - export RISCV=$LOCAL_ESP_DIR - export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib - export PATH=$RISCV/bin:$PATH - make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR ${mapping[$1]} - ;; - chipyard-gemmini) - export RISCV=$LOCAL_ESP_DIR - export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib - export PATH=$RISCV/bin:$PATH - GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests - rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests - cd $LOCAL_SIM_DIR - $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal - ;; - chipyard-sha3) - export RISCV=$LOCAL_ESP_DIR - export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib - export PATH=$RISCV/bin:$PATH - (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) - $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/tests/bare/sha3-rocc.riscv - ;; - chipyard-streaming-passthrough) - make -C $LOCAL_CHIPYARD_DIR/tests - $LOCAL_SIM_DIR/simulator-chipyard-StreamingPassthroughRocketConfig $LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv - ;; - chipyard-streaming-fir) - make -C $LOCAL_CHIPYARD_DIR/tests - $LOCAL_SIM_DIR/simulator-chipyard-StreamingFIRRocketConfig $LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv - ;; - chipyard-spiflashread) - make -C $LOCAL_CHIPYARD_DIR/tests - make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary - ;; - chipyard-spiflashwrite) - make -C $LOCAL_CHIPYARD_DIR/tests - make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary - [[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false - ;; - tracegen) - run_tracegen ${mapping[$1]} - ;; - tracegen-boom) - run_tracegen ${mapping[$1]} - ;; - chipyard-cva6) - make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv - ;; - chipyard-sodor) - run_asm ${mapping[$1]} - ;; - chipyard-ibex) - run_bmark ${mapping[$1]} #TODO: Find 32-bit test - ;; - chipyard-nvdla) - make -C $LOCAL_CHIPYARD_DIR/tests - make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary - ;; - icenet) - make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR ${mapping[$1]} - ;; - testchipip) - make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR ${mapping[$1]} - ;; - *) - echo "No set of tests for $1. Did you spell it right?" - exit 1 - ;; -esac diff --git a/.gitignore b/.gitignore index f57cd7e..c436e1e 100644 --- a/.gitignore +++ b/.gitignore @@ -26,11 +26,11 @@ cep_adrMap.h v2c_cmds.h .PERSUITE* -**/*.dump -**/*.bin -**/*.img -**/*.elf -**/*.o +*.dump +*.bin +*.img +*.elf +*.o diff --git a/.gitmodules b/.gitmodules index 0329de8..1032cda 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,18 +4,15 @@ [submodule "fpga/fpga-shells"] path = fpga/fpga-shells url = https://github.com/sifive/fpga-shells.git -[submodule "generators/fft-generator"] - path = generators/fft-generator - url = https://github.com/ucb-bar/FFTGenerator.git -[submodule "CEP_Chipyard_ASIC"] - path = CEP_Chipyard_ASIC - url = ssh://git@llcad-github/HSS/CEP_Chipyard_ASIC.git [submodule "generators/boom"] path = generators/boom url = https://github.com/riscv-boom/riscv-boom.git [submodule "generators/cva6"] path = generators/cva6 url = https://github.com/ucb-bar/cva6-wrapper.git +[submodule "generators/fft-generator"] + path = generators/fft-generator + url = https://github.com/ucb-bar/FFTGenerator.git [submodule "generators/gemmini"] path = generators/gemmini url = https://github.com/ucb-bar/gemmini @@ -133,3 +130,6 @@ [submodule "vlsi/hammer-cadence-plugins"] path = vlsi/hammer-cadence-plugins url = https://github.com/ucb-bar/hammer-cadence-plugins.git +[submodule "CEP_Chipyard_ASIC"] + path = CEP_Chipyard_ASIC + url = ssh://git@llcad-github/HSS/CEP_Chipyard_ASIC.git diff --git a/CHANGELOG.CEP.md b/CHANGELOG.CEP.md index 1297bfd..344d9f9 100644 --- a/CHANGELOG.CEP.md +++ b/CHANGELOG.CEP.md @@ -6,74 +6,121 @@ # CEP Changelog -This changelog follows the format defined here (beginning with v4.0): https://keepachangelog.com/en/1.0.0/ +## [v4.20] - 2022-08-03 -##v1.0 - Initial release +### Added +* Added kgetc to bare metal console routines +* Verified firemarshal generated linux build boots on the Arty100T, VC707, and VCU118. Instructions added to [README.md](./README.md) +* Added `helloworld` and `gpiotest` to ./software/linux. Makefiles allow application's install to firemarshal's buildroot. +* Added VC707 CEP FPGA target thanks to the folks at NECSTLab (https://github.com/necst) +* Added VCU118 CEP FPGA target -##v1.1 - (19 July 2018) -* Directory structure has been reorganized (details below) -* Upgraded to the non-deprecated mor1kx (added as a subnodule) -* Verified with both the pre-built and build-your-own version of the Newlib toolchain as described on [http://openrisc.io](http://openrisc.io) -* In addition to test vectors for each of the cores, some additional test_software, such as "hello world", have been added for reference -* Expanded testbench (details below) -* Bug fixes and general code cleanup [Additional details in the git commit history] +### Changed +* Unified console print routines across bootroms, cosim baremetal, and standalone bare metal code. Bare metal prints are now handled using stdio functions with + putchar, getchar, and putstr being mapped to the console versions + +### Known issues +* cep_cosim + * Cadence XCellium on RHEL7 *occasionally* fails some of the bareMetal tests. Root cause has not been determined, but it is recommended that the test be re-run. + * Known est failures: + * ./testSuites/bfmTests/macroMix - GPS Test - First core passes, subsequent cores fail. + * Virtual mode ISA tests - Failure on Questsim/Ubuntu, passes on XCellium/RHEL7 + * ./testSuites/isaTests/rv64mi-p-csr + * ./testSuites/isaTests/rv64si-p-csr + * ./testSuites/bfmTests/srotErrorTest + * ./testSuites/bareMetalTests/plicPrioIntr + * ./testSuites/bareMetalTests/extIntr + * ./testSuites/bareMetalTests/lsrcOps + * ./testSuites/isaTests/dtmTest -##v1.1.1 - (27 September 2018) -* Added CEP\_utilization\_placed.rpt in implSummaries directory. This summarizes utlization of the CEP v1.1 targetted to the VC707 using Vivado 2018.1. +## [v4.10] - 2022-07-01 -##v1.2 - (15 November 2018) -* Major Update: The underlying bus has been converted from Wishbone-B4 to AXI4-Lite. All cores as well as the MOR1KX has been wrapped with translation modules. All the wrapping logic and interconnect are now in SystemVerilog. -* Regression Suite: In additon to each core's unit tests, a regression test suite has been included. When compiled by the or1k toolchain, it be loaded/synthesized into the CEP RAM block and run at boot time. -* Modelsim Testing: Unit-level and system-level modelsim-based testbenches added -* GPS clkgen: The GPS clock gen component has been moved to the top level of the CEP, simplifying its replacement when targetting an ASIC. -* Misc. bug fixes +### Added +* Added a bareMetal/aesMacro test for running on the Arty100T build, which currently only has one AES core and the SRoT -##v2.0 - (16 August 2019) -* Major Update: mor1k proceesor core replaced with the UCB Rocket-Chip within the SiFive Freedom U500 Platform. All modules have been updated to support TileLink natively. Currently only the AES and FIR cores have been integrated, but v2.1 will include the re-release of all the CEP cores. +### Changed +* Unified/debugged console printf functionality when building bare metal executables. By default, it is disabled, but can be enabled with the ENABLE_KPRINTF directive +* Arty100T and cep_sim use the same 'sd.c' source file, but leverage different makefiles. +* Misc. code and readme cleanup +* Bumped Chipyard to 1.7.0 from 1.5.0. See [CHANGELOG](./CHANGELOG.md). +* Rocket-Chip bumped to v1.5 -##v2.1 - (31 October 2019) -* Integrated DES3, GPS, MD5, RSA, SHA256, DFT, IDFT, and IIR cores. +### Fixed +* iDFT test code fixed in cep_idft.cc -##v2.2 - (31 January 2020) -* Added co-simulation environment that supports both Bus Functional Model (BFM) and Baremetal simulation modes. Additional diagnostic capabilities within Linux. +## [v4.00] - 2022-06-21 -##v2.3 - (17 April 2020) -* Added unit-level testbenches for all CEP cores. Co-simulation modified to generate unit-level test stimulus. +### Added +* Chipyard Arty100t branch merged in (Commit 4440db0, March 4, 2022) -##v2.4 - (5 June 2020) -* CEP core test coverage expanded -* Unit testbenches transactional-level support added -* AES-derived and FIR-derived generated cores added -* Misc. bug fixes +### Changed +* CHANGELOG.CEP.md updated based on guidance from *keep a changelog* (https://keepachangelog.com/en/1.0.0/) +* CEP has been completely ported to the UCB Chipyard Framework (https://github.com/ucb-bar/chipyard) +* Arty-A7 100T FPGA target running bare-metal code is currently supported (Linux is not currently supported) -##v2.5 - (31 July 2020) -* All Unit-level testbenches have been expanded to optional support the Logic Locking Keying Interface (LLKI) - for both cycle-level and transactional-level modes +## v3.41 - (10 September 2021) +* CEP Configuration nows includes 4xGPS and 4xSHA-256 cores +* Integrated configurable co-simulation environment (provide a co-sim that can more easily adapt to CEP architecture changes) +* Known Issues: + - Some idft test vectors fail under QuestaSim (xcellium regression ran successfully) + - Multithreaded test (#23) non-functional under linux -##v2.51 - (7 August 2020) -* Legacy unused core wrapper files (axi4lite and wb) removed +##v3.4 - (6 August 2021) +* Added external interrupt test (extIntr) +* Added test to boot rom to verify code execution out of scratchpad is working +* Added cryptoMask to cep_srot to support individual key loading only if enable +* Restructured cosim Makefiles to support re-use from other repos +* Modified cadence Makefile to enable partial toggle scoring +* Changed un-initialized main memory default state (from 0 -> 1) to improve coverage +* Addressed an LLKI bug in which the LLKI-PP component would send a respond to the SRoT before llkid_key_complete is asserted by the mock_tss_fsm +* Fixed GPS port directions in verilog +* Scratchpad RAM changed to blackbox implementation to facilitate ASIC development +* OpenSSL replaced by Cryptopp for crypto-related tests (cosim + linux) -##v2.52 - (2 September 2020) -* Added ./doc/CEP_TestDescriptions.pdf +##v3.3 - (19 May 2021) +* Increased capacity for LLKI key size including larger KeyRAM (2048 64-bit words) +* Added Cosim JTAG/OpenOCD +* Stability fixes for cep_diag under Linux +* Virtual Address TLB test suite is added to regression (not 100% complete) +* Expanded cep_diag +* New simulation ONLY interrupt tests for CLINT and PLIC modules (on going) +* Re-capture vectors for unit sim due to changes in LLKI key size +* Bootrom size is increased to 32K bytes (8kx32) to accomodate new built-in test (execute codes out of bootrom without main memory) -##v2.6 - (18 September 2020) -* Rocket-Chip and Freedom repositories updated. Source responsitory list: - https://github.com/sifive/freedom/tree/8622a684e7e54d0a20df90659285b9c587772629 - Aug 19, 2020 - https://github.com/chipsalliance/rocket-chip/tree/d2210f9545903fad40c9860389cdcf9c28515dba - Apr 2, 2020 - https://github.com/sifive/fpga-shells/tree/19d0818deda5d295154992bd4e2c490b7c905df9 - Jan 28, 2020 - https://github.com/sifive/sifive-blocks/tree/12bdbe50636b6c57c8dc997e483787fdb5ee540b - Dec 17, 2019 - https://github.com/mcd500/freedom-u-sdk/tree/29fe529f8dd8e1974fe1743184b3e13ebb2a21dc - Apr 12, 2019 -* riscv-tools (formerly under rocket-chip) now located in ./software/riscv-gnu-toolchain -* KNOWN ISSUES: - - The iCacheCoherency passes when running bare-metal simulation, but fails when running on the VC-707. There is an issue with - the iCache protocol that the tight-looped iCache coherency test results in one or more of the Rocket Cores (there are 4 in - the CEP) L1 iCache not getting the value associated with the most recent write to instruction memory. +##v3.2 - (16 April 2021) +* LLKI bug fixes +* Scratchpad RAM added +* Cadenece xcelium simulator and coverage support added +* Linux tests updated and expanded +* New tests added to cosim focused on LLKI and Scratchpad RAM - Functionally, this should only cause an issue when dealing with self-modifying code, which is an atypical coding practice. +##v3.11 - (29 March 2021) +* Unit Simulations updated for full LLKI support +* GPS core bugfix to provide specification compliance and increase functional coverage +* SRoT tests added +* SRoT has been updated to use a single port (1RW) RAM. +* Misc. bug fixes and README cleanup +* Known Issues: + - cep_diag (on Linux) has NOT been updated to work with the LLKI. Thus, running the tests that use + the CEP cores (e.g., cep_aes, cep_des3, etc.) will result in failure -##v2.61 - (2 October 2020) - - Added initial simulation support for Cadence XCellium - - Cosim: Expanded DDR3 memory size to support "larger" bare-metal executables created by the new RISCV toolchain released with v2.6 +##v3.1 - (22 February 2021) +* Full LLKI support (All CEP cores are now LLKI enabled) +* Known Issues: + - cep_diag (on Linux) has NOT been updated to work with the LLKI. Thus, running the tests that use + the CEP cores (e.g., cep_aes, cep_des3, etc.) will result in failure + - rv64si-p-dirty ISA test fails + - unit_simulations need to be updated to be compatible with the LLKI + +##v3.01 - (19 December 2020) +* Removed used flash model reference in cep_tb.v + +##v3.0 - (18 December 2020) +* Initial LLKI release with Surrogate Root of Trust +* AES core replaced with LLKI-enabled AES core, all other cores remain unchanged + +##v2.71 - (2 November 2020) +* Corrected README.md issue ##v2.7 - (28 October 2020) * Added support for RISC-V ISA tests (under ./cosim/isaTests) @@ -90,93 +137,71 @@ This changelog follows the format defined here (beginning with v4.0): https://ke - isaTests/rv64mi-p-access - isaTests/rv64ud-p-ldst -##v2.71 - (2 November 2020) -* Corrected README.md issue - -##v3.0 - (18 December 2020) -* Initial LLKI release with Surrogate Root of Trust -* AES core replaced with LLKI-enabled AES core, all other cores remain unchanged +##v2.61 - (2 October 2020) + - Added initial simulation support for Cadence XCellium + - Cosim: Expanded DDR3 memory size to support "larger" bare-metal executables created by the new RISCV toolchain released with v2.6 -##v3.01 - (19 December 2020) -* Removed used flash model reference in cep_tb.v +##v2.6 - (18 September 2020) +* Rocket-Chip and Freedom repositories updated. Source responsitory list: + https://github.com/sifive/freedom/tree/8622a684e7e54d0a20df90659285b9c587772629 - Aug 19, 2020 + https://github.com/chipsalliance/rocket-chip/tree/d2210f9545903fad40c9860389cdcf9c28515dba - Apr 2, 2020 + https://github.com/sifive/fpga-shells/tree/19d0818deda5d295154992bd4e2c490b7c905df9 - Jan 28, 2020 + https://github.com/sifive/sifive-blocks/tree/12bdbe50636b6c57c8dc997e483787fdb5ee540b - Dec 17, 2019 + https://github.com/mcd500/freedom-u-sdk/tree/29fe529f8dd8e1974fe1743184b3e13ebb2a21dc - Apr 12, 2019 +* riscv-tools (formerly under rocket-chip) now located in ./software/riscv-gnu-toolchain +* KNOWN ISSUES: + - The iCacheCoherency passes when running bare-metal simulation, but fails when running on the VC-707. There is an issue with + the iCache protocol that the tight-looped iCache coherency test results in one or more of the Rocket Cores (there are 4 in + the CEP) L1 iCache not getting the value associated with the most recent write to instruction memory. -##v3.1 - (22 February 2021) -* Full LLKI support (All CEP cores are now LLKI enabled) -* Known Issues: - - cep_diag (on Linux) has NOT been updated to work with the LLKI. Thus, running the tests that use - the CEP cores (e.g., cep_aes, cep_des3, etc.) will result in failure - - rv64si-p-dirty ISA test fails - - unit_simulations need to be updated to be compatible with the LLKI + Functionally, this should only cause an issue when dealing with self-modifying code, which is an atypical coding practice. -##v3.11 - (29 March 2021) -* Unit Simulations updated for full LLKI support -* GPS core bugfix to provide specification compliance and increase functional coverage -* SRoT tests added -* SRoT has been updated to use a single port (1RW) RAM. -* Misc. bug fixes and README cleanup -* Known Issues: - - cep_diag (on Linux) has NOT been updated to work with the LLKI. Thus, running the tests that use - the CEP cores (e.g., cep_aes, cep_des3, etc.) will result in failure +##v2.52 - (2 September 2020) +* Added ./doc/CEP_TestDescriptions.pdf -##v3.2 - (16 April 2021) -* LLKI bug fixes -* Scratchpad RAM added -* Cadenece xcelium simulator and coverage support added -* Linux tests updated and expanded -* New tests added to cosim focused on LLKI and Scratchpad RAM +##v2.51 - (7 August 2020) +* Legacy unused core wrapper files (axi4lite and wb) removed -##v3.3 - (19 May 2021) -* Increased capacity for LLKI key size including larger KeyRAM (2048 64-bit words) -* Added Cosim JTAG/OpenOCD -* Stability fixes for cep_diag under Linux -* Virtual Address TLB test suite is added to regression (not 100% complete) -* Expanded cep_diag -* New simulation ONLY interrupt tests for CLINT and PLIC modules (on going) -* Re-capture vectors for unit sim due to changes in LLKI key size -* Bootrom size is increased to 32K bytes (8kx32) to accomodate new built-in test (execute codes out of bootrom without main memory) +##v2.5 - (31 July 2020) +* All Unit-level testbenches have been expanded to optional support the Logic Locking Keying Interface (LLKI) + for both cycle-level and transactional-level modes -##v3.4 - (6 August 2021) -* Added external interrupt test (extIntr) -* Added test to boot rom to verify code execution out of scratchpad is working -* Added cryptoMask to cep_srot to support individual key loading only if enable -* Restructured cosim Makefiles to support re-use from other repos -* Modified cadence Makefile to enable partial toggle scoring -* Changed un-initialized main memory default state (from 0 -> 1) to improve coverage -* Addressed an LLKI bug in which the LLKI-PP component would send a respond to the SRoT before llkid_key_complete is asserted by the mock_tss_fsm -* Fixed GPS port directions in verilog -* Scratchpad RAM changed to blackbox implementation to facilitate ASIC development -* OpenSSL replaced by Cryptopp for crypto-related tests (cosim + linux) +##v2.4 - (5 June 2020) +* CEP core test coverage expanded +* Unit testbenches transactional-level support added +* AES-derived and FIR-derived generated cores added +* Misc. bug fixes -## v3.41 - (10 September 2021) -* CEP Configuration nows includes 4xGPS and 4xSHA-256 cores -* Integrated configurable co-simulation environment (provide a co-sim that can more easily adapt to CEP architecture changes) -* Known Issues: - - Some idft test vectors fail under QuestaSim (xcellium regression ran successfully) - - Multithreaded test (#23) non-functional under linux +##v2.3 - (17 April 2020) +* Added unit-level testbenches for all CEP cores. Co-simulation modified to generate unit-level test stimulus. -## [v4.00] - 2022-06-21 +##v2.2 - (31 January 2020) +* Added co-simulation environment that supports both Bus Functional Model (BFM) and Baremetal simulation modes. Additional diagnostic capabilities within Linux. -### Added -* Chipyard Arty100t branch merged in (Commit 4440db0, March 4, 2022) +##v2.1 - (31 October 2019) +* Integrated DES3, GPS, MD5, RSA, SHA256, DFT, IDFT, and IIR cores. -### Changed -* CHANGELOG.CEP.md updated based on guidance from *keep a changelog* (https://keepachangelog.com/en/1.0.0/) -* CEP has been completely ported to the UCB Chipyard Framework (https://github.com/ucb-bar/chipyard) -* Arty-A7 100T FPGA target running bare-metal code is currently supported (Linux is not currently supported) +##v2.0 - (16 August 2019) +* Major Update: mor1k proceesor core replaced with the UCB Rocket-Chip within the SiFive Freedom U500 Platform. All modules have been updated to support TileLink natively. Currently only the AES and FIR cores have been integrated, but v2.1 will include the re-release of all the CEP cores. -## [v4.10] - 2022-07-01 +##v1.2 - (15 November 2018) +* Major Update: The underlying bus has been converted from Wishbone-B4 to AXI4-Lite. All cores as well as the MOR1KX has been wrapped with translation modules. All the wrapping logic and interconnect are now in SystemVerilog. +* Regression Suite: In additon to each core's unit tests, a regression test suite has been included. When compiled by the or1k toolchain, it be loaded/synthesized into the CEP RAM block and run at boot time. +* Modelsim Testing: Unit-level and system-level modelsim-based testbenches added +* GPS clkgen: The GPS clock gen component has been moved to the top level of the CEP, simplifying its replacement when targetting an ASIC. +* Misc. bug fixes -### Added -* Added a bareMetal/aesMacro test for running on the Arty100T build, which currently only has one AES core and the SRoT +##v1.1.1 - (27 September 2018) +* Added CEP\_utilization\_placed.rpt in implSummaries directory. This summarizes utlization of the CEP v1.1 targetted to the VC707 using Vivado 2018.1. -### Changed -* Unified/debugged console printf functionality when building bare metal executables. By default, it is disabled, but can be enabled with the ENABLE_KPRINTF directive -* Arty100T and cep_sim use the same 'sd.c' source file, but leverage different makefiles. -* Misc. code and readme cleanup -* Bumped Chipyard to 1.7.0 from 1.5.0. See [CHANGELOG](./CHANGELOG.md). -* Rocket-Chip bumped to v1.5 +##v1.1 - (19 July 2018) +* Directory structure has been reorganized (details below) +* Upgraded to the non-deprecated mor1kx (added as a subnodule) +* Verified with both the pre-built and build-your-own version of the Newlib toolchain as described on [http://openrisc.io](http://openrisc.io) +* In addition to test vectors for each of the cores, some additional test_software, such as "hello world", have been added for reference +* Expanded testbench (details below) +* Bug fixes and general code cleanup [Additional details in the git commit history] -### Fixed -* iDFT test code fixed in cep_idft.cc +##v1.0 - Initial release (15 Aug 2017) #### Return to the root CEP [README](./README.md) \ No newline at end of file diff --git a/LICENSE.Components.md b/LICENSE.Components.md index 2691edf..aa15be5 100644 --- a/LICENSE.Components.md +++ b/LICENSE.Components.md @@ -185,3 +185,13 @@ License Terms : Copyright (c) 2018 Project Nayuki. (MIT License) * liability, whether in an action of contract, tort or otherwise, arising from, * out of or in connection with the Software or the use or other dealings in the * Software. + +Title : libgpiod-example +Source : https://github.com/starnight/libgpiod-example +CEP Directory : ./software/linux/gpiotest +License Description : BSD 3-Clause + +Title : Chipyard VC707 FPGA build target +Source : https://github.com/necst/chipyard-vc707 +CEP Directory : ./fpga/src/main/scala/vc707 +License Description : BSD 3-Clause diff --git a/README.md b/README.md index 5964227..044ed96 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ [//]: # (Copyright 2022 Massachusetts Institute of Technology) [//]: # (SPDX short identifier: BSD-2-Clause) -# Common Evaluation Platform v4.1 +# Common Evaluation Platform v4.2 [![DOI](https://zenodo.org/badge/108179132.svg)](https://zenodo.org/badge/latestdoi/108179132) [![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)](https://opensource.org/licenses/BSD-2-Clause) @@ -21,6 +21,8 @@ The Common Evaluation Platform (CEP) is an SoC design that contains only license-unencumbered, freely available components. The CEP includes a range of accelerator cores coupled with a key delivery mechanism, and parametrically-defined challenge modules which can be synthesized to support developmental testing. The implementation of the CEP includes a comprehensive verification environment to ensure modifications do not impede intended functionality. It is intended to be targeted to either an FPGA or ASIC implementation. +Please check the [CEP changelog](./CHANGELOG.CEP.md) for release history. + Beginning with CEP v4.0, the platform has been ported to the UCB Chipyard Framework. The original Chipyard Readme can be found [here](./README.Chipyard.md). Throughout the CEP READMEs, `` refers to the root directory of the cloned CEP repository. @@ -40,7 +42,7 @@ Instructions on how to modelsim, xcelium, and Vivado are beyond the scope of thi ## Setting up your environment -To build the CEP, several packages and toolsets must be installed and built. The typical steps are listed below. Additional information can be found in the Chipyard Documentation at https://chipyard.readthedocs.io/ +To build the CEP, several packages and toolsets must be installed and built. The typical steps are listed below. Additional information can be found in the Chipyard Documentation [here](https://chipyard.readthedocs.io/en/latest/Chipyard-Basics/index.html). A note about proxies: If your system is behind a proxy, you'll want to ensure your environment is properly configured. Exact details vary by system, but the proxy needs to be available to apt / yum, curl, and sbt (Simple Build Tool for Scala) @@ -58,9 +60,9 @@ If using RHEL7, you need to ensure gcc 7.x.x+ is installed. This can be found i * `./scripts/init-submodules-no-riscv-tools.sh` * `./scripts/init-fpga.sh` * Build the RISC-V Toolchain. - * Depending on your available hardware, you can expedite the build by executing `export MAKEFLAGS=-jN` prior to running the build script. N is the number of cores you can devote to the build + * Depending on your available hardware, you can expedite the build by executing `export MAKEFLAGS=-jN` prior to running the build script. N is the number of cores you can devote to the build. * `./scripts/build-toolchains.sh riscv-tools` -* The chipyard build needs make v4.x or later, which is not included in the default packages. Recommend building from source (https://ftp.gnu.org/gnu/make/). Once installed, you can force the version of make used using the following: `MAKE=/usr/local/bin/make ./scripts/build-toolchains.sh riscv-tools` +* RHEL7: The chipyard build needs make v4.x or later, which is not included in the default packages. Recommend building from source (https://ftp.gnu.org/gnu/make/). Once installed, you can force the version of make used using the following: `MAKE=/usr/local/bin/make ./scripts/build-toolchains.sh riscv-tools` * It is advisable to move the compiled toolchain outside of the current repo if you plan to have multiple CEP working directories. Complete directions are beyond the scope of this document, but they do include moving the `riscv-tools-install` directory and `env-riscv-tools.sh` file. Modification of the aforementioned file as well as `env.sh` will required for smooth operation * Sometimes the toolchain build may fail. One may need to run the build several times. * Once the toolchain is built, your want to source the new environment script: `source /env.sh`. @@ -87,52 +89,92 @@ Providing a complete directory structure is impractical, but some items are high ``` ### Building the CEP FPGA -In addition to those included with Chipyard, multiple Chipyard *SUB_PROJECTS* have been defined for the CEP. +Multiple Chipyard *SUB_PROJECTS* have been defined for the CEP when targetting FPGA Development boards. -For the Arty-A7 100T FPGA board, the `cep_arty100t` *SUB_PROJECT* has been defined in `/fpga/Makefile`. +These subprojects define the system configuration and are as follows: -With v4.0, the following FPGA configurations have been defined with the CEP-unique additions listed: +`cep_arty100t` - Arty100T Development Board +- 50 MHz Core Frequency +- 98% LUT Utilization +- 1x WithNBigCore +- CEP Registers +- AES Core +- Surrogate Root of Trust (SRoT) -`cep_arty100t` +`cep_vc707` - VC707 Development Board +- 100 MHz Core Frequency4 +- 11% LUT Utilization +- 1x WithNBigCore - CEP Registers -- 1 x AES Core +- AES Core - Surrogate Root of Trust (SRoT) -`cep_min_arty100t` +`cep_big_vc707` - VC707 Development Board +- 100 MHz Core Frequency +- 70% LUT Utilization +- 4x WithNBigCores +- CEP Registers +- AES Core +- DES3 Core +- FIR Core +- IIR Core +- DFT Core +- IDFT Core +- MD5 Core +- 4x GPS Cores +- 4x SHA-256 Cores +- RSA Core +- Surrogate Root of Trust + +`cep_vcu118` - VCU118 Development Board +- 100 MHz Core Frequency +- 5% LUT Utilization +- 1x WithNBigCore - CEP Registers +- AES Core +- Surrogate Root of Trust (SRoT) -Assuming the Vivado environment scripts have been sourced within your current shell, the following commands can be used to build and program the FPGA *SUB_PROJECT*. Programming requires that the digilent drivers have been installed and that you have a USB connection to the micro-USB port on the Arty100T. +Assuming the Vivado environment scripts have been sourced within your current shell, the following commands can be used to build and program the FPGA *SUB_PROJECT*. Programming requires that the digilent drivers have been installed and that you have a USB connection to the JTAG USB-port of you preffered FPGA board. Default CEP builds can be customized by following the instructions in the Chipyard documentation. -The Arty100T will configure from FLASH or JTAG based on the state of the MODE jumper. Additional information on the Arty board can be found [here](https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/). - +The FPGA boards will configure from FLASH or JTAG based on the state of the MODE jumper. Additional information can be found: +* Arty100T - [here](https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/). +* VC707 - [here](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html/). +* VCU118 - [here](https://www.xilinx.com/products/boards-and-kits/vcu118.html/). ``` cd /fpga -make # cep_arty100t is the default SUB_PROJECT +make SUB_PROJECT= -./program_arty100t_flash.sh - Create the MCS file & program the Arty100T FLASH. Power needs to be cycled or the *PROG* button needs to be asserted to reboot with the new configuration. +./program__flash.sh - Create the MCS file & program the development board's flash. Power needs to be cycled or the *PROG* button needs to be asserted to reboot with the new configuration. OR -./program_arty100t_jtag.sh - Program the FPGA via JTAG. System will automatically reset or you can use the *RESET* button. +./program__jtag.sh - Program the FPGA via JTAG. System will automatically reset or you can use the *RESET* button. ``` -### Building software for the CEP FPGA +### Building Bare Metal software for the CEP FPGA + +The Arty100T shares a single microUSB connector for JTAG and UART, while the VC707 and VCU118 have seperate ports for each. + +For the Arty100T, connect a Digilent SD or microSD PMOD board o connector JA. For the VCU118, connect the same to the PMOD connector on the right side of the board. The PMOD connectors can be ordered from Digikey, Digilent, or other distributors. -In additional to connecting USB to the Arty100T's microUSB port, a Digilent SD or microSD PMOD connected should be connected to connector JA. The PMOD connectors can be ordered from Digikey, Digilent, or other distributors. Additional information can be found here: (https://digilent.com/shop/pmod-sd-full-sized-sd-card-slot/ or https://digilent.com/shop/pmod-microsd-microsd-card-slot/). -It should be noted that the microUSB port uses an FTDI chip to provide both JTAG and UART functionality. Your system may differ, but typically the UART shows up as `/dev/ttyUSB0` or `/dev/ttyUSB1`. UART settings are 115200baud, 8N1 and should be visible to any terminal program. +As noted, for the Arty100T the microUSB port uses an FTDI chip to provide both JTAG and UART functionality. Your system may differ, but typically the UART shows up as `/dev/ttyUSB0` or `/dev/ttyUSB1`. UART settings are 115200baud, 8N1 and should be visible to any terminal program. Both HW and SW flow control should be disabled. -Once released from reset, the CEP's bootrom will read the baremetal executable from the SD card, copy it DDR memory, and then jump to that location and execute the program. +It is worth noting that *minicom* enables HW flow control by default. -An example UART output for the gpiotest is included below: +Once released from reset, the CEP's bootrom will read the baremetal executable from the SD card, copy it DDR memory, and then jump to that location and execute the program. The bootrom's default payload size is large enough for a linux boot. For bare metal executables, the payloads are typically much smaller. The payload size can be overriden at boot time by holding *BTN0* on the Arty100T or *SWN* on the VC707/VCU118 when the chip is released from reset. + +An example UART output for the baremetal gpiotest follows: ``` ---- Common Evaluation Platform v00000004.00000000 --- +--- Common Evaluation Platform v4.20 --- +--- Based on the UCB Chipyard Framework --- --- Copyright 2022 Massachusetts Institute of Technology --- ---- BootRom Image built on Jun 13 2022 07:22:08 --- +--- BootRom Image built on Aug 1 2022 12:41:36 --- + INIT CMD0 CMD8 @@ -140,48 +182,70 @@ ACMD41 CMD58 CMD16 CMD18 -LOADING 0x00080000 PAYLOAD -LOADING +LOADING 128kB PAYLOAD +.... BOOT ------------------- - RISC-V GPIO Test ------------------- +-------------------------- + RISC-V GPIO Test +-------------------------- + Built for VCU118 + Console Echo Enabled -switches = 00000000 -switches = 00000004 -switches = 00000005 -switches = 00000001 -switches = 00000000 +gpio = 00000010 +gpio = 00000000 +gpio = 00000020 +gpio = 00000000 +gpio = 00000080 +gpio = 00000000 +gpio = 00000040 +gpio = 00000000 +... ``` A developer may use baremetal software from the CEP cosimulation or the examples as provided in `/software/baremetal`. +The (micro)SD card needs to be partitioned as described in (https://chipyard.readthedocs.io/en/latest/Prototyping/VCU118.html#running-linux-on-vcu118-designs). Once partitioned, proceed to the next step. + In either case, it is important to note what device your (micro)SD card gets mapped to (e.g., `/dev/sdd`). Using `/sims/cep_cosim/testSuites/bareMetal/regTest` as an example, the following steps will build and load the executable onto the (micro)SD card. ``` cd /sims/cep_cosim/testSuites/bareMetal/regTest -make ENABLE_KPRINTF=1 riscv_wrapper <-- builds riscv_wrapper.img with console printf enabled -make DISK=/dev/sdd riscv_wrapper_sd_write <-- copies riscv_wrapper.img to /dev/sdd (subsitute with your device name) +make DISABLE_KPRINTF=0 riscv_wrapper <-- builds riscv_wrapper.img with console printf enabled +make DISK=/dev/sdd1 riscv_wrapper_sd_write <-- copies riscv_wrapper.img to partition /dev/sdd1 (subsitute with your partition name) ``` -In the above example, the bare metal regTest is build with the console printf function enabled. It is advised that you enable the addition of a carriage return in your chosen terminal program. +In the above example, the bare metal regTest is built with the console printf function enabled. The steps in `/software/baremetal/gpiotest` are slight different. ``` cd /software/baremetal/gpiotest -make DISK=/dev/sdd sd_write <-- copies gpiotest.img to /dev/sdd (subsitute with your device name) +make DISK=/dev/sdd1 sd_write <-- copies gpiotest.img to partition /dev/sdd1 (subsitute with your device name) ``` It is worth noting that the examples in `/software/baremetal` do not require the compilation of the all the cosimulation libraries, but as a result, will not have access to those support functions. -### CEP Co-Simulation +### Booting Linux +The CEP Arty100T/VC707/VCU118 builds has been verified to support a firemarshall-based linux build by following the default workload instructions [here](https://chipyard.readthedocs.io/en/latest/Prototyping/VCU118.html#running-linux-on-vcu118-designs). + +A couple of notes: +- The SD card must be partitioned as instructed +- Due to a bug in libguestfs on Ubuntu, the firemarshal build *may* fail. Ensure your current shell has active sudo permissions before running the build. I used a quick `sudo su`, exited the root shell, and then ran the build. +- Customization of the linux build will affect the resulting image size `/software/firemarshal/images/br-base-bin-nodisk-flat`. Ensure that `PAYLOAD_SIZE_B` in `/sims/cep_cosim/bootrom/sd.c` is sized to accomodated the image. + +### Linux Applications +You can install an example application in firemarshal's buildroot prior to building linux by running `make MAINPROGRAM= install` from /software/linux. Applications include `helloworld` and `gpiotest`. + +It is advisable to clean the buildroot build, should you change the configuration. This can accomplished by running `make clean` within `/software/firemarshal/boards/prototype/distros/br/buildroot/`. +If you ncurses-based gpiotest application crashes before cleanup, executing the `reset` command should restore terminal behavior. + +### CEP Co-Simulation For simulation using the CEP Co-Simulation environment, the `cep_cosim` and `cep_cosim_asic` *SUB_PROJECTS* are defined in `/variables.mk`. At this time, due to licensing constraints, the CEP ASIC build is not available as part of this repository. As a result, any attempt to build it will fail given that a multitude of files are missing. Instructions on the CEP Co-Simulation (including the Chipyard build) can be found [here](./sims/cep_cosim/README.md). @@ -189,8 +253,6 @@ Instructions on the CEP Co-Simulation (including the Chipyard build) can be foun ### Generated DSP code notes Due to licensing contraints, two of the DSP cores used during CEP development cannot be included in our repository. Instructions on generating all the cores can be found [here](./generators/mitll-blocks/src/main/resources/vsrc/dsp/README.md). -Please check the [CEP changelog](./CHANGELOG.CEP.md) for release history. - ## Errors? Ommissions? Questions? Please feel free to file a github issue which the CEP developers check frequently. @@ -204,7 +266,6 @@ As the CEP has been developed with input from many sources, multiple licenses ap * [Chipyard License](./LICENSE.md) * [SiFive License](./LICENSE.SiFive.md) - ## DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited. This material is based upon work supported by the Defense Advanced Research Projects Agency under Air Force Contract No. FA8702-15-D-0001. Any opinions, findings, conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Defense Advanced Research Projects Agency. diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst deleted file mode 100644 index ccf7eb3..0000000 --- a/docs/VLSI/Tutorial.rst +++ /dev/null @@ -1,167 +0,0 @@ -.. _tutorial: - -ASAP7 Tutorial -============== -The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. - -Project Structure ------------------ - -This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders: - -* Makefile, sim.mk, power.mk - - * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands. - -* build - - * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. - * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. - -* env.yml - - * A template file for tool environment configuration. Fill in the install and license server paths for your environment. - -* example-vlsi - - * Entry point to Hammer. Contains example placeholders for hooks. - -* example-asap7.yml, example-tools.yml - - * Hammer IR for this tutorial. - -* example-design.yml, example-nangate45.yml, example-tech.yml - - * Hammer IR not used for this tutorial but provided as templates. - -* generated-src - - * All of the elaborated Chisel and FIRRTL. - -* hammer, hammer--plugins, hammer--plugin - - * Core, tool, tech repositories. - -* view_gds.py - - * A convenience script to view a layout using gdstk or gdspy. Only use this for small layouts (i.e. smaller than the TinyRocketConfig example) since the gdstk-produced SVG will be too big and gdspy's GUI is very slow for large layouts! - -Prerequisites -------------- - -* Python 3.4+ -* numpy and `gdstk `__ or `gdspy `__ packages. Note: gdspy must be version 1.4. -* Genus, Innovus, Voltus, VCS, and Calibre licenses -* For ASAP7 specifically (`README `__ for more details): - - * First, download the `ASAP7 v1p7 PDK `__ (we recommend shallow-cloning or downloading an archive of the repository). Then, download the `encrypted Calibre decks tarball `__ tarball to a directory of choice (e.g. the root directory of the PDK) but do not extract it like the instructions say. The tech plugin is configured to extract the tarball into a cache directory for you. - * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. - -Initial Setup -------------- -In the Chipyard root, run: - -.. code-block:: shell - - ./scripts/init-vlsi.sh asap7 - -to pull the Hammer & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. - -Pull the Hammer environment into the shell: - -.. code-block:: shell - - cd vlsi - export HAMMER_HOME=$PWD/hammer - source $HAMMER_HOME/sourceme.sh - -Building the Design --------------------- -To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow: - -.. code-block:: shell - - make buildfile CONFIG=TinyRocketConfig - -The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. - -For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. - -Running the VLSI Flow ---------------------- - -example-vlsi -^^^^^^^^^^^^ -This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. - -example-asap7.yml -^^^^^^^^^^^^^^^^^ -This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. - -First, set ``technology.asap7.tarball_dir`` to the absolute path to the directory where the downloaded the ASAP7 Calibre deck tarball lives. If it is not in the PDK's root directory, then also set ``technology.asap7.pdk_install_dir`` and ``technology.asap7.stdcell_install_dir``. - -Synthesis -^^^^^^^^^ -.. code-block:: shell - - make syn CONFIG=TinyRocketConfig - -Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. - -Place-and-Route -^^^^^^^^^^^^^^^ -.. code-block:: shell - - make par CONFIG=TinyRocketConfig - -After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``. - -Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. - -Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. - -`gdspy` can be used to `view the final layout `__, but it is somewhat crude and slow (wait a few minutes for it to load): - -.. code-block:: shell - - ./view_gds.py build/chipyard.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds - -By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names. - -DRC & LVS -^^^^^^^^^ -To run DRC & LVS, and view the results in Calibre: - -.. code-block:: shell - - make drc CONFIG=TinyRocketConfig - ./build/drc-rundir/generated-scripts/view-drc - make lvs CONFIG=TinyRocketConfig - ./build/lvs-rundir/generated-scripts/view-lvs - -Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. -Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors. - -Simulation -^^^^^^^^^^ -Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation: - -.. code-block:: shell - - make sim-rtl CONFIG=TinyRocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple - -Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` targets, respectively. - -You can also append ``-debug`` and ``-debug-timing`` to the above sim targets, which will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. - -Power/Rail Analysis -^^^^^^^^^^^^^^^^^^^ -Post-P&R power and rail (IR drop) analysis is supported with Voltus: - -.. code-block:: shell - - make power-par CONFIG=TinyRocketConfig - -If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim--debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform. - -Note that power and rail analysis can also be run without gate-level simulation, but you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Only static and active (vectorless) power & IR drop will be reported. diff --git a/fpga/Makefile b/fpga/Makefile index af73a7a..2f4d0de 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -12,114 +12,67 @@ sim_dir=$(abspath .) # include shared variables ######################################################################################### -# Verify vivado is available +# Verify vivado is available, capture and display the version if it is... +ifeq "$(findstring clean,${MAKECMDGOALS})" "" ifeq (,$(shell which vivado)) $(error Vivado is not available. Please install and ensure the environment script is sourced.) -endif - -# Detect and +else VIVADO_VERSION := $(shell vivado -version | head -1 | grep -o -P '(?<=\s).*(?=\s)') $(info Vivado $(VIVADO_VERSION) detected.) +endif +endif # Set default SUB_PROJECT SUB_PROJECT ?= cep_arty100t -ifeq ($(SUB_PROJECT),vcu118) +# Bootrom targets are "cleared" for CEP FPGA targets, since +# build is controlled from within the chisel configuration +ifeq ($(SUB_PROJECT),cep_vcu118) SBT_PROJECT ?= fpga_platforms MODEL ?= VCU118FPGATestHarness VLOG_MODEL ?= VCU118FPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.vcu118 - CONFIG ?= RocketVCU118Config + CONFIG ?= RocketVCU118CEPConfig CONFIG_PACKAGE ?= chipyard.fpga.vcu118 GENERATOR_PACKAGE ?= chipyard TOP ?= ChipTop BOARD ?= vcu118 FPGA_BRAND ?= xilinx + SORT_SCRIPT := $(base_dir)/scripts/sort-blackbox.py + SORT_FILE := $(base_dir)/cep_sort.f + BOOTROM_TARGETS := endif -ifeq ($(SUB_PROJECT),bringup) - SBT_PROJECT ?= fpga_platforms - MODEL ?= BringupVCU118FPGATestHarness - VLOG_MODEL ?= BringupVCU118FPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup - CONFIG ?= RocketBringupConfig - CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup - GENERATOR_PACKAGE ?= chipyard - TOP ?= ChipTop - BOARD ?= vcu118 - FPGA_BRAND ?= xilinx -endif - -ifeq ($(SUB_PROJECT),arty) - SBT_PROJECT ?= fpga_platforms - MODEL ?= ArtyFPGATestHarness - VLOG_MODEL ?= ArtyFPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.arty - CONFIG ?= TinyRocketArtyConfig - CONFIG_PACKAGE ?= chipyard.fpga.arty - GENERATOR_PACKAGE ?= chipyard - TOP ?= ChipTop - BOARD ?= arty - FPGA_FAMILY ?= artix7 - FPGA_BRAND ?= xilinx -endif - -ifeq ($(SUB_PROJECT),artysim) - # TODO: Fix with Arty - SBT_PROJECT ?= fpga_platforms - MODEL ?= ArtyFPGATestHarness - VLOG_MODEL ?= ArtyFPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.arty - CONFIG ?= TinyRocketArtySimConfig - CONFIG_PACKAGE ?= chipyard.fpga.arty - GENERATOR_PACKAGE ?= chipyard - TB ?= ArtyTestDriver - TOP ?= ChipTop - BOARD ?= arty - FPGA_FAMILY ?= artix7 - FPGA_BRAND ?= xilinx -endif - -ifeq ($(SUB_PROJECT),arty100t) +# Bootrom targets are "cleared" for CEP FPGA targets, since +# build is controlled from within the chisel configuration +ifeq ($(SUB_PROJECT),cep_arty100t) SBT_PROJECT ?= fpga_platforms MODEL ?= Arty100TFPGATestHarness VLOG_MODEL ?= Arty100TFPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.arty100t - CONFIG ?= RocketArty100TConfig - CONFIG_PACKAGE ?= chipyard.fpga.arty100t - GENERATOR_PACKAGE ?= chipyard - TOP ?= ChipTop - BOARD ?= arty_a7_100 - FPGA_BRAND ?= xilinx -endif - -ifeq ($(SUB_PROJECT),arty100tsim) - SBT_PROJECT ?= fpga_platforms - MODEL ?= Arty100TFPGASimTestHarness - VLOG_MODEL ?= Arty100TFPGASimTestHarness - MODEL_PACKAGE ?= chipyard.fpga.arty100t - CONFIG ?= RocketArty100TSimConfig + CONFIG ?= RocketArty100TCEPConfig CONFIG_PACKAGE ?= chipyard.fpga.arty100t GENERATOR_PACKAGE ?= chipyard - TB ?= Arty100TTestDriver TOP ?= ChipTop BOARD ?= arty_a7_100 - FPGA_FAMILY ?= artix7 FPGA_BRAND ?= xilinx + SORT_SCRIPT := $(base_dir)/scripts/sort-blackbox.py + SORT_FILE := $(base_dir)/cep_sort.f + BOOTROM_TARGETS := endif # Bootrom targets are "cleared" for CEP FPGA targets, since # build is controlled from within the chisel configuration -ifeq ($(SUB_PROJECT),cep_arty100t) +ifeq ($(SUB_PROJECT),cep_vc707) SBT_PROJECT ?= fpga_platforms - MODEL ?= Arty100TFPGATestHarness - VLOG_MODEL ?= Arty100TFPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.arty100t - CONFIG ?= RocketArty100TCEPConfig - CONFIG_PACKAGE ?= chipyard.fpga.arty100t + MODEL ?= VC707FPGATestHarness + VLOG_MODEL ?= VC707FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vc707 + CONFIG ?= RocketVC707CEPConfig + CONFIG_PACKAGE ?= chipyard.fpga.vc707 GENERATOR_PACKAGE ?= chipyard TOP ?= ChipTop - BOARD ?= arty_a7_100 + BOARD ?= vc707 FPGA_BRAND ?= xilinx SORT_SCRIPT := $(base_dir)/scripts/sort-blackbox.py SORT_FILE := $(base_dir)/cep_sort.f @@ -128,21 +81,26 @@ endif # Bootrom targets are "cleared" for CEP FPGA targets, since # build is controlled from within the chisel configuration -ifeq ($(SUB_PROJECT),cep_min_arty100t) +ifeq ($(SUB_PROJECT),cep_big_vc707) SBT_PROJECT ?= fpga_platforms - MODEL ?= Arty100TFPGATestHarness - VLOG_MODEL ?= Arty100TFPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.arty100t - CONFIG ?= RocketArty100TMinCEPConfig - CONFIG_PACKAGE ?= chipyard.fpga.arty100t + MODEL ?= VC707FPGATestHarness + VLOG_MODEL ?= VC707FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vc707 + CONFIG ?= RocketVC707BigCEPConfig + CONFIG_PACKAGE ?= chipyard.fpga.vc707 GENERATOR_PACKAGE ?= chipyard TOP ?= ChipTop - BOARD ?= arty_a7_100 + BOARD ?= vc707 FPGA_BRAND ?= xilinx SORT_SCRIPT := $(base_dir)/scripts/sort-blackbox.py SORT_FILE := $(base_dir)/cep_sort.f BOOTROM_TARGETS := endif + +ifeq ($(SBT_PROJECT),) +$(error Invalid SUB_PROJECT) +endif + include $(base_dir)/variables.mk # default variables to build the arty example @@ -317,3 +275,5 @@ sim-fpga: $(sim) .PHONY: clean clean: cep_clean rm -rf $(gen_dir) + rm -f *.log + rm -f *.jou \ No newline at end of file diff --git a/fpga/fpga-shells b/fpga/fpga-shells deleted file mode 160000 index f9fb9fd..0000000 --- a/fpga/fpga-shells +++ /dev/null @@ -1 +0,0 @@ -Subproject commit f9fb9fd338e5fca2ff5116b1d01506c424280d70 diff --git a/fpga/program_arty100t_flash.tcl b/fpga/program_arty100t_flash.tcl index 9fa0d6b..ad45ca9 100644 --- a/fpga/program_arty100t_flash.tcl +++ b/fpga/program_arty100t_flash.tcl @@ -4,11 +4,11 @@ #// #// File : program_arty100t_flash.tcl #// Project : Common Evaluation Platform (CEP) -#// Description : TCL script for automatic programming of Arty100t CEP build -#// Notes : This TCL script assumes the arty100t CEP build target +#// Description : TCL script for automatic programming of Arty100t CEP build via JTAG +#// Notes : #//-------------------------------------------------------------------------------------- -# Script to program the Arty A7 memory configuration device +# Script to program the configuration device open_hw_manager connect_hw_server open_hw_target @@ -16,7 +16,7 @@ open_hw_target # Create MCS file write_cfgmem -format mcs -size 16 -interface SPIx4 -loadbit {up 0x00000000 "./generated-src/chipyard.fpga.arty100t.Arty100TFPGATestHarness.RocketArty100TCEPConfig/obj/Arty100TFPGATestHarness.bit" } -force -file "./generated-src/chipyard.fpga.arty100t.Arty100TFPGATestHarness.RocketArty100TCEPConfig/obj/Arty100TFPGATestHarness.mcs" -# Select Arty A7 board via JTAG +# Select and program the Flash device create_hw_cfgmem -hw_device [lindex [get_hw_devices xc7a100t_0] 0] [lindex [get_cfgmem_parts {s25fl128sxxxxxx0-spi-x1_x2_x4}] 0] set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]] set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]] @@ -24,8 +24,6 @@ set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [ge set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]] set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]] refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0] - -# Select and program the Flash device set_property PROGRAM.FILES [list "./generated-src/chipyard.fpga.arty100t.Arty100TFPGATestHarness.RocketArty100TCEPConfig/obj/Arty100TFPGATestHarness.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]] set_property PROGRAM.PRM_FILE {./generated-src/chipyard.fpga.arty100t.Arty100TFPGATestHarness.RocketArty100TCEPConfig/obj/Arty100TFPGATestHarness.prm} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]] set_property PROGRAM.BPI_RS_PINS {none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] diff --git a/fpga/program_arty100t_jtag.tcl b/fpga/program_arty100t_jtag.tcl index d741617..eec9d52 100644 --- a/fpga/program_arty100t_jtag.tcl +++ b/fpga/program_arty100t_jtag.tcl @@ -4,8 +4,8 @@ #// #// File : program_arty100t_jtag.tcl #// Project : Common Evaluation Platform (CEP) -#// Description : TCL script for automatic programming of Arty100t CEP build -#// Notes : This TCL script assumes the arty100t CEP build target +#// Description : TCL script for automatic programming of Arty100t CEP build via JTA +#// Notes : #//-------------------------------------------------------------------------------------- open_hw_manager connect_hw_server diff --git a/fpga/program_vc707_flash.sh b/fpga/program_vc707_flash.sh new file mode 100755 index 0000000..1429b32 --- /dev/null +++ b/fpga/program_vc707_flash.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +#//-------------------------------------------------------------------------------------- +#// Copyright 2022 Massachusets Institute of Technology +#// SPDX short identifier: BSD-2-Clause +#// +#// File : program_vc707_flash.sh +#// Project : Common Evaluation Platform (CEP) +#// Description : Shell script for invoking program_vc707_flash.tcl +#// Notes : exit script if any command fails +#//-------------------------------------------------------------------------------------- +set -e +set -o pipefail + +vivado -mode tcl -source program_vc707_flash.tcl diff --git a/fpga/program_vc707_flash.tcl b/fpga/program_vc707_flash.tcl new file mode 100644 index 0000000..93a4c27 --- /dev/null +++ b/fpga/program_vc707_flash.tcl @@ -0,0 +1,40 @@ +#//-------------------------------------------------------------------------------------- +#// Copyright 2022 Massachusets Institute of Technology +#// SPDX short identifier: BSD-2-Clause +#// +#// File : program_vc707_flash.tcl +#// Project : Common Evaluation Platform (CEP) +#// Description : TCL script for automatic programming of VC707 CEP build via FLASH +#// Notes : +#//-------------------------------------------------------------------------------------- + +# Script to program the memory configuration device +open_hw_manager +connect_hw_server +open_hw_target + +# Create MCS file +write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "./generated-src/chipyard.fpga.vc707.VC707FPGATestHarness.RocketVC707CEPConfig/obj/VC707FPGATestHarness.bit" } -force -file "./generated-src/chipyard.fpga.vc707.VC707FPGATestHarness.RocketVC707CEPConfig/obj/VC707FPGATestHarness.mcs" + +# Select and program the Flash device +create_hw_cfgmem -hw_device [lindex [get_hw_devices xc7vx485t_0] 0] [lindex [get_cfgmem_parts {mt28gu01gaax1e-bpi-x16}] 0] +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7vx485t_0] 0]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7vx485t_0] 0]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7vx485t_0] 0]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7vx485t_0] 0]] +set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7vx485t_0] 0]] +refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0] +set_property PROGRAM.FILES [list "./generated-src/chipyard.fpga.vc707.VC707FPGATestHarness.RocketVC707CEPConfig/obj/VC707FPGATestHarness.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]] +set_property PROGRAM.PRM_FILE {./generated-src/chipyard.fpga.vc707.VC707FPGATestHarness.RocketVC707CEPConfig/obj/VC707FPGATestHarness.prm} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]] +set_property PROGRAM.BPI_RS_PINS {none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +startgroup +if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; }; +program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +close_hw_manager +quit \ No newline at end of file diff --git a/fpga/program_vc707_jtag.sh b/fpga/program_vc707_jtag.sh new file mode 100755 index 0000000..2bd8e59 --- /dev/null +++ b/fpga/program_vc707_jtag.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +#//-------------------------------------------------------------------------------------- +#// Copyright 2022 Massachusets Institute of Technology +#// SPDX short identifier: BSD-2-Clause +#// +#// File : program_vc707_jtag.sh +#// Project : Common Evaluation Platform (CEP) +#// Description : Shell script for invoking program_vc707_jtag.tcl +#// Notes : exit script if any command fails +#//-------------------------------------------------------------------------------------- +set -e +set -o pipefail + +vivado -mode tcl -source program_vc707_jtag.tcl diff --git a/fpga/program_vc707_jtag.tcl b/fpga/program_vc707_jtag.tcl new file mode 100644 index 0000000..fa8ebe2 --- /dev/null +++ b/fpga/program_vc707_jtag.tcl @@ -0,0 +1,16 @@ +#//-------------------------------------------------------------------------------------- +#// Copyright 2022 Massachusets Institute of Technology +#// SPDX short identifier: BSD-2-Clause +#// +#// File : program_vc707_jtag.tcl +#// Project : Common Evaluation Platform (CEP) +#// Description : TCL script for automatic programming of VC707 CEP build via JTAG +#// Notes : +#//-------------------------------------------------------------------------------------- +open_hw_manager +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {./generated-src/chipyard.fpga.vc707.VC707FPGATestHarness.RocketVC707CEPConfig/obj/VC707FPGATestHarness.bit} [get_hw_devices xc7vx485t_0] +program_hw_devices +close_hw_manager +quit diff --git a/fpga/program_vcu118_flash.sh b/fpga/program_vcu118_flash.sh new file mode 100755 index 0000000..5898347 --- /dev/null +++ b/fpga/program_vcu118_flash.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +#//-------------------------------------------------------------------------------------- +#// Copyright 2022 Massachusets Institute of Technology +#// SPDX short identifier: BSD-2-Clause +#// +#// File : program_vcu118_flash.sh +#// Project : Common Evaluation Platform (CEP) +#// Description : Shell script for invoking program_vcu118_flash.tcl +#// Notes : exit script if any command fails +#//-------------------------------------------------------------------------------------- +set -e +set -o pipefail + +vivado -mode tcl -source program_vcu118_flash.tcl diff --git a/fpga/program_vcu118_flash.tcl b/fpga/program_vcu118_flash.tcl new file mode 100644 index 0000000..1f35105 --- /dev/null +++ b/fpga/program_vcu118_flash.tcl @@ -0,0 +1,42 @@ +#//-------------------------------------------------------------------------------------- +#// Copyright 2022 Massachusets Institute of Technology +#// SPDX short identifier: BSD-2-Clause +#// +#// File : program_vcu118_flash.tcl +#// Project : Common Evaluation Platform (CEP) +#// Description : TCL script for automatic programming of VCU118 CEP build +#// Notes : T +#//-------------------------------------------------------------------------------------- + +# Script to program the memory configuration device +open_hw_manager +connect_hw_server +open_hw_target + +# Create MCS file +write_cfgmem -format mcs -size 128 -interface SPIx8 -loadbit {up 0x00000000 "./generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.RocketVCU118CEPConfig/obj/VCU118FPGATestHarness.bit" } -force -file "./generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.RocketVCU118CEPConfig/obj/VCU118FPGATestHarness.mcs" + +# Select and program the Flash device +current_hw_device [get_hw_devices xcvu9p_0] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0] +create_hw_cfgmem -hw_device [lindex [get_hw_devices xcvu9p_0] 0] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0] +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.FILES [list "./generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.RocketVCU118CEPConfig/obj/VCU118FPGATestHarness_primary.mcs" "./generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.RocketVCU118CEPConfig/obj/VCU118FPGATestHarness_secondary.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.PRM_FILES [list "./generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.RocketVCU118CEPConfig/obj/VCU118FPGATestHarness_primary.prm" "./generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.RocketVCU118CEPConfig/obj/VCU118FPGATestHarness_secondary.prm" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +startgroup +create_hw_bitstream -hw_device [lindex [get_hw_devices xcvu9p_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xcvu9p_0] 0]]; program_hw_devices [lindex [get_hw_devices xcvu9p_0] 0]; refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0]; +program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcvu9p_0] 0]] +close_hw_manager +quit \ No newline at end of file diff --git a/fpga/program_vcu118_jtag.sh b/fpga/program_vcu118_jtag.sh new file mode 100755 index 0000000..ffc9ddb --- /dev/null +++ b/fpga/program_vcu118_jtag.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +#//-------------------------------------------------------------------------------------- +#// Copyright 2022 Massachusets Institute of Technology +#// SPDX short identifier: BSD-2-Clause +#// +#// File : program_vcu118_jtag.sh +#// Project : Common Evaluation Platform (CEP) +#// Description : Shell script for invoking program_vcu118_jtag.tcl +#// Notes : exit script if any command fails +#//-------------------------------------------------------------------------------------- +set -e +set -o pipefail + +vivado -mode tcl -source program_vcu118_jtag.tcl diff --git a/fpga/program_vcu118_jtag.tcl b/fpga/program_vcu118_jtag.tcl new file mode 100644 index 0000000..951d465 --- /dev/null +++ b/fpga/program_vcu118_jtag.tcl @@ -0,0 +1,16 @@ +#//-------------------------------------------------------------------------------------- +#// Copyright 2022 Massachusets Institute of Technology +#// SPDX short identifier: BSD-2-Clause +#// +#// File : program_vcu118_jtag.tcl +#// Project : Common Evaluation Platform (CEP) +#// Description : TCL script for automatic programming of the VCU118 CEP build via JTAG +#// Notes : +#//-------------------------------------------------------------------------------------- +open_hw_manager +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {./generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.RocketVCU118CEPConfig/obj/VCU118FPGATestHarness.bit} [get_hw_devices xcvu9p_0] +program_hw_devices +close_hw_manager +quit diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/Makefile b/fpga/src/main/resources/arty100t/cep_sdboot/Makefile index ae7aecd..f48ec6b 100644 --- a/fpga/src/main/resources/arty100t/cep_sdboot/Makefile +++ b/fpga/src/main/resources/arty100t/cep_sdboot/Makefile @@ -6,22 +6,22 @@ REPO_ROOT_DIR := $(shell git rev-parse --show-toplevel) ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) BUILD_DIR := $(ROOT_DIR)/build -CC=$(RISCV)/bin/riscv64-unknown-elf-gcc -OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy -OBJDUMP=$(RISCV)/bin/riscv64-unknown-elf-objdump -CFLAGS=-march=rv64ima -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles -CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 -CFLAGS+= -I $(ROOT_DIR)/include -I. -LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds - -SDC_SOURCE := $(REPO_ROOT_DIR)/sims/cep_cosim/bootrom/sd.c +CC =$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY =$(RISCV)/bin/riscv64-unknown-elf-objcopy +OBJDUMP =$(RISCV)/bin/riscv64-unknown-elf-objdump +CFLAGS = -mcmodel=medany -O2 -Wall -fno-common -fno-builtin-printf -fno-builtin-puts +CFLAGS += -I $(ROOT_DIR)/include -I. +CFLAGS += -mabi=lp64 -march=rv64ima +CFLAGS += -DENTROPY=0 -DNONSMP_HART=0 +LFLAGS = -static -nostdlib -nostartfiles -T sdboot.elf.lds +SDSOURCE = ${REPO_ROOT_DIR}/sims/cep_cosim/bootrom/sd.c default: elf bin dump elf := $(BUILD_DIR)/sdboot.elf -$(elf): head.S kprintf.c $(SDC_SOURCE) +$(elf): head.S ${SDSOURCE} kprintf.c syscalls_bootrom.c mkdir -p $(BUILD_DIR) - $(CC) $(CFLAGS) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S $(SDC_SOURCE) kprintf.c + $(CC) $(CFLAGS) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S ${SDSOURCE} kprintf.c syscalls_bootrom.c .PHONY: elf elf: $(elf) diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/common.h b/fpga/src/main/resources/arty100t/cep_sdboot/common.h deleted file mode 100644 index ccb9cd3..0000000 --- a/fpga/src/main/resources/arty100t/cep_sdboot/common.h +++ /dev/null @@ -1,10 +0,0 @@ -// See LICENSE.Sifive for license details. -#ifndef _SDBOOT_COMMON_H -#define _SDBOOT_COMMON_H - -#ifndef PAYLOAD_DEST - #define PAYLOAD_DEST MEMORY_MEM_ADDR -#endif - - -#endif diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/head.S b/fpga/src/main/resources/arty100t/cep_sdboot/head.S index c6653f7..f11fcbc 100644 --- a/fpga/src/main/resources/arty100t/cep_sdboot/head.S +++ b/fpga/src/main/resources/arty100t/cep_sdboot/head.S @@ -1,19 +1,18 @@ // See LICENSE.Sifive for license details. #include #include -#include "common.h" .section .text.init .option norvc .globl _prog_start _prog_start: smp_pause(s1, s2) - li sp, (PAYLOAD_DEST + 0xffff000) + li sp, (MEMORY_MEM_ADDR + 0xffff000) call main smp_resume(s1, s2) csrr a0, mhartid // hartid for next level bootloader la a1, dtb // dtb address for next level bootloader - li s1, PAYLOAD_DEST + li s1, MEMORY_MEM_ADDR jr s1 .section .dtb diff --git a/sims/cep_cosim/drivers/bare/encoding.h b/fpga/src/main/resources/arty100t/cep_sdboot/include/encoding.h similarity index 100% rename from sims/cep_cosim/drivers/bare/encoding.h rename to fpga/src/main/resources/arty100t/cep_sdboot/include/encoding.h diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/include/kprintf.h b/fpga/src/main/resources/arty100t/cep_sdboot/include/kprintf.h new file mode 100644 index 0000000..2733e2d --- /dev/null +++ b/fpga/src/main/resources/arty100t/cep_sdboot/include/kprintf.h @@ -0,0 +1,28 @@ +// See LICENSE.Sifive for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +#define UART_RXEMPTY (1 << 31) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + + +void kputc(int c); +int kgetc(void); +void kputs(const char *); + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/include/platform.h b/fpga/src/main/resources/arty100t/cep_sdboot/include/platform.h index e322c3b..50039d2 100644 --- a/fpga/src/main/resources/arty100t/cep_sdboot/include/platform.h +++ b/fpga/src/main/resources/arty100t/cep_sdboot/include/platform.h @@ -1,4 +1,13 @@ -// See LICENSE for license details. +//------------------------------------------------------------------------------------- +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: platform.h +// Program: Common Evaluation Platform (CEP) +// Description: +// Notes: This version has a 1GB main memory size and 1 core +// +//-------------------------------------------------------------------------------------- #ifndef _CHIPYARD_PLATFORM_H #define _CHIPYARD_PLATFORM_H diff --git a/sims/cep_cosim/drivers/bare/util.h b/fpga/src/main/resources/arty100t/cep_sdboot/include/util.h similarity index 100% rename from sims/cep_cosim/drivers/bare/util.h rename to fpga/src/main/resources/arty100t/cep_sdboot/include/util.h diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/kprintf.c b/fpga/src/main/resources/arty100t/cep_sdboot/kprintf.c index 3e3f218..bbb47e8 100644 --- a/fpga/src/main/resources/arty100t/cep_sdboot/kprintf.c +++ b/fpga/src/main/resources/arty100t/cep_sdboot/kprintf.c @@ -2,74 +2,42 @@ #include #include #include - #include "kprintf.h" -static inline void _kputs(const char *s) +void kputc(int c) { - char c; - for (; (c = *s) != '\0'; s++) - kputc(c); +#ifndef DISABLE_KPRINTF + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); + while ((int32_t)(*tx) < 0); + *tx = (c & 0xFF); +#endif } -void kputs(const char *s) +int kgetc(void) { - _kputs(s); - kputc('\r'); - kputc('\n'); +#ifndef DISABLE_KPRINTF + uint32_t ch; + volatile uint32_t *rx = ®32(uart, UART_REG_RXFIFO); + ch = *rx; + + if ((uint32_t)(ch & UART_RXEMPTY)) { + return -1; + } else { + return(ch & 0x0ff); + } +#else + return -1; +#endif } -void kprintf(const char *fmt, ...) +void kputs(const char *s) { - va_list vl; - bool is_format, is_long, is_char; - char c; - - va_start(vl, fmt); - is_format = false; - is_long = false; - is_char = false; - while ((c = *fmt++) != '\0') { - if (is_format) { - switch (c) { - case 'l': - is_long = true; - continue; - case 'h': - is_char = true; - continue; - case 'x': { - unsigned long n; - long i; - if (is_long) { - n = va_arg(vl, unsigned long); - i = (sizeof(unsigned long) << 3) - 4; - } else { - n = va_arg(vl, unsigned int); - i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; - } - for (; i >= 0; i -= 4) { - long d; - d = (n >> i) & 0xF; - kputc(d < 10 ? '0' + d : 'a' + d - 10); - } - break; - } - case 's': - _kputs(va_arg(vl, const char *)); - break; - case 'c': - kputc(va_arg(vl, int)); - break; - } - is_format = false; - is_long = false; - is_char = false; - } else if (c == '%') { - is_format = true; - } else { - kputc(c); - } - } - va_end(vl); -} + char c; + while (*s != '\0') { + c = *s; + kputc((int) c); + s++; + } + kputc('\r'); + kputc('\n'); +} \ No newline at end of file diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/kprintf.h b/fpga/src/main/resources/arty100t/cep_sdboot/kprintf.h deleted file mode 100644 index a7a9486..0000000 --- a/fpga/src/main/resources/arty100t/cep_sdboot/kprintf.h +++ /dev/null @@ -1,49 +0,0 @@ -// See LICENSE.Sifive for license details. -#ifndef _SDBOOT_KPRINTF_H -#define _SDBOOT_KPRINTF_H - -#include -#include - -#define REG32(p, i) ((p)[(i) >> 2]) - -#ifndef UART_CTRL_ADDR - #ifndef UART_NUM - #define UART_NUM 0 - #endif - - #define _CONCAT3(A, B, C) A ## B ## C - #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) - #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) -#endif -static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); - -static inline void kputc(char c) -{ - volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); -#ifdef __riscv_atomic - int32_t r; - do { - __asm__ __volatile__ ( - "amoor.w %0, %2, %1\n" - : "=r" (r), "+A" (*tx) - : "r" (c)); - } while (r < 0); -#else - while ((int32_t)(*tx) < 0); - *tx = c; -#endif -} - -extern void kputs(const char *); -extern void kprintf(const char *, ...); - -#ifdef DEBUG -#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) -#define dputs(s) kputs((s)) -#else -#define dprintf(s, ...) do { } while (0) -#define dputs(s) do { } while (0) -#endif - -#endif /* _SDBOOT_KPRINTF_H */ diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/sd.c b/fpga/src/main/resources/arty100t/cep_sdboot/sd.c deleted file mode 100644 index df64384..0000000 --- a/fpga/src/main/resources/arty100t/cep_sdboot/sd.c +++ /dev/null @@ -1,317 +0,0 @@ -//------------------------------------------------------------------------------------- -// Copyright 2022 Massachusets Institute of Technology -// SPDX short identifier: BSD-2-Clause -// -// File Name: sd.c -// Program: Common Evaluation Platform (CEP) -// Description: SPI and UART initialization code for the CEP Bootrom -// Notes: Specification referenced is: -// "SD Specifications Part 1 Physical Layer Simplified Specification 8.00, September 23, 2020" -// -// - Updated ACMD41 processing to read all five bytes of the R3 response and check -// the busy bit in the response per specification Figure 4-4 (Response bit 39) -// - Removed 34-byte BBL offset in sd_copy (now set to 0) -//-------------------------------------------------------------------------------------- - -// See LICENSE.Sifive for license details. -#include -#include - -#define DEBUG -#include "kprintf.h" - -// Total payload in B -#define PAYLOAD_SIZE_B (1 << 19) // 512kB - -// A sector is 512 bytes, so (1 << 11) * 512B = 1 MiB -#define SECTOR_SIZE_B 512 - -// Payload size in # of sectors -#define PAYLOAD_SIZE (PAYLOAD_SIZE_B / SECTOR_SIZE_B) - -// The sector at which the BBL partition starts -#define BBL_PARTITION_START_SECTOR 34 - -#ifndef TL_CLK -#error Must define TL_CLK -#endif - -#define F_CLK TL_CLK - -#define REG64(p, i) ((p)[(i) >> 3]) - -static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); -static volatile uint64_t * const cepregs = (void *)(CEPREGS_ADDR); - -static inline uint8_t spi_xfer(uint8_t d) -{ - int32_t r; - - REG32(spi, SPI_REG_TXFIFO) = d; - do { - r = REG32(spi, SPI_REG_RXFIFO); - } while (r < 0); - return r; -} - -static inline uint8_t sd_dummy(void) -{ - return spi_xfer(0xFF); -} - -static uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) -{ - unsigned long n; - uint8_t r; - - REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_HOLD; - sd_dummy(); - spi_xfer(cmd); - spi_xfer(arg >> 24); - spi_xfer(arg >> 16); - spi_xfer(arg >> 8); - spi_xfer(arg); - spi_xfer(crc); - - n = 1000; - do { - r = sd_dummy(); - if (!(r & 0x80)) { - goto done; - } - } while (--n > 0); - kputs("sd_cmd: timeout"); -done: - return r; -} - -static inline void sd_cmd_end(void) -{ - sd_dummy(); - REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO; -} - - -static void sd_poweron(void) -{ - long i; - REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); - REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF; - for (i = 10; i > 0; i--) { - sd_dummy(); - } - REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO; -} - -static int sd_cmd0(void) -{ - int rc; - kputs("CMD0"); - rc = (sd_cmd(0x40, 0, 0x95) != 0x01); - sd_cmd_end(); - return rc; -} - -static int sd_cmd8(void) -{ - int rc; - kputs("CMD8"); - // Per section 7.3.2.6 of the specification, the card should be in the IDLE state and - // running the initialization process - rc = (sd_cmd(0x48, 0x000001AA, 0x87) != 0x01); - sd_dummy(); /* command version; reserved */ - sd_dummy(); /* reserved */ - rc |= ((sd_dummy() & 0xF) != 0x1); /* voltage */ - rc |= (sd_dummy() != 0xAA); /* check pattern */ - sd_cmd_end(); - return rc; -} - -// Printting of cmd55 send status has been removed since the number varies greatly and -// can result in a lot of scrolling -static void sd_cmd55(void) -{ - sd_cmd(0x77, 0, 0x65); - sd_cmd_end(); -} - -static int sd_acmd41(void) -{ - uint8_t r; - dputs("ACMD41"); - do { - sd_cmd55(); - r = sd_cmd(0x69, 0x40000000, 0x77); /* HCS = 1 */ - } while (r == 0x01); - return (r != 0x00); -} - -static int sd_cmd58(void) -{ - int rc; - kputs("CMD58"); - rc = (sd_cmd(0x7A, 0, 0xFD) != 0x00); - rc |= ((sd_dummy() & 0x80) != 0x80); /* Power up status */ - sd_dummy(); - sd_dummy(); - sd_dummy(); - sd_cmd_end(); - return rc; -} - -// Set block length set to 512 bytes -static int sd_cmd16(void) -{ - int rc; - kputs("CMD16"); - rc = (sd_cmd(0x50, 0x200, 0x15) != 0x00); - sd_cmd_end(); - return rc; -} - -static uint16_t crc16_round(uint16_t crc, uint8_t data) { - crc = (uint8_t)(crc >> 8) | (crc << 8); - crc ^= data; - crc ^= (uint8_t)(crc >> 4) & 0xf; - crc ^= crc << 12; - crc ^= (crc & 0xff) << 5; - return crc; -} - -#define SPIN_SHIFT 6 -#define SPIN_UPDATE(i) (!((i) & ((1 << SPIN_SHIFT)-1))) -#define SPIN_INDEX(i) (((i) >> SPIN_SHIFT) & 0x3) - -static const char spinner[] = { '-', '/', '|', '\\' }; - -// Copy SD contents to main memory -static int sd_copy(void) -{ - volatile uint8_t *p = (void *)(MEMORY_MEM_ADDR); - long i = PAYLOAD_SIZE; - int rc = 0; - - kputs("CMD18"); - - // Performing multiplication here in the event that PAYLOAD_SIZE is - // overriden in simulation - kprintf("LOADING 0x%x PAYLOAD\r\n", SECTOR_SIZE_B * i); - kprintf("LOADING "); - - // Begin a multi-cycle read - REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); - if (sd_cmd(0x52, 0, 0xE1) != 0x00) { - sd_cmd_end(); - return 1; - } - do { - uint16_t crc, crc_exp; - long n; - - crc = 0; - n = SECTOR_SIZE_B; - - // Wait for the start token - while (sd_dummy() != 0xFE); - - // Copy a block/sector of data - do { - uint8_t x = sd_dummy(); - *p++ = x; - crc = crc16_round(crc, x); - } while (--n > 0); - - crc_exp = ((uint16_t)sd_dummy() << 8); - crc_exp |= sd_dummy(); - - if (crc != crc_exp) { - kputs("CRC mismatch"); - rc = 1; - break; - } - - if (SPIN_UPDATE(i)) { - kputc('\b'); - kputc(spinner[SPIN_INDEX(i)]); - } - } while (--i > 0); - sd_cmd_end(); - - sd_cmd(0x4C, 0, 0x01); - sd_cmd_end(); - kputs("\b "); - return rc; -} - -// Main Function -int main(void) -{ - - // The default Chipyard VCU118/Arty100t bootrom has been modified - // to read the CEP W0 Scratch Register to alter functionality. By default, - // the following is enabled: - // - Print Welcome message out the UART - // - Enable SD Boot - // - // If bits 1 and 0 are set, the UART Welcome message will be disabled - // If bits 2 and 3 are set, SD Boot will be disabled - // - uint64_t scratch_reg = 0; - uint64_t version_reg = 0; - uint8_t major_version = 0; - uint8_t minor_version = 0; - - version_reg = REG64(cepregs, CEPREGS_VERSION); - major_version = (version_reg >> 48) & 0xFF; - minor_version = (version_reg >> 56) & 0xFF; - - // Enable the UART - REG32(uart, UART_REG_TXCTRL) = UART_TXEN; - - // Enable the welcome message if the two LSBits in CEP Scratch Register are NOT set - kprintf("--- Common Evaluation Platform v%x.%x ---\r\n", major_version, minor_version); - kprintf("--- Copyright 2022 Massachusetts Institute of Technology ---\r\n"); - kprintf("--- BootRom Image built on %s %s ---\r\n",__DATE__,__TIME__); - - // Enable SD Boot if bits 3 & 2 of the CEP Scratch register are NOT set - kputs("INIT"); - - sd_poweron(); - - if (sd_cmd0()) { - kputs("CMD0 ERROR"); - return 1; - } - - if (sd_cmd8()) { - kputs("CMD8 ERROR"); - return 1; - } - - if (sd_acmd41()) { - kputs("ACMD41 ERROR"); - return 1; - } - - if (sd_cmd58()) { - kputs("CMD58 ERROR"); - return 1; - } - - if (sd_cmd16()) { - kputs("CMD16 ERROR"); - return 1; - } - - if (sd_copy()) { - kputs("SDCOPY ERROR"); - return 1; - } - - kputs("BOOT"); - - // Force instruction and data stream synchronization - __asm__ __volatile__ ("fence.i" : : : "memory"); - - return 0; -} diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/linker/sdboot.elf.lds b/fpga/src/main/resources/arty100t/cep_sdboot/sdboot.elf.lds similarity index 100% rename from fpga/src/main/resources/arty100t/cep_sdboot/linker/sdboot.elf.lds rename to fpga/src/main/resources/arty100t/cep_sdboot/sdboot.elf.lds diff --git a/fpga/src/main/resources/arty100t/cep_sdboot/syscalls_bootrom.c b/fpga/src/main/resources/arty100t/cep_sdboot/syscalls_bootrom.c new file mode 100644 index 0000000..c5c970c --- /dev/null +++ b/fpga/src/main/resources/arty100t/cep_sdboot/syscalls_bootrom.c @@ -0,0 +1,438 @@ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: syscalls_bootrom.c +// Program: Common Evaluation Platform (CEP) +// Description: Modified baremetal system calls for RISC-V +// Notes: Customized version of syscalls.c for the bootrom +// +//-------------------------------------------------------------------------------------- + + +// See LICENSE for license details. + +#include +#include +#include +#include +#include +#include +#include +#include "kprintf.h" +#include "util.h" + +#define SYS_write 64 + +#undef strcmp + +#define NUM_COUNTERS 2 +static uintptr_t counters[NUM_COUNTERS]; +static char* counter_names[NUM_COUNTERS]; + +void setStats(int enable) +{ + int i = 0; +#define READ_CTR(name) do { \ + while (i >= NUM_COUNTERS) ; \ + uintptr_t csr = read_csr(name); \ + if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \ + counters[i++] = csr; \ + } while (0) + + READ_CTR(mcycle); + READ_CTR(minstret); + +#undef READ_CTR +} + +void __attribute__((noreturn)) tohost_exit(uintptr_t code) +{ + while (1); +} + +uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) +{ + tohost_exit(1337); +} + +void exit(int code) +{ + tohost_exit(code); +} + +void abort() +{ + exit(128 + SIGABRT); +} + +// Syscall is currently disabled as it does +// not function properly in simulation +int puts(const char* s) +{ + kputs(s); + + return 0; +} + +void __attribute__((weak)) thread_entry(int cid, int nc) +{ + // multi-threaded programs override this function. + // for the case of single-threaded programs, only let core 0 proceed. + while (cid != 0); +} + +int __attribute__((weak)) main(int argc, char** argv) +{ + // single-threaded programs override this function. + puts("Implement main(), foo!\n"); + return -1; +} + +#undef getchar +int getchar() +{ + return kgetc(); +} + + +#undef putchar +int putchar(int ch) +{ + kputc(ch); + + return 0; +} + +void printhex(uint64_t x) +{ + char str[17]; + int i; + for (i = 0; i < 16; i++) + { + str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); + x >>= 4; + } + str[16] = 0; + + puts(str); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*CHAR_BIT]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static unsigned long long getuint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, unsigned long long); + else if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long long getint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, long long); + else if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch; + unsigned long long num; + int base, lflag, width, precision; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') { + return; + } else if (ch == '\n') { + putch('\n', putdat); + putch('\r', putdat); + fmt++; + } else { + putch(ch, putdat); + fmt++; + } + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag (doubled for long long) + case 'l': + lflag++; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long long) num < 0) { + putch('-', putdat); + num = -(long long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + static_assert(sizeof(long) == sizeof(void*)); + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +// Calling of putchar from printf is currently disabled +// as syscalls do not function correctly +int printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + vprintfmt((void*)kputc, 0, fmt, ap); + va_end(ap); + + return 0; // incorrect return value, but who cares, anyway? +} + +int sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + void sprintf_putch(int ch, void** data) + { + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; + } + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +} + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +size_t strnlen(const char *s, size_t n) +{ + const char *p = s; + while (n-- && *p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + +long atol(const char* str) +{ + long res = 0; + int sign = 0; + + while (*str == ' ') + str++; + + if (*str == '-' || *str == '+') { + sign = *str == '-'; + str++; + } + + while (*str) { + res *= 10; + res += *str++ - '0'; + } + + return sign ? -res : res; +} \ No newline at end of file diff --git a/fpga/src/main/resources/vc707/cep_sdboot/.gitignore b/fpga/src/main/resources/vc707/cep_sdboot/.gitignore new file mode 100644 index 0000000..07ed706 --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/.gitignore @@ -0,0 +1 @@ +build/* \ No newline at end of file diff --git a/fpga/src/main/resources/vc707/cep_sdboot/Makefile b/fpga/src/main/resources/vc707/cep_sdboot/Makefile new file mode 100644 index 0000000..ddd2dbf --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/Makefile @@ -0,0 +1,46 @@ +# Default parameters +PBUS_CLK ?= 1000000 + +# RISCV environment variable must be set +REPO_ROOT_DIR := $(shell git rev-parse --show-toplevel) +ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +BUILD_DIR := $(ROOT_DIR)/build + +CC =$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY =$(RISCV)/bin/riscv64-unknown-elf-objcopy +OBJDUMP =$(RISCV)/bin/riscv64-unknown-elf-objdump +CFLAGS = -mcmodel=medany -O2 -Wall -fno-common -fno-builtin-printf -fno-builtin-puts +CFLAGS += -I $(ROOT_DIR)/include -I. +CFLAGS += -mabi=lp64 -march=rv64ima +CFLAGS += -DENTROPY=0 -DNONSMP_HART=0 +LFLAGS = -static -nostdlib -nostartfiles -T sdboot.elf.lds +SDSOURCE = ${REPO_ROOT_DIR}/sims/cep_cosim/bootrom/sd.c + +default: elf bin dump + +elf := $(BUILD_DIR)/sdboot.elf +$(elf): head.S ${SDSOURCE} kprintf.c syscalls_bootrom.c + mkdir -p $(BUILD_DIR) + $(CC) $(CFLAGS) -DVC707 -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S ${SDSOURCE} kprintf.c syscalls_bootrom.c + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/sdboot.bin +$(bin): $(elf) + mkdir -p $(BUILD_DIR) + $(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@ + +.PHONY: bin +bin: $(bin) + +dump := $(BUILD_DIR)/sdboot.dump +$(dump): $(elf) + $(OBJDUMP) -D -S $< > $@ + +.PHONY: dump +dump: $(dump) + +.PHONY: clean +clean:: + rm -rf $(BUILD_DIR) diff --git a/fpga/src/main/resources/vc707/cep_sdboot/head.S b/fpga/src/main/resources/vc707/cep_sdboot/head.S new file mode 100644 index 0000000..f11fcbc --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/head.S @@ -0,0 +1,20 @@ +// See LICENSE.Sifive for license details. +#include +#include + + .section .text.init + .option norvc + .globl _prog_start +_prog_start: + smp_pause(s1, s2) + li sp, (MEMORY_MEM_ADDR + 0xffff000) + call main + smp_resume(s1, s2) + csrr a0, mhartid // hartid for next level bootloader + la a1, dtb // dtb address for next level bootloader + li s1, MEMORY_MEM_ADDR + jr s1 + + .section .dtb + .align 3 +dtb: diff --git a/fpga/src/main/resources/vc707/cep_sdboot/include/bits.h b/fpga/src/main/resources/vc707/cep_sdboot/include/bits.h new file mode 100644 index 0000000..216b698 --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/include/bits.h @@ -0,0 +1,36 @@ +// See LICENSE.Sifive for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/sims/cep_cosim/drivers/bare/const.h b/fpga/src/main/resources/vc707/cep_sdboot/include/const.h similarity index 100% rename from sims/cep_cosim/drivers/bare/const.h rename to fpga/src/main/resources/vc707/cep_sdboot/include/const.h diff --git a/software/baremetal/template/include/devices/cepregs.h b/fpga/src/main/resources/vc707/cep_sdboot/include/devices/cepregs.h similarity index 100% rename from software/baremetal/template/include/devices/cepregs.h rename to fpga/src/main/resources/vc707/cep_sdboot/include/devices/cepregs.h diff --git a/sims/cep_cosim/drivers/bare/devices/clint.h b/fpga/src/main/resources/vc707/cep_sdboot/include/devices/clint.h similarity index 100% rename from sims/cep_cosim/drivers/bare/devices/clint.h rename to fpga/src/main/resources/vc707/cep_sdboot/include/devices/clint.h diff --git a/sims/cep_cosim/drivers/bare/devices/gpio.h b/fpga/src/main/resources/vc707/cep_sdboot/include/devices/gpio.h similarity index 100% rename from sims/cep_cosim/drivers/bare/devices/gpio.h rename to fpga/src/main/resources/vc707/cep_sdboot/include/devices/gpio.h diff --git a/sims/cep_cosim/drivers/bare/devices/plic.h b/fpga/src/main/resources/vc707/cep_sdboot/include/devices/plic.h similarity index 100% rename from sims/cep_cosim/drivers/bare/devices/plic.h rename to fpga/src/main/resources/vc707/cep_sdboot/include/devices/plic.h diff --git a/sims/cep_cosim/drivers/bare/devices/spi.h b/fpga/src/main/resources/vc707/cep_sdboot/include/devices/spi.h similarity index 100% rename from sims/cep_cosim/drivers/bare/devices/spi.h rename to fpga/src/main/resources/vc707/cep_sdboot/include/devices/spi.h diff --git a/sims/cep_cosim/drivers/bare/devices/uart.h b/fpga/src/main/resources/vc707/cep_sdboot/include/devices/uart.h similarity index 100% rename from sims/cep_cosim/drivers/bare/devices/uart.h rename to fpga/src/main/resources/vc707/cep_sdboot/include/devices/uart.h diff --git a/fpga/src/main/resources/vc707/cep_sdboot/include/encoding.h b/fpga/src/main/resources/vc707/cep_sdboot/include/encoding.h new file mode 100644 index 0000000..dcf9162 --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/include/encoding.h @@ -0,0 +1,1471 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +//DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +//DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/fpga/src/main/resources/vc707/cep_sdboot/include/kprintf.h b/fpga/src/main/resources/vc707/cep_sdboot/include/kprintf.h new file mode 100644 index 0000000..2733e2d --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/include/kprintf.h @@ -0,0 +1,28 @@ +// See LICENSE.Sifive for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +#define UART_RXEMPTY (1 << 31) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + + +void kputc(int c); +int kgetc(void); +void kputs(const char *); + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/fpga/src/main/resources/vc707/cep_sdboot/include/platform.h b/fpga/src/main/resources/vc707/cep_sdboot/include/platform.h new file mode 100644 index 0000000..50039d2 --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/include/platform.h @@ -0,0 +1,118 @@ +//------------------------------------------------------------------------------------- +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: platform.h +// Program: Common Evaluation Platform (CEP) +// Description: +// Notes: This version has a 1GB main memory size and 1 core +// +//-------------------------------------------------------------------------------------- + +#ifndef _CHIPYARD_PLATFORM_H +#define _CHIPYARD_PLATFORM_H + +#include "const.h" +#include "devices/clint.h" +#include "devices/gpio.h" +#include "devices/plic.h" +#include "devices/spi.h" +#include "devices/uart.h" +#include "devices/cepregs.h" + + // Some things missing from the official encoding.h +#if __riscv_xlen == 32 + #define MCAUSE_INT 0x80000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFUL +#else + #define MCAUSE_INT 0x8000000000000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL +#endif + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// CPU info +#define NUM_CORES 1 +#define GLOBAL_INT_SIZE 38 +#define GLOBAL_INT_MAX_PRIORITY 7 + +// Memory map +#define CLINT_CTRL_ADDR _AC(0x2000000,UL) +#define CLINT_CTRL_SIZE _AC(0x10000,UL) +#define DEBUG_CTRL_ADDR _AC(0x0,UL) +#define DEBUG_CTRL_SIZE _AC(0x1000,UL) +#define ERROR_MEM_ADDR _AC(0x3000,UL) +#define ERROR_MEM_SIZE _AC(0x1000,UL) +#define GPIO_CTRL_ADDR _AC(0x64002000,UL) +#define GPIO_CTRL_SIZE _AC(0x1000,UL) +#define MASKROM_MEM_ADDR _AC(0x10000,UL) +#define MASKROM_MEM_SIZE _AC(0x10000,UL) +#define MEMORY_MEM_ADDR _AC(0x80000000,UL) +#define MEMORY_MEM_SIZE _AC(0x10000000,UL) +#define PLIC_CTRL_ADDR _AC(0xc000000,UL) +#define PLIC_CTRL_SIZE _AC(0x4000000,UL) +#define SPI_CTRL_ADDR _AC(0x64001000,UL) +#define SPI_CTRL_SIZE _AC(0x1000,UL) +#define SPI1_CTRL_ADDR _AC(0x64004000,UL) +#define SPI1_CTRL_SIZE _AC(0x1000,UL) +#define TEST_CTRL_ADDR _AC(0x4000,UL) +#define TEST_CTRL_SIZE _AC(0x1000,UL) +#define UART_CTRL_ADDR _AC(0x64000000,UL) +#define UART_CTRL_SIZE _AC(0x1000,UL) +#define UART1_CTRL_ADDR _AC(0x64003000,UL) +#define UART1_CTRL_SIZE _AC(0x1000,UL) +#define I2C_CTRL_ADDR _AC(0x64005000,UL) +#define I2C_CTRL_SIZE _AC(0x1000,UL) +#define CEPREGS_ADDR _AC(0x700F0000,UL) + +// IOF masks + + +// Interrupt numbers +#define UART_INT_BASE 1 +#define UART1_INT_BASE 2 +#define I2C_INT_BASE 3 +#define GPIO_INT_BASE 4 +#define SPI_INT_BASE 36 +#define SPI1_INT_BASE 37 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset) +#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset) +#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset) +#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset) +#define SPI1_REG64(offset) _REG64(SPI1_CTRL_ADDR, offset) +#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset) +#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset) +#define UART1_REG64(offset) _REG64(UART1_CTRL_ADDR, offset) +#define I2C_REG64(offset) _REG64(I2C_CTRL_ADDR, offset) + +// Misc + + +#endif /* _CHIPYARD_PLATFORM_H */ diff --git a/fpga/src/main/resources/vc707/cep_sdboot/include/sections.h b/fpga/src/main/resources/vc707/cep_sdboot/include/sections.h new file mode 100644 index 0000000..4ec1ef7 --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/include/sections.h @@ -0,0 +1,17 @@ +// See LICENSE.Sifive for license details. +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/fpga/src/main/resources/vc707/cep_sdboot/include/smp.h b/fpga/src/main/resources/vc707/cep_sdboot/include/smp.h new file mode 100644 index 0000000..d93e64b --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/include/smp.h @@ -0,0 +1,143 @@ +// See LICENSE.Sifive for license details. +#ifndef SIFIVE_SMP +#define SIFIVE_SMP +#include "platform.h" + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) +#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + li reg1, NONSMP_HART ;\ + csrr reg2, mhartid ;\ + bne reg1, reg2, 42f + +#ifdef CLINT1_CTRL_ADDR +// If a second CLINT exists, then make sure we: +// 1) Trigger a software interrupt on all harts of both CLINTs. +// 2) Locate your own hart's software interrupt pending register and clear it. +// 3) Wait for all harts on both CLINTs to clear their software interrupt +// pending register. +// WARNING: This code makes these assumptions, which are only true for Fadu as +// of now: +// 1) hart0 uses CLINT0 at offset 0 +// 2) hart2 uses CLINT1 at offset 0 +// 3) hart3 uses CLINT1 at offset 1 +// 4) There are no other harts or CLINTs in the system. +#define smp_resume(reg1, reg2) \ + /* Trigger software interrupt on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Trigger software interrupt on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Wait to receive software interrupt */ \ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + /* Clear own software interrupt bit */ \ + csrr reg2, mhartid ;\ + bnez reg2, 41f; \ + /* hart0 case: Use CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ + j 42f; \ +41: \ + /* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ + addi reg2, reg2, -2; \ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ; \ +42: \ + /* Wait for all software interrupt bits to be cleared on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* Wait for all software interrupt bits to be cleared on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* End smp_resume() */ + +#else + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif /* ifdef CLINT1_CTRL_ADDR */ + +#endif diff --git a/fpga/src/main/resources/vc707/cep_sdboot/include/util.h b/fpga/src/main/resources/vc707/cep_sdboot/include/util.h new file mode 100644 index 0000000..d0b4bfc --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/include/util.h @@ -0,0 +1,77 @@ +// See LICENSE for license details. + +#ifndef __UTIL_H +#define __UTIL_H + +//-------------------------------------------------------------------------- +// Macros + +// Set HOST_DEBUG to 1 if you are going to compile this for a host +// machine (ie Athena/Linux) for debug purposes and set HOST_DEBUG +// to 0 if you are compiling with the smips-gcc toolchain. + +#ifndef HOST_DEBUG +#define HOST_DEBUG 0 +#endif + +// Set PREALLOCATE to 1 if you want to preallocate the benchmark +// function before starting stats. If you have instruction/data +// caches and you don't want to count the overhead of misses, then +// you will need to use preallocation. + +#ifndef PREALLOCATE +#define PREALLOCATE 0 +#endif + +// Set SET_STATS to 1 if you want to carve out the piece that actually +// does the computation. + +#if HOST_DEBUG +#include +static void setStats(int enable) {} +#else +extern void setStats(int enable); +#endif + +#include + +#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } + +#if 0 +static void __attribute__((noinline)) barrier(int ncores) +{ + static volatile int sense; + static volatile int count; + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == ncores-1) + { + count = 0; + sense = threadsense; + } + else while(sense != threadsense) + ; + + __sync_synchronize(); +} +#endif + +#ifdef __riscv +#include "encoding.h" +#endif + +#define stringify_1(s) #s +#define stringify(s) stringify_1(s) +#define stats(code, iter) do { \ + unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ + code; \ + _c += read_csr(mcycle), _i += read_csr(minstret); \ + if (cid == 0) \ + printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ + stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \ + } while(0) + +#endif //__UTIL_H diff --git a/fpga/src/main/resources/vc707/cep_sdboot/kprintf.c b/fpga/src/main/resources/vc707/cep_sdboot/kprintf.c new file mode 100644 index 0000000..bbb47e8 --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/kprintf.c @@ -0,0 +1,43 @@ +// See LICENSE.Sifive for license details. +#include +#include +#include +#include "kprintf.h" + +void kputc(int c) +{ +#ifndef DISABLE_KPRINTF + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); + while ((int32_t)(*tx) < 0); + *tx = (c & 0xFF); +#endif +} + +int kgetc(void) +{ +#ifndef DISABLE_KPRINTF + uint32_t ch; + volatile uint32_t *rx = ®32(uart, UART_REG_RXFIFO); + ch = *rx; + + if ((uint32_t)(ch & UART_RXEMPTY)) { + return -1; + } else { + return(ch & 0x0ff); + } +#else + return -1; +#endif +} + +void kputs(const char *s) +{ + char c; + while (*s != '\0') { + c = *s; + kputc((int) c); + s++; + } + kputc('\r'); + kputc('\n'); +} \ No newline at end of file diff --git a/fpga/src/main/resources/vc707/cep_sdboot/sdboot.elf.lds b/fpga/src/main/resources/vc707/cep_sdboot/sdboot.elf.lds new file mode 100644 index 0000000..6779196 --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/sdboot.elf.lds @@ -0,0 +1,84 @@ +OUTPUT_ARCH("riscv") +ENTRY(_prog_start) + +MEMORY +{ + bootrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x10000 + memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x10000000 +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + PROVIDE(_ram = ORIGIN(memory_mem)); + PROVIDE(_ram_end = _ram + LENGTH(memory_mem)); + + .text ALIGN((ORIGIN(bootrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(bootrom_mem) + 0x0), 8)) { + PROVIDE(_ftext = .); + *(.text.init) + *(.text.unlikely .text.unlikely.*) + *(.text .text.* .gnu.linkonce.t.*) + PROVIDE(_etext = .); + . += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */ + } >bootrom_mem :text + + .eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) { + *(.eh_frame) + } >bootrom_mem :text + + .srodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT { + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata.*) + } >bootrom_mem :data + + .data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT { + *(.data .data.* .gnu.linkonce.d.*) + *(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */ + } >bootrom_mem :data + + .sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >bootrom_mem :data + + .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.dtb) /* Must be last if this code is added to RC's BootROM */ + } >bootrom_mem :data + + PROVIDE(_data = ADDR(.rodata)); + PROVIDE(_data_lma = LOADADDR(.rodata)); + PROVIDE(_edata = .); + + .bss ALIGN((ORIGIN(memory_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(memory_mem) + 0x0), 8)) ALIGN(8) { + PROVIDE(_fbss = .); + PROVIDE(__global_pointer$ = . + 0x7C0); + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(8); + PROVIDE(_ebss = .); + } >memory_mem :bss + + PROVIDE(_end = .); + + /* + * heap_stack_region_usable_end: (ORIGIN(memory_mem) + LENGTH(memory_mem)) + * heap_stack_min_size: 4096 + * heap_stack_max_size: 1048576 + */ + PROVIDE(_sp = ALIGN(MIN((ORIGIN(memory_mem) + LENGTH(memory_mem)), _ebss + 1048576) - 7, 8)); + PROVIDE(_heap_end = _sp - 2048); + + /* This section is a noop and is only used for the ASSERT */ + .stack : { + ASSERT(_sp >= (_ebss + 4096), "Error: No room left for the heap and stack"); + } +} diff --git a/fpga/src/main/resources/vc707/cep_sdboot/syscalls_bootrom.c b/fpga/src/main/resources/vc707/cep_sdboot/syscalls_bootrom.c new file mode 100644 index 0000000..c5c970c --- /dev/null +++ b/fpga/src/main/resources/vc707/cep_sdboot/syscalls_bootrom.c @@ -0,0 +1,438 @@ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: syscalls_bootrom.c +// Program: Common Evaluation Platform (CEP) +// Description: Modified baremetal system calls for RISC-V +// Notes: Customized version of syscalls.c for the bootrom +// +//-------------------------------------------------------------------------------------- + + +// See LICENSE for license details. + +#include +#include +#include +#include +#include +#include +#include +#include "kprintf.h" +#include "util.h" + +#define SYS_write 64 + +#undef strcmp + +#define NUM_COUNTERS 2 +static uintptr_t counters[NUM_COUNTERS]; +static char* counter_names[NUM_COUNTERS]; + +void setStats(int enable) +{ + int i = 0; +#define READ_CTR(name) do { \ + while (i >= NUM_COUNTERS) ; \ + uintptr_t csr = read_csr(name); \ + if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \ + counters[i++] = csr; \ + } while (0) + + READ_CTR(mcycle); + READ_CTR(minstret); + +#undef READ_CTR +} + +void __attribute__((noreturn)) tohost_exit(uintptr_t code) +{ + while (1); +} + +uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) +{ + tohost_exit(1337); +} + +void exit(int code) +{ + tohost_exit(code); +} + +void abort() +{ + exit(128 + SIGABRT); +} + +// Syscall is currently disabled as it does +// not function properly in simulation +int puts(const char* s) +{ + kputs(s); + + return 0; +} + +void __attribute__((weak)) thread_entry(int cid, int nc) +{ + // multi-threaded programs override this function. + // for the case of single-threaded programs, only let core 0 proceed. + while (cid != 0); +} + +int __attribute__((weak)) main(int argc, char** argv) +{ + // single-threaded programs override this function. + puts("Implement main(), foo!\n"); + return -1; +} + +#undef getchar +int getchar() +{ + return kgetc(); +} + + +#undef putchar +int putchar(int ch) +{ + kputc(ch); + + return 0; +} + +void printhex(uint64_t x) +{ + char str[17]; + int i; + for (i = 0; i < 16; i++) + { + str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); + x >>= 4; + } + str[16] = 0; + + puts(str); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*CHAR_BIT]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static unsigned long long getuint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, unsigned long long); + else if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long long getint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, long long); + else if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch; + unsigned long long num; + int base, lflag, width, precision; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') { + return; + } else if (ch == '\n') { + putch('\n', putdat); + putch('\r', putdat); + fmt++; + } else { + putch(ch, putdat); + fmt++; + } + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag (doubled for long long) + case 'l': + lflag++; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long long) num < 0) { + putch('-', putdat); + num = -(long long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + static_assert(sizeof(long) == sizeof(void*)); + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +// Calling of putchar from printf is currently disabled +// as syscalls do not function correctly +int printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + vprintfmt((void*)kputc, 0, fmt, ap); + va_end(ap); + + return 0; // incorrect return value, but who cares, anyway? +} + +int sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + void sprintf_putch(int ch, void** data) + { + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; + } + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +} + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +size_t strnlen(const char *s, size_t n) +{ + const char *p = s; + while (n-- && *p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + +long atol(const char* str) +{ + long res = 0; + int sign = 0; + + while (*str == ' ') + str++; + + if (*str == '-' || *str == '+') { + sign = *str == '-'; + str++; + } + + while (*str) { + res *= 10; + res += *str++ - '0'; + } + + return sign ? -res : res; +} \ No newline at end of file diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/Makefile b/fpga/src/main/resources/vcu118/cep_sdboot/Makefile new file mode 100644 index 0000000..ebd0adc --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/Makefile @@ -0,0 +1,46 @@ +# Default parameters +PBUS_CLK ?= 1000000 + +# RISCV environment variable must be set +REPO_ROOT_DIR := $(shell git rev-parse --show-toplevel) +ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +BUILD_DIR := $(ROOT_DIR)/build + +CC =$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY =$(RISCV)/bin/riscv64-unknown-elf-objcopy +OBJDUMP =$(RISCV)/bin/riscv64-unknown-elf-objdump +CFLAGS = -mcmodel=medany -O2 -Wall -fno-common -fno-builtin-printf -fno-builtin-puts +CFLAGS += -I $(ROOT_DIR)/include -I. +CFLAGS += -mabi=lp64 -march=rv64ima +CFLAGS += -DENTROPY=0 -DNONSMP_HART=0 +LFLAGS = -static -nostdlib -nostartfiles -T sdboot.elf.lds +SDSOURCE = ${REPO_ROOT_DIR}/sims/cep_cosim/bootrom/sd.c + +default: elf bin dump + +elf := $(BUILD_DIR)/sdboot.elf +$(elf): head.S ${SDSOURCE} kprintf.c syscalls_bootrom.c + mkdir -p $(BUILD_DIR) + $(CC) $(CFLAGS) -DVCU118 -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S ${SDSOURCE} kprintf.c syscalls_bootrom.c + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/sdboot.bin +$(bin): $(elf) + mkdir -p $(BUILD_DIR) + $(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@ + +.PHONY: bin +bin: $(bin) + +dump := $(BUILD_DIR)/sdboot.dump +$(dump): $(elf) + $(OBJDUMP) -D -S $< > $@ + +.PHONY: dump +dump: $(dump) + +.PHONY: clean +clean:: + rm -rf $(BUILD_DIR) diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/head.S b/fpga/src/main/resources/vcu118/cep_sdboot/head.S new file mode 100644 index 0000000..f11fcbc --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/head.S @@ -0,0 +1,20 @@ +// See LICENSE.Sifive for license details. +#include +#include + + .section .text.init + .option norvc + .globl _prog_start +_prog_start: + smp_pause(s1, s2) + li sp, (MEMORY_MEM_ADDR + 0xffff000) + call main + smp_resume(s1, s2) + csrr a0, mhartid // hartid for next level bootloader + la a1, dtb // dtb address for next level bootloader + li s1, MEMORY_MEM_ADDR + jr s1 + + .section .dtb + .align 3 +dtb: diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/include/bits.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/bits.h new file mode 100644 index 0000000..216b698 --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/include/bits.h @@ -0,0 +1,36 @@ +// See LICENSE.Sifive for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/software/baremetal/template/include/const.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/const.h similarity index 100% rename from software/baremetal/template/include/const.h rename to fpga/src/main/resources/vcu118/cep_sdboot/include/const.h diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/include/devices/cepregs.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/devices/cepregs.h new file mode 100644 index 0000000..6a73d0a --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/include/devices/cepregs.h @@ -0,0 +1,22 @@ +// See LICENSE.Sifive for license details. + +#ifndef _CEPREGS_H +#define _CEPREGS_H + +/* Register offsets */ +#define CEPREGS_VERSION 0x0000 +#define CEPREGS_TESTNSET 0xFD10 +#define CEPREGS_SCRATCH_W0 0xFE00 +#define CEPREGS_SCRATCH_W1 0xFE08 +#define CEPREGS_SCRATCH_W2 0xFE10 +#define CEPREGS_SCRATCH_W3 0xFE18 +#define CEPREGS_SCRATCH_W4 0xFE20 +#define CEPREGS_SCRATCH_W5 0xFE28 +#define CEPREGS_SCRATCH_W6 0xFE30 +#define CEPREGS_SCRATCH_W7 0xFE38 +#define CEPREGS_CORE0_STATUS 0xFF00 +#define CEPREGS_CORE1_STATUS 0xFF08 +#define CEPREGS_CORE2_STATUS 0xFF10 +#define CEPREGS_CORE3_STATUS 0xFF18 + +#endif /* _CEPREGS_H */ diff --git a/software/baremetal/template/include/devices/clint.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/devices/clint.h similarity index 100% rename from software/baremetal/template/include/devices/clint.h rename to fpga/src/main/resources/vcu118/cep_sdboot/include/devices/clint.h diff --git a/software/baremetal/template/include/devices/gpio.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/devices/gpio.h similarity index 100% rename from software/baremetal/template/include/devices/gpio.h rename to fpga/src/main/resources/vcu118/cep_sdboot/include/devices/gpio.h diff --git a/software/baremetal/template/include/devices/plic.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/devices/plic.h similarity index 100% rename from software/baremetal/template/include/devices/plic.h rename to fpga/src/main/resources/vcu118/cep_sdboot/include/devices/plic.h diff --git a/software/baremetal/template/include/devices/spi.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/devices/spi.h similarity index 100% rename from software/baremetal/template/include/devices/spi.h rename to fpga/src/main/resources/vcu118/cep_sdboot/include/devices/spi.h diff --git a/software/baremetal/template/include/devices/uart.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/devices/uart.h similarity index 100% rename from software/baremetal/template/include/devices/uart.h rename to fpga/src/main/resources/vcu118/cep_sdboot/include/devices/uart.h diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/include/encoding.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/encoding.h new file mode 100644 index 0000000..dcf9162 --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/include/encoding.h @@ -0,0 +1,1471 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +//DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +//DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/include/kprintf.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/kprintf.h new file mode 100644 index 0000000..2733e2d --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/include/kprintf.h @@ -0,0 +1,28 @@ +// See LICENSE.Sifive for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +#define UART_RXEMPTY (1 << 31) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + + +void kputc(int c); +int kgetc(void); +void kputs(const char *); + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/include/platform.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/platform.h new file mode 100644 index 0000000..50039d2 --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/include/platform.h @@ -0,0 +1,118 @@ +//------------------------------------------------------------------------------------- +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: platform.h +// Program: Common Evaluation Platform (CEP) +// Description: +// Notes: This version has a 1GB main memory size and 1 core +// +//-------------------------------------------------------------------------------------- + +#ifndef _CHIPYARD_PLATFORM_H +#define _CHIPYARD_PLATFORM_H + +#include "const.h" +#include "devices/clint.h" +#include "devices/gpio.h" +#include "devices/plic.h" +#include "devices/spi.h" +#include "devices/uart.h" +#include "devices/cepregs.h" + + // Some things missing from the official encoding.h +#if __riscv_xlen == 32 + #define MCAUSE_INT 0x80000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFUL +#else + #define MCAUSE_INT 0x8000000000000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL +#endif + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// CPU info +#define NUM_CORES 1 +#define GLOBAL_INT_SIZE 38 +#define GLOBAL_INT_MAX_PRIORITY 7 + +// Memory map +#define CLINT_CTRL_ADDR _AC(0x2000000,UL) +#define CLINT_CTRL_SIZE _AC(0x10000,UL) +#define DEBUG_CTRL_ADDR _AC(0x0,UL) +#define DEBUG_CTRL_SIZE _AC(0x1000,UL) +#define ERROR_MEM_ADDR _AC(0x3000,UL) +#define ERROR_MEM_SIZE _AC(0x1000,UL) +#define GPIO_CTRL_ADDR _AC(0x64002000,UL) +#define GPIO_CTRL_SIZE _AC(0x1000,UL) +#define MASKROM_MEM_ADDR _AC(0x10000,UL) +#define MASKROM_MEM_SIZE _AC(0x10000,UL) +#define MEMORY_MEM_ADDR _AC(0x80000000,UL) +#define MEMORY_MEM_SIZE _AC(0x10000000,UL) +#define PLIC_CTRL_ADDR _AC(0xc000000,UL) +#define PLIC_CTRL_SIZE _AC(0x4000000,UL) +#define SPI_CTRL_ADDR _AC(0x64001000,UL) +#define SPI_CTRL_SIZE _AC(0x1000,UL) +#define SPI1_CTRL_ADDR _AC(0x64004000,UL) +#define SPI1_CTRL_SIZE _AC(0x1000,UL) +#define TEST_CTRL_ADDR _AC(0x4000,UL) +#define TEST_CTRL_SIZE _AC(0x1000,UL) +#define UART_CTRL_ADDR _AC(0x64000000,UL) +#define UART_CTRL_SIZE _AC(0x1000,UL) +#define UART1_CTRL_ADDR _AC(0x64003000,UL) +#define UART1_CTRL_SIZE _AC(0x1000,UL) +#define I2C_CTRL_ADDR _AC(0x64005000,UL) +#define I2C_CTRL_SIZE _AC(0x1000,UL) +#define CEPREGS_ADDR _AC(0x700F0000,UL) + +// IOF masks + + +// Interrupt numbers +#define UART_INT_BASE 1 +#define UART1_INT_BASE 2 +#define I2C_INT_BASE 3 +#define GPIO_INT_BASE 4 +#define SPI_INT_BASE 36 +#define SPI1_INT_BASE 37 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset) +#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset) +#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset) +#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset) +#define SPI1_REG64(offset) _REG64(SPI1_CTRL_ADDR, offset) +#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset) +#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset) +#define UART1_REG64(offset) _REG64(UART1_CTRL_ADDR, offset) +#define I2C_REG64(offset) _REG64(I2C_CTRL_ADDR, offset) + +// Misc + + +#endif /* _CHIPYARD_PLATFORM_H */ diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/include/sections.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/sections.h new file mode 100644 index 0000000..4ec1ef7 --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/include/sections.h @@ -0,0 +1,17 @@ +// See LICENSE.Sifive for license details. +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/include/smp.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/smp.h new file mode 100644 index 0000000..d93e64b --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/include/smp.h @@ -0,0 +1,143 @@ +// See LICENSE.Sifive for license details. +#ifndef SIFIVE_SMP +#define SIFIVE_SMP +#include "platform.h" + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) +#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + li reg1, NONSMP_HART ;\ + csrr reg2, mhartid ;\ + bne reg1, reg2, 42f + +#ifdef CLINT1_CTRL_ADDR +// If a second CLINT exists, then make sure we: +// 1) Trigger a software interrupt on all harts of both CLINTs. +// 2) Locate your own hart's software interrupt pending register and clear it. +// 3) Wait for all harts on both CLINTs to clear their software interrupt +// pending register. +// WARNING: This code makes these assumptions, which are only true for Fadu as +// of now: +// 1) hart0 uses CLINT0 at offset 0 +// 2) hart2 uses CLINT1 at offset 0 +// 3) hart3 uses CLINT1 at offset 1 +// 4) There are no other harts or CLINTs in the system. +#define smp_resume(reg1, reg2) \ + /* Trigger software interrupt on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Trigger software interrupt on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Wait to receive software interrupt */ \ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + /* Clear own software interrupt bit */ \ + csrr reg2, mhartid ;\ + bnez reg2, 41f; \ + /* hart0 case: Use CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ + j 42f; \ +41: \ + /* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ + addi reg2, reg2, -2; \ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ; \ +42: \ + /* Wait for all software interrupt bits to be cleared on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* Wait for all software interrupt bits to be cleared on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* End smp_resume() */ + +#else + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif /* ifdef CLINT1_CTRL_ADDR */ + +#endif diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/include/util.h b/fpga/src/main/resources/vcu118/cep_sdboot/include/util.h new file mode 100644 index 0000000..d0b4bfc --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/include/util.h @@ -0,0 +1,77 @@ +// See LICENSE for license details. + +#ifndef __UTIL_H +#define __UTIL_H + +//-------------------------------------------------------------------------- +// Macros + +// Set HOST_DEBUG to 1 if you are going to compile this for a host +// machine (ie Athena/Linux) for debug purposes and set HOST_DEBUG +// to 0 if you are compiling with the smips-gcc toolchain. + +#ifndef HOST_DEBUG +#define HOST_DEBUG 0 +#endif + +// Set PREALLOCATE to 1 if you want to preallocate the benchmark +// function before starting stats. If you have instruction/data +// caches and you don't want to count the overhead of misses, then +// you will need to use preallocation. + +#ifndef PREALLOCATE +#define PREALLOCATE 0 +#endif + +// Set SET_STATS to 1 if you want to carve out the piece that actually +// does the computation. + +#if HOST_DEBUG +#include +static void setStats(int enable) {} +#else +extern void setStats(int enable); +#endif + +#include + +#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } + +#if 0 +static void __attribute__((noinline)) barrier(int ncores) +{ + static volatile int sense; + static volatile int count; + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == ncores-1) + { + count = 0; + sense = threadsense; + } + else while(sense != threadsense) + ; + + __sync_synchronize(); +} +#endif + +#ifdef __riscv +#include "encoding.h" +#endif + +#define stringify_1(s) #s +#define stringify(s) stringify_1(s) +#define stats(code, iter) do { \ + unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ + code; \ + _c += read_csr(mcycle), _i += read_csr(minstret); \ + if (cid == 0) \ + printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ + stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \ + } while(0) + +#endif //__UTIL_H diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/kprintf.c b/fpga/src/main/resources/vcu118/cep_sdboot/kprintf.c new file mode 100644 index 0000000..bbb47e8 --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/kprintf.c @@ -0,0 +1,43 @@ +// See LICENSE.Sifive for license details. +#include +#include +#include +#include "kprintf.h" + +void kputc(int c) +{ +#ifndef DISABLE_KPRINTF + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); + while ((int32_t)(*tx) < 0); + *tx = (c & 0xFF); +#endif +} + +int kgetc(void) +{ +#ifndef DISABLE_KPRINTF + uint32_t ch; + volatile uint32_t *rx = ®32(uart, UART_REG_RXFIFO); + ch = *rx; + + if ((uint32_t)(ch & UART_RXEMPTY)) { + return -1; + } else { + return(ch & 0x0ff); + } +#else + return -1; +#endif +} + +void kputs(const char *s) +{ + char c; + while (*s != '\0') { + c = *s; + kputc((int) c); + s++; + } + kputc('\r'); + kputc('\n'); +} \ No newline at end of file diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/sdboot.elf.lds b/fpga/src/main/resources/vcu118/cep_sdboot/sdboot.elf.lds new file mode 100644 index 0000000..6779196 --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/sdboot.elf.lds @@ -0,0 +1,84 @@ +OUTPUT_ARCH("riscv") +ENTRY(_prog_start) + +MEMORY +{ + bootrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x10000 + memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x10000000 +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + PROVIDE(_ram = ORIGIN(memory_mem)); + PROVIDE(_ram_end = _ram + LENGTH(memory_mem)); + + .text ALIGN((ORIGIN(bootrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(bootrom_mem) + 0x0), 8)) { + PROVIDE(_ftext = .); + *(.text.init) + *(.text.unlikely .text.unlikely.*) + *(.text .text.* .gnu.linkonce.t.*) + PROVIDE(_etext = .); + . += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */ + } >bootrom_mem :text + + .eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) { + *(.eh_frame) + } >bootrom_mem :text + + .srodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT { + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata.*) + } >bootrom_mem :data + + .data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT { + *(.data .data.* .gnu.linkonce.d.*) + *(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */ + } >bootrom_mem :data + + .sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >bootrom_mem :data + + .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.dtb) /* Must be last if this code is added to RC's BootROM */ + } >bootrom_mem :data + + PROVIDE(_data = ADDR(.rodata)); + PROVIDE(_data_lma = LOADADDR(.rodata)); + PROVIDE(_edata = .); + + .bss ALIGN((ORIGIN(memory_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(memory_mem) + 0x0), 8)) ALIGN(8) { + PROVIDE(_fbss = .); + PROVIDE(__global_pointer$ = . + 0x7C0); + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(8); + PROVIDE(_ebss = .); + } >memory_mem :bss + + PROVIDE(_end = .); + + /* + * heap_stack_region_usable_end: (ORIGIN(memory_mem) + LENGTH(memory_mem)) + * heap_stack_min_size: 4096 + * heap_stack_max_size: 1048576 + */ + PROVIDE(_sp = ALIGN(MIN((ORIGIN(memory_mem) + LENGTH(memory_mem)), _ebss + 1048576) - 7, 8)); + PROVIDE(_heap_end = _sp - 2048); + + /* This section is a noop and is only used for the ASSERT */ + .stack : { + ASSERT(_sp >= (_ebss + 4096), "Error: No room left for the heap and stack"); + } +} diff --git a/fpga/src/main/resources/vcu118/cep_sdboot/syscalls_bootrom.c b/fpga/src/main/resources/vcu118/cep_sdboot/syscalls_bootrom.c new file mode 100644 index 0000000..c5c970c --- /dev/null +++ b/fpga/src/main/resources/vcu118/cep_sdboot/syscalls_bootrom.c @@ -0,0 +1,438 @@ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: syscalls_bootrom.c +// Program: Common Evaluation Platform (CEP) +// Description: Modified baremetal system calls for RISC-V +// Notes: Customized version of syscalls.c for the bootrom +// +//-------------------------------------------------------------------------------------- + + +// See LICENSE for license details. + +#include +#include +#include +#include +#include +#include +#include +#include "kprintf.h" +#include "util.h" + +#define SYS_write 64 + +#undef strcmp + +#define NUM_COUNTERS 2 +static uintptr_t counters[NUM_COUNTERS]; +static char* counter_names[NUM_COUNTERS]; + +void setStats(int enable) +{ + int i = 0; +#define READ_CTR(name) do { \ + while (i >= NUM_COUNTERS) ; \ + uintptr_t csr = read_csr(name); \ + if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \ + counters[i++] = csr; \ + } while (0) + + READ_CTR(mcycle); + READ_CTR(minstret); + +#undef READ_CTR +} + +void __attribute__((noreturn)) tohost_exit(uintptr_t code) +{ + while (1); +} + +uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) +{ + tohost_exit(1337); +} + +void exit(int code) +{ + tohost_exit(code); +} + +void abort() +{ + exit(128 + SIGABRT); +} + +// Syscall is currently disabled as it does +// not function properly in simulation +int puts(const char* s) +{ + kputs(s); + + return 0; +} + +void __attribute__((weak)) thread_entry(int cid, int nc) +{ + // multi-threaded programs override this function. + // for the case of single-threaded programs, only let core 0 proceed. + while (cid != 0); +} + +int __attribute__((weak)) main(int argc, char** argv) +{ + // single-threaded programs override this function. + puts("Implement main(), foo!\n"); + return -1; +} + +#undef getchar +int getchar() +{ + return kgetc(); +} + + +#undef putchar +int putchar(int ch) +{ + kputc(ch); + + return 0; +} + +void printhex(uint64_t x) +{ + char str[17]; + int i; + for (i = 0; i < 16; i++) + { + str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); + x >>= 4; + } + str[16] = 0; + + puts(str); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*CHAR_BIT]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static unsigned long long getuint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, unsigned long long); + else if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long long getint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, long long); + else if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch; + unsigned long long num; + int base, lflag, width, precision; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') { + return; + } else if (ch == '\n') { + putch('\n', putdat); + putch('\r', putdat); + fmt++; + } else { + putch(ch, putdat); + fmt++; + } + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag (doubled for long long) + case 'l': + lflag++; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long long) num < 0) { + putch('-', putdat); + num = -(long long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + static_assert(sizeof(long) == sizeof(void*)); + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +// Calling of putchar from printf is currently disabled +// as syscalls do not function correctly +int printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + vprintfmt((void*)kputc, 0, fmt, ap); + va_end(ap); + + return 0; // incorrect return value, but who cares, anyway? +} + +int sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + void sprintf_putch(int ch, void** data) + { + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; + } + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +} + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +size_t strnlen(const char *s, size_t n) +{ + const char *p = s; + while (n-- && *p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + +long atol(const char* str) +{ + long res = 0; + int sign = 0; + + while (*str == ' ') + str++; + + if (*str == '-' || *str == '+') { + sign = *str == '-'; + str++; + } + + while (*str) { + res *= 10; + res += *str++ - '0'; + } + + return sign ? -res : res; +} \ No newline at end of file diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index a289378..ca796aa 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -17,6 +17,8 @@ import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{ArtyDDRSize} +import mitllBlocks.cep_addresses._ + import testchipip.{SerialTLKey} import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} @@ -39,19 +41,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { } }) -class WithSystemModifications extends Config((site, here, up) => { - case DTSTimebase => BigInt((1e6).toLong) - case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => - // invoke makefile for sdboot - val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong - val make = s"make -B -C fpga/src/main/resources/arty100t/sdboot PBUS_CLK=${freqMHz} bin" - require (make.! == 0, "Failed to build bootrom") - p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/arty100t/sdboot/build/sdboot.bin") - } - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(ArtyDDRSize)))) // set extmem to DDR size - case SerialTLKey => None // remove serialized tl port -}) - // Update to use the same bootrom as the CEP Cosimulation class WithCEPSystemModifications extends Config((site, here, up) => { case DTSTimebase => BigInt((1e6).toLong) @@ -66,26 +55,6 @@ class WithCEPSystemModifications extends Config((site, here, up) => { case SerialTLKey => None // remove serialized tl port }) -// DOC include start: AbstractArty100T and Rocket -class WithArty100TTweaks extends Config( - // harness binders - new WithUART ++ - new WithSPISDCard ++ - new WithDDRMem ++ - // io binders - new WithUARTIOPassthrough ++ - new WithSPIIOPassthrough ++ - new WithTLIOPassthrough ++ - // other configuration - new WithDefaultPeripherals ++ - new chipyard.config.WithTLBackingMemory ++ // use TL backing memory - new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size - new chipyard.config.WithNoDebug ++ // remove debug module - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ - new WithFPGAFrequency(100) // default 100MHz freq -) - // DOC include start: AbstractArty100T and Rocket class WithArty100TCEPTweaks extends Config( // harness binders @@ -108,24 +77,6 @@ class WithArty100TCEPTweaks extends Config( new WithFPGAFrequency(100) // default 100MHz freq ) -class RocketArty100TConfig extends Config( - // reduce L2 size to fit in 100T's BRAMs - new freechips.rocketchip.subsystem.WithInclusiveCache(capacityKB=256) ++ - // with reduced cache size, closes timing at 50 MHz - new WithFPGAFrequency(50) ++ - new WithArty100TTweaks ++ - new chipyard.RocketConfig -) -// DOC include end: AbstractArty100T and Rocket - -class RocketArty100TSimConfig extends Config( - new WithFPGASimSerial ++ - new testchipip.WithDefaultSerialTL ++ - new chipyard.harness.WithSimSerial ++ - new chipyard.harness.WithTiedOffDebug ++ - new RocketArty100TConfig - ) - class RocketArty100TCEPConfig extends Config( // Add the CEP registers new chipyard.config.WithCEPRegisters ++ @@ -133,30 +84,19 @@ class RocketArty100TCEPConfig extends Config( new chipyard.config.WithSROTFPGA ++ // Overide the chip info - new WithDTS("mit-ll,rocketchip-cep", Nil) ++ + new WithDTS("mit-ll,cep-arty100t", Nil) ++ // with reduced cache size, closes timing at 50 MHz new WithFPGAFrequency(50) ++ // Include the Arty100T Tweaks with CEP Registers enabled (passed to the bootrom build) new WithArty100TCEPTweaks ++ - new chipyard.RocketNoL2Config -) -// A minimum CEP configuration with only the registers component -class RocketArty100TMinCEPConfig extends Config( - // Add the CEP registers - new chipyard.config.WithCEPRegisters ++ - - // Overide the chip info - new WithDTS("mit-ll,rocketchip-cep", Nil) ++ - - // with reduced cache size, closes timing at 50 MHz - new WithFPGAFrequency(50) ++ - - // Include the Arty100T Tweaks with CEP Registers enabled (passed to the bootrom build) - new WithArty100TCEPTweaks ++ - new chipyard.RocketNoL2Config + // Instantiate one big core + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + + // Default Chipyard AbstractConfig with L2 removed + new chipyard.config.AbstractNoL2Config ) class WithFPGAFrequency(fMHz: Double) extends Config( diff --git a/fpga/src/main/scala/arty100t/TestHarness.scala b/fpga/src/main/scala/arty100t/TestHarness.scala index cbdc9bd..470773a 100644 --- a/fpga/src/main/scala/arty100t/TestHarness.scala +++ b/fpga/src/main/scala/arty100t/TestHarness.scala @@ -50,8 +50,8 @@ class Arty100TFPGATestHarness(override implicit val p: Parameters) extends Arty1 /*** UART ***/ -// DOC include start: UartOverlay - // 1st UART goes to the VCU118 dedicated UART + // DOC include start: UartOverlay + // 1st UART goes to the Arty100T dedicated UART val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala new file mode 100644 index 0000000..ac0f227 --- /dev/null +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -0,0 +1,210 @@ +package chipyard.fpga.vc707 + +import sys.process._ +import math.min + +import freechips.rocketchip.config.{Config, Parameters} +import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem, WithDTS} +import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} +import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.tile.{XLen} + +import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} +import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} +import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} + +import sifive.fpgashells.shell.{DesignKey} +import sifive.fpgashells.shell.xilinx.{VC7071GDDRSize} + +import mitllBlocks.cep_addresses._ + +import testchipip.{SerialTLKey} + +import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} + +class WithDefaultPeripherals extends Config((site, here, up) => { + case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) + case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) + case PeripheryGPIOKey => { + if (VC707GPIOs.width > 0) { + require(VC707GPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) + val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000)) + val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32) + List.tabulate(((VC707GPIOs.width - 1)/maxGPIOSupport) + 1)(n => { + GPIOParams(address = gpioAddrs(n), width = min(VC707GPIOs.width - maxGPIOSupport*n, maxGPIOSupport)) + }) + } + else { + List.empty[GPIOParams] + } + } +}) + +class WithCEPSystemModifications extends Config((site, here, up) => { + case DTSTimebase => BigInt((1e6).toLong) + case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => + // invoke makefile for sdboot + val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong + val make = s"make -B -C fpga/src/main/resources/vc707/cep_sdboot PBUS_CLK=${freqMHz} bin" + require (make.! == 0, "Failed to build bootrom") + p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/cep_sdboot/build/sdboot.bin") + } + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7071GDDRSize)))) // set extmem to DDR size + case SerialTLKey => None // remove serialized tl port +}) + +class WithVC707CEPTweaks extends Config( + // harness bindersn + new WithUART ++ + new WithSPISDCard ++ + new WithDDRMem ++ + new WithGPIO ++ + // io binders + new WithUARTIOPassthrough ++ + new WithSPIIOPassthrough ++ + new WithTLIOPassthrough ++ + new WithGPIOPassthrough ++ + // other configuration + new WithDefaultPeripherals ++ + new chipyard.config.WithTLBackingMemory ++ // use TL backing memory + new WithCEPSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size + new chipyard.config.WithNoDebug ++ // remove debug module + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ + new WithFPGAFrequency(100) // default 100MHz freq +) + +class RocketVC707CEPConfig extends Config( + // Add the CEP registers + new chipyard.config.WithCEPRegisters ++ + new chipyard.config.WithAES ++ + new chipyard.config.WithSROTFPGA ++ + + // Overide the chip info + new WithDTS("mit-ll,cep-vc707", Nil) ++ + + // with reduced cache size, closes timing at 50 MHz + new WithFPGAFrequency(100) ++ + + // Include the VC707 Tweaks with CEP Registers enabled (passed to the bootrom build) + new WithVC707CEPTweaks ++ + + // Instantiate one big core + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + + // Default Chipyard AbstractConfig with L2 removed + new chipyard.config.AbstractNoL2Config +) + +class RocketVC707BigCEPConfig extends Config( + new chipyard.config.WithAES ++ + new chipyard.config.WithDES3 ++ + new chipyard.config.WithFIR ++ + new chipyard.config.WithIIR ++ + new chipyard.config.WithDFT ++ + new chipyard.config.WithIDFT ++ + new chipyard.config.WithMD5 ++ + new chipyard.config.WithGPS(params = Seq( + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.gps_0_base_addr), + slave_depth = BigInt(CEPBaseAddresses.gps_0_depth), + llki_base_addr = BigInt(CEPBaseAddresses.gps_0_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.gps_0_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_0_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_0_llki_sendrecv_addr), + dev_name = s"gps_0"), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.gps_1_base_addr), + slave_depth = BigInt(CEPBaseAddresses.gps_1_depth), + llki_base_addr = BigInt(CEPBaseAddresses.gps_1_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.gps_1_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_1_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_1_llki_sendrecv_addr), + dev_name = s"gps_1"), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.gps_2_base_addr), + slave_depth = BigInt(CEPBaseAddresses.gps_2_depth), + llki_base_addr = BigInt(CEPBaseAddresses.gps_2_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.gps_2_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_2_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_2_llki_sendrecv_addr), + dev_name = s"gps_2"), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.gps_3_base_addr), + slave_depth = BigInt(CEPBaseAddresses.gps_3_depth), + llki_base_addr = BigInt(CEPBaseAddresses.gps_3_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.gps_3_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_3_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_3_llki_sendrecv_addr), + dev_name = s"gps_3") + )) ++ + new chipyard.config.WithSHA256(params = Seq( + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.sha256_0_base_addr), + slave_depth = BigInt(CEPBaseAddresses.sha256_0_depth), + llki_base_addr = BigInt(CEPBaseAddresses.sha256_0_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.sha256_0_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_0_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_0_llki_sendrecv_addr), + dev_name = s"sha256_0"), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.sha256_1_base_addr), + slave_depth = BigInt(CEPBaseAddresses.sha256_1_depth), + llki_base_addr = BigInt(CEPBaseAddresses.sha256_1_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.sha256_1_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_1_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_1_llki_sendrecv_addr), + dev_name = s"sha256_1"), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.sha256_2_base_addr), + slave_depth = BigInt(CEPBaseAddresses.sha256_2_depth), + llki_base_addr = BigInt(CEPBaseAddresses.sha256_2_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.sha256_2_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_2_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_2_llki_sendrecv_addr), + dev_name = s"sha256_2"), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.sha256_3_base_addr), + slave_depth = BigInt(CEPBaseAddresses.sha256_3_depth), + llki_base_addr = BigInt(CEPBaseAddresses.sha256_3_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.sha256_3_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_3_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_3_llki_sendrecv_addr), + dev_name = s"sha256_3") + )) ++ + + new chipyard.config.WithCEPRegisters ++ + + // Instantiation of the RSA core with or w/o the ARM compiled memories + new chipyard.config.WithRSA ++ + + // Instantiation of the Surrogate Root of Trust (with or w/o the ARM compiled memories) + new chipyard.config.WithSROT ++ + + // Overide the chip info + new WithDTS("mit-ll,cep-vc707", Nil) ++ + + // with reduced cache size, closes timing at 50 MHz + new WithFPGAFrequency(100) ++ + + // Include the VC707 Tweaks with CEP Registers enabled (passed to the bootrom build) + new WithVC707CEPTweaks ++ + + // Instantiate four big cores + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ + + // Default Chipyard AbstractConfig with L2 removed + new chipyard.config.AbstractNoL2Config +) + +class WithFPGAFrequency(fMHz: Double) extends Config( + new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. + new chipyard.config.WithMemoryBusFrequency(fMHz) +) + +class WithFPGAFreq25MHz extends WithFPGAFrequency(25) +class WithFPGAFreq50MHz extends WithFPGAFrequency(50) +class WithFPGAFreq75MHz extends WithFPGAFrequency(75) +class WithFPGAFreq100MHz extends WithFPGAFrequency(100) + diff --git a/fpga/src/main/scala/vc707/CustomOverlays.scala b/fpga/src/main/scala/vc707/CustomOverlays.scala new file mode 100644 index 0000000..195b4d3 --- /dev/null +++ b/fpga/src/main/scala/vc707/CustomOverlays.scala @@ -0,0 +1,66 @@ +//#************************************************************************ +//# Copyright 2022 Massachusets Institute of Technology +//# SPDX short identifier: BSD-2-Clause +//# +//# File Name: CustomOverlays.scala +//# Program: Common Evaluation Platform (CEP) +//# Description: Custom FPGA Shell overlays for VC707 +//# Notes: Modified from the Chipyard VCU118 CustomOverlays.scala +//#************************************************************************ + +package chipyard.fpga.vc707 + +import chisel3._ +import chisel3.experimental.{attach} + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} + +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.clocks._ + +/* Connect GPIOs to FPGA I/Os */ +abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) + extends GPIOPlacedOverlay(name, di, si) +{ + def shell: XilinxShell + + shell { InModuleBody { + (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) => + val iobuf = Module(new IOBUF) + iobuf.suggestName(s"gpio_iobuf") + attach(ioPin, iobuf.io.IO) + sinkPin.i.ival := iobuf.io.O + iobuf.io.T := !sinkPin.o.oe + iobuf.io.I := sinkPin.o.oval + } + } } +} + +class CustomGPIOVC707PlacedOverlay(val shell: VC707Shell, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) + extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + require(gpioNames.length == io.gpio.length) + + val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) => + val (pin, iostd, pullupEnable) = VC707GPIOs.pinMapping(name) + (pin, iostd, pullupEnable, IOPin(io)) + } + + packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, pullupEnable, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, iostd) + if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } + if (pullupEnable) { shell.xdc.addPullup(io) } + } } + } } +} + +class CustomGPIOVC707ShellPlacer(shell: VC707Shell, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) + extends GPIOShellPlacer[VC707Shell] { + def place(designInput: GPIODesignInput) = new CustomGPIOVC707PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) +} diff --git a/fpga/src/main/scala/vc707/GPIOs.scala b/fpga/src/main/scala/vc707/GPIOs.scala new file mode 100644 index 0000000..eb0249a --- /dev/null +++ b/fpga/src/main/scala/vc707/GPIOs.scala @@ -0,0 +1,47 @@ +//#************************************************************************ +//# Copyright 2022 Massachusets Institute of Technology +//# SPDX short identifier: BSD-2-Clause +//# +//# File Name: GPIOs.scala +//# Program: Common Evaluation Platform (CEP) +//# Description: Pin mappings for GPIO on the vc707 +//# Notes: Modified from the Chipyard VCU118 BringupGPIOs.scala +//#************************************************************************ + +package chipyard.fpga.vc707 + +import scala.collection.mutable.{LinkedHashMap} + +object VC707GPIOs { + // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD, add pullup resistor?) + + val pinMapping = LinkedHashMap( + "sw0" -> ("AV30", "LVCMOS18", false), // Bit0 - 8-Pole DIP Bit0 + "sw1" -> ("AY33", "LVCMOS18", false), // Bit1 - 8-Pole DIP Bit1 + "sw2" -> ("BA31", "LVCMOS18", false), // Bit2 - 8-Pole DIP Bit2 + "sw3" -> ("BA32", "LVCMOS18", false), // Bit3 - 8-Pole DIP Bit3 + "sw4" -> ("AW30", "LVCMOS18", false), // Bit4 - 8-Pole DIP Bit4 + "sw5" -> ("AY30", "LVCMOS18", false), // Bit5 - 8-Pole DIP Bit5 + "sw6" -> ("BA30", "LVCMOS18", false), // Bit6 - 8-Pole DIP Bit6 + "sw7" -> ("BB31", "LVCMOS18", false), // Bit7 - 8-Pole DIP Bit7 + "swN" -> ("AR40", "LVCMOS18", false), // Bit8 - GPIO Button N + "swE" -> ("AU38", "LVCMOS18", false), // Bit9 - GPIO Button E + "swS" -> ("AP40", "LVCMOS18", false), // Bit10 - GPIO Button S + "swW" -> ("AW40", "LVCMOS18", false), // Bit11 - GPIO Button W + "swC" -> ("AV39", "LVCMOS18", false), // Bit12 - GPIO Button C + "led0" -> ("AM39", "LVCMOS18", false), // Bit13 - GPIO LED 0 + "led1" -> ("AN39", "LVCMOS18", false), // Bit14 - GPIO LED 1 + "led2" -> ("AR37", "LVCMOS18", false), // Bit15 - GPIO LED 2 + "led3" -> ("AT37", "LVCMOS18", false), // Bit16 - GPIO LED 3 + "led4" -> ("AR35", "LVCMOS18", false), // Bit17 - GPIO LED 4 + "led5" -> ("AP41", "LVCMOS18", false), // Bit18 - GPIO LED 5 + "led6" -> ("AP42", "LVCMOS18", false), // Bit19 - GPIO LED 6 + "led7" -> ("AU39", "LVCMOS18", false) // Bit20 - GPIO LED 7 + ) + + // return list of names (ordered) + def names: Seq[String] = pinMapping.keys.toSeq + + // return number of GPIOs + def width: Int = pinMapping.size +} diff --git a/fpga/src/main/scala/vc707/HarnessBinders.scala b/fpga/src/main/scala/vc707/HarnessBinders.scala new file mode 100644 index 0000000..13eefac --- /dev/null +++ b/fpga/src/main/scala/vc707/HarnessBinders.scala @@ -0,0 +1,60 @@ +package chipyard.fpga.vc707 + +import chisel3._ +import chisel3.experimental.{BaseModule} + +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} + +import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} +import chipyard.harness.{OverrideHarnessBinder} + +import testchipip._ + +/*** UART ***/ +class WithUART extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + th match { case vc707th: VC707FPGATestHarnessImp => { + vc707th.vc707Outer.io_uart_bb.bundle <> ports.head + } } + } +}) + +/*** SPI ***/ +class WithSPISDCard extends OverrideHarnessBinder({ + (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { + th match { case vc707th: VC707FPGATestHarnessImp => { + vc707th.vc707Outer.io_spi_bb.bundle <> ports.head + } } + } +}) + +/*** GPIO ***/ +class WithGPIO extends OverrideHarnessBinder({ + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { + th match { case vc707th: VC707FPGATestHarnessImp => { + (vc707th.vc707Outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => + bb_io.bundle <> dut_io + } + } } + } +}) + +/*** Experimental DDR ***/ +class WithDDRMem extends OverrideHarnessBinder({ + (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + th match { case vc707th: VC707FPGATestHarnessImp => { + require(ports.size == 1) + + val bundles = vc707th.vc707Outer.ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> ports.head + } } + } +}) + diff --git a/fpga/src/main/scala/vc707/IOBinders.scala b/fpga/src/main/scala/vc707/IOBinders.scala new file mode 100644 index 0000000..e043fe4 --- /dev/null +++ b/fpga/src/main/scala/vc707/IOBinders.scala @@ -0,0 +1,63 @@ +package chipyard.fpga.vc707 + +import chisel3._ +import chisel3.experimental.{IO, DataMirror} + +import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody} +import freechips.rocketchip.subsystem.{BaseSubsystem} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} +import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} + +import chipyard.{CanHaveMasterTLMemPort} +import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} + +class WithUARTIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") } + (io_uart_pins_temp zip system.uart).map { case (io, sysio) => + io <> sysio + } + (io_uart_pins_temp, Nil) + } +}) + +class WithGPIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp) => { + val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") } + (io_gpio_pins_temp zip system.gpio).map { case (io, sysio) => + io <> sysio + } + (io_gpio_pins_temp, Nil) + } +}) + +class WithSPIIOPassthrough extends OverrideLazyIOBinder({ + (system: HasPeripherySPI) => { + // attach resource to 1st SPI + ResourceBinding { + Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) + } + + InModuleBody { + system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { + val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } + (io_spi_pins_temp zip system.spi).map { case (io, sysio) => + io <> sysio + } + (io_spi_pins_temp, Nil) + } } + } + } +}) + +class WithTLIOPassthrough extends OverrideIOBinder({ + (system: CanHaveMasterTLMemPort) => { + val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") + io_tl_mem_pins_temp <> system.mem_tl + (Seq(io_tl_mem_pins_temp), Nil) + } +}) diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala new file mode 100644 index 0000000..07947a3 --- /dev/null +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -0,0 +1,126 @@ +package chipyard.fpga.vc707 + +import chisel3._ +import chisel3.experimental.{IO} + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tilelink._ + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.gpio._ + +import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey} +import chipyard.iobinders.{HasIOBinders} +import chipyard.harness.{ApplyHarnessBinders} + +class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { + def dp = designParameters + + val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC707ShellPlacer(this, UARTShellInput(index = 0)))) + val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") + + // DOC include start: ClockOverlay + // place all clocks in the shell + require(dp(ClockInputOverlayKey).size >= 1) + val sysClkNode = dp(ClockInputOverlayKey).head.place(ClockInputDesignInput()).overlayOutput.node + + /*** Connect/Generate clocks ***/ + + // connect to the PLL that will generate multiple clocks + val harnessSysPLL = dp(PLLFactoryKey)() + harnessSysPLL := sysClkNode + + // create and connect to the dutClock + println(s"VC707 FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz") + val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey)) + val dutWrangler = LazyModule(new ResetWrangler) + val dutGroup = ClockGroup() + dutClock := dutWrangler.node := dutGroup := harnessSysPLL + // DOC include end: ClockOverlay + + /*** UART ***/ + + // DOC include start: UartOverlay + // 1st UART goes to the VC707 dedicated UART + + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + // DOC include end: UartOverlay + + /*** SPI ***/ + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) + dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) + + /*** GPIO ***/ + val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { + val maxGPIOSupport = 32 // max gpio per gpio chip + val names = VC707GPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) + Overlay(GPIOOverlayKey, new CustomGPIOVC707ShellPlacer(this, GPIOShellInput(), names)) + }) + + val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } + (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => + placer.place(GPIODesignInput(params, io_gpio_bb(i))) + } + + /*** DDR ***/ + val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr + + // connect 1 mem. channel to the FPGA DDR + val inParams = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(inParams.master)) + ddrNode := ddrClient + + // module implementation + override lazy val module = new VC707FPGATestHarnessImp(this) +} + +class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { + val vc707Outer = _outer + + val reset = IO(Input(Bool())) + _outer.xdc.addBoardPin(reset, "reset") + + val resetIBUF = Module(new IBUF) + resetIBUF.io.I := reset + + val sysclk: Clock = _outer.sysClkNode.out.head._1.clock + + val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) + _outer.sdc.addAsyncPath(Seq(powerOnReset)) + + _outer.pllReset := (resetIBUF.io.O) || powerOnReset + + // reset setup + val hReset = Wire(Reset()) + hReset := _outer.dutClock.in.head._1.reset + + val buildtopClock = _outer.dutClock.in.head._1.clock + val buildtopReset = WireInit(hReset) + val dutReset = hReset.asAsyncReset + val success = false.B + + childClock := buildtopClock + childReset := buildtopReset + + // harness binders are non-lazy + _outer.topDesign match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) + } + + // check the top-level reference clock is equal to the default + // non-exhaustive since you need all ChipTop clocks to equal the default + require(getRefClockFreq == p(DefaultClockFrequencyKey)) +} \ No newline at end of file diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 47a22dc..00450ad 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -1,9 +1,10 @@ package chipyard.fpga.vcu118 import sys.process._ +import math.min import freechips.rocketchip.config.{Config, Parameters} -import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} +import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem, WithDTS} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} @@ -11,10 +12,13 @@ import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} +import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import mitllBlocks.cep_addresses._ + import testchipip.{SerialTLKey} import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} @@ -23,50 +27,77 @@ class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) case VCU118ShellPMOD => "SDIO" + case PeripheryGPIOKey => { + if (VCU118GPIOs.width > 0) { + require(VCU118GPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) + val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000)) + val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32) + List.tabulate(((VCU118GPIOs.width - 1)/maxGPIOSupport) + 1)(n => { + GPIOParams(address = gpioAddrs(n), width = min(VCU118GPIOs.width - maxGPIOSupport*n, maxGPIOSupport)) + }) + } + else { + List.empty[GPIOParams] + } + } }) -class WithSystemModifications extends Config((site, here, up) => { +class WithCEPSystemModifications extends Config((site, here, up) => { case DTSTimebase => BigInt((1e6).toLong) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => // invoke makefile for sdboot val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong - val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin" + val make = s"make -C fpga/src/main/resources/vcu118/cep_sdboot PBUS_CLK=${freqMHz} bin" require (make.! == 0, "Failed to build bootrom") - p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") + p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/cep_sdboot/build/sdboot.bin") } case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size case SerialTLKey => None // remove serialized tl port }) -// DOC include start: AbstractVCU118 and Rocket -class WithVCU118Tweaks extends Config( +class WithVCU118CEPTweaks extends Config( // harness binders new WithUART ++ new WithSPISDCard ++ new WithDDRMem ++ + new WithGPIO ++ // io binders new WithUARTIOPassthrough ++ new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ + new WithGPIOIOPassthrough ++ // other configuration new WithDefaultPeripherals ++ new chipyard.config.WithTLBackingMemory ++ // use TL backing memory - new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size + new WithCEPSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ new WithFPGAFrequency(100) // default 100MHz freq ) -class RocketVCU118Config extends Config( - new WithVCU118Tweaks ++ - new chipyard.RocketConfig) -// DOC include end: AbstractVCU118 and Rocket +class RocketVCU118CEPConfig extends Config( + // Add the CEP registers + new chipyard.config.WithCEPRegisters ++ + new chipyard.config.WithAES ++ + new chipyard.config.WithSROTFPGA ++ + + // Overide the chip info + new WithDTS("mit-ll,cep-vcu118", Nil) ++ -class BoomVCU118Config extends Config( - new WithFPGAFrequency(50) ++ - new WithVCU118Tweaks ++ - new chipyard.MegaBoomConfig) + // with reduced cache size, closes timing at 50 MHz + new WithFPGAFrequency(100) ++ + + // Include the VCU118 Tweaks with CEP Registers enabled (passed to the bootrom build) + new WithVCU118CEPTweaks ++ + + // Instantiate one big core + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + + // Default Chipyard AbstractConfig with L2 removed + new chipyard.config.AbstractNoL2Config +) +// DOC include end: AbstractVCU118 and Rocket class WithFPGAFrequency(fMHz: Double) extends Config( new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala index a58fb42..a121d0c 100644 --- a/fpga/src/main/scala/vcu118/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -1,6 +1,7 @@ package chipyard.fpga.vcu118 import chisel3._ +import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters, Field} @@ -10,8 +11,52 @@ import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.clocks._ + import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} +/* Connect GPIOs to FPGA I/Os */ +abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) + extends GPIOPlacedOverlay(name, di, si) +{ + def shell: XilinxShell + + shell { InModuleBody { + (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) => + val iobuf = Module(new IOBUF) + iobuf.suggestName(s"gpio_iobuf") + attach(ioPin, iobuf.io.IO) + sinkPin.i.ival := iobuf.io.O + iobuf.io.T := !sinkPin.o.oe + iobuf.io.I := sinkPin.o.oval + } + } } +} + +class CustomGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) + extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + require(gpioNames.length == io.gpio.length) + + val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) => + val (pin, iostd, pullupEnable) = VCU118GPIOs.pinMapping(name) + (pin, iostd, pullupEnable, IOPin(io)) + } + + packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, pullupEnable, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, iostd) + if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } + if (pullupEnable) { shell.xdc.addPullup(io) } + } } + } } +} + +class CustomGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) + extends GPIOShellPlacer[VCU118ShellBasicOverlays] { + def place(designInput: GPIODesignInput) = new CustomGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) +} + class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) { diff --git a/fpga/src/main/scala/vcu118/GPIOs.scala b/fpga/src/main/scala/vcu118/GPIOs.scala new file mode 100644 index 0000000..b2a17e3 --- /dev/null +++ b/fpga/src/main/scala/vcu118/GPIOs.scala @@ -0,0 +1,33 @@ +package chipyard.fpga.vcu118 + +import scala.collection.mutable.{LinkedHashMap} + +object VCU118GPIOs { + // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD, add pullup resistor?) + val pinMapping = LinkedHashMap( + // these connect to LEDs and switches on the VCU118 (and use 1.2V) + "sw0" -> ("B17", "LVCMOS12", false), // Bit0 - 4-Pole DIP Bit 0 + "sw1" -> ("G16", "LVCMOS12", false), // Bit1 - 4-Pole DIP Bit 1 + "sw2" -> ("J16", "LVCMOS12", false), // Bit2 - 4-Pole DIP Bit 2 + "sw3" -> ("D21", "LVCMOS12", false), // Bit3 - 4-Pole DIP Bit 3 + "swN" -> ("BB24", "LVCMOS18", false), // Bit4 - GPIO Button N + "swE" -> ("BE23", "LVCMOS18", false), // Bit5 - GPIO Button E + "swW" -> ("BF22", "LVCMOS18", false), // Bit6 - GPIO Button W + "swS" -> ("BE22", "LVCMOS18", false), // Bit7 - GPIO Button S + "swC" -> ("BD23", "LVCMOS18", false), // Bit8 - GPIO Button C + "led0" -> ("AT32", "LVCMOS12", false), // Bit9 - GPIO LED 0 + "led1" -> ("AV34", "LVCMOS12", false), // Bit10 - GPIO LED 1 + "led2" -> ("AY30", "LVCMOS12", false), // Bit11 - GPIO LED 2 + "led3" -> ("BB32", "LVCMOS12", false), // Bit12 - GPIO LED 3 + "led4" -> ("BF32", "LVCMOS12", false), // Bit13 - GPIO LED 4 + "led5" -> ("AU37", "LVCMOS12", false), // Bit14 - GPIO LED 5 + "led6" -> ("AV36", "LVCMOS12", false), // Bit15 - GPIO LED 6 + "led7" -> ("BA37", "LVCMOS12", false) // Bit16 - GPIO LED 7 + ) + + // return list of names (ordered) + def names: Seq[String] = pinMapping.keys.toSeq + + // return number of GPIOs + def width: Int = pinMapping.size +} diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index d60af21..54810cb 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -8,10 +8,14 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} import chipyard.harness.{OverrideHarnessBinder} +import testchipip._ + + /*** UART ***/ class WithUART extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { @@ -21,6 +25,17 @@ class WithUART extends OverrideHarnessBinder({ } }) +/*** GPIO ***/ +class WithGPIO extends OverrideHarnessBinder({ + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { + th match { case vcu118th: VCU118FPGATestHarnessImp => { + (vcu118th.vcu118Outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => + bb_io.bundle <> dut_io + } + } } + } +}) + /*** SPI ***/ class WithSPISDCard extends OverrideHarnessBinder({ (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala index a1f67bc..c145377 100644 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} import chipyard.{CanHaveMasterTLMemPort} @@ -24,6 +25,16 @@ class WithUARTIOPassthrough extends OverrideIOBinder({ } }) +class WithGPIOIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp) => { + val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") } + (io_gpio_pins_temp zip system.gpio).map { case (io, sysio) => + io <> sysio + } + (io_gpio_pins_temp, Nil) + } +}) + class WithSPIIOPassthrough extends OverrideLazyIOBinder({ (system: HasPeripherySPI) => { // attach resource to 1st SPI diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 2ec405b..ebc4152 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -69,6 +69,19 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) // DOC include end: UartOverlay + /*** GPIO ***/ + + val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { + val maxGPIOSupport = 32 // max gpio per gpio chip + val names = VCU118GPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) + Overlay(GPIOOverlayKey, new CustomGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) + }) + + val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } + (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => + placer.place(GPIODesignInput(params, io_gpio_bb(i))) + } + /*** SPI ***/ // 1st SPI goes to the VCU118 SDIO port diff --git a/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala b/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala deleted file mode 100644 index 40c33bf..0000000 --- a/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala +++ /dev/null @@ -1,28 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import scala.collection.mutable.{LinkedHashMap} - -object BringupGPIOs { - // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD, add pullup resistor?) - val pinMapping = LinkedHashMap( - // these connect to LEDs and switches on the VCU118 (and use 1.2V) - "led0" -> ("AT32", "LVCMOS12", false), // 0 - "led1" -> ("AV34", "LVCMOS12", false), // 1 - "led2" -> ("AY30", "LVCMOS12", false), // 2 - "led3" -> ("BB32", "LVCMOS12", false), // 3 - "led4" -> ("BF32", "LVCMOS12", false), // 4 - "led5" -> ("AU37", "LVCMOS12", false), // 5 - "led6" -> ("AV36", "LVCMOS12", false), // 6 - "led7" -> ("BA37", "LVCMOS12", false), // 7 - "sw0" -> ("B17", "LVCMOS12", false), // 8 - "sw1" -> ("G16", "LVCMOS12", false), // 9 - "sw2" -> ("J16", "LVCMOS12", false), // 10 - "sw3" -> ("D21", "LVCMOS12", false) // 11 - ) - - // return list of names (ordered) - def names: Seq[String] = pinMapping.keys.toSeq - - // return number of GPIOs - def width: Int = pinMapping.size -} diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala deleted file mode 100644 index 62c2af3..0000000 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ /dev/null @@ -1,97 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import math.min - -import freechips.rocketchip.config.{Config, Parameters} -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.subsystem.{MasterPortParams} - -import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} -import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} -import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} - -import sifive.fpgashells.shell.{DesignKey} -import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} - -import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} - -import chipyard.{BuildSystem} - -import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size} - -class WithBringupPeripherals extends Config((site, here, up) => { - case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) - case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) - case PeripheryGPIOKey => { - if (BringupGPIOs.width > 0) { - require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) - val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000)) - val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32) - List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => { - GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport)) - }) - } - else { - List.empty[GPIOParams] - } - } - case TSIClockMaxFrequencyKey => 100 - case PeripheryTSIHostKey => List( - TSIHostParams( - offchipSerialIfWidth = 4, - mmioBaseAddress = BigInt(0x64006000), - mmioSourceId = 1 << 13, // manager source - serdesParams = TSIHostSerdesParams( - clientPortParams = TLMasterPortParameters.v1( - clients = Seq(TLMasterParameters.v1( - name = "tl-tsi-host-serdes", - sourceId = IdRange(0, (1 << 13))))), - managerPortParams = TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip - regionType = RegionType.UNCACHED, - executable = true, - supportsGet = TransferSizes(1, 64), - supportsPutFull = TransferSizes(1, 64), - supportsPutPartial = TransferSizes(1, 64), - supportsAcquireT = TransferSizes(1, 64), - supportsAcquireB = TransferSizes(1, 64), - supportsArithmetic = TransferSizes(1, 64), - supportsLogical = TransferSizes(1, 64))), - endSinkId = 1 << 6, // manager sink - beatBytes = 8)), - targetMasterPortParams = MasterPortParams( - base = BigInt("80000000", 16), - size = site(VCU118DDR2Size), - beatBytes = 8, // comes from test chip - idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG - )) -}) - -class WithBringupVCU118System extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top -}) - -class WithBringupAdditions extends Config( - new WithBringupUART ++ - new WithBringupI2C ++ - new WithBringupGPIO ++ - new WithBringupTSIHost ++ - new WithTSITLIOPassthrough ++ - new WithI2CIOPassthrough ++ - new WithGPIOIOPassthrough ++ - new WithBringupPeripherals ++ - new WithBringupVCU118System) - -class RocketBringupConfig extends Config( - new WithBringupAdditions ++ - new WithVCU118Tweaks ++ - new chipyard.RocketConfig) - -class BoomBringupConfig extends Config( - new WithFPGAFrequency(50) ++ - new WithBringupAdditions ++ - new WithVCU118Tweaks ++ - new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala deleted file mode 100644 index 43d559f..0000000 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ /dev/null @@ -1,204 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.experimental.{attach} - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} - -import sifive.fpgashells.shell._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.clocks._ -import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} - -import testchipip.{TSIHostWidgetIO} - -import chipyard.fpga.vcu118.{FMCPMap} - -/* Connect the I2C to certain FMC pins */ -class BringupI2CVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) - extends I2CXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - require(shellInput.index == 0) // only support 1 I2C <-> FMC connection - val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2"))) - val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)), - (i2cLocations(shellInput.index)(1), IOPin(io.sda))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - shell.xdc.addIOB(io) - } } - } } -} - -class BringupI2CVCU118ShellPlacer(val shell: VCU118ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName) - extends I2CShellPlacer[VCU118ShellBasicOverlays] -{ - def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} - -/* Connect the UART to certain FMC pins */ -class BringupUARTVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) - extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) -{ - shell { InModuleBody { - val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused - (FMCPMap("E10"), IOPin(io.rtsn.get)), // unused - (FMCPMap("C15"), IOPin(io.rxd)), - (FMCPMap("C14"), IOPin(io.txd))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - shell.xdc.addIOB(io) - } } - - // add pullup on ctsn (ctsn is an input that is not used or driven) - packagePinsWithPackageIOs take 1 foreach { case (pin, io) => { - shell.xdc.addPullup(io) - } } - } } -} - -class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName) - extends UARTShellPlacer[VCU118ShellBasicOverlays] { - def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} - -/* Connect GPIOs to FPGA I/Os */ -abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) - extends GPIOPlacedOverlay(name, di, si) -{ - def shell: XilinxShell - - shell { InModuleBody { - (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) => - val iobuf = Module(new IOBUF) - iobuf.suggestName(s"gpio_iobuf") - attach(ioPin, iobuf.io.IO) - sinkPin.i.ival := iobuf.io.O - iobuf.io.T := !sinkPin.o.oe - iobuf.io.I := sinkPin.o.oval - } - } } -} - -class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) - extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - require(gpioNames.length == io.gpio.length) - - val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) => - val (pin, iostd, pullupEnable) = BringupGPIOs.pinMapping(name) - (pin, iostd, pullupEnable, IOPin(io)) - } - - packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, pullupEnable, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, iostd) - if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } - if (pullupEnable) { shell.xdc.addPullup(io) } - } } - } } -} - -class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) - extends GPIOShellPlacer[VCU118ShellBasicOverlays] { - def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) -} - -case class TSIHostShellInput() -case class TSIHostDesignInput( - serialIfWidth: Int, - node: BundleBridgeSource[TSIHostWidgetIO] - )( - implicit val p: Parameters) -case class TSIHostOverlayOutput() -trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] - -case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil) - -abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput) - extends IOPlacedOverlay[IO, TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] -{ - implicit val p = di.p -} - -case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB -class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) - extends TSIHostPlacedOverlay[TSIHostWidgetIO](name, designInput, shellInput) -{ - val tlTsiSerialSink = di.node.makeSink() - val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.serialIfWidth)) - val topTSIIONode = shell { tsiIoNode.makeSink() } - - def overlayOutput = TSIHostOverlayOutput() - def ioFactory = new TSIHostWidgetIO(di.serialIfWidth) - - InModuleBody { - // connect TSI serial - val tsiSourcePort = tsiIoNode.bundle - val tsiSinkPort = tlTsiSerialSink.bundle - tsiSinkPort.serial_clock := tsiSourcePort.serial_clock - tsiSourcePort.serial.out.bits := tsiSinkPort.serial.out.bits - tsiSourcePort.serial.out.valid := tsiSinkPort.serial.out.valid - tsiSinkPort.serial.out.ready := tsiSourcePort.serial.out.ready - tsiSinkPort.serial.in.bits := tsiSourcePort.serial.in.bits - tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid - tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready - } -} - -case object TSIClockMaxFrequencyKey extends Field[Int](50) // in MHz -class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) - extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) -{ - // connect the TSI port - shell { InModuleBody { - // connect TSI signals - val tsiPort = topTSIIONode.bundle - io <> tsiPort - - require(di.serialIfWidth == 4) - - val clkIo = IOPin(io.serial_clock) - val packagePinsWithPackageIOs = Seq( - (FMCPMap("D8"), clkIo), - (FMCPMap("D17"), IOPin(io.serial.out.ready)), - (FMCPMap("D18"), IOPin(io.serial.out.valid)), - (FMCPMap("D11"), IOPin(io.serial.out.bits, 0)), - (FMCPMap("D12"), IOPin(io.serial.out.bits, 1)), - (FMCPMap("D14"), IOPin(io.serial.out.bits, 2)), - (FMCPMap("D15"), IOPin(io.serial.out.bits, 3)), - (FMCPMap("D26"), IOPin(io.serial.in.ready)), - (FMCPMap("D27"), IOPin(io.serial.in.valid)), - (FMCPMap("D20"), IOPin(io.serial.in.bits, 0)), - (FMCPMap("D21"), IOPin(io.serial.in.bits, 1)), - (FMCPMap("D23"), IOPin(io.serial.in.bits, 2)), - (FMCPMap("D24"), IOPin(io.serial.in.bits, 3))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - } } - - // Don't add an IOB to the clock - (packagePinsWithPackageIOs take 1) foreach { case (pin, io) => { - shell.xdc.addIOB(io) - } } - - shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequencyKey)) - shell.sdc.addGroup(pins = Seq(clkIo)) - shell.xdc.clockDedicatedRouteFalse(clkIo) - } } -} - -class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val shellInput: TSIHostShellInput)(implicit val valName: ValName) - extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] { - def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala deleted file mode 100644 index 5b554f5..0000000 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ /dev/null @@ -1,26 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -import chipyard.{DigitalTop, DigitalTopModule} - -// ------------------------------------ -// Bringup VCU118 DigitalTop -// ------------------------------------ - -class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.i2c.HasPeripheryI2C - with testchipip.HasPeripheryTSIHostWidget -{ - override lazy val module = new BringupVCU118DigitalTopModule(this) -} - -class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala deleted file mode 100644 index 27689ca..0000000 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ /dev/null @@ -1,70 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.experimental.{Analog, IO, BaseModule} - -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} -import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} -import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} - -import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} - -import chipyard.{HasHarnessSignalReferences} -import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} - -/*** UART ***/ -class WithBringupUART extends ComposeHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { - th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - require(ports.size == 2) - - vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last - } } - } -}) - -/*** I2C ***/ -class WithBringupI2C extends OverrideHarnessBinder({ - (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { - th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - require(ports.size == 1) - - vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head - } } - } -}) - -/*** GPIO ***/ -class WithBringupGPIO extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { - th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - (vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) => - bb_io.bundle <> dut_io - } - } } - } -}) - -/*** TSI Host Widget ***/ -class WithBringupTSIHost extends OverrideHarnessBinder({ - (system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { - th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link - - ports.head match { case tlPort: HeterogeneousBag[TLBundle] => - val tsiBundles = vcu118th.bringupOuter.tsiDdrClient.out.map(_._1) - val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType))) - tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io } - tsiDdrClientBundle <> tlPort - } - - ports.last match { case serialPort: TSIHostWidgetIO => - vcu118th.bringupOuter.io_tsi_serial_bb.bundle <> serialPort - } - } } - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala deleted file mode 100644 index 87763cd..0000000 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ /dev/null @@ -1,47 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.experimental.{IO, DataMirror} - -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} -import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} - -import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} - -import chipyard.iobinders.{OverrideIOBinder} - -class WithGPIOIOPassthrough extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => { - val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") } - (io_gpio_pins_temp zip system.gpio).map { case (io, sysio) => - io <> sysio - } - (io_gpio_pins_temp, Nil) - } -}) - -class WithI2CIOPassthrough extends OverrideIOBinder({ - (system: HasPeripheryI2CModuleImp) => { - val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } - (io_i2c_pins_temp zip system.i2c).map { case (io, sysio) => - io <> sysio - } - (io_i2c_pins_temp, Nil) - } -}) - -class WithTSITLIOPassthrough extends OverrideIOBinder({ - (system: HasPeripheryTSIHostWidget) => { - require(system.tsiTLMem.size == 1) - val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave") - io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head - - require(system.tsiSerial.size == 1) - val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial") - io_tsi_serial_pins_temp <> system.tsiSerial.head - (Seq(io_tsi_tl_mem_pins_temp, io_tsi_serial_pins_temp), Nil) - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala deleted file mode 100644 index 2406cb7..0000000 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ /dev/null @@ -1,100 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ - -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks._ - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.gpio._ - -import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter} - -import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer} - -import chipyard.{ChipTop} - -class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness { - - /*** UART ***/ - - require(dp(PeripheryUARTKey).size == 2) - - // 2nd UART goes to the FMC UART - - val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - - val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) - dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb)) - - /*** I2C ***/ - - val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) - - val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) - dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) - - /*** GPIO ***/ - - val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { - val maxGPIOSupport = 32 // max gpio per gpio chip - val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) - Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) - }) - - val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } - (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => - placer.place(GPIODesignInput(params, io_gpio_bb(i))) - } - - /*** TSI Host Widget ***/ - require(dp(PeripheryTSIHostKey).size == 1) - - // use the 2nd system clock for the 2nd DDR - val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node - - val ddr2PLL = dp(PLLFactoryKey)() - ddr2PLL := sysClk2Node - - val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - val ddr2Wrangler = LazyModule(new ResetWrangler) - val ddr2Group = ClockGroup() - ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL - - val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) - - val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr - - val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth))) - dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb)) - - // connect 1 mem. channel to the FPGA DDR - val inTsiParams = topDesign match { case td: ChipTop => - td.lazySystem match { case lsys: HasPeripheryTSIHostWidget => - lsys.tsiMemTLNodes.head.edges.in(0) - } - } - val tsiDdrClient = TLClientNode(Seq(inTsiParams.master)) - (ddr2Node - := TLFragmenter(8,64,holdFirstDeny=true) - := TLCacheCork() - := TLAtomicAutomata(passthrough=false) - := TLSinkSetter(64) - := tsiDdrClient) - - // module implementation - override lazy val module = new BringupVCU118FPGATestHarnessImp(this) -} - -class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { - lazy val bringupOuter = _outer -} diff --git a/generators/boom b/generators/boom deleted file mode 160000 index ad64c54..0000000 --- a/generators/boom +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ad64c5419151e5e886daee7084d8399713b46b4b diff --git a/generators/chipyard/src/main/scala/config/CEPConfigs.scala b/generators/chipyard/src/main/scala/config/CEPConfigs.scala index 5706b8b..14c8c99 100644 --- a/generators/chipyard/src/main/scala/config/CEPConfigs.scala +++ b/generators/chipyard/src/main/scala/config/CEPConfigs.scala @@ -1,3 +1,13 @@ +//------------------------------------------------------------------------------------- +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: CEPConfigs.scala +// Program: Common Evaluation Platform (CEP) +// Description: CEP specific chipyard configurations +// Notes: +//-------------------------------------------------------------------------------------- + package chipyard import freechips.rocketchip.config.{Config} @@ -121,8 +131,3 @@ class CEPRocketConfig extends Config( ) -// Tweak to the default Rocket Config that removes the L2 Cache (and uses a medium core) -class RocketNoL2Config extends Config( - new freechips.rocketchip.subsystem.WithNMedCores(1) ++ // single "medium" rocket core - new chipyard.config.AbstractNoL2Config) - diff --git a/generators/cva6 b/generators/cva6 deleted file mode 160000 index 705c48a..0000000 --- a/generators/cva6 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 705c48a1dacc011cef9b4d021a88b4948e7f9b64 diff --git a/generators/fft-generator b/generators/fft-generator deleted file mode 160000 index 4c335ff..0000000 --- a/generators/fft-generator +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 4c335ff6aba3734fcc373548ea39f4c798f70cea diff --git a/generators/gemmini b/generators/gemmini deleted file mode 160000 index c47cb7f..0000000 --- a/generators/gemmini +++ /dev/null @@ -1 +0,0 @@ -Subproject commit c47cb7f3eb5c18390f176f3a53c43c8546d487d2 diff --git a/generators/hwacha b/generators/hwacha deleted file mode 160000 index 7cc6354..0000000 --- a/generators/hwacha +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7cc6354351457c6b5bf186cdd34297ee5caeb22a diff --git a/generators/ibex b/generators/ibex deleted file mode 160000 index 0eac465..0000000 --- a/generators/ibex +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 0eac465e3e9e06eceba111b4b43d5178ede817c2 diff --git a/generators/icenet b/generators/icenet deleted file mode 160000 index e14c1e8..0000000 --- a/generators/icenet +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e14c1e8c54851d3fa7bc55fbbc6fc48873a3b2a9 diff --git a/generators/mitll-blocks/src/main/scala/aes.scala b/generators/mitll-blocks/src/main/scala/aes.scala index a479f92..54b2a42 100644 --- a/generators/mitll-blocks/src/main/scala/aes.scala +++ b/generators/mitll-blocks/src/main/scala/aes.scala @@ -85,7 +85,7 @@ class aesTLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) ex regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/cep_addresses.scala b/generators/mitll-blocks/src/main/scala/cep_addresses.scala index e1bb7bb..e900850 100644 --- a/generators/mitll-blocks/src/main/scala/cep_addresses.scala +++ b/generators/mitll-blocks/src/main/scala/cep_addresses.scala @@ -32,6 +32,11 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ +object CEPVersion { + val CEP_MAJOR_VERSION = 0x04 + val CEP_MINOR_VERSION = 0x20 +} + object CEPBaseAddresses { val scratchpad_base_addr = 0x64800000L val scratchpad_depth = 0x0001FFFFL @@ -159,11 +164,6 @@ object CEPBaseAddresses { val srot_base_depth = 0x0000ffffL } -object CEPVersion { - val CEP_MAJOR_VERSION = 0x04 - val CEP_MINOR_VERSION = 0x10 -} - object AESAddresses { val aes_ctrlstatus_addr = 0x0000 val aes_pt0_addr = 0x0008 diff --git a/generators/mitll-blocks/src/main/scala/des3.scala b/generators/mitll-blocks/src/main/scala/des3.scala index 0f7a5fa..858b9aa 100644 --- a/generators/mitll-blocks/src/main/scala/des3.scala +++ b/generators/mitll-blocks/src/main/scala/des3.scala @@ -85,12 +85,12 @@ class des3TLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) e regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order beatBytes = coreattachparams.llki_bus.beatBytes))) - + // Create the RegisterRouter node val slave_node = TLRegisterNode( address = Seq(AddressSet( diff --git a/generators/mitll-blocks/src/main/scala/dft.scala b/generators/mitll-blocks/src/main/scala/dft.scala index cbed89b..bd30e0b 100644 --- a/generators/mitll-blocks/src/main/scala/dft.scala +++ b/generators/mitll-blocks/src/main/scala/dft.scala @@ -90,7 +90,7 @@ class dftTLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) ex regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/fir.scala b/generators/mitll-blocks/src/main/scala/fir.scala index 51f82a6..047134a 100644 --- a/generators/mitll-blocks/src/main/scala/fir.scala +++ b/generators/mitll-blocks/src/main/scala/fir.scala @@ -90,7 +90,7 @@ class firTLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) ex regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/gps.scala b/generators/mitll-blocks/src/main/scala/gps.scala index 8367229..6d0911a 100644 --- a/generators/mitll-blocks/src/main/scala/gps.scala +++ b/generators/mitll-blocks/src/main/scala/gps.scala @@ -86,7 +86,7 @@ class gpsTLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) ex regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/idft.scala b/generators/mitll-blocks/src/main/scala/idft.scala index 2035488..72e55f1 100644 --- a/generators/mitll-blocks/src/main/scala/idft.scala +++ b/generators/mitll-blocks/src/main/scala/idft.scala @@ -90,7 +90,7 @@ class idftTLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) e regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/iir.scala b/generators/mitll-blocks/src/main/scala/iir.scala index b4d0815..9efab06 100644 --- a/generators/mitll-blocks/src/main/scala/iir.scala +++ b/generators/mitll-blocks/src/main/scala/iir.scala @@ -90,7 +90,7 @@ class iirTLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) ex regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/md5.scala b/generators/mitll-blocks/src/main/scala/md5.scala index b584b4b..31c2c23 100644 --- a/generators/mitll-blocks/src/main/scala/md5.scala +++ b/generators/mitll-blocks/src/main/scala/md5.scala @@ -86,7 +86,7 @@ class md5TLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) ex regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/rsa.scala b/generators/mitll-blocks/src/main/scala/rsa.scala index 3eedb57..336e8c8 100644 --- a/generators/mitll-blocks/src/main/scala/rsa.scala +++ b/generators/mitll-blocks/src/main/scala/rsa.scala @@ -85,7 +85,7 @@ class rsaTLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) ex regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/sha256.scala b/generators/mitll-blocks/src/main/scala/sha256.scala index 1070617..86941ca 100644 --- a/generators/mitll-blocks/src/main/scala/sha256.scala +++ b/generators/mitll-blocks/src/main/scala/sha256.scala @@ -86,7 +86,7 @@ class sha256TLModule(coreattachparams: COREAttachParams)(implicit p: Parameters) regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/mitll-blocks/src/main/scala/srot.scala b/generators/mitll-blocks/src/main/scala/srot.scala index d44f91a..ab33c1e 100644 --- a/generators/mitll-blocks/src/main/scala/srot.scala +++ b/generators/mitll-blocks/src/main/scala/srot.scala @@ -89,7 +89,7 @@ class srotTLModule(srotattachparams: SROTAttachParams)(implicit p: Parameters) e regionType = RegionType.IDEMPOTENT, supportsGet = TransferSizes(1, 8), supportsPutFull = TransferSizes(1, 8), - supportsPutPartial = TransferSizes(1, 8), + supportsPutPartial = TransferSizes.none, supportsArithmetic = TransferSizes.none, supportsLogical = TransferSizes.none, fifoId = Some(0))), // requests are handled in order diff --git a/generators/nvdla b/generators/nvdla deleted file mode 160000 index 2b17011..0000000 --- a/generators/nvdla +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 2b17011b266025704b958efeeca2363c0cdd446d diff --git a/generators/riscv-sodor b/generators/riscv-sodor deleted file mode 160000 index 5643a8e..0000000 --- a/generators/riscv-sodor +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 5643a8e245d562647f626295ad2dab9b4d5f6a13 diff --git a/generators/rocket-chip b/generators/rocket-chip deleted file mode 160000 index 114325b..0000000 --- a/generators/rocket-chip +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 114325b27cfe5312c86a8a325b187be9455a62af diff --git a/generators/sha3 b/generators/sha3 deleted file mode 160000 index 88ada85..0000000 --- a/generators/sha3 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 88ada85a84253434ea5cef729d90cd74796aa442 diff --git a/generators/sifive-blocks b/generators/sifive-blocks deleted file mode 160000 index 545a396..0000000 --- a/generators/sifive-blocks +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 545a396f3486132b01ceef3cbce2085608984478 diff --git a/generators/sifive-cache b/generators/sifive-cache deleted file mode 160000 index e3a3000..0000000 --- a/generators/sifive-cache +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e3a3000cc1fd4cdf3a4e638e4d081b8aae94ebf0 diff --git a/generators/testchipip b/generators/testchipip deleted file mode 160000 index 03535f5..0000000 --- a/generators/testchipip +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 03535f56a6318236ab6abf5342d78eecf453984d diff --git a/opentitan b/opentitan deleted file mode 160000 index 14b1b20..0000000 --- a/opentitan +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 14b1b20e8a165461c87fd9ca925f90b21a48f400 diff --git a/scripts/tutorial-patches/RocketConfigs.scala.patch b/scripts/tutorial-patches/RocketConfigs.scala.patch deleted file mode 100644 index 351f8ca..0000000 --- a/scripts/tutorial-patches/RocketConfigs.scala.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -index 8e6e486..fc3a811 100644 ---- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala -+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -@@ -105,7 +105,7 @@ class GB1MemoryRocketConfig extends Config( - - // DOC include start: Sha3Rocket - class Sha3RocketConfig extends Config( -- new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator -+// new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - // DOC include end: Sha3Rocket diff --git a/sims/cep_cosim/README.md b/sims/cep_cosim/README.md index c86b34e..6e0ae81 100644 --- a/sims/cep_cosim/README.md +++ b/sims/cep_cosim/README.md @@ -168,23 +168,4 @@ The following variables can be overwritten (or changed in cep_buildHW.make). Th XCELIUM_INSTALL ?= /brewhouse/cad4/x86_64/Cadence/${XCELIUM_VERSION} QUESTASIM_PATH ?= /opt/questa-2019.1/questasim/bin -### Test Status / Known Issues -Cadence XCellium on RHEL7 *occasionally* fails some of the bareMetal tests. Root cause has not been determined, but it is recommended that the test be re-run. - -The following tests current "fail" with the notes contained therein: -* ./testSuites/bfmTests/macroMix - GPS tests fail. Updated will be rolled into the next release. - -The following tests are currently non-functional and are thus excluded from the various testSuite *TEST_LIST* -* ./testSuites/bfmTests/srotErrorTest -* ./testSuites/bareMetalTests/plicPrioIntr -* ./testSuites/bareMetalTests/extIntr -* ./testSuites/bareMetalTests/lsrcOps -* ./testSuites/isaTests/dtmTest - -The following tests run, but currently fail: -* ./testSuites/bareMetalTests/plicTest -* ./testSuites/isaTests/rv64mi-p-csr -* ./testSuites/isaTests/rv64si-p-csr -* ./testSuites/isaTests/*all -v tests* (virtual mode tests) - ### Return to the Root CEP [readme](../../README.md). diff --git a/sims/cep_cosim/bootrom/Makefile b/sims/cep_cosim/bootrom/Makefile index 7e27183..b951781 100644 --- a/sims/cep_cosim/bootrom/Makefile +++ b/sims/cep_cosim/bootrom/Makefile @@ -22,22 +22,21 @@ ROOT_DIR := $(strip $(shell cd .; pwd)) COSIM_TOP_DIR := $(strip $(shell cd ..; pwd)) CONVERT_BOOTROM := ${COSIM_TOP_DIR}/bin/convert-bootrom.py -BOOTROM_IMG = bootrom.rv64.img bootrom.rv32.img -BOOTROM_DUMP = bootrom.rv64.dump bootrom.rv32.dump -BOOTROM_ELF = bootrom.rv64.elf bootrom.rv32.elf +BOOTROM_IMG = bootrom.rv64.img +BOOTROM_DUMP = bootrom.rv64.dump +BOOTROM_ELF = bootrom.rv64.elf CEP_LDS_FILE = ${ROOT_DIR}/cep_boot.lds CC = $(RISCV)/bin/riscv64-unknown-elf-gcc OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy OBJDUMP = $(RISCV)/bin/riscv64-unknown-elf-objdump -CFLAGS = -mcmodel=medany -O2 -std=gnu11 -Wall -fno-common -g +CFLAGS = -mcmodel=medany -O2 -fno-common -fno-builtin-printf -fno-builtin-puts -Wall -Wno-unused-function CFLAGS += -DENTROPY=0 -DNONSMP_HART=0 CFLAGS += -I $(ROOT_DIR)/include -I ${ROOT_DIR} -CFLAGS_RV64 = -mabi=lp64 -march=rv64ima -CFLAGS_RV32 = -mabi=ilp32 -march=rv32ima -LFLAGS = -static -nostdlib -nostartfiles -T ${CEP_LDS_FILE} +CFLAGS_RV64 += -mabi=lp64 -march=rv64ima +LFLAGS = -static -nostdlib -nostartfiles -lgcc -T ${CEP_LDS_FILE} default: bootrom_info img dump elf rcf @@ -75,11 +74,8 @@ rcf: img %.dump: %.elf $(OBJDUMP) -D -S $< > $@ -bootrom.rv32.elf: head.S kprintf.c sd.c ${CEP_LDS_FILE} ${BOOTROM_CHECK} - $(CC) $(CFLAGS) $(CFLAGS_RV32) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S sd.c kprintf.c - bootrom.rv64.elf: head.S kprintf.c sd.c ${CEP_LDS_FILE} ${BOOTROM_CHECK} - $(CC) $(CFLAGS) $(CFLAGS_RV64) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S sd.c kprintf.c + $(CC) $(CFLAGS) $(CFLAGS_RV64) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S sd.c kprintf.c syscalls_bootrom.c # Use to force rebuilds for rules that include this dependency .force: diff --git a/sims/cep_cosim/bootrom/head.S b/sims/cep_cosim/bootrom/head.S index fce3cf3..865fb6f 100644 --- a/sims/cep_cosim/bootrom/head.S +++ b/sims/cep_cosim/bootrom/head.S @@ -18,7 +18,7 @@ _prog_start: // Initialize the stack pointer - li sp, (scratchpad_base_addr + scratchpad_sp_offset) + li sp, (MEMORY_MEM_ADDR + MEMORY_MEM_SP_OFFSET) // Call the main function witha single core smp_pause(s1, s2) @@ -29,7 +29,7 @@ _prog_start: la a1, dtb // dtb address for next level bootloader // Jump to main memory - li s1, scratchpad_base_addr + li s1, MEMORY_MEM_ADDR jr s1 .section .dtb diff --git a/sims/cep_cosim/bootrom/include/encoding.h b/sims/cep_cosim/bootrom/include/encoding.h new file mode 100644 index 0000000..dcf9162 --- /dev/null +++ b/sims/cep_cosim/bootrom/include/encoding.h @@ -0,0 +1,1471 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +//DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +//DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/sims/cep_cosim/bootrom/include/kprintf.h b/sims/cep_cosim/bootrom/include/kprintf.h new file mode 100644 index 0000000..2733e2d --- /dev/null +++ b/sims/cep_cosim/bootrom/include/kprintf.h @@ -0,0 +1,28 @@ +// See LICENSE.Sifive for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +#define UART_RXEMPTY (1 << 31) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + + +void kputc(int c); +int kgetc(void); +void kputs(const char *); + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/sims/cep_cosim/bootrom/include/platform.h b/sims/cep_cosim/bootrom/include/platform.h index b6c989b..12aca53 100644 --- a/sims/cep_cosim/bootrom/include/platform.h +++ b/sims/cep_cosim/bootrom/include/platform.h @@ -5,7 +5,7 @@ // File Name: platform.h // Program: Common Evaluation Platform (CEP) // Description: -// Notes: +// Notes: This version has a 1MB main memory size and 4 cores // //-------------------------------------------------------------------------------------- @@ -38,14 +38,6 @@ #define GLOBAL_INT_SIZE 38 #define GLOBAL_INT_MAX_PRIORITY 7 - -// Address constants taken from cep_adrMap.h. This is -// explicitly included here (versus using the CEP CoSim generated file) -// to avoid a circular -#define scratchpad_sp_offset 0x00070000 -#define scratchpad_base_addr 0x80000000 -#define scratchpad_base_size 0x00080000 - // Memory map #define CLINT_CTRL_ADDR _AC(0x2000000,UL) #define CLINT_CTRL_SIZE _AC(0x10000,UL) diff --git a/sims/cep_cosim/bootrom/include/util.h b/sims/cep_cosim/bootrom/include/util.h new file mode 100644 index 0000000..d0b4bfc --- /dev/null +++ b/sims/cep_cosim/bootrom/include/util.h @@ -0,0 +1,77 @@ +// See LICENSE for license details. + +#ifndef __UTIL_H +#define __UTIL_H + +//-------------------------------------------------------------------------- +// Macros + +// Set HOST_DEBUG to 1 if you are going to compile this for a host +// machine (ie Athena/Linux) for debug purposes and set HOST_DEBUG +// to 0 if you are compiling with the smips-gcc toolchain. + +#ifndef HOST_DEBUG +#define HOST_DEBUG 0 +#endif + +// Set PREALLOCATE to 1 if you want to preallocate the benchmark +// function before starting stats. If you have instruction/data +// caches and you don't want to count the overhead of misses, then +// you will need to use preallocation. + +#ifndef PREALLOCATE +#define PREALLOCATE 0 +#endif + +// Set SET_STATS to 1 if you want to carve out the piece that actually +// does the computation. + +#if HOST_DEBUG +#include +static void setStats(int enable) {} +#else +extern void setStats(int enable); +#endif + +#include + +#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } + +#if 0 +static void __attribute__((noinline)) barrier(int ncores) +{ + static volatile int sense; + static volatile int count; + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == ncores-1) + { + count = 0; + sense = threadsense; + } + else while(sense != threadsense) + ; + + __sync_synchronize(); +} +#endif + +#ifdef __riscv +#include "encoding.h" +#endif + +#define stringify_1(s) #s +#define stringify(s) stringify_1(s) +#define stats(code, iter) do { \ + unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ + code; \ + _c += read_csr(mcycle), _i += read_csr(minstret); \ + if (cid == 0) \ + printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ + stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \ + } while(0) + +#endif //__UTIL_H diff --git a/sims/cep_cosim/bootrom/kprintf.c b/sims/cep_cosim/bootrom/kprintf.c index 3e3f218..bbb47e8 100644 --- a/sims/cep_cosim/bootrom/kprintf.c +++ b/sims/cep_cosim/bootrom/kprintf.c @@ -2,74 +2,42 @@ #include #include #include - #include "kprintf.h" -static inline void _kputs(const char *s) +void kputc(int c) { - char c; - for (; (c = *s) != '\0'; s++) - kputc(c); +#ifndef DISABLE_KPRINTF + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); + while ((int32_t)(*tx) < 0); + *tx = (c & 0xFF); +#endif } -void kputs(const char *s) +int kgetc(void) { - _kputs(s); - kputc('\r'); - kputc('\n'); +#ifndef DISABLE_KPRINTF + uint32_t ch; + volatile uint32_t *rx = ®32(uart, UART_REG_RXFIFO); + ch = *rx; + + if ((uint32_t)(ch & UART_RXEMPTY)) { + return -1; + } else { + return(ch & 0x0ff); + } +#else + return -1; +#endif } -void kprintf(const char *fmt, ...) +void kputs(const char *s) { - va_list vl; - bool is_format, is_long, is_char; - char c; - - va_start(vl, fmt); - is_format = false; - is_long = false; - is_char = false; - while ((c = *fmt++) != '\0') { - if (is_format) { - switch (c) { - case 'l': - is_long = true; - continue; - case 'h': - is_char = true; - continue; - case 'x': { - unsigned long n; - long i; - if (is_long) { - n = va_arg(vl, unsigned long); - i = (sizeof(unsigned long) << 3) - 4; - } else { - n = va_arg(vl, unsigned int); - i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; - } - for (; i >= 0; i -= 4) { - long d; - d = (n >> i) & 0xF; - kputc(d < 10 ? '0' + d : 'a' + d - 10); - } - break; - } - case 's': - _kputs(va_arg(vl, const char *)); - break; - case 'c': - kputc(va_arg(vl, int)); - break; - } - is_format = false; - is_long = false; - is_char = false; - } else if (c == '%') { - is_format = true; - } else { - kputc(c); - } - } - va_end(vl); -} + char c; + while (*s != '\0') { + c = *s; + kputc((int) c); + s++; + } + kputc('\r'); + kputc('\n'); +} \ No newline at end of file diff --git a/sims/cep_cosim/bootrom/kprintf.h b/sims/cep_cosim/bootrom/kprintf.h deleted file mode 100644 index a7a9486..0000000 --- a/sims/cep_cosim/bootrom/kprintf.h +++ /dev/null @@ -1,49 +0,0 @@ -// See LICENSE.Sifive for license details. -#ifndef _SDBOOT_KPRINTF_H -#define _SDBOOT_KPRINTF_H - -#include -#include - -#define REG32(p, i) ((p)[(i) >> 2]) - -#ifndef UART_CTRL_ADDR - #ifndef UART_NUM - #define UART_NUM 0 - #endif - - #define _CONCAT3(A, B, C) A ## B ## C - #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) - #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) -#endif -static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); - -static inline void kputc(char c) -{ - volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); -#ifdef __riscv_atomic - int32_t r; - do { - __asm__ __volatile__ ( - "amoor.w %0, %2, %1\n" - : "=r" (r), "+A" (*tx) - : "r" (c)); - } while (r < 0); -#else - while ((int32_t)(*tx) < 0); - *tx = c; -#endif -} - -extern void kputs(const char *); -extern void kprintf(const char *, ...); - -#ifdef DEBUG -#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) -#define dputs(s) kputs((s)) -#else -#define dprintf(s, ...) do { } while (0) -#define dputs(s) do { } while (0) -#endif - -#endif /* _SDBOOT_KPRINTF_H */ diff --git a/sims/cep_cosim/bootrom/sd.c b/sims/cep_cosim/bootrom/sd.c index 567cb32..fd1d432 100644 --- a/sims/cep_cosim/bootrom/sd.c +++ b/sims/cep_cosim/bootrom/sd.c @@ -11,17 +11,16 @@ // - Updated ACMD41 processing to read all five bytes of the R3 response and check // the busy bit in the response per specification Figure 4-4 (Response bit 39) // - Removed 34-byte BBL offset in sd_copy (now set to 0) +// - Increased default payload size to 35MB to accomodate larger Linux images //-------------------------------------------------------------------------------------- // See LICENSE.Sifive for license details. +#include #include #include -#define DEBUG -#include "kprintf.h" - -// Total payload in B -#define PAYLOAD_SIZE_B (1 << 19) // 512kB +// Payload size in bytes +#define PAYLOAD_SIZE_B (35 << 20) // 35 MB // A sector is 512 bytes, so (1 << 11) * 512B = 1 MiB #define SECTOR_SIZE_B 512 @@ -39,9 +38,25 @@ #define F_CLK TL_CLK #define REG64(p, i) ((p)[(i) >> 3]) +#define REG32(p, i) ((p)[(i) >> 2]) +#define REG16(p, i) ((p)[(i) >> 1]) static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); +static volatile uint32_t * const gpio = (void *)(GPIO_CTRL_ADDR); static volatile uint64_t * const cepregs = (void *)(CEPREGS_ADDR); +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + +// Button used to allow for a "fast boot" +#ifdef VCU118 + // GPIO Button N on VCU118 + #define BTN0_MASK (0x00000010) +#elif VC707 + // GPIO Button N on VC707 + #define BTN0_MASK (0x00000100) +#else + // BTN0 on Arty100T + #define BTN0_MASK (0x00001000) +#endif static inline uint8_t spi_xfer(uint8_t d) { @@ -80,7 +95,7 @@ static uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) goto done; } } while (--n > 0); - kputs("sd_cmd: timeout"); + puts("sd_cmd: timeout"); done: return r; } @@ -106,7 +121,7 @@ static void sd_poweron(void) static int sd_cmd0(void) { int rc; - kputs("CMD0"); + puts("CMD0"); rc = (sd_cmd(0x40, 0, 0x95) != 0x01); sd_cmd_end(); return rc; @@ -115,7 +130,7 @@ static int sd_cmd0(void) static int sd_cmd8(void) { int rc; - kputs("CMD8"); + puts("CMD8"); // Per section 7.3.2.6 of the specification, the card should be in the IDLE state and // running the initialization process rc = (sd_cmd(0x48, 0x000001AA, 0x87) != 0x01); @@ -135,19 +150,19 @@ static void sd_cmd55(void) static int sd_acmd41(void) { - uint8_t r; - dputs("ACMD41"); - do { - sd_cmd55(); - r = sd_cmd(0x69, 0x40000000, 0x77); /* HCS = 1 */ - } while (r == 0x01); - return (r != 0x00); + uint8_t r; + puts("ACMD41"); + do { + sd_cmd55(); + r = sd_cmd(0x69, 0x40000000, 0x77); /* HCS = 1 */ + } while (r == 0x01); + return (r != 0x00); } static int sd_cmd58(void) { int rc; - kputs("CMD58"); + puts("CMD58"); rc = (sd_cmd(0x7A, 0, 0xFD) != 0x00); rc |= ((sd_dummy() & 0x80) != 0x80); /* Power up status */ sd_dummy(); @@ -161,7 +176,7 @@ static int sd_cmd58(void) static int sd_cmd16(void) { int rc; - kputs("CMD16"); + puts("CMD16"); rc = (sd_cmd(0x50, 0x200, 0x15) != 0x00); sd_cmd_end(); return rc; @@ -176,11 +191,10 @@ static uint16_t crc16_round(uint16_t crc, uint8_t data) { return crc; } -#define SPIN_SHIFT 6 -#define SPIN_UPDATE(i) (!((i) & ((1 << SPIN_SHIFT)-1))) -#define SPIN_INDEX(i) (((i) >> SPIN_SHIFT) & 0x3) - -static const char spinner[] = { '-', '/', '|', '\\' }; +#define STATUS_SHIFT 6 +#define STATUS_NEWLINE_SHIFT 12 +#define STATUS_UPDATE(i) (!((i) & ((1 << STATUS_SHIFT)-1))) +#define STATUS_NEWLINE(i) (!((i) & ((1 << STATUS_NEWLINE_SHIFT)-1))) // Copy SD contents to main memory static int sd_copy(void) @@ -188,26 +202,38 @@ static int sd_copy(void) volatile uint8_t *p = (void *)(MEMORY_MEM_ADDR); long i = PAYLOAD_SIZE; int rc = 0; + uint32_t fast_boot = 0; - // The following logic allows for a simulation overwrite of the number of blocks to be loaded - // If the scratch_w7 register is not "forced" by the simulation, then the default payload size - // will prevail. - REG64(cepregs, CEPREGS_SCRATCH_W7) = i; - i = REG64(cepregs, CEPREGS_SCRATCH_W7); + puts("CMD18"); - kputs("CMD18"); + // Read the state of button 0 on the arty100t board to determine if a fast boot is requested + REG32(gpio, GPIO_INPUT_EN) = (uint32_t)(BTN0_MASK); + fast_boot = REG32(gpio, GPIO_INPUT_VAL) & BTN0_MASK; + REG32(gpio, GPIO_INPUT_EN) = (uint32_t)(0); + + // The following logic allows for overiding of the default payload size by either holding button zero upon + // release from reset OR being forced by the simulation. + // Given that the simulation has it's own override, the "fast boot" is targetted to bare metal boots + // on the FPGA dev boards. + if (fast_boot) { + i = 0x100; // 256 x 512B = 132kB + } else { + REG64(cepregs, CEPREGS_SCRATCH_W7) = i; + i = REG64(cepregs, CEPREGS_SCRATCH_W7); + } // Performing multiplication here in the event that PAYLOAD_SIZE is // overriden in simulation - kprintf("LOADING 0x%x PAYLOAD\r\n", SECTOR_SIZE_B * i); - kprintf("LOADING "); + printf("LOADING %ldkB PAYLOAD\n", (i * SECTOR_SIZE_B)/1024); - // Begin a multi-cycle read + // Begin a multi-cycle read. Divider taked from default VCU118 Bootroml REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); - if (sd_cmd(0x52, 0, 0xE1) != 0x00) { + + if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { sd_cmd_end(); return 1; } + do { uint16_t crc, crc_exp; long n; @@ -229,21 +255,25 @@ static int sd_copy(void) crc_exp |= sd_dummy(); if (crc != crc_exp) { - kputs("CRC mismatch"); + puts("CRC mismatch"); rc = 1; break; } - if (SPIN_UPDATE(i)) { - kputc('\b'); - kputc(spinner[SPIN_INDEX(i)]); + if (STATUS_UPDATE(i)) { + putchar('.'); + if (STATUS_NEWLINE(i)) { + printf("%ldkB\n", (i * SECTOR_SIZE_B)/1024); + } } + } while (--i > 0); - sd_cmd_end(); + sd_cmd_end(); sd_cmd(0x4C, 0, 0x01); sd_cmd_end(); - kputs("\b "); + printf("\n"); + return rc; } @@ -275,48 +305,51 @@ int main(void) // Enable the welcome message if the two LSBits in CEP Scratch Register are NOT set if ((scratch_reg & 0x3) != 0x3) { - kprintf("--- Common Evaluation Platform v%x.%x ---\r\n", major_version, minor_version); - kprintf("--- Copyright 2022 Massachusetts Institute of Technology ---\r\n"); - kprintf("--- BootRom Image built on %s %s ---\r\n",__DATE__,__TIME__); + printf("\n"); + printf("--- Common Evaluation Platform v%x.%x ---\n", major_version, minor_version); + printf("--- Based on the UCB Chipyard Framework ---\n"); + printf("--- Copyright 2022 Massachusetts Institute of Technology ---\n"); + printf("--- BootRom Image built on %s %s ---\n",__DATE__,__TIME__); + printf("\n"); } // if ((scratch_reg & 0x3) != 0x3) // Enable SD Boot if bits 3 & 2 of the CEP Scratch register are NOT set if ((scratch_reg & 0xC) != 0xC) { - kputs("INIT"); + puts("INIT"); sd_poweron(); if (sd_cmd0()) { - kputs("CMD0 ERROR"); + puts("CMD0 ERROR"); return 1; } if (sd_cmd8()) { - kputs("CMD8 ERROR"); + puts("CMD8 ERROR"); return 1; } if (sd_acmd41()) { - kputs("ACMD41 ERROR"); + puts("ACMD41 ERROR"); return 1; } if (sd_cmd58()) { - kputs("CMD58 ERROR"); + puts("CMD58 ERROR"); return 1; } if (sd_cmd16()) { - kputs("CMD16 ERROR"); + puts("CMD16 ERROR"); return 1; } if (sd_copy()) { - kputs("SDCOPY ERROR"); + puts("SDCOPY ERROR"); return 1; } - kputs("BOOT"); + puts("BOOT"); } // if ((scratch_reg & 0xC) != 0xC) // Force instruction and data stream synchronization diff --git a/sims/cep_cosim/bootrom/syscalls_bootrom.c b/sims/cep_cosim/bootrom/syscalls_bootrom.c new file mode 100644 index 0000000..c5c970c --- /dev/null +++ b/sims/cep_cosim/bootrom/syscalls_bootrom.c @@ -0,0 +1,438 @@ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: syscalls_bootrom.c +// Program: Common Evaluation Platform (CEP) +// Description: Modified baremetal system calls for RISC-V +// Notes: Customized version of syscalls.c for the bootrom +// +//-------------------------------------------------------------------------------------- + + +// See LICENSE for license details. + +#include +#include +#include +#include +#include +#include +#include +#include "kprintf.h" +#include "util.h" + +#define SYS_write 64 + +#undef strcmp + +#define NUM_COUNTERS 2 +static uintptr_t counters[NUM_COUNTERS]; +static char* counter_names[NUM_COUNTERS]; + +void setStats(int enable) +{ + int i = 0; +#define READ_CTR(name) do { \ + while (i >= NUM_COUNTERS) ; \ + uintptr_t csr = read_csr(name); \ + if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \ + counters[i++] = csr; \ + } while (0) + + READ_CTR(mcycle); + READ_CTR(minstret); + +#undef READ_CTR +} + +void __attribute__((noreturn)) tohost_exit(uintptr_t code) +{ + while (1); +} + +uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) +{ + tohost_exit(1337); +} + +void exit(int code) +{ + tohost_exit(code); +} + +void abort() +{ + exit(128 + SIGABRT); +} + +// Syscall is currently disabled as it does +// not function properly in simulation +int puts(const char* s) +{ + kputs(s); + + return 0; +} + +void __attribute__((weak)) thread_entry(int cid, int nc) +{ + // multi-threaded programs override this function. + // for the case of single-threaded programs, only let core 0 proceed. + while (cid != 0); +} + +int __attribute__((weak)) main(int argc, char** argv) +{ + // single-threaded programs override this function. + puts("Implement main(), foo!\n"); + return -1; +} + +#undef getchar +int getchar() +{ + return kgetc(); +} + + +#undef putchar +int putchar(int ch) +{ + kputc(ch); + + return 0; +} + +void printhex(uint64_t x) +{ + char str[17]; + int i; + for (i = 0; i < 16; i++) + { + str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); + x >>= 4; + } + str[16] = 0; + + puts(str); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*CHAR_BIT]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static unsigned long long getuint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, unsigned long long); + else if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long long getint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, long long); + else if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch; + unsigned long long num; + int base, lflag, width, precision; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') { + return; + } else if (ch == '\n') { + putch('\n', putdat); + putch('\r', putdat); + fmt++; + } else { + putch(ch, putdat); + fmt++; + } + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag (doubled for long long) + case 'l': + lflag++; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long long) num < 0) { + putch('-', putdat); + num = -(long long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + static_assert(sizeof(long) == sizeof(void*)); + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +// Calling of putchar from printf is currently disabled +// as syscalls do not function correctly +int printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + vprintfmt((void*)kputc, 0, fmt, ap); + va_end(ap); + + return 0; // incorrect return value, but who cares, anyway? +} + +int sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + void sprintf_putch(int ch, void** data) + { + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; + } + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +} + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +size_t strnlen(const char *s, size_t n) +{ + const char *p = s; + while (n-- && *p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + +long atol(const char* str) +{ + long res = 0; + int sign = 0; + + while (*str == ' ') + str++; + + if (*str == '-' || *str == '+') { + sign = *str == '-'; + str++; + } + + while (*str) { + res *= 10; + res += *str++ - '0'; + } + + return sign ? -res : res; +} \ No newline at end of file diff --git a/sims/cep_cosim/cep_buildSW.make b/sims/cep_cosim/cep_buildSW.make index a13bff8..8dcee51 100644 --- a/sims/cep_cosim/cep_buildSW.make +++ b/sims/cep_cosim/cep_buildSW.make @@ -25,8 +25,8 @@ COMMON_CFLAGS += -DASICMODE RISCV_BARE_CFLAGS += -DASICMODE endif -ifeq (${ENABLE_KPRINTF},1) -RISCV_BARE_CFLAGS += -DENABLE_KPRINTF +ifeq (${DISABLE_KPRINTF},1) +RISCV_BARE_CFLAGS += -DDISABLE_KPRINTF endif #-------------------------------------------------------------------------------------- @@ -228,8 +228,8 @@ RISCV_VIRT_INC += -I${DRIVERS_DIR}/virtual -I${RISCV_TEST_DIR}/isa/macros/ # -g - Produce debugging information in the operating system’s native format # -c - Compile, but don't link files # -lgcc - ????? -RISCV_BARE_CFLAGS += -mcmodel=medany -O2 -Wall -fno-common -fno-builtin-printf -RISCV_BARE_CFLAGS += -I ${BARE_D} -I ${VECTOR_D} ${COMMON_INCLUDE_LIST} +RISCV_BARE_CFLAGS += -mcmodel=medany -O2 -fno-common -fno-builtin-printf -fno-builtin-puts -Wall -Wno-unused-function +RISCV_BARE_CFLAGS += -I ${BARE_D} -I ${BARE_D}/include -I ${VECTOR_D} ${COMMON_INCLUDE_LIST} RISCV_BARE_CFLAGS += -mabi=lp64 -march=rv64ima RISCV_BARE_CFLAGS += -DBARE_MODE -DRISCV_CPU RISCV_BARE_LFILE += ${BARE_D}/cep_link.lds diff --git a/sims/cep_cosim/common.make b/sims/cep_cosim/common.make index 4a8bda3..ee3e375 100644 --- a/sims/cep_cosim/common.make +++ b/sims/cep_cosim/common.make @@ -40,7 +40,7 @@ endif NOWAVE ?= 1 TL_CAPTURE ?= 0 BYPASS_PLL ?= 0 -ENABLE_KPRINTF ?= 0 +DISABLE_KPRINTF ?= 1 DISABLE_CHISEL_PRINTF ?= 1 # The following flags are defined here to support the eventual enablement of legacy functionality @@ -139,7 +139,7 @@ V2C_CMD = ${BIN_DIR}/v2c.pl #-------------------------------------------------------------------------------------- # To detect if any important flags have changed since last run #-------------------------------------------------------------------------------------- -PERSUITE_CHECK = ${TEST_SUITE_DIR}/.PERSUITE_${DUT_SIM_MODE}_${NOWAVE}_${PROFILE}_${COVERAGE}_${DISABLE_CHISEL_PRINTF}_${ENABLE_KPRINTF}_${TL_CAPTURE}_${USE_GDB}_${BYPASS_PLL} +PERSUITE_CHECK = ${TEST_SUITE_DIR}/.PERSUITE_${DUT_SIM_MODE}_${NOWAVE}_${PROFILE}_${COVERAGE}_${DISABLE_CHISEL_PRINTF}_${DISABLE_KPRINTF}_${TL_CAPTURE}_${USE_GDB}_${BYPASS_PLL} ${PERSUITE_CHECK}: .force @if test ! -f ${PERSUITE_CHECK}; then rm -f ${TEST_SUITE_DIR}/.PERSUITE_*; touch ${PERSUITE_CHECK}; fi @@ -178,7 +178,7 @@ endif @echo "CEP_COSIM: BYPASS_PLL = ${BYPASS_PLL}" @echo "CEP_COSIM: ASIC_MODE = ${ASIC_MODE}" @echo "CEP_COSIM: DISABLE_CHISEL_PRINTF = ${DISABLE_CHISEL_PRINTF}" - @echo "CEP_COSIM: ENABLE_KPRINTF = ${ENABLE_KPRINTF}" + @echo "CEP_COSIM: DISABLE_KPRINTF = ${DISABLE_KPRINTF}" @echo "" #-------------------------------------------------------------------------------------- @@ -369,7 +369,7 @@ User controlled options: (0 = not set, 1 = set) TL_CAPTURE : Default: 0: Enables capturing of CEP core tilelink I/O as required by bareMetal macroMix tests and unit simulation BYPASS_PLL : Default, 0: Applicable only when running the ASIC simulation, enables PLL bypass when set. DISABLE_CHISEL_PRINTF : Default, 1: When not set, enables instruction trace of the Rocket Cores (not applicable in BFM mode) - ENABLE_KPRINTF : Default, 0: When set, maps the LOGI/W/E/F functions to kprintf, thus enabling printf functionality in bare metal mode. + DISABLE_KPRINTF : Default, 1: When not set, maps the LOGI/W/E/F functions to printf, thus enabling printf functionality in bare metal mode. Targets: usage : Print this usage information. diff --git a/sims/cep_cosim/drivers/bare/bare_malloc.h b/sims/cep_cosim/drivers/bare/include/bare_malloc.h similarity index 100% rename from sims/cep_cosim/drivers/bare/bare_malloc.h rename to sims/cep_cosim/drivers/bare/include/bare_malloc.h diff --git a/software/baremetal/template/include/compiler.h b/sims/cep_cosim/drivers/bare/include/compiler.h similarity index 100% rename from software/baremetal/template/include/compiler.h rename to sims/cep_cosim/drivers/bare/include/compiler.h diff --git a/sims/cep_cosim/drivers/bare/include/const.h b/sims/cep_cosim/drivers/bare/include/const.h new file mode 100644 index 0000000..8507e16 --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/const.h @@ -0,0 +1,18 @@ +// See LICENSE.Sifive for license details. +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/sims/cep_cosim/drivers/bare/include/devices/arty100t_gpio.h b/sims/cep_cosim/drivers/bare/include/devices/arty100t_gpio.h new file mode 100644 index 0000000..d9d2d62 --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/devices/arty100t_gpio.h @@ -0,0 +1,25 @@ +#ifndef _ARTY100T_GPIO_H +#define _ARTY100T_GPIO_H + +#define GPIO0_MASK (0x00000001) +#define GPIO1_MASK (0x00000002) +#define GPIO2_MASK (0x00000004) +#define GPIO3_MASK (0x00000008) +#define GPIO4_MASK (0x00000010) +#define GPIO5_MASK (0x00000020) +#define GPIO6_MASK (0x00000040) +#define GPIO7_MASK (0x00000080) +#define SW0_MASK (0x00000100) +#define SW1_MASK (0x00000200) +#define SW2_MASK (0x00000400) +#define SW3_MASK (0x00000800) +#define BTN0_MASK (0x00001000) +#define BTN1_MASK (0x00002000) +#define BTN2_MASK (0x00004000) +#define BTN3_MASK (0x00008000) +#define LED0_MASK (0x00010000) +#define LED1_MASK (0x00020000) +#define LED2_MASK (0x00040000) +#define LED3_MASK (0x00080000) + +#endif /* _ARTY100T_GPIO_H */ diff --git a/sims/cep_cosim/drivers/bare/include/devices/cepregs.h b/sims/cep_cosim/drivers/bare/include/devices/cepregs.h new file mode 100644 index 0000000..6a73d0a --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/devices/cepregs.h @@ -0,0 +1,22 @@ +// See LICENSE.Sifive for license details. + +#ifndef _CEPREGS_H +#define _CEPREGS_H + +/* Register offsets */ +#define CEPREGS_VERSION 0x0000 +#define CEPREGS_TESTNSET 0xFD10 +#define CEPREGS_SCRATCH_W0 0xFE00 +#define CEPREGS_SCRATCH_W1 0xFE08 +#define CEPREGS_SCRATCH_W2 0xFE10 +#define CEPREGS_SCRATCH_W3 0xFE18 +#define CEPREGS_SCRATCH_W4 0xFE20 +#define CEPREGS_SCRATCH_W5 0xFE28 +#define CEPREGS_SCRATCH_W6 0xFE30 +#define CEPREGS_SCRATCH_W7 0xFE38 +#define CEPREGS_CORE0_STATUS 0xFF00 +#define CEPREGS_CORE1_STATUS 0xFF08 +#define CEPREGS_CORE2_STATUS 0xFF10 +#define CEPREGS_CORE3_STATUS 0xFF18 + +#endif /* _CEPREGS_H */ diff --git a/sims/cep_cosim/drivers/bare/include/devices/clint.h b/sims/cep_cosim/drivers/bare/include/devices/clint.h new file mode 100644 index 0000000..08092cd --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE.Sifive for license details. + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/sims/cep_cosim/drivers/bare/include/devices/gpio.h b/sims/cep_cosim/drivers/bare/include/devices/gpio.h new file mode 100644 index 0000000..76dcb9f --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE.Sifive for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/sims/cep_cosim/drivers/bare/include/devices/plic.h b/sims/cep_cosim/drivers/bare/include/devices/plic.h new file mode 100644 index 0000000..eddcae9 --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE.Sifive for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/sims/cep_cosim/drivers/bare/include/devices/spi.h b/sims/cep_cosim/drivers/bare/include/devices/spi.h new file mode 100644 index 0000000..85c1099 --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/devices/spi.h @@ -0,0 +1,79 @@ +// See LICENSE.Sifive for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#endif /* _SIFIVE_SPI_H */ diff --git a/sims/cep_cosim/drivers/bare/include/devices/uart.h b/sims/cep_cosim/drivers/bare/include/devices/uart.h new file mode 100644 index 0000000..c3f6a53 --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/devices/uart.h @@ -0,0 +1,28 @@ +// See LICENSE.Sifive for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXNSTOP 0x2 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/software/baremetal/template/include/encoding.h b/sims/cep_cosim/drivers/bare/include/encoding.h similarity index 100% rename from software/baremetal/template/include/encoding.h rename to sims/cep_cosim/drivers/bare/include/encoding.h diff --git a/sims/cep_cosim/drivers/bare/include/kprintf.h b/sims/cep_cosim/drivers/bare/include/kprintf.h new file mode 100644 index 0000000..2733e2d --- /dev/null +++ b/sims/cep_cosim/drivers/bare/include/kprintf.h @@ -0,0 +1,28 @@ +// See LICENSE.Sifive for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +#define UART_RXEMPTY (1 << 31) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + + +void kputc(int c); +int kgetc(void); +void kputs(const char *); + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/software/baremetal/template/include/mmio.h b/sims/cep_cosim/drivers/bare/include/mmio.h similarity index 100% rename from software/baremetal/template/include/mmio.h rename to sims/cep_cosim/drivers/bare/include/mmio.h diff --git a/software/baremetal/template/include/platform.h b/sims/cep_cosim/drivers/bare/include/platform.h similarity index 99% rename from software/baremetal/template/include/platform.h rename to sims/cep_cosim/drivers/bare/include/platform.h index b6c989b..326a9c9 100644 --- a/software/baremetal/template/include/platform.h +++ b/sims/cep_cosim/drivers/bare/include/platform.h @@ -19,6 +19,7 @@ #include "devices/spi.h" #include "devices/uart.h" #include "devices/cepregs.h" +#include "devices/arty100t_gpio.h" // Some things missing from the official encoding.h #if __riscv_xlen == 32 diff --git a/software/baremetal/template/include/util.h b/sims/cep_cosim/drivers/bare/include/util.h similarity index 100% rename from software/baremetal/template/include/util.h rename to sims/cep_cosim/drivers/bare/include/util.h diff --git a/sims/cep_cosim/drivers/bare/kprintf.c b/sims/cep_cosim/drivers/bare/kprintf.c index 3e3f218..bbb47e8 100644 --- a/sims/cep_cosim/drivers/bare/kprintf.c +++ b/sims/cep_cosim/drivers/bare/kprintf.c @@ -2,74 +2,42 @@ #include #include #include - #include "kprintf.h" -static inline void _kputs(const char *s) +void kputc(int c) { - char c; - for (; (c = *s) != '\0'; s++) - kputc(c); +#ifndef DISABLE_KPRINTF + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); + while ((int32_t)(*tx) < 0); + *tx = (c & 0xFF); +#endif } -void kputs(const char *s) +int kgetc(void) { - _kputs(s); - kputc('\r'); - kputc('\n'); +#ifndef DISABLE_KPRINTF + uint32_t ch; + volatile uint32_t *rx = ®32(uart, UART_REG_RXFIFO); + ch = *rx; + + if ((uint32_t)(ch & UART_RXEMPTY)) { + return -1; + } else { + return(ch & 0x0ff); + } +#else + return -1; +#endif } -void kprintf(const char *fmt, ...) +void kputs(const char *s) { - va_list vl; - bool is_format, is_long, is_char; - char c; - - va_start(vl, fmt); - is_format = false; - is_long = false; - is_char = false; - while ((c = *fmt++) != '\0') { - if (is_format) { - switch (c) { - case 'l': - is_long = true; - continue; - case 'h': - is_char = true; - continue; - case 'x': { - unsigned long n; - long i; - if (is_long) { - n = va_arg(vl, unsigned long); - i = (sizeof(unsigned long) << 3) - 4; - } else { - n = va_arg(vl, unsigned int); - i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; - } - for (; i >= 0; i -= 4) { - long d; - d = (n >> i) & 0xF; - kputc(d < 10 ? '0' + d : 'a' + d - 10); - } - break; - } - case 's': - _kputs(va_arg(vl, const char *)); - break; - case 'c': - kputc(va_arg(vl, int)); - break; - } - is_format = false; - is_long = false; - is_char = false; - } else if (c == '%') { - is_format = true; - } else { - kputc(c); - } - } - va_end(vl); -} + char c; + while (*s != '\0') { + c = *s; + kputc((int) c); + s++; + } + kputc('\r'); + kputc('\n'); +} \ No newline at end of file diff --git a/sims/cep_cosim/drivers/bare/kprintf.h b/sims/cep_cosim/drivers/bare/kprintf.h deleted file mode 100644 index 858f657..0000000 --- a/sims/cep_cosim/drivers/bare/kprintf.h +++ /dev/null @@ -1,58 +0,0 @@ -// See LICENSE.Sifive for license details. -#ifndef _SDBOOT_KPRINTF_H -#define _SDBOOT_KPRINTF_H - -#include -#include - -#define REG32(p, i) ((p)[(i) >> 2]) - -#ifndef UART_CTRL_ADDR - #ifndef UART_NUM - #define UART_NUM 0 - #endif - - #define _CONCAT3(A, B, C) A ## B ## C - #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) - #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) -#endif -static volatile uint32_t * const uart = (uint32_t *)(UART_CTRL_ADDR); - -#ifdef __cplusplus -extern "C" { -#endif - -static inline void kputc(char c) -{ - volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); -#ifdef __riscv_atomic - int32_t r; - do { - __asm__ __volatile__ ( - "amoor.w %0, %2, %1\n" - : "=r" (r), "+A" (*tx) - : "r" (c)); - } while (r < 0); -#else - while ((int32_t)(*tx) < 0); - *tx = c; -#endif -} - -void kputs(const char *); -void kprintf(const char *, ...); - -#ifdef DEBUG -#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) -#define dputs(s) kputs((s)) -#else -#define dprintf(s, ...) do { } while (0) -#define dputs(s) do { } while (0) -#endif - -// end of extern -#ifdef __cplusplus -} -#endif - -#endif /* _SDBOOT_KPRINTF_H */ diff --git a/sims/cep_cosim/drivers/bare/syscalls.c b/sims/cep_cosim/drivers/bare/syscalls.c index fb49f36..226fff4 100644 --- a/sims/cep_cosim/drivers/bare/syscalls.c +++ b/sims/cep_cosim/drivers/bare/syscalls.c @@ -28,24 +28,6 @@ extern volatile uint64_t tohost; extern volatile uint64_t fromhost; -static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2) -{ - volatile uint64_t magic_mem[8] __attribute__((aligned(64))); - magic_mem[0] = which; - magic_mem[1] = arg0; - magic_mem[2] = arg1; - magic_mem[3] = arg2; - __sync_synchronize(); - - tohost = (uintptr_t)magic_mem; - while (fromhost == 0) - ; - fromhost = 0; - - __sync_synchronize(); - return magic_mem[0]; -} - #define NUM_COUNTERS 2 static uintptr_t counters[NUM_COUNTERS]; static char* counter_names[NUM_COUNTERS]; @@ -89,16 +71,11 @@ void abort() // Syscall is currently disabled as it does // not function properly in simulation -void printstr(const char* s) +int puts(const char* s) { - -#ifdef ENABLE_KPRINTF kputs(s); -#else - ; -// syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); -#endif + return 0; } void __attribute__((weak)) thread_entry(int cid, int nc) @@ -111,7 +88,7 @@ void __attribute__((weak)) thread_entry(int cid, int nc) int __attribute__((weak)) main(int argc, char** argv) { // single-threaded programs override this function. - printstr("Implement main(), foo!\n"); + puts("Implement main(), foo!\n"); return -1; } @@ -140,24 +117,22 @@ void _init(int cid, int nc) if (counters[i]) pbuf += sprintf(pbuf, "%s = %" PRIuPTR "\n", counter_names[i], counters[i]); if (pbuf != buf) - printstr(buf); + puts(buf); exit(ret); } -#undef putchar -int putchar(int ch) +#undef getchar +int getchar() { - static __thread char buf[64] __attribute__((aligned(64))); - static __thread int buflen = 0; + return kgetc(); +} - buf[buflen++] = ch; - if (ch == '\n' || buflen == sizeof(buf)) - { - syscall(SYS_write, 1, (uintptr_t)buf, buflen); - buflen = 0; - } +#undef putchar +int putchar(int ch) +{ + kputc(ch); return 0; } @@ -173,7 +148,7 @@ void printhex(uint64_t x) } str[16] = 0; - printstr(str); + puts(str); } static inline void printnum(void (*putch)(int, void**), void **putdat, @@ -221,17 +196,23 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt { register const char* p; const char* last_fmt; - register int ch, err; + register int ch; unsigned long long num; - int base, lflag, width, precision, altflag; + int base, lflag, width, precision; char padc; while (1) { while ((ch = *(unsigned char *) fmt) != '%') { - if (ch == '\0') + if (ch == '\0') { return; - fmt++; - putch(ch, putdat); + } else if (ch == '\n') { + putch('\n', putdat); + putch('\r', putdat); + fmt++; + } else { + putch(ch, putdat); + fmt++; + } } fmt++; @@ -241,7 +222,6 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt width = -1; precision = -1; lflag = 0; - altflag = 0; reswitch: switch (ch = *(unsigned char *) fmt++) { @@ -283,7 +263,6 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt goto reswitch; case '#': - altflag = 1; goto reswitch; process_precision: @@ -372,16 +351,11 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt // as syscalls do not function correctly int printf(const char* fmt, ...) { - -#ifdef ENABLE_KPRINTF va_list ap; va_start(ap, fmt); vprintfmt((void*)kputc, 0, fmt, ap); va_end(ap); -#else - ; -// vprintfmt((void*)putchar, 0, fmt, ap); -#endif + return 0; // incorrect return value, but who cares, anyway? } diff --git a/sims/cep_cosim/drivers/cep_tests/cep_gps.cc b/sims/cep_cosim/drivers/cep_tests/cep_gps.cc index 80578b7..903ce2f 100644 --- a/sims/cep_cosim/drivers/cep_tests/cep_gps.cc +++ b/sims/cep_cosim/drivers/cep_tests/cep_gps.cc @@ -22,6 +22,32 @@ #include "CEP.h" #include "random48.h" +static uint16_t x_buf_size = 4096; + +static uint16_t X1A_period = 4092; +static uint16_t X1B_period = 4093; +static uint16_t X2A_period = 4092; +static uint16_t X2B_period = 4093; + +static uint32_t XN_cnt_speed = 1; +static uint32_t Z_cnt_speed = 1; + +static uint32_t X_a_full_count = 3750; +static uint32_t X_b_full_count = 3749; +static uint32_t X1A_loops = ((int) ((X_a_full_count+XN_cnt_speed-1)/ XN_cnt_speed)); +static uint32_t X1B_loops = ((int) ((X_b_full_count+XN_cnt_speed-1)/ XN_cnt_speed)); + +static uint64_t Z_full_period = 403200; +static uint64_t Z_period = ((Z_full_period + Z_cnt_speed - 1 ) / Z_cnt_speed); +static uint64_t Code_length = (Z_period * X1A_loops * X1A_period); +static uint64_t X1_period = X1A_period * X1A_loops; +static uint64_t X2_period = X1_period + 37; +static uint64_t X_b_hold = ((X1A_period*X1A_loops) - (X1B_period*X1B_loops)); + +static uint64_t X2A_last_hold = ((Code_length % X2_period) % X2A_period); +static uint64_t X2B_last_hold = ((Code_length % X2_period) % X2B_period); + + cep_gps::cep_gps(int coreIndex, int seed, int verbose) : cep_aes(coreIndex, seed, verbose) { init(coreIndex); mStaticPCodeInit = 0; @@ -78,10 +104,30 @@ x2a = 0b100100100101 x2b = 0b010101010100 */ void cep_gps::SetPcodeXnInit (uint16_t x1a_initial, uint16_t x1b_initial, uint16_t x2a_initial, uint16_t x2b_initial) { - m_x1a_initial &= x1a_initial & 0xfff; - m_x1b_initial &= x1b_initial & 0xfff; - m_x2a_initial &= x2a_initial & 0xfff; - m_x2b_initial &= x2b_initial & 0xfff; + m_x1a_initial = x1a_initial & 0xfff; + m_x1b_initial = x1b_initial & 0xfff; + m_x2a_initial = x2a_initial & 0xfff; + m_x2b_initial = x2b_initial & 0xfff; + // Update values for fast loop + X1A_period = 10; + X1B_period = 9; + X2A_period = 10; + X2B_period = 9; + + XN_cnt_speed = 163; + Z_cnt_speed = 174763; + + X1A_loops = ((int) ((X_a_full_count+XN_cnt_speed-1)/ XN_cnt_speed)); + X1B_loops = ((int) ((X_b_full_count+XN_cnt_speed-1)/ XN_cnt_speed)); + X1_period = X1A_period * X1A_loops; + X2_period = X1_period + 37; + + X_b_hold = ((X1A_period*X1A_loops) - (X1B_period*X1B_loops)); + Z_period = ((Z_full_period + Z_cnt_speed - 1 ) / Z_cnt_speed); + Code_length = (Z_period * X1A_loops * X1A_period); + + X2A_last_hold = ((Code_length % X2_period) % X2A_period); + X2B_last_hold = ((Code_length % X2_period) % X2B_period); uint64_t pcode_xinitial = 0; pcode_xinitial |= (uint64_t)m_x1a_initial << 0; @@ -89,6 +135,8 @@ void cep_gps::SetPcodeXnInit (uint16_t x1a_initial, uint16_t x1b_initial, uint16 pcode_xinitial |= (uint64_t)m_x2a_initial << 24; pcode_xinitial |= (uint64_t)m_x2b_initial << 36; cep_writeNcapture(GPS_PCODE_XINI, pcode_xinitial); + uint64_t pcode_speed = XN_cnt_speed | (Z_cnt_speed << 12); + cep_writeNcapture(GPS_PCODE_SPEED, pcode_speed); } @@ -177,7 +225,7 @@ void cep_gps::x_prep(void) { LFSR x1b_reg = {.x = m_x1b_initial}; LFSR x2a_reg = {.x = m_x2a_initial}; LFSR x2b_reg = {.x = m_x2b_initial}; - for (int i = 0; i < 4096; i++) { + for (int i = 0; i < x_buf_size; i++) { uint8_t bits; bits = x1a_shift(&x1a_reg) << 0; bits |= x1b_shift(&x1b_reg) << 1; @@ -192,67 +240,65 @@ void cep_gps::x_prep(void) { } uint8_t cep_gps::x1_lookup(uint8_t * x_buf, uint64_t index) { - index = index % 15345000; - uint8_t x1a = (x_buf[index%4092]>>0) &1; + index = index % X1_period; + uint8_t x1a = (x_buf[index % X1A_period]>>0) &1; - if ( index >= 15345000-343 ) - index = 4092; //Hold logic for x1b - - uint8_t x1b = (x_buf[index%4093]>>1) &1; + if ( index >= X1_period - X_b_hold ){ + index = X1B_period -1; //Hold logic for x1b + } + uint8_t x1b = (x_buf[index % X1B_period]>>1) &1; return x1a ^ x1b; } uint8_t cep_gps::x2_lookup(uint8_t * x_buf, uint64_t index) { - uint64_t index_x2a = index % 15345037; + uint64_t index_x2a = index % X2_period; uint64_t index_x2b = index_x2a; - uint64_t index_a = index % 15345000; + uint64_t index_a = index % X1_period; uint64_t index_b = index_a; - if (index_a>=(15345037-37)) - index_x2a = 4091; //Hold logic for x2a - - uint8_t x2a = (x_buf[index_x2a%4092]>>2) &1; + if (index_x2a >= X1_period){ + index_x2a = X2A_period - 1; //Hold logic for x2a + } + uint8_t x2a = (x_buf[index_x2a % X2A_period]>>2) &1; - if ( index_b >= 15345037-37-343 ) - index_x2b = 4092; //Hold logic for x2b - - uint8_t x2b = (x_buf[index_x2b%4093]>>3) &1; + if ( index_x2b >= X1_period - X_b_hold ){ + index_x2b = X2B_period - 1; //Hold logic for x2b + } + uint8_t x2b = (x_buf[index_x2b % X2B_period]>>3) &1; return x2a ^ x2b; } uint8_t cep_gps::x2_lookup_last(uint8_t * x_buf, uint64_t index) { - uint64_t index_x2a = index % 15345037; + uint64_t index_x2a = index % X2_period; uint64_t index_x2b = index_x2a; - uint64_t index_a = index % 15345000; + uint64_t index_a = index % X1_period; uint64_t index_b = index_a; - - if (index_a>=(15345000-1069)) - index_x2a = 4091; //Hold logic for x2a - - uint8_t x2a = (x_buf[index_x2a%4092]>>2) &1; - - if ( index_b >= 15345000-965 ) - index_x2b = 4092; //Hold logic for x2b - uint8_t x2b = (x_buf[index_x2b%4093]>>3) &1; + if (index >= (Code_length - X2A_last_hold)){ + index_x2a = X2A_period - 1 ; //Hold logic for x2a + } + uint8_t x2a = (x_buf[index_x2a % X2A_period]>>2) &1; + + if ( index >= Code_length - X2B_last_hold){ + index_x2b = X2B_period - 1; //Hold logic for x2b + } + uint8_t x2b = (x_buf[index_x2b % X2B_period]>>3) &1; return x2a ^ x2b; } uint8_t cep_gps::pcode_lookup(uint8_t * x_buf, uint64_t index, uint8_t prn) { uint8_t day = (prn-1)/37; - prn = prn - 37*day; index += CHIP_RATE*86400*day; - uint64_t index_x2 = (CODE_LENGTH + index - prn) % CODE_LENGTH; //pre add CODE_LENGTH, otherwise problems with index-prn being negative - index %= CODE_LENGTH; + uint64_t index_x2 = (Code_length + index - prn) % Code_length; //pre add CODE_LENGTH, otherwise problems with index-prn being negative + index %= Code_length; uint8_t p_x1 = x1_lookup(x_buf, index); uint8_t p_x2 = x2_lookup(x_buf, index_x2); - - if (index_x2>=CODE_LENGTH-4092) { - p_x2 = x2_lookup_last(x_buf, index_x2); + if ((index_x2>= Code_length - X1A_period) ) { + p_x2 = x2_lookup_last(x_buf, index_x2); } return p_x1 ^ p_x2; @@ -261,8 +307,9 @@ uint8_t cep_gps::pcode_lookup(uint8_t * x_buf, uint64_t index, uint8_t prn) { // Generate an expected 128-bit P code value void cep_gps::GenP_Code(void) { - if (m_pcode_index == 4096) - m_pcode_index = 0; + if (m_pcode_index == x_buf_size){ + m_pcode_index = 0; + } for (int i = 0; i < 128; i+=4) { uint8_t code = 0; @@ -277,7 +324,6 @@ void cep_gps::GenP_Code(void) { // Upper nibble else mSwPt[i/8] |= (code & 0x0F); - } } // void cep_gps::GenP_Code(void) @@ -572,7 +618,6 @@ int cep_gps::RunGpsTest(int maxLoop) { for (int i = 0; i < 192 / 8 ; i++) { mKEY[i] = 0xAA; } - //Check first 128 bits of all SAT numbers //Except sat=1, for that get 2nd 128 bits for a total of 256. for (int i = 1 ; i <= maxLoop; i++) { @@ -599,7 +644,6 @@ int cep_gps::RunGpsTest(int maxLoop) { if (mErrCnt) break; } // for (int i=1 ; i <= maxLoop; i++) - if (!mErrCnt) { //HW Coverage test: SetSvNum(0); // so GPS can detect a change @@ -609,14 +653,13 @@ int cep_gps::RunGpsTest(int maxLoop) { // Static mode, the initialization vectors will NOT be changed if (!mStaticPCodeInit) { SetPcodeXnInit(120, 3666, 766, 1474); //_A loops over 10 values, _B loops over 9 values. -// SetPcodeSpeed(163, 174763); //Xn: XnA epoch = 24 loops, XnB reaches end in only 23. } // if (!mLegacyPCode) ResetCA_Code(); SetSvNum(1); //Need to record a total of 3*24*10 = 720 bits total. This requires 6 loops. - for (int i = 0; i <= 6; i++) { + for (int i = 0; i <= 5; i++) { if (GetVerbose()) { LOGI("%s: Coverage Loop %d\n",__FUNCTION__,i); } diff --git a/sims/cep_cosim/drivers/cep_tests/cep_gps.h b/sims/cep_cosim/drivers/cep_tests/cep_gps.h index 3730d04..1f982bd 100644 --- a/sims/cep_cosim/drivers/cep_tests/cep_gps.h +++ b/sims/cep_cosim/drivers/cep_tests/cep_gps.h @@ -26,7 +26,6 @@ #define X2B_PERIOD 4093 #define CHIP_RATE ((uint64_t)10230000) -#define CODE_LENGTH (CHIP_RATE * 86400 * 7) // // CEP's GPS diff --git a/sims/cep_cosim/drivers/diag/cepCsrTest.cc b/sims/cep_cosim/drivers/diag/cepCsrTest.cc index b258eef..cb5ec43 100644 --- a/sims/cep_cosim/drivers/diag/cepCsrTest.cc +++ b/sims/cep_cosim/drivers/diag/cepCsrTest.cc @@ -45,10 +45,10 @@ extern void regBaseTest_Construct(regBaseTest_t *me, int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verbose) { int errCnt = 0; + #if (BARE_MODE || LINUX_MODE) uint64_t dat64; -#if 1 uint64_t saveCustom; // // testing custom CSR @0x7c1 @@ -67,52 +67,22 @@ int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb if (errCnt) goto apiDone; // put back asm volatile ("csrw 0x7c1,%0" : : "r"(saveCustom)); -#endif - - // - // - regBaseTest_t *regp; // - // - cepCsrTest_CREATE(regp,cpuId, accessSize, seed + (cpuId*100),verbose); - - // - // start adding register to test - // - //(*regp->AddAReg_p)(regp, CSR_MUCOUNTEREN,(uint64_t)(1<<32)-1); - //(*regp->AddAReg_p)(regp, CSR_MSCOUNTEREN,(uint64_t)(1<<32)-1); - //(*regp->AddAReg_p)(regp, CSR_DSCRATCH,(uint64_t)(-1)); // trap! - //(*regp->AddAReg_p)(regp, CSR_SBADADDR,(uint64_t)(-1)); - //(*regp->AddAReg_p)(reagp, CSR_MISA,(uint64_t)(-1)); // can't write - /* - */ - - // (*regp->AddAReg_p)(regp, CSR_SPTBR,(uint32_t)(-1)); // bit[1:0] = 0 - //(*regp->AddAReg_p)(regp, CSR_MINSTRET,(uint32_t)(-1)); // bit[1:0] = 0 - //(*regp->AddAReg_p)(regp, CSR_TDATA2,(uint32_t)(-1)); // bit[1:0] = 0 - // - //(*regp->AddAReg_p)(regp, CSR_DPC,(uint32_t)(-1)-1); // bit[1:0] = 0 - //(*regp->AddAReg_p)(regp, CSR_DSCRATCH,(uint32_t)(-1)-1); // bit[1:0] = 0 + regBaseTest_t *regp; + cepCsrTest_CREATE(regp,cpuId, accessSize, seed + (cpuId*100),verbose); - // // Some holes - // // Read Only (*regp->SetNoWr2ROreg_p)(regp, 1); - // + (*regp->AddROReg_p)(regp, CSR_MISA, 0x800000000094112d, (uint64_t)(-1)); (*regp->AddROReg_p)(regp, CSR_MVENDORID,0x0000000000000000, (uint64_t)(-1)); (*regp->AddROReg_p)(regp, CSR_MARCHID, 0x0000000000000001, (uint64_t)(-1)); (*regp->AddROReg_p)(regp, CSR_MIMPID, 0x0000000020181004, (uint64_t)(-1)); (*regp->AddROReg_p)(regp, CSR_MHARTID, cpuId, (uint64_t)(-1)); - //#ifdef SIM_ENV_ONLY -#if 1 - // - // working - // - (*regp->AddAReg_p)(regp, CSR_MTVAL, 0); // 0xFFFFFFFFF0); // 40 bits + (*regp->AddAReg_p)(regp, CSR_MBADADDR, 0); // 0xFFFFFFFFF0); // 40 bits (*regp->AddAReg_p)(regp, CSR_MTVEC, 0xFFFFFF00); // (*regp->AddAReg_p)(regp, CSR_MEDELEG,(uint64_t)(0)); // full write/no read (*regp->AddAReg_p)(regp, CSR_MIDELEG,(uint64_t)(0)); // full write/no read @@ -120,73 +90,25 @@ int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb (*regp->AddAReg_p)(regp, CSR_MEPC,0xFFFFFFFFFC); // 40 bits (*regp->AddAReg_p)(regp, CSR_SSCRATCH,(uint64_t)(-1)); (*regp->AddAReg_p)(regp, CSR_MSCRATCH,(uint64_t)(-1)); - // - // cfg0 contains 8 cfg for PMPAdr0-7 - // - //(*regp->AddAReg_p)(regp, CSR_PMPCFG0,(uint64_t)(-1)); - (*regp->AddAReg_p)(regp, CSR_PMPADDR0,((uint64_t)(1) << 30) -1); // 30 bits? - (*regp->AddAReg_p)(regp, CSR_PMPADDR1,((uint64_t)(1) << 30) -1); - (*regp->AddAReg_p)(regp, CSR_PMPADDR2,((uint64_t)(1) << 30) -1); - (*regp->AddAReg_p)(regp, CSR_PMPADDR3,((uint64_t)(1) << 30) -1); - (*regp->AddAReg_p)(regp, CSR_PMPADDR4,((uint64_t)(1) << 30) -1); - (*regp->AddAReg_p)(regp, CSR_PMPADDR5,((uint64_t)(1) << 30) -1); - (*regp->AddAReg_p)(regp, CSR_PMPADDR6,((uint64_t)(1) << 30) -1); - (*regp->AddAReg_p)(regp, CSR_PMPADDR7,((uint64_t)(1) << 30) -1); - -#endif - /* - (*regp->AddAReg_p)(regp, CSR_STVEC,(uint64_t)(-1)); - (*regp->AddAReg_p)(regp, CSR_SIE,(uint64_t)(-1)); - (*regp->AddAReg_p)(regp, CSR_SEPC,(uint64_t)(-1)); - */ - - // - // now do it + errCnt = (*regp->doRegTest_p)(regp); - // - // custom - // - - // - // These to toggle PMP_mask all bit to 1 - // - // load CSR_PMPCFG0 with - // bit[7] = Lock - // bit[6:5] = -NA- - // [4:3] = A = - // 0 : disable - // 1 : TOR: top-of-range - // 2 : NA4 - // 3 : NAPOT - // [2] = X - // [1] = W - // [0] = R - //#ifdef SIM_ENV_ONLY -#if 1 - //regWr(`CSR_PMPCFG0, {8{8'b0_00_11_1_1_1}}); - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPCFG0,0x7F7F7F7F7F7F7F7F); - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPADDR0,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPADDR1,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPADDR2,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPADDR3,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPADDR4,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPADDR5,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPADDR6,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPADDR7,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPCFG0,0); - errCnt += cepCsrTest_WriteEntry(regp, CSR_PMPCFG0,(uint64_t)(-1)); // with lock - // - // - // some write-Only - // - // - errCnt += cepCsrTest_WriteEntry(regp, CSR_STVAL,(uint64_t)(-1)); - errCnt += cepCsrTest_WriteEntry(regp, CSR_SATP,(uint64_t)(-1)); - errCnt += cepCsrTest_WriteEntry(regp, CSR_MCOUNTEREN,(uint64_t)(-1)); + errCnt += cepCsrTest_WriteEntry(regp, CSR_MHPMCOUNTER3,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s + errCnt += cepCsrTest_WriteEntry(regp, CSR_MHPMCOUNTER4,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s + errCnt += cepCsrTest_WriteEntry(regp, CSR_MHPMCOUNTER5,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s + errCnt += cepCsrTest_WriteEntry(regp, CSR_MHPMCOUNTER6,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s + errCnt += cepCsrTest_WriteEntry(regp, CSR_MHPMCOUNTER7,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s + errCnt += cepCsrTest_WriteEntry(regp, CSR_MHPMCOUNTER8,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s + errCnt += cepCsrTest_WriteEntry(regp, CSR_MHPMCOUNTER9,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s + errCnt += cepCsrTest_WriteEntry(regp, CSR_MHPMCOUNTER10,(1 << 29)-1); // 'b0_<29bits Of1 = mask = all 1s + + // Write-Only + errCnt += cepCsrTest_WriteEntry(regp, CSR_SBADADDR,(uint64_t)(-1)); + errCnt += cepCsrTest_WriteEntry(regp, CSR_SPTBR,(uint64_t)(-1)); errCnt += cepCsrTest_WriteEntry(regp, CSR_MINSTRET,(uint64_t)(-1)); - // + errCnt += cepCsrTest_WriteEntry(regp, CSR_MISA,(uint64_t)(-1)); + // the rest of them just read to complete a full decoding dat64 += cepCsrTest_ReadEntry(regp,CSR_HPMCOUNTER4 ); dat64 += cepCsrTest_ReadEntry(regp,CSR_HPMCOUNTER5 ); @@ -199,11 +121,10 @@ int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb dat64 += cepCsrTest_ReadEntry(regp,CSR_HPMCOUNTER27 ); dat64 += cepCsrTest_ReadEntry(regp,CSR_HPMCOUNTER29 ); dat64 += cepCsrTest_ReadEntry(regp,CSR_HPMCOUNTER31 ); - dat64 += cepCsrTest_ReadEntry(regp,CSR_PMPCFG2 ); - dat64 += cepCsrTest_ReadEntry(regp,CSR_PMPADDR9 ); - dat64 += cepCsrTest_ReadEntry(regp,CSR_PMPADDR10 ); - dat64 += cepCsrTest_ReadEntry(regp,CSR_PMPADDR11 ); - dat64 += cepCsrTest_ReadEntry(regp,CSR_PMPADDR12 ); + dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMCOUNTER9 ); + dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMCOUNTER10 ); + dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMCOUNTER11 ); + dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMCOUNTER12 ); dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMCOUNTER3 ); dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMCOUNTER4 ); dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMCOUNTER5 ); @@ -233,13 +154,12 @@ int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMEVENT28 ); dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMEVENT29 ); dat64 += cepCsrTest_ReadEntry(regp,CSR_MHPMEVENT30 ); -#endif - // + // Destructors - // cepCsrTest_DELETE(regp); + #endif - // + apiDone: return errCnt; } diff --git a/sims/cep_cosim/drivers/diag/cepMaskromTest.cc b/sims/cep_cosim/drivers/diag/cepMaskromTest.cc index 66ecfb8..7e410b3 100644 --- a/sims/cep_cosim/drivers/diag/cepMaskromTest.cc +++ b/sims/cep_cosim/drivers/diag/cepMaskromTest.cc @@ -37,8 +37,8 @@ int cepMaskromTest_runTest(int cpuId, int seed, int verbose) { uint8_t dat8, edat8; // from bootrom.rv64.dump - uint32_t known_pat1 = 0x00008137; // location 0 - uint32_t known_pat0 = 0x0071011b; // location 4 + uint32_t known_pat1 = 0x00080137; // location 0 + uint32_t known_pat0 = 0x07f1011b; // location 4 offs = bootrom_base_addr; // + ((1<<13)-8); // 64-bit diff --git a/sims/cep_cosim/drivers/diag/cepRegTest.cc b/sims/cep_cosim/drivers/diag/cepRegTest.cc index 84ba1af..e357c91 100644 --- a/sims/cep_cosim/drivers/diag/cepRegTest.cc +++ b/sims/cep_cosim/drivers/diag/cepRegTest.cc @@ -113,22 +113,14 @@ int cepRegTest_runTest(int cpuId, int accessSize, int revCheck, int seed, int ve break; } } + // add some holes to punch for coverage - /* - for (int i=0;iAddAHole_p)(regp, cep_core_info[i].base_address + 0xFFF8,(uint64_t)(-1)); - } - */ - // from 0x700x_xxxx - 0x7FFx_xxxx (*regp->AddAHole_p)(regp, interrupt_controller_base_addr + 0xFF8,(uint64_t)(-1)); - //(*regp->AddAHole_p)(regp, 0x7FFFFFF8,(uint64_t)(-1)); - // - // now do it + // Run the test errCnt = (*regp->doRegTest_p)(regp); - // + // Destructors - // cepRegTest_DELETE(regp); // // diff --git a/sims/firesim b/sims/firesim deleted file mode 160000 index f424359..0000000 --- a/sims/firesim +++ /dev/null @@ -1 +0,0 @@ -Subproject commit f42435985182f1f3a484605ba9ae7a287c0a9b10 diff --git a/software/baremetal/template/.gitignore b/software/baremetal/gpiotest/.gitignore similarity index 100% rename from software/baremetal/template/.gitignore rename to software/baremetal/gpiotest/.gitignore diff --git a/software/baremetal/gpiotest/Makefile b/software/baremetal/gpiotest/Makefile index fe4855f..aa3f313 100644 --- a/software/baremetal/gpiotest/Makefile +++ b/software/baremetal/gpiotest/Makefile @@ -15,6 +15,7 @@ ifndef RISCV $(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file) endif +BOARD ?= arty_a7_100 BASEDIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) INCDIR := $(BASEDIR)/include MAINPROGRAM ?= gpiotest @@ -22,13 +23,26 @@ MAINPROGRAM ?= gpiotest CC := riscv64-unknown-elf-gcc OBJDUMP := riscv64-unknown-elf-objdump OBJCOPY := riscv64-unknown-elf-objcopy -CFLAGS := -mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -Wno-unused-function +CFLAGS := -mcmodel=medany -O2 -fno-common -fno-builtin-printf -fno-builtin-puts -Wall -Wno-unused-function CFLAGS += -I $(INCDIR) LDFLAGS := -static -nostdlib -nostartfiles -lgcc +ifeq ($(BOARD),arty_a7_100) +CFLAGS += -DARTY100T_TARGET +else ifeq ($(BOARD),vc707) +CFLAGS += -DVC707_TARGET +else ifeq ($(BOARD),vcu118) +CFLAGS += -DVCU118_TARGET +else +$(error $(BOARD) is not a supported BOARD target...) +endif OBJS := crt.o syscalls.o kprintf.o LDSCRIPT := link.ld HDRS := $(wildcard *.h) $(wildcard $(INCDIR)/*.h) +$(info ) +$(info Build for $(BOARD)...) +$(info ) + %.o: %.c $(HDRS) $(CC) $(CFLAGS) -o $@ -c $< %.o: %.S $(hdrs) diff --git a/software/baremetal/gpiotest/gpiotest.c b/software/baremetal/gpiotest/gpiotest.c index 144b10a..00cc781 100644 --- a/software/baremetal/gpiotest/gpiotest.c +++ b/software/baremetal/gpiotest/gpiotest.c @@ -6,32 +6,82 @@ // Program: Common Evaluation Platform // Description: A program that sets up the GPIO to read the // Arty100T switches and set the User LEDs accordingly -// Notes: +// Notes: GPIO mapping from arty100t_gpio.h // //************************************************************************ #include +#include #include "encoding.h" #include "compiler.h" #include "kprintf.h" #include "platform.h" #include "mmio.h" +#define DEBOUNCE_CNT 10 +#define DEBOUNCE_WS 50000 + +// A simple routine to debouce gpio reads +uint32_t get_gpio_debounced(uint32_t mask) { + + uint32_t gpio_old = 0; + uint32_t gpio_new = 0; + int debounce_counter = 0; + + while (debounce_counter < DEBOUNCE_CNT) { + gpio_new = reg_read32((uintptr_t)(GPIO_CTRL_ADDR + GPIO_INPUT_VAL)) & mask; + + // Introduce some wait states beteween reads + for (volatile int i = 0; i < DEBOUNCE_WS; i++) {} + + if (gpio_new == gpio_old) { + debounce_counter++; + } else { + debounce_counter = 0; + } + + gpio_old = gpio_new; + + } // end while + + return gpio_new; + +} // get_switch + + int main() { - kputs(""); - kputs(""); - kputs("------------------"); - kputs(" RISC-V GPIO Test "); - kputs("------------------"); - kputs(""); - kputs(""); + int c; + + // Enable UART TX & RX (let's not assume the bootrom did it) + REG32(uart, UART_REG_TXCTRL) |= UART_TXEN; + REG32(uart, UART_REG_RXCTRL) |= UART_RXEN; + + puts(""); + puts(""); + puts("--------------------------"); + puts(" RISC-V GPIO Test "); + puts("--------------------------"); +#ifdef VCU118_TARGET + puts(" Built for VCU118"); +#elif VC707_TARGET + puts(" Built for VC707"); +#else + puts(" Built for Arty100T"); +#endif + puts(" Console Echo Enabled "); + puts(""); + puts(""); - uint32_t switch_old = 0xFFFFFFFF; - uint32_t switch_new = 0; + uint32_t gpio_old = 0xFFFFFFFF; + uint32_t gpio_new = 0; // Enable the switch inputs +#if defined(VCU118_TARGET) || defined(VC707_TARGET) + reg_write32((uintptr_t)(GPIO_CTRL_ADDR + GPIO_INPUT_EN), (uint32_t)(SWN_MASK | SWE_MASK | SWS_MASK | SWW_MASK)); +#else reg_write32((uintptr_t)(GPIO_CTRL_ADDR + GPIO_INPUT_EN), (uint32_t)(SW0_MASK | SW1_MASK | SW2_MASK | SW3_MASK)); +#endif // Enable the LED outputs reg_write32((uintptr_t)(GPIO_CTRL_ADDR + GPIO_OUTPUT_EN), (uint32_t)(LED0_MASK | LED1_MASK | LED2_MASK | LED3_MASK)); @@ -39,15 +89,30 @@ int main() { // Infinite loop where you read the switches and write the LEDs while (1) { - switch_new = (reg_read32((uintptr_t)(GPIO_CTRL_ADDR + GPIO_INPUT_VAL)) >> 8) & 0xFF; + // Get the switches state +#if defined(VCU118_TARGET) || defined(VC707_TARGET) + gpio_new = get_gpio_debounced(SWN_MASK | SWE_MASK | SWS_MASK | SWW_MASK); +#else + gpio_new = get_gpio_debounced(SW0_MASK | SW1_MASK | SW2_MASK | SW3_MASK); +#endif + + // A change of switch state has been detected... post debounce + if (gpio_new != gpio_old) { + printf("gpio = %08x\n", gpio_new); + gpio_old = gpio_new; + } - // A change of switch state has been detected... post debounce - if (switch_new != switch_old) { - kprintf("switches = %x\n\r", switch_new); - switch_old = switch_new; - } + // A simple tty echo routine where CR and LF are converted to CR+LF (getchar, which mapps to kgetc in baremetal, is non-blocking) + c = getchar(); + if (c == '\r' || c == '\n') { + putchar('\r'); + putchar('\n'); + } else if (c >= 0) { + putchar(c); + } - reg_write32((uintptr_t)(GPIO_CTRL_ADDR + GPIO_OUTPUT_VAL), switch_new << 16); + // Write the LEDs + reg_write32((uintptr_t)(GPIO_CTRL_ADDR + GPIO_OUTPUT_VAL), (gpio_new & SWtoLED_MASK) << SWtoLED_SHIFT); } return 0; diff --git a/software/baremetal/gpiotest/include/devices/arty100t_gpio.h b/software/baremetal/gpiotest/include/devices/arty100t_gpio.h index d9d2d62..497bbf2 100644 --- a/software/baremetal/gpiotest/include/devices/arty100t_gpio.h +++ b/software/baremetal/gpiotest/include/devices/arty100t_gpio.h @@ -1,3 +1,15 @@ +//************************************************************************ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: arty100t_gpio.h +// Program: Common Evaluation Platform +// Description: Bit mappings for the CEP's Arty100T GPIO +// Notes: +// +//************************************************************************ + +#ifdef ARTY100T_TARGET #ifndef _ARTY100T_GPIO_H #define _ARTY100T_GPIO_H @@ -22,4 +34,8 @@ #define LED2_MASK (0x00040000) #define LED3_MASK (0x00080000) +#define SWtoLED_SHIFT 8 +#define SWtoLED_MASK (0x00000F00) + #endif /* _ARTY100T_GPIO_H */ +#endif /* ARTY100T_TARGET */ \ No newline at end of file diff --git a/software/baremetal/gpiotest/include/devices/vc707_gpio.h b/software/baremetal/gpiotest/include/devices/vc707_gpio.h new file mode 100644 index 0000000..1362915 --- /dev/null +++ b/software/baremetal/gpiotest/include/devices/vc707_gpio.h @@ -0,0 +1,42 @@ +//************************************************************************ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: arty100t_gpio.h +// Program: Common Evaluation Platform +// Description: Bit mappings for the CEP's Arty100T GPIO +// Notes: +// +//************************************************************************ + +#ifdef VC707_TARGET +#ifndef _VC707_GPIO_H +#define _VC707_GPIO_H + +#define SW0_MASK (0x00000001) +#define SW1_MASK (0x00000002) +#define SW2_MASK (0x00000004) +#define SW3_MASK (0x00000008) +#define SW4_MASK (0x00000010) +#define SW5_MASK (0x00000020) +#define SW6_MASK (0x00000040) +#define SW7_MASK (0x00000080) +#define SWN_MASK (0x00000100) +#define SWE_MASK (0x00000200) +#define SWS_MASK (0x00000400) +#define SWW_MASK (0x00000800) +#define SWC_MASK (0x00001000) +#define LED0_MASK (0x00002000) +#define LED1_MASK (0x00004000) +#define LED2_MASK (0x00008000) +#define LED3_MASK (0x00010000) +#define LED4_MASK (0x00020000) +#define LED5_MASK (0x00040000) +#define LED6_MASK (0x00080000) +#define LED7_MASK (0x00100000) + +#define SWtoLED_SHIFT 13 +#define SWtoLED_MASK (0x000000FF) + +#endif /* _VC707_GPIO_H */ +#endif /* VC707_TARGET */ \ No newline at end of file diff --git a/software/baremetal/gpiotest/include/devices/vcu118_gpio.h b/software/baremetal/gpiotest/include/devices/vcu118_gpio.h new file mode 100644 index 0000000..5b9f090 --- /dev/null +++ b/software/baremetal/gpiotest/include/devices/vcu118_gpio.h @@ -0,0 +1,38 @@ +//************************************************************************ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: arty100t_gpio.h +// Program: Common Evaluation Platform +// Description: Bit mappings for the CEP's Arty100T GPIO +// Notes: +// +//************************************************************************ + +#ifdef VCU118_TARGET +#ifndef _VCU118_GPIO_H +#define _VCU118_GPIO_H + +#define SW0_MASK (0x00000001) +#define SW1_MASK (0x00000002) +#define SW2_MASK (0x00000004) +#define SW3_MASK (0x00000008) +#define SWN_MASK (0x00000010) +#define SWE_MASK (0x00000020) +#define SWW_MASK (0x00000040) +#define SWS_MASK (0x00000080) +#define SWC_MASK (0x00000100) +#define LED0_MASK (0x00000200) +#define LED1_MASK (0x00000400) +#define LED2_MASK (0x00000800) +#define LED3_MASK (0x00001000) +#define LED4_MASK (0x00002000) +#define LED5_MASK (0x00004000) +#define LED6_MASK (0x00008000) +#define LED7_MASK (0x00010000) + +#define SWtoLED_SHIFT 5 +#define SWtoLED_MASK (0x000001F0) + +#endif /* _VCU118_GPIO_H */ +#endif /* VCU118_TARGET */ \ No newline at end of file diff --git a/software/baremetal/gpiotest/include/kprintf.h b/software/baremetal/gpiotest/include/kprintf.h index a7a9486..2733e2d 100644 --- a/software/baremetal/gpiotest/include/kprintf.h +++ b/software/baremetal/gpiotest/include/kprintf.h @@ -2,11 +2,13 @@ #ifndef _SDBOOT_KPRINTF_H #define _SDBOOT_KPRINTF_H -#include #include +#include #define REG32(p, i) ((p)[(i) >> 2]) +#define UART_RXEMPTY (1 << 31) + #ifndef UART_CTRL_ADDR #ifndef UART_NUM #define UART_NUM 0 @@ -18,32 +20,9 @@ #endif static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); -static inline void kputc(char c) -{ - volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); -#ifdef __riscv_atomic - int32_t r; - do { - __asm__ __volatile__ ( - "amoor.w %0, %2, %1\n" - : "=r" (r), "+A" (*tx) - : "r" (c)); - } while (r < 0); -#else - while ((int32_t)(*tx) < 0); - *tx = c; -#endif -} - -extern void kputs(const char *); -extern void kprintf(const char *, ...); -#ifdef DEBUG -#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) -#define dputs(s) kputs((s)) -#else -#define dprintf(s, ...) do { } while (0) -#define dputs(s) do { } while (0) -#endif +void kputc(int c); +int kgetc(void); +void kputs(const char *); #endif /* _SDBOOT_KPRINTF_H */ diff --git a/software/baremetal/gpiotest/include/platform.h b/software/baremetal/gpiotest/include/platform.h index 326a9c9..458caac 100644 --- a/software/baremetal/gpiotest/include/platform.h +++ b/software/baremetal/gpiotest/include/platform.h @@ -20,6 +20,8 @@ #include "devices/uart.h" #include "devices/cepregs.h" #include "devices/arty100t_gpio.h" +#include "devices/vc707_gpio.h" +#include "devices/vcu118_gpio.h" // Some things missing from the official encoding.h #if __riscv_xlen == 32 diff --git a/software/baremetal/gpiotest/kprintf.c b/software/baremetal/gpiotest/kprintf.c index 3e3f218..bbb47e8 100644 --- a/software/baremetal/gpiotest/kprintf.c +++ b/software/baremetal/gpiotest/kprintf.c @@ -2,74 +2,42 @@ #include #include #include - #include "kprintf.h" -static inline void _kputs(const char *s) +void kputc(int c) { - char c; - for (; (c = *s) != '\0'; s++) - kputc(c); +#ifndef DISABLE_KPRINTF + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); + while ((int32_t)(*tx) < 0); + *tx = (c & 0xFF); +#endif } -void kputs(const char *s) +int kgetc(void) { - _kputs(s); - kputc('\r'); - kputc('\n'); +#ifndef DISABLE_KPRINTF + uint32_t ch; + volatile uint32_t *rx = ®32(uart, UART_REG_RXFIFO); + ch = *rx; + + if ((uint32_t)(ch & UART_RXEMPTY)) { + return -1; + } else { + return(ch & 0x0ff); + } +#else + return -1; +#endif } -void kprintf(const char *fmt, ...) +void kputs(const char *s) { - va_list vl; - bool is_format, is_long, is_char; - char c; - - va_start(vl, fmt); - is_format = false; - is_long = false; - is_char = false; - while ((c = *fmt++) != '\0') { - if (is_format) { - switch (c) { - case 'l': - is_long = true; - continue; - case 'h': - is_char = true; - continue; - case 'x': { - unsigned long n; - long i; - if (is_long) { - n = va_arg(vl, unsigned long); - i = (sizeof(unsigned long) << 3) - 4; - } else { - n = va_arg(vl, unsigned int); - i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; - } - for (; i >= 0; i -= 4) { - long d; - d = (n >> i) & 0xF; - kputc(d < 10 ? '0' + d : 'a' + d - 10); - } - break; - } - case 's': - _kputs(va_arg(vl, const char *)); - break; - case 'c': - kputc(va_arg(vl, int)); - break; - } - is_format = false; - is_long = false; - is_char = false; - } else if (c == '%') { - is_format = true; - } else { - kputc(c); - } - } - va_end(vl); -} + char c; + while (*s != '\0') { + c = *s; + kputc((int) c); + s++; + } + kputc('\r'); + kputc('\n'); +} \ No newline at end of file diff --git a/software/baremetal/gpiotest/syscalls.c b/software/baremetal/gpiotest/syscalls.c index c2be98a..226fff4 100644 --- a/software/baremetal/gpiotest/syscalls.c +++ b/software/baremetal/gpiotest/syscalls.c @@ -1,3 +1,14 @@ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: syscalls.c +// Program: Common Evaluation Platform (CEP) +// Description: Modified baremetal system calls for RISC-V +// Notes: Roll +// +//-------------------------------------------------------------------------------------- + + // See LICENSE for license details. #include @@ -7,8 +18,8 @@ #include #include #include -#include "util.h" #include "kprintf.h" +#include "util.h" #define SYS_write 64 @@ -17,24 +28,6 @@ extern volatile uint64_t tohost; extern volatile uint64_t fromhost; -static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2) -{ - volatile uint64_t magic_mem[8] __attribute__((aligned(64))); - magic_mem[0] = which; - magic_mem[1] = arg0; - magic_mem[2] = arg1; - magic_mem[3] = arg2; - __sync_synchronize(); - - tohost = (uintptr_t)magic_mem; - while (fromhost == 0) - ; - fromhost = 0; - - __sync_synchronize(); - return magic_mem[0]; -} - #define NUM_COUNTERS 2 static uintptr_t counters[NUM_COUNTERS]; static char* counter_names[NUM_COUNTERS]; @@ -76,9 +69,13 @@ void abort() exit(128 + SIGABRT); } -void printstr(const char* s) +// Syscall is currently disabled as it does +// not function properly in simulation +int puts(const char* s) { - syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); + kputs(s); + + return 0; } void __attribute__((weak)) thread_entry(int cid, int nc) @@ -91,7 +88,7 @@ void __attribute__((weak)) thread_entry(int cid, int nc) int __attribute__((weak)) main(int argc, char** argv) { // single-threaded programs override this function. - printstr("Implement main(), foo!\n"); + puts("Implement main(), foo!\n"); return -1; } @@ -108,9 +105,7 @@ static void init_tls() void _init(int cid, int nc) { - - // The memset within init_tls does not seem to work correctly on an arty100t build with a single medium core - //init_tls(); + init_tls(); thread_entry(cid, nc); // only single-threaded programs should ever get here. @@ -122,24 +117,22 @@ void _init(int cid, int nc) if (counters[i]) pbuf += sprintf(pbuf, "%s = %" PRIuPTR "\n", counter_names[i], counters[i]); if (pbuf != buf) - printstr(buf); + puts(buf); exit(ret); } -#undef putchar -int putchar(int ch) +#undef getchar +int getchar() { - static __thread char buf[64] __attribute__((aligned(64))); - static __thread int buflen = 0; + return kgetc(); +} - buf[buflen++] = ch; - if (ch == '\n' || buflen == sizeof(buf)) - { - syscall(SYS_write, 1, (uintptr_t)buf, buflen); - buflen = 0; - } +#undef putchar +int putchar(int ch) +{ + kputc(ch); return 0; } @@ -155,7 +148,7 @@ void printhex(uint64_t x) } str[16] = 0; - printstr(str); + puts(str); } static inline void printnum(void (*putch)(int, void**), void **putdat, @@ -210,10 +203,16 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt while (1) { while ((ch = *(unsigned char *) fmt) != '%') { - if (ch == '\0') + if (ch == '\0') { return; - fmt++; - putch(ch, putdat); + } else if (ch == '\n') { + putch('\n', putdat); + putch('\r', putdat); + fmt++; + } else { + putch(ch, putdat); + fmt++; + } } fmt++; @@ -348,14 +347,15 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt } } +// Calling of putchar from printf is currently disabled +// as syscalls do not function correctly int printf(const char* fmt, ...) { va_list ap; va_start(ap, fmt); - - vprintfmt((void*)putchar, 0, fmt, ap); - + vprintfmt((void*)kputc, 0, fmt, ap); va_end(ap); + return 0; // incorrect return value, but who cares, anyway? } @@ -397,7 +397,6 @@ void* memcpy(void* dest, const void* src, size_t len) void* memset(void* dest, int byte, size_t len) { - if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { uintptr_t word = byte & 0xFF; word |= word << 8; @@ -470,4 +469,4 @@ long atol(const char* str) } return sign ? -res : res; -} +} \ No newline at end of file diff --git a/software/baremetal/hello_world/.gitignore b/software/baremetal/hello_world/.gitignore new file mode 100644 index 0000000..9e0a083 --- /dev/null +++ b/software/baremetal/hello_world/.gitignore @@ -0,0 +1,4 @@ +*.o +*.dump +*.elf +*.img \ No newline at end of file diff --git a/software/baremetal/template/Makefile b/software/baremetal/hello_world/Makefile similarity index 94% rename from software/baremetal/template/Makefile rename to software/baremetal/hello_world/Makefile index 4042b9c..d40abd9 100644 --- a/software/baremetal/template/Makefile +++ b/software/baremetal/hello_world/Makefile @@ -22,7 +22,7 @@ MAINPROGRAM ?= hello_world CC := riscv64-unknown-elf-gcc OBJDUMP := riscv64-unknown-elf-objdump OBJCOPY := riscv64-unknown-elf-objcopy -CFLAGS := -mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -Wno-unused-function +CFLAGS := -mcmodel=medany -O2 -fno-common -fno-builtin-printf -fno-builtin-puts -Wall -Wno-unused-function CFLAGS += -I $(INCDIR) LDFLAGS := -static -nostdlib -nostartfiles -lgcc OBJS := crt.o syscalls.o kprintf.o diff --git a/software/baremetal/template/crt.S b/software/baremetal/hello_world/crt.S similarity index 100% rename from software/baremetal/template/crt.S rename to software/baremetal/hello_world/crt.S diff --git a/software/baremetal/template/hello_world.c b/software/baremetal/hello_world/hello_world.c similarity index 76% rename from software/baremetal/template/hello_world.c rename to software/baremetal/hello_world/hello_world.c index 85038ea..9e986a9 100644 --- a/software/baremetal/template/hello_world.c +++ b/software/baremetal/hello_world/hello_world.c @@ -18,13 +18,13 @@ int main() { - kputs(""); - kputs(""); - kputs("------------------"); - kputs("RISC-V Hello World"); - kputs("------------------"); - kputs(""); - kputs(""); + puts(""); + puts(""); + puts("-------------------------------"); + puts(" Bare-Metal RISC-V Hello World "); + puts("-------------------------------"); + puts(""); + puts(""); return 0; } diff --git a/software/baremetal/hello_world/include/compiler.h b/software/baremetal/hello_world/include/compiler.h new file mode 100644 index 0000000..6771e1d --- /dev/null +++ b/software/baremetal/hello_world/include/compiler.h @@ -0,0 +1,18 @@ +#ifndef __COMPILER_H +#define __COMPILER_H + +#ifdef __GNUC__ + +#ifndef __aligned +#define __aligned(x) __attribute__ ((aligned (x))) +#endif + +#else /* !__GNU_C__ */ +#warning "Unknown compiler" + +#ifndef +#define __aligned(x) +#endif +#endif + +#endif /* __COMPILER_H */ diff --git a/software/baremetal/hello_world/include/const.h b/software/baremetal/hello_world/include/const.h new file mode 100644 index 0000000..8507e16 --- /dev/null +++ b/software/baremetal/hello_world/include/const.h @@ -0,0 +1,18 @@ +// See LICENSE.Sifive for license details. +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/software/baremetal/hello_world/include/devices/arty100t_gpio.h b/software/baremetal/hello_world/include/devices/arty100t_gpio.h new file mode 100644 index 0000000..d9d2d62 --- /dev/null +++ b/software/baremetal/hello_world/include/devices/arty100t_gpio.h @@ -0,0 +1,25 @@ +#ifndef _ARTY100T_GPIO_H +#define _ARTY100T_GPIO_H + +#define GPIO0_MASK (0x00000001) +#define GPIO1_MASK (0x00000002) +#define GPIO2_MASK (0x00000004) +#define GPIO3_MASK (0x00000008) +#define GPIO4_MASK (0x00000010) +#define GPIO5_MASK (0x00000020) +#define GPIO6_MASK (0x00000040) +#define GPIO7_MASK (0x00000080) +#define SW0_MASK (0x00000100) +#define SW1_MASK (0x00000200) +#define SW2_MASK (0x00000400) +#define SW3_MASK (0x00000800) +#define BTN0_MASK (0x00001000) +#define BTN1_MASK (0x00002000) +#define BTN2_MASK (0x00004000) +#define BTN3_MASK (0x00008000) +#define LED0_MASK (0x00010000) +#define LED1_MASK (0x00020000) +#define LED2_MASK (0x00040000) +#define LED3_MASK (0x00080000) + +#endif /* _ARTY100T_GPIO_H */ diff --git a/software/baremetal/hello_world/include/devices/cepregs.h b/software/baremetal/hello_world/include/devices/cepregs.h new file mode 100644 index 0000000..6a73d0a --- /dev/null +++ b/software/baremetal/hello_world/include/devices/cepregs.h @@ -0,0 +1,22 @@ +// See LICENSE.Sifive for license details. + +#ifndef _CEPREGS_H +#define _CEPREGS_H + +/* Register offsets */ +#define CEPREGS_VERSION 0x0000 +#define CEPREGS_TESTNSET 0xFD10 +#define CEPREGS_SCRATCH_W0 0xFE00 +#define CEPREGS_SCRATCH_W1 0xFE08 +#define CEPREGS_SCRATCH_W2 0xFE10 +#define CEPREGS_SCRATCH_W3 0xFE18 +#define CEPREGS_SCRATCH_W4 0xFE20 +#define CEPREGS_SCRATCH_W5 0xFE28 +#define CEPREGS_SCRATCH_W6 0xFE30 +#define CEPREGS_SCRATCH_W7 0xFE38 +#define CEPREGS_CORE0_STATUS 0xFF00 +#define CEPREGS_CORE1_STATUS 0xFF08 +#define CEPREGS_CORE2_STATUS 0xFF10 +#define CEPREGS_CORE3_STATUS 0xFF18 + +#endif /* _CEPREGS_H */ diff --git a/software/baremetal/hello_world/include/devices/clint.h b/software/baremetal/hello_world/include/devices/clint.h new file mode 100644 index 0000000..08092cd --- /dev/null +++ b/software/baremetal/hello_world/include/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE.Sifive for license details. + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/software/baremetal/hello_world/include/devices/gpio.h b/software/baremetal/hello_world/include/devices/gpio.h new file mode 100644 index 0000000..76dcb9f --- /dev/null +++ b/software/baremetal/hello_world/include/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE.Sifive for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/software/baremetal/hello_world/include/devices/plic.h b/software/baremetal/hello_world/include/devices/plic.h new file mode 100644 index 0000000..eddcae9 --- /dev/null +++ b/software/baremetal/hello_world/include/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE.Sifive for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/software/baremetal/hello_world/include/devices/spi.h b/software/baremetal/hello_world/include/devices/spi.h new file mode 100644 index 0000000..85c1099 --- /dev/null +++ b/software/baremetal/hello_world/include/devices/spi.h @@ -0,0 +1,79 @@ +// See LICENSE.Sifive for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#endif /* _SIFIVE_SPI_H */ diff --git a/software/baremetal/hello_world/include/devices/uart.h b/software/baremetal/hello_world/include/devices/uart.h new file mode 100644 index 0000000..c3f6a53 --- /dev/null +++ b/software/baremetal/hello_world/include/devices/uart.h @@ -0,0 +1,28 @@ +// See LICENSE.Sifive for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXNSTOP 0x2 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/software/baremetal/hello_world/include/encoding.h b/software/baremetal/hello_world/include/encoding.h new file mode 100644 index 0000000..35e0f9f --- /dev/null +++ b/software/baremetal/hello_world/include/encoding.h @@ -0,0 +1,1313 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/software/baremetal/hello_world/include/kprintf.h b/software/baremetal/hello_world/include/kprintf.h new file mode 100644 index 0000000..2733e2d --- /dev/null +++ b/software/baremetal/hello_world/include/kprintf.h @@ -0,0 +1,28 @@ +// See LICENSE.Sifive for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +#define UART_RXEMPTY (1 << 31) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + + +void kputc(int c); +int kgetc(void); +void kputs(const char *); + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/software/baremetal/hello_world/include/mmio.h b/software/baremetal/hello_world/include/mmio.h new file mode 100644 index 0000000..c37bff0 --- /dev/null +++ b/software/baremetal/hello_world/include/mmio.h @@ -0,0 +1,54 @@ +#ifndef __MMIO_H__ +#define __MMIO_H__ + +#include + +static inline void reg_write8(uintptr_t addr, uint8_t data) +{ + volatile uint8_t *ptr = (volatile uint8_t *) addr; + *ptr = data; +} + +static inline uint8_t reg_read8(uintptr_t addr) +{ + volatile uint8_t *ptr = (volatile uint8_t *) addr; + return *ptr; +} + +static inline void reg_write16(uintptr_t addr, uint16_t data) +{ + volatile uint16_t *ptr = (volatile uint16_t *) addr; + *ptr = data; +} + +static inline uint16_t reg_read16(uintptr_t addr) +{ + volatile uint16_t *ptr = (volatile uint16_t *) addr; + return *ptr; +} + +static inline void reg_write32(uintptr_t addr, uint32_t data) +{ + volatile uint32_t *ptr = (volatile uint32_t *) addr; + *ptr = data; +} + +static inline uint32_t reg_read32(uintptr_t addr) +{ + volatile uint32_t *ptr = (volatile uint32_t *) addr; + return *ptr; +} + +static inline void reg_write64(unsigned long addr, uint64_t data) +{ + volatile uint64_t *ptr = (volatile uint64_t *) addr; + *ptr = data; +} + +static inline uint64_t reg_read64(unsigned long addr) +{ + volatile uint64_t *ptr = (volatile uint64_t *) addr; + return *ptr; +} + +#endif diff --git a/sims/cep_cosim/drivers/bare/platform.h b/software/baremetal/hello_world/include/platform.h similarity index 96% rename from sims/cep_cosim/drivers/bare/platform.h rename to software/baremetal/hello_world/include/platform.h index d5940b9..326a9c9 100644 --- a/sims/cep_cosim/drivers/bare/platform.h +++ b/software/baremetal/hello_world/include/platform.h @@ -18,6 +18,8 @@ #include "devices/plic.h" #include "devices/spi.h" #include "devices/uart.h" +#include "devices/cepregs.h" +#include "devices/arty100t_gpio.h" // Some things missing from the official encoding.h #if __riscv_xlen == 32 @@ -43,7 +45,7 @@ // to avoid a circular #define scratchpad_sp_offset 0x00070000 #define scratchpad_base_addr 0x80000000 -#define scratchpad_base_size 0x00100000 +#define scratchpad_base_size 0x00080000 // Memory map #define CLINT_CTRL_ADDR _AC(0x2000000,UL) @@ -73,6 +75,7 @@ #define UART1_CTRL_SIZE _AC(0x1000,UL) #define I2C_CTRL_ADDR _AC(0x64005000,UL) #define I2C_CTRL_SIZE _AC(0x1000,UL) +#define CEPREGS_ADDR _AC(0x700F0000,UL) // IOF masks @@ -89,6 +92,7 @@ #define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) #define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) #define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) + // Bulk set bits in `reg` to either 0 or 1. // E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 // E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 @@ -121,5 +125,4 @@ // Misc - #endif /* _CHIPYARD_PLATFORM_H */ diff --git a/software/baremetal/hello_world/include/util.h b/software/baremetal/hello_world/include/util.h new file mode 100644 index 0000000..22f81cf --- /dev/null +++ b/software/baremetal/hello_world/include/util.h @@ -0,0 +1,135 @@ +// See LICENSE for license details. + +#ifndef __UTIL_H +#define __UTIL_H + +//-------------------------------------------------------------------------- +// Macros + +// Set HOST_DEBUG to 1 if you are going to compile this for a host +// machine (ie Athena/Linux) for debug purposes and set HOST_DEBUG +// to 0 if you are compiling with the smips-gcc toolchain. + +#ifndef HOST_DEBUG +#define HOST_DEBUG 0 +#endif + +// Set PREALLOCATE to 1 if you want to preallocate the benchmark +// function before starting stats. If you have instruction/data +// caches and you don't want to count the overhead of misses, then +// you will need to use preallocation. + +#ifndef PREALLOCATE +#define PREALLOCATE 0 +#endif + +// Set SET_STATS to 1 if you want to carve out the piece that actually +// does the computation. + +#if HOST_DEBUG +#include +static void setStats(int enable) {} +#else +extern void setStats(int enable); +#endif + +#include + +#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } + +static void printArray(const char name[], int n, const int arr[]) +{ +#if HOST_DEBUG + int i; + printf( " %10s :", name ); + for ( i = 0; i < n; i++ ) + printf( " %3d ", arr[i] ); + printf( "\n" ); +#endif +} + +static void printDoubleArray(const char name[], int n, const double arr[]) +{ +#if HOST_DEBUG + int i; + printf( " %10s :", name ); + for ( i = 0; i < n; i++ ) + printf( " %g ", arr[i] ); + printf( "\n" ); +#endif +} + +static int verify(int n, const volatile int* test, const int* verify) +{ + int i; + // Unrolled for faster verification + for (i = 0; i < n/2*2; i+=2) + { + int t0 = test[i], t1 = test[i+1]; + int v0 = verify[i], v1 = verify[i+1]; + if (t0 != v0) return i+1; + if (t1 != v1) return i+2; + } + if (n % 2 != 0 && test[n-1] != verify[n-1]) + return n; + return 0; +} + +static int verifyDouble(int n, const volatile double* test, const double* verify) +{ + int i; + // Unrolled for faster verification + for (i = 0; i < n/2*2; i+=2) + { + double t0 = test[i], t1 = test[i+1]; + double v0 = verify[i], v1 = verify[i+1]; + int eq1 = t0 == v0, eq2 = t1 == v1; + if (!(eq1 & eq2)) return i+1+eq1; + } + if (n % 2 != 0 && test[n-1] != verify[n-1]) + return n; + return 0; +} + +static void __attribute__((noinline)) barrier(int ncores) +{ + static volatile int sense; + static volatile int count; + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == ncores-1) + { + count = 0; + sense = threadsense; + } + else while(sense != threadsense) + ; + + __sync_synchronize(); +} + +static uint64_t lfsr(uint64_t x) +{ + uint64_t bit = (x ^ (x >> 1)) & 1; + return (x >> 1) | (bit << 62); +} + +#ifdef __riscv +#include "encoding.h" +#endif + +#define stringify_1(s) #s +#define stringify(s) stringify_1(s) +#define stats(code, iter) do { \ + unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ + code; \ + _c += read_csr(mcycle), _i += read_csr(minstret); \ + if (cid == 0) \ + printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ + stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \ + } while(0) + +#endif //__UTIL_H diff --git a/software/baremetal/hello_world/kprintf.c b/software/baremetal/hello_world/kprintf.c new file mode 100644 index 0000000..bbb47e8 --- /dev/null +++ b/software/baremetal/hello_world/kprintf.c @@ -0,0 +1,43 @@ +// See LICENSE.Sifive for license details. +#include +#include +#include +#include "kprintf.h" + +void kputc(int c) +{ +#ifndef DISABLE_KPRINTF + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); + while ((int32_t)(*tx) < 0); + *tx = (c & 0xFF); +#endif +} + +int kgetc(void) +{ +#ifndef DISABLE_KPRINTF + uint32_t ch; + volatile uint32_t *rx = ®32(uart, UART_REG_RXFIFO); + ch = *rx; + + if ((uint32_t)(ch & UART_RXEMPTY)) { + return -1; + } else { + return(ch & 0x0ff); + } +#else + return -1; +#endif +} + +void kputs(const char *s) +{ + char c; + while (*s != '\0') { + c = *s; + kputc((int) c); + s++; + } + kputc('\r'); + kputc('\n'); +} \ No newline at end of file diff --git a/software/baremetal/template/link.ld b/software/baremetal/hello_world/link.ld similarity index 100% rename from software/baremetal/template/link.ld rename to software/baremetal/hello_world/link.ld diff --git a/software/baremetal/template/syscalls.c b/software/baremetal/hello_world/syscalls.c similarity index 89% rename from software/baremetal/template/syscalls.c rename to software/baremetal/hello_world/syscalls.c index c2be98a..226fff4 100644 --- a/software/baremetal/template/syscalls.c +++ b/software/baremetal/hello_world/syscalls.c @@ -1,3 +1,14 @@ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: syscalls.c +// Program: Common Evaluation Platform (CEP) +// Description: Modified baremetal system calls for RISC-V +// Notes: Roll +// +//-------------------------------------------------------------------------------------- + + // See LICENSE for license details. #include @@ -7,8 +18,8 @@ #include #include #include -#include "util.h" #include "kprintf.h" +#include "util.h" #define SYS_write 64 @@ -17,24 +28,6 @@ extern volatile uint64_t tohost; extern volatile uint64_t fromhost; -static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2) -{ - volatile uint64_t magic_mem[8] __attribute__((aligned(64))); - magic_mem[0] = which; - magic_mem[1] = arg0; - magic_mem[2] = arg1; - magic_mem[3] = arg2; - __sync_synchronize(); - - tohost = (uintptr_t)magic_mem; - while (fromhost == 0) - ; - fromhost = 0; - - __sync_synchronize(); - return magic_mem[0]; -} - #define NUM_COUNTERS 2 static uintptr_t counters[NUM_COUNTERS]; static char* counter_names[NUM_COUNTERS]; @@ -76,9 +69,13 @@ void abort() exit(128 + SIGABRT); } -void printstr(const char* s) +// Syscall is currently disabled as it does +// not function properly in simulation +int puts(const char* s) { - syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); + kputs(s); + + return 0; } void __attribute__((weak)) thread_entry(int cid, int nc) @@ -91,7 +88,7 @@ void __attribute__((weak)) thread_entry(int cid, int nc) int __attribute__((weak)) main(int argc, char** argv) { // single-threaded programs override this function. - printstr("Implement main(), foo!\n"); + puts("Implement main(), foo!\n"); return -1; } @@ -108,9 +105,7 @@ static void init_tls() void _init(int cid, int nc) { - - // The memset within init_tls does not seem to work correctly on an arty100t build with a single medium core - //init_tls(); + init_tls(); thread_entry(cid, nc); // only single-threaded programs should ever get here. @@ -122,24 +117,22 @@ void _init(int cid, int nc) if (counters[i]) pbuf += sprintf(pbuf, "%s = %" PRIuPTR "\n", counter_names[i], counters[i]); if (pbuf != buf) - printstr(buf); + puts(buf); exit(ret); } -#undef putchar -int putchar(int ch) +#undef getchar +int getchar() { - static __thread char buf[64] __attribute__((aligned(64))); - static __thread int buflen = 0; + return kgetc(); +} - buf[buflen++] = ch; - if (ch == '\n' || buflen == sizeof(buf)) - { - syscall(SYS_write, 1, (uintptr_t)buf, buflen); - buflen = 0; - } +#undef putchar +int putchar(int ch) +{ + kputc(ch); return 0; } @@ -155,7 +148,7 @@ void printhex(uint64_t x) } str[16] = 0; - printstr(str); + puts(str); } static inline void printnum(void (*putch)(int, void**), void **putdat, @@ -210,10 +203,16 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt while (1) { while ((ch = *(unsigned char *) fmt) != '%') { - if (ch == '\0') + if (ch == '\0') { return; - fmt++; - putch(ch, putdat); + } else if (ch == '\n') { + putch('\n', putdat); + putch('\r', putdat); + fmt++; + } else { + putch(ch, putdat); + fmt++; + } } fmt++; @@ -348,14 +347,15 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt } } +// Calling of putchar from printf is currently disabled +// as syscalls do not function correctly int printf(const char* fmt, ...) { va_list ap; va_start(ap, fmt); - - vprintfmt((void*)putchar, 0, fmt, ap); - + vprintfmt((void*)kputc, 0, fmt, ap); va_end(ap); + return 0; // incorrect return value, but who cares, anyway? } @@ -397,7 +397,6 @@ void* memcpy(void* dest, const void* src, size_t len) void* memset(void* dest, int byte, size_t len) { - if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { uintptr_t word = byte & 0xFF; word |= word << 8; @@ -470,4 +469,4 @@ long atol(const char* str) } return sign ? -res : res; -} +} \ No newline at end of file diff --git a/software/baremetal/template/include/kprintf.h b/software/baremetal/template/include/kprintf.h deleted file mode 100644 index a7a9486..0000000 --- a/software/baremetal/template/include/kprintf.h +++ /dev/null @@ -1,49 +0,0 @@ -// See LICENSE.Sifive for license details. -#ifndef _SDBOOT_KPRINTF_H -#define _SDBOOT_KPRINTF_H - -#include -#include - -#define REG32(p, i) ((p)[(i) >> 2]) - -#ifndef UART_CTRL_ADDR - #ifndef UART_NUM - #define UART_NUM 0 - #endif - - #define _CONCAT3(A, B, C) A ## B ## C - #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) - #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) -#endif -static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); - -static inline void kputc(char c) -{ - volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); -#ifdef __riscv_atomic - int32_t r; - do { - __asm__ __volatile__ ( - "amoor.w %0, %2, %1\n" - : "=r" (r), "+A" (*tx) - : "r" (c)); - } while (r < 0); -#else - while ((int32_t)(*tx) < 0); - *tx = c; -#endif -} - -extern void kputs(const char *); -extern void kprintf(const char *, ...); - -#ifdef DEBUG -#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) -#define dputs(s) kputs((s)) -#else -#define dprintf(s, ...) do { } while (0) -#define dputs(s) do { } while (0) -#endif - -#endif /* _SDBOOT_KPRINTF_H */ diff --git a/software/baremetal/template/kprintf.c b/software/baremetal/template/kprintf.c deleted file mode 100644 index 3e3f218..0000000 --- a/software/baremetal/template/kprintf.c +++ /dev/null @@ -1,75 +0,0 @@ -// See LICENSE.Sifive for license details. -#include -#include -#include - -#include "kprintf.h" - -static inline void _kputs(const char *s) -{ - char c; - for (; (c = *s) != '\0'; s++) - kputc(c); -} - -void kputs(const char *s) -{ - _kputs(s); - kputc('\r'); - kputc('\n'); -} - -void kprintf(const char *fmt, ...) -{ - va_list vl; - bool is_format, is_long, is_char; - char c; - - va_start(vl, fmt); - is_format = false; - is_long = false; - is_char = false; - while ((c = *fmt++) != '\0') { - if (is_format) { - switch (c) { - case 'l': - is_long = true; - continue; - case 'h': - is_char = true; - continue; - case 'x': { - unsigned long n; - long i; - if (is_long) { - n = va_arg(vl, unsigned long); - i = (sizeof(unsigned long) << 3) - 4; - } else { - n = va_arg(vl, unsigned int); - i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; - } - for (; i >= 0; i -= 4) { - long d; - d = (n >> i) & 0xF; - kputc(d < 10 ? '0' + d : 'a' + d - 10); - } - break; - } - case 's': - _kputs(va_arg(vl, const char *)); - break; - case 'c': - kputc(va_arg(vl, int)); - break; - } - is_format = false; - is_long = false; - is_char = false; - } else if (c == '%') { - is_format = true; - } else { - kputc(c); - } - } - va_end(vl); -} diff --git a/software/coremark b/software/coremark deleted file mode 160000 index cf8b8f7..0000000 --- a/software/coremark +++ /dev/null @@ -1 +0,0 @@ -Subproject commit cf8b8f7d82e085b3ecb31865fa40fb3dd62554f2 diff --git a/software/firemarshal b/software/firemarshal deleted file mode 160000 index da82066..0000000 --- a/software/firemarshal +++ /dev/null @@ -1 +0,0 @@ -Subproject commit da820669117f7619bfb6b7a8fc21e6080c33cfc1 diff --git a/software/linux/Makefile b/software/linux/Makefile new file mode 100644 index 0000000..383f9b0 --- /dev/null +++ b/software/linux/Makefile @@ -0,0 +1,51 @@ +#************************************************************************ +# Copyright 2022 Massachusets Institute of Technology +# SPDX short identifier: BSD-2-Clause +# +# File Name: Makefile +# Program: Common Evaluation Platform (CEP) +# Description: +# Notes: +# +#************************************************************************ + +REPOROOT := $(shell git rev-parse --show-toplevel) +BASEDIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +PACKAGE = BR2_PACKAGE_$(shell echo $(MAINPROGRAM) | tr '[:lower:]' '[:upper:]') +INSTALL_DIR = ${REPOROOT}/software/firemarshal/boards/prototype/distros/br/buildroot/package/$(MAINPROGRAM) +BR_CONFIG_IN = ${REPOROOT}/software/firemarshal/boards/prototype/distros/br/buildroot/package/Config.in +BR_CONFIG = ${REPOROOT}/software/firemarshal/boards/prototype/base-workloads/br-base/buildroot-config + +# Rerform some error checking +ifeq (,${MAINPROGRAM}) +$(error Usage make MAINPROGRAM= ) +endif + +ifeq (, $(wildcard ${MAINPROGRAM})) +$(error Directory ${MAINPROGRAM} not found) +endif + +info: + @echo "Usage: make install - Installs application in firemarshal's buildroot" + +install: + @echo "Installing $(MAINPROGRAM) into firemarshal's buildroot..." +ifeq (,$(shell grep ${PACKAGE} ${BR_CONFIG})) + echo "$(PACKAGE)=y" >> $(BR_CONFIG) +endif +ifeq (,$(shell grep "package/${MAINPROGRAM}/Config.in" ${BR_CONFIG_IN})) + sed -i '/xutil_util-macros/i\ \ \ \ source "package\/${MAINPROGRAM}\/Config.in"' $(BR_CONFIG_IN) +endif + rm -rf $(INSTALL_DIR) + mkdir $(INSTALL_DIR) + -cp $(MAINPROGRAM)/Config.in $(MAINPROGRAM)/$(MAINPROGRAM).mk $(INSTALL_DIR) + +.PHONY: clean +clean: + rm -rf $(INSTALL_DIR) +ifneq (,$(shell grep ${PACKAGE} ${BR_CONFIG})) + sed -i '/$(PACKAGE)/d' $(BR_CONFIG) +endif +ifneq (,$(shell grep "package/${MAINPROGRAM}/Config.in" ${BR_CONFIG_IN})) + sed -i '/package\/${MAINPROGRAM}\/Config.in/d' $(BR_CONFIG_IN) +endif diff --git a/software/linux/gpiotest/CMakeLists.txt b/software/linux/gpiotest/CMakeLists.txt new file mode 100644 index 0000000..0c9129c --- /dev/null +++ b/software/linux/gpiotest/CMakeLists.txt @@ -0,0 +1,22 @@ +#*********************************************************************** +# Copyright 2022 Massachusets Institute of Technology +# SPDX short identifier: BSD-2-Clause +# +# File Name: CMakeLists.txt +# Program: Common Evaluation Platform (CEP) +# Description: CMake file +# Notes: +#************************************************************************ +cmake_minimum_required(VERSION 3.8) +project(gpiotest C) +set(CMAKE_C_STANDARD 11) + +add_executable(gpiotest gpiotest.c) + +target_include_directories(gpiotest PRIVATE) + +target_link_libraries(gpiotest PRIVATE "gpiod") + +set(CMAKE_INSTALL_PREFIX "/usr" CACHE PATH "Standard install prefix" FORCE) + +install(TARGETS gpiotest RUNTIME DESTINATION bin) \ No newline at end of file diff --git a/software/linux/gpiotest/Config.in b/software/linux/gpiotest/Config.in new file mode 100644 index 0000000..5b1bdc6 --- /dev/null +++ b/software/linux/gpiotest/Config.in @@ -0,0 +1,15 @@ +#*********************************************************************** +# Copyright 2022 Massachusets Institute of Technology +# SPDX short identifier: BSD-2-Clause +# +# File Name: Config.in +# Program: Common Evaluation Platform (CEP) +# Description: Buildroot configuration file for CEP linux application +# Notes: +#************************************************************************ + +config BR2_PACKAGE_GPIOTEST + bool "gpiotest" + depends on BR2_PACKAGE_LIBGPIOD + help + A linux port of the baremetal gpiotest program diff --git a/software/linux/gpiotest/gpiotest.c b/software/linux/gpiotest/gpiotest.c new file mode 100644 index 0000000..f983f6c --- /dev/null +++ b/software/linux/gpiotest/gpiotest.c @@ -0,0 +1,194 @@ +//************************************************************************ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: gpiotest.c +// Program: Common Evaluation Platform +// Description: Linux program that uses gpiod to read the switches +// and set the LEDs accordingly +// Notes: The board type will be determined by examining the +// appropriate value from the devicetree +// +//************************************************************************ + +#include +#include +#include +#include +#include +#include + +#define GPIO_WIDTH 4 +#define DEBOUNCE_CNT 10 +#define SUPPORTED_BOARDS 3 +#define MAX_LINE_LENGTH 80 + +// Defines the supported board targets +const char* board_names[SUPPORTED_BOARDS] = {"arty100t", "vc707", "vcu118"}; + +unsigned int input_line_offsets[SUPPORTED_BOARDS][GPIO_WIDTH] = + { { 8, 9, 10, 11}, + { 8, 9, 10, 11}, + { 4, 5, 6, 7}}; + +unsigned int output_line_offsets[SUPPORTED_BOARDS][GPIO_WIDTH] = + { {16, 17, 18, 19}, + {13, 14, 15, 16}, + {10, 11, 12, 13}}; + +// Compare arrays function +int compare_arrays(int left[], int right[], int num_elements) { + for (int i = 0; i < num_elements; i++) { + if (left[i] != right[i]) { + return 0; + } + } + + return 1; +} + +// A simple routine to debouce gpio reads +int get_switches_debounced(struct gpiod_line_bulk *bulk, int values_old[GPIO_WIDTH]) { + + int values_new[GPIO_WIDTH] = {0, 0, 0, 0}; + int debounce_counter = 0; + int i; + int j; + int ret; + + while (debounce_counter < DEBOUNCE_CNT) { + + ret = gpiod_line_get_value_bulk(bulk, values_new); + if (ret) + return ret; + + if (compare_arrays(values_new, values_old, GPIO_WIDTH)) + debounce_counter++; + else + debounce_counter = 0; + + for (i = 0; i < GPIO_WIDTH; i++) { + values_old[i] = values_new[i]; + } + + } // end while + + return 0; + +} // get_switch + +int main(int argc, char **argv) +{ + + char *chipname = "gpiochip0"; + struct gpiod_chip *chip; + struct gpiod_line_bulk input_lines; + struct gpiod_line_request_config input_config[GPIO_WIDTH]; + struct gpiod_line_bulk output_lines; + struct gpiod_line_request_config output_config[GPIO_WIDTH]; + int values_old[GPIO_WIDTH] = {2, 2, 2, 2}; // guarentees at least one printout + int values_new[GPIO_WIDTH] = {0, 0, 0, 0}; + int i; + int j; + int board_match = -1; + int ret; + char soc_compatible[MAX_LINE_LENGTH]; + + // Retrieve the board variant we are running on... + FILE *compatible_file = fopen("/sys/firmware/devicetree/base/soc/compatible", "r"); + fgets(soc_compatible, MAX_LINE_LENGTH, compatible_file); + fclose(compatible_file); + + // Look for a board type match + for (i = 0; i < SUPPORTED_BOARDS; i++) { + if (strstr(soc_compatible, board_names[i])) { + board_match = i; + break; + } + } + + // No match was found + if (board_match == -1) { + perror("Unsupported board\n"); + goto end; + } + + printf("\n"); + printf("\n"); + printf("--------------------------\n"); + printf(" Linux RISC-V GPIO Test \n"); + printf("--------------------------\n"); + printf(" %s detected\n", board_names[board_match]); + printf("\n"); + + // Enable access to the GPIO Device + chip = gpiod_chip_open_by_name(chipname); + if (!chip) { + perror("Open chip failed\n"); + goto end; + } + + // Get the gpio lines + ret = gpiod_chip_get_lines(chip, input_line_offsets[board_match] , GPIO_WIDTH, &input_lines); + ret |= gpiod_chip_get_lines(chip, output_line_offsets[board_match] , GPIO_WIDTH, &output_lines); + if (ret) { + perror("Get line failed\n"); + goto release_lines; + } + + // Setup the configs + for (i = 0; i < GPIO_WIDTH; i++) { + input_config[i].consumer = "gpiotest"; + input_config[i].request_type = GPIOD_LINE_REQUEST_DIRECTION_INPUT; + input_config[i].flags = 0; + output_config[i].consumer = "gpiotest"; + output_config[i].request_type = GPIOD_LINE_REQUEST_DIRECTION_OUTPUT; + output_config[i].flags = 0; + } + + // Set the gpio directions + ret = gpiod_line_request_bulk(&input_lines, input_config, values_old); + ret |= gpiod_line_request_bulk(&output_lines, output_config, values_old); + if (ret) { + perror("gpiod_line_request_bulk\n"); + goto release_lines; + } + + // Simple loop to read the switches and write the LEDs + do { + + ret = get_switches_debounced(&input_lines, values_new); + if (ret) { + perror("Get line value failed\n"); + goto release_lines; + } + + // Print the switches value if there is a change in state + for (i = 0; i < GPIO_WIDTH; i++) { + if (!compare_arrays(values_new, values_old, GPIO_WIDTH)) { + printf("switches = "); + for (j = 0; j < GPIO_WIDTH; j++) { + printf("%0x", values_new[GPIO_WIDTH - j - 1]); + values_old[j] = values_new[j]; + } + printf("\n"); + break; + } + } + + // LEDs are always set to new, regardless if there has been a change or not + ret = gpiod_line_set_value_bulk(&output_lines, values_new); + if (ret) { + perror("Set line value failed\n"); + goto release_lines; + } + } while (1); + +release_lines: + gpiod_line_release_bulk(&input_lines); + gpiod_line_release_bulk(&output_lines); +close_chip: + gpiod_chip_close(chip); +end: + return 0; +} \ No newline at end of file diff --git a/software/linux/gpiotest/gpiotest.mk b/software/linux/gpiotest/gpiotest.mk new file mode 100644 index 0000000..6863dc9 --- /dev/null +++ b/software/linux/gpiotest/gpiotest.mk @@ -0,0 +1,19 @@ +#*********************************************************************** +# Copyright 2022 Massachusets Institute of Technology +# SPDX short identifier: BSD-2-Clause +# +# File Name: gpiotest.mk +# Program: Common Evaluation Platform (CEP) +# Description: Buildroot makefile +# Notes: +#************************************************************************ + +GPIOTEST_VERSION = 1.0.0 +GPIOTEST_LICENSE = BSD-2-Clause +GPIOTEST_DEPENDENCIES = libgpiod +GPIOTEST_SITE = $(TOPDIR)/../../../../../../linux/gpiotest +GPIOTEST_SITE_METHOD = local +GPIOTEST_INSTALL_STAGING = NO +GPIOTEST_INSTALL_TARGET = YES + +$(eval $(cmake-package)) diff --git a/software/linux/helloworld/CMakeLists.txt b/software/linux/helloworld/CMakeLists.txt new file mode 100644 index 0000000..dd6ae0b --- /dev/null +++ b/software/linux/helloworld/CMakeLists.txt @@ -0,0 +1,22 @@ +#*********************************************************************** +# Copyright 2022 Massachusets Institute of Technology +# SPDX short identifier: BSD-2-Clause +# +# File Name: CMakeLists.txt +# Program: Common Evaluation Platform (CEP) +# Description: CMake file +# Notes: +#************************************************************************ +cmake_minimum_required(VERSION 3.8) +project(helloworld C) +set(CMAKE_C_STANDARD 11) + +add_executable(helloworld helloworld.c) + +target_include_directories(helloworld PRIVATE) + +target_link_libraries(helloworld PRIVATE) + +set(CMAKE_INSTALL_PREFIX "/usr" CACHE PATH "Standard install prefix" FORCE) + +install(TARGETS helloworld RUNTIME DESTINATION bin) \ No newline at end of file diff --git a/software/linux/helloworld/Config.in b/software/linux/helloworld/Config.in new file mode 100644 index 0000000..9c19e34 --- /dev/null +++ b/software/linux/helloworld/Config.in @@ -0,0 +1,14 @@ +#*********************************************************************** +# Copyright 2022 Massachusets Institute of Technology +# SPDX short identifier: BSD-2-Clause +# +# File Name: Config.in +# Program: Common Evaluation Platform (CEP) +# Description: Buildroot configuration file for CEP linux application +# Notes: +#************************************************************************ + +config BR2_PACKAGE_HELLOWORLD + bool "helloworld" + help + A simple hello world program diff --git a/software/linux/helloworld/helloworld.c b/software/linux/helloworld/helloworld.c new file mode 100644 index 0000000..0edb116 --- /dev/null +++ b/software/linux/helloworld/helloworld.c @@ -0,0 +1,26 @@ +//************************************************************************ +// Copyright 2022 Massachusets Institute of Technology +// SPDX short identifier: BSD-2-Clause +// +// File Name: hello_world.c +// Program: Common Evaluation Platform +// Description: A basic linux hello world program to run on the +// RISC-V +// Notes: +// +//************************************************************************ + +#include + +int main() { + + puts(""); + puts(""); + puts("--------------------------"); + puts(" Linux RISC-V Hello World "); + puts("--------------------------"); + puts(""); + puts(""); + + return 0; +} diff --git a/software/linux/helloworld/helloworld.mk b/software/linux/helloworld/helloworld.mk new file mode 100644 index 0000000..9c82599 --- /dev/null +++ b/software/linux/helloworld/helloworld.mk @@ -0,0 +1,19 @@ +#************************************************************************ +# Copyright 2022 Massachusets Institute of Technology +# SPDX short identifier: BSD-2-Clause +# +# File Name: helloworld.mk +# Program: Common Evaluation Platform (CEP) +# Description: Buildroot makefile +# Notes: +#************************************************************************ + +HELLOWORLD_VERSION = 1.0.0 +HELLOWORLD_LICENSE = BSD-2-Clause +HELLOWORLD_DEPENDENCIES = +HELLOWORLD_SITE = $(TOPDIR)/../../../../../../linux/helloworld +HELLOWORLD_SITE_METHOD = local +HELLOWORLD_INSTALL_STAGING = NO +HELLOWORLD_INSTALL_TARGET = YES + +$(eval $(cmake-package)) diff --git a/software/nvdla-workload b/software/nvdla-workload deleted file mode 160000 index 30290c3..0000000 --- a/software/nvdla-workload +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 30290c3ed8014577fa2ad234fa1b731a082299fb diff --git a/software/spec2017 b/software/spec2017 deleted file mode 160000 index 83e3311..0000000 --- a/software/spec2017 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 83e33110472c47aaa762257ed7c053ff1278834c diff --git a/toolchains/esp-tools/riscv-gnu-toolchain b/toolchains/esp-tools/riscv-gnu-toolchain deleted file mode 160000 index 9f53229..0000000 --- a/toolchains/esp-tools/riscv-gnu-toolchain +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 9f532293985d08b0c176d96c7b650e5f433780e1 diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim deleted file mode 160000 index ce42f1b..0000000 --- a/toolchains/esp-tools/riscv-isa-sim +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ce42f1b55a3fa5a3a522439b5370be2256f68862 diff --git a/toolchains/esp-tools/riscv-pk b/toolchains/esp-tools/riscv-pk deleted file mode 160000 index e8e6b3a..0000000 --- a/toolchains/esp-tools/riscv-pk +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e8e6b3aaee44d43b48164fbd377864c3a682dbd3 diff --git a/toolchains/esp-tools/riscv-tests b/toolchains/esp-tools/riscv-tests deleted file mode 160000 index 7c3dfd3..0000000 --- a/toolchains/esp-tools/riscv-tests +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7c3dfd3205fa90104db06346e797a8eeea149207 diff --git a/toolchains/libgloss b/toolchains/libgloss deleted file mode 160000 index 04b2497..0000000 --- a/toolchains/libgloss +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 04b249764b1bc0b784b9f7ff422084f4b53a07ef diff --git a/toolchains/qemu b/toolchains/qemu deleted file mode 160000 index fdd76fe..0000000 --- a/toolchains/qemu +++ /dev/null @@ -1 +0,0 @@ -Subproject commit fdd76fecdde1ad444ff4deb7f1c4f7e4a1ef97d6 diff --git a/toolchains/riscv-tools/riscv-gnu-toolchain b/toolchains/riscv-tools/riscv-gnu-toolchain deleted file mode 160000 index 2855d82..0000000 --- a/toolchains/riscv-tools/riscv-gnu-toolchain +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 2855d823a6e93d50af604264b02ced951e80de67 diff --git a/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt b/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt deleted file mode 160000 index 918be23..0000000 --- a/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 918be2371723257ed6590c77d5996ed040261c85 diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim deleted file mode 160000 index ce42f1b..0000000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ce42f1b55a3fa5a3a522439b5370be2256f68862 diff --git a/toolchains/riscv-tools/riscv-openocd b/toolchains/riscv-tools/riscv-openocd deleted file mode 160000 index cbb1558..0000000 --- a/toolchains/riscv-tools/riscv-openocd +++ /dev/null @@ -1 +0,0 @@ -Subproject commit cbb15587dc782ac8ade7ae252e7b760cfba4a178 diff --git a/toolchains/riscv-tools/riscv-pk b/toolchains/riscv-tools/riscv-pk deleted file mode 160000 index e8e6b3a..0000000 --- a/toolchains/riscv-tools/riscv-pk +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e8e6b3aaee44d43b48164fbd377864c3a682dbd3 diff --git a/toolchains/riscv-tools/riscv-tests b/toolchains/riscv-tools/riscv-tests deleted file mode 160000 index 1ce128f..0000000 --- a/toolchains/riscv-tools/riscv-tests +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 1ce128fa78c24bb0ed399c647e7139322b5353a7 diff --git a/tools/DRAMSim2 b/tools/DRAMSim2 deleted file mode 160000 index 2ec7965..0000000 --- a/tools/DRAMSim2 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 2ec7965b2ee051aaff03d5db21c6709aea4dd24e diff --git a/tools/api-config-chipsalliance b/tools/api-config-chipsalliance deleted file mode 160000 index fd8df11..0000000 --- a/tools/api-config-chipsalliance +++ /dev/null @@ -1 +0,0 @@ -Subproject commit fd8df1105a92065425cd353b6855777e35bd79b4 diff --git a/tools/axe b/tools/axe deleted file mode 160000 index 4a7cf86..0000000 --- a/tools/axe +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 4a7cf86960425fbf0b6224865b745ff511dc5742 diff --git a/tools/barstools b/tools/barstools deleted file mode 160000 index 064c8be..0000000 --- a/tools/barstools +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 064c8be7bb3d86eccfd603c614f74de6de1c3f4a diff --git a/tools/chisel-testers b/tools/chisel-testers deleted file mode 160000 index ce4e027..0000000 --- a/tools/chisel-testers +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ce4e027e5f3d871df59236b8471ea3e5be40130e diff --git a/tools/dromajo/dromajo-src b/tools/dromajo/dromajo-src deleted file mode 160000 index 09fbef4..0000000 --- a/tools/dromajo/dromajo-src +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 09fbef4565429f641a7eb93f190ad0e45e11d7f8 diff --git a/tools/dsptools b/tools/dsptools deleted file mode 160000 index a1809fb..0000000 --- a/tools/dsptools +++ /dev/null @@ -1 +0,0 @@ -Subproject commit a1809fbae9e49de7213116bbec79252645292e39 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils deleted file mode 160000 index 0ffb46a..0000000 --- a/tools/rocket-dsp-utils +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 0ffb46ad12d0335a1d44bc283bae596abfd79606 diff --git a/tools/torture b/tools/torture deleted file mode 160000 index b2b66a6..0000000 --- a/tools/torture +++ /dev/null @@ -1 +0,0 @@ -Subproject commit b2b66a66d51b360e0ae95017774d03377c78c574 diff --git a/vlsi/hammer b/vlsi/hammer deleted file mode 160000 index 0ddd5dd..0000000 --- a/vlsi/hammer +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 0ddd5dd7819851e88d2a53628e868c7ddfc43453 diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins deleted file mode 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