diff --git a/flight/Modules/Loadable/loadable.c b/flight/Modules/Loadable/loadable.c
index b3221a262b..6ba505bfc6 100644
--- a/flight/Modules/Loadable/loadable.c
+++ b/flight/Modules/Loadable/loadable.c
@@ -297,9 +297,9 @@ void MemManageHandler_C(uint32_t *exception_stack) {
exception_stack[EXCEPTION_STACK_PC_OFFSET] = pc;
}
-void MemManageVector(void) __attribute__((naked));
+void MemManage_Handler(void) __attribute__((naked));
-void MemManageVector(void)
+void MemManage_Handler(void)
{
/* Stores the exception stack pointer into an argument, and invokes
* the real handler (without linkage-- the BX LR at completion of
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/documentation.html b/flight/PiOS/Common/Libraries/ChibiOS/documentation.html
index 6cc46acc0e..dc4f07166d 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/documentation.html
+++ b/flight/PiOS/Common/Libraries/ChibiOS/documentation.html
@@ -1,7 +1,7 @@
-
+
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/exception.txt b/flight/PiOS/Common/Libraries/ChibiOS/exception.txt
deleted file mode 100644
index d74e8aeadc..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/exception.txt
+++ /dev/null
@@ -1,48 +0,0 @@
- GPL Exception Text
-
- In addition, as a special exception, the copyright holder of ChibiOS/RT,
-gives You the additional right to link the unmodified code of this Program with
-code not covered under the GNU General Public License ("Non-GPL Code") and to
-distribute linked combinations including the two, subject to the limitations
-in this paragraph.
-
- 1. Non-GPL Code permitted under this exception must only link to the
- unmodified code of this Program through those well defined interfaces
- identified as "Approved Interfaces".
- 2. Every copy of the combined work is accompanied by a written statement
- that details to the recipient the version of ChibiOS/RT used and an
- offer by yourself to provide the ChibiOS/RT source code should the
- recipient request it.
- 3. The combined work is not itself an RTOS, scheduler, kernel or related
- product.
- 4. The combined work is not itself a binary library intended for linking
- into other software applications.
-
- The Approved Interfaces
-
- 1. The files of Non-GPL Code may include the unmodified ChibiOS/RT
- distribution header files contained under:
- ./os/kernel/include
- ./os/ports
- ./os/hal/include
- without causing the resulting work to be covered by the GNU General
- Public License.
- 2. The files of Non-GPL Code may link to the unmodified ChibiOS/RT
- distribution files contained under:
- ./os/kernel/src
- ./os/ports
- ./os/hal/src
- without causing the resulting work to be covered by the GNU General
- Public License.
- 3. The files of Non-GPL Code may link to, or include, the modified or
- unmodified ChibiOS/RT distribution files contained under:
- ./os/kernel/templates
- without causing the resulting work to be covered by the GNU General
- Public License.
-
- Only the copyright holder of ChibiOS/RT may make changes or additions to the
-list of Approved Interfaces.
-
- You must obey the GNU General Public License in all respects for all of the
-Program code and other code used in conjunction with the Program except the
-Non-GPL Code covered by this exception.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chbsem.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chbsem.h
new file mode 100644
index 0000000000..ff5c27099a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chbsem.h
@@ -0,0 +1,311 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chbsem.h
+ * @brief Binary semaphores structures and macros.
+ *
+ * @addtogroup binary_semaphores
+ * @details Binary semaphores related APIs and services.
+ * Operation mode
+ * Binary semaphores are implemented as a set of inline functions
+ * that use the existing counting semaphores primitives. The
+ * difference between counting and binary semaphores is that the
+ * counter of binary semaphores is not allowed to grow above the
+ * value 1. Repeated signal operation are ignored. A binary
+ * semaphore can thus have only two defined states:
+ * - Taken, when its counter has a value of zero or lower
+ * than zero. A negative number represent the number of threads
+ * queued on the binary semaphore.
+ * - Not taken, when its counter has a value of one.
+ * .
+ * Binary semaphores are different from mutexes because there is no
+ * concept of ownership, a binary semaphore can be taken by a
+ * thread and signaled by another thread or an interrupt handler,
+ * mutexes can only be taken and released by the same thread. Another
+ * difference is that binary semaphores, unlike mutexes, do not
+ * implement the priority inheritance protocol.
+ * In order to use the binary semaphores APIs the
+ * @p CH_CFG_USE_SEMAPHORES option must be enabled in @p chconf.h.
+ * @{
+ */
+
+#ifndef CHBSEM_H
+#define CHBSEM_H
+
+#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @extends semaphore_t
+ *
+ * @brief Binary semaphore type.
+ */
+typedef struct {
+ semaphore_t sem;
+} binary_semaphore_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Data part of a static semaphore initializer.
+ * @details This macro should be used when statically initializing a semaphore
+ * that is part of a bigger structure.
+ *
+ * @param[in] name the name of the semaphore variable
+ * @param[in] taken the semaphore initial state
+ */
+#define _BSEMAPHORE_DATA(name, taken) \
+ {_SEMAPHORE_DATA(name.sem, ((taken) ? 0 : 1))}
+
+/**
+ * @brief Static semaphore initializer.
+ * @details Statically initialized semaphores require no explicit
+ * initialization using @p chBSemInit().
+ *
+ * @param[in] name the name of the semaphore variable
+ * @param[in] taken the semaphore initial state
+ */
+#define BSEMAPHORE_DECL(name, taken) \
+ binary_semaphore_t name = _BSEMAPHORE_DATA(name, taken)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes a binary semaphore.
+ *
+ * @param[out] bsp pointer to a @p binary_semaphore_t structure
+ * @param[in] taken initial state of the binary semaphore:
+ * - @a false, the initial state is not taken.
+ * - @a true, the initial state is taken.
+ * .
+ *
+ * @init
+ */
+static inline void chBSemObjectInit(binary_semaphore_t *bsp, bool taken) {
+
+ chSemObjectInit(&bsp->sem, taken ? (cnt_t)0 : (cnt_t)1);
+}
+
+/**
+ * @brief Wait operation on the binary semaphore.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ * @return A message specifying how the invoking thread has been
+ * released from the semaphore.
+ * @retval MSG_OK if the binary semaphore has been successfully taken.
+ * @retval MSG_RESET if the binary semaphore has been reset using
+ * @p bsemReset().
+ *
+ * @api
+ */
+static inline msg_t chBSemWait(binary_semaphore_t *bsp) {
+
+ return chSemWait(&bsp->sem);
+}
+
+/**
+ * @brief Wait operation on the binary semaphore.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ * @return A message specifying how the invoking thread has been
+ * released from the semaphore.
+ * @retval MSG_OK if the binary semaphore has been successfully taken.
+ * @retval MSG_RESET if the binary semaphore has been reset using
+ * @p bsemReset().
+ *
+ * @sclass
+ */
+static inline msg_t chBSemWaitS(binary_semaphore_t *bsp) {
+
+ chDbgCheckClassS();
+
+ return chSemWaitS(&bsp->sem);
+}
+
+/**
+ * @brief Wait operation on the binary semaphore.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ * @param[in] time the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return A message specifying how the invoking thread has been
+ * released from the semaphore.
+ * @retval MSG_OK if the binary semaphore has been successfully taken.
+ * @retval MSG_RESET if the binary semaphore has been reset using
+ * @p bsemReset().
+ * @retval MSG_TIMEOUT if the binary semaphore has not been signaled or reset
+ * within the specified timeout.
+ *
+ * @sclass
+ */
+static inline msg_t chBSemWaitTimeoutS(binary_semaphore_t *bsp,
+ systime_t time) {
+
+ chDbgCheckClassS();
+
+ return chSemWaitTimeoutS(&bsp->sem, time);
+}
+
+/**
+ * @brief Wait operation on the binary semaphore.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ * @param[in] time the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return A message specifying how the invoking thread has been
+ * released from the semaphore.
+ * @retval MSG_OK if the binary semaphore has been successfully taken.
+ * @retval MSG_RESET if the binary semaphore has been reset using
+ * @p bsemReset().
+ * @retval MSG_TIMEOUT if the binary semaphore has not been signaled or reset
+ * within the specified timeout.
+ *
+ * @api
+ */
+static inline msg_t chBSemWaitTimeout(binary_semaphore_t *bsp,
+ systime_t time) {
+
+ return chSemWaitTimeout(&bsp->sem, time);
+}
+
+/**
+ * @brief Reset operation on the binary semaphore.
+ * @note The released threads can recognize they were waked up by a reset
+ * rather than a signal because the @p bsemWait() will return
+ * @p MSG_RESET instead of @p MSG_OK.
+ * @note This function does not reschedule.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ * @param[in] taken new state of the binary semaphore
+ * - @a false, the new state is not taken.
+ * - @a true, the new state is taken.
+ * .
+ *
+ * @iclass
+ */
+static inline void chBSemResetI(binary_semaphore_t *bsp, bool taken) {
+
+ chDbgCheckClassI();
+
+ chSemResetI(&bsp->sem, taken ? (cnt_t)0 : (cnt_t)1);
+}
+
+/**
+ * @brief Reset operation on the binary semaphore.
+ * @note The released threads can recognize they were waked up by a reset
+ * rather than a signal because the @p bsemWait() will return
+ * @p MSG_RESET instead of @p MSG_OK.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ * @param[in] taken new state of the binary semaphore
+ * - @a false, the new state is not taken.
+ * - @a true, the new state is taken.
+ * .
+ *
+ * @api
+ */
+static inline void chBSemReset(binary_semaphore_t *bsp, bool taken) {
+
+ chSemReset(&bsp->sem, taken ? (cnt_t)0 : (cnt_t)1);
+}
+
+/**
+ * @brief Performs a signal operation on a binary semaphore.
+ * @note This function does not reschedule.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ *
+ * @iclass
+ */
+static inline void chBSemSignalI(binary_semaphore_t *bsp) {
+
+ chDbgCheckClassI();
+
+ if (bsp->sem.cnt < (cnt_t)1) {
+ chSemSignalI(&bsp->sem);
+ }
+}
+
+/**
+ * @brief Performs a signal operation on a binary semaphore.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ *
+ * @api
+ */
+static inline void chBSemSignal(binary_semaphore_t *bsp) {
+
+ chSysLock();
+ chBSemSignalI(bsp);
+ chSchRescheduleS();
+ chSysUnlock();
+}
+
+/**
+ * @brief Returns the binary semaphore current state.
+ *
+ * @param[in] bsp pointer to a @p binary_semaphore_t structure
+ * @return The binary semaphore current state.
+ * @retval false if the binary semaphore is not taken.
+ * @retval true if the binary semaphore is taken.
+ *
+ * @iclass
+ */
+static inline bool chBSemGetStateI(binary_semaphore_t *bsp) {
+
+ chDbgCheckClassI();
+
+ return (bsp->sem.cnt > (cnt_t)0) ? false : true;
+}
+
+#endif /* CH_CFG_USE_SEMAPHORES == TRUE */
+
+#endif /* CHBSEM_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chheap.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chheap.h
new file mode 100644
index 0000000000..7f4a69541d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chheap.h
@@ -0,0 +1,179 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chheap.h
+ * @brief Heaps macros and structures.
+ *
+ * @addtogroup heaps
+ * @{
+ */
+
+#ifndef CHHEAP_H
+#define CHHEAP_H
+
+#if (CH_CFG_USE_HEAP == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Minimum alignment used for heap.
+ * @note Cannot use the sizeof operator in this macro.
+ */
+#if (SIZEOF_PTR == 4) || defined(__DOXYGEN__)
+#define CH_HEAP_ALIGNMENT 8U
+#elif (SIZEOF_PTR == 2)
+#define CH_HEAP_ALIGNMENT 4U
+#else
+#error "unsupported pointer size"
+#endif
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if CH_CFG_USE_MEMCORE == FALSE
+#error "CH_CFG_USE_HEAP requires CH_CFG_USE_MEMCORE"
+#endif
+
+#if (CH_CFG_USE_MUTEXES == FALSE) && (CH_CFG_USE_SEMAPHORES == FALSE)
+#error "CH_CFG_USE_HEAP requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a memory heap.
+ */
+typedef struct memory_heap memory_heap_t;
+
+/**
+ * @brief Type of a memory heap header.
+ */
+typedef union heap_header heap_header_t;
+
+/**
+ * @brief Memory heap block header.
+ */
+union heap_header {
+ stkalign_t align;
+ struct {
+ heap_header_t *next; /**< @brief Next block in free list. */
+ size_t pages; /**< @brief Size of the area in pages. */
+ } free;
+ struct {
+ memory_heap_t *heap; /**< @brief Block owner heap. */
+ size_t size; /**< @brief Size of the area in bytes. */
+ } used;
+};
+
+/**
+ * @brief Structure describing a memory heap.
+ */
+struct memory_heap {
+ memgetfunc2_t provider; /**< @brief Memory blocks provider for
+ this heap. */
+ heap_header_t header; /**< @brief Free blocks list header. */
+#if CH_CFG_USE_MUTEXES == TRUE
+ mutex_t mtx; /**< @brief Heap access mutex. */
+#else
+ semaphore_t sem; /**< @brief Heap access semaphore. */
+#endif
+};
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Allocation of an aligned static heap buffer.
+ */
+#define CH_HEAP_AREA(name, size) \
+ ALIGNED_VAR(CH_HEAP_ALIGNMENT) \
+ uint8_t name[MEM_ALIGN_NEXT((size), CH_HEAP_ALIGNMENT)]
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _heap_init(void);
+ void chHeapObjectInit(memory_heap_t *heapp, void *buf, size_t size);
+ void *chHeapAllocAligned(memory_heap_t *heapp, size_t size, unsigned align);
+ void chHeapFree(void *p);
+ size_t chHeapStatus(memory_heap_t *heapp, size_t *totalp, size_t *largestp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Allocates a block of memory from the heap by using the first-fit
+ * algorithm.
+ * @details The allocated block is guaranteed to be properly aligned for a
+ * pointer data type.
+ *
+ * @param[in] heapp pointer to a heap descriptor or @p NULL in order to
+ * access the default heap.
+ * @param[in] size the size of the block to be allocated. Note that the
+ * allocated block may be a bit bigger than the requested
+ * size for alignment and fragmentation reasons.
+ * @return A pointer to the allocated block.
+ * @retval NULL if the block cannot be allocated.
+ *
+ * @api
+ */
+static inline void *chHeapAlloc(memory_heap_t *heapp, size_t size) {
+
+ return chHeapAllocAligned(heapp, size, CH_HEAP_ALIGNMENT);
+}
+
+/**
+ * @brief Returns the size of an allocated block.
+ * @note The returned value is the requested size, the real size is the
+ * same value aligned to the next @p CH_HEAP_ALIGNMENT multiple.
+ *
+ * @param[in] p pointer to the memory block
+ * @return Size of the block.
+ *
+ * @api
+ */
+static inline size_t chHeapGetSize(const void *p) {
+
+ return ((heap_header_t *)p)->used.size;
+}
+
+#endif /* CH_CFG_USE_HEAP == TRUE */
+
+#endif /* CHHEAP_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmboxes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmboxes.h
new file mode 100644
index 0000000000..b8e6a1de85
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmboxes.h
@@ -0,0 +1,210 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmboxes.h
+ * @brief Mailboxes macros and structures.
+ *
+ * @addtogroup mailboxes
+ * @{
+ */
+
+#ifndef CHMBOXES_H
+#define CHMBOXES_H
+
+#if (CH_CFG_USE_MAILBOXES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Structure representing a mailbox object.
+ */
+typedef struct {
+ msg_t *buffer; /**< @brief Pointer to the mailbox
+ buffer. */
+ msg_t *top; /**< @brief Pointer to the location
+ after the buffer. */
+ msg_t *wrptr; /**< @brief Write pointer. */
+ msg_t *rdptr; /**< @brief Read pointer. */
+ cnt_t cnt; /**< @brief Messages in queue. */
+ bool reset; /**< @brief True in reset state. */
+ threads_queue_t qw; /**< @brief Queued writers. */
+ threads_queue_t qr; /**< @brief Queued readers. */
+} mailbox_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Data part of a static mailbox initializer.
+ * @details This macro should be used when statically initializing a
+ * mailbox that is part of a bigger structure.
+ *
+ * @param[in] name the name of the mailbox variable
+ * @param[in] buffer pointer to the mailbox buffer array of @p msg_t
+ * @param[in] size number of @p msg_t elements in the buffer array
+ */
+#define _MAILBOX_DATA(name, buffer, size) { \
+ (msg_t *)(buffer), \
+ (msg_t *)(buffer) + size, \
+ (msg_t *)(buffer), \
+ (msg_t *)(buffer), \
+ (cnt_t)0, \
+ false, \
+ _THREADS_QUEUE_DATA(name.qw), \
+ _THREADS_QUEUE_DATA(name.qr), \
+}
+
+/**
+ * @brief Static mailbox initializer.
+ * @details Statically initialized mailboxes require no explicit
+ * initialization using @p chMBObjectInit().
+ *
+ * @param[in] name the name of the mailbox variable
+ * @param[in] buffer pointer to the mailbox buffer array of @p msg_t
+ * @param[in] size number of @p msg_t elements in the buffer array
+ */
+#define MAILBOX_DECL(name, buffer, size) \
+ mailbox_t name = _MAILBOX_DATA(name, buffer, size)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chMBObjectInit(mailbox_t *mbp, msg_t *buf, cnt_t n);
+ void chMBReset(mailbox_t *mbp);
+ void chMBResetI(mailbox_t *mbp);
+ msg_t chMBPost(mailbox_t *mbp, msg_t msg, systime_t timeout);
+ msg_t chMBPostS(mailbox_t *mbp, msg_t msg, systime_t timeout);
+ msg_t chMBPostI(mailbox_t *mbp, msg_t msg);
+ msg_t chMBPostAhead(mailbox_t *mbp, msg_t msg, systime_t timeout);
+ msg_t chMBPostAheadS(mailbox_t *mbp, msg_t msg, systime_t timeout);
+ msg_t chMBPostAheadI(mailbox_t *mbp, msg_t msg);
+ msg_t chMBFetch(mailbox_t *mbp, msg_t *msgp, systime_t timeout);
+ msg_t chMBFetchS(mailbox_t *mbp, msg_t *msgp, systime_t timeout);
+ msg_t chMBFetchI(mailbox_t *mbp, msg_t *msgp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the mailbox buffer size as number of messages.
+ *
+ * @param[in] mbp the pointer to an initialized mailbox_t object
+ * @return The size of the mailbox.
+ *
+ * @iclass
+ */
+static inline cnt_t chMBGetSizeI(const mailbox_t *mbp) {
+
+ /*lint -save -e9033 [10.8] Perfectly safe pointers
+ arithmetic.*/
+ return (cnt_t)(mbp->top - mbp->buffer);
+ /*lint -restore*/
+}
+
+/**
+ * @brief Returns the number of used message slots into a mailbox.
+ *
+ * @param[in] mbp the pointer to an initialized mailbox_t object
+ * @return The number of queued messages.
+ * @retval QUEUE_RESET if the queue is in reset state.
+ *
+ * @iclass
+ */
+static inline cnt_t chMBGetUsedCountI(const mailbox_t *mbp) {
+
+ chDbgCheckClassI();
+
+ return mbp->cnt;
+}
+
+/**
+ * @brief Returns the number of free message slots into a mailbox.
+ *
+ * @param[in] mbp the pointer to an initialized mailbox_t object
+ * @return The number of empty message slots.
+ *
+ * @iclass
+ */
+static inline cnt_t chMBGetFreeCountI(const mailbox_t *mbp) {
+
+ chDbgCheckClassI();
+
+ return chMBGetSizeI(mbp) - chMBGetUsedCountI(mbp);
+}
+
+/**
+ * @brief Returns the next message in the queue without removing it.
+ * @pre A message must be waiting in the queue for this function to work
+ * or it would return garbage. The correct way to use this macro is
+ * to use @p chMBGetFullCountI() and then use this macro, all within
+ * a lock state.
+ *
+ * @param[in] mbp the pointer to an initialized mailbox_t object
+ * @return The next message in queue.
+ *
+ * @iclass
+ */
+static inline msg_t chMBPeekI(const mailbox_t *mbp) {
+
+ chDbgCheckClassI();
+
+ return *mbp->rdptr;
+}
+
+/**
+ * @brief Terminates the reset state.
+ *
+ * @param[in] mbp the pointer to an initialized mailbox_t object
+ *
+ * @xclass
+ */
+static inline void chMBResumeX(mailbox_t *mbp) {
+
+ mbp->reset = false;
+}
+
+#endif /* CH_CFG_USE_MAILBOXES == TRUE */
+
+#endif /* CHMBOXES_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmemcore.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmemcore.h
new file mode 100644
index 0000000000..7a24a80c03
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmemcore.h
@@ -0,0 +1,198 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmemcore.h
+ * @brief Core memory manager macros and structures.
+ *
+ * @addtogroup memcore
+ * @{
+ */
+
+#ifndef CHMEMCORE_H
+#define CHMEMCORE_H
+
+#if (CH_CFG_USE_MEMCORE == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#if !defined(CH_CFG_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_CFG_MEMCORE_SIZE 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if CH_CFG_MEMCORE_SIZE < 0
+#error "invalid CH_CFG_MEMCORE_SIZE value specified"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Memory get function.
+ */
+typedef void *(*memgetfunc_t)(size_t size, unsigned align);
+
+/**
+ * @brief Enhanced memory get function.
+ */
+typedef void *(*memgetfunc2_t)(size_t size, unsigned align, size_t offset);
+
+/**
+ * @brief Type of memory core object.
+ */
+typedef struct {
+ /**
+ * @brief Next free address.
+ */
+ uint8_t *nextmem;
+ /**
+ * @brief Final address.
+ */
+ uint8_t *endmem;
+} memcore_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern memcore_t ch_memcore;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _core_init(void);
+ void *chCoreAllocAlignedWithOffsetI(size_t size,
+ unsigned align,
+ size_t offset);
+ void *chCoreAllocAlignedWithOffset(size_t size,
+ unsigned align,
+ size_t offset);
+ size_t chCoreGetStatusX(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Allocates a memory block.
+ * @details The allocated block is guaranteed to be properly aligned to the
+ * specified alignment.
+ *
+ * @param[in] size the size of the block to be allocated.
+ * @param[in] align desired memory alignment
+ * @return A pointer to the allocated memory block.
+ * @retval NULL allocation failed, core memory exhausted.
+ *
+ * @iclass
+ */
+static inline void *chCoreAllocAlignedI(size_t size, unsigned align) {
+
+ return chCoreAllocAlignedWithOffsetI(size, align, 0U);
+}
+
+/**
+ * @brief Allocates a memory block.
+ * @details The allocated block is guaranteed to be properly aligned to the
+ * specified alignment.
+ *
+ * @param[in] size the size of the block to be allocated
+ * @param[in] align desired memory alignment
+ * @return A pointer to the allocated memory block.
+ * @retval NULL allocation failed, core memory exhausted.
+ *
+ * @api
+ */
+static inline void *chCoreAllocAligned(size_t size, unsigned align) {
+ void *p;
+
+ chSysLock();
+ p = chCoreAllocAlignedWithOffsetI(size, align, 0U);
+ chSysUnlock();
+
+ return p;
+}
+
+/**
+ * @brief Allocates a memory block.
+ * @details The allocated block is guaranteed to be properly aligned for a
+ * pointer data type.
+ *
+ * @param[in] size the size of the block to be allocated.
+ * @return A pointer to the allocated memory block.
+ * @retval NULL allocation failed, core memory exhausted.
+ *
+ * @iclass
+ */
+static inline void *chCoreAllocI(size_t size) {
+
+ return chCoreAllocAlignedWithOffsetI(size, PORT_NATURAL_ALIGN, 0U);
+}
+
+/**
+ * @brief Allocates a memory block.
+ * @details The allocated block is guaranteed to be properly aligned for a
+ * pointer data type.
+ *
+ * @param[in] size the size of the block to be allocated.
+ * @return A pointer to the allocated memory block.
+ * @retval NULL allocation failed, core memory exhausted.
+ *
+ * @api
+ */
+static inline void *chCoreAlloc(size_t size) {
+
+ return chCoreAllocAlignedWithOffset(size, PORT_NATURAL_ALIGN, 0U);
+}
+
+#endif /* CH_CFG_USE_MEMCORE == TRUE */
+
+#endif /* CHMEMCORE_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmempools.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmempools.h
new file mode 100644
index 0000000000..b1a01afda5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/include/chmempools.h
@@ -0,0 +1,257 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmempools.h
+ * @brief Memory Pools macros and structures.
+ *
+ * @addtogroup pools
+ * @{
+ */
+
+#ifndef CHMEMPOOLS_H
+#define CHMEMPOOLS_H
+
+#if (CH_CFG_USE_MEMPOOLS == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if CH_CFG_USE_MEMCORE == FALSE
+#error "CH_CFG_USE_MEMPOOLS requires CH_CFG_USE_MEMCORE"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Memory pool free object header.
+ */
+struct pool_header {
+ struct pool_header *next; /**< @brief Pointer to the next pool
+ header in the list. */
+};
+
+/**
+ * @brief Memory pool descriptor.
+ */
+typedef struct {
+ struct pool_header *next; /**< @brief Pointer to the header. */
+ size_t object_size; /**< @brief Memory pool objects
+ size. */
+ memgetfunc_t provider; /**< @brief Memory blocks provider
+ for this pool. */
+} memory_pool_t;
+
+#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Guarded memory pool descriptor.
+ */
+typedef struct {
+ semaphore_t sem; /**< @brief Counter semaphore guarding
+ the memory pool. */
+ memory_pool_t pool; /**< @brief The memory pool itself. */
+} guarded_memory_pool_t;
+#endif /* CH_CFG_USE_SEMAPHORES == TRUE */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Data part of a static memory pool initializer.
+ * @details This macro should be used when statically initializing a
+ * memory pool that is part of a bigger structure.
+ *
+ * @param[in] name the name of the memory pool variable
+ * @param[in] size size of the memory pool contained objects
+ * @param[in] provider memory provider function for the memory pool
+ */
+#define _MEMORYPOOL_DATA(name, size, provider) \
+ {NULL, size, provider}
+
+/**
+ * @brief Static memory pool initializer.
+ * @details Statically initialized memory pools require no explicit
+ * initialization using @p chPoolInit().
+ *
+ * @param[in] name the name of the memory pool variable
+ * @param[in] size size of the memory pool contained objects
+ * @param[in] provider memory provider function for the memory pool or @p NULL
+ * if the pool is not allowed to grow automatically
+ */
+#define MEMORYPOOL_DECL(name, size, provider) \
+ memory_pool_t name = _MEMORYPOOL_DATA(name, size, provider)
+
+#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Data part of a static guarded memory pool initializer.
+ * @details This macro should be used when statically initializing a
+ * memory pool that is part of a bigger structure.
+ *
+ * @param[in] name the name of the memory pool variable
+ * @param[in] size size of the memory pool contained objects
+ */
+#define _GUARDEDMEMORYPOOL_DATA(name, size) { \
+ _SEMAPHORE_DATA(name.sem, (cnt_t)0), \
+ _MEMORYPOOL_DATA(NULL, size, NULL) \
+}
+
+/**
+ * @brief Static guarded memory pool initializer.
+ * @details Statically initialized guarded memory pools require no explicit
+ * initialization using @p chGuardedPoolInit().
+ *
+ * @param[in] name the name of the guarded memory pool variable
+ * @param[in] size size of the memory pool contained objects
+ */
+#define GUARDEDMEMORYPOOL_DECL(name, size) \
+ guarded_memory_pool_t name = _GUARDEDMEMORYPOOL_DATA(name, size)
+#endif /* CH_CFG_USE_SEMAPHORES == TRUE */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chPoolObjectInit(memory_pool_t *mp, size_t size, memgetfunc_t provider);
+ void chPoolLoadArray(memory_pool_t *mp, void *p, size_t n);
+ void *chPoolAllocI(memory_pool_t *mp);
+ void *chPoolAlloc(memory_pool_t *mp);
+ void chPoolFreeI(memory_pool_t *mp, void *objp);
+ void chPoolFree(memory_pool_t *mp, void *objp);
+#if CH_CFG_USE_SEMAPHORES == TRUE
+ void chGuardedPoolObjectInit(guarded_memory_pool_t *gmp, size_t size);
+ void chGuardedPoolLoadArray(guarded_memory_pool_t *gmp, void *p, size_t n);
+ void *chGuardedPoolAllocTimeoutS(guarded_memory_pool_t *gmp,
+ systime_t timeout);
+ void *chGuardedPoolAllocTimeout(guarded_memory_pool_t *gmp,
+ systime_t timeout);
+ void chGuardedPoolFreeI(guarded_memory_pool_t *gmp, void *objp);
+ void chGuardedPoolFree(guarded_memory_pool_t *gmp, void *objp);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Adds an object to a memory pool.
+ * @pre The memory pool must be already been initialized.
+ * @pre The added object must be of the right size for the specified
+ * memory pool.
+ * @pre The added object must be memory aligned to the size of
+ * @p stkalign_t type.
+ * @note This function is just an alias for @p chPoolFree() and has been
+ * added for clarity.
+ *
+ * @param[in] mp pointer to a @p memory_pool_t structure
+ * @param[in] objp the pointer to the object to be added
+ *
+ * @api
+ */
+static inline void chPoolAdd(memory_pool_t *mp, void *objp) {
+
+ chPoolFree(mp, objp);
+}
+
+/**
+ * @brief Adds an object to a memory pool.
+ * @pre The memory pool must be already been initialized.
+ * @pre The added object must be of the right size for the specified
+ * memory pool.
+ * @pre The added object must be memory aligned to the size of
+ * @p stkalign_t type.
+ * @note This function is just an alias for @p chPoolFreeI() and has been
+ * added for clarity.
+ *
+ * @param[in] mp pointer to a @p memory_pool_t structure
+ * @param[in] objp the pointer to the object to be added
+ *
+ * @iclass
+ */
+static inline void chPoolAddI(memory_pool_t *mp, void *objp) {
+
+ chDbgCheckClassI();
+
+ chPoolFreeI(mp, objp);
+}
+
+#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Adds an object to a guarded memory pool.
+ * @pre The guarded memory pool must be already been initialized.
+ * @pre The added object must be of the right size for the specified
+ * guarded memory pool.
+ * @pre The added object must be properly aligned.
+ * @note This function is just an alias for @p chGuardedPoolFree() and
+ * has been added for clarity.
+ *
+ * @param[in] gmp pointer to a @p guarded_memory_pool_t structure
+ * @param[in] objp the pointer to the object to be added
+ *
+ * @api
+ */
+static inline void chGuardedPoolAdd(guarded_memory_pool_t *gmp, void *objp) {
+
+ chGuardedPoolFree(gmp, objp);
+}
+
+/**
+ * @brief Adds an object to a guarded memory pool.
+ * @pre The guarded memory pool must be already been initialized.
+ * @pre The added object must be of the right size for the specified
+ * guarded memory pool.
+ * @pre The added object must be properly aligned.
+ * @note This function is just an alias for @p chGuardedPoolFreeI() and
+ * has been added for clarity.
+ *
+ * @param[in] gmp pointer to a @p guarded_memory_pool_t structure
+ * @param[in] objp the pointer to the object to be added
+ *
+ * @iclass
+ */
+static inline void chGuardedPoolAddI(guarded_memory_pool_t *gmp, void *objp) {
+
+ chDbgCheckClassI();
+
+ chGuardedPoolFreeI(gmp, objp);
+}
+#endif /* CH_CFG_USE_SEMAPHORES == TRUE */
+
+#endif /* CH_CFG_USE_MEMPOOLS == TRUE */
+
+#endif /* CHMEMPOOLS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/readme.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/readme.txt
new file mode 100644
index 0000000000..1ccb5681b1
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/readme.txt
@@ -0,0 +1,3 @@
+All the code contained under ./os/common/oslib are optional RTOS modules
+compatible with both RT and NIL. The code is placed under ./os/common in
+order to prevent code duplication and disalignments.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chheap.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chheap.c
new file mode 100644
index 0000000000..ece5168c7b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chheap.c
@@ -0,0 +1,397 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chheap.c
+ * @brief Heaps code.
+ *
+ * @addtogroup heaps
+ * @details Heap Allocator related APIs.
+ * Operation mode
+ * The heap allocator implements a first-fit strategy and its APIs
+ * are functionally equivalent to the usual @p malloc() and @p free()
+ * library functions. The main difference is that the OS heap APIs
+ * are guaranteed to be thread safe and there is the ability to
+ * return memory blocks aligned to arbitrary powers of two.
+ * @pre In order to use the heap APIs the @p CH_CFG_USE_HEAP option must
+ * be enabled in @p chconf.h.
+ * @note Compatible with RT and NIL.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_CFG_USE_HEAP == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*
+ * Defaults on the best synchronization mechanism available.
+ */
+#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__)
+#define H_LOCK(h) chMtxLock(&(h)->mtx)
+#define H_UNLOCK(h) chMtxUnlock(&(h)->mtx)
+#else
+#define H_LOCK(h) (void) chSemWait(&(h)->sem)
+#define H_UNLOCK(h) chSemSignal(&(h)->sem)
+#endif
+
+#define H_BLOCK(hp) ((hp) + 1U)
+
+#define H_LIMIT(hp) (H_BLOCK(hp) + H_PAGES(hp))
+
+#define H_NEXT(hp) ((hp)->free.next)
+
+#define H_PAGES(hp) ((hp)->free.pages)
+
+#define H_HEAP(hp) ((hp)->used.heap)
+
+#define H_SIZE(hp) ((hp)->used.size)
+
+/*
+ * Number of pages between two pointers in a MISRA-compatible way.
+ */
+#define NPAGES(p1, p2) \
+ /*lint -save -e9033 [10.8] The cast is safe.*/ \
+ ((size_t)((p1) - (p2))) \
+ /*lint -restore*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/**
+ * @brief Default heap descriptor.
+ */
+static memory_heap_t default_heap;
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the default heap.
+ *
+ * @notapi
+ */
+void _heap_init(void) {
+
+ default_heap.provider = chCoreAllocAlignedWithOffset;
+ H_NEXT(&default_heap.header) = NULL;
+ H_PAGES(&default_heap.header) = 0;
+#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__)
+ chMtxObjectInit(&default_heap.mtx);
+#else
+ chSemObjectInit(&default_heap.sem, (cnt_t)1);
+#endif
+}
+
+/**
+ * @brief Initializes a memory heap from a static memory area.
+ * @note The heap buffer base and size are adjusted if the passed buffer
+ * is not aligned to @p CH_HEAP_ALIGNMENT. This mean that the
+ * effective heap size can be less than @p size.
+ *
+ * @param[out] heapp pointer to the memory heap descriptor to be initialized
+ * @param[in] buf heap buffer base
+ * @param[in] size heap size
+ *
+ * @init
+ */
+void chHeapObjectInit(memory_heap_t *heapp, void *buf, size_t size) {
+ heap_header_t *hp = (heap_header_t *)MEM_ALIGN_NEXT(buf, CH_HEAP_ALIGNMENT);
+
+ chDbgCheck((heapp != NULL) && (size > 0U));
+
+ /* Adjusting the size in case the initial block was not correctly
+ aligned.*/
+ size -= (size_t)((uint8_t *)hp - (uint8_t *)buf);
+
+ /* Initializing the heap header.*/
+ heapp->provider = NULL;
+ H_NEXT(&heapp->header) = hp;
+ H_PAGES(&heapp->header) = 0;
+ H_NEXT(hp) = NULL;
+ H_PAGES(hp) = (size - sizeof (heap_header_t)) / CH_HEAP_ALIGNMENT;
+#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__)
+ chMtxObjectInit(&heapp->mtx);
+#else
+ chSemObjectInit(&heapp->sem, (cnt_t)1);
+#endif
+}
+
+/**
+ * @brief Allocates a block of memory from the heap by using the first-fit
+ * algorithm.
+ * @details The allocated block is guaranteed to be properly aligned to the
+ * specified alignment.
+ *
+ * @param[in] heapp pointer to a heap descriptor or @p NULL in order to
+ * access the default heap.
+ * @param[in] size the size of the block to be allocated. Note that the
+ * allocated block may be a bit bigger than the requested
+ * size for alignment and fragmentation reasons.
+ * @param[in] align desired memory alignment
+ * @return A pointer to the aligned allocated block.
+ * @retval NULL if the block cannot be allocated.
+ *
+ * @api
+ */
+void *chHeapAllocAligned(memory_heap_t *heapp, size_t size, unsigned align) {
+ heap_header_t *qp, *hp, *ahp;
+ size_t pages;
+
+ chDbgCheck((size > 0U) && MEM_IS_VALID_ALIGNMENT(align));
+
+ /* If an heap is not specified then the default system header is used.*/
+ if (heapp == NULL) {
+ heapp = &default_heap;
+ }
+
+ /* Minimum alignment is constrained by the heap header structure size.*/
+ if (align < CH_HEAP_ALIGNMENT) {
+ align = CH_HEAP_ALIGNMENT;
+ }
+
+ /* Size is converted in number of elementary allocation units.*/
+ pages = MEM_ALIGN_NEXT(size, CH_HEAP_ALIGNMENT) / CH_HEAP_ALIGNMENT;
+
+ /* Taking heap mutex/semaphore.*/
+ H_LOCK(heapp);
+
+ /* Start of the free blocks list.*/
+ qp = &heapp->header;
+ while (H_NEXT(qp) != NULL) {
+
+ /* Next free block.*/
+ hp = H_NEXT(qp);
+
+ /* Pointer aligned to the requested alignment.*/
+ ahp = (heap_header_t *)MEM_ALIGN_NEXT(H_BLOCK(hp), align) - 1U;
+
+ if ((ahp < H_LIMIT(hp)) && (pages <= NPAGES(H_LIMIT(hp), ahp + 1U))) {
+ /* The block is large enough to contain a correctly aligned area
+ of sufficient size.*/
+
+ if (ahp > hp) {
+ /* The block is not properly aligned, must split it.*/
+ size_t bpages;
+
+ bpages = NPAGES(H_LIMIT(hp), H_BLOCK(ahp));
+ H_PAGES(hp) = NPAGES(ahp, H_BLOCK(hp));
+ if (bpages > pages) {
+ /* The block is bigger than required, must split the excess.*/
+ heap_header_t *fp;
+
+ /* Creating the excess block.*/
+ fp = H_BLOCK(ahp) + pages;
+ H_PAGES(fp) = (bpages - pages) - 1U;
+
+ /* Linking the excess block.*/
+ H_NEXT(fp) = H_NEXT(hp);
+ H_NEXT(hp) = fp;
+ }
+
+ hp = ahp;
+ }
+ else {
+ /* The block is already properly aligned.*/
+
+ if (H_PAGES(hp) == pages) {
+ /* Exact size, getting the whole block.*/
+ H_NEXT(qp) = H_NEXT(hp);
+ }
+ else {
+ /* The block is bigger than required, must split the excess.*/
+ heap_header_t *fp;
+
+ fp = H_BLOCK(hp) + pages;
+ H_NEXT(fp) = H_NEXT(hp);
+ H_PAGES(fp) = NPAGES(H_LIMIT(hp), H_BLOCK(fp));
+ H_NEXT(qp) = fp;
+ }
+ }
+
+ /* Setting in the block owner heap and size.*/
+ H_SIZE(hp) = size;
+ H_HEAP(hp) = heapp;
+
+ /* Releasing heap mutex/semaphore.*/
+ H_UNLOCK(heapp);
+
+ /*lint -save -e9087 [11.3] Safe cast.*/
+ return (void *)H_BLOCK(hp);
+ /*lint -restore*/
+ }
+
+ /* Next in the free blocks list.*/
+ qp = hp;
+ }
+
+ /* Releasing heap mutex/semaphore.*/
+ H_UNLOCK(heapp);
+
+ /* More memory is required, tries to get it from the associated provider
+ else fails.*/
+ if (heapp->provider != NULL) {
+ ahp = heapp->provider((pages + 1U) * CH_HEAP_ALIGNMENT,
+ align,
+ sizeof (heap_header_t));
+ if (ahp != NULL) {
+ hp = ahp - 1U;
+ H_HEAP(hp) = heapp;
+ H_SIZE(hp) = size;
+
+ /*lint -save -e9087 [11.3] Safe cast.*/
+ return (void *)ahp;
+ /*lint -restore*/
+ }
+ }
+
+ return NULL;
+}
+
+/**
+ * @brief Frees a previously allocated memory block.
+ *
+ * @param[in] p pointer to the memory block to be freed
+ *
+ * @api
+ */
+void chHeapFree(void *p) {
+ heap_header_t *qp, *hp;
+ memory_heap_t *heapp;
+
+ chDbgCheck((p != NULL) && MEM_IS_ALIGNED(p, CH_HEAP_ALIGNMENT));
+
+ /*lint -save -e9087 [11.3] Safe cast.*/
+ hp = (heap_header_t *)p - 1U;
+ /*lint -restore*/
+ heapp = H_HEAP(hp);
+ qp = &heapp->header;
+
+ /* Size is converted in number of elementary allocation units.*/
+ H_PAGES(hp) = MEM_ALIGN_NEXT(H_SIZE(hp),
+ CH_HEAP_ALIGNMENT) / CH_HEAP_ALIGNMENT;
+
+ /* Taking heap mutex/semaphore.*/
+ H_LOCK(heapp);
+
+ while (true) {
+ chDbgAssert((hp < qp) || (hp >= H_LIMIT(qp)), "within free block");
+
+ if (((qp == &heapp->header) || (hp > qp)) &&
+ ((H_NEXT(qp) == NULL) || (hp < H_NEXT(qp)))) {
+ /* Insertion after qp.*/
+ H_NEXT(hp) = H_NEXT(qp);
+ H_NEXT(qp) = hp;
+ /* Verifies if the newly inserted block should be merged.*/
+ if (H_LIMIT(hp) == H_NEXT(hp)) {
+ /* Merge with the next block.*/
+ H_PAGES(hp) += H_PAGES(H_NEXT(hp)) + 1U;
+ H_NEXT(hp) = H_NEXT(H_NEXT(hp));
+ }
+ if ((H_LIMIT(qp) == hp)) {
+ /* Merge with the previous block.*/
+ H_PAGES(qp) += H_PAGES(hp) + 1U;
+ H_NEXT(qp) = H_NEXT(hp);
+ }
+ break;
+ }
+ qp = H_NEXT(qp);
+ }
+
+ /* Releasing heap mutex/semaphore.*/
+ H_UNLOCK(heapp);
+
+ return;
+}
+
+/**
+ * @brief Reports the heap status.
+ * @note This function is meant to be used in the test suite, it should
+ * not be really useful for the application code.
+ *
+ * @param[in] heapp pointer to a heap descriptor or @p NULL in order to
+ * access the default heap.
+ * @param[in] totalp pointer to a variable that will receive the total
+ * fragmented free space or @ NULL
+ * @param[in] largestp pointer to a variable that will receive the largest
+ * free free block found space or @ NULL
+ * @return The number of fragments in the heap.
+ *
+ * @api
+ */
+size_t chHeapStatus(memory_heap_t *heapp, size_t *totalp, size_t *largestp) {
+ heap_header_t *qp;
+ size_t n, tpages, lpages;
+
+ if (heapp == NULL) {
+ heapp = &default_heap;
+ }
+
+ H_LOCK(heapp);
+ tpages = 0U;
+ lpages = 0U;
+ n = 0U;
+ qp = &heapp->header;
+ while (H_NEXT(qp) != NULL) {
+ size_t pages = H_PAGES(H_NEXT(qp));
+
+ /* Updating counters.*/
+ n++;
+ tpages += pages;
+ if (pages > lpages) {
+ lpages = pages;
+ }
+
+ qp = H_NEXT(qp);
+ }
+
+ /* Writing out fragmented free memory.*/
+ if (totalp != NULL) {
+ *totalp = tpages * CH_HEAP_ALIGNMENT;
+ }
+
+ /* Writing out unfragmented free memory.*/
+ if (largestp != NULL) {
+ *largestp = lpages * CH_HEAP_ALIGNMENT;
+ }
+ H_UNLOCK(heapp);
+
+ return n;
+}
+
+#endif /* CH_CFG_USE_HEAP == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmboxes.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmboxes.c
new file mode 100644
index 0000000000..041118b3ba
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmboxes.c
@@ -0,0 +1,522 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmboxes.c
+ * @brief Mailboxes code.
+ *
+ * @addtogroup mailboxes
+ * @details Asynchronous messages.
+ * Operation mode
+ * A mailbox is an asynchronous communication mechanism.
+ * Operations defined for mailboxes:
+ * - Post: Posts a message on the mailbox in FIFO order.
+ * - Post Ahead: Posts a message on the mailbox with urgent
+ * priority.
+ * - Fetch: A message is fetched from the mailbox and removed
+ * from the queue.
+ * - Reset: The mailbox is emptied and all the stored messages
+ * are lost.
+ * .
+ * A message is a variable of type msg_t that is guaranteed to have
+ * the same size of and be compatible with (data) pointers (anyway an
+ * explicit cast is needed).
+ * If larger messages need to be exchanged then a pointer to a
+ * structure can be posted in the mailbox but the posting side has
+ * no predefined way to know when the message has been processed. A
+ * possible approach is to allocate memory (from a memory pool for
+ * example) from the posting side and free it on the fetching side.
+ * Another approach is to set a "done" flag into the structure pointed
+ * by the message.
+ * @pre In order to use the mailboxes APIs the @p CH_CFG_USE_MAILBOXES
+ * option must be enabled in @p chconf.h.
+ * @note Compatible with RT and NIL.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_CFG_USE_MAILBOXES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes a @p mailbox_t object.
+ *
+ * @param[out] mbp the pointer to the @p mailbox_t structure to be
+ * initialized
+ * @param[in] buf pointer to the messages buffer as an array of @p msg_t
+ * @param[in] n number of elements in the buffer array
+ *
+ * @init
+ */
+void chMBObjectInit(mailbox_t *mbp, msg_t *buf, cnt_t n) {
+
+ chDbgCheck((mbp != NULL) && (buf != NULL) && (n > (cnt_t)0));
+
+ mbp->buffer = buf;
+ mbp->rdptr = buf;
+ mbp->wrptr = buf;
+ mbp->top = &buf[n];
+ mbp->cnt = (cnt_t)0;
+ mbp->reset = false;
+ chThdQueueObjectInit(&mbp->qw);
+ chThdQueueObjectInit(&mbp->qr);
+}
+
+/**
+ * @brief Resets a @p mailbox_t object.
+ * @details All the waiting threads are resumed with status @p MSG_RESET and
+ * the queued messages are lost.
+ * @post The mailbox is in reset state, all operations will fail and
+ * return @p MSG reset until the mailbox is enabled again using
+ * @p chMBResumeX().
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ *
+ * @api
+ */
+void chMBReset(mailbox_t *mbp) {
+
+ chSysLock();
+ chMBResetI(mbp);
+ chSchRescheduleS();
+ chSysUnlock();
+}
+
+/**
+ * @brief Resets a @p mailbox_t object.
+ * @details All the waiting threads are resumed with status @p MSG_RESET and
+ * the queued messages are lost.
+ * @post The mailbox is in reset state, all operations will fail and
+ * return @p MSG reset until the mailbox is enabled again using
+ * @p chMBResumeX().
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ *
+ * @api
+ */
+void chMBResetI(mailbox_t *mbp) {
+
+ chDbgCheckClassI();
+ chDbgCheck(mbp != NULL);
+
+ mbp->wrptr = mbp->buffer;
+ mbp->rdptr = mbp->buffer;
+ mbp->cnt = (cnt_t)0;
+ mbp->reset = true;
+ chThdDequeueAllI(&mbp->qw, MSG_RESET);
+ chThdDequeueAllI(&mbp->qr, MSG_RESET);
+}
+
+/**
+ * @brief Posts a message into a mailbox.
+ * @details The invoking thread waits until a empty slot in the mailbox becomes
+ * available or the specified time runs out.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[in] msg the message to be posted on the mailbox
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the operation has timed out.
+ *
+ * @api
+ */
+msg_t chMBPost(mailbox_t *mbp, msg_t msg, systime_t timeout) {
+ msg_t rdymsg;
+
+ chSysLock();
+ rdymsg = chMBPostS(mbp, msg, timeout);
+ chSysUnlock();
+
+ return rdymsg;
+}
+
+/**
+ * @brief Posts a message into a mailbox.
+ * @details The invoking thread waits until a empty slot in the mailbox becomes
+ * available or the specified time runs out.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[in] msg the message to be posted on the mailbox
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the operation has timed out.
+ *
+ * @sclass
+ */
+msg_t chMBPostS(mailbox_t *mbp, msg_t msg, systime_t timeout) {
+ msg_t rdymsg;
+
+ chDbgCheckClassS();
+ chDbgCheck(mbp != NULL);
+
+ do {
+ /* If the mailbox is in reset state then returns immediately.*/
+ if (mbp->reset) {
+ return MSG_RESET;
+ }
+
+ /* Is there a free message slot in queue? if so then post.*/
+ if (chMBGetFreeCountI(mbp) > (cnt_t)0) {
+ *mbp->wrptr++ = msg;
+ if (mbp->wrptr >= mbp->top) {
+ mbp->wrptr = mbp->buffer;
+ }
+ mbp->cnt++;
+
+ /* If there is a reader waiting then makes it ready.*/
+ chThdDequeueNextI(&mbp->qr, MSG_OK);
+ chSchRescheduleS();
+
+ return MSG_OK;
+ }
+
+ /* No space in the queue, waiting for a slot to become available.*/
+ rdymsg = chThdEnqueueTimeoutS(&mbp->qw, timeout);
+ } while (rdymsg == MSG_OK);
+
+ return rdymsg;
+}
+
+/**
+ * @brief Posts a message into a mailbox.
+ * @details This variant is non-blocking, the function returns a timeout
+ * condition if the queue is full.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[in] msg the message to be posted on the mailbox
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the mailbox is full and the message cannot be
+ * posted.
+ *
+ * @iclass
+ */
+msg_t chMBPostI(mailbox_t *mbp, msg_t msg) {
+
+ chDbgCheckClassI();
+ chDbgCheck(mbp != NULL);
+
+ /* If the mailbox is in reset state then returns immediately.*/
+ if (mbp->reset) {
+ return MSG_RESET;
+ }
+
+ /* Is there a free message slot in queue? if so then post.*/
+ if (chMBGetFreeCountI(mbp) > (cnt_t)0) {
+ *mbp->wrptr++ = msg;
+ if (mbp->wrptr >= mbp->top) {
+ mbp->wrptr = mbp->buffer;
+ }
+ mbp->cnt++;
+
+ /* If there is a reader waiting then makes it ready.*/
+ chThdDequeueNextI(&mbp->qr, MSG_OK);
+
+ return MSG_OK;
+ }
+
+ /* No space, immediate timeout.*/
+ return MSG_TIMEOUT;
+}
+
+/**
+ * @brief Posts an high priority message into a mailbox.
+ * @details The invoking thread waits until a empty slot in the mailbox becomes
+ * available or the specified time runs out.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[in] msg the message to be posted on the mailbox
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the operation has timed out.
+ *
+ * @api
+ */
+msg_t chMBPostAhead(mailbox_t *mbp, msg_t msg, systime_t timeout) {
+ msg_t rdymsg;
+
+ chSysLock();
+ rdymsg = chMBPostAheadS(mbp, msg, timeout);
+ chSysUnlock();
+
+ return rdymsg;
+}
+
+/**
+ * @brief Posts an high priority message into a mailbox.
+ * @details The invoking thread waits until a empty slot in the mailbox becomes
+ * available or the specified time runs out.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[in] msg the message to be posted on the mailbox
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the operation has timed out.
+ *
+ * @sclass
+ */
+msg_t chMBPostAheadS(mailbox_t *mbp, msg_t msg, systime_t timeout) {
+ msg_t rdymsg;
+
+ chDbgCheckClassS();
+ chDbgCheck(mbp != NULL);
+
+ do {
+ /* If the mailbox is in reset state then returns immediately.*/
+ if (mbp->reset) {
+ return MSG_RESET;
+ }
+
+ /* Is there a free message slot in queue? if so then post.*/
+ if (chMBGetFreeCountI(mbp) > (cnt_t)0) {
+ if (--mbp->rdptr < mbp->buffer) {
+ mbp->rdptr = mbp->top - 1;
+ }
+ *mbp->rdptr = msg;
+ mbp->cnt++;
+
+ /* If there is a reader waiting then makes it ready.*/
+ chThdDequeueNextI(&mbp->qr, MSG_OK);
+ chSchRescheduleS();
+
+ return MSG_OK;
+ }
+
+ /* No space in the queue, waiting for a slot to become available.*/
+ rdymsg = chThdEnqueueTimeoutS(&mbp->qw, timeout);
+ } while (rdymsg == MSG_OK);
+
+ return rdymsg;
+}
+
+/**
+ * @brief Posts an high priority message into a mailbox.
+ * @details This variant is non-blocking, the function returns a timeout
+ * condition if the queue is full.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[in] msg the message to be posted on the mailbox
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the mailbox is full and the message cannot be
+ * posted.
+ *
+ * @iclass
+ */
+msg_t chMBPostAheadI(mailbox_t *mbp, msg_t msg) {
+
+ chDbgCheckClassI();
+ chDbgCheck(mbp != NULL);
+
+ /* If the mailbox is in reset state then returns immediately.*/
+ if (mbp->reset) {
+ return MSG_RESET;
+ }
+
+ /* Is there a free message slot in queue? if so then post.*/
+ if (chMBGetFreeCountI(mbp) > (cnt_t)0) {
+ if (--mbp->rdptr < mbp->buffer) {
+ mbp->rdptr = mbp->top - 1;
+ }
+ *mbp->rdptr = msg;
+ mbp->cnt++;
+
+ /* If there is a reader waiting then makes it ready.*/
+ chThdDequeueNextI(&mbp->qr, MSG_OK);
+
+ return MSG_OK;
+ }
+
+ /* No space, immediate timeout.*/
+ return MSG_TIMEOUT;
+}
+
+/**
+ * @brief Retrieves a message from a mailbox.
+ * @details The invoking thread waits until a message is posted in the mailbox
+ * or the specified time runs out.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[out] msgp pointer to a message variable for the received message
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly fetched.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the operation has timed out.
+ *
+ * @api
+ */
+msg_t chMBFetch(mailbox_t *mbp, msg_t *msgp, systime_t timeout) {
+ msg_t rdymsg;
+
+ chSysLock();
+ rdymsg = chMBFetchS(mbp, msgp, timeout);
+ chSysUnlock();
+
+ return rdymsg;
+}
+
+/**
+ * @brief Retrieves a message from a mailbox.
+ * @details The invoking thread waits until a message is posted in the mailbox
+ * or the specified time runs out.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[out] msgp pointer to a message variable for the received message
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly fetched.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the operation has timed out.
+ *
+ * @sclass
+ */
+msg_t chMBFetchS(mailbox_t *mbp, msg_t *msgp, systime_t timeout) {
+ msg_t rdymsg;
+
+ chDbgCheckClassS();
+ chDbgCheck((mbp != NULL) && (msgp != NULL));
+
+ do {
+ /* If the mailbox is in reset state then returns immediately.*/
+ if (mbp->reset) {
+ return MSG_RESET;
+ }
+
+ /* Is there a message in queue? if so then fetch.*/
+ if (chMBGetUsedCountI(mbp) > (cnt_t)0) {
+ *msgp = *mbp->rdptr++;
+ if (mbp->rdptr >= mbp->top) {
+ mbp->rdptr = mbp->buffer;
+ }
+ mbp->cnt--;
+
+ /* If there is a writer waiting then makes it ready.*/
+ chThdDequeueNextI(&mbp->qw, MSG_OK);
+ chSchRescheduleS();
+
+ return MSG_OK;
+ }
+
+ /* No message in the queue, waiting for a message to become available.*/
+ rdymsg = chThdEnqueueTimeoutS(&mbp->qr, timeout);
+ } while (rdymsg == MSG_OK);
+
+ return rdymsg;
+}
+
+/**
+ * @brief Retrieves a message from a mailbox.
+ * @details This variant is non-blocking, the function returns a timeout
+ * condition if the queue is empty.
+ *
+ * @param[in] mbp the pointer to an initialized @p mailbox_t object
+ * @param[out] msgp pointer to a message variable for the received message
+ * @return The operation status.
+ * @retval MSG_OK if a message has been correctly fetched.
+ * @retval MSG_RESET if the mailbox has been reset.
+ * @retval MSG_TIMEOUT if the mailbox is empty and a message cannot be
+ * fetched.
+ *
+ * @iclass
+ */
+msg_t chMBFetchI(mailbox_t *mbp, msg_t *msgp) {
+
+ chDbgCheckClassI();
+ chDbgCheck((mbp != NULL) && (msgp != NULL));
+
+ /* If the mailbox is in reset state then returns immediately.*/
+ if (mbp->reset) {
+ return MSG_RESET;
+ }
+
+ /* Is there a message in queue? if so then fetch.*/
+ if (chMBGetUsedCountI(mbp) > (cnt_t)0) {
+ *msgp = *mbp->rdptr++;
+ if (mbp->rdptr >= mbp->top) {
+ mbp->rdptr = mbp->buffer;
+ }
+ mbp->cnt--;
+
+ /* If there is a writer waiting then makes it ready.*/
+ chThdDequeueNextI(&mbp->qw, MSG_OK);
+
+ return MSG_OK;
+ }
+
+ /* No message, immediate timeout.*/
+ return MSG_TIMEOUT;
+}
+#endif /* CH_CFG_USE_MAILBOXES == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmemcore.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmemcore.c
new file mode 100644
index 0000000000..a768dc6757
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmemcore.c
@@ -0,0 +1,175 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmemcore.c
+ * @brief Core memory manager code.
+ *
+ * @addtogroup memcore
+ * @details Core Memory Manager related APIs and services.
+ * Operation mode
+ * The core memory manager is a simplified allocator that only
+ * allows to allocate memory blocks without the possibility to
+ * free them.
+ * This allocator is meant as a memory blocks provider for the
+ * other allocators such as:
+ * - C-Runtime allocator (through a compiler specific adapter module).
+ * - Heap allocator (see @ref heaps).
+ * - Memory pools allocator (see @ref pools).
+ * .
+ * By having a centralized memory provider the various allocators
+ * can coexist and share the main memory.
+ * This allocator, alone, is also useful for very simple
+ * applications that just require a simple way to get memory
+ * blocks.
+ * @pre In order to use the core memory manager APIs the @p CH_CFG_USE_MEMCORE
+ * option must be enabled in @p chconf.h.
+ * @note Compatible with RT and NIL.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_CFG_USE_MEMCORE == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief Memory core descriptor.
+ */
+memcore_t ch_memcore;
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level memory manager initialization.
+ *
+ * @notapi
+ */
+void _core_init(void) {
+#if CH_CFG_MEMCORE_SIZE == 0
+ extern uint8_t __heap_base__[];
+ extern uint8_t __heap_end__[];
+
+ /*lint -save -e9033 [10.8] Required cast operations.*/
+ ch_memcore.nextmem = __heap_base__;
+ ch_memcore.endmem = __heap_end__;
+ /*lint restore*/
+#else
+ static uint8_t static_heap[CH_CFG_MEMCORE_SIZE];
+
+ ch_memcore.nextmem = &static_heap[0];
+ ch_memcore.endmem = &static_heap[CH_CFG_MEMCORE_SIZE];
+#endif
+}
+
+/**
+ * @brief Allocates a memory block.
+ * @details This function allocates a block of @p offset + @p size bytes. The
+ * returned pointer has @p offset bytes before its address and
+ * @p size bytes after.
+ *
+ * @param[in] size the size of the block to be allocated.
+ * @param[in] align desired memory alignment
+ * @param[in] offset aligned pointer offset
+ * @return A pointer to the allocated memory block.
+ * @retval NULL allocation failed, core memory exhausted.
+ *
+ * @iclass
+ */
+void *chCoreAllocAlignedWithOffsetI(size_t size,
+ unsigned align,
+ size_t offset) {
+ uint8_t *p, *next;
+
+ chDbgCheckClassI();
+ chDbgCheck(MEM_IS_VALID_ALIGNMENT(align));
+
+ size = MEM_ALIGN_NEXT(size, align);
+ p = (uint8_t *)MEM_ALIGN_NEXT(ch_memcore.nextmem + offset, align);
+ next = p + size;
+
+ /* Considering also the case where there is numeric overflow.*/
+ if ((next > ch_memcore.endmem) || (next < ch_memcore.nextmem)) {
+ return NULL;
+ }
+
+ ch_memcore.nextmem = next;
+
+ return p;
+}
+
+/**
+ * @brief Allocates a memory block.
+ * @details This function allocates a block of @p offset + @p size bytes. The
+ * returned pointer has @p offset bytes before its address and
+ * @p size bytes after.
+ *
+ * @param[in] size the size of the block to be allocated.
+ * @param[in] align desired memory alignment
+ * @param[in] offset aligned pointer offset
+ * @return A pointer to the allocated memory block.
+ * @retval NULL allocation failed, core memory exhausted.
+ *
+ * @api
+ */
+void *chCoreAllocAlignedWithOffset(size_t size,
+ unsigned align,
+ size_t offset) {
+ void *p;
+
+ chSysLock();
+ p = chCoreAllocAlignedWithOffsetI(size, align, offset);
+ chSysUnlock();
+
+ return p;
+}
+
+/**
+ * @brief Core memory status.
+ *
+ * @return The size, in bytes, of the free core memory.
+ *
+ * @xclass
+ */
+size_t chCoreGetStatusX(void) {
+
+ /*lint -save -e9033 [10.8] The cast is safe.*/
+ return (size_t)(ch_memcore.endmem - ch_memcore.nextmem);
+ /*lint -restore*/
+}
+#endif /* CH_CFG_USE_MEMCORE == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmempools.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmempools.c
new file mode 100644
index 0000000000..46278ece4d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/oslib/src/chmempools.c
@@ -0,0 +1,338 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmempools.c
+ * @brief Memory Pools code.
+ *
+ * @addtogroup pools
+ * @details Memory Pools related APIs and services.
+ * Operation mode
+ * The Memory Pools APIs allow to allocate/free fixed size objects in
+ * constant time and reliably without memory fragmentation
+ * problems.
+ * Memory Pools do not enforce any alignment constraint on the
+ * contained object however the objects must be properly aligned
+ * to contain a pointer to void.
+ * @pre In order to use the memory pools APIs the @p CH_CFG_USE_MEMPOOLS option
+ * must be enabled in @p chconf.h.
+ * @note Compatible with RT and NIL.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_CFG_USE_MEMPOOLS == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes an empty memory pool.
+ *
+ * @param[out] mp pointer to a @p memory_pool_t structure
+ * @param[in] size the size of the objects contained in this memory pool,
+ * the minimum accepted size is the size of a pointer to
+ * void.
+ * @param[in] provider memory provider function for the memory pool or
+ * @p NULL if the pool is not allowed to grow
+ * automatically
+ *
+ * @init
+ */
+void chPoolObjectInit(memory_pool_t *mp, size_t size, memgetfunc_t provider) {
+
+ chDbgCheck((mp != NULL) && (size >= sizeof(void *)));
+
+ mp->next = NULL;
+ mp->object_size = size;
+ mp->provider = provider;
+}
+
+/**
+ * @brief Loads a memory pool with an array of static objects.
+ * @pre The memory pool must be already been initialized.
+ * @pre The array elements must be of the right size for the specified
+ * memory pool.
+ * @post The memory pool contains the elements of the input array.
+ *
+ * @param[in] mp pointer to a @p memory_pool_t structure
+ * @param[in] p pointer to the array first element
+ * @param[in] n number of elements in the array
+ *
+ * @api
+ */
+void chPoolLoadArray(memory_pool_t *mp, void *p, size_t n) {
+
+ chDbgCheck((mp != NULL) && (n != 0U));
+
+ while (n != 0U) {
+ chPoolAdd(mp, p);
+ /*lint -save -e9087 [11.3] Safe cast.*/
+ p = (void *)(((uint8_t *)p) + mp->object_size);
+ /*lint -restore*/
+ n--;
+ }
+}
+
+/**
+ * @brief Allocates an object from a memory pool.
+ * @pre The memory pool must be already been initialized.
+ *
+ * @param[in] mp pointer to a @p memory_pool_t structure
+ * @return The pointer to the allocated object.
+ * @retval NULL if pool is empty.
+ *
+ * @iclass
+ */
+void *chPoolAllocI(memory_pool_t *mp) {
+ void *objp;
+
+ chDbgCheckClassI();
+ chDbgCheck(mp != NULL);
+
+ objp = mp->next;
+ /*lint -save -e9013 [15.7] There is no else because it is not needed.*/
+ if (objp != NULL) {
+ mp->next = mp->next->next;
+ }
+ else if (mp->provider != NULL) {
+ objp = mp->provider(mp->object_size, PORT_NATURAL_ALIGN); /* TODO: Alignment is not properly handled */
+ }
+ /*lint -restore*/
+
+ return objp;
+}
+
+/**
+ * @brief Allocates an object from a memory pool.
+ * @pre The memory pool must be already been initialized.
+ *
+ * @param[in] mp pointer to a @p memory_pool_t structure
+ * @return The pointer to the allocated object.
+ * @retval NULL if pool is empty.
+ *
+ * @api
+ */
+void *chPoolAlloc(memory_pool_t *mp) {
+ void *objp;
+
+ chSysLock();
+ objp = chPoolAllocI(mp);
+ chSysUnlock();
+
+ return objp;
+}
+
+/**
+ * @brief Releases an object into a memory pool.
+ * @pre The memory pool must be already been initialized.
+ * @pre The freed object must be of the right size for the specified
+ * memory pool.
+ * @pre The added object must be properly aligned.
+ *
+ * @param[in] mp pointer to a @p memory_pool_t structure
+ * @param[in] objp the pointer to the object to be released
+ *
+ * @iclass
+ */
+void chPoolFreeI(memory_pool_t *mp, void *objp) {
+ struct pool_header *php = objp;
+
+ chDbgCheckClassI();
+ chDbgCheck((mp != NULL) && (objp != NULL));
+
+ php->next = mp->next;
+ mp->next = php;
+}
+
+/**
+ * @brief Releases an object into a memory pool.
+ * @pre The memory pool must be already been initialized.
+ * @pre The freed object must be of the right size for the specified
+ * memory pool.
+ * @pre The added object must be properly aligned.
+ *
+ * @param[in] mp pointer to a @p memory_pool_t structure
+ * @param[in] objp the pointer to the object to be released
+ *
+ * @api
+ */
+void chPoolFree(memory_pool_t *mp, void *objp) {
+
+ chSysLock();
+ chPoolFreeI(mp, objp);
+ chSysUnlock();
+}
+
+#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Initializes an empty guarded memory pool.
+ *
+ * @param[out] gmp pointer to a @p guarded_memory_pool_t structure
+ * @param[in] size the size of the objects contained in this guarded
+ * memory pool, the minimum accepted size is the size
+ * of a pointer to void.
+ *
+ * @init
+ */
+void chGuardedPoolObjectInit(guarded_memory_pool_t *gmp, size_t size) {
+
+ chPoolObjectInit(&gmp->pool, size, NULL);
+ chSemObjectInit(&gmp->sem, (cnt_t)0);
+}
+
+/**
+ * @brief Loads a guarded memory pool with an array of static objects.
+ * @pre The guarded memory pool must be already been initialized.
+ * @pre The array elements must be of the right size for the specified
+ * guarded memory pool.
+ * @post The guarded memory pool contains the elements of the input array.
+ *
+ * @param[in] gmp pointer to a @p guarded_memory_pool_t structure
+ * @param[in] p pointer to the array first element
+ * @param[in] n number of elements in the array
+ *
+ * @api
+ */
+void chGuardedPoolLoadArray(guarded_memory_pool_t *gmp, void *p, size_t n) {
+
+ chDbgCheck((gmp != NULL) && (n != 0U));
+
+ while (n != 0U) {
+ chGuardedPoolAdd(gmp, p);
+ /*lint -save -e9087 [11.3] Safe cast.*/
+ p = (void *)(((uint8_t *)p) + gmp->pool.object_size);
+ /*lint -restore*/
+ n--;
+ }
+}
+
+/**
+ * @brief Allocates an object from a guarded memory pool.
+ * @pre The guarded memory pool must be already been initialized.
+ *
+ * @param[in] gmp pointer to a @p guarded_memory_pool_t structure
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The pointer to the allocated object.
+ * @retval NULL if the operation timed out.
+ *
+ * @sclass
+ */
+void *chGuardedPoolAllocTimeoutS(guarded_memory_pool_t *gmp,
+ systime_t timeout) {
+ msg_t msg;
+
+ msg = chSemWaitTimeoutS(&gmp->sem, timeout);
+ if (msg != MSG_OK) {
+ return NULL;
+ }
+
+ return chPoolAllocI(&gmp->pool);
+}
+
+/**
+ * @brief Allocates an object from a guarded memory pool.
+ * @pre The guarded memory pool must be already been initialized.
+ *
+ * @param[in] gmp pointer to a @p guarded_memory_pool_t structure
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The pointer to the allocated object.
+ * @retval NULL if the operation timed out.
+ *
+ * @api
+ */
+void *chGuardedPoolAllocTimeout(guarded_memory_pool_t *gmp,
+ systime_t timeout) {
+ void *p;
+
+ chSysLock();
+ p = chGuardedPoolAllocTimeoutS(gmp, timeout);
+ chSysUnlock();
+
+ return p;
+}
+
+/**
+ * @brief Releases an object into a guarded memory pool.
+ * @pre The guarded memory pool must be already been initialized.
+ * @pre The freed object must be of the right size for the specified
+ * guarded memory pool.
+ * @pre The added object must be properly aligned.
+ *
+ * @param[in] gmp pointer to a @p guarded_memory_pool_t structure
+ * @param[in] objp the pointer to the object to be released
+ *
+ * @iclass
+ */
+void chGuardedPoolFreeI(guarded_memory_pool_t *gmp, void *objp) {
+
+ chPoolFreeI(&gmp->pool, objp);
+ chSemSignalI(&gmp->sem);
+}
+
+/**
+ * @brief Releases an object into a guarded memory pool.
+ * @pre The guarded memory pool must be already been initialized.
+ * @pre The freed object must be of the right size for the specified
+ * guarded memory pool.
+ * @pre The added object must be properly aligned.
+ *
+ * @param[in] gmp pointer to a @p guarded_memory_pool_t structure
+ * @param[in] objp the pointer to the object to be released
+ *
+ * @api
+ */
+void chGuardedPoolFree(guarded_memory_pool_t *gmp, void *objp) {
+
+ chSysLock();
+ chGuardedPoolFreeI(gmp, objp);
+ chSchRescheduleS();
+ chSysUnlock();
+}
+#endif
+
+#endif /* CH_CFG_USE_MEMPOOLS == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore.c
new file mode 100644
index 0000000000..27306de348
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore.c
@@ -0,0 +1,54 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file ARMCMx/chcore.c
+ * @brief ARM Cortex-Mx port code.
+ *
+ * @addtogroup ARMCMx_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore.h
similarity index 50%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore.h
index d1c542f9cb..65e7daf21c 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore.h
@@ -1,195 +1,215 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
- This file is part of ChibiOS/RT.
+ This file is part of ChibiOS.
- ChibiOS/RT is free software; you can redistribute it and/or modify
+ ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
- ChibiOS/RT is distributed in the hope that it will be useful,
+ ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
*/
/**
- * @file GCC/ARMCMx/chcore.h
+ * @file ARMCMx/chcore.h
* @brief ARM Cortex-Mx port macros and structures.
*
* @addtogroup ARMCMx_CORE
* @{
*/
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
+#ifndef CHCORE_H
+#define CHCORE_H
/*===========================================================================*/
-/* Port constants (common). */
+/* Module constants. */
/*===========================================================================*/
-/* Added to make the header stand-alone when included from asm.*/
-#ifndef FALSE
-#define FALSE 0
-#endif
-#ifndef TRUE
-#define TRUE (!FALSE)
-#endif
-
-#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
-#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
-#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
-#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
-
-/* Inclusion of the Cortex-Mx implementation specific parameters.*/
-#include "cmparams.h"
-
-/* Cortex model check, only M0 and M3 supported right now.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \
- (CORTEX_MODEL == CORTEX_M4)
-#elif (CORTEX_MODEL == CORTEX_M1)
-#warning "untested Cortex-M model"
-#else
-#error "unknown or unsupported Cortex-M model"
-#endif
-
/**
- * @brief Total priority levels.
+ * @name Architecture and Compiler
+ * @{
*/
-#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
-
/**
- * @brief Minimum priority level.
- * @details This minimum priority level is calculated from the number of
- * priority bits supported by the specific Cortex-Mx implementation.
+ * @brief Macro defining a generic ARM architecture.
*/
-#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+#define PORT_ARCHITECTURE_ARM
+
+/* The following code is not processed when the file is included from an
+ asm module because those intrinsic macros are not necessarily defined
+ by the assembler too.*/
+#if !defined(_FROM_ASM_)
/**
- * @brief Maximum priority level.
- * @details The maximum allowed priority level is always zero.
+ * @brief Compiler name and version.
*/
-#define CORTEX_MAXIMUM_PRIORITY 0
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME "GCC " __VERSION__
-/*===========================================================================*/
-/* Port macros (common). */
-/*===========================================================================*/
+#elif defined(__ICCARM__)
+#define PORT_COMPILER_NAME "IAR"
-/**
- * @brief Priority level verification macro.
- */
-#define CORTEX_IS_VALID_PRIORITY(n) \
- (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
+#elif defined(__CC_ARM)
+#define PORT_COMPILER_NAME "RVCT"
-/**
- * @brief Priority level verification macro.
- */
-#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \
- (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
+#else
+#error "unsupported compiler"
+#endif
-/**
- * @brief Priority level to priority mask conversion macro.
- */
-#define CORTEX_PRIORITY_MASK(n) \
- ((n) << (8 - CORTEX_PRIORITY_BITS))
+#endif /* !defined(_FROM_ASM_) */
-/*===========================================================================*/
-/* Port configurable parameters (common). */
-/*===========================================================================*/
+/** @} */
-/*===========================================================================*/
-/* Port derived parameters (common). */
-/*===========================================================================*/
+/* Inclusion of the Cortex-Mx implementation specific parameters.*/
+#include "cmparams.h"
/*===========================================================================*/
-/* Port exported info (common). */
+/* Module pre-compile time settings. */
/*===========================================================================*/
/**
- * @brief Macro defining a generic ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM
-
-/**
- * @brief Name of the compiler supported by this port.
+ * @brief Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ * @p chcore_timer.h, if this option is enabled then the file
+ * @p chcore_timer_alt.h is included instead.
*/
-#define CH_COMPILER_NAME "GCC " __VERSION__
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER FALSE
+#endif
/*===========================================================================*/
-/* Port implementation part (common). */
+/* Derived constants and error checks. */
/*===========================================================================*/
-/* Includes the sub-architecture-specific part.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
-#include "chcore_v6m.h"
-#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
-#include "chcore_v7m.h"
-#endif
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+/* The following code is not processed when the file is included from an
+ asm module.*/
#if !defined(_FROM_ASM_)
-#include "nvic.h"
-
-/* The following declarations are there just for Doxygen documentation, the
- real declarations are inside the sub-headers.*/
-#if defined(__DOXYGEN__)
+/**
+ * @brief Type of a generic ARM register.
+ */
+typedef void *regarm_t;
/**
- * @brief Stack and memory alignment enforcement.
+ * @brief Type of stack and memory alignment enforcement.
* @note In this architecture the stack alignment is enforced to 64 bits,
* 32 bits alignment is supported by hardware but deprecated by ARM,
* the implementation choice is to not offer the option.
*/
typedef uint64_t stkalign_t;
+/* The following declarations are there just for Doxygen documentation, the
+ real declarations are inside the sub-headers being specific for the
+ sub-architectures.*/
+#if defined(__DOXYGEN__)
/**
* @brief Interrupt saved context.
* @details This structure represents the stack frame saved during a
* preemption-capable interrupt handler.
* @note It is implemented to match the Cortex-Mx exception context.
*/
-struct extctx {};
+struct port_extctx {};
/**
* @brief System saved context.
* @details This structure represents the inner stack frame during a context
- * switching.
+ * switch.
*/
-struct intctx {};
-
+struct port_intctx {};
#endif /* defined(__DOXYGEN__) */
/**
- * @brief Excludes the default @p chSchIsPreemptionRequired()implementation.
+ * @brief Platform dependent part of the @p thread_t structure.
+ * @details In this port the structure just holds a pointer to the
+ * @p port_intctx structure representing the stack pointer
+ * at context switch time.
+ */
+struct port_context {
+ struct port_intctx *sp;
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Total priority levels.
+ */
+#define CORTEX_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS)
+
+/**
+ * @brief Minimum priority level.
+ * @details This minimum priority level is calculated from the number of
+ * priority bits supported by the specific Cortex-Mx implementation.
+ */
+#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+
+/**
+ * @brief Maximum priority level.
+ * @details The maximum allowed priority level is always zero.
+ */
+#define CORTEX_MAXIMUM_PRIORITY 0U
+
+/**
+ * @brief Priority level to priority mask conversion macro.
+ */
+#define CORTEX_PRIO_MASK(n) \
+ ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS))
+
+/**
+ * @brief Priority level verification macro.
*/
-#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
+#define PORT_IRQ_IS_VALID_PRIORITY(n) \
+ (((n) >= 0U) && ((n) < CORTEX_PRIORITY_LEVELS))
-#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
/**
- * @brief Inline-able version of this kernel function.
+ * @brief Priority level verification macro.
*/
-#define chSchIsPreemptionRequired() \
- (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \
- firstprio(&rlist.r_queue) >= currp->p_prio)
-#else /* CH_TIME_QUANTUM == 0 */
-#define chSchIsPreemptionRequired() \
- (firstprio(&rlist.r_queue) > currp->p_prio)
-#endif /* CH_TIME_QUANTUM == 0 */
+#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \
+ (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/* Includes the sub-architecture-specific part.*/
+#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1)
+#include "chcore_v6m.h"
+#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4) || (CORTEX_MODEL == 7)
+#include "mpu.h"
+#include "chcore_v7m.h"
+#else
+#error "unknown Cortex-M variant"
+#endif
+
+#if !defined(_FROM_ASM_)
+
+#if CH_CFG_ST_TIMEDELTA > 0
+#if PORT_USE_ALT_TIMER == FALSE
+#include "chcore_timer.h"
+#else /* PORT_USE_ALT_TIMER != FALSE */
+#include "chcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER != FALSE */
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
-#endif /* _FROM_ASM_ */
+#endif /* !defined(_FROM_ASM_) */
-#endif /* _CHCORE_H_ */
+#endif /* CHCORE_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_timer.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_timer.h
new file mode 100644
index 0000000000..42e4a74c32
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_timer.h
@@ -0,0 +1,124 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chcore_timer.h
+ * @brief System timer header file.
+ *
+ * @addtogroup ARMCMx_TIMER
+ * @{
+ */
+
+#ifndef CHCORE_TIMER_H
+#define CHCORE_TIMER_H
+
+/* This is the only header in the HAL designed to be include-able alone.*/
+#include "hal_st.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_start_alarm(systime_t time) {
+
+ stStartAlarm(time);
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void port_timer_stop_alarm(void) {
+
+ stStopAlarm();
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_set_alarm(systime_t time) {
+
+ stSetAlarm(time);
+}
+
+/**
+ * @brief Returns the system time.
+ *
+ * @return The system time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_time(void) {
+
+ return stGetCounter();
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_alarm(void) {
+
+ return stGetAlarm();
+}
+
+#endif /* CHCORE_TIMER_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v6m.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v6m.c
new file mode 100644
index 0000000000..159363584a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v6m.c
@@ -0,0 +1,147 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chcore_v6m.c
+ * @brief ARMv6-M architecture port code.
+ *
+ * @addtogroup ARMCMx_V6M_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers. */
+/*===========================================================================*/
+
+#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__)
+/**
+ * @brief NMI vector.
+ * @details The NMI vector is used for exception mode re-entering after a
+ * context switch.
+ */
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void NMI_Handler(void) {
+/*lint -restore*/
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ ctxp++;
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+
+ /* Restoring the normal interrupts status.*/
+ port_unlock_from_isr();
+}
+#endif /* !CORTEX_ALTERNATE_SWITCH */
+
+#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ * context switch.
+ */
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void PendSV_Handler(void) {
+/*lint -restore*/
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ ctxp++;
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+}
+#endif /* CORTEX_ALTERNATE_SWITCH */
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief IRQ epilogue code.
+ *
+ * @param[in] lr value of the @p LR register on ISR entry
+ */
+void _port_irq_epilogue(regarm_t lr) {
+
+ if (lr != (regarm_t)0xFFFFFFF1U) {
+ struct port_extctx *ctxp;
+
+ port_lock_from_isr();
+
+ /* The extctx structure is pointed by the PSP register.*/
+ ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Adding an artificial exception return context, there is no need to
+ populate it fully.*/
+ ctxp--;
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+
+ /* Setting up a fake XPSR register value.*/
+ ctxp->xpsr = (regarm_t)0x01000000;
+
+ /* The exit sequence is different depending on if a preemption is
+ required or not.*/
+ if (chSchIsPreemptionRequired()) {
+ /* Preemption is required we need to enforce a context switch.*/
+ ctxp->pc = (regarm_t)_port_switch_from_isr;
+ }
+ else {
+ /* Preemption not required, we just need to exit the exception
+ atomically.*/
+ ctxp->pc = (regarm_t)_port_exit_from_isr;
+ }
+
+ /* Note, returning without unlocking is intentional, this is done in
+ order to keep the rest of the context switch atomic.*/
+ }
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v6m.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v6m.h
similarity index 56%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v6m.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v6m.h
index 3047c45c90..0ed3994032 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v6m.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v6m.h
@@ -1,45 +1,65 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
- This file is part of ChibiOS/RT.
+ This file is part of ChibiOS.
- ChibiOS/RT is free software; you can redistribute it and/or modify
+ ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
- ChibiOS/RT is distributed in the hope that it will be useful,
+ ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
*/
/**
- * @file GCC/ARMCMx/chcore_v6m.h
+ * @file chcore_v6m.h
* @brief ARMv6-M architecture port macros and structures.
*
* @addtogroup ARMCMx_V6M_CORE
* @{
*/
-#ifndef _CHCORE_V6M_H_
-#define _CHCORE_V6M_H_
+#ifndef CHCORE_V6M_H
+#define CHCORE_V6M_H
/*===========================================================================*/
-/* Port constants. */
+/* Module constants. */
/*===========================================================================*/
+/**
+ * @name Port Capabilities and Constants
+ * @{
+ */
+/**
+ * @brief This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT FALSE
+
+/**
+ * @brief Natural alignment constant.
+ * @note It is the minimum alignment for pointer-size variables.
+ */
+#define PORT_NATURAL_ALIGN sizeof (void *)
+
+/**
+ * @brief Stack alignment constant.
+ * @note It is the alignement required for the stack pointer.
+ */
+#define PORT_STACK_ALIGN sizeof (stkalign_t)
+
+/**
+ * @brief Working Areas alignment constant.
+ * @note It is the alignment to be enforced for thread working areas.
+ */
+#define PORT_WORKING_AREA_ALIGN PORT_STACK_ALIGN
+/** @} */
+
/**
* @brief PendSV priority level.
* @note This priority is enforced to be equal to @p 0,
@@ -49,11 +69,7 @@
#define CORTEX_PRIORITY_PENDSV 0
/*===========================================================================*/
-/* Port macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters. */
+/* Module pre-compile time settings. */
/*===========================================================================*/
/**
@@ -89,18 +105,6 @@
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
-/**
- * @brief SYSTICK handler priority.
- * @note The default SYSTICK handler priority is calculated as the priority
- * level in the middle of the numeric priorities range.
- */
-#if !defined(CORTEX_PRIORITY_SYSTICK)
-#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
-
/**
* @brief Alternate preemption method.
* @details Activating this option will make the Kernel use the PendSV
@@ -111,68 +115,73 @@
#endif
/*===========================================================================*/
-/* Port derived parameters. */
+/* Derived constants and error checks. */
/*===========================================================================*/
-/**
- * @brief Maximum usable priority for normal ISRs.
- */
-#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define CORTEX_MAX_KERNEL_PRIORITY 1
-#else
-#define CORTEX_MAX_KERNEL_PRIORITY 0
+#if !defined(CH_CUSTOMER_LIC_PORT_CM0)
+#error "CH_CUSTOMER_LIC_PORT_CM0 not defined"
#endif
-/*===========================================================================*/
-/* Port exported info. */
-/*===========================================================================*/
+#if CH_CUSTOMER_LIC_PORT_CM0 == FALSE
+#error "ChibiOS Cortex-M0 port not licensed"
+#endif
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) || \
+ defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
-#define CH_ARCHITECTURE_ARM_v6M
+#define PORT_ARCHITECTURE_ARM_v6M
/**
* @brief Name of the implemented architecture.
*/
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
+#define PORT_ARCHITECTURE_NAME "ARMv6-M"
/**
* @brief Name of the architecture variant.
*/
-#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
-#define CH_CORE_VARIANT_NAME "Cortex-M0"
-#elif (CORTEX_MODEL == CORTEX_M1)
-#define CH_CORE_VARIANT_NAME "Cortex-M1"
+#define PORT_CORE_VARIANT_NAME "Cortex-M0"
+
+#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT)
+#define PORT_ARCHITECTURE_ARM_v6M
+#define PORT_ARCHITECTURE_NAME "ARMv6-M"
+#define PORT_CORE_VARIANT_NAME "Cortex-M0+"
#endif
/**
* @brief Port-specific information string.
*/
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define CH_PORT_INFO "Preemption through NMI"
+#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__)
+#define PORT_INFO "Preemption through NMI"
+#else
+#define PORT_INFO "Preemption through PendSV"
+#endif
+/** @} */
+
+/**
+ * @brief Maximum usable priority for normal ISRs.
+ */
+#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__)
+#define CORTEX_MAX_KERNEL_PRIORITY 1
#else
-#define CH_PORT_INFO "Preemption through PendSV"
+#define CORTEX_MAX_KERNEL_PRIORITY 0
#endif
/*===========================================================================*/
-/* Port implementation part. */
+/* Module data structures and types. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
-/**
- * @brief Generic ARM register.
- */
-typedef void *regarm_t;
-
/* The documentation of the following declarations is in chconf.h in order
to not have duplicated structure names into the documentation.*/
#if !defined(__DOXYGEN__)
-
-typedef uint64_t stkalign_t __attribute__ ((aligned (8)));
-
-struct extctx {
+struct port_extctx {
regarm_t r0;
regarm_t r1;
regarm_t r2;
@@ -183,7 +192,7 @@ struct extctx {
regarm_t xpsr;
};
-struct intctx {
+struct port_intctx {
regarm_t r8;
regarm_t r9;
regarm_t r10;
@@ -194,60 +203,59 @@ struct intctx {
regarm_t r7;
regarm_t lr;
};
-
#endif /* !defined(__DOXYGEN__) */
-/**
- * @brief Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- * structure representing the stack pointer at context switch time.
- */
-struct context {
- struct intctx *r13;
-};
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
/**
* @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = (void *)(pf); \
- tp->p_ctx.r13->r5 = (void *)(arg); \
- tp->p_ctx.r13->lr = (void *)(_port_thread_start); \
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
+ (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
+ sizeof (struct port_intctx)); \
+ (tp)->ctx.sp->r4 = (regarm_t)(pf); \
+ (tp)->ctx.sp->r5 = (regarm_t)(arg); \
+ (tp)->ctx.sp->lr = (regarm_t)_port_thread_start; \
}
-/**
- * @brief Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
/**
* @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
*/
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- sizeof(struct intctx) + \
- sizeof(struct extctx) + \
- (n) + (PORT_INT_REQUIRED_STACK))
+#define PORT_WA_SIZE(n) (sizeof (struct port_intctx) + \
+ sizeof (struct port_extctx) + \
+ ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK)))
/**
* @brief Static working area allocation.
* @details This macro is used to allocate a static thread working area
* aligned as both position and size.
+ *
+ * @param[in] s the name to be assigned to the stack array
+ * @param[in] n the stack size to be assigned to the thread
*/
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
+#define PORT_WORKING_AREA(s, n) \
+ stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_IRQ_PROLOGUE() \
+ regarm_t _saved_lr = (regarm_t)__builtin_return_address(0)
+#elif defined(__ICCARM__)
#define PORT_IRQ_PROLOGUE() \
- regarm_t _saved_lr; \
- asm volatile ("mov %0, lr" : "=r" (_saved_lr) : : "memory")
+ regarm_t _saved_lr = (regarm_t)__get_LR()
+#elif defined(__CC_ARM)
+#define PORT_IRQ_PROLOGUE() \
+ regarm_t _saved_lr = (regarm_t)__return_address()
+#endif
/**
* @brief IRQ epilogue code.
@@ -270,63 +278,153 @@ struct context {
*/
#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects directly the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) { \
+ struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
+ if ((stkalign_t *)(r13 - 1) < (otp)->wabase) { \
+ chSysHalt("stack overflow"); \
+ } \
+ _port_switch(ntp, otp); \
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_irq_epilogue(regarm_t lr);
+ void _port_switch(thread_t *ntp, thread_t *otp);
+ void _port_thread_start(void);
+ void _port_switch_from_isr(void);
+ void _port_exit_from_isr(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
/**
* @brief Port-related initialization code.
*/
-#define port_init() { \
- SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
- nvicSetSystemHandlerPriority(HANDLER_PENDSV, \
- CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
- nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \
- CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
+static inline void port_init(void) {
+
+ NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
+}
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+ return (syssts_t)__get_PRIMASK();
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retval false the word specified a disabled interrupts status.
+ * @retval true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+ return (sts & (syssts_t)1) == (syssts_t)0;
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+ return (bool)((__get_IPSR() & 0x1FFU) != 0U);
}
/**
* @brief Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- * more actions.
+ * @details In this port this function disables interrupts globally.
*/
-#define port_lock() asm volatile ("cpsid i" : : : "memory")
+static inline void port_lock(void) {
+
+ __disable_irq();
+}
/**
* @brief Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- * more actions.
+ * @details In this port this function enables interrupts globally.
*/
-#define port_unlock() asm volatile ("cpsie i" : : : "memory")
+static inline void port_unlock(void) {
+
+ __enable_irq();
+}
/**
* @brief Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- * interrupt handlers. The implementation is architecture dependent,
- * in its simplest form it is void.
+ * @details In this port this function disables interrupts globally.
* @note Same as @p port_lock() in this port.
*/
-#define port_lock_from_isr() port_lock()
+static inline void port_lock_from_isr(void) {
+
+ port_lock();
+}
/**
* @brief Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- * handlers. The implementation is architecture dependent, in its
- * simplest form it is void.
+ * @details In this port this function enables interrupts globally.
* @note Same as @p port_lock() in this port.
*/
-#define port_unlock_from_isr() port_unlock()
+static inline void port_unlock_from_isr(void) {
+
+ port_unlock();
+}
/**
* @brief Disables all the interrupt sources.
*/
-#define port_disable() asm volatile ("cpsid i" : : : "memory")
+static inline void port_disable(void) {
+
+ __disable_irq();
+}
/**
* @brief Disables the interrupt sources below kernel-level priority.
*/
-#define port_suspend() asm volatile ("cpsid i" : : : "memory")
+static inline void port_suspend(void) {
+
+ __disable_irq();
+}
/**
* @brief Enables all the interrupt sources.
*/
-#define port_enable() asm volatile ("cpsie i" : : : "memory")
+static inline void port_enable(void) {
+
+ __enable_irq();
+}
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
@@ -336,48 +434,15 @@ struct context {
* modes.
* @note Implemented as an inlined @p WFI instruction.
*/
-#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() asm volatile ("wfi" : : : "memory")
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- * is responsible for the context switch between 2 threads.
- * @note The implementation of this code affects directly the context
- * switch performance so optimize here as much as you can.
- *
- * @param[in] ntp the thread to be switched in
- * @param[in] otp the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) { \
- register struct intctx *r13 asm ("r13"); \
- if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \
- chDbgPanic("stack overflow"); \
- _port_switch(ntp, otp); \
-}
-#endif
+static inline void port_wait_for_interrupt(void) {
-#ifdef __cplusplus
-extern "C" {
+#if CORTEX_ENABLE_WFI_IDLE == TRUE
+ __WFI();
#endif
- void port_halt(void);
- void _port_irq_epilogue(regarm_t lr);
- void _port_switch_from_isr(void);
- void _port_exit_from_isr(void);
- void _port_switch(Thread *ntp, Thread *otp);
- void _port_thread_start(void);
-#ifdef __cplusplus
}
-#endif
#endif /* _FROM_ASM_ */
-#endif /* _CHCORE_V6M_H_ */
+#endif /* CHCORE_V6M_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v7m.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v7m.c
new file mode 100644
index 0000000000..b492a3e987
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v7m.c
@@ -0,0 +1,168 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chcore_v7m.c
+ * @brief ARMv7-M architecture port code.
+ *
+ * @addtogroup ARMCMx_V7M_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers. */
+/*===========================================================================*/
+
+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
+/**
+ * @brief SVC vector.
+ * @details The SVC vector is used for exception mode re-entering after a
+ * context switch.
+ * @note The PendSV vector is only used in advanced kernel mode.
+ */
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void SVC_Handler(void) {
+/*lint -restore*/
+ struct port_extctx *ctxp;
+
+#if CORTEX_USE_FPU
+ /* Enforcing unstacking of the FP part of the context.*/
+ FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk;
+#endif
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ ctxp++;
+
+ /* Restoring real position of the original stack frame.*/
+ __set_PSP((uint32_t)ctxp);
+
+ /* Restoring the normal interrupts status.*/
+ port_unlock_from_isr();
+}
+#endif /* CORTEX_SIMPLIFIED_PRIORITY == FALSE */
+
+#if (CORTEX_SIMPLIFIED_PRIORITY == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ * context switch.
+ * @note The PendSV vector is only used in compact kernel mode.
+ */
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void PendSV_Handler(void) {
+/*lint -restore*/
+ struct port_extctx *ctxp;
+
+#if CORTEX_USE_FPU
+ /* Enforcing unstacking of the FP part of the context.*/
+ FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk;
+#endif
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ ctxp++;
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+}
+#endif /* CORTEX_SIMPLIFIED_PRIORITY == TRUE */
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Exception exit redirection to _port_switch_from_isr().
+ */
+void _port_irq_epilogue(void) {
+
+ port_lock_from_isr();
+ if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0U) {
+ struct port_extctx *ctxp;
+
+#if CORTEX_USE_FPU == TRUE
+ /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/
+ (void) __get_FPSCR();
+#endif
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Adding an artificial exception return context, there is no need to
+ populate it fully.*/
+ ctxp--;
+
+ /* Setting up a fake XPSR register value.*/
+ ctxp->xpsr = (regarm_t)0x01000000;
+#if CORTEX_USE_FPU == TRUE
+ ctxp->fpscr = (regarm_t)FPU->FPDSCR;
+#endif
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+
+ /* The exit sequence is different depending on if a preemption is
+ required or not.*/
+ if (chSchIsPreemptionRequired()) {
+ /* Preemption is required we need to enforce a context switch.*/
+ ctxp->pc = (regarm_t)_port_switch_from_isr;
+ }
+ else {
+ /* Preemption not required, we just need to exit the exception
+ atomically.*/
+ ctxp->pc = (regarm_t)_port_exit_from_isr;
+ }
+
+ /* Note, returning without unlocking is intentional, this is done in
+ order to keep the rest of the context switch atomic.*/
+ return;
+ }
+ port_unlock_from_isr();
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v7m.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v7m.h
new file mode 100644
index 0000000000..9482898b2d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/chcore_v7m.h
@@ -0,0 +1,715 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chcore_v7m.h
+ * @brief ARMv7-M architecture port macros and structures.
+ *
+ * @addtogroup ARMCMx_V7M_CORE
+ * @{
+ */
+
+#ifndef CHCORE_V7M_H
+#define CHCORE_V7M_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Port Capabilities and Constants
+ * @{
+ */
+/**
+ * @brief This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT TRUE
+
+/**
+ * @brief Natural alignment constant.
+ * @note It is the minimum alignment for pointer-size variables.
+ */
+#define PORT_NATURAL_ALIGN sizeof (void *)
+
+/**
+ * @brief Stack alignment constant.
+ * @note It is the alignement required for the stack pointer.
+ */
+#define PORT_STACK_ALIGN sizeof (stkalign_t)
+
+/**
+ * @brief Working Areas alignment constant.
+ * @note It is the alignment to be enforced for thread working areas.
+ */
+#define PORT_WORKING_AREA_ALIGN (PORT_ENABLE_GUARD_PAGES == TRUE ? \
+ 32U : PORT_STACK_ALIGN)
+/** @} */
+
+/**
+ * @brief Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED 0U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables stack overflow guard pages using MPU.
+ * @note This option can only be enabled if also option
+ * @p CH_DBG_ENABLE_STACK_CHECK is enabled.
+ * @note The use of this option has an overhead of 32 bytes for each
+ * thread.
+ */
+#if !defined(PORT_ENABLE_GUARD_PAGES) || defined(__DOXYGEN__)
+#define PORT_ENABLE_GUARD_PAGES FALSE
+#endif
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 16 because the idle thread does have
+ * a stack frame when compiling without optimizations. You may
+ * reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE 16
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * @note In this port this value is conservatively set to 64 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK 64
+#endif
+
+/**
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
+ */
+#if !defined(CORTEX_ENABLE_WFI_IDLE)
+#define CORTEX_ENABLE_WFI_IDLE FALSE
+#endif
+
+/**
+ * @brief FPU support in context switch.
+ * @details Activating this option activates the FPU support in the kernel.
+ */
+#if !defined(CORTEX_USE_FPU)
+#define CORTEX_USE_FPU CORTEX_HAS_FPU
+#elif (CORTEX_USE_FPU == TRUE) && (CORTEX_HAS_FPU == FALSE)
+/* This setting requires an FPU presence check in case it is externally
+ redefined.*/
+#error "the selected core does not have an FPU"
+#endif
+
+/**
+ * @brief Simplified priority handling flag.
+ * @details Activating this option makes the Kernel work in compact mode.
+ * In compact mode interrupts are disabled globally instead of
+ * raising the priority mask to some intermediate level.
+ */
+#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
+#define CORTEX_SIMPLIFIED_PRIORITY FALSE
+#endif
+
+/**
+ * @brief SVCALL handler priority.
+ * @note The default SVCALL handler priority is defaulted to
+ * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
+ * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
+ * priority level.
+ */
+#if !defined(CORTEX_PRIORITY_SVCALL)
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1U)
+#elif !PORT_IRQ_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
+/* If it is externally redefined then better perform a validity check on it.*/
+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
+#endif
+
+/**
+ * @brief NVIC PRIGROUP initialization expression.
+ * @details The default assigns all available priority bits as preemption
+ * priority with no sub-priority.
+ */
+#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
+#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+/**
+ * @brief MPU guard page size.
+ */
+#if (PORT_ENABLE_GUARD_PAGES == TRUE) || defined(__DOXYGEN__)
+ #if CH_DBG_ENABLE_STACK_CHECK == FALSE
+ #error "PORT_ENABLE_GUARD_PAGES requires CH_DBG_ENABLE_STACK_CHECK"
+ #endif
+ #if __MPU_PRESENT == 0
+ #error "MPU not present in current device"
+ #endif
+ #define PORT_GUARD_PAGE_SIZE 32U
+#else
+ #define PORT_GUARD_PAGE_SIZE 0U
+#endif
+#endif /* !defined(_FROM_ASM_) */
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+#if (CORTEX_MODEL == 3) || defined(__DOXYGEN__)
+
+ #if !defined(CH_CUSTOMER_LIC_PORT_CM3)
+ #error "CH_CUSTOMER_LIC_PORT_CM3 not defined"
+ #endif
+
+ #if CH_CUSTOMER_LIC_PORT_CM3 == FALSE
+ #error "ChibiOS Cortex-M3 port not licensed"
+ #endif
+
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM_v7M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME "ARMv7-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#if (PORT_ENABLE_GUARD_PAGES == FALSE) || defined(__DOXYGEN__)
+ #define PORT_CORE_VARIANT_NAME "Cortex-M3"
+#else
+ #define PORT_CORE_VARIANT_NAME "Cortex-M3 (MPU)"
+#endif
+
+#elif (CORTEX_MODEL == 4)
+
+ #if !defined(CH_CUSTOMER_LIC_PORT_CM4)
+ #error "CH_CUSTOMER_LIC_PORT_CM4 not defined"
+ #endif
+
+ #if CH_CUSTOMER_LIC_PORT_CM4 == FALSE
+ #error "ChibiOS Cortex-M4 port not licensed"
+ #endif
+
+ #define PORT_ARCHITECTURE_ARM_v7ME
+ #define PORT_ARCHITECTURE_NAME "ARMv7E-M"
+ #if CORTEX_USE_FPU
+ #if PORT_ENABLE_GUARD_PAGES == FALSE
+ #define PORT_CORE_VARIANT_NAME "Cortex-M4F"
+ #else
+ #define PORT_CORE_VARIANT_NAME "Cortex-M4F (MPU)"
+ #endif
+ #else
+ #if PORT_ENABLE_GUARD_PAGES == FALSE
+ #define PORT_CORE_VARIANT_NAME "Cortex-M4"
+ #else
+ #define PORT_CORE_VARIANT_NAME "Cortex-M4 (MPU)"
+ #endif
+ #endif
+
+#elif (CORTEX_MODEL == 7)
+
+ #if !defined(CH_CUSTOMER_LIC_PORT_CM7)
+ #error "CH_CUSTOMER_LIC_PORT_CM7 not defined"
+ #endif
+
+ #if CH_CUSTOMER_LIC_PORT_CM7 == FALSE
+ #error "ChibiOS Cortex-M7 port not licensed"
+ #endif
+
+#define PORT_ARCHITECTURE_ARM_v7ME
+ #define PORT_ARCHITECTURE_NAME "ARMv7E-M"
+ #if CORTEX_USE_FPU
+ #if PORT_ENABLE_GUARD_PAGES == FALSE
+ #define PORT_CORE_VARIANT_NAME "Cortex-M7F"
+ #else
+ #define PORT_CORE_VARIANT_NAME "Cortex-M7F (MPU)"
+ #endif
+ #else
+ #if PORT_ENABLE_GUARD_PAGES == FALSE
+ #define PORT_CORE_VARIANT_NAME "Cortex-M7"
+ #else
+ #define PORT_CORE_VARIANT_NAME "Cortex-M7 (MPU)"
+ #endif
+ #endif
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
+#define PORT_INFO "Advanced kernel mode"
+#else
+#define PORT_INFO "Compact kernel mode"
+#endif
+/** @} */
+
+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
+/**
+ * @brief Maximum usable priority for normal ISRs.
+ */
+#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1U)
+
+/**
+ * @brief BASEPRI level within kernel lock.
+ */
+#define CORTEX_BASEPRI_KERNEL \
+ CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
+#else
+
+#define CORTEX_MAX_KERNEL_PRIORITY 0U
+#endif
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to
+ * @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
+ * highest priority that cannot preempt the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* The documentation of the following declarations is in chconf.h in order
+ to not have duplicated structure names into the documentation.*/
+#if !defined(__DOXYGEN__)
+struct port_extctx {
+ regarm_t r0;
+ regarm_t r1;
+ regarm_t r2;
+ regarm_t r3;
+ regarm_t r12;
+ regarm_t lr_thd;
+ regarm_t pc;
+ regarm_t xpsr;
+#if CORTEX_USE_FPU
+ regarm_t s0;
+ regarm_t s1;
+ regarm_t s2;
+ regarm_t s3;
+ regarm_t s4;
+ regarm_t s5;
+ regarm_t s6;
+ regarm_t s7;
+ regarm_t s8;
+ regarm_t s9;
+ regarm_t s10;
+ regarm_t s11;
+ regarm_t s12;
+ regarm_t s13;
+ regarm_t s14;
+ regarm_t s15;
+ regarm_t fpscr;
+ regarm_t reserved;
+#endif /* CORTEX_USE_FPU */
+};
+
+struct port_intctx {
+#if CORTEX_USE_FPU
+ regarm_t s16;
+ regarm_t s17;
+ regarm_t s18;
+ regarm_t s19;
+ regarm_t s20;
+ regarm_t s21;
+ regarm_t s22;
+ regarm_t s23;
+ regarm_t s24;
+ regarm_t s25;
+ regarm_t s26;
+ regarm_t s27;
+ regarm_t s28;
+ regarm_t s29;
+ regarm_t s30;
+ regarm_t s31;
+#endif /* CORTEX_USE_FPU */
+ regarm_t r4;
+ regarm_t r5;
+ regarm_t r6;
+ regarm_t r7;
+ regarm_t r8;
+ regarm_t r9;
+ regarm_t r10;
+ regarm_t r11;
+ regarm_t lr;
+};
+#endif /* !defined(__DOXYGEN__) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
+ (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
+ sizeof (struct port_intctx)); \
+ (tp)->ctx.sp->r4 = (regarm_t)(pf); \
+ (tp)->ctx.sp->r5 = (regarm_t)(arg); \
+ (tp)->ctx.sp->lr = (regarm_t)_port_thread_start; \
+}
+
+/**
+ * @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) ((size_t)PORT_GUARD_PAGE_SIZE + \
+ sizeof (struct port_intctx) + \
+ sizeof (struct port_extctx) + \
+ (size_t)(n) + \
+ (size_t)PORT_INT_REQUIRED_STACK)
+
+/**
+ * @brief Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ * aligned as both position and size.
+ *
+ * @param[in] s the name to be assigned to the stack array
+ * @param[in] n the stack size to be assigned to the thread
+ */
+#if (PORT_ENABLE_GUARD_PAGES == FALSE) || defined(__DOXYGEN__)
+#define PORT_WORKING_AREA(s, n) \
+ stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
+#else
+#define PORT_WORKING_AREA(s, n) \
+ ALIGNED_VAR(32) stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
+#endif
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects directly the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#if PORT_ENABLE_GUARD_PAGES == FALSE
+#define port_switch(ntp, otp) { \
+ struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
+ if ((stkalign_t *)(r13 - 1) < (otp)->wabase) { \
+ chSysHalt("stack overflow"); \
+ } \
+ _port_switch(ntp, otp); \
+}
+#else
+#define port_switch(ntp, otp) { \
+ _port_switch(ntp, otp); \
+ \
+ /* Setting up the guard page for the switched-in thread.*/ \
+ mpuConfigureRegion(MPU_REGION_0, \
+ chThdGetSelfX()->wabase, \
+ MPU_RASR_ATTR_AP_NA_NA | \
+ MPU_RASR_ATTR_NON_CACHEABLE | \
+ MPU_RASR_SIZE_32 | \
+ MPU_RASR_ENABLE); \
+}
+#endif
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_irq_epilogue(void);
+ void _port_switch(thread_t *ntp, thread_t *otp);
+ void _port_thread_start(void);
+ void _port_switch_from_isr(void);
+ void _port_exit_from_isr(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+ /* Initializing priority grouping.*/
+ NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
+
+ /* DWT cycle counter enable, note, the M7 requires DWT unlocking.*/
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+#if CORTEX_MODEL == 7
+ DWT->LAR = 0xC5ACCE55U;
+#endif
+ DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+
+ /* Initialization of the system vectors used by the port.*/
+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
+ NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);
+#endif
+ NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
+
+#if PORT_ENABLE_GUARD_PAGES == TRUE
+ {
+ extern stkalign_t __main_thread_stack_base__;
+
+ /* Setting up the guard page on the main() function stack base
+ initially.*/
+ mpuConfigureRegion(MPU_REGION_0,
+ &__main_thread_stack_base__,
+ MPU_RASR_ATTR_AP_NA_NA |
+ MPU_RASR_ATTR_NON_CACHEABLE |
+ MPU_RASR_SIZE_32 |
+ MPU_RASR_ENABLE);
+
+ /* MPU is enabled.*/
+ mpuEnable(MPU_CTRL_PRIVDEFENA);
+ }
+#endif
+}
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+ syssts_t sts;
+
+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
+ sts = (syssts_t)__get_BASEPRI();
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ sts = (syssts_t)__get_PRIMASK();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+ return sts;
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retval false the word specified a disabled interrupts status.
+ * @retval true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
+ return sts == (syssts_t)CORTEX_BASEPRI_DISABLED;
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ return (sts & (syssts_t)1) == (syssts_t)0;
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+ return (bool)((__get_IPSR() & 0x1FFU) != 0U);
+}
+
+/**
+ * @brief Kernel-lock action.
+ * @details In this port this function raises the base priority to kernel
+ * level.
+ */
+static inline void port_lock(void) {
+
+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
+#if defined(__CM7_REV)
+#if __CM7_REV <= 1
+ __disable_irq();
+#endif
+#endif
+ __set_BASEPRI(CORTEX_BASEPRI_KERNEL);
+#if defined(__CM7_REV)
+#if __CM7_REV <= 1
+ __enable_irq();
+#endif
+#endif
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ __disable_irq();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief Kernel-unlock action.
+ * @details In this port this function lowers the base priority to user
+ * level.
+ */
+static inline void port_unlock(void) {
+
+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
+ __set_BASEPRI(CORTEX_BASEPRI_DISABLED);
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ __enable_irq();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @details In this port this function raises the base priority to kernel
+ * level.
+ * @note Same as @p port_lock() in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+ port_lock();
+}
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @details In this port this function lowers the base priority to user
+ * level.
+ * @note Same as @p port_unlock() in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+ port_unlock();
+}
+
+/**
+ * @brief Disables all the interrupt sources.
+ * @note In this port it disables all the interrupt sources by raising
+ * the priority mask to level 0.
+ */
+static inline void port_disable(void) {
+
+ __disable_irq();
+}
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ * @note Interrupt sources above kernel level remains enabled.
+ * @note In this port it raises/lowers the base priority to kernel level.
+ */
+static inline void port_suspend(void) {
+
+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
+ __set_BASEPRI(CORTEX_BASEPRI_KERNEL);
+ __enable_irq();
+#else
+ __disable_irq();
+#endif
+}
+
+/**
+ * @brief Enables all the interrupt sources.
+ * @note In this port it lowers the base priority to user level.
+ */
+static inline void port_enable(void) {
+
+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
+ __set_BASEPRI(CORTEX_BASEPRI_DISABLED);
+#endif
+ __enable_irq();
+}
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ * @note Implemented as an inlined @p WFI instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if CORTEX_ENABLE_WFI_IDLE == TRUE
+ __WFI();
+#endif
+}
+
+/**
+ * @brief Returns the current value of the realtime counter.
+ *
+ * @return The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+ return DWT->CYCCNT;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CHCORE_V7M_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S
new file mode 100644
index 0000000000..cf5212fc4e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S
@@ -0,0 +1,159 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file compilers/GCC/chcoreasm_v6m.S
+ * @brief ARMv6-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define _FROM_ASM_
+#include "chlicense.h"
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+/*
+ * RTOS-specific context offset.
+ */
+#if defined(_CHIBIOS_RT_CONF_)
+#define CONTEXT_OFFSET 12
+#elif defined(_CHIBIOS_NIL_CONF_)
+#define CONTEXT_OFFSET 0
+#else
+#error "invalid chconf.h"
+#endif
+
+ .set SCB_ICSR, 0xE000ED04
+ .set ICSR_PENDSVSET, 0x10000000
+ .set ICSR_NMIPENDSET, 0x80000000
+
+ .cpu cortex-m0
+ .fpu softvfp
+
+ .thumb
+ .text
+
+/*--------------------------------------------------------------------------*
+ * Performs a context switch between two threads.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_switch
+_port_switch:
+ push {r4, r5, r6, r7, lr}
+ mov r4, r8
+ mov r5, r9
+ mov r6, r10
+ mov r7, r11
+ push {r4, r5, r6, r7}
+
+ mov r3, sp
+ str r3, [r1, #CONTEXT_OFFSET]
+ ldr r3, [r0, #CONTEXT_OFFSET]
+ mov sp, r3
+
+ pop {r4, r5, r6, r7}
+ mov r8, r4
+ mov r9, r5
+ mov r10, r6
+ mov r11, r7
+ pop {r4, r5, r6, r7, pc}
+
+/*--------------------------------------------------------------------------*
+ * Start a thread by invoking its work function.
+ *
+ * Threads execution starts here, the code leaves the system critical zone
+ * and then jumps into the thread function passed in register R4. The
+ * register R5 contains the thread parameter. The function chThdExit() is
+ * called on thread function return.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+ cpsie i
+ mov r0, r5
+ blx r4
+#if defined(_CHIBIOS_RT_CONF_)
+ movs r0, #0 /* MSG_OK */
+ bl chThdExit
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
+ mov r3, #0
+ bl chSysHalt
+#endif
+
+/*--------------------------------------------------------------------------*
+ * Post-IRQ switch code.
+ *
+ * Exception handlers return here for context switching.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_switch_from_isr
+_port_switch_from_isr:
+#if CH_DBG_STATISTICS
+ bl _stats_start_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+ .globl _port_exit_from_isr
+_port_exit_from_isr:
+ ldr r2, .L2
+ ldr r3, .L3
+ str r3, [r2, #0]
+#if CORTEX_ALTERNATE_SWITCH
+ cpsie i
+#endif
+.L1: b .L1
+
+ .align 2
+.L2: .word SCB_ICSR
+#if CORTEX_ALTERNATE_SWITCH
+.L3: .word ICSR_PENDSVSET
+#else
+.L3: .word ICSR_NMIPENDSET
+#endif
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S
new file mode 100644
index 0000000000..09394fa133
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S
@@ -0,0 +1,165 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file compilers/GCC/chcoreasm_v7m.S
+ * @brief ARMv7-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define _FROM_ASM_
+#include "chlicense.h"
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+/*
+ * RTOS-specific context offset.
+ */
+#if defined(_CHIBIOS_RT_CONF_)
+#define CONTEXT_OFFSET 12
+#elif defined(_CHIBIOS_NIL_CONF_)
+#define CONTEXT_OFFSET 0
+#else
+#error "invalid chconf.h"
+#endif
+
+ .set SCB_ICSR, 0xE000ED04
+ .set ICSR_PENDSVSET, 0x10000000
+
+ .syntax unified
+ .cpu cortex-m4
+#if CORTEX_USE_FPU
+ .fpu fpv4-sp-d16
+#else
+ .fpu softvfp
+#endif
+
+ .thumb
+ .text
+
+/*--------------------------------------------------------------------------*
+ * Performs a context switch between two threads.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_switch
+_port_switch:
+ push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+ vpush {s16-s31}
+#endif
+
+ str sp, [r1, #CONTEXT_OFFSET]
+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \
+ ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4))
+ /* Workaround for ARM errata 752419, only applied if
+ condition exists for it to be triggered.*/
+ ldr r3, [r0, #CONTEXT_OFFSET]
+ mov sp, r3
+#else
+ ldr sp, [r0, #CONTEXT_OFFSET]
+#endif
+
+#if CORTEX_USE_FPU
+ vpop {s16-s31}
+#endif
+ pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+
+/*--------------------------------------------------------------------------*
+ * Start a thread by invoking its work function.
+ *
+ * Threads execution starts here, the code leaves the system critical zone
+ * and then jumps into the thread function passed in register R4. The
+ * register R5 contains the thread parameter. The function chThdExit() is
+ * called on thread function return.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+#if CORTEX_SIMPLIFIED_PRIORITY
+ cpsie i
+#else
+ movs r3, #0 /* CORTEX_BASEPRI_DISABLED */
+ msr BASEPRI, r3
+#endif
+ mov r0, r5
+ blx r4
+#if defined(_CHIBIOS_RT_CONF_)
+ movs r0, #0 /* MSG_OK */
+ bl chThdExit
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
+ mov r3, #0
+ bl chSysHalt
+#endif
+
+/*--------------------------------------------------------------------------*
+ * Post-IRQ switch code.
+ *
+ * Exception handlers return here for context switching.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_switch_from_isr
+_port_switch_from_isr:
+#if CH_DBG_STATISTICS
+ bl _stats_start_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+ .globl _port_exit_from_isr
+_port_exit_from_isr:
+#if CORTEX_SIMPLIFIED_PRIORITY
+ movw r3, #:lower16:SCB_ICSR
+ movt r3, #:upper16:SCB_ICSR
+ mov r2, ICSR_PENDSVSET
+ str r2, [r3, #0]
+ cpsie i
+#else /* !CORTEX_SIMPLIFIED_PRIORITY */
+ svc #0
+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
+.L1: b .L1
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chtypes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chtypes.h
new file mode 100644
index 0000000000..06bad63e4f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chtypes.h
@@ -0,0 +1,115 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/chtypes.h
+ * @brief ARM Cortex-Mx port system types.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#ifndef CHTYPES_H
+#define CHTYPES_H
+
+#include
+#include
+#include
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+/** @} */
+
+/**
+ * @name Kernel types
+ * @{
+ */
+typedef uint32_t rtcnt_t; /**< Realtime counter. */
+typedef uint64_t rttime_t; /**< Realtime accumulator. */
+typedef uint32_t syssts_t; /**< System status word. */
+typedef uint8_t tmode_t; /**< Thread flags. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef uint8_t trefs_t; /**< Thread references counter. */
+typedef uint8_t tslices_t; /**< Thread time slices counter.*/
+typedef uint32_t tprio_t; /**< Thread priority. */
+typedef int32_t msg_t; /**< Inter-thread message. */
+typedef int32_t eventid_t; /**< Numeric event identifier. */
+typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
+typedef uint32_t eventflags_t; /**< Mask of event flags. */
+typedef int32_t cnt_t; /**< Generic signed counter. */
+typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
+/** @} */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then some
+ * time-dependent services could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+/**
+ * @brief Memory alignment enforcement for variables.
+ */
+#define ALIGNED_VAR(n) __attribute__((aligned(n)))
+
+/**
+ * @brief Size of a pointer.
+ * @note To be used where the sizeof operator cannot be used, preprocessor
+ * expressions for example.
+ */
+#define SIZEOF_PTR 4
+
+/**
+ * @brief True if alignment is low-high in current architecture.
+ */
+#define REVERSE_ORDER 1
+
+#endif /* CHTYPES_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
new file mode 100644
index 0000000000..029990813f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
@@ -0,0 +1,8 @@
+# List of the ChibiOS/RT Cortex-M0 STM32F0xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/chcore.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/chcore_v6m.c
+
+PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S
+
+PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
new file mode 100644
index 0000000000..2ebab97eeb
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
@@ -0,0 +1,8 @@
+# List of the ChibiOS/RT ARMv7M generic port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/chcore.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/chcore_v7m.c
+
+PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S
+
+PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s
new file mode 100644
index 0000000000..297135ca89
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s
@@ -0,0 +1,160 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file compilers/IAR/chcoreasm_v6m.s
+ * @brief ARMv6-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_IAR_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define _FROM_ASM_
+#include "chlicense.h"
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+/*
+ * RTOS-specific context offset.
+ */
+#if defined(_CHIBIOS_RT_CONF_)
+#define CONTEXT_OFFSET 12
+#elif defined(_CHIBIOS_NIL_CONF_)
+#define CONTEXT_OFFSET 0
+#else
+#error "invalid chconf.h"
+#endif
+
+ MODULE ?chcoreasm_v6m
+
+ AAPCS INTERWORK, VFP_COMPATIBLE
+ PRESERVE8
+
+SCB_ICSR SET 0xE000ED04
+
+ SECTION .text:CODE:NOROOT(2)
+
+ EXTERN chThdExit
+ EXTERN chSchDoReschedule
+#if CH_DBG_STATISTICS
+ EXTERN _stats_start_measure_crit_thd
+ EXTERN _stats_stop_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ EXTERN _dbg_check_unlock
+ EXTERN _dbg_check_lock
+#endif
+
+ THUMB
+
+/*
+ * Performs a context switch between two threads.
+ */
+ PUBLIC _port_switch
+_port_switch:
+ push {r4, r5, r6, r7, lr}
+ mov r4, r8
+ mov r5, r9
+ mov r6, r10
+ mov r7, r11
+ push {r4, r5, r6, r7}
+ mov r3, sp
+ str r3, [r1, #CONTEXT_OFFSET]
+ ldr r3, [r0, #CONTEXT_OFFSET]
+ mov sp, r3
+ pop {r4, r5, r6, r7}
+ mov r8, r4
+ mov r9, r5
+ mov r10, r6
+ mov r11, r7
+ pop {r4, r5, r6, r7, pc}
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+ PUBLIC _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+ cpsie i
+ mov r0, r5
+ blx r4
+#if defined(_CHIBIOS_RT_CONF_)
+ movs r0, #0 /* MSG_OK */
+ bl chThdExit
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
+ mov r3, #0
+ bl chSysHalt
+#endif
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+ PUBLIC _port_switch_from_isr
+ PUBLIC _port_exit_from_isr
+_port_switch_from_isr:
+#if CH_DBG_STATISTICS
+ bl _stats_start_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+_port_exit_from_isr:
+ ldr r2, =SCB_ICSR
+ movs r3, #128
+#if CORTEX_ALTERNATE_SWITCH
+ lsls r3, r3, #21
+ str r3, [r2, #0]
+ cpsie i
+#else
+ lsls r3, r3, #24
+ str r3, [r2, #0]
+#endif
+waithere:
+ b waithere
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s
new file mode 100644
index 0000000000..1875165d06
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s
@@ -0,0 +1,168 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file compilers/IAR/chcoreasm_v7m.s
+ * @brief ARMv7-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_IAR_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define _FROM_ASM_
+#include "chlicense.h"
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+/*
+ * RTOS-specific context offset.
+ */
+#if defined(_CHIBIOS_RT_CONF_)
+#define CONTEXT_OFFSET 12
+#elif defined(_CHIBIOS_NIL_CONF_)
+#define CONTEXT_OFFSET 0
+#else
+#error "invalid chconf.h"
+#endif
+
+ MODULE ?chcoreasm_v7m
+
+ AAPCS INTERWORK, VFP_COMPATIBLE
+ PRESERVE8
+
+SCB_ICSR SET 0xE000ED04
+ICSR_PENDSVSET SET 0x10000000
+
+ SECTION .text:CODE:NOROOT(2)
+
+ EXTERN chThdExit
+ EXTERN chSchDoReschedule
+#if CH_DBG_STATISTICS
+ EXTERN _stats_start_measure_crit_thd
+ EXTERN _stats_stop_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ EXTERN _dbg_check_unlock
+ EXTERN _dbg_check_lock
+#endif
+
+ THUMB
+
+/*
+ * Performs a context switch between two threads.
+ */
+ PUBLIC _port_switch
+_port_switch:
+ push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+ vpush {s16-s31}
+#endif
+
+ str sp, [r1, #CONTEXT_OFFSET]
+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \
+ ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4))
+ /* Workaround for ARM errata 752419, only applied if
+ condition exists for it to be triggered.*/
+ ldr r3, [r0, #CONTEXT_OFFSET]
+ mov sp, r3
+#else
+ ldr sp, [r0, #CONTEXT_OFFSET]
+#endif
+
+#if CORTEX_USE_FPU
+ vpop {s16-s31}
+#endif
+ pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+ PUBLIC _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+#if CORTEX_SIMPLIFIED_PRIORITY
+ cpsie i
+#else
+ movs r3, #0 /* CORTEX_BASEPRI_DISABLED */
+ msr BASEPRI, r3
+#endif
+ mov r0, r5
+ blx r4
+#if defined(_CHIBIOS_RT_CONF_)
+ movs r0, #0 /* MSG_OK */
+ bl chThdExit
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
+ mov r3, #0
+ bl chSysHalt
+#endif
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+ PUBLIC _port_switch_from_isr
+ PUBLIC _port_exit_from_isr
+_port_switch_from_isr:
+#if CH_DBG_STATISTICS
+ bl _stats_start_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+_port_exit_from_isr:
+#if CORTEX_SIMPLIFIED_PRIORITY
+ mov r3, #LWRD SCB_ICSR
+ movt r3, #HWRD SCB_ICSR
+ mov r2, #ICSR_PENDSVSET
+ str r2, [r3]
+ cpsie i
+#else
+ svc #0
+#endif
+.L3: b .L3
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chtypes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chtypes.h
new file mode 100644
index 0000000000..2a9dcc483f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/IAR/chtypes.h
@@ -0,0 +1,115 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file ARMCMx/compilers/IAR/chtypes.h
+ * @brief ARM Cortex-Mx port system types.
+ *
+ * @addtogroup ARMCMx_IAR_CORE
+ * @{
+ */
+
+#ifndef CHTYPES_H
+#define CHTYPES_H
+
+#include
+#include
+#include
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE (!FALSE)
+#endif
+/** @} */
+
+/**
+ * @name Kernel types
+ * @{
+ */
+typedef uint32_t rtcnt_t; /**< Realtime counter. */
+typedef uint64_t rttime_t; /**< Realtime accumulator. */
+typedef uint32_t syssts_t; /**< System status word. */
+typedef uint8_t tmode_t; /**< Thread flags. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef uint8_t trefs_t; /**< Thread references counter. */
+typedef uint8_t tslices_t; /**< Thread time slices counter.*/
+typedef uint32_t tprio_t; /**< Thread priority. */
+typedef int32_t msg_t; /**< Inter-thread message. */
+typedef int32_t eventid_t; /**< Numeric event identifier. */
+typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
+typedef uint32_t eventflags_t; /**< Mask of event flags. */
+typedef int32_t cnt_t; /**< Generic signed counter. */
+typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
+/** @} */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then some
+ * time-dependent services could be degraded.
+ */
+#define NOINLINE _Pragma("inline=never")
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __packed
+
+/**
+ * @brief Memory alignment enforcement for variables.
+ */
+#define ALIGNED_VAR(n) _Pragma(__CH_STRINGIFY(data_alignment=n))
+
+/**
+ * @brief Size of a pointer.
+ * @note To be used where the sizeof operator cannot be used, preprocessor
+ * expressions for example.
+ */
+#define SIZEOF_PTR 4
+
+/**
+ * @brief True if alignment is low-high in current architecture.
+ */
+#define REVERSE_ORDER 1
+
+#endif /* CHTYPES_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s
new file mode 100644
index 0000000000..b9cd6c3785
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s
@@ -0,0 +1,157 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file compilers/RVCT/chcoreasm_v6m.s
+ * @brief ARMv6-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_RVCT_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define _FROM_ASM_
+#include "chlicense.h"
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+/*
+ * RTOS-specific context offset.
+ */
+#if defined(_CHIBIOS_RT_CONF_)
+#define CONTEXT_OFFSET 12
+#elif defined(_CHIBIOS_NIL_CONF_)
+#define CONTEXT_OFFSET 0
+#else
+#error "invalid chconf.h"
+#endif
+
+SCB_ICSR EQU 0xE000ED04
+
+ PRESERVE8
+ THUMB
+ AREA |.text|, CODE, READONLY
+
+ IMPORT chThdExit
+ IMPORT chSchDoReschedule
+#if CH_DBG_STATISTICS
+ IMPORT _stats_start_measure_crit_thd
+ IMPORT _stats_stop_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ IMPORT _dbg_check_unlock
+ IMPORT _dbg_check_lock
+#endif
+
+/*
+ * Performs a context switch between two threads.
+ */
+ EXPORT _port_switch
+_port_switch PROC
+ push {r4, r5, r6, r7, lr}
+ mov r4, r8
+ mov r5, r9
+ mov r6, r10
+ mov r7, r11
+ push {r4, r5, r6, r7}
+ mov r3, sp
+ str r3, [r1, #CONTEXT_OFFSET]
+ ldr r3, [r0, #CONTEXT_OFFSET]
+ mov sp, r3
+ pop {r4, r5, r6, r7}
+ mov r8, r4
+ mov r9, r5
+ mov r10, r6
+ mov r11, r7
+ pop {r4, r5, r6, r7, pc}
+ ENDP
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+ EXPORT _port_thread_start
+_port_thread_start PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+ cpsie i
+ mov r0, r5
+ blx r4
+#if defined(_CHIBIOS_RT_CONF_)
+ movs r0, #0 /* MSG_OK */
+ bl chThdExit
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
+ mov r3, #0
+ bl chSysHalt
+#endif
+ ENDP
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+ EXPORT _port_switch_from_isr
+ EXPORT _port_exit_from_isr
+_port_switch_from_isr PROC
+#if CH_DBG_STATISTICS
+ bl _stats_start_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+_port_exit_from_isr
+ ldr r2, =SCB_ICSR
+ movs r3, #128
+#if CORTEX_ALTERNATE_SWITCH
+ lsls r3, r3, #21
+ str r3, [r2, #0]
+ cpsie i
+#else
+ lsls r3, r3, #24
+ str r3, [r2, #0]
+#endif
+waithere b waithere
+ ENDP
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s
new file mode 100644
index 0000000000..e48dd890ea
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s
@@ -0,0 +1,166 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file compilers/RVCT/chcoreasm_v7m.s
+ * @brief ARMv7-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_RVCT_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define _FROM_ASM_
+#include "chlicense.h"
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+/*
+ * RTOS-specific context offset.
+ */
+#if defined(_CHIBIOS_RT_CONF_)
+#define CONTEXT_OFFSET 12
+#elif defined(_CHIBIOS_NIL_CONF_)
+#define CONTEXT_OFFSET 0
+#else
+#error "invalid chconf.h"
+#endif
+
+SCB_ICSR EQU 0xE000ED04
+ICSR_PENDSVSET EQU 0x10000000
+
+ PRESERVE8
+ THUMB
+ AREA |.text|, CODE, READONLY
+
+ IMPORT chThdExit
+ IMPORT chSchDoReschedule
+#if CH_DBG_STATISTICS
+ IMPORT _stats_start_measure_crit_thd
+ IMPORT _stats_stop_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ IMPORT _dbg_check_unlock
+ IMPORT _dbg_check_lock
+#endif
+
+/*
+ * Performs a context switch between two threads.
+ */
+ EXPORT _port_switch
+_port_switch PROC
+ push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+ vpush {s16-s31}
+#endif
+
+ str sp, [r1, #CONTEXT_OFFSET]
+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \
+ ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4))
+ /* Workaround for ARM errata 752419, only applied if
+ condition exists for it to be triggered.*/
+ ldr r3, [r0, #CONTEXT_OFFSET]
+ mov sp, r3
+#else
+ ldr sp, [r0, #CONTEXT_OFFSET]
+#endif
+
+#if CORTEX_USE_FPU
+ vpop {s16-s31}
+#endif
+ pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+ ENDP
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+ EXPORT _port_thread_start
+_port_thread_start PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+#if CORTEX_SIMPLIFIED_PRIORITY
+ cpsie i
+#else
+ movs r3, #0 /* CORTEX_BASEPRI_DISABLED */
+ msr BASEPRI, r3
+#endif
+ mov r0, r5
+ blx r4
+#if defined(_CHIBIOS_RT_CONF_)
+ movs r0, #0 /* MSG_OK */
+ bl chThdExit
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
+ mov r3, #0
+ bl chSysHalt
+#endif
+ ENDP
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+ EXPORT _port_switch_from_isr
+ EXPORT _port_exit_from_isr
+_port_switch_from_isr PROC
+#if CH_DBG_STATISTICS
+ bl _stats_start_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+ bl _stats_stop_measure_crit_thd
+#endif
+_port_exit_from_isr
+#if CORTEX_SIMPLIFIED_PRIORITY
+ mov r3, #SCB_ICSR :AND: 0xFFFF
+ movt r3, #SCB_ICSR :SHR: 16
+ mov r2, #ICSR_PENDSVSET
+ str r2, [r3, #0]
+ cpsie i
+#else
+ svc #0
+#endif
+waithere b waithere
+ ENDP
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chtypes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chtypes.h
new file mode 100644
index 0000000000..6fead3e7a8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/compilers/RVCT/chtypes.h
@@ -0,0 +1,115 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file ARMCMx/compilers/RVCT/chtypes.h
+ * @brief ARM Cortex-Mx port system types.
+ *
+ * @addtogroup ARMCMx_RVCT_CORE
+ * @{
+ */
+
+#ifndef CHTYPES_H
+#define CHTYPES_H
+
+#include
+#include
+#include
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE (!FALSE)
+#endif
+/** @} */
+
+/**
+ * @name Kernel types
+ * @{
+ */
+typedef uint32_t rtcnt_t; /**< Realtime counter. */
+typedef uint64_t rttime_t; /**< Realtime accumulator. */
+typedef uint32_t syssts_t; /**< System status word. */
+typedef uint8_t tmode_t; /**< Thread flags. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef uint8_t trefs_t; /**< Thread references counter. */
+typedef uint8_t tslices_t; /**< Thread time slices counter.*/
+typedef uint32_t tprio_t; /**< Thread priority. */
+typedef int32_t msg_t; /**< Inter-thread message. */
+typedef int32_t eventid_t; /**< Numeric event identifier. */
+typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
+typedef uint32_t eventflags_t; /**< Mask of event flags. */
+typedef int32_t cnt_t; /**< Generic signed counter. */
+typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
+/** @} */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then some
+ * time-dependent services could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __packed
+
+/**
+ * @brief Memory alignment enforcement for variables.
+ */
+#define ALIGNED_VAR(n) __attribute__((aligned(n)))
+
+/**
+ * @brief Size of a pointer.
+ * @note To be used where the sizeof operator cannot be used, preprocessor
+ * expressions for example.
+ */
+#define SIZEOF_PTR 4
+
+/**
+ * @brief True if alignment is low-high in current architecture.
+ */
+#define REVERSE_ORDER 1
+
+#endif /* CHTYPES_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/mpu.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/mpu.h
new file mode 100644
index 0000000000..269bad2906
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/ARMCMx/mpu.h
@@ -0,0 +1,208 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file common/ARMCMx/mpu.h
+ * @brief Cortex-Mx MPU support macros and structures.
+ *
+ * @addtogroup COMMON_ARMCMx_MPU
+ * @{
+ */
+
+#ifndef MPU_H
+#define MPU_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name MPU registers definitions
+ * @{
+ */
+#define MPU_TYPE_SEPARATED (1U << 0U)
+#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U)
+#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U)
+
+#define MPU_CTRL_ENABLE (1U << 0U)
+#define MPU_CTRL_HFNMIENA (1U << 1U)
+#define MPU_CTRL_PRIVDEFENA (1U << 2U)
+
+#define MPU_RNR_REGION_MASK (255U << 0U)
+#define MPU_RNR_REGION(n) ((n) << 0U)
+
+#define MPU_RBAR_REGION_MASK (15U << 0U)
+#define MPU_RBAR_REGION(n) ((n) << 0U)
+#define MPU_RBAR_VALID (1U << 4U)
+#define MPU_RBAR_ADDR_MASK 0xFFFFFFE0U
+#define MPU_RBAR_ADDR(n) ((n) << 5U)
+
+#define MPU_RASR_ENABLE (1U << 0U)
+#define MPU_RASR_SIZE_MASK (31U << 1U)
+#define MPU_RASR_SIZE(n) ((n) << 1U)
+#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4U)
+#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5U)
+#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6U)
+#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7U)
+#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8U)
+#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9U)
+#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10U)
+#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11U)
+#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12U)
+#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13U)
+#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14U)
+#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15U)
+#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16U)
+#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17U)
+#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18U)
+#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19U)
+#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20U)
+#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21U)
+#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22U)
+#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23U)
+#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24U)
+#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25U)
+#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26U)
+#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27U)
+#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28U)
+#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29U)
+#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30U)
+#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31U)
+#define MPU_RASR_SRD_MASK (255U << 8U)
+#define MPU_RASR_SRD(n) ((n) << 8U)
+#define MPU_RASR_SRD_ALL (0U << 8U)
+#define MPU_RASR_SRD_DISABLE_SUB0 (1U << 8U)
+#define MPU_RASR_SRD_DISABLE_SUB1 (2U << 8U)
+#define MPU_RASR_SRD_DISABLE_SUB2 (4U << 8U)
+#define MPU_RASR_SRD_DISABLE_SUB3 (8U << 8U)
+#define MPU_RASR_SRD_DISABLE_SUB4 (16U << 8U)
+#define MPU_RASR_SRD_DISABLE_SUB5 (32U << 8U)
+#define MPU_RASR_SRD_DISABLE_SUB6 (64U << 8U)
+#define MPU_RASR_SRD_DISABLE_SUB7 (128U << 8U)
+#define MPU_RASR_ATTR_B (1U << 16U)
+#define MPU_RASR_ATTR_C (1U << 17U)
+#define MPU_RASR_ATTR_S (1U << 18U)
+#define MPU_RASR_ATTR_TEX_MASK (7U << 19U)
+#define MPU_RASR_ATTR_TEX(n) ((n) << 19U)
+#define MPU_RASR_ATTR_AP_MASK (7U << 24U)
+#define MPU_RASR_ATTR_AP(n) ((n) << 24U)
+#define MPU_RASR_ATTR_AP_NA_NA (0U << 24U)
+#define MPU_RASR_ATTR_AP_RW_NA (1U << 24U)
+#define MPU_RASR_ATTR_AP_RW_RO (2U << 24U)
+#define MPU_RASR_ATTR_AP_RW_RW (3U << 24U)
+#define MPU_RASR_ATTR_AP_RO_NA (5U << 24U)
+#define MPU_RASR_ATTR_AP_RO_RO (6U << 24U)
+#define MPU_RASR_ATTR_XN (1U << 28U)
+/** @} */
+
+/**
+ * @name Region attributes
+ * @{
+ */
+#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0))
+#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B)
+#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C)
+#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C)
+#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1))
+#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C)
+#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2))
+/** @} */
+
+/**
+ * @name Region identifiers
+ * @{
+ */
+#define MPU_REGION_0 0U
+#define MPU_REGION_1 1U
+#define MPU_REGION_2 2U
+#define MPU_REGION_3 3U
+#define MPU_REGION_4 4U
+#define MPU_REGION_5 5U
+#define MPU_REGION_6 6U
+#define MPU_REGION_7 7U
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the MPU.
+ * @note MEMFAULENA is enabled in SCB_SHCSR.
+ *
+ * @param[in] ctrl MPU control modes as defined in @p MPU_CTRL register,
+ * the enable bit is enforced
+ *
+ * @api
+ */
+#define mpuEnable(ctrl) { \
+ MPU->CTRL = ((uint32_t)ctrl) | MPU_CTRL_ENABLE; \
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; \
+}
+
+/**
+ * @brief Disables the MPU.
+ * @note MEMFAULENA is disabled in SCB_SHCSR.
+ *
+ * @api
+ */
+#define mpuDisable() { \
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; \
+ MPU->CTRL = 0; \
+}
+
+/**
+ * @brief Configures an MPU region.
+ *
+ * @param[in] region the region number
+ * @param[in] address start address of the region, note, there are alignment
+ * constraints
+ * @param[in] attribs attributes mask as defined in @p MPU_RASR register
+ *
+ * @api
+ */
+#define mpuConfigureRegion(region, addr, attribs) { \
+ MPU->RNR = ((uint32_t)region); \
+ MPU->RBAR = ((uint32_t)addr); \
+ MPU->RASR = ((uint32_t)attribs); \
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MPU_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/readme.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/readme.txt
new file mode 100644
index 0000000000..cad1dabd44
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/readme.txt
@@ -0,0 +1,3 @@
+All the code contained under ./os/common/ports are RTOS ports compatible
+with both RT and NIL. The code is placed under ./os/common in order to
+prevent code duplication and disalignments.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chcore.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chcore.c
new file mode 100644
index 0000000000..d44a2f7be3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chcore.c
@@ -0,0 +1,79 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file templates/chcore.c
+ * @brief Port related template code.
+ * @details This file is a template of the system driver functions provided by
+ * a port. Some of the following functions may be implemented as
+ * macros in chcore.h if the implementer decides that there is an
+ * advantage in doing so, for example because performance concerns.
+ *
+ * @addtogroup core
+ * @details Non portable code templates.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Port-related initialization code.
+ * @note This function is usually empty.
+ */
+void _port_init(void) {
+}
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects directly the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+void _port_switch(thread_t *ntp, thread_t *otp) {
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chcore.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chcore.h
new file mode 100644
index 0000000000..cae23fb9df
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chcore.h
@@ -0,0 +1,452 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file templates/chcore.h
+ * @brief Port related template macros and structures.
+ * @details This file is a template of the system driver macros provided by
+ * a port.
+ *
+ * @addtogroup core
+ * @{
+ */
+
+#ifndef CHCORE_H
+#define CHCORE_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Port Capabilities and Constants
+ * @{
+ */
+/**
+ * @brief This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT FALSE
+
+/**
+ * @brief Natural alignment constant.
+ * @note It is the minimum alignment for pointer-size variables.
+ */
+#define PORT_NATURAL_ALIGN sizeof (void *)
+
+/**
+ * @brief Stack alignment constant.
+ * @note It is the alignement required for the stack pointer.
+ */
+#define PORT_STACK_ALIGN sizeof (stkalign_t)
+
+/**
+ * @brief Working Areas alignment constant.
+ * @note It is the alignment to be enforced for thread working areas.
+ */
+#define PORT_WORKING_AREA_ALIGN sizeof (stkalign_t)
+/** @} */
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief Macro defining an XXX architecture.
+ */
+#define PORT_ARCHITECTURE_XXX
+
+/**
+ * @brief Macro defining the specific XXX architecture.
+ */
+#define PORT_ARCHITECTURE_XXX_YYY
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME "XXX Architecture"
+
+/**
+ * @brief Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME "GCC " __VERSION__
+
+#else
+#error "unsupported compiler"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#define PORT_INFO "no info"
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE 32
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK 256
+#endif
+
+/**
+ * @brief Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ * @p chcore_timer.h, if this option is enabled then the file
+ * @p chcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER) || defined(__DOXYGEN__)
+#define PORT_USE_ALT_TIMER FALSE
+#endif
+
+/**
+ * @brief Enables a "wait for interrupt" instruction in the idle loop.
+ */
+#if !defined(PORT_XXX_WFI_SLEEP_IDLE) || defined(__DOXYGEN__)
+#define PORT_XXX_ENABLE_WFI_IDLE FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Type of stack and memory alignment enforcement.
+ * @note In this architecture the stack alignment is enforced to 64 bits.
+ */
+typedef uint64_t stkalign_t;
+
+/**
+ * @brief Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ * preemption-capable interrupt handler.
+ * @note R2 and R13 are not saved because those are assumed to be immutable
+ * during the system life cycle.
+ */
+struct port_extctx {
+};
+
+/**
+ * @brief System saved context.
+ * @details This structure represents the inner stack frame during a context
+ * switching.
+ * @note R2 and R13 are not saved because those are assumed to be immutable
+ * during the system life cycle.
+ * @note LR is stored in the caller context so it is not present in this
+ * structure.
+ */
+struct port_intctx {
+};
+
+/**
+ * @brief Platform dependent part of the @p thread_t structure.
+ * @details This structure usually contains just the saved stack pointer
+ * defined as a pointer to a @p port_intctx structure.
+ */
+struct port_context {
+ struct port_intctx *sp;
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
+}
+
+/**
+ * @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
+ sizeof(struct port_extctx) + \
+ ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK)))
+
+/**
+ * @brief Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ * aligned as both position and size.
+ *
+ * @param[in] s the name to be assigned to the stack array
+ * @param[in] n the stack size to be assigned to the thread
+ */
+#define PORT_WORKING_AREA(s, n) \
+ stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
+
+/**
+ * @brief Priority level verification macro.
+ */
+#define PORT_IRQ_IS_VALID_PRIORITY(n) false
+
+/**
+ * @brief Priority level verification macro.
+ */
+#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) false
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects directly the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) { \
+ register struct port_intctx *sp asm ("%r1"); \
+ if ((stkalign_t *)(sp - 1) < otp->wabase) \
+ chSysHalt("stack overflow"); \
+ _port_switch(ntp, otp); \
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_init(void);
+ void _port_switch(thread_t *ntp, thread_t *otp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+ return 0;
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retval false the word specified a disabled interrupts status.
+ * @retval true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+ (void)sts;
+
+ return false;
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+ return false;
+}
+
+/**
+ * @brief Kernel-lock action.
+ * @details Usually this function just disables interrupts but may perform more
+ * actions.
+ */
+static inline void port_lock(void) {
+
+}
+
+/**
+ * @brief Kernel-unlock action.
+ * @details Usually this function just enables interrupts but may perform more
+ * actions.
+ */
+static inline void port_unlock(void) {
+
+}
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @details This function is invoked before invoking I-class APIs from
+ * interrupt handlers. The implementation is architecture dependent,
+ * in its simplest form it is void.
+ */
+static inline void port_lock_from_isr(void) {
+
+}
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @details This function is invoked after invoking I-class APIs from interrupt
+ * handlers. The implementation is architecture dependent, in its
+ * simplest form it is void.
+ */
+static inline void port_unlock_from_isr(void) {
+
+}
+
+/**
+ * @brief Disables all the interrupt sources.
+ * @note Of course non-maskable interrupt sources are not included.
+ */
+static inline void port_disable(void) {
+
+}
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ * @note Interrupt sources above kernel level remains enabled.
+ */
+static inline void port_suspend(void) {
+
+}
+
+/**
+ * @brief Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+}
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if PORT_XXX_ENABLE_WFI_IDLE
+#endif
+}
+
+/**
+ * @brief Returns the current value of the realtime counter.
+ *
+ * @return The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+ return 0;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module late inclusions. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#if CH_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "chcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "chcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CHCORE_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chtypes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chtypes.h
new file mode 100644
index 0000000000..6ee8ec6037
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/ports/templates/chtypes.h
@@ -0,0 +1,119 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file templates/chtypes.h
+ * @brief System types template.
+ * @details The types defined in this file may change depending on the target
+ * architecture. You may also try to optimize the size of the various
+ * types in order to privilege size or performance, be careful in
+ * doing so.
+ *
+ * @addtogroup types
+ * @{
+ */
+
+#ifndef CHTYPES_H
+#define CHTYPES_H
+
+#include
+#include
+#include
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE (!FALSE)
+#endif
+/** @} */
+
+/**
+ * @name Kernel types
+ * @{
+ */
+typedef uint32_t rtcnt_t; /**< Realtime counter. */
+typedef uint64_t rttime_t; /**< Realtime accumulator. */
+typedef uint32_t syssts_t; /**< System status word. */
+typedef uint8_t tmode_t; /**< Thread flags. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef uint8_t trefs_t; /**< Thread references counter. */
+typedef uint8_t tslices_t; /**< Thread time slices counter.*/
+typedef uint32_t tprio_t; /**< Thread priority. */
+typedef int32_t msg_t; /**< Inter-thread message. */
+typedef int32_t eventid_t; /**< Numeric event identifier. */
+typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
+typedef uint32_t eventflags_t; /**< Mask of event flags. */
+typedef int32_t cnt_t; /**< Generic signed counter. */
+typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
+/** @} */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then the
+ * realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+/**
+ * @brief Memory alignment enforcement for variables.
+ */
+#define ALIGNED_VAR(n) __attribute__((aligned(n)))
+
+/**
+ * @brief Size of a pointer.
+ * @note To be used where the sizeof operator cannot be used, preprocessor
+ * expressions for example.
+ */
+#define SIZEOF_PTR 4
+
+/**
+ * @brief True if alignment is low-high in current architecture.
+ */
+#define REVERSE_ORDER 1
+
+#endif /* CHTYPES_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
new file mode 100644
index 0000000000..c9e2293189
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
@@ -0,0 +1,288 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file crt0_v6m.S
+ * @brief Generic ARMv6-M (Cortex-M0/M1) startup file for ChibiOS.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP_V6M
+ * @{
+ */
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define CONTROL_MODE_PRIVILEGED 0
+#define CONTROL_MODE_UNPRIVILEGED 1
+#define CONTROL_USE_MSP 0
+#define CONTROL_USE_PSP 2
+
+#define SCB_VTOR 0xE000ED08
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enforces initialization of MSP.
+ * @note This is required if the boot process is not reliable for whatever
+ * reason (bad ROMs, bad bootloaders, bad debuggers=.
+ */
+#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
+#define CRT0_FORCE_MSP_INIT TRUE
+#endif
+
+/**
+ * @brief VTOR special register initialization.
+ * @details VTOR is initialized to point to the vectors table.
+ * @note This option can only be enabled on Cortex-M0+ cores.
+ */
+#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
+#define CRT0_VTOR_INIT FALSE
+#endif
+
+/**
+ * @brief Control special register initialization value.
+ * @details The system is setup to run in privileged mode using the PSP
+ * stack (dual stack mode).
+ */
+#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
+#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
+ CONTROL_MODE_PRIVILEGED)
+#endif
+
+/**
+ * @brief Core initialization switch.
+ */
+#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
+#define CRT0_INIT_CORE TRUE
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief RAM areas initialization switch.
+ */
+#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
+#define CRT0_INIT_RAM_AREAS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+ .cpu cortex-m0
+ .fpu softvfp
+
+ .thumb
+ .text
+
+/*
+ * Reset handler.
+ */
+ .align 2
+ .thumb_func
+ .global Reset_Handler
+Reset_Handler:
+ /* Interrupts are globally masked initially.*/
+ cpsid i
+
+#if CRT0_FORCE_MSP_INIT == TRUE
+ /* MSP stack pointers initialization.*/
+ ldr r0, =__main_stack_end__
+ msr MSP, r0
+#endif
+
+ /* PSP stack pointers initialization.*/
+ ldr r0, =__process_stack_end__
+ msr PSP, r0
+
+ /* CPU mode initialization as configured.*/
+ movs r0, #CRT0_CONTROL_INIT
+ msr CONTROL, r0
+ isb
+
+#if CRT0_VTOR_INIT == TRUE
+ ldr r0, =_vectors
+ ldr r1, =SCB_VTOR
+ str r0, [r1]
+#endif
+
+#if CRT0_INIT_CORE == TRUE
+ /* Core initialization.*/
+ bl __core_init
+#endif
+
+ /* Early initialization..*/
+ bl __early_init
+
+#if CRT0_INIT_STACKS == TRUE
+ ldr r0, =CRT0_STACKS_FILL_PATTERN
+ /* Main Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r1, =__main_stack_base__
+ ldr r2, =__main_stack_end__
+msloop:
+ cmp r1, r2
+ bge endmsloop
+ str r0, [r1]
+ add r1, r1, #4
+ b msloop
+endmsloop:
+ /* Process Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r1, =__process_stack_base__
+ ldr r2, =__process_stack_end__
+psloop:
+ cmp r1, r2
+ bge endpsloop
+ str r0, [r1]
+ add r1, r1, #4
+ b psloop
+endpsloop:
+#endif
+
+#if CRT0_INIT_DATA == TRUE
+ /* Data initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =_textdata
+ ldr r2, =_data
+ ldr r3, =_edata
+dloop:
+ cmp r2, r3
+ bge enddloop
+ ldr r0, [r1]
+ str r0, [r2]
+ add r1, r1, #4
+ add r2, r2, #4
+ b dloop
+enddloop:
+#endif
+
+#if CRT0_INIT_BSS == TRUE
+ /* BSS initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ movs r0, #0
+ ldr r1, =_bss_start
+ ldr r2, =_bss_end
+bloop:
+ cmp r1, r2
+ bge endbloop
+ str r0, [r1]
+ add r1, r1, #4
+ b bloop
+endbloop:
+#endif
+
+#if CRT0_INIT_RAM_AREAS == TRUE
+ /* RAM areas initialization.*/
+ bl __init_ram_areas
+#endif
+
+ /* Late initialization..*/
+ bl __late_init
+
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ ldr r4, =__init_array_start
+ ldr r5, =__init_array_end
+initloop:
+ cmp r4, r5
+ bge endinitloop
+ ldr r1, [r4]
+ blx r1
+ add r4, r4, #4
+ b initloop
+endinitloop:
+#endif
+
+ /* Main program invocation, r0 contains the returned value.*/
+ bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ ldr r4, =__fini_array_start
+ ldr r5, =__fini_array_end
+finiloop:
+ cmp r4, r5
+ bge endfiniloop
+ ldr r1, [r4]
+ blx r1
+ add r4, r4, #4
+ b finiloop
+endfiniloop:
+#endif
+
+ /* Branching to the defined exit handler.*/
+ ldr r1, =__default_exit
+ bx r1
+
+#endif
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
new file mode 100644
index 0000000000..96e919d19d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
@@ -0,0 +1,360 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file crt0_v7m.S
+ * @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP_V7M
+ * @{
+ */
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define CONTROL_MODE_PRIVILEGED 0
+#define CONTROL_MODE_UNPRIVILEGED 1
+#define CONTROL_USE_MSP 0
+#define CONTROL_USE_PSP 2
+#define CONTROL_FPCA 4
+
+#define FPCCR_ASPEN (1 << 31)
+#define FPCCR_LSPEN (1 << 30)
+
+#define SCB_VTOR 0xE000ED08
+#define SCB_CPACR 0xE000ED88
+#define SCB_FPCCR 0xE000EF34
+#define SCB_FPDSCR 0xE000EF3C
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/* dRonin: This if fixed upstream apparently, remove on upgrade to 18.x. */
+/**
+ * @brief MSP register initialization.
+ * @details MSP is initialized to point to the proper main process tack.
+ */
+#if !defined(CRT0_FORCE_MSP_INIT) || defined(__DOXYGEN__)
+#define CRT0_FORCE_MSP_INIT TRUE
+#endif
+
+/**
+ * @brief VTOR special register initialization.
+ * @details VTOR is initialized to point to the vectors table.
+ */
+#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
+#define CRT0_VTOR_INIT TRUE
+#endif
+
+/**
+ * @brief FPU initialization switch.
+ */
+#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
+#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
+#define CRT0_INIT_FPU CORTEX_USE_FPU
+#else
+#define CRT0_INIT_FPU FALSE
+#endif
+#endif
+
+/**
+ * @brief Control special register initialization value.
+ * @details The system is setup to run in privileged mode using the PSP
+ * stack (dual stack mode).
+ */
+#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
+#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
+ CONTROL_MODE_PRIVILEGED)
+#endif
+
+/**
+ * @brief Core initialization switch.
+ */
+#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
+#define CRT0_INIT_CORE TRUE
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief RAM areas initialization switch.
+ */
+#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
+#define CRT0_INIT_RAM_AREAS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+/**
+ * @brief FPU FPCCR register initialization value.
+ * @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
+ */
+#if !defined(CRT0_FPCCR_INIT) || defined(__DOXYGEN__)
+#define CRT0_FPCCR_INIT (FPCCR_ASPEN | FPCCR_LSPEN)
+#endif
+
+/**
+ * @brief CPACR register initialization value.
+ * @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
+ */
+#if !defined(CRT0_CPACR_INIT) || defined(__DOXYGEN__)
+#define CRT0_CPACR_INIT 0x00F00000
+#endif
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+ .syntax unified
+ .cpu cortex-m3
+#if CRT0_INIT_FPU == TRUE
+ .fpu fpv4-sp-d16
+#else
+ .fpu softvfp
+#endif
+
+ .thumb
+ .text
+
+/*
+ * Reset handler.
+ */
+ .align 2
+ .thumb_func
+ .global Reset_Handler
+Reset_Handler:
+ /* Interrupts are globally masked initially.*/
+ cpsid i
+
+#if CRT0_FORCE_MSP_INIT == TRUE
+ /* MSP stack pointers initialization.*/
+ ldr r0, =__main_stack_end__
+ msr MSP, r0
+#endif
+
+ /* PSP stack pointers initialization.*/
+ ldr r0, =__process_stack_end__
+ msr PSP, r0
+
+#if CRT0_VTOR_INIT == TRUE
+ ldr r0, =_vectors
+ movw r1, #SCB_VTOR & 0xFFFF
+ movt r1, #SCB_VTOR >> 16
+ str r0, [r1]
+#endif
+
+#if CRT0_INIT_FPU == TRUE
+ /* FPU FPCCR initialization.*/
+ movw r0, #CRT0_FPCCR_INIT & 0xFFFF
+ movt r0, #CRT0_FPCCR_INIT >> 16
+ movw r1, #SCB_FPCCR & 0xFFFF
+ movt r1, #SCB_FPCCR >> 16
+ str r0, [r1]
+ dsb
+ isb
+
+ /* CPACR initialization.*/
+ movw r0, #CRT0_CPACR_INIT & 0xFFFF
+ movt r0, #CRT0_CPACR_INIT >> 16
+ movw r1, #SCB_CPACR & 0xFFFF
+ movt r1, #SCB_CPACR >> 16
+ str r0, [r1]
+ dsb
+ isb
+
+ /* FPU FPSCR initially cleared.*/
+ mov r0, #0
+ vmsr FPSCR, r0
+
+ /* FPU FPDSCR initially cleared.*/
+ movw r1, #SCB_FPDSCR & 0xFFFF
+ movt r1, #SCB_FPDSCR >> 16
+ str r0, [r1]
+
+ /* Enforcing FPCA bit in the CONTROL register.*/
+ movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA
+
+#else
+ movs r0, #CRT0_CONTROL_INIT
+#endif
+
+ /* CONTROL register initialization as configured.*/
+ msr CONTROL, r0
+ isb
+
+#if CRT0_INIT_CORE == TRUE
+ /* Core initialization.*/
+ bl __core_init
+#endif
+
+ /* Early initialization.*/
+ bl __early_init
+
+#if CRT0_INIT_STACKS == TRUE
+ ldr r0, =CRT0_STACKS_FILL_PATTERN
+ /* Main Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r1, =__main_stack_base__
+ ldr r2, =__main_stack_end__
+msloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo msloop
+
+ /* Process Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r1, =__process_stack_base__
+ ldr r2, =__process_stack_end__
+psloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo psloop
+#endif
+
+#if CRT0_INIT_DATA == TRUE
+ /* Data initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =_textdata_start
+ ldr r2, =_data_start
+ ldr r3, =_data_end
+dloop:
+ cmp r2, r3
+ ittt lo
+ ldrlo r0, [r1], #4
+ strlo r0, [r2], #4
+ blo dloop
+#endif
+
+#if CRT0_INIT_BSS == TRUE
+ /* BSS initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ movs r0, #0
+ ldr r1, =_bss_start
+ ldr r2, =_bss_end
+bloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo bloop
+
+ /* Also initialize the CCM RAM. */
+ movs r0, #0
+ ldr r1, =_cmm_start
+ ldr r2, =_cmm_end
+cloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo cloop
+#endif
+
+#if CRT0_INIT_RAM_AREAS == TRUE
+ /* RAM areas initialization.*/
+ bl __init_ram_areas
+#endif
+
+ /* Late initialization..*/
+ bl __late_init
+
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ ldr r4, =__init_array_start
+ ldr r5, =__init_array_end
+initloop:
+ cmp r4, r5
+ bge endinitloop
+ ldr r1, [r4], #4
+ blx r1
+ b initloop
+endinitloop:
+#endif
+
+ /* Main program invocation, r0 contains the returned value.*/
+ bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ ldr r4, =__fini_array_start
+ ldr r5, =__fini_array_end
+finiloop:
+ cmp r4, r5
+ bge endfiniloop
+ ldr r1, [r4], #4
+ blx r1
+ b finiloop
+endfiniloop:
+#endif
+
+ /* Branching to the defined exit handler.*/
+ b __default_exit
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt1.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt1.c
new file mode 100644
index 0000000000..36385b66f3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt1.c
@@ -0,0 +1,218 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/crt1.c
+ * @brief Startup stub functions.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP
+ * @{
+ */
+
+#include
+
+#include "cmparams.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+#if !defined(CRT1_AREAS_NUMBER) || defined(__DOXYGEN__)
+#define CRT1_AREAS_NUMBER 8
+#endif
+
+#if (CRT1_AREAS_NUMBER < 0) || (CRT1_AREAS_NUMBER > 8)
+#error "CRT1_AREAS_NUMBER must be within 0 and 8"
+#endif
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of an area to be initialized.
+ */
+typedef struct {
+ uint32_t *init_text_area;
+ uint32_t *init_area;
+ uint32_t *clear_area;
+ uint32_t *no_init_area;
+} ram_init_area_t;
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__)
+extern uint32_t __ram0_init_text__, __ram0_init__, __ram0_clear__, __ram0_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__)
+extern uint32_t __ram1_init_text__, __ram1_init__, __ram1_clear__, __ram1_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__)
+extern uint32_t __ram2_init_text__, __ram2_init__, __ram2_clear__, __ram2_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__)
+extern uint32_t __ram3_init_text__, __ram3_init__, __ram3_clear__, __ram3_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__)
+extern uint32_t __ram4_init_text__, __ram4_init__, __ram4_clear__, __ram4_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__)
+extern uint32_t __ram5_init_text__, __ram5_init__, __ram5_clear__, __ram5_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__)
+extern uint32_t __ram6_init_text__, __ram6_init__, __ram6_clear__, __ram6_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__)
+extern uint32_t __ram7_init_text__, __ram7_init__, __ram7_clear__, __ram7_noinit__;
+#endif
+
+/**
+ * @brief Static table of areas to be initialized.
+ */
+#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__)
+static const ram_init_area_t ram_areas[CRT1_AREAS_NUMBER] = {
+ {&__ram0_init_text__, &__ram0_init__, &__ram0_clear__, &__ram0_noinit__},
+#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__)
+ {&__ram1_init_text__, &__ram1_init__, &__ram1_clear__, &__ram1_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__)
+ {&__ram2_init_text__, &__ram2_init__, &__ram2_clear__, &__ram2_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__)
+ {&__ram3_init_text__, &__ram3_init__, &__ram3_clear__, &__ram3_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__)
+ {&__ram4_init_text__, &__ram4_init__, &__ram4_clear__, &__ram4_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__)
+ {&__ram5_init_text__, &__ram5_init__, &__ram5_clear__, &__ram5_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__)
+ {&__ram6_init_text__, &__ram6_init__, &__ram6_clear__, &__ram6_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__)
+ {&__ram7_init_text__, &__ram7_init__, &__ram7_clear__, &__ram7_noinit__},
+#endif
+};
+#endif
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Architecture-dependent core initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ * and before the DATA and BSS segments initialization.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __core_init(void) {
+
+#if CORTEX_MODEL == 7
+ SCB_EnableICache();
+ SCB_EnableDCache();
+#endif
+}
+
+/**
+ * @brief Early initialization.
+ * @details This hook is invoked immediately after the stack and core
+ * initialization and before the DATA and BSS segments
+ * initialization.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __early_init(void) {}
+/*lint -restore*/
+
+/**
+ * @brief Late initialization.
+ * @details This hook is invoked after the DATA and BSS segments
+ * initialization and before any static constructor. The
+ * default behavior is to do nothing.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __late_init(void) {}
+/*lint -restore*/
+
+/**
+ * @brief Default @p main() function exit handler.
+ * @details This handler is invoked or the @p main() function exit. The
+ * default behavior is to enter an infinite loop.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((noreturn, weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __default_exit(void) {
+/*lint -restore*/
+
+ while (true) {
+ }
+}
+
+/**
+ * @brief Performs the initialization of the various RAM areas.
+ */
+void __init_ram_areas(void) {
+#if CRT1_AREAS_NUMBER > 0
+ const ram_init_area_t *rap = ram_areas;
+
+ do {
+ uint32_t *tp = rap->init_text_area;
+ uint32_t *p = rap->init_area;
+
+ /* Copying initialization data.*/
+ while (p < rap->clear_area) {
+ *p = *tp;
+ p++;
+ tp++;
+ }
+
+ /* Zeroing clear area.*/
+ while (p < rap->no_init_area) {
+ *p = 0;
+ p++;
+ }
+ rap++;
+ }
+ while (rap < &ram_areas[CRT1_AREAS_NUMBER]);
+#endif
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x4.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x4.ld
new file mode 100644
index 0000000000..9aa5be706f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x4.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F030x4 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 16k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 4k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x6.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x6.ld
new file mode 100644
index 0000000000..56dd362503
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x6.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F030x6 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 32k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 4k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x8.ld
new file mode 100644
index 0000000000..900c925579
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F030x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F031x6.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F031x6.ld
new file mode 100644
index 0000000000..f7a23c40cc
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F031x6.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F031x6 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 32k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 4k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F042x6.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F042x6.ld
new file mode 100644
index 0000000000..8325981d35
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F042x6.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F042x6 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 32k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 6k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F051x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
new file mode 100644
index 0000000000..34048290ef
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F051x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070xB.ld
new file mode 100644
index 0000000000..a0ff522d63
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F070xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 128k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F072xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F072xB.ld
new file mode 100644
index 0000000000..d11b83b6ba
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F072xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F072xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 128k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F091xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F091xC.ld
new file mode 100644
index 0000000000..2ea579638a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F091xC.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F091xC memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 256k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 32k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F100xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F100xB.ld
new file mode 100644
index 0000000000..ea02b96145
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F100xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F100xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 128k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103x8.ld
new file mode 100644
index 0000000000..9ad88f9a3b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 20k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB.ld
new file mode 100644
index 0000000000..52420918d9
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 128k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 20k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB_maplemini_bootloader.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB_maplemini_bootloader.ld
new file mode 100644
index 0000000000..6d292d2737
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB_maplemini_bootloader.ld
@@ -0,0 +1,88 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xB memory setup for use with the maplemini bootloader.
+ * You will have to
+ * #define CORTEX_VTOR_INIT 0x5000
+ * in your projects chconf.h
+ */
+MEMORY
+{
+ flash0 : org = 0x08005000, len = 128k - 0x5000
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000C00, len = 20k - 0xC00
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xD.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xD.ld
new file mode 100644
index 0000000000..0edea944b9
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xD.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xE memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 384k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 64k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xE.ld
new file mode 100644
index 0000000000..afe2c1ec37
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xE.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xE memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 512k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 64k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xG.ld
new file mode 100644
index 0000000000..d1f55fa4b6
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xG.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xG memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 96k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F107xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F107xC.ld
new file mode 100644
index 0000000000..473c79047f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F107xC.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F107xC memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 256k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 64k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F207xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F207xG.ld
new file mode 100644
index 0000000000..44c65deeb0
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F207xG.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F207xG memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F302x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F302x8.ld
new file mode 100644
index 0000000000..bd23653b0d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F302x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F302x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303x8.ld
new file mode 100644
index 0000000000..0e5129327d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 12k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 4k
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xC.ld
new file mode 100644
index 0000000000..5a5dce9518
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xC.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303xC memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 256k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 40k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 8k
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xE.ld
new file mode 100644
index 0000000000..d1ea7c50cd
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xE.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303xE memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 512k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 64k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 16k
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F334x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F334x8.ld
new file mode 100644
index 0000000000..c98eec07b0
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F334x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F3334x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 12k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 4k
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F373xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F373xC.ld
new file mode 100644
index 0000000000..0529b5c0ab
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F373xC.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303xC memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 256k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 32k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xC.ld
new file mode 100644
index 0000000000..d749976d5a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xC.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F401xC memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 256k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 64k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xE.ld
new file mode 100644
index 0000000000..9f0f948357
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xE.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F401xE memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 512k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 96k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F405xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F405xG.ld
new file mode 100644
index 0000000000..a725ae4add
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F405xG.ld
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F405xG memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xE.ld
new file mode 100644
index 0000000000..25341a3344
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xE.ld
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F407xE memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 512k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xG.ld
new file mode 100644
index 0000000000..765ffc4850
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xG.ld
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F407xG memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410x8.ld
new file mode 100644
index 0000000000..c21e50c646
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F410x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 32k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410xB.ld
new file mode 100644
index 0000000000..c605a514b4
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F410xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 128k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 32k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xC.ld
new file mode 100644
index 0000000000..0e289edbdf
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xC.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F411xC memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 256k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 128k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xE.ld
new file mode 100644
index 0000000000..f2d278e4c6
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xE.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F411xE memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 512k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 128k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld
new file mode 100644
index 0000000000..4d51767a23
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F412xE memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 512k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 256k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld
new file mode 100644
index 0000000000..b4bb300231
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F412xG memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 256k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F429xI.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F429xI.ld
new file mode 100644
index 0000000000..72bbf3b9b2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F429xI.ld
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F429xI memory setup.
+ * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */
+ ram1 : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20020000, len = 64k /* SRAM3 */
+ ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xC.ld
new file mode 100644
index 0000000000..d1944c65b7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xC.ld
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F446xC memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 256k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 : org = 0x00000000, len = 16k /* SRAM2 */
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xE.ld
new file mode 100644
index 0000000000..8b54bf52c3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xE.ld
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F446xE memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 512k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 : org = 0x00000000, len = 16k /* SRAM2 */
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld
new file mode 100644
index 0000000000..cdaeb461a8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F469xI memory setup.
+ * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 384k /* SRAM1 + SRAM2 + SRAM3 */
+ ram1 : org = 0x20000000, len = 160k /* SRAM1 */
+ ram2 : org = 0x20028000, len = 32k /* SRAM2 */
+ ram3 : org = 0x20030000, len = 128k /* SRAM3 */
+ ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
new file mode 100644
index 0000000000..faefa5bd20
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
@@ -0,0 +1,132 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F746xG generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld
new file mode 100644
index 0000000000..417f6c46a1
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld
@@ -0,0 +1,133 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F746xG Ethernet setup.
+ *
+ * RAM1 - Data, Heap.
+ * RAM2 - ETH.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram1);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram1);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram2);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld
new file mode 100644
index 0000000000..728ddc5ede
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld
@@ -0,0 +1,134 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F746xG maximum RAM setup.
+ *
+ * RAM0 - Data, BSS, Heap.
+ * RAM3 - Main Stack, Process Stack, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in cached RAM, DMA buffers management is delegated to the
+ * application code. This setup maximizes the linear RAM available to BSS and
+ * Heap.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld
new file mode 100644
index 0000000000..2054fd494c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld
@@ -0,0 +1,132 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F76xxG generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20020000, len = 368k /* SRAM1 */
+ ram2 : org = 0x2007C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */
+ ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld
new file mode 100644
index 0000000000..7d66cb2ee3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld
@@ -0,0 +1,132 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F76xxI generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */
+ flash1 : org = 0x00200000, len = 2M /* Flash as ITCM */
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20020000, len = 368k /* SRAM1 */
+ ram2 : org = 0x2007C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */
+ ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x3.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x3.ld
new file mode 100644
index 0000000000..c3ba94beb5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x3.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L011x3 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 8k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 2k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x4.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x4.ld
new file mode 100644
index 0000000000..cfb74b1be4
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x4.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L011x4 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 16k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 2k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x4.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x4.ld
new file mode 100644
index 0000000000..fddc933e83
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x4.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L031x4 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 16k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x6.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x6.ld
new file mode 100644
index 0000000000..8e8836a065
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x6.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L031x6 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 32k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x6.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x6.ld
new file mode 100644
index 0000000000..e4859cf5a5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x6.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L052x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 16k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x8.ld
new file mode 100644
index 0000000000..5d2cef4312
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L052x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x6.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x6.ld
new file mode 100644
index 0000000000..ab2ad3ee76
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x6.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L053x6 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 32k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x8.ld
new file mode 100644
index 0000000000..6844d37e8f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L053x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073x8.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073x8.ld
new file mode 100644
index 0000000000..5e740a4dc1
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073x8.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L073x8 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 64k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 20k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xB.ld
new file mode 100644
index 0000000000..9f47d96981
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L073xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 128k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 20k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xZ.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xZ.ld
new file mode 100644
index 0000000000..5cd69b03a2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xZ.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L073xZ memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 192k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 20k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L151x6.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L151x6.ld
new file mode 100644
index 0000000000..20bf9eb2b7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L151x6.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L151x6 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 32k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 10k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xB.ld
new file mode 100644
index 0000000000..38149ca3e2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L152xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 128k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xE.ld
new file mode 100644
index 0000000000..c6a59b574e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xE.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L152xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 512k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 80k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xB.ld
new file mode 100644
index 0000000000..1436826a7f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L432xB memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 128k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 64k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xC.ld
new file mode 100644
index 0000000000..7d873b7086
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xC.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L432xC memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 256k
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 64k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L476xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L476xG.ld
new file mode 100644
index 0000000000..7ad304cc2b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L476xG.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L476xG memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 96k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 32k
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules.ld
new file mode 100644
index 0000000000..30e3da7e9c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules.ld
@@ -0,0 +1,8 @@
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_code.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_code.ld
new file mode 100644
index 0000000000..542aa68788
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_code.ld
@@ -0,0 +1,77 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .vectors : ALIGN(16)
+ {
+ KEEP(*(.vectors))
+ } > VECTORS_FLASH AT > VECTORS_FLASH_LMA
+
+ .xtors : ALIGN(4)
+ {
+ __init_array_start = .;
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ __init_array_end = .;
+ __fini_array_start = .;
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+ } > XTORS_FLASH AT > XTORS_FLASH_LMA
+
+ .text ALIGN(16) : ALIGN(16)
+ {
+ *(.text)
+ *(.text.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ } > TEXT_FLASH AT > TEXT_FLASH_LMA
+
+ .rodata : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __rodata_base__ = .;
+ *(.rodata)
+ *(.rodata.*)
+ . = ALIGN(4);
+ __rodata_end__ = .;
+ } > RODATA_FLASH AT > RODATA_FLASH_LMA
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
+}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_data.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_data.ld
new file mode 100644
index 0000000000..1d1e38fdb8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_data.ld
@@ -0,0 +1,273 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__ram0_start__ = ORIGIN(ram0);
+__ram0_size__ = LENGTH(ram0);
+__ram0_end__ = __ram0_start__ + __ram0_size__;
+__ram1_start__ = ORIGIN(ram1);
+__ram1_size__ = LENGTH(ram1);
+__ram1_end__ = __ram1_start__ + __ram1_size__;
+__ram2_start__ = ORIGIN(ram2);
+__ram2_size__ = LENGTH(ram2);
+__ram2_end__ = __ram2_start__ + __ram2_size__;
+__ram3_start__ = ORIGIN(ram3);
+__ram3_size__ = LENGTH(ram3);
+__ram3_end__ = __ram3_start__ + __ram3_size__;
+__ram4_start__ = ORIGIN(ram4);
+__ram4_size__ = LENGTH(ram4);
+__ram4_end__ = __ram4_start__ + __ram4_size__;
+__ram5_start__ = ORIGIN(ram5);
+__ram5_size__ = LENGTH(ram5);
+__ram5_end__ = __ram5_start__ + __ram5_size__;
+__ram6_start__ = ORIGIN(ram6);
+__ram6_size__ = LENGTH(ram6);
+__ram6_end__ = __ram6_start__ + __ram6_size__;
+__ram7_start__ = ORIGIN(ram7);
+__ram7_size__ = LENGTH(ram7);
+__ram7_end__ = __ram7_start__ + __ram7_size__;
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .data : ALIGN(4)
+ {
+ . = ALIGN(4);
+ PROVIDE(_textdata = LOADADDR(.data));
+ PROVIDE(_data = .);
+ _textdata_start = LOADADDR(.data);
+ _data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.ramtext)
+ . = ALIGN(4);
+ PROVIDE(_edata = .);
+ _data_end = .;
+ } > DATA_RAM AT > DATA_RAM_LMA
+
+ .bss (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ _bss_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _bss_end = .;
+ PROVIDE(end = .);
+ } > BSS_RAM
+
+ .ram0_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram0_init_text__ = LOADADDR(.ram0_init);
+ __ram0_init__ = .;
+ KEEP(*(.ram0_init))
+ KEEP(*(.ram0_init.*))
+ . = ALIGN(4);
+ } > ram0 AT > RAM_INIT_FLASH_LMA
+
+ .ram0 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram0_clear__ = .;
+ *(.ram0_clear)
+ *(.ram0_clear.*)
+ . = ALIGN(4);
+ __ram0_noinit__ = .;
+ *(.ram0)
+ *(.ram0.*)
+ . = ALIGN(4);
+ __ram0_free__ = .;
+ } > ram0
+
+ .ram1_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram1_init_text__ = LOADADDR(.ram1_init);
+ __ram1_init__ = .;
+ KEEP(*(.ram1_init))
+ KEEP(*(.ram1_init.*))
+ . = ALIGN(4);
+ } > ram1 AT > RAM_INIT_FLASH_LMA
+
+ .ram1 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram1_clear__ = .;
+ *(.ram1_clear)
+ *(.ram1_clear.*)
+ . = ALIGN(4);
+ __ram1_noinit__ = .;
+ *(.ram1)
+ *(.ram1.*)
+ . = ALIGN(4);
+ __ram1_free__ = .;
+ } > ram1
+
+ .ram2_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram2_init_text__ = LOADADDR(.ram2_init);
+ __ram2_init__ = .;
+ KEEP(*(.ram2_init))
+ KEEP(*(.ram2_init.*))
+ . = ALIGN(4);
+ } > ram2 AT > RAM_INIT_FLASH_LMA
+
+ .ram2 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram2_clear__ = .;
+ *(.ram2_clear)
+ *(.ram2_clear.*)
+ . = ALIGN(4);
+ __ram2_noinit__ = .;
+ *(.ram2)
+ *(.ram2.*)
+ . = ALIGN(4);
+ __ram2_free__ = .;
+ } > ram2
+
+ .ram3_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram3_init_text__ = LOADADDR(.ram3_init);
+ __ram3_init__ = .;
+ KEEP(*(.ram3_init))
+ KEEP(*(.ram3_init.*))
+ . = ALIGN(4);
+ } > ram3 AT > RAM_INIT_FLASH_LMA
+
+ .ram3 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram3_clear__ = .;
+ *(.ram3_clear)
+ *(.ram3_clear.*)
+ . = ALIGN(4);
+ __ram3_noinit__ = .;
+ *(.ram3)
+ *(.ram3.*)
+ . = ALIGN(4);
+ __ram3_free__ = .;
+ } > ram3
+
+ .ram4_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram4_init_text__ = LOADADDR(.ram4_init);
+ __ram4_init__ = .;
+ KEEP(*(.ram4_init))
+ KEEP(*(.ram4_init.*))
+ . = ALIGN(4);
+ } > ram4 AT > RAM_INIT_FLASH_LMA
+
+ .ram4 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram4_clear__ = .;
+ *(.ram4_clear)
+ *(.ram4_clear.*)
+ . = ALIGN(4);
+ __ram4_noinit__ = .;
+ *(.ram4)
+ *(.ram4.*)
+ . = ALIGN(4);
+ __ram4_free__ = .;
+ } > ram4
+
+ .ram5_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram5_init_text__ = LOADADDR(.ram5_init);
+ __ram5_init__ = .;
+ KEEP(*(.ram5_init))
+ KEEP(*(.ram5_init.*))
+ . = ALIGN(4);
+ } > ram5 AT > RAM_INIT_FLASH_LMA
+
+ .ram5 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram5_clear__ = .;
+ *(.ram5_clear)
+ *(.ram5_clear.*)
+ . = ALIGN(4);
+ __ram5_noinit__ = .;
+ *(.ram5)
+ *(.ram5.*)
+ . = ALIGN(4);
+ __ram5_free__ = .;
+ } > ram5
+
+ .ram6_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram6_init_text__ = LOADADDR(.ram6_init);
+ __ram6_init__ = .;
+ KEEP(*(.ram6_init))
+ KEEP(*(.ram6_init.*))
+ . = ALIGN(4);
+ } > ram6 AT > RAM_INIT_FLASH_LMA
+
+ .ram6 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram6_clear__ = .;
+ *(.ram6_clear)
+ *(.ram6_clear.*)
+ . = ALIGN(4);
+ __ram6_noinit__ = .;
+ *(.ram6)
+ *(.ram6.*)
+ . = ALIGN(4);
+ __ram6_free__ = .;
+ } > ram6
+
+ .ram7_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram7_init_text__ = LOADADDR(.ram7_init);
+ __ram7_init__ = .;
+ KEEP(*(.ram7_init))
+ KEEP(*(.ram7_init.*))
+ . = ALIGN(4);
+ } > ram7 AT > RAM_INIT_FLASH_LMA
+
+ .ram7 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram7_clear__ = .;
+ *(.ram7_clear)
+ *(.ram7_clear.*)
+ . = ALIGN(4);
+ __ram7_noinit__ = .;
+ *(.ram7)
+ *(.ram7.*)
+ . = ALIGN(4);
+ __ram7_free__ = .;
+ } > ram7
+
+ /* The default heap uses the (statically) unused part of a RAM section.*/
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __heap_base__ = .;
+ . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
+ __heap_end__ = .;
+ } > HEAP_RAM
+}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_stacks.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_stacks.ld
new file mode 100644
index 0000000000..2d1c6907dc
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/ld/rules_stacks.ld
@@ -0,0 +1,38 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+SECTIONS
+{
+ /* Special section for exceptions stack.*/
+ .mstack :
+ {
+ . = ALIGN(8);
+ __main_stack_base__ = .;
+ . += __main_stack_size__;
+ . = ALIGN(8);
+ __main_stack_end__ = .;
+ } > MAIN_STACK_RAM
+
+ /* Special section for process stack.*/
+ .pstack :
+ {
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > PROCESS_STACK_RAM
+}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk
new file mode 100644
index 0000000000..69795ad1c9
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk
@@ -0,0 +1,10 @@
+# List of the ChibiOS generic STM32F0xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F0xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk
new file mode 100644
index 0000000000..c3aff9606d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk
@@ -0,0 +1,10 @@
+# List of the ChibiOS generic STM32F1xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F1xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk
new file mode 100644
index 0000000000..7d6c661073
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk
@@ -0,0 +1,12 @@
+# List of the ChibiOS generic STM32F2xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F2xx \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS)/os/common/ext/CMSIS/ST/STM32F2xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk
new file mode 100644
index 0000000000..a276b8ed03
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk
@@ -0,0 +1,10 @@
+# List of the ChibiOS generic STM32F3xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F3xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
new file mode 100644
index 0000000000..ba3d7adadf
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
@@ -0,0 +1,10 @@
+# List of the ChibiOS generic STM32F4xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F4xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk
new file mode 100644
index 0000000000..481889484e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk
@@ -0,0 +1,12 @@
+# List of the ChibiOS generic STM32F7xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F7xx \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS)/os/common/ext/CMSIS/ST/STM32F7xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk
new file mode 100644
index 0000000000..be91496538
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk
@@ -0,0 +1,12 @@
+# List of the ChibiOS generic STM32L0xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32L0xx \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS)/os/common/ext/CMSIS/ST/STM32L0xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk
new file mode 100644
index 0000000000..5ba7860dce
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk
@@ -0,0 +1,12 @@
+# List of the ChibiOS generic STM32L1xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32L1xx \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS)/os/common/ext/CMSIS/ST/STM32L1xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk
new file mode 100644
index 0000000000..a2e842c7bd
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk
@@ -0,0 +1,12 @@
+# List of the ChibiOS generic STM32L4xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32L4xx \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS)/os/common/ext/CMSIS/ST/STM32L4xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/rules.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/rules.mk
similarity index 58%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/rules.mk
rename to flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/rules.mk
index 438130af76..82337ec116 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/rules.mk
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/rules.mk
@@ -5,13 +5,13 @@
#
# Compiler options
-OPT = $(USE_OPT)
-COPT = $(USE_COPT)
-CPPOPT = $(USE_CPPOPT)
+OPT := $(USE_OPT)
+COPT := $(USE_COPT)
+CPPOPT := $(USE_CPPOPT)
# Garbage collection
ifeq ($(USE_LINK_GC),yes)
- OPT += -ffunction-sections -fdata-sections -fno-common
+ OPT += -ffunction-sections -fdata-sections -fno-common
LDOPT := ,--gc-sections
else
LDOPT :=
@@ -27,19 +27,38 @@ ifeq ($(USE_LTO),yes)
OPT += -flto
endif
+# FPU options default (Cortex-M4 and Cortex-M7 single precision).
+ifeq ($(USE_FPU_OPT),)
+ USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+endif
+
# FPU-related options
ifeq ($(USE_FPU),)
USE_FPU = no
endif
ifneq ($(USE_FPU),no)
- OPT += -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -fsingle-precision-constant
- DDEFS += -DCORTEX_USE_FPU=TRUE
+ OPT += $(USE_FPU_OPT)
+ DDEFS += -DCORTEX_USE_FPU=TRUE
DADEFS += -DCORTEX_USE_FPU=TRUE
else
- DDEFS += -DCORTEX_USE_FPU=FALSE
+ DDEFS += -DCORTEX_USE_FPU=FALSE
DADEFS += -DCORTEX_USE_FPU=FALSE
endif
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
# Output directory and files
ifeq ($(BUILDDIR),)
BUILDDIR = build
@@ -47,70 +66,81 @@ endif
ifeq ($(BUILDDIR),.)
BUILDDIR = build
endif
-OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
- $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp
+OUTFILES := $(BUILDDIR)/$(PROJECT).elf \
+ $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).bin \
+ $(BUILDDIR)/$(PROJECT).dmp \
+ $(BUILDDIR)/$(PROJECT).list
+
+ifdef SREC
+ OUTFILES += $(BUILDDIR)/$(PROJECT).srec
+endif
# Source files groups and paths
ifeq ($(USE_THUMB),yes)
- TCSRC += $(CSRC)
+ TCSRC += $(CSRC)
TCPPSRC += $(CPPSRC)
else
- ACSRC += $(CSRC)
+ ACSRC += $(CSRC)
ACPPSRC += $(CPPSRC)
endif
-ASRC = $(ACSRC)$(ACPPSRC)
-TSRC = $(TCSRC)$(TCPPSRC)
-SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
+ASRC := $(ACSRC) $(ACPPSRC)
+TSRC := $(TCSRC) $(TCPPSRC)
+SRCPATHS := $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
# Various directories
-OBJDIR = $(BUILDDIR)/obj
-LSTDIR = $(BUILDDIR)/lst
+OBJDIR := $(BUILDDIR)/obj
+LSTDIR := $(BUILDDIR)/lst
# Object files groups
-ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
-ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
-TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
-TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
-ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
-ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
-OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+ACOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
+ACPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
+TCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
+TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
+ASMOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS := $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
# Paths
-IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
-LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+IINCDIR := $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR := $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+LLIBDIR += -L$(dir $(LDSCRIPT))
# Macros
-DEFS = $(DDEFS) $(UDEFS)
-ADEFS = $(DADEFS) $(UADEFS)
+DEFS := $(DDEFS) $(UDEFS)
+ADEFS := $(DADEFS) $(UADEFS)
# Libs
-LIBS = $(DLIBS) $(ULIBS)
+LIBS := $(DLIBS) $(ULIBS)
# Various settings
-MCFLAGS = -mcpu=$(MCU)
+MCFLAGS := -mcpu=$(MCU)
ODFLAGS = -x --syms
-ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
-ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+ASFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
-LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT)
+LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH)/ld,--script=$(LDSCRIPT)$(LDOPT)
# Thumb interwork enabled only if needed because it kills performance.
-ifneq ($(TSRC),)
+ifneq ($(strip $(TSRC)),)
CFLAGS += -DTHUMB_PRESENT
CPPFLAGS += -DTHUMB_PRESENT
ASFLAGS += -DTHUMB_PRESENT
- ifneq ($(ASRC),)
+ ASXFLAGS += -DTHUMB_PRESENT
+ ifneq ($(strip $(ASRC)),)
# Mixed ARM and THUMB mode.
CFLAGS += -mthumb-interwork
CPPFLAGS += -mthumb-interwork
ASFLAGS += -mthumb-interwork
+ ASXFLAGS += -mthumb-interwork
LDFLAGS += -mthumb-interwork
else
# Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
+ ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
LDFLAGS += -mno-thumb-interwork -mthumb
endif
else
@@ -118,11 +148,13 @@ else
CFLAGS += -mno-thumb-interwork
CPPFLAGS += -mno-thumb-interwork
ASFLAGS += -mno-thumb-interwork
+ ASXFLAGS += -mno-thumb-interwork
LDFLAGS += -mno-thumb-interwork
endif
# Generate dependency information
ASFLAGS += -MD -MP -MF .dep/$(@F).d
+ASXFLAGS += -MD -MP -MF .dep/$(@F).d
CFLAGS += -MD -MP -MF .dep/$(@F).d
CPPFLAGS += -MD -MP -MF .dep/$(@F).d
@@ -133,20 +165,27 @@ VPATH = $(SRCPATHS)
# Makefile rules
#
-all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
-MAKE_ALL_RULE_HOOK:
+PRE_MAKE_ALL_RULE_HOOK:
-$(OBJS): | $(BUILDDIR)
+POST_MAKE_ALL_RULE_HOOK:
-$(BUILDDIR) $(OBJDIR) $(LSTDIR):
+$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR)
+
+$(BUILDDIR):
ifneq ($(USE_VERBOSE_COMPILE),yes)
@echo Compiler Options
@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
@echo
endif
- mkdir -p $(OBJDIR)
- mkdir -p $(LSTDIR)
+ @mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+ @mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+ @mkdir -p $(LSTDIR)
$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
ifeq ($(USE_VERBOSE_COMPILE),yes)
@@ -202,7 +241,7 @@ else
@$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
endif
-%.elf: $(OBJS) $(LDSCRIPT)
+$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT)
ifeq ($(USE_VERBOSE_COMPILE),yes)
@echo
$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
@@ -211,7 +250,7 @@ else
@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
endif
-%.hex: %.elf $(LDSCRIPT)
+%.hex: %.elf
ifeq ($(USE_VERBOSE_COMPILE),yes)
$(HEX) $< $@
else
@@ -219,7 +258,7 @@ else
@$(HEX) $< $@
endif
-%.bin: %.elf $(LDSCRIPT)
+%.bin: %.elf
ifeq ($(USE_VERBOSE_COMPILE),yes)
$(BIN) $< $@
else
@@ -227,24 +266,52 @@ else
@$(BIN) $< $@
endif
-%.dmp: %.elf $(LDSCRIPT)
+%.srec: %.elf
+ifdef SREC
+ ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(SREC) $< $@
+ else
+ @echo Creating $@
+ @$(SREC) $< $@
+ endif
+endif
+
+%.dmp: %.elf
ifeq ($(USE_VERBOSE_COMPILE),yes)
$(OD) $(ODFLAGS) $< > $@
+ $(SZ) $<
else
@echo Creating $@
@$(OD) $(ODFLAGS) $< > $@
@echo
@$(SZ) $<
+endif
+
+%.list: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) -S $< > $@
+else
+ @echo Creating $@
+ @$(OD) -S $< > $@
@echo
@echo Done
endif
-clean:
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+ @$(AR) -r $@ $^
+ @echo
+ @echo Done
+
+clean: CLEAN_RULE_HOOK
@echo Cleaning
-rm -fR .dep $(BUILDDIR)
@echo
@echo Done
+CLEAN_RULE_HOOK:
+
#
# Include the dependency files, should be the last of the makefile
#
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/vectors.c b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/vectors.c
new file mode 100644
index 0000000000..cdbe876b79
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/vectors.c
@@ -0,0 +1,630 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/vectors.c
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#include
+#include
+
+#include "vectors.h"
+
+#if (CORTEX_NUM_VECTORS % 8) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+/**
+ * @brief Unhandled exceptions handler.
+ * @details Any undefined exception vector points to this function by default.
+ * This function simply stops the system into an infinite loop.
+ *
+ * @notapi
+ */
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+__attribute__((weak))
+void _unhandled_exception(void) {
+/*lint -restore*/
+
+ while (true) {
+ }
+}
+
+#if !defined(__DOXYGEN__)
+extern uint32_t __main_stack_end__;
+void Reset_Handler(void);
+void NMI_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void HardFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void MemManage_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void BusFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void UsageFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
+void SVC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void DebugMon_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
+void PendSV_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void SysTick_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
+#if CORTEX_NUM_VECTORS > 4
+void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 8
+void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 12
+void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 16
+void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 20
+void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 24
+void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 28
+void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 32
+void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 36
+void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 40
+void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 44
+void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 48
+void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 52
+void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 56
+void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 60
+void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 64
+void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 68
+void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 72
+void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 76
+void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 80
+void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector188(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector18C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 84
+void Vector190(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector194(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector198(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector19C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 88
+void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 92
+void Vector1B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 96
+void Vector1C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 100
+void Vector1D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 104
+void Vector1E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 108
+void Vector1F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 112
+void Vector200(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector204(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector208(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector20C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 116
+void Vector210(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector214(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector218(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector21C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 120
+void Vector220(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector224(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector228(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector22C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 124
+void Vector230(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector234(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector238(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector23C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 128
+void Vector240(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector244(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector248(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector24C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 132
+void Vector250(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector254(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector258(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector25C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 136
+void Vector260(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector264(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector268(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector26C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 140
+void Vector270(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector274(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector278(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector27C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 144
+void Vector280(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector284(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector288(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector28C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 148
+void Vector290(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector294(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector298(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector29C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 152
+void Vector2A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 156
+void Vector2B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 160
+void Vector2C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 164
+void Vector2D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 168
+void Vector2E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 172
+void Vector2F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 176
+void Vector300(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector304(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector308(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector30C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 180
+void Vector310(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector314(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector318(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector31C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 184
+void Vector320(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector324(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector328(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector32C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 188
+void Vector330(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector334(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector338(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector33C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 192
+void Vector340(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector344(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector348(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector34C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 196
+void Vector350(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector354(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector358(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector35C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 200
+void Vector360(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector364(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector368(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector36C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 204
+void Vector370(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector374(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector378(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector37C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 208
+void Vector380(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector384(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector388(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector38C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 212
+void Vector390(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector394(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector398(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector39C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 216
+void Vector3A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 220
+void Vector3B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 224
+void Vector3C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 228
+void Vector3D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 232
+void Vector3E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 236
+void Vector3F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#endif /* !defined(__DOXYGEN__) */
+
+/**
+ * @brief STM32 vectors table.
+ */
+#if !defined(__DOXYGEN__)
+#if !defined(VECTORS_SECTION)
+__attribute__ ((used, aligned(128), section(".vectors")))
+#else
+__attribute__ ((used, aligned(128), section(VECTORS_SECTION)))
+#endif
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+vectors_t _vectors = {
+/*lint -restore*/
+ &__main_stack_end__,Reset_Handler, NMI_Handler, HardFault_Handler,
+ MemManage_Handler, BusFault_Handler, UsageFault_Handler, Vector1C,
+ Vector20, Vector24, Vector28, SVC_Handler,
+ DebugMon_Handler, Vector34, PendSV_Handler, SysTick_Handler,
+ {
+ Vector40, Vector44, Vector48, Vector4C,
+#if CORTEX_NUM_VECTORS > 4
+ Vector50, Vector54, Vector58, Vector5C,
+#endif
+#if CORTEX_NUM_VECTORS > 8
+ Vector60, Vector64, Vector68, Vector6C,
+#endif
+#if CORTEX_NUM_VECTORS > 12
+ Vector70, Vector74, Vector78, Vector7C,
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ Vector80, Vector84, Vector88, Vector8C,
+#endif
+#if CORTEX_NUM_VECTORS > 20
+ Vector90, Vector94, Vector98, Vector9C,
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ VectorA0, VectorA4, VectorA8, VectorAC,
+#endif
+#if CORTEX_NUM_VECTORS > 28
+ VectorB0, VectorB4, VectorB8, VectorBC,
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ VectorC0, VectorC4, VectorC8, VectorCC,
+#endif
+#if CORTEX_NUM_VECTORS > 36
+ VectorD0, VectorD4, VectorD8, VectorDC,
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ VectorE0, VectorE4, VectorE8, VectorEC,
+#endif
+#if CORTEX_NUM_VECTORS > 44
+ VectorF0, VectorF4, VectorF8, VectorFC,
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ Vector100, Vector104, Vector108, Vector10C,
+#endif
+#if CORTEX_NUM_VECTORS > 52
+ Vector110, Vector114, Vector118, Vector11C,
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ Vector120, Vector124, Vector128, Vector12C,
+#endif
+#if CORTEX_NUM_VECTORS > 60
+ Vector130, Vector134, Vector138, Vector13C,
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ Vector140, Vector144, Vector148, Vector14C,
+#endif
+#if CORTEX_NUM_VECTORS > 68
+ Vector150, Vector154, Vector158, Vector15C,
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ Vector160, Vector164, Vector168, Vector16C,
+#endif
+#if CORTEX_NUM_VECTORS > 76
+ Vector170, Vector174, Vector178, Vector17C,
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ Vector180, Vector184, Vector188, Vector18C,
+#endif
+#if CORTEX_NUM_VECTORS > 84
+ Vector190, Vector194, Vector198, Vector19C,
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ Vector1A0, Vector1A4, Vector1A8, Vector1AC,
+#endif
+#if CORTEX_NUM_VECTORS > 92
+ Vector1B0, Vector1B4, Vector1B8, Vector1BC,
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ Vector1C0, Vector1C4, Vector1C8, Vector1CC,
+#endif
+#if CORTEX_NUM_VECTORS > 100
+ Vector1D0, Vector1D4, Vector1D8, Vector1DC,
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ Vector1E0, Vector1E4, Vector1E8, Vector1EC,
+#endif
+#if CORTEX_NUM_VECTORS > 108
+ Vector1F0, Vector1F4, Vector1F8, Vector1FC,
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ Vector200, Vector204, Vector208, Vector20C,
+#endif
+#if CORTEX_NUM_VECTORS > 116
+ Vector210, Vector214, Vector218, Vector21C,
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ Vector220, Vector224, Vector228, Vector22C,
+#endif
+#if CORTEX_NUM_VECTORS > 124
+ Vector230, Vector234, Vector238, Vector23C,
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ Vector240, Vector244, Vector248, Vector24C,
+#endif
+#if CORTEX_NUM_VECTORS > 132
+ Vector250, Vector254, Vector258, Vector25C,
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ Vector260, Vector264, Vector268, Vector26C,
+#endif
+#if CORTEX_NUM_VECTORS > 140
+ Vector270, Vector274, Vector278, Vector27C,
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ Vector280, Vector284, Vector288, Vector28C,
+#endif
+#if CORTEX_NUM_VECTORS > 148
+ Vector290, Vector294, Vector298, Vector29C,
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ Vector2A0, Vector2A4, Vector2A8, Vector2AC,
+#endif
+#if CORTEX_NUM_VECTORS > 156
+ Vector2B0, Vector2B4, Vector2B8, Vector2BC,
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ Vector2C0, Vector2C4, Vector2C8, Vector2CC,
+#endif
+#if CORTEX_NUM_VECTORS > 164
+ Vector2D0, Vector2D4, Vector2D8, Vector2DC,
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ Vector2E0, Vector2E4, Vector2E8, Vector2EC,
+#endif
+#if CORTEX_NUM_VECTORS > 172
+ Vector2F0, Vector2F4, Vector2F8, Vector2FC,
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ Vector300, Vector304, Vector308, Vector30C,
+#endif
+#if CORTEX_NUM_VECTORS > 180
+ Vector310, Vector314, Vector318, Vector31C,
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ Vector320, Vector324, Vector328, Vector32C,
+#endif
+#if CORTEX_NUM_VECTORS > 188
+ Vector330, Vector334, Vector338, Vector33C,
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ Vector340, Vector344, Vector348, Vector34C,
+#endif
+#if CORTEX_NUM_VECTORS > 196
+ Vector350, Vector354, Vector358, Vector35C,
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ Vector360, Vector364, Vector368, Vector36C,
+#endif
+#if CORTEX_NUM_VECTORS > 204
+ Vector370, Vector374, Vector378, Vector37C,
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ Vector380, Vector384, Vector388, Vector38C,
+#endif
+#if CORTEX_NUM_VECTORS > 212
+ Vector390, Vector394, Vector398, Vector39C,
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ Vector3A0, Vector3A4, Vector3A8, Vector3AC,
+#endif
+#if CORTEX_NUM_VECTORS > 220
+ Vector3B0, Vector3B4, Vector3B8, Vector3BC,
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ Vector3C0, Vector3C4, Vector3C8, Vector3CC,
+#endif
+#if CORTEX_NUM_VECTORS > 228
+ Vector3D0, Vector3D4, Vector3D8, Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ Vector3E0, Vector3E4, Vector3E8, Vector3EC
+#endif
+#if CORTEX_NUM_VECTORS > 236
+ Vector3F0, Vector3F4, Vector3F8, Vector3FC
+#endif
+ }
+};
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/vectors.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/vectors.h
new file mode 100644
index 0000000000..9cae96f949
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/GCC/vectors.h
@@ -0,0 +1,112 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/vectors.h
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#ifndef VECTORS_H
+#define VECTORS_H
+
+#include "cmparams.h"
+
+/* This inclusion can be used to remap vectors using different names.
+ * Example:
+ * #define Vector7C UartRX_Handler
+ * This can be useful when using 3rd part libraries that assume specific
+ * vector names.
+ */
+#if defined(VECTORS_USE_CONF)
+#include "vectorsconf.h"
+#endif
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+/**
+ * @brief Type of an IRQ vector.
+ */
+typedef void (*irq_vector_t)(void);
+
+/**
+ * @brief Type of a structure representing the whole vectors table.
+ */
+typedef struct {
+ uint32_t *init_stack;
+ irq_vector_t reset_handler;
+ irq_vector_t nmi_handler;
+ irq_vector_t hardfault_handler;
+ irq_vector_t memmanage_handler;
+ irq_vector_t busfault_handler;
+ irq_vector_t usagefault_handler;
+ irq_vector_t vector1c;
+ irq_vector_t vector20;
+ irq_vector_t vector24;
+ irq_vector_t vector28;
+ irq_vector_t svc_handler;
+ irq_vector_t debugmonitor_handler;
+ irq_vector_t vector34;
+ irq_vector_t pendsv_handler;
+ irq_vector_t systick_handler;
+ irq_vector_t vectors[CORTEX_NUM_VECTORS];
+} vectors_t;
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+extern vectors_t _vectors;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* VECTORS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/IAR/cstartup.s b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/IAR/cstartup.s
new file mode 100644
index 0000000000..4dd0272411
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/IAR/cstartup.s
@@ -0,0 +1,169 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/IAR/cstartup.s
+ * @brief Generic IAR Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_IAR_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+#define SCB_VTOR 0xE000ED08
+
+ /**
+ * @brief VTOR special register initialization.
+ * @details VTOR is initialized to point to the vectors table.
+ * @note IAR assembler #if directive conditions do not work like C/C++ conditions.
+ * @details Set to 0 to disable the function, 1 to enable
+ */
+#ifndef CRT0_VTOR_INIT
+#define CRT0_VTOR_INIT 1
+#endif
+/**
+ * @brief Stack segments initialization value.
+ */
+#ifndef CRT0_STACKS_FILL_PATTERN
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ * @details Set to 0 to disable the function, 1 to enable
+ */
+#ifndef CRT0_INIT_STACKS
+#define CRT0_INIT_STACKS 1
+#endif
+
+/**
+ * @brief Heap segment initialization value.
+ */
+#ifndef CRT0_HEAP_FILL_PATTERN
+#define CRT0_HEAP_FILL_PATTERN 0xCCCCCCCC
+#endif
+
+/**
+ * @brief Heap segment initialization switch.
+ * @details Set to 0 to disable the function, 1 to enable
+ */
+#ifndef CRT0_INIT_HEAP
+#define CRT0_INIT_HEAP 1
+#endif
+
+
+ MODULE ?cstartup
+
+CONTROL_MODE_PRIVILEGED SET 0
+CONTROL_MODE_UNPRIVILEGED SET 1
+CONTROL_USE_MSP SET 0
+CONTROL_USE_PSP SET 2
+
+ AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
+ PRESERVE8
+
+ SECTION HEAP:DATA:NOROOT(3)
+ PUBLIC __heap_base__
+__heap_base__: /* Note: heap section defines sysheap base */
+
+ SECTION SYSHEAP:DATA:NOROOT(3)
+ PUBLIC __heap_end__
+__heap_end__: /* Note: sysheap section defines sysheap end */
+
+ PUBLIC __iar_program_start
+ EXTWEAK __iar_init_core
+ EXTWEAK __iar_init_vfp
+ EXTERN __cmain
+ EXTERN __vector_table
+ EXTERN __main_stack_base__
+ EXTERN __main_stack_end__
+ EXTERN __process_stack_base__
+ EXTERN __process_stack_end__
+
+ SECTION IRQSTACK:DATA:NOROOT(3)
+ SECTION CSTACK:DATA:NOROOT(3)
+ SECTION .text:CODE:REORDER(2)
+ THUMB
+
+__iar_program_start:
+ cpsid i
+ ldr r0, =SFE(IRQSTACK)
+ msr MSP, r0
+ ldr r0, =SFE(CSTACK)
+ msr PSP, r0
+ movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
+ msr CONTROL, r0
+ isb
+
+#if (CRT0_VTOR_INIT)
+ ldr r0, =__vector_table
+ movw r1, #SCB_VTOR & 0xFFFF
+ movt r1, #SCB_VTOR >> 16
+ str r0, [r1]
+#endif
+
+#if (CRT0_INIT_STACKS)
+ ldr r0, =CRT0_STACKS_FILL_PATTERN
+ /* Main Stack initialization. Note, it assumes that the stack size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__main_stack_base__
+ ldr r2, =__main_stack_end__
+msloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo msloop
+
+ /* Process Stack initialization. Note, it assumes that the stack size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__process_stack_base__
+ ldr r2, =__process_stack_end__
+psloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo psloop
+#endif
+
+#if (CRT0_INIT_HEAP)
+ ldr r0, =CRT0_HEAP_FILL_PATTERN
+ /* Sys Heap initialization. Note, it assumes that the heap size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__heap_base__
+ ldr r2, =__heap_end__
+hloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo hloop
+#endif
+
+ bl __early_init
+ bl __iar_init_core
+ bl __iar_init_vfp
+ b __cmain
+
+ SECTION .text:CODE:NOROOT:REORDER(2)
+ PUBWEAK __early_init
+__early_init:
+ bx lr
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/IAR/vectors.s b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/IAR/vectors.s
new file mode 100644
index 0000000000..9609f74c5f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/IAR/vectors.s
@@ -0,0 +1,1006 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/IAR/vectors.c
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_IAR_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if !defined(__DOXYGEN__)
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+ MODULE ?vectors
+
+ AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
+ PRESERVE8
+
+ SECTION IRQSTACK:DATA:NOROOT(3)
+ SECTION .intvec:CODE:NOROOT(3)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table:
+ DCD SFE(IRQSTACK)
+ DCD __iar_program_start
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD Vector1C
+ DCD Vector20
+ DCD Vector24
+ DCD Vector28
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD Vector34
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+ DCD Vector40
+ DCD Vector44
+ DCD Vector48
+ DCD Vector4C
+ DCD Vector50
+ DCD Vector54
+ DCD Vector58
+ DCD Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ DCD Vector60
+ DCD Vector64
+ DCD Vector68
+ DCD Vector6C
+ DCD Vector70
+ DCD Vector74
+ DCD Vector78
+ DCD Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ DCD Vector80
+ DCD Vector84
+ DCD Vector88
+ DCD Vector8C
+ DCD Vector90
+ DCD Vector94
+ DCD Vector98
+ DCD Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ DCD VectorA0
+ DCD VectorA4
+ DCD VectorA8
+ DCD VectorAC
+ DCD VectorB0
+ DCD VectorB4
+ DCD VectorB8
+ DCD VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ DCD VectorC0
+ DCD VectorC4
+ DCD VectorC8
+ DCD VectorCC
+ DCD VectorD0
+ DCD VectorD4
+ DCD VectorD8
+ DCD VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ DCD VectorE0
+ DCD VectorE4
+ DCD VectorE8
+ DCD VectorEC
+ DCD VectorF0
+ DCD VectorF4
+ DCD VectorF8
+ DCD VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ DCD Vector100
+ DCD Vector104
+ DCD Vector108
+ DCD Vector10C
+ DCD Vector110
+ DCD Vector114
+ DCD Vector118
+ DCD Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ DCD Vector120
+ DCD Vector124
+ DCD Vector128
+ DCD Vector12C
+ DCD Vector130
+ DCD Vector134
+ DCD Vector138
+ DCD Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ DCD Vector140
+ DCD Vector144
+ DCD Vector148
+ DCD Vector14C
+ DCD Vector150
+ DCD Vector154
+ DCD Vector158
+ DCD Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ DCD Vector160
+ DCD Vector164
+ DCD Vector168
+ DCD Vector16C
+ DCD Vector170
+ DCD Vector174
+ DCD Vector178
+ DCD Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ DCD Vector180
+ DCD Vector184
+ DCD Vector188
+ DCD Vector18C
+ DCD Vector190
+ DCD Vector194
+ DCD Vector198
+ DCD Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ DCD Vector1A0
+ DCD Vector1A4
+ DCD Vector1A8
+ DCD Vector1AC
+ DCD Vector1B0
+ DCD Vector1B4
+ DCD Vector1B8
+ DCD Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ DCD Vector1C0
+ DCD Vector1C4
+ DCD Vector1C8
+ DCD Vector1CC
+ DCD Vector1D0
+ DCD Vector1D4
+ DCD Vector1D8
+ DCD Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ DCD Vector1E0
+ DCD Vector1E4
+ DCD Vector1E8
+ DCD Vector1EC
+ DCD Vector1F0
+ DCD Vector1F4
+ DCD Vector1F8
+ DCD Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ DCD Vector200
+ DCD Vector204
+ DCD Vector208
+ DCD Vector20C
+ DCD Vector210
+ DCD Vector214
+ DCD Vector218
+ DCD Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ DCD Vector220
+ DCD Vector224
+ DCD Vector228
+ DCD Vector22C
+ DCD Vector230
+ DCD Vector234
+ DCD Vector238
+ DCD Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ DCD Vector240
+ DCD Vector244
+ DCD Vector248
+ DCD Vector24C
+ DCD Vector250
+ DCD Vector254
+ DCD Vector258
+ DCD Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ DCD Vector260
+ DCD Vector264
+ DCD Vector268
+ DCD Vector26C
+ DCD Vector270
+ DCD Vector274
+ DCD Vector278
+ DCD Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ DCD Vector280
+ DCD Vector284
+ DCD Vector288
+ DCD Vector28C
+ DCD Vector290
+ DCD Vector294
+ DCD Vector298
+ DCD Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ DCD Vector2A0
+ DCD Vector2A4
+ DCD Vector2A8
+ DCD Vector2AC
+ DCD Vector2B0
+ DCD Vector2B4
+ DCD Vector2B8
+ DCD Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ DCD Vector2C0
+ DCD Vector2C4
+ DCD Vector2C8
+ DCD Vector2CC
+ DCD Vector2D0
+ DCD Vector2D4
+ DCD Vector2D8
+ DCD Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ DCD Vector2E0
+ DCD Vector2E4
+ DCD Vector2E8
+ DCD Vector2EC
+ DCD Vector2F0
+ DCD Vector2F4
+ DCD Vector2F8
+ DCD Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ DCD Vector300
+ DCD Vector304
+ DCD Vector308
+ DCD Vector30C
+ DCD Vector310
+ DCD Vector314
+ DCD Vector318
+ DCD Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ DCD Vector320
+ DCD Vector324
+ DCD Vector328
+ DCD Vector32C
+ DCD Vector330
+ DCD Vector334
+ DCD Vector338
+ DCD Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ DCD Vector340
+ DCD Vector344
+ DCD Vector348
+ DCD Vector34C
+ DCD Vector350
+ DCD Vector354
+ DCD Vector358
+ DCD Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ DCD Vector360
+ DCD Vector364
+ DCD Vector368
+ DCD Vector36C
+ DCD Vector370
+ DCD Vector374
+ DCD Vector378
+ DCD Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ DCD Vector380
+ DCD Vector384
+ DCD Vector388
+ DCD Vector38C
+ DCD Vector390
+ DCD Vector394
+ DCD Vector398
+ DCD Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ DCD Vector3A0
+ DCD Vector3A4
+ DCD Vector3A8
+ DCD Vector3AC
+ DCD Vector3B0
+ DCD Vector3B4
+ DCD Vector3B8
+ DCD Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ DCD Vector3C0
+ DCD Vector3C4
+ DCD Vector3C8
+ DCD Vector3CC
+ DCD Vector3D0
+ DCD Vector3D4
+ DCD Vector3D8
+ DCD Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ DCD Vector3E0
+ DCD Vector3E4
+ DCD Vector3E8
+ DCD Vector3EC
+ DCD Vector3F0
+ DCD Vector3F4
+ DCD Vector3F8
+ DCD Vector3FC
+#endif
+
+/*
+ * Default interrupt handlers.
+ */
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK Vector1C
+ PUBWEAK Vector20
+ PUBWEAK Vector24
+ PUBWEAK Vector28
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK Vector34
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK Vector40
+ PUBWEAK Vector44
+ PUBWEAK Vector48
+ PUBWEAK Vector4C
+ PUBWEAK Vector50
+ PUBWEAK Vector54
+ PUBWEAK Vector58
+ PUBWEAK Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ PUBWEAK Vector60
+ PUBWEAK Vector64
+ PUBWEAK Vector68
+ PUBWEAK Vector6C
+ PUBWEAK Vector70
+ PUBWEAK Vector74
+ PUBWEAK Vector78
+ PUBWEAK Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ PUBWEAK Vector80
+ PUBWEAK Vector84
+ PUBWEAK Vector88
+ PUBWEAK Vector8C
+ PUBWEAK Vector90
+ PUBWEAK Vector94
+ PUBWEAK Vector98
+ PUBWEAK Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ PUBWEAK VectorA0
+ PUBWEAK VectorA4
+ PUBWEAK VectorA8
+ PUBWEAK VectorAC
+ PUBWEAK VectorB0
+ PUBWEAK VectorB4
+ PUBWEAK VectorB8
+ PUBWEAK VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ PUBWEAK VectorC0
+ PUBWEAK VectorC4
+ PUBWEAK VectorC8
+ PUBWEAK VectorCC
+ PUBWEAK VectorD0
+ PUBWEAK VectorD4
+ PUBWEAK VectorD8
+ PUBWEAK VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ PUBWEAK VectorE0
+ PUBWEAK VectorE4
+ PUBWEAK VectorE8
+ PUBWEAK VectorEC
+ PUBWEAK VectorF0
+ PUBWEAK VectorF4
+ PUBWEAK VectorF8
+ PUBWEAK VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ PUBWEAK Vector100
+ PUBWEAK Vector104
+ PUBWEAK Vector108
+ PUBWEAK Vector10C
+ PUBWEAK Vector110
+ PUBWEAK Vector114
+ PUBWEAK Vector118
+ PUBWEAK Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ PUBWEAK Vector120
+ PUBWEAK Vector124
+ PUBWEAK Vector128
+ PUBWEAK Vector12C
+ PUBWEAK Vector130
+ PUBWEAK Vector134
+ PUBWEAK Vector138
+ PUBWEAK Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ PUBWEAK Vector140
+ PUBWEAK Vector144
+ PUBWEAK Vector148
+ PUBWEAK Vector14C
+ PUBWEAK Vector150
+ PUBWEAK Vector154
+ PUBWEAK Vector158
+ PUBWEAK Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ PUBWEAK Vector160
+ PUBWEAK Vector164
+ PUBWEAK Vector168
+ PUBWEAK Vector16C
+ PUBWEAK Vector170
+ PUBWEAK Vector174
+ PUBWEAK Vector178
+ PUBWEAK Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ PUBWEAK Vector180
+ PUBWEAK Vector184
+ PUBWEAK Vector188
+ PUBWEAK Vector18C
+ PUBWEAK Vector190
+ PUBWEAK Vector194
+ PUBWEAK Vector198
+ PUBWEAK Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ PUBWEAK Vector1A0
+ PUBWEAK Vector1A4
+ PUBWEAK Vector1A8
+ PUBWEAK Vector1AC
+ PUBWEAK Vector1B0
+ PUBWEAK Vector1B4
+ PUBWEAK Vector1B8
+ PUBWEAK Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ PUBWEAK Vector1C0
+ PUBWEAK Vector1C4
+ PUBWEAK Vector1C8
+ PUBWEAK Vector1CC
+ PUBWEAK Vector1D0
+ PUBWEAK Vector1D4
+ PUBWEAK Vector1D8
+ PUBWEAK Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ PUBWEAK Vector1E0
+ PUBWEAK Vector1E4
+ PUBWEAK Vector1E8
+ PUBWEAK Vector1EC
+ PUBWEAK Vector1F0
+ PUBWEAK Vector1F4
+ PUBWEAK Vector1F8
+ PUBWEAK Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ PUBWEAK Vector200
+ PUBWEAK Vector204
+ PUBWEAK Vector208
+ PUBWEAK Vector20C
+ PUBWEAK Vector210
+ PUBWEAK Vector214
+ PUBWEAK Vector218
+ PUBWEAK Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ PUBWEAK Vector220
+ PUBWEAK Vector224
+ PUBWEAK Vector228
+ PUBWEAK Vector22C
+ PUBWEAK Vector230
+ PUBWEAK Vector234
+ PUBWEAK Vector238
+ PUBWEAK Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ PUBWEAK Vector240
+ PUBWEAK Vector244
+ PUBWEAK Vector248
+ PUBWEAK Vector24C
+ PUBWEAK Vector250
+ PUBWEAK Vector254
+ PUBWEAK Vector258
+ PUBWEAK Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ PUBWEAK Vector260
+ PUBWEAK Vector264
+ PUBWEAK Vector268
+ PUBWEAK Vector26C
+ PUBWEAK Vector270
+ PUBWEAK Vector274
+ PUBWEAK Vector278
+ PUBWEAK Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ PUBWEAK Vector280
+ PUBWEAK Vector284
+ PUBWEAK Vector288
+ PUBWEAK Vector28C
+ PUBWEAK Vector290
+ PUBWEAK Vector294
+ PUBWEAK Vector298
+ PUBWEAK Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ PUBWEAK Vector2A0
+ PUBWEAK Vector2A4
+ PUBWEAK Vector2A8
+ PUBWEAK Vector2AC
+ PUBWEAK Vector2B0
+ PUBWEAK Vector2B4
+ PUBWEAK Vector2B8
+ PUBWEAK Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ PUBWEAK Vector2C0
+ PUBWEAK Vector2C4
+ PUBWEAK Vector2C8
+ PUBWEAK Vector2CC
+ PUBWEAK Vector2D0
+ PUBWEAK Vector2D4
+ PUBWEAK Vector2D8
+ PUBWEAK Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ PUBWEAK Vector2E0
+ PUBWEAK Vector2E4
+ PUBWEAK Vector2E8
+ PUBWEAK Vector2EC
+ PUBWEAK Vector2F0
+ PUBWEAK Vector2F4
+ PUBWEAK Vector2F8
+ PUBWEAK Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ PUBWEAK Vector300
+ PUBWEAK Vector304
+ PUBWEAK Vector308
+ PUBWEAK Vector30C
+ PUBWEAK Vector310
+ PUBWEAK Vector314
+ PUBWEAK Vector318
+ PUBWEAK Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ PUBWEAK Vector320
+ PUBWEAK Vector324
+ PUBWEAK Vector328
+ PUBWEAK Vector32C
+ PUBWEAK Vector330
+ PUBWEAK Vector334
+ PUBWEAK Vector338
+ PUBWEAK Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ PUBWEAK Vector340
+ PUBWEAK Vector344
+ PUBWEAK Vector348
+ PUBWEAK Vector34C
+ PUBWEAK Vector350
+ PUBWEAK Vector354
+ PUBWEAK Vector358
+ PUBWEAK Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ PUBWEAK Vector360
+ PUBWEAK Vector364
+ PUBWEAK Vector368
+ PUBWEAK Vector36C
+ PUBWEAK Vector370
+ PUBWEAK Vector374
+ PUBWEAK Vector378
+ PUBWEAK Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ PUBWEAK Vector380
+ PUBWEAK Vector384
+ PUBWEAK Vector388
+ PUBWEAK Vector38C
+ PUBWEAK Vector390
+ PUBWEAK Vector394
+ PUBWEAK Vector398
+ PUBWEAK Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ PUBWEAK Vector3A0
+ PUBWEAK Vector3A4
+ PUBWEAK Vector3A8
+ PUBWEAK Vector3AC
+ PUBWEAK Vector3B0
+ PUBWEAK Vector3B4
+ PUBWEAK Vector3B8
+ PUBWEAK Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ PUBWEAK Vector3C0
+ PUBWEAK Vector3C4
+ PUBWEAK Vector3C8
+ PUBWEAK Vector3CC
+ PUBWEAK Vector3D0
+ PUBWEAK Vector3D4
+ PUBWEAK Vector3D8
+ PUBWEAK Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ PUBWEAK Vector3E0
+ PUBWEAK Vector3E4
+ PUBWEAK Vector3E8
+ PUBWEAK Vector3EC
+ PUBWEAK Vector3F0
+ PUBWEAK Vector3F4
+ PUBWEAK Vector3F8
+ PUBWEAK Vector3FC
+#endif
+ PUBLIC _unhandled_exception
+
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+Vector1C
+Vector20
+Vector24
+Vector28
+SVC_Handler
+DebugMon_Handler
+Vector34
+PendSV_Handler
+SysTick_Handler
+Vector40
+Vector44
+Vector48
+Vector4C
+Vector50
+Vector54
+Vector58
+Vector5C
+#if CORTEX_NUM_VECTORS > 8
+Vector60
+Vector64
+Vector68
+Vector6C
+Vector70
+Vector74
+Vector78
+Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+Vector80
+Vector84
+Vector88
+Vector8C
+Vector90
+Vector94
+Vector98
+Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+VectorA0
+VectorA4
+VectorA8
+VectorAC
+VectorB0
+VectorB4
+VectorB8
+VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+VectorC0
+VectorC4
+VectorC8
+VectorCC
+VectorD0
+VectorD4
+VectorD8
+VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+VectorE0
+VectorE4
+VectorE8
+VectorEC
+VectorF0
+VectorF4
+VectorF8
+VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+Vector100
+Vector104
+Vector108
+Vector10C
+Vector110
+Vector114
+Vector118
+Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+Vector120
+Vector124
+Vector128
+Vector12C
+Vector130
+Vector134
+Vector138
+Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+Vector140
+Vector144
+Vector148
+Vector14C
+Vector150
+Vector154
+Vector158
+Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+Vector160
+Vector164
+Vector168
+Vector16C
+Vector170
+Vector174
+Vector178
+Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+Vector180
+Vector184
+Vector188
+Vector18C
+Vector190
+Vector194
+Vector198
+Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+Vector1A0
+Vector1A4
+Vector1A8
+Vector1AC
+Vector1B0
+Vector1B4
+Vector1B8
+Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+Vector1C0
+Vector1C4
+Vector1C8
+Vector1CC
+Vector1D0
+Vector1D4
+Vector1D8
+Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+Vector1E0
+Vector1E4
+Vector1E8
+Vector1EC
+Vector1F0
+Vector1F4
+Vector1F8
+Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+Vector200
+Vector204
+Vector208
+Vector20C
+Vector210
+Vector214
+Vector218
+Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+Vector220
+Vector224
+Vector228
+Vector22C
+Vector230
+Vector234
+Vector238
+Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+Vector240
+Vector244
+Vector248
+Vector24C
+Vector250
+Vector254
+Vector258
+Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+Vector260
+Vector264
+Vector268
+Vector26C
+Vector270
+Vector274
+Vector278
+Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+Vector280
+Vector284
+Vector288
+Vector28C
+Vector290
+Vector294
+Vector298
+Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+Vector2A0
+Vector2A4
+Vector2A8
+Vector2AC
+Vector2B0
+Vector2B4
+Vector2B8
+Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+Vector2C0
+Vector2C4
+Vector2C8
+Vector2CC
+Vector2D0
+Vector2D4
+Vector2D8
+Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+Vector2E0
+Vector2E4
+Vector2E8
+Vector2EC
+Vector2F0
+Vector2F4
+Vector2F8
+Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+Vector300
+Vector304
+Vector308
+Vector30C
+Vector310
+Vector314
+Vector318
+Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+Vector320
+Vector324
+Vector328
+Vector32C
+Vector330
+Vector334
+Vector338
+Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+Vector340
+Vector344
+Vector348
+Vector34C
+Vector350
+Vector354
+Vector358
+Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+Vector360
+Vector364
+Vector368
+Vector36C
+Vector370
+Vector374
+Vector378
+Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+Vector380
+Vector384
+Vector388
+Vector38C
+Vector390
+Vector394
+Vector398
+Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+Vector3A0
+Vector3A4
+Vector3A8
+Vector3AC
+Vector3B0
+Vector3B4
+Vector3B8
+Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+Vector3C0
+Vector3C4
+Vector3C8
+Vector3CC
+Vector3D0
+Vector3D4
+Vector3D8
+Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+Vector3E0
+Vector3E4
+Vector3E8
+Vector3EC
+Vector3F0
+Vector3F4
+Vector3F8
+Vector3FC
+#endif
+_unhandled_exception
+ b _unhandled_exception
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/RVCT/cstartup.s b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/RVCT/cstartup.s
new file mode 100644
index 0000000000..6250f1d67f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/RVCT/cstartup.s
@@ -0,0 +1,131 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/RVCT/cstartup.s
+ * @brief Generic RVCT Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_RVCT_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+;/* <<< Use Configuration Wizard in Context Menu >>> */
+
+;// Main Stack Configuration (IRQ Stack)
+;// Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;//
+main_stack_size EQU 0x00000400
+
+;// Process Stack Configuration
+;// Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;//
+proc_stack_size EQU 0x00000400
+
+;// C-runtime heap size
+;// C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8>
+;//
+heap_size EQU 0x00000400
+
+ AREA MSTACK, NOINIT, READWRITE, ALIGN=3
+main_stack_mem SPACE main_stack_size
+ EXPORT __initial_msp
+__initial_msp
+
+ AREA CSTACK, NOINIT, READWRITE, ALIGN=3
+__main_thread_stack_base__
+ EXPORT __main_thread_stack_base__
+proc_stack_mem SPACE proc_stack_size
+ EXPORT __initial_sp
+__initial_sp
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE heap_size
+__heap_limit
+
+CONTROL_MODE_PRIVILEGED EQU 0
+CONTROL_MODE_UNPRIVILEGED EQU 1
+CONTROL_USE_MSP EQU 0
+CONTROL_USE_PSP EQU 2
+
+ PRESERVE8
+ THUMB
+
+ AREA |.text|, CODE, READONLY
+
+/*
+ * Reset handler.
+ */
+ IMPORT __main
+ EXPORT Reset_Handler
+Reset_Handler PROC
+ cpsid i
+ ldr r0, =__initial_sp
+ msr PSP, r0
+ movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP
+ msr CONTROL, r0
+ isb
+ bl __early_init
+
+ IF {CPU} = "Cortex-M4.fp"
+ LDR R0, =0xE000ED88 ; Enable CP10,CP11
+ LDR R1, [R0]
+ ORR R1, R1, #(0xF << 20)
+ STR R1, [R0]
+ ENDIF
+
+ ldr r0, =__main
+ bx r0
+ ENDP
+
+__early_init PROC
+ EXPORT __early_init [WEAK]
+ bx lr
+ ENDP
+
+ ALIGN
+
+/*
+ * User Initial Stack & Heap.
+ */
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+ ldr r0, =Heap_Mem
+ ldr r1, =(proc_stack_mem + proc_stack_size)
+ ldr r2, =(Heap_Mem + heap_size)
+ ldr r3, =proc_stack_mem
+ bx lr
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/RVCT/vectors.s b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/RVCT/vectors.s
new file mode 100644
index 0000000000..a95e239c77
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/compilers/RVCT/vectors.s
@@ -0,0 +1,1002 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/RVCT/vectors.c
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_RVCT_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if !defined(__DOXYGEN__)
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+ PRESERVE8
+
+ AREA RESET, DATA, READONLY
+
+ IMPORT __initial_msp
+ IMPORT Reset_Handler
+ EXPORT __Vectors
+
+__Vectors
+ DCD __initial_msp
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD Vector1C
+ DCD Vector20
+ DCD Vector24
+ DCD Vector28
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD Vector34
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+ DCD Vector40
+ DCD Vector44
+ DCD Vector48
+ DCD Vector4C
+ DCD Vector50
+ DCD Vector54
+ DCD Vector58
+ DCD Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ DCD Vector60
+ DCD Vector64
+ DCD Vector68
+ DCD Vector6C
+ DCD Vector70
+ DCD Vector74
+ DCD Vector78
+ DCD Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ DCD Vector80
+ DCD Vector84
+ DCD Vector88
+ DCD Vector8C
+ DCD Vector90
+ DCD Vector94
+ DCD Vector98
+ DCD Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ DCD VectorA0
+ DCD VectorA4
+ DCD VectorA8
+ DCD VectorAC
+ DCD VectorB0
+ DCD VectorB4
+ DCD VectorB8
+ DCD VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ DCD VectorC0
+ DCD VectorC4
+ DCD VectorC8
+ DCD VectorCC
+ DCD VectorD0
+ DCD VectorD4
+ DCD VectorD8
+ DCD VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ DCD VectorE0
+ DCD VectorE4
+ DCD VectorE8
+ DCD VectorEC
+ DCD VectorF0
+ DCD VectorF4
+ DCD VectorF8
+ DCD VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ DCD Vector100
+ DCD Vector104
+ DCD Vector108
+ DCD Vector10C
+ DCD Vector110
+ DCD Vector114
+ DCD Vector118
+ DCD Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ DCD Vector120
+ DCD Vector124
+ DCD Vector128
+ DCD Vector12C
+ DCD Vector130
+ DCD Vector134
+ DCD Vector138
+ DCD Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ DCD Vector140
+ DCD Vector144
+ DCD Vector148
+ DCD Vector14C
+ DCD Vector150
+ DCD Vector154
+ DCD Vector158
+ DCD Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ DCD Vector160
+ DCD Vector164
+ DCD Vector168
+ DCD Vector16C
+ DCD Vector170
+ DCD Vector174
+ DCD Vector178
+ DCD Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ DCD Vector180
+ DCD Vector184
+ DCD Vector188
+ DCD Vector18C
+ DCD Vector190
+ DCD Vector194
+ DCD Vector198
+ DCD Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ DCD Vector1A0
+ DCD Vector1A4
+ DCD Vector1A8
+ DCD Vector1AC
+ DCD Vector1B0
+ DCD Vector1B4
+ DCD Vector1B8
+ DCD Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ DCD Vector1C0
+ DCD Vector1C4
+ DCD Vector1C8
+ DCD Vector1CC
+ DCD Vector1D0
+ DCD Vector1D4
+ DCD Vector1D8
+ DCD Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ DCD Vector1E0
+ DCD Vector1E4
+ DCD Vector1E8
+ DCD Vector1EC
+ DCD Vector1F0
+ DCD Vector1F4
+ DCD Vector1F8
+ DCD Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ DCD Vector200
+ DCD Vector204
+ DCD Vector208
+ DCD Vector20C
+ DCD Vector210
+ DCD Vector214
+ DCD Vector218
+ DCD Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ DCD Vector220
+ DCD Vector224
+ DCD Vector228
+ DCD Vector22C
+ DCD Vector230
+ DCD Vector234
+ DCD Vector238
+ DCD Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ DCD Vector240
+ DCD Vector244
+ DCD Vector248
+ DCD Vector24C
+ DCD Vector250
+ DCD Vector254
+ DCD Vector258
+ DCD Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ DCD Vector260
+ DCD Vector264
+ DCD Vector268
+ DCD Vector26C
+ DCD Vector270
+ DCD Vector274
+ DCD Vector278
+ DCD Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ DCD Vector280
+ DCD Vector284
+ DCD Vector288
+ DCD Vector28C
+ DCD Vector290
+ DCD Vector294
+ DCD Vector298
+ DCD Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ DCD Vector2A0
+ DCD Vector2A4
+ DCD Vector2A8
+ DCD Vector2AC
+ DCD Vector2B0
+ DCD Vector2B4
+ DCD Vector2B8
+ DCD Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ DCD Vector2C0
+ DCD Vector2C4
+ DCD Vector2C8
+ DCD Vector2CC
+ DCD Vector2D0
+ DCD Vector2D4
+ DCD Vector2D8
+ DCD Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ DCD Vector2E0
+ DCD Vector2E4
+ DCD Vector2E8
+ DCD Vector2EC
+ DCD Vector2F0
+ DCD Vector2F4
+ DCD Vector2F8
+ DCD Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ DCD Vector300
+ DCD Vector304
+ DCD Vector308
+ DCD Vector30C
+ DCD Vector310
+ DCD Vector314
+ DCD Vector318
+ DCD Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ DCD Vector320
+ DCD Vector324
+ DCD Vector328
+ DCD Vector32C
+ DCD Vector330
+ DCD Vector334
+ DCD Vector338
+ DCD Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ DCD Vector340
+ DCD Vector344
+ DCD Vector348
+ DCD Vector34C
+ DCD Vector350
+ DCD Vector354
+ DCD Vector358
+ DCD Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ DCD Vector360
+ DCD Vector364
+ DCD Vector368
+ DCD Vector36C
+ DCD Vector370
+ DCD Vector374
+ DCD Vector378
+ DCD Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ DCD Vector380
+ DCD Vector384
+ DCD Vector388
+ DCD Vector38C
+ DCD Vector390
+ DCD Vector394
+ DCD Vector398
+ DCD Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ DCD Vector3A0
+ DCD Vector3A4
+ DCD Vector3A8
+ DCD Vector3AC
+ DCD Vector3B0
+ DCD Vector3B4
+ DCD Vector3B8
+ DCD Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ DCD Vector3C0
+ DCD Vector3C4
+ DCD Vector3C8
+ DCD Vector3CC
+ DCD Vector3D0
+ DCD Vector3D4
+ DCD Vector3D8
+ DCD Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ DCD Vector3E0
+ DCD Vector3E4
+ DCD Vector3E8
+ DCD Vector3EC
+ DCD Vector3F0
+ DCD Vector3F4
+ DCD Vector3F8
+ DCD Vector3FC
+#endif
+
+ AREA |.text|, CODE, READONLY
+ THUMB
+
+/*
+ * Default interrupt handlers.
+ */
+ EXPORT _unhandled_exception
+_unhandled_exception PROC
+ EXPORT NMI_Handler [WEAK]
+ EXPORT HardFault_Handler [WEAK]
+ EXPORT MemManage_Handler [WEAK]
+ EXPORT BusFault_Handler [WEAK]
+ EXPORT UsageFault_Handler [WEAK]
+ EXPORT Vector1C [WEAK]
+ EXPORT Vector20 [WEAK]
+ EXPORT Vector24 [WEAK]
+ EXPORT Vector28 [WEAK]
+ EXPORT SVC_Handler [WEAK]
+ EXPORT DebugMon_Handler [WEAK]
+ EXPORT Vector34 [WEAK]
+ EXPORT PendSV_Handler [WEAK]
+ EXPORT SysTick_Handler [WEAK]
+ EXPORT Vector40 [WEAK]
+ EXPORT Vector44 [WEAK]
+ EXPORT Vector48 [WEAK]
+ EXPORT Vector4C [WEAK]
+ EXPORT Vector50 [WEAK]
+ EXPORT Vector54 [WEAK]
+ EXPORT Vector58 [WEAK]
+ EXPORT Vector5C [WEAK]
+#if CORTEX_NUM_VECTORS > 8
+ EXPORT Vector60 [WEAK]
+ EXPORT Vector64 [WEAK]
+ EXPORT Vector68 [WEAK]
+ EXPORT Vector6C [WEAK]
+ EXPORT Vector70 [WEAK]
+ EXPORT Vector74 [WEAK]
+ EXPORT Vector78 [WEAK]
+ EXPORT Vector7C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ EXPORT Vector80 [WEAK]
+ EXPORT Vector84 [WEAK]
+ EXPORT Vector88 [WEAK]
+ EXPORT Vector8C [WEAK]
+ EXPORT Vector90 [WEAK]
+ EXPORT Vector94 [WEAK]
+ EXPORT Vector98 [WEAK]
+ EXPORT Vector9C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ EXPORT VectorA0 [WEAK]
+ EXPORT VectorA4 [WEAK]
+ EXPORT VectorA8 [WEAK]
+ EXPORT VectorAC [WEAK]
+ EXPORT VectorB0 [WEAK]
+ EXPORT VectorB4 [WEAK]
+ EXPORT VectorB8 [WEAK]
+ EXPORT VectorBC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ EXPORT VectorC0 [WEAK]
+ EXPORT VectorC4 [WEAK]
+ EXPORT VectorC8 [WEAK]
+ EXPORT VectorCC [WEAK]
+ EXPORT VectorD0 [WEAK]
+ EXPORT VectorD4 [WEAK]
+ EXPORT VectorD8 [WEAK]
+ EXPORT VectorDC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ EXPORT VectorE0 [WEAK]
+ EXPORT VectorE4 [WEAK]
+ EXPORT VectorE8 [WEAK]
+ EXPORT VectorEC [WEAK]
+ EXPORT VectorF0 [WEAK]
+ EXPORT VectorF4 [WEAK]
+ EXPORT VectorF8 [WEAK]
+ EXPORT VectorFC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ EXPORT Vector100 [WEAK]
+ EXPORT Vector104 [WEAK]
+ EXPORT Vector108 [WEAK]
+ EXPORT Vector10C [WEAK]
+ EXPORT Vector110 [WEAK]
+ EXPORT Vector114 [WEAK]
+ EXPORT Vector118 [WEAK]
+ EXPORT Vector11C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ EXPORT Vector120 [WEAK]
+ EXPORT Vector124 [WEAK]
+ EXPORT Vector128 [WEAK]
+ EXPORT Vector12C [WEAK]
+ EXPORT Vector130 [WEAK]
+ EXPORT Vector134 [WEAK]
+ EXPORT Vector138 [WEAK]
+ EXPORT Vector13C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ EXPORT Vector140 [WEAK]
+ EXPORT Vector144 [WEAK]
+ EXPORT Vector148 [WEAK]
+ EXPORT Vector14C [WEAK]
+ EXPORT Vector150 [WEAK]
+ EXPORT Vector154 [WEAK]
+ EXPORT Vector158 [WEAK]
+ EXPORT Vector15C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ EXPORT Vector160 [WEAK]
+ EXPORT Vector164 [WEAK]
+ EXPORT Vector168 [WEAK]
+ EXPORT Vector16C [WEAK]
+ EXPORT Vector170 [WEAK]
+ EXPORT Vector174 [WEAK]
+ EXPORT Vector178 [WEAK]
+ EXPORT Vector17C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ EXPORT Vector180 [WEAK]
+ EXPORT Vector184 [WEAK]
+ EXPORT Vector188 [WEAK]
+ EXPORT Vector18C [WEAK]
+ EXPORT Vector190 [WEAK]
+ EXPORT Vector194 [WEAK]
+ EXPORT Vector198 [WEAK]
+ EXPORT Vector19C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ EXPORT Vector1A0 [WEAK]
+ EXPORT Vector1A4 [WEAK]
+ EXPORT Vector1A8 [WEAK]
+ EXPORT Vector1AC [WEAK]
+ EXPORT Vector1B0 [WEAK]
+ EXPORT Vector1B4 [WEAK]
+ EXPORT Vector1B8 [WEAK]
+ EXPORT Vector1BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ EXPORT Vector1C0 [WEAK]
+ EXPORT Vector1C4 [WEAK]
+ EXPORT Vector1C8 [WEAK]
+ EXPORT Vector1CC [WEAK]
+ EXPORT Vector1D0 [WEAK]
+ EXPORT Vector1D4 [WEAK]
+ EXPORT Vector1D8 [WEAK]
+ EXPORT Vector1DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ EXPORT Vector1E0 [WEAK]
+ EXPORT Vector1E4 [WEAK]
+ EXPORT Vector1E8 [WEAK]
+ EXPORT Vector1EC [WEAK]
+ EXPORT Vector1F0 [WEAK]
+ EXPORT Vector1F4 [WEAK]
+ EXPORT Vector1F8 [WEAK]
+ EXPORT Vector1FC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ EXPORT Vector200 [WEAK]
+ EXPORT Vector204 [WEAK]
+ EXPORT Vector208 [WEAK]
+ EXPORT Vector20C [WEAK]
+ EXPORT Vector210 [WEAK]
+ EXPORT Vector214 [WEAK]
+ EXPORT Vector218 [WEAK]
+ EXPORT Vector21C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ EXPORT Vector220 [WEAK]
+ EXPORT Vector224 [WEAK]
+ EXPORT Vector228 [WEAK]
+ EXPORT Vector22C [WEAK]
+ EXPORT Vector230 [WEAK]
+ EXPORT Vector234 [WEAK]
+ EXPORT Vector238 [WEAK]
+ EXPORT Vector23C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ EXPORT Vector240 [WEAK]
+ EXPORT Vector244 [WEAK]
+ EXPORT Vector248 [WEAK]
+ EXPORT Vector24C [WEAK]
+ EXPORT Vector250 [WEAK]
+ EXPORT Vector254 [WEAK]
+ EXPORT Vector258 [WEAK]
+ EXPORT Vector25C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ EXPORT Vector260 [WEAK]
+ EXPORT Vector264 [WEAK]
+ EXPORT Vector268 [WEAK]
+ EXPORT Vector26C [WEAK]
+ EXPORT Vector270 [WEAK]
+ EXPORT Vector274 [WEAK]
+ EXPORT Vector278 [WEAK]
+ EXPORT Vector27C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ EXPORT Vector280 [WEAK]
+ EXPORT Vector284 [WEAK]
+ EXPORT Vector288 [WEAK]
+ EXPORT Vector28C [WEAK]
+ EXPORT Vector290 [WEAK]
+ EXPORT Vector294 [WEAK]
+ EXPORT Vector298 [WEAK]
+ EXPORT Vector29C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ EXPORT Vector2A0 [WEAK]
+ EXPORT Vector2A4 [WEAK]
+ EXPORT Vector2A8 [WEAK]
+ EXPORT Vector2AC [WEAK]
+ EXPORT Vector2B0 [WEAK]
+ EXPORT Vector2B4 [WEAK]
+ EXPORT Vector2B8 [WEAK]
+ EXPORT Vector2BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ EXPORT Vector2C0 [WEAK]
+ EXPORT Vector2C4 [WEAK]
+ EXPORT Vector2C8 [WEAK]
+ EXPORT Vector2CC [WEAK]
+ EXPORT Vector2D0 [WEAK]
+ EXPORT Vector2D4 [WEAK]
+ EXPORT Vector2D8 [WEAK]
+ EXPORT Vector2DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ EXPORT Vector2E0 [WEAK]
+ EXPORT Vector2E4 [WEAK]
+ EXPORT Vector2E8 [WEAK]
+ EXPORT Vector2EC [WEAK]
+ EXPORT Vector2F0 [WEAK]
+ EXPORT Vector2F4 [WEAK]
+ EXPORT Vector2F8 [WEAK]
+ EXPORT Vector2FC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ EXPORT Vector300 [WEAK]
+ EXPORT Vector304 [WEAK]
+ EXPORT Vector308 [WEAK]
+ EXPORT Vector30C [WEAK]
+ EXPORT Vector310 [WEAK]
+ EXPORT Vector314 [WEAK]
+ EXPORT Vector318 [WEAK]
+ EXPORT Vector31C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ EXPORT Vector320 [WEAK]
+ EXPORT Vector324 [WEAK]
+ EXPORT Vector328 [WEAK]
+ EXPORT Vector32C [WEAK]
+ EXPORT Vector330 [WEAK]
+ EXPORT Vector334 [WEAK]
+ EXPORT Vector338 [WEAK]
+ EXPORT Vector33C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ EXPORT Vector340 [WEAK]
+ EXPORT Vector344 [WEAK]
+ EXPORT Vector348 [WEAK]
+ EXPORT Vector34C [WEAK]
+ EXPORT Vector350 [WEAK]
+ EXPORT Vector354 [WEAK]
+ EXPORT Vector358 [WEAK]
+ EXPORT Vector35C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ EXPORT Vector360 [WEAK]
+ EXPORT Vector364 [WEAK]
+ EXPORT Vector368 [WEAK]
+ EXPORT Vector36C [WEAK]
+ EXPORT Vector370 [WEAK]
+ EXPORT Vector374 [WEAK]
+ EXPORT Vector378 [WEAK]
+ EXPORT Vector37C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ EXPORT Vector380 [WEAK]
+ EXPORT Vector384 [WEAK]
+ EXPORT Vector388 [WEAK]
+ EXPORT Vector38C [WEAK]
+ EXPORT Vector390 [WEAK]
+ EXPORT Vector394 [WEAK]
+ EXPORT Vector398 [WEAK]
+ EXPORT Vector39C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ EXPORT Vector3A0 [WEAK]
+ EXPORT Vector3A4 [WEAK]
+ EXPORT Vector3A8 [WEAK]
+ EXPORT Vector3AC [WEAK]
+ EXPORT Vector3B0 [WEAK]
+ EXPORT Vector3B4 [WEAK]
+ EXPORT Vector3B8 [WEAK]
+ EXPORT Vector3BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ EXPORT Vector3C0 [WEAK]
+ EXPORT Vector3C4 [WEAK]
+ EXPORT Vector3C8 [WEAK]
+ EXPORT Vector3CC [WEAK]
+ EXPORT Vector3D0 [WEAK]
+ EXPORT Vector3D4 [WEAK]
+ EXPORT Vector3D8 [WEAK]
+ EXPORT Vector3DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ EXPORT Vector3E0 [WEAK]
+ EXPORT Vector3E4 [WEAK]
+ EXPORT Vector3E8 [WEAK]
+ EXPORT Vector3EC [WEAK]
+ EXPORT Vector3F0 [WEAK]
+ EXPORT Vector3F4 [WEAK]
+ EXPORT Vector3F8 [WEAK]
+ EXPORT Vector3FC [WEAK]
+#endif
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+Vector1C
+Vector20
+Vector24
+Vector28
+SVC_Handler
+DebugMon_Handler
+Vector34
+PendSV_Handler
+SysTick_Handler
+Vector40
+Vector44
+Vector48
+Vector4C
+Vector50
+Vector54
+Vector58
+Vector5C
+#if CORTEX_NUM_VECTORS > 8
+Vector60
+Vector64
+Vector68
+Vector6C
+Vector70
+Vector74
+Vector78
+Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+Vector80
+Vector84
+Vector88
+Vector8C
+Vector90
+Vector94
+Vector98
+Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+VectorA0
+VectorA4
+VectorA8
+VectorAC
+VectorB0
+VectorB4
+VectorB8
+VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+VectorC0
+VectorC4
+VectorC8
+VectorCC
+VectorD0
+VectorD4
+VectorD8
+VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+VectorE0
+VectorE4
+VectorE8
+VectorEC
+VectorF0
+VectorF4
+VectorF8
+VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+Vector100
+Vector104
+Vector108
+Vector10C
+Vector110
+Vector114
+Vector118
+Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+Vector120
+Vector124
+Vector128
+Vector12C
+Vector130
+Vector134
+Vector138
+Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+Vector140
+Vector144
+Vector148
+Vector14C
+Vector150
+Vector154
+Vector158
+Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+Vector160
+Vector164
+Vector168
+Vector16C
+Vector170
+Vector174
+Vector178
+Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+Vector180
+Vector184
+Vector188
+Vector18C
+Vector190
+Vector194
+Vector198
+Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+Vector1A0
+Vector1A4
+Vector1A8
+Vector1AC
+Vector1B0
+Vector1B4
+Vector1B8
+Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+Vector1C0
+Vector1C4
+Vector1C8
+Vector1CC
+Vector1D0
+Vector1D4
+Vector1D8
+Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+Vector1E0
+Vector1E4
+Vector1E8
+Vector1EC
+Vector1F0
+Vector1F4
+Vector1F8
+Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+Vector200
+Vector204
+Vector208
+Vector20C
+Vector210
+Vector214
+Vector218
+Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+Vector220
+Vector224
+Vector228
+Vector22C
+Vector230
+Vector234
+Vector238
+Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+Vector240
+Vector244
+Vector248
+Vector24C
+Vector250
+Vector254
+Vector258
+Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+Vector260
+Vector264
+Vector268
+Vector26C
+Vector270
+Vector274
+Vector278
+Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+Vector280
+Vector284
+Vector288
+Vector28C
+Vector290
+Vector294
+Vector298
+Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+Vector2A0
+Vector2A4
+Vector2A8
+Vector2AC
+Vector2B0
+Vector2B4
+Vector2B8
+Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+Vector2C0
+Vector2C4
+Vector2C8
+Vector2CC
+Vector2D0
+Vector2D4
+Vector2D8
+Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+Vector2E0
+Vector2E4
+Vector2E8
+Vector2EC
+Vector2F0
+Vector2F4
+Vector2F8
+Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+Vector300
+Vector304
+Vector308
+Vector30C
+Vector310
+Vector314
+Vector318
+Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+Vector320
+Vector324
+Vector328
+Vector32C
+Vector330
+Vector334
+Vector338
+Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+Vector340
+Vector344
+Vector348
+Vector34C
+Vector350
+Vector354
+Vector358
+Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+Vector360
+Vector364
+Vector368
+Vector36C
+Vector370
+Vector374
+Vector378
+Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+Vector380
+Vector384
+Vector388
+Vector38C
+Vector390
+Vector394
+Vector398
+Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+Vector3A0
+Vector3A4
+Vector3A8
+Vector3AC
+Vector3B0
+Vector3B4
+Vector3B8
+Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+Vector3C0
+Vector3C4
+Vector3C8
+Vector3CC
+Vector3D0
+Vector3D4
+Vector3D8
+Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+Vector3E0
+Vector3E4
+Vector3E8
+Vector3EC
+Vector3F0
+Vector3F4
+Vector3F8
+Vector3FC
+#endif
+ b _unhandled_exception
+ ENDP
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F0xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F0xx/cmparams.h
new file mode 100644
index 0000000000..f20983efef
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F0xx/cmparams.h
@@ -0,0 +1,89 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F0xx/cmparams.h
+ * @brief ARM Cortex-M0 parameters for the STM32F0xx.
+ *
+ * @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ * STM32F0xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 0
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && \
+ !defined (STM32F078xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f0xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F1xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F1xx/cmparams.h
new file mode 100644
index 0000000000..f44aa72ef0
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F1xx/cmparams.h
@@ -0,0 +1,90 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F1xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32F1xx.
+ *
+ * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F1xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 3
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 72
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F100xB) && !defined(STM32F100xE) && \
+ !defined(STM32F101x6) && !defined(STM32F101xB) && \
+ !defined(STM32F101xE) && !defined(STM32F101xG) && \
+ !defined(STM32F102x6) && !defined(STM32F102xB) && \
+ !defined(STM32F103x6) && !defined(STM32F103xB) && \
+ !defined(STM32F103xE) && !defined(STM32F103xG) && \
+ !defined(STM32F105xC) && !defined(STM32F107xC)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f1xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F2xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F2xx/cmparams.h
new file mode 100644
index 0000000000..7ce2091164
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F2xx/cmparams.h
@@ -0,0 +1,84 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F2xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32F2xx.
+ *
+ * @defgroup ARMCMx_STM32F2xx STM32F2xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M3 specific parameters for the
+ * STM32F2xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 3
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 96
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F2XX)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f2xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F3xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F3xx/cmparams.h
new file mode 100644
index 0000000000..8fbb0c0b68
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F3xx/cmparams.h
@@ -0,0 +1,93 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F3xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F3xx.
+ *
+ * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F3xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 88
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (STM32F301x8) && !defined (STM32F318xx) && \
+ !defined (STM32F302x8) && !defined (STM32F302xC) && \
+ !defined (STM32F303x8) && !defined (STM32F303xC) && \
+ !defined (STM32F358xx) && !defined (STM32F334x8) && \
+ !defined (STM32F328xx) && \
+ !defined (STM32F373xC) && !defined (STM32F378xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f3xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h
new file mode 100644
index 0000000000..03316180ea
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h
@@ -0,0 +1,95 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F4xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F4xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 104
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F405xx) && !defined(STM32F415xx) && \
+ !defined(STM32F407xx) && !defined(STM32F417xx) && \
+ !defined(STM32F427xx) && !defined(STM32F437xx) && \
+ !defined(STM32F429xx) && !defined(STM32F439xx) && \
+ !defined(STM32F401xC) && !defined(STM32F401xE) && \
+ !defined(STM32F410Cx) && !defined(STM32F410Rx) && \
+ !defined(STM32F411xE) && !defined(STM32F446xx) && \
+ !defined(STM32F469xx) && !defined(STM32F479xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f4xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F7xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F7xx/cmparams.h
new file mode 100644
index 0000000000..d95bc0d6fc
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32F7xx/cmparams.h
@@ -0,0 +1,88 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F7xx/cmparams.h
+ * @brief ARM Cortex-M7 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32F7xx STM32F7xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M7 specific parameters for the
+ * STM32F7xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 7
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 112
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F745xx) && !defined(STM32F746xx) && !defined(STM32F756xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f7xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L0xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L0xx/cmparams.h
new file mode 100644
index 0000000000..522973c5ba
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L0xx/cmparams.h
@@ -0,0 +1,88 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/cmparams.h
+ * @brief ARM Cortex-M0+ parameters for the STM32L0xx.
+ *
+ * @defgroup ARMCMx_STM32L0xx STM32L0xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ * STM32L0xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 0
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32L011xx) && !defined(STM32L031xx) && \
+ !defined(STM32L051xx) && !defined(STM32L052xx) && \
+ !defined(STM32L053xx) && !defined(STM32L061xx) && \
+ !defined(STM32L062xx) && !defined(STM32L063xx) && \
+ !defined(STM32L073xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32l0xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L1xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L1xx/cmparams.h
new file mode 100644
index 0000000000..e38f69fd53
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L1xx/cmparams.h
@@ -0,0 +1,97 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32L1xx.
+ *
+ * @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M3 specific parameters for the
+ * STM32L1xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 3
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 64
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32L100xB) && !defined(STM32L100xBA) && \
+ !defined(STM32L100xC) && !defined(STM32L151xB) && \
+ !defined(STM32L151xBA) && !defined(STM32L151xC) && \
+ !defined(STM32L151xCA) && !defined(STM32L151xD) && \
+ !defined(STM32L151xDX) && !defined(STM32L151xE) && \
+ !defined(STM32L152xB) && !defined(STM32L152xBA) && \
+ !defined(STM32L152xC) && !defined(STM32L152xCA) && \
+ !defined(STM32L152xD) && !defined(STM32L152xDX) && \
+ !defined(STM32L152xE) && !defined(STM32L162xC) && \
+ !defined(STM32L162xCA) && !defined(STM32L162xD) && \
+ !defined(STM32L162xDX) && !defined(STM32L162xE)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32l1xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+/* Fix for yet another consistency error in ST headers.*/
+#define SVCall_IRQn SVC_IRQn
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h
new file mode 100644
index 0000000000..98fe0c3a33
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h
@@ -0,0 +1,90 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F4xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32L$xx STM32L4xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32L4xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 88
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32L471xx) && !defined(STM32L475xx) && \
+ !defined(STM32L476xx) && !defined(STM32L485xx) && \
+ !defined (STM32L486xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32l4xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/adc.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/adc.dox
deleted file mode 100644
index 76e7b95fd9..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/adc.dox
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup ADC ADC Driver
- * @brief Generic ADC Driver.
- * @details This module implements a generic ADC (Analog to Digital Converter)
- * driver supporting a variety of buffer and conversion modes.
- * @pre In order to use the ADC driver the @p HAL_USE_ADC option
- * must be enabled in @p halconf.h.
- *
- * @section adc_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
- digraph example {
- rankdir="LR";
- size="5, 7";
-
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="ADC_STOP\nLow Power"];
- uninit [label="ADC_UNINIT", style="bold"];
- ready [label="ADC_READY\nClock Enabled"];
- active [label="ADC_ACTIVE\nConverting"];
- error [label="ADC_ERROR\nError"];
- complete [label="ADC_COMPLETE\nComplete"];
-
- uninit -> stop [label="\n adcInit()", constraint=false];
- stop -> ready [label="\nadcStart()"];
- ready -> ready [label="\nadcStart()\nadcStopConversion()"];
- ready -> stop [label="\nadcStop()"];
- stop -> stop [label="\nadcStop()"];
- ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"];
- active -> ready [label="\nadcStopConversion()\nsync return"];
- active -> active [label="\nasync callback (half buffer, circular)\nasync callback (full buffer)\n>acg_endcb<"];
- active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"];
- active -> error [label="\n\nasync callback (error)\n>error_cb<"];
- complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"];
- complete -> ready [label="\ncallback return"];
- error -> active [label="\nadcStartConversionI()\nthen\ncallback return"];
- error -> ready [label="\ncallback return"];
- }
- * @enddot
- * @else
- * @dot
- digraph example {
- rankdir="LR";
-
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="ADC_STOP\nLow Power"];
- uninit [label="ADC_UNINIT", style="bold"];
- ready [label="ADC_READY\nClock Enabled"];
- active [label="ADC_ACTIVE\nConverting"];
- error [label="ADC_ERROR\nError"];
- complete [label="ADC_COMPLETE\nComplete"];
-
- uninit -> stop [label="\n adcInit()", constraint=false];
- stop -> ready [label="\nadcStart()"];
- ready -> ready [label="\nadcStart()\nadcStopConversion()"];
- ready -> stop [label="\nadcStop()"];
- stop -> stop [label="\nadcStop()"];
- ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"];
- active -> ready [label="\nadcStopConversion()\nsync return"];
- active -> active [label="\nasync callback (half buffer, circular)\nasync callback (full buffer)\n>acg_endcb<"];
- active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"];
- active -> error [label="\n\nasync callback (error)\n>error_cb<"];
- complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"];
- complete -> ready [label="\ncallback return"];
- error -> active [label="\nadcStartConversionI()\nthen\ncallback return"];
- error -> ready [label="\ncallback return"];
- }
- * @enddot
- * @endif
- *
- * @section adc_2 ADC Operations
- * The ADC driver is quite complex, an explanation of the terminology and of
- * the operational details follows.
- *
- * @subsection adc_2_1 ADC Conversion Groups
- * The @p ADCConversionGroup is the objects that specifies a physical
- * conversion operation. This structure contains some standard fields and
- * several implementation-dependent fields.
- * The standard fields define the CG mode, the number of channels belonging
- * to the CG and the optional callbacks.
- * The implementation-dependent fields specify the physical ADC operation
- * mode, the analog channels belonging to the group and any other
- * implementation-specific setting. Usually the extra fields just mirror
- * the physical ADC registers, please refer to the vendor's MCU Reference
- * Manual for details about the available settings. Details are also available
- * into the documentation of the ADC low level drivers and in the various
- * sample applications.
- *
- * @subsection adc_2_2 ADC Conversion Modes
- * The driver supports several conversion modes:
- * - One Shot, the driver performs a single group conversion then stops.
- * - Linear Buffer, the driver performs a series of group conversions
- * then stops. This mode is like a one shot conversion repeated N times,
- * the buffer pointer increases after each conversion. The buffer is
- * organized as an S(CG)*N samples matrix, when S(CG) is the conversion
- * group size (number of channels) and N is the buffer depth (number of
- * repeated conversions).
- * - Circular Buffer, much like the linear mode but the operation does
- * not stop when the buffer is filled, it is automatically restarted
- * with the buffer pointer wrapping back to the buffer base.
- * .
- * @subsection adc_2_3 ADC Callbacks
- * The driver is able to invoke callbacks during the conversion process. A
- * callback is invoked when the operation has been completed or, in circular
- * mode, when the buffer has been filled and the operation is restarted. In
- * circular mode a callback is also invoked when the buffer is half filled.
- * The "half filled" and "filled" callbacks in circular mode allow to
- * implement "streaming processing" of the sampled data, while the driver is
- * busy filling one half of the buffer the application can process the
- * other half, this allows for continuous interleaved operations.
- *
- * The driver is not thread safe for performance reasons, if you need to access
- * the ADC bus from multiple threads then use the @p adcAcquireBus() and
- * @p adcReleaseBus() APIs in order to gain exclusive access.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/can.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/can.dox
deleted file mode 100644
index e32e9ce3fe..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/can.dox
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup CAN CAN Driver
- * @brief Generic CAN Driver.
- * @details This module implements a generic CAN (Controller Area Network)
- * driver allowing the exchange of information at frame level.
- * @pre In order to use the CAN driver the @p HAL_USE_CAN option
- * must be enabled in @p halconf.h.
- *
- * @section can_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
- digraph example {
- size="5, 7";
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="CAN_STOP\nLow Power"];
- uninit [label="CAN_UNINIT", style="bold"];
- starting [label="CAN_STARTING\nInitializing"];
- ready [label="CAN_READY\nClock Enabled"];
- sleep [label="CAN_SLEEP\nLow Power"];
-
- uninit -> stop [label=" canInit()", constraint=false];
- stop -> stop [label="\ncanStop()"];
- stop -> ready [label="\ncanStart()\n(fast implementation)"];
- stop -> starting [label="\ncanStart()\n(slow implementation)"];
- starting -> starting [label="\ncanStart()\n(other thread)"];
- starting -> ready [label="\ninitialization complete\n(all threads)"];
- ready -> stop [label="\ncanStop()"];
- ready -> ready [label="\ncanStart()\ncanReceive()\ncanTransmit()"];
- ready -> sleep [label="\ncanSleep()"];
- sleep -> sleep [label="\ncanSleep()"];
- sleep -> ready [label="\ncanWakeup()"];
- sleep -> ready [label="\nhardware\nwakeup event"];
- }
- * @enddot
- * @else
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="CAN_STOP\nLow Power"];
- uninit [label="CAN_UNINIT", style="bold"];
- starting [label="CAN_STARTING\nInitializing"];
- ready [label="CAN_READY\nClock Enabled"];
- sleep [label="CAN_SLEEP\nLow Power"];
-
- uninit -> stop [label=" canInit()", constraint=false];
- stop -> stop [label="\ncanStop()"];
- stop -> ready [label="\ncanStart()\n(fast implementation)"];
- stop -> starting [label="\ncanStart()\n(slow implementation)"];
- starting -> starting [label="\ncanStart()\n(other thread)"];
- starting -> ready [label="\ninitialization complete\n(all threads)"];
- ready -> stop [label="\ncanStop()"];
- ready -> ready [label="\ncanStart()\ncanReceive()\ncanTransmit()"];
- ready -> sleep [label="\ncanSleep()"];
- sleep -> sleep [label="\ncanSleep()"];
- sleep -> ready [label="\ncanWakeup()"];
- sleep -> ready [label="\nhardware\nwakeup event"];
- }
- * @enddot
- * @endif
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/ext.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/ext.dox
deleted file mode 100644
index 6b9a12a7a7..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/ext.dox
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup EXT EXT Driver
- * @brief Generic EXT Driver.
- * @details This module implements a generic EXT (EXTernal) driver.
- * @pre In order to use the EXT driver the @p HAL_USE_EXT option
- * must be enabled in @p halconf.h.
- *
- * @section ext_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
- digraph example {
- size="5, 7";
- rankdir="LR";
-
- node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Sans, fontsize=8];
-
- uninit [label="EXT_UNINIT", style="bold"];
- stop [label="EXT_STOP\nLow Power"];
- active [label="EXT_ACTIVE"];
-
- uninit -> stop [label="extInit()"];
- stop -> stop [label="\nextStop()"];
- stop -> active [label="\nextStart()"];
- active -> stop [label="\nextStop()"];
- active -> active [label="\nextStart()"];
- }
- * @enddot
- * @else
- * @dot
- digraph example {
- rankdir="LR";
-
- node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Sans, fontsize=8];
-
- uninit [label="EXT_UNINIT", style="bold"];
- stop [label="EXT_STOP\nLow Power"];
- active [label="EXT_ACTIVE"];
-
- uninit -> stop [label="extInit()"];
- stop -> stop [label="\nextStop()"];
- stop -> active [label="\nextStart()"];
- active -> stop [label="\nextStop()"];
- active -> active [label="\nextStart()"];
- }
- * @enddot
- * @endif
- *
- * @section ext_2 EXT Operations.
- * This driver abstracts generic external interrupt sources, a callback
- * is invoked when a programmable transition is detected on one of the
- * configured channels. Several channel modes are possible.
- * - EXT_CH_MODE_DISABLED, channel not used.
- * - EXT_CH_MODE_RISING_EDGE, callback on a rising edge.
- * - EXT_CH_MODE_FALLING_EDGE, callback on a falling edge.
- * - EXT_CH_MODE_BOTH_EDGES, callback on a both edges.
- * .
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/gpt.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/gpt.dox
deleted file mode 100644
index 695f99e319..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/gpt.dox
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup GPT GPT Driver
- * @brief Generic GPT Driver.
- * @details This module implements a generic GPT (General Purpose Timer)
- * driver. The timer can be programmed in order to trigger callbacks
- * after a specified time period or continuously with a specified
- * interval.
- * @pre In order to use the GPT driver the @p HAL_USE_GPT option
- * must be enabled in @p halconf.h.
- *
- * @section gpt_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="GPT_STOP\nLow Power"];
- uninit [label="GPT_UNINIT", style="bold"];
- ready [label="GPT_READY\nClock Enabled"];
- continuous [label="GPT_CONT..S\nContinuous\nMode"];
- oneshot [label="GPT_ONESHOT\nOne Shot\nMode"];
-
- uninit -> stop [label=" gptInit()", constraint=false];
- stop -> stop [label="\ngptStop()"];
- stop -> ready [label="\ngptStart()"];
- ready -> stop [label="\ngptStop()"];
- ready -> ready [label="\ngptStart()"];
- ready -> continuous [label="\ngptStartContinuous()"];
- continuous -> ready [label="\ngptStopTimer()"];
- continuous -> continuous [label=">callback<"];
- ready -> oneshot [label="\ngptStartOneShot()\ngptPolledDelay()"];
- oneshot -> ready [label="\n>callback<\nor\nDelay Over"];
- }
- * @enddot
- *
- * @section gpt_2 GPT Operations.
- * This driver abstracts a generic timer composed of:
- * - A clock prescaler.
- * - A main up counter.
- * - A comparator register that resets the main counter to zero when the limit
- * is reached. A callback is invoked when this happens.
- * .
- * The timer can operate in three different modes:
- * - Continuous Mode, a periodic callback is invoked until the driver
- * is explicitly stopped.
- * - One Shot Mode, a callback is invoked after the programmed period
- * and then the timer automatically stops.
- * - Delay Mode, the timer is used for inserting a brief delay into
- * the execution flow, no callback is invoked in this mode.
- * .
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/hal.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/hal.dox
deleted file mode 100644
index 95e30f6e95..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/hal.dox
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup HAL HAL Driver
- * @brief Hardware Abstraction Layer.
- * @details The HAL (Hardware Abstraction Layer) driver performs the system
- * initialization and includes the platform support code shared by
- * the other drivers. This driver does contain any API function
- * except for a general initialization function @p halInit() that
- * must be invoked before any HAL service can be used, usually the
- * HAL initialization should be performed immediately before the
- * kernel initialization.
- * Some HAL driver implementations also offer a custom early clock
- * setup function that can be invoked before the C runtime
- * initialization in order to accelerate the startup time.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/i2c.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/i2c.dox
deleted file mode 100644
index 038b17e4f5..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/i2c.dox
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup I2C I2C Driver
- * @brief Generic I2C Driver.
- * @details This module implements a generic I2C (Inter-Integrated Circuit)
- * driver.
- * @pre In order to use the I2C driver the @p HAL_USE_I2C option
- * must be enabled in @p halconf.h.
- *
- * @section i2c_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
- digraph example {
- size="5, 7";
- rankdir="LR";
-
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="I2C_STOP\nLow Power"];
- uninit [label="I2C_UNINIT", style="bold"];
- ready [label="I2C_READY\nClock Enabled"];
- active_tx [label="I2C_ACTIVE_TX\nBus TX Active"];
- active_rx [label="I2C_ACTIVE_RX\nBus RX Active"];
- locked [label="I2C_LOCKED\nBus Locked"];
-
- uninit -> stop [label="i2cInit()", constraint=false];
- stop -> stop [label="i2cStop()"];
- stop -> ready [label="i2cStart()"];
- ready -> ready [label="i2cStart()"];
- ready -> stop [label="i2cStop()"];
- ready -> active_tx [label="i2cMasterTransmit()"];
- ready -> active_rx [label="i2cMasterReceive()"];
- active_tx -> ready [label="completed"];
- active_rx -> ready [label="completed"];
- active_tx -> locked [label="RDY_TIMEOUT"];
- active_rx -> locked [label="RDY_TIMEOUT"];
- locked -> stop [label="i2cStop()"];
- locked -> ready [label="i2cStart()"];
- }
- * @else
- * @dot
- digraph example {
- rankdir="LR";
-
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="I2C_STOP\nLow Power"];
- uninit [label="I2C_UNINIT", style="bold"];
- ready [label="I2C_READY\nClock Enabled"];
- active_tx [label="I2C_ACTIVE_TX\nBus TX Active"];
- active_rx [label="I2C_ACTIVE_RX\nBus RX Active"];
- locked [label="I2C_LOCKED\nBus Locked"];
-
- uninit -> stop [label="i2cInit()", constraint=false];
- stop -> stop [label="i2cStop()"];
- stop -> ready [label="i2cStart()"];
- ready -> ready [label="i2cStart()"];
- ready -> stop [label="i2cStop()"];
- ready -> active_tx [label="i2cMasterTransmit()"];
- ready -> active_rx [label="i2cMasterReceive()"];
- active_tx -> ready [label="completed"];
- active_rx -> ready [label="completed"];
- active_tx -> locked [label="RDY_TIMEOUT"];
- active_rx -> locked [label="RDY_TIMEOUT"];
- locked -> stop [label="i2cStop()"];
- locked -> ready [label="i2cStart()"];
- }
- * @enddot
- * @endif
- * The driver is not thread safe for performance reasons, if you need to access
- * the I2C bus from multiple threads then use the @p i2cAcquireBus() and
- * @p i2cReleaseBus() APIs in order to gain exclusive access.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/i2s.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/i2s.dox
deleted file mode 100644
index 05259d2890..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/i2s.dox
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup I2S I2S Driver
- * @brief Generic I2S Driver.
- * @details This module implements a generic I2S driver.
- * @pre In order to use the I2S driver the @p HAL_USE_I2S option
- * must be enabled in @p halconf.h.
- *
- * @section i2s_1 Driver State Machine
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/icu.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/icu.dox
deleted file mode 100644
index 0c385c213f..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/icu.dox
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-*/
-
-/**
- * @defgroup ICU ICU Driver
- * @brief Generic ICU Driver.
- * @details This module implements a generic ICU (Input Capture Unit) driver.
- * @pre In order to use the ICU driver the @p HAL_USE_ICU option
- * must be enabled in @p halconf.h.
- *
- * @section icu_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
- digraph example {
- size="5, 7";
- rankdir="LR";
-
- node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Sans, fontsize=8];
-
- stop [label="ICU_STOP\nLow Power"];
- uninit [label="ICU_UNINIT", style="bold"];
- ready [label="ICU_READY\nClock Enabled"];
- waiting [label="ICU_WAITING"];
- active [label="ICU_ACTIVE"];
- idle [label="ICU_IDLE"];
-
- uninit -> stop [label=" icuInit()", constraint=false];
- stop -> stop [label="\nicuStop()"];
- stop -> ready [label="\nicuStart()"];
- ready -> stop [label="\nicuStop()"];
- ready -> ready [label="\nicuStart()\nicuDisable()"];
- ready -> waiting [label="\nicuEnable()"];
- waiting -> active [label="\nStart Front"];
- waiting -> ready [label="\nicuDisable()"];
- waiting -> waiting [label="\nStop Front"];
- active -> idle [label="\nStop Front\n>width_cb<"];
- active -> ready [label="\nicuDisable()\nicuDisableI()"];
- idle -> active [label="\nStart Front\n>period_cb<"];
- idle -> ready [label="\nicuDisable()\nicuDisableI()"];
- }
- * @enddot
- * @else
- * @dot
- digraph example {
- rankdir="LR";
-
- node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Sans, fontsize=8];
-
- stop [label="ICU_STOP\nLow Power"];
- uninit [label="ICU_UNINIT", style="bold"];
- ready [label="ICU_READY\nClock Enabled"];
- waiting [label="ICU_WAITING"];
- active [label="ICU_ACTIVE"];
- idle [label="ICU_IDLE"];
-
- uninit -> stop [label=" icuInit()", constraint=false];
- stop -> stop [label="\nicuStop()"];
- stop -> ready [label="\nicuStart()"];
- ready -> stop [label="\nicuStop()"];
- ready -> ready [label="\nicuStart()\nicuDisable()"];
- ready -> waiting [label="\nicuEnable()"];
- waiting -> active [label="\nStart Front"];
- waiting -> ready [label="\nicuDisable()"];
- waiting -> waiting [label="\nStop Front"];
- active -> idle [label="\nStop Front\n>width_cb<"];
- active -> ready [label="\nicuDisable()\nicuDisableI()"];
- idle -> active [label="\nStart Front\n>period_cb<"];
- idle -> ready [label="\nicuDisable()\nicuDisableI()"];
- }
- * @enddot
- * @endif
- *
- * @section icu_2 ICU Operations.
- * This driver abstracts a generic Input Capture Unit composed of:
- * - A clock prescaler.
- * - A main up counter.
- * - Two capture registers triggered by the rising and falling edges on
- * the sampled input.
- * .
- * The ICU unit can be programmed to synchronize on the rising or falling
- * edge of the sample input:
- * - ICU_INPUT_ACTIVE_HIGH, a rising edge is the start signal.
- * - ICU_INPUT_ACTIVE_LOW, a falling edge is the start signal.
- * .
- * After the activation the ICU unit can be in one of the following
- * states at any time:
- * - ICU_WAITING, waiting the first start signal.
- * - ICU_ACTIVE, after a start signal.
- * - ICU_IDLE, after a stop signal.
- * .
- * Callbacks are invoked when start or stop signals occur.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/io_block.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/io_block.dox
deleted file mode 100644
index ec63a398f3..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/io_block.dox
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup IO_BLOCK Abstract I/O Block Device
- * @ingroup IO
- *
- * @section io_block_1 Driver State Machine
- * The drivers implementing this interface shall implement the following
- * state machine internally. Not all the driver functionalities can be used
- * in any moment, any transition not explicitly shown in the following
- * diagram has to be considered an error and shall be captured by an
- * assertion (if enabled).
- * @if LATEX_PDF
- * @dot
- digraph example {
- size="5, 7";
- rankdir="LR";
-
- node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Sans, fontsize=8];
-
- stop [label="BLK_STOP\nLow Power"];
- uninit [label="BLK_UNINIT", style="bold"];
- active [label="BLK_ACTIVE\nClock Enabled"];
- connecting [label="BLK_CONN.ING\nConnecting"];
- disconnecting [label="BLK_DISC.ING\nDisconnecting"];
- ready [label="BLK_READY\nCard Ready"];
- reading [label="BLK_READING\nReading"];
- writing [label="BLK_WRITING\nWriting"];
-
- uninit -> stop [label=" blkInit()", constraint=false];
- stop -> stop [label="\nblkStop()"];
- stop -> active [label="\nblkStart()"];
- active -> stop [label="\nblkStop()"];
- active -> active [label="\nblkStart()\nblkDisconnect()"];
- active -> connecting [label="\nblkConnect()"];
- connecting -> ready [label="\nconnection\nsuccessful"];
- connecting -> ready [label="\nblkConnect()", dir="back"];
- connecting -> active [label="\nconnection\nfailed"];
- disconnecting -> ready [label="\nblkDisconnect()", dir="back"];
- active -> disconnecting [label="\ndisconnection\nfinished", dir="back"];
- ready -> reading [label="\nblkRead()"];
- reading -> ready [label="\nread finished\nread error"];
- ready -> writing [label="\nblkWrite()"];
- writing -> ready [label="\nwrite finished\nwrite error"];
- }
- * @enddot
- * @else
- * @dot
- digraph example {
- rankdir="LR";
-
- node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Sans, fontsize=8];
-
- stop [label="BLK_STOP\nLow Power"];
- uninit [label="BLK_UNINIT", style="bold"];
- active [label="BLK_ACTIVE\nClock Enabled"];
- connecting [label="BLK_CONN.ING\nConnecting"];
- disconnecting [label="BLK_DISC.ING\nDisconnecting"];
- ready [label="BLK_READY\nCard Ready"];
- reading [label="BLK_READING\nReading"];
- writing [label="BLK_WRITING\nWriting"];
- syncing [label="BLK_SYNCING\nSynchronizing"];
-
- uninit -> stop [label=" blkInit()", constraint=false];
- stop -> stop [label="\nblkStop()"];
- stop -> active [label="\nblkStart()"];
- active -> stop [label="\nblkStop()"];
- active -> active [label="\nblkStart()\nblkDisconnect()"];
- active -> connecting [label="\nblkConnect()"];
- connecting -> ready [label="\nconnection\nsuccessful"];
- connecting -> ready [label="\nblkConnect()", dir="back"];
- connecting -> active [label="\nconnection\nfailed"];
- disconnecting -> ready [label="\nblkDisconnect()", dir="back"];
- active -> disconnecting [label="\ndisconnection\nfinished", dir="back"];
- ready -> reading [label="\nblkRead()"];
- reading -> ready [label="\nread finished\nread error"];
- ready -> writing [label="\nblkWrite()"];
- writing -> ready [label="\nwrite finished\nwrite error"];
- ready -> syncing [label="\nblkSync()"];
- syncing -> ready [label="\nsynchronization finished"];
- }
- * @enddot
- * @endif
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/io_channel.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/io_channel.dox
deleted file mode 100644
index 0980d67d2e..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/io_channel.dox
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup IO_CHANNEL Abstract I/O Channel
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mac.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mac.dox
deleted file mode 100644
index 6de76d75b5..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mac.dox
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup MAC MAC Driver
- * @brief Generic MAC driver.
- * @details This module implements a generic MAC (Media Access Control)
- * driver for Ethernet controllers.
- * @pre In order to use the MAC driver the @p HAL_USE_MAC option
- * must be enabled in @p halconf.h.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mmc_spi.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mmc_spi.dox
deleted file mode 100644
index 44bdd8e17d..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mmc_spi.dox
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup MMC_SPI MMC over SPI Driver
- * @brief Generic MMC driver.
- * @details This module implements a portable MMC/SD driver that uses a SPI
- * driver as physical layer. Hot plugging and removal are supported
- * through kernel events.
- * @pre In order to use the MMC_SPI driver the @p HAL_USE_MMC_SPI and
- * @p HAL_USE_SPI options must be enabled in @p halconf.h.
- *
- * @section mmc_spi_1 Driver State Machine
- * This driver implements a state machine internally, see the @ref IO_BLOCK
- * module documentation for details.
- *
- * @section mmc_spi_2 Driver Operations
- * This driver allows to read or write single or multiple 512 bytes blocks
- * on a SD Card.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mmcsd.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mmcsd.dox
deleted file mode 100644
index fb949229e4..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/mmcsd.dox
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup MMCSD MMC/SD Block Device
- * @details This module implements a common ancestor for all device drivers
- * accessing MMC or SD cards. This interface inherits the state
- * machine and the interface from the @ref IO_BLOCK module.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/pal.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/pal.dox
deleted file mode 100644
index c2ed7eb148..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/pal.dox
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup PAL PAL Driver
- * @brief I/O Ports Abstraction Layer
- * @details This module defines an abstract interface for digital I/O ports.
- * Note that most I/O ports functions are just macros. The macros
- * have default software implementations that can be redefined in a
- * PAL Low Level Driver if the target hardware supports special
- * features like, for example, atomic bit set/reset/masking. Please
- * refer to the ports specific documentation for details.
- * The @ref PAL has the advantage to make the access to the I/O
- * ports platform independent and still be optimized for the specific
- * architectures.
- * Note that the PAL Low Level Driver may also offer non standard
- * macro and functions in order to support specific features but,
- * of course, the use of such interfaces would not be portable.
- * Such interfaces shall be marked with the architecture name inside
- * the function names.
- * @pre In order to use the PAL driver the @p HAL_USE_PAL option
- * must be enabled in @p halconf.h.
- *
- * @section pal_1 Implementation Rules
- * In implementing a PAL Low Level Driver there are some rules/behaviors that
- * should be respected.
- *
- * @subsection pal_1_1 Writing on input pads
- * The behavior is not specified but there are implementations better than
- * others, this is the list of possible implementations, preferred options
- * are on top:
- * -# The written value is not actually output but latched, should the pads
- * be reprogrammed as outputs the value would be in effect.
- * -# The write operation is ignored.
- * -# The write operation has side effects, as example disabling/enabling
- * pull up/down resistors or changing the pad direction. This scenario is
- * discouraged, please try to avoid this scenario.
- * .
- * @subsection pal_1_2 Reading from output pads
- * The behavior is not specified but there are implementations better than
- * others, this is the list of possible implementations, preferred options
- * are on top:
- * -# The actual pads states are read (not the output latch).
- * -# The output latch value is read (regardless of the actual pads states).
- * -# Unspecified, please try to avoid this scenario.
- * .
- * @subsection pal_1_3 Writing unused or unimplemented port bits
- * The behavior is not specified.
- *
- * @subsection pal_1_4 Reading from unused or unimplemented port bits
- * The behavior is not specified.
- *
- * @subsection pal_1_5 Reading or writing on pins associated to other functionalities
- * The behavior is not specified.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/pwm.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/pwm.dox
deleted file mode 100644
index d842981093..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/pwm.dox
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup PWM PWM Driver
- * @brief Generic PWM Driver.
- * @details This module implements a generic PWM (Pulse Width Modulation)
- * driver.
- * @pre In order to use the PWM driver the @p HAL_USE_PWM option
- * must be enabled in @p halconf.h.
- *
- * @section pwm_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
- uninit [label="PWM_UNINIT", style="bold"];
- stop [label="PWM_STOP\nLow Power"];
- ready [label="PWM_READY\nClock Enabled"];
- uninit -> stop [label="pwmInit()"];
- stop -> stop [label="pwmStop()"];
- stop -> ready [label="pwmStart()"];
- ready -> stop [label="pwmStop()"];
- ready -> ready [label="pwmEnableChannel()\npwmDisableChannel()"];
- }
- * @enddot
- *
- * @section pwm_2 PWM Operations.
- * This driver abstracts a generic PWM timer composed of:
- * - A clock prescaler.
- * - A main up counter.
- * - A comparator register that resets the main counter to zero when the limit
- * is reached. An optional callback can be generated when this happens.
- * - An array of @p PWM_CHANNELS PWM channels, each channel has an output,
- * a comparator and is able to invoke an optional callback when a comparator
- * match with the main counter happens.
- * .
- * A PWM channel output can be in two different states:
- * - IDLE, when the channel is disabled or after a match occurred.
- * - ACTIVE, when the channel is enabled and a match didn't occur yet
- * in the current PWM cycle.
- * .
- * Note that the two states can be associated to both logical zero or one in
- * the @p PWMChannelConfig structure.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/rtc.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/rtc.dox
deleted file mode 100644
index 9d10996c8d..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/rtc.dox
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup RTC RTC Driver
- * @brief Real Time Clock Abstraction Layer
- * @details This module defines an abstract interface for a Real Time Clock
- * Peripheral.
- * @pre In order to use the RTC driver the @p HAL_USE_RTC option
- * must be enabled in @p halconf.h.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/sdc.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/sdc.dox
deleted file mode 100644
index 261587e56d..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/sdc.dox
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup SDC SDC Driver
- * @brief Generic SD Card Driver.
- * @details This module implements a generic SDC (Secure Digital Card) driver.
- * @pre In order to use the SDC driver the @p HAL_USE_SDC option
- * must be enabled in @p halconf.h.
- *
- * @section sdc_1 Driver State Machine
- * This driver implements a state machine internally, see the @ref IO_BLOCK
- * module documentation for details.
- *
- * @section sdc_2 Driver Operations
- * This driver allows to read or write single or multiple 512 bytes blocks
- * on a SD Card.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/serial.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/serial.dox
deleted file mode 100644
index f112da0b31..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/serial.dox
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup SERIAL Serial Driver
- * @brief Generic Serial Driver.
- * @details This module implements a generic full duplex serial driver. The
- * driver implements a @p SerialDriver interface and uses I/O Queues
- * for communication between the upper and the lower driver. Event
- * flags are used to notify the application about incoming data,
- * outgoing data and other I/O events.
- * The module also contains functions that make the implementation
- * of the interrupt service routines much easier.
- * @pre In order to use the SERIAL driver the @p HAL_USE_SERIAL option
- * must be enabled in @p halconf.h.
- *
- *
- * @section serial_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- uninit [label="SD_UNINIT", style="bold"];
- stop [label="SD_STOP\nLow Power"];
- ready [label="SD_READY\nClock Enabled"];
-
- uninit -> stop [label=" sdInit()"];
- stop -> stop [label="\nsdStop()"];
- stop -> ready [label="\nsdStart()"];
- ready -> stop [label="\nsdStop()"];
- ready -> ready [label="\nsdStart()"];
- ready -> ready [label="\nAny I/O operation"];
- }
- * @enddot
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/serial_usb.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/serial_usb.dox
deleted file mode 100644
index 45ac8dd6b2..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/serial_usb.dox
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup SERIAL_USB Serial over USB Driver
- * @brief Serial over USB Driver.
- * @details This module implements an USB Communication Device Class
- * (CDC) as a normal serial communication port accessible from
- * the device application.
- * @pre In order to use the USB over Serial driver the
- * @p HAL_USE_SERIAL_USB option must be enabled in @p halconf.h.
- *
- * @section usb_serial_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- uninit [label="SDU_UNINIT", style="bold"];
- stop [label="SDU_STOP\nLow Power"];
- ready [label="SDU_READY\nClock Enabled"];
-
- uninit -> stop [label=" sduInit()"];
- stop -> stop [label="\nsduStop()"];
- stop -> ready [label="\nsduStart()"];
- ready -> stop [label="\nsduStop()"];
- ready -> ready [label="\nsduStart()"];
- ready -> ready [label="\nAny I/O operation"];
- }
- * @enddot
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/spi.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/spi.dox
deleted file mode 100644
index 7d622a528a..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/spi.dox
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup SPI SPI Driver
- * @brief Generic SPI Driver.
- * @details This module implements a generic SPI (Serial Peripheral Interface)
- * driver allowing bidirectional and monodirectional transfers,
- * complex atomic transactions are supported as well.
- * @pre In order to use the SPI driver the @p HAL_USE_SPI option
- * must be enabled in @p halconf.h.
- *
- * @section spi_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
- digraph example {
- size="5, 7";
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="SPI_STOP\nLow Power"];
- uninit [label="SPI_UNINIT", style="bold"];
- ready [label="SPI_READY\nClock Enabled"];
- active [label="SPI_ACTIVE\nBus Active"];
- complete [label="SPI_COMPLETE\nComplete"];
-
- uninit -> stop [label="\n spiInit()", constraint=false];
- stop -> ready [label="\nspiStart()"];
- ready -> ready [label="\nspiSelect()\nspiUnselect()\nspiStart()"];
- ready -> stop [label="\nspiStop()"];
- stop -> stop [label="\nspiStop()"];
- ready -> active [label="\nspiStartXXXI() (async)\nspiXXX() (sync)"];
- active -> ready [label="\nsync return"];
- active -> complete [label="\nasync callback\n>spc_endcb<"];
- complete -> active [label="\nspiStartXXXI() (async)\nthen\ncallback return"];
- complete -> ready [label="\ncallback return"];
- }
- * @enddot
- * @else
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="SPI_STOP\nLow Power"];
- uninit [label="SPI_UNINIT", style="bold"];
- ready [label="SPI_READY\nClock Enabled"];
- active [label="SPI_ACTIVE\nBus Active"];
- complete [label="SPI_COMPLETE\nComplete"];
-
- uninit -> stop [label="\n spiInit()", constraint=false];
- stop -> ready [label="\nspiStart()"];
- ready -> ready [label="\nspiSelect()\nspiUnselect()\nspiStart()"];
- ready -> stop [label="\nspiStop()"];
- stop -> stop [label="\nspiStop()"];
- ready -> active [label="\nspiStartXXX() (async)\nspiXXX() (sync)"];
- active -> ready [label="\nsync return"];
- active -> complete [label="\nasync callback\n>spc_endcb<"];
- complete -> active [label="\nspiStartXXXI() (async)\nthen\ncallback return"];
- complete -> ready [label="\ncallback return"];
- }
- * @enddot
- * @endif
- *
- * The driver is not thread safe for performance reasons, if you need to access
- * the SPI bus from multiple threads then use the @p spiAcquireBus() and
- * @p spiReleaseBus() APIs in order to gain exclusive access.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/tm.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/tm.dox
deleted file mode 100644
index 81f0b0fde4..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/tm.dox
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup TM Time Measurement Driver
- *
- * @brief Time Measurement unit.
- * @details This module implements a time measurement mechanism able to
- * monitor a portion of code and store the best/worst/last
- * measurement. The measurement is performed using the realtime
- * counter mechanism abstracted in the HAL driver.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/uart.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/uart.dox
deleted file mode 100644
index 8d0da4a2e6..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/uart.dox
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup UART UART Driver
- * @brief Generic UART Driver.
- * @details This driver abstracts a generic UART (Universal Asynchronous
- * Receiver Transmitter) peripheral, the API is designed to be:
- * - Unbuffered and copy-less, transfers are always directly performed
- * from/to the application-level buffers without extra copy
- * operations.
- * - Asynchronous, the API is always non blocking.
- * - Callbacks capable, operations completion and other events are
- * notified using callbacks.
- * .
- * Special hardware features like deep hardware buffers, DMA transfers
- * are hidden to the user but fully supportable by the low level
- * implementations.
- * This driver model is best used where communication events are
- * meant to drive an higher level state machine, as example:
- * - RS485 drivers.
- * - Multipoint network drivers.
- * - Serial protocol decoders.
- * .
- * If your application requires a synchronous buffered driver then
- * the @ref SERIAL should be used instead.
- * @pre In order to use the UART driver the @p HAL_USE_UART option
- * must be enabled in @p halconf.h.
- *
- * @section uart_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- uninit [label="UART_UNINIT", style="bold"];
- stop [label="UART_STOP\nLow Power"];
- ready [label="UART_READY\nClock Enabled"];
-
- uninit -> stop [label="\nuartInit()"];
- stop -> ready [label="\nuartStart()"];
- ready -> ready [label="\nuartStart()"];
- ready -> stop [label="\nuartStop()"];
- stop -> stop [label="\nuartStop()"];
- }
- * @enddot
- *
- * @subsection uart_1_1 Transmitter sub State Machine
- * The follow diagram describes the transmitter state machine, this diagram
- * is valid while the driver is in the @p UART_READY state. This state
- * machine is automatically reset to the @p TX_IDLE state each time the
- * driver enters the @p UART_READY state.
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- tx_idle [label="TX_IDLE", style="bold"];
- tx_active [label="TX_ACTIVE"];
- tx_complete [label="TX_COMPLETE"];
- tx_fatal [label="Fatal Error", style="bold"];
-
- tx_idle -> tx_active [label="\nuartStartSend()"];
- tx_idle -> tx_idle [label="\nuartStopSend()\n>uc_txend2<"];
- tx_active -> tx_complete [label="\nbuffer transmitted\n>uc_txend1<"];
- tx_active -> tx_idle [label="\nuartStopSend()"];
- tx_active -> tx_fatal [label="\nuartStartSend()"];
- tx_complete -> tx_active [label="\nuartStartSendI()\nthen\ncallback return"];
- tx_complete -> tx_idle [label="\ncallback return"];
- }
- * @enddot
- *
- * @subsection uart_1_2 Receiver sub State Machine
- * The follow diagram describes the receiver state machine, this diagram
- * is valid while the driver is in the @p UART_READY state. This state
- * machine is automatically reset to the @p RX_IDLE state each time the
- * driver enters the @p UART_READY state.
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- rx_idle [label="RX_IDLE", style="bold"];
- rx_active [label="RX_ACTIVE"];
- rx_complete [label="RX_COMPLETE"];
- rx_fatal [label="Fatal Error", style="bold"];
-
- rx_idle -> rx_idle [label="\nuartStopReceive()\n>uc_rxchar<\n>uc_rxerr<"];
- rx_idle -> rx_active [label="\nuartStartReceive()"];
-
- rx_active -> rx_complete [label="\nbuffer filled\n>uc_rxend<"];
- rx_active -> rx_idle [label="\nuartStopReceive()"];
- rx_active -> rx_active [label="\nreceive error\n>uc_rxerr<"];
- rx_active -> rx_fatal [label="\nuartStartReceive()"];
- rx_complete -> rx_active [label="\nuartStartReceiveI()\nthen\ncallback return"];
- rx_complete -> rx_idle [label="\ncallback return"];
- }
- * @enddot
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/usb.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/usb.dox
deleted file mode 100644
index 1e21737829..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/dox/usb.dox
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup USB USB Driver
- * @brief Generic USB Driver.
- * @details This module implements a generic USB (Universal Serial Bus) driver
- * supporting device-mode operations.
- * @pre In order to use the USB driver the @p HAL_USE_USB option
- * must be enabled in @p halconf.h.
- *
- * @section usb_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
- digraph example {
- size="5, 7";
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="USB_STOP\nLow Power"];
- uninit [label="USB_UNINIT", style="bold"];
- ready [label="USB_READY\nClock Enabled"];
- selected [label="\nUSB_SELECTED\naddress\nassigned"];
- active [label="\nUSB_ACTIVE\nconfiguration\nselected"];
-
- uninit -> stop [label=" usbInit()", constraint=false];
- stop -> stop [label="\nusbStop()"];
- stop -> ready [label="\nusbStart()"];
- ready -> stop [label="\nusbStop()"];
- ready -> ready [label="\n\nusbStart()"];
- ready -> ready [label="\nSUSPEND/WAKEUP\n>event_cb<"];
- ready -> selected [label="\nSET_ADDRESS\n>event_cb<"];
- selected -> stop [label="\nusbStop()"];
- selected -> ready [label="\nUSB RESET\n>event_cb<"];
- selected -> selected [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<"];
- selected -> active [label="\nSET_CONF(n)\n>event_cb<"];
- active -> stop [label="\nusbStop()"];
- active -> selected [label="\nSET_CONF(0)\n>event_cb<"];
- active -> active [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<\n\nEndpoints Activity\n >in_cb< or >out_cb<"];
- active -> ready [label="\nUSB RESET\n>event_cb<"];
- }
- * @enddot
- * @else
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- stop [label="USB_STOP\nLow Power"];
- uninit [label="USB_UNINIT", style="bold"];
- ready [label="USB_READY\nClock Enabled"];
- selected [label="\nUSB_SELECTED\naddress\nassigned"];
- active [label="\nUSB_ACTIVE\nconfiguration\nselected"];
-
- uninit -> stop [label=" usbInit()", constraint=false];
- stop -> stop [label="\nusbStop()"];
- stop -> ready [label="\nusbStart()"];
- ready -> stop [label="\nusbStop()"];
- ready -> ready [label="\n\nusbStart()"];
- ready -> ready [label="\nSUSPEND/WAKEUP\n>event_cb<"];
- ready -> selected [label="\nSET_ADDRESS\n>event_cb<"];
- selected -> stop [label="\nusbStop()"];
- selected -> ready [label="\nUSB RESET\n>event_cb<"];
- selected -> selected [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<"];
- selected -> active [label="\nSET_CONF(n)\n>event_cb<"];
- active -> stop [label="\nusbStop()"];
- active -> selected [label="\nSET_CONF(0)\n>event_cb<"];
- active -> active [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<\n\nEndpoints Activity\n >in_cb< or >out_cb<"];
- active -> ready [label="\nUSB RESET\n>event_cb<"];
- }
- * @enddot
- * @endif
- *
- * @section usb_2 USB Operations
- * The USB driver is quite complex and USB is complex in itself, it is
- * recommended to study the USB specification before trying to use the
- * driver.
- *
- * @subsection usb_2_1 USB Implementation
- * The USB driver abstracts the inner details of the underlying USB hardware.
- * The driver works asynchronously and communicates with the application
- * using callbacks. The application is responsible of the descriptors and
- * strings required by the USB device class to be implemented and of the
- * handling of the specific messages sent over the endpoint zero. Standard
- * messages are handled internally to the driver. The application can use
- * hooks in order to handle custom messages or override the handling of the
- * default handling of standard messages.
- *
- * @subsection usb_2_2 USB Endpoints
- * USB endpoints are the objects that the application uses to exchange
- * data with the host. There are two kind of endpoints:
- * - IN endpoints are used by the application to transmit data to
- * the host.
- * - OUT endpoints are used by the application to receive data from
- * the host.
- * .
- * The driver invokes a callback after finishing an IN or OUT transaction.
- * States diagram for OUT endpoints in transaction mode:
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- disabled [label="EP_DISABLED\nDisabled", style="bold"];
- receiving [label="EP_BUSY\nReceiving"];
- idle [label="EP_IDLE\nReady"];
-
- disabled -> idle [label="\nusbInitEndpointI()"];
- idle -> receiving [label="\nusbPrepareReceive()\nusbStartReceiveI()"];
- receiving -> receiving [label="\nmore packets"];
- receiving -> idle [label="\nreception end\n>out_cb<"];
- receiving -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"];
- idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"];
- }
- * @enddot
- *
- * States diagram for IN endpoints in transaction mode:
- * @dot
- digraph example {
- rankdir="LR";
- node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
- width="0.9", height="0.9"];
- edge [fontname=Helvetica, fontsize=8];
-
- disabled [label="EP_DISABLED\nDisabled", style="bold"];
- transmitting [label="EP_BUSY\nTransmitting"];
- idle [label="EP_IDLE\nReady"];
-
- disabled -> idle [label="\usbInitEndpointI()"];
- idle -> transmitting [label="\nusbPrepareTransmit()\nusbStartTransmitI()"];
- transmitting -> transmitting [label="\nmore packets"];
- transmitting -> idle [label="\ntransmission end\n>in_cb<"];
- transmitting -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"];
- idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"];
- }
- * @enddot
- *
- *
- * @subsection usb_2_4 USB Callbacks
- * The USB driver uses callbacks in order to interact with the application.
- * There are several kinds of callbacks to be handled:
- * - Driver events callback. As example errors, suspend event, reset event
- * etc.
- * - Messages Hook callback. This hook allows the application to implement
- * handling of custom messages or to override the default handling of
- * standard messages on endpoint zero.
- * - Descriptor Requested callback. When the driver endpoint zero handler
- * receives a GET DESCRIPTOR message and needs to send a descriptor to
- * the host it queries the application using this callback.
- * - Start of Frame callback. This callback is invoked each time a SOF
- * packet is received.
- * - Endpoint callbacks. Each endpoint informs the application about I/O
- * conditions using those callbacks.
- * .
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/hal.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/hal.dox
deleted file mode 100644
index a3b7923c49..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/hal.dox
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup IO HAL
- * @brief Hardware Abstraction Layer.
- * @details Under ChibiOS/RT the set of the various device driver interfaces
- * is called the HAL subsystem: Hardware Abstraction Layer. The HAL is the
- * abstract interface between ChibiOS/RT application and hardware.
- *
- * @section hal_device_driver_arch HAL Device Drivers Architecture
- * A device driver is usually split in two layers:
- * - High Level Device Driver (HLD). This layer contains the definitions
- * of the driver's APIs and the platform independent part of the driver.
- * An HLD is composed by two files:
- * - @p @.c, the HLD implementation file. This file must be
- * included in the Makefile in order to use the driver.
- * - @p @.h, the HLD header file. This file is implicitly
- * included by the HAL header file @p hal.h.
- * .
- * - Low Level Device Driver (LLD). This layer contains the platform
- * dependent part of the driver.
- * A LLD is composed by two files:
- * - @p @_lld.c, the LLD implementation file. This file must be
- * included in the Makefile in order to use the driver.
- * - @p @_lld.h, the LLD header file. This file is implicitly
- * included by the HLD header file.
- * .
- * The LLD may be not present in those drivers that do not access the
- * hardware directly but through other device drivers, as example the
- * MMC_SPI driver uses the SPI and PAL drivers in order to implement
- * its functionalities.
- * .
- * @subsection hal_device_driver_diagram Diagram
- * @dot
- digraph example {
- graph [size="5, 7", pad="1.5, 0"];
- node [shape=rectangle, fontname=Helvetica, fontsize=8,
- fixedsize="true", width="2.0", height="0.4"];
- edge [fontname=Helvetica, fontsize=8];
-
- app [label="Application"];
- hld [label="High Level Driver"];
- lld [label="Low Level Driver"];
- hw [label="Microcontroller Hardware"];
- hal_lld [label="HAL shared low level code"];
-
- app->hld;
- hld->lld;
- lld-> hw;
- lld->hal_lld;
- hal_lld->hw;
- }
- * @enddot
- */
-
-/**
- * @defgroup HAL_CONF Configuration
- * @brief HAL Configuration.
- * @details The file @p halconf.h contains the high level settings for all
- * the drivers supported by the HAL. The low level, platform dependent,
- * settings are contained in the @p mcuconf.h file instead and are describe
- * in the various platforms reference manuals.
- *
- * @ingroup IO
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/hal.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/hal.mk
index f3fa3f758f..367faf1299 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/hal.mk
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/hal.mk
@@ -1,25 +1,104 @@
-# List of all the ChibiOS/RT HAL files, there is no need to remove the files
+# List of all the ChibiOS/HAL files, there is no need to remove the files
# from this list, you can disable parts of the HAL by editing halconf.h.
-HALSRC = ${CHIBIOS}/os/hal/src/hal.c \
- ${CHIBIOS}/os/hal/src/adc.c \
- ${CHIBIOS}/os/hal/src/can.c \
- ${CHIBIOS}/os/hal/src/ext.c \
- ${CHIBIOS}/os/hal/src/gpt.c \
- ${CHIBIOS}/os/hal/src/i2c.c \
- ${CHIBIOS}/os/hal/src/icu.c \
- ${CHIBIOS}/os/hal/src/mac.c \
- ${CHIBIOS}/os/hal/src/mmc_spi.c \
- ${CHIBIOS}/os/hal/src/mmcsd.c \
- ${CHIBIOS}/os/hal/src/pal.c \
- ${CHIBIOS}/os/hal/src/pwm.c \
- ${CHIBIOS}/os/hal/src/rtc.c \
- ${CHIBIOS}/os/hal/src/sdc.c \
- ${CHIBIOS}/os/hal/src/serial.c \
- ${CHIBIOS}/os/hal/src/serial_usb.c \
- ${CHIBIOS}/os/hal/src/spi.c \
- ${CHIBIOS}/os/hal/src/tm.c \
- ${CHIBIOS}/os/hal/src/uart.c \
- ${CHIBIOS}/os/hal/src/usb.c
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+HALSRC := $(CHIBIOS)/os/hal/src/hal.c \
+ $(CHIBIOS)/os/hal/src/hal_st.c \
+ $(CHIBIOS)/os/hal/src/hal_buffers.c \
+ $(CHIBIOS)/os/hal/src/hal_queues.c \
+ $(CHIBIOS)/os/hal/src/hal_mmcsd.c
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_adc.c
+endif
+ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_can.c
+endif
+ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_dac.c
+endif
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_ext.c
+endif
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_gpt.c
+endif
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_i2c.c
+endif
+ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_i2s.c
+endif
+ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_icu.c
+endif
+ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_mac.c
+endif
+ifneq ($(findstring HAL_USE_MMC_SPI TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_mmc_spi.c
+endif
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_pal.c
+endif
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_pwm.c
+endif
+ifneq ($(findstring HAL_USE_QSPI TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_qspi.c
+endif
+ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_rtc.c
+endif
+ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_sdc.c
+endif
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_serial.c
+endif
+ifneq ($(findstring HAL_USE_SERIAL_USB TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_serial_usb.c
+endif
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_spi.c
+endif
+ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_uart.c
+endif
+ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_usb.c
+endif
+ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
+HALSRC += $(CHIBIOS)/os/hal/src/hal_wdg.c
+endif
+else
+HALSRC = $(CHIBIOS)/os/hal/src/hal.c \
+ $(CHIBIOS)/os/hal/src/hal_buffers.c \
+ $(CHIBIOS)/os/hal/src/hal_queues.c \
+ $(CHIBIOS)/os/hal/src/hal_mmcsd.c \
+ $(CHIBIOS)/os/hal/src/hal_adc.c \
+ $(CHIBIOS)/os/hal/src/hal_can.c \
+ $(CHIBIOS)/os/hal/src/hal_dac.c \
+ $(CHIBIOS)/os/hal/src/hal_ext.c \
+ $(CHIBIOS)/os/hal/src/hal_gpt.c \
+ $(CHIBIOS)/os/hal/src/hal_i2c.c \
+ $(CHIBIOS)/os/hal/src/hal_i2s.c \
+ $(CHIBIOS)/os/hal/src/hal_icu.c \
+ $(CHIBIOS)/os/hal/src/hal_mac.c \
+ $(CHIBIOS)/os/hal/src/hal_mmc_spi.c \
+ $(CHIBIOS)/os/hal/src/hal_pal.c \
+ $(CHIBIOS)/os/hal/src/hal_pwm.c \
+ $(CHIBIOS)/os/hal/src/hal_qspi.c \
+ $(CHIBIOS)/os/hal/src/hal_rtc.c \
+ $(CHIBIOS)/os/hal/src/hal_sdc.c \
+ $(CHIBIOS)/os/hal/src/hal_serial.c \
+ $(CHIBIOS)/os/hal/src/hal_serial_usb.c \
+ $(CHIBIOS)/os/hal/src/hal_spi.c \
+ $(CHIBIOS)/os/hal/src/hal_st.c \
+ $(CHIBIOS)/os/hal/src/hal_uart.c \
+ $(CHIBIOS)/os/hal/src/hal_usb.c \
+ $(CHIBIOS)/os/hal/src/hal_wdg.c
+endif
# Required include directories
-HALINC = ${CHIBIOS}/os/hal/include
+HALINC = $(CHIBIOS)/os/hal/include
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal.h
index 74d87b4825..9d756a7aa2 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal.h
@@ -1,28 +1,17 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
@@ -33,170 +22,206 @@
* @{
*/
-#ifndef _HAL_H_
-#define _HAL_H_
+#ifndef HAL_H
+#define HAL_H
-#include "ch.h"
+#include "osal.h"
#include "board.h"
#include "halconf.h"
+/* Error checks on the configuration header file.*/
+#if !defined(HAL_USE_PAL)
+#define HAL_USE_PAL FALSE
+#endif
+
+#if !defined(HAL_USE_ADC)
+#define HAL_USE_ADC FALSE
+#endif
+
+#if !defined(HAL_USE_CAN)
+#define HAL_USE_CAN FALSE
+#endif
+
+#if !defined(HAL_USE_DAC)
+#define HAL_USE_DAC FALSE
+#endif
+
+#if !defined(HAL_USE_EXT)
+#define HAL_USE_ETX FALSE
+#endif
+
+#if !defined(HAL_USE_GPT)
+#define HAL_USE_GPT FALSE
+#endif
+
+#if !defined(HAL_USE_I2C)
+#define HAL_USE_I2C FALSE
+#endif
+
+#if !defined(HAL_USE_I2S)
+#define HAL_USE_I2S FALSE
+#endif
+
+#if !defined(HAL_USE_ICU)
+#define HAL_USE_ICU FALSE
+#endif
+
+#if !defined(HAL_USE_MAC)
+#define HAL_USE_MAC FALSE
+#endif
+
+#if !defined(HAL_USE_PWM)
+#define HAL_USE_PWM FALSE
+#endif
+
+#if !defined(HAL_USE_QSPI)
+#define HAL_USE_QSPI FALSE
+#endif
+
+#if !defined(HAL_USE_RTC)
+#define HAL_USE_RTC FALSE
+#endif
+
+#if !defined(HAL_USE_SERIAL)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+#if !defined(HAL_USE_SDC)
+#define HAL_USE_SDC FALSE
+#endif
+
+#if !defined(HAL_USE_SPI)
+#define HAL_USE_SPI FALSE
+#endif
+
+#if !defined(HAL_USE_UART)
+#define HAL_USE_UART FALSE
+#endif
+
+#if !defined(HAL_USE_USB)
+#define HAL_USE_USB FALSE
+#endif
+
+#if !defined(HAL_USE_WDG)
+#define HAL_USE_WDG FALSE
+#endif
+
+/* Low Level HAL support.*/
#include "hal_lld.h"
/* Abstract interfaces.*/
-#include "io_channel.h"
-#include "io_block.h"
+#include "hal_streams.h"
+#include "hal_channels.h"
+#include "hal_files.h"
+#include "hal_ioblock.h"
+#include "hal_mmcsd.h"
/* Shared headers.*/
-#include "mmcsd.h"
-
-/* Layered drivers.*/
-#include "tm.h"
-#include "pal.h"
-#include "adc.h"
-#include "can.h"
-#include "ext.h"
-#include "gpt.h"
-#include "i2c.h"
-#include "icu.h"
-#include "mac.h"
-#include "pwm.h"
-#include "rtc.h"
-#include "serial.h"
-#include "sdc.h"
-#include "spi.h"
-#include "uart.h"
-#include "usb.h"
-
-/* Complex drivers.*/
-#include "mmc_spi.h"
-#include "serial_usb.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
+#include "hal_buffers.h"
+#include "hal_queues.h"
+
+/* Normal drivers.*/
+#include "hal_pal.h"
+#include "hal_adc.h"
+#include "hal_can.h"
+#include "hal_dac.h"
+#include "hal_ext.h"
+#include "hal_gpt.h"
+#include "hal_i2c.h"
+#include "hal_i2s.h"
+#include "hal_icu.h"
+#include "hal_mac.h"
+#include "hal_pwm.h"
+#include "hal_qspi.h"
+#include "hal_rtc.h"
+#include "hal_serial.h"
+#include "hal_sdc.h"
+#include "hal_spi.h"
+#include "hal_uart.h"
+#include "hal_usb.h"
+#include "hal_wdg.h"
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
+/*
+ * The ST driver is a special case, it is only included if the OSAL is
+ * configured to require it.
+ */
+#if OSAL_ST_MODE != OSAL_ST_MODE_NONE
+#include "hal_st.h"
+#endif
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
+/* Complex drivers.*/
+#include "hal_mmc_spi.h"
+#include "hal_serial_usb.h"
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
+/* Community drivers.*/
+#if defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#if (HAL_USE_COMMUNITY == TRUE) || defined(__DOXYGEN__)
+#include "hal_community.h"
+#endif
+#endif
/*===========================================================================*/
-/* Driver macros. */
+/* Driver constants. */
/*===========================================================================*/
-#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__)
/**
- * @name Time conversion utilities for the realtime counter
- * @{
+ * @brief ChibiOS/HAL identification macro.
*/
+#define _CHIBIOS_HAL_
+
/**
- * @brief Seconds to realtime ticks.
- * @details Converts from seconds to realtime ticks number.
- * @note The result is rounded upward to the next tick boundary.
- *
- * @param[in] sec number of seconds
- * @return The number of ticks.
- *
- * @api
+ * @brief Stable release flag.
*/
-#define S2RTT(sec) (halGetCounterFrequency() * (sec))
+#define CH_HAL_STABLE 1
/**
- * @brief Milliseconds to realtime ticks.
- * @details Converts from milliseconds to realtime ticks number.
- * @note The result is rounded upward to the next tick boundary.
- *
- * @param[in] msec number of milliseconds
- * @return The number of ticks.
- *
- * @api
+ * @name ChibiOS/HAL version identification
+ * @{
*/
-#define MS2RTT(msec) (((halGetCounterFrequency() + 999UL) / 1000UL) * (msec))
-
/**
- * @brief Microseconds to realtime ticks.
- * @details Converts from microseconds to realtime ticks number.
- * @note The result is rounded upward to the next tick boundary.
- *
- * @param[in] usec number of microseconds
- * @return The number of ticks.
- *
- * @api
+ * @brief HAL version string.
*/
-#define US2RTT(usec) (((halGetCounterFrequency() + 999999UL) / 1000000UL) * \
- (usec))
+#define HAL_VERSION "5.1.2"
/**
- * @brief Realtime ticks to seconds to.
- * @details Converts from realtime ticks number to seconds.
- *
- * @param[in] ticks number of ticks
- * @return The number of seconds.
- *
- * @api
+ * @brief HAL version major number.
*/
-#define RTT2S(ticks) ((ticks) / halGetCounterFrequency())
+#define CH_HAL_MAJOR 5
/**
- * @brief Realtime ticks to milliseconds.
- * @details Converts from realtime ticks number to milliseconds.
- *
- * @param[in] ticks number of ticks
- * @return The number of milliseconds.
- *
- * @api
+ * @brief HAL version minor number.
*/
-#define RTT2MS(ticks) ((ticks) / (halGetCounterFrequency() / 1000UL))
+#define CH_HAL_MINOR 1
/**
- * @brief Realtime ticks to microseconds.
- * @details Converts from realtime ticks number to microseconds.
- *
- * @param[in] ticks number of ticks
- * @return The number of microseconds.
- *
- * @api
+ * @brief HAL version patch number.
*/
-#define RTT2US(ticks) ((ticks) / (halGetCounterFrequency() / 1000000UL))
+#define CH_HAL_PATCH 2
/** @} */
/**
- * @name Macro Functions
+ * @name Return codes
* @{
*/
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This is an optional service that could not be implemented in
- * all HAL implementations.
- * @note This function can be called from any context.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @special
- */
-#define halGetCounterValue() hal_lld_get_counter_value()
-
-/**
- * @brief Realtime counter frequency.
- * @note This is an optional service that could not be implemented in
- * all HAL implementations.
- * @note This function can be called from any context.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @special
- */
-#define halGetCounterFrequency() hal_lld_get_counter_frequency()
+#define HAL_SUCCESS false
+#define HAL_FAILED true
/** @} */
-#endif /* HAL_IMPLEMENTS_COUNTERS */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
@@ -206,14 +231,10 @@
extern "C" {
#endif
void halInit(void);
-#if HAL_IMPLEMENTS_COUNTERS
- bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end);
- void halPolledDelay(halrtcnt_t ticks);
-#endif /* HAL_IMPLEMENTS_COUNTERS */
#ifdef __cplusplus
}
#endif
-#endif /* _HAL_H_ */
+#endif /* HAL_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/adc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_adc.h
similarity index 70%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/adc.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_adc.h
index 120f631280..c4ea60c5f8 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/adc.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_adc.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file adc.h
+ * @file hal_adc.h
* @brief ADC Driver macros and structures.
*
* @addtogroup ADC
* @{
*/
-#ifndef _ADC_H_
-#define _ADC_H_
+#ifndef HAL_ADC_H
+#define HAL_ADC_H
-#if HAL_USE_ADC || defined(__DOXYGEN__)
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -71,10 +60,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if ADC_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "ADC_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -88,20 +73,20 @@ typedef enum {
ADC_READY = 2, /**< Ready. */
ADC_ACTIVE = 3, /**< Converting. */
ADC_COMPLETE = 4, /**< Conversion complete. */
- ADC_ERROR = 5 /**< Conversion complete. */
+ ADC_ERROR = 5 /**< Conversion error. */
} adcstate_t;
-#include "adc_lld.h"
+#include "hal_adc_lld.h"
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
- * @name Low Level driver helper macros
+ * @name Low level driver helper macros
* @{
*/
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
/**
* @brief Resumes a thread waiting for a conversion completion.
*
@@ -109,14 +94,8 @@ typedef enum {
*
* @notapi
*/
-#define _adc_reset_i(adcp) { \
- if ((adcp)->thread != NULL) { \
- Thread *tp = (adcp)->thread; \
- (adcp)->thread = NULL; \
- tp->p_u.rdymsg = RDY_RESET; \
- chSchReadyI(tp); \
- } \
-}
+#define _adc_reset_i(adcp) \
+ osalThreadResumeI(&(adcp)->thread, MSG_RESET)
/**
* @brief Resumes a thread waiting for a conversion completion.
@@ -125,13 +104,8 @@ typedef enum {
*
* @notapi
*/
-#define _adc_reset_s(adcp) { \
- if ((adcp)->thread != NULL) { \
- Thread *tp = (adcp)->thread; \
- (adcp)->thread = NULL; \
- chSchWakeupS(tp, RDY_RESET); \
- } \
-}
+#define _adc_reset_s(adcp) \
+ osalThreadResumeS(&(adcp)->thread, MSG_RESET)
/**
* @brief Wakes up the waiting thread.
@@ -141,15 +115,9 @@ typedef enum {
* @notapi
*/
#define _adc_wakeup_isr(adcp) { \
- chSysLockFromIsr(); \
- if ((adcp)->thread != NULL) { \
- Thread *tp; \
- tp = (adcp)->thread; \
- (adcp)->thread = NULL; \
- tp->p_u.rdymsg = RDY_OK; \
- chSchReadyI(tp); \
- } \
- chSysUnlockFromIsr(); \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(adcp)->thread, MSG_OK); \
+ osalSysUnlockFromISR(); \
}
/**
@@ -160,15 +128,9 @@ typedef enum {
* @notapi
*/
#define _adc_timeout_isr(adcp) { \
- chSysLockFromIsr(); \
- if ((adcp)->thread != NULL) { \
- Thread *tp; \
- tp = (adcp)->thread; \
- (adcp)->thread = NULL; \
- tp->p_u.rdymsg = RDY_TIMEOUT; \
- chSchReadyI(tp); \
- } \
- chSysUnlockFromIsr(); \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(adcp)->thread, MSG_TIMEOUT); \
+ osalSysUnlockFromISR(); \
}
#else /* !ADC_USE_WAIT */
@@ -268,8 +230,12 @@ typedef enum {
(adcp)->grpp->error_cb(adcp, err); \
if ((adcp)->state == ADC_ERROR) \
(adcp)->state = ADC_READY; \
+ (adcp)->grpp = NULL; \
+ } \
+ else { \
+ (adcp)->state = ADC_READY; \
+ (adcp)->grpp = NULL; \
} \
- (adcp)->grpp = NULL; \
_adc_timeout_isr(adcp); \
}
/** @} */
@@ -295,22 +261,22 @@ extern "C" {
size_t depth);
void adcStopConversion(ADCDriver *adcp);
void adcStopConversionI(ADCDriver *adcp);
-#if ADC_USE_WAIT
+#if ADC_USE_WAIT == TRUE
msg_t adcConvert(ADCDriver *adcp,
const ADCConversionGroup *grpp,
adcsample_t *samples,
size_t depth);
#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if ADC_USE_MUTUAL_EXCLUSION == TRUE
void adcAcquireBus(ADCDriver *adcp);
void adcReleaseBus(ADCDriver *adcp);
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#endif
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_ADC */
+#endif /* HAL_USE_ADC == TRUE */
-#endif /* _ADC_H_ */
+#endif /* HAL_ADC_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_buffers.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_buffers.h
new file mode 100644
index 0000000000..96bb926c92
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_buffers.h
@@ -0,0 +1,319 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_buffers.h
+ * @brief I/O Buffers macros and structures.
+ *
+ * @addtogroup HAL_BUFFERS
+ * @{
+ */
+
+#ifndef HAL_BUFFERS_H
+#define HAL_BUFFERS_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a generic queue of buffers.
+ */
+typedef struct io_buffers_queue io_buffers_queue_t;
+
+/**
+ * @brief Double buffer notification callback type.
+ *
+ * @param[in] iodbp the buffers queue pointer
+ */
+typedef void (*bqnotify_t)(io_buffers_queue_t *bqp);
+
+/**
+ * @brief Structure of a generic buffers queue.
+ */
+struct io_buffers_queue {
+ /**
+ * @brief Queue of waiting threads.
+ */
+ threads_queue_t waiting;
+ /**
+ * @brief Queue suspended state flag.
+ */
+ bool suspended;
+ /**
+ * @brief Active buffers counter.
+ */
+ volatile size_t bcounter;
+ /**
+ * @brief Buffer write pointer.
+ */
+ uint8_t *bwrptr;
+ /**
+ * @brief Buffer read pointer.
+ */
+ uint8_t *brdptr;
+ /**
+ * @brief Pointer to the buffers boundary.
+ */
+ uint8_t *btop;
+ /**
+ * @brief Size of buffers.
+ * @note The buffer size must be not lower than sizeof(size_t) + 2
+ * because the first bytes are used to store the used size of the
+ * buffer.
+ */
+ size_t bsize;
+ /**
+ * @brief Number of buffers.
+ */
+ size_t bn;
+ /**
+ * @brief Queue of buffer objects.
+ */
+ uint8_t *buffers;
+ /**
+ * @brief Pointer for R/W sequential access.
+ * @note It is @p NULL if a new buffer must be fetched from the queue.
+ */
+ uint8_t *ptr;
+ /**
+ * @brief Boundary for R/W sequential access.
+ */
+ uint8_t *top;
+ /**
+ * @brief Data notification callback.
+ */
+ bqnotify_t notify;
+ /**
+ * @brief Application defined field.
+ */
+ void *link;
+};
+
+/**
+ * @brief Type of an input buffers queue.
+ */
+typedef io_buffers_queue_t input_buffers_queue_t;
+
+/**
+ * @brief Type of an output buffers queue.
+ */
+typedef io_buffers_queue_t output_buffers_queue_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Computes the size of a buffers queue buffer size.
+ *
+ * @param[in] n number of buffers in the queue
+ * @param[in] size size of the buffers
+ */
+#define BQ_BUFFER_SIZE(n, size) \
+ (((size_t)(size) + sizeof (size_t)) * (size_t)(n))
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Returns the queue's number of buffers.
+ *
+ * @param[in] bqp pointer to an @p io_buffers_queue_t structure
+ * @return The number of buffers.
+ *
+ * @xclass
+ */
+#define bqSizeX(bqp) ((bqp)->bn)
+
+/**
+ * @brief Return the ready buffers number.
+ * @details Returns the number of filled buffers if used on an input queue
+ * or the number of empty buffers if used on an output queue.
+ *
+ * @param[in] bqp pointer to an @p io_buffers_queue_t structure
+ * @return The number of ready buffers.
+ *
+ * @iclass
+ */
+#define bqSpaceI(bqp) ((bqp)->bcounter)
+
+/**
+ * @brief Returns the queue application-defined link.
+ *
+ * @param[in] bqp pointer to an @p io_buffers_queue_t structure
+ * @return The application-defined link.
+ *
+ * @special
+ */
+#define bqGetLinkX(bqp) ((bqp)->link)
+
+/**
+ * @brief Return the suspended state of the queue.
+ *
+ * @param[in] bqp pointer to an @p io_buffers_queue_t structure
+ * @return The suspended state.
+ * @retval false if blocking access to the queue is enabled.
+ * @retval true if blocking access to the queue is suspended.
+ *
+ * @xclass
+ */
+#define bqIsSuspendedX(bqp) ((bqp)->suspended)
+
+/**
+ * @brief Puts the queue in suspended state.
+ * @details When the queue is put in suspended state all waiting threads are
+ * woken with message @p MSG_RESET and subsequent attempt at waiting
+ * on the queue will result in an immediate return with @p MSG_RESET
+ * message.
+ * @note The content of the queue is not altered, queues can be accessed
+ * is suspended state until a blocking operation is met then a
+ * @p MSG_RESET occurs.
+ *
+ * @param[in] bqp pointer to an @p io_buffers_queue_t structure
+ *
+ * @iclass
+ */
+#define bqSuspendI(bqp) { \
+ (bqp)->suspended = true; \
+ osalThreadDequeueAllI(&(bqp)->waiting, MSG_RESET); \
+}
+
+/**
+ * @brief Resumes normal queue operations.
+ *
+ * @param[in] bqp pointer to an @p io_buffers_queue_t structure
+ *
+ * @xclass
+ */
+#define bqResumeX(bqp) { \
+ (bqp)->suspended = false; \
+}
+
+/**
+ * @brief Evaluates to @p TRUE if the specified input buffers queue is empty.
+ *
+ * @param[in] ibqp pointer to an @p input_buffers_queue_t structure
+ * @return The queue status.
+ * @retval false if the queue is not empty.
+ * @retval true if the queue is empty.
+ *
+ * @iclass
+ */
+#define ibqIsEmptyI(ibqp) ((bool)(bqSpaceI(ibqp) == 0U))
+
+/**
+ * @brief Evaluates to @p TRUE if the specified input buffers queue is full.
+ *
+ * @param[in] ibqp pointer to an @p input_buffers_queue_t structure
+ * @return The queue status.
+ * @retval false if the queue is not full.
+ * @retval true if the queue is full.
+ *
+ * @iclass
+ */
+#define ibqIsFullI(ibqp) \
+ /*lint -save -e9007 [13.5] No side effects, a pointer is passed.*/ \
+ ((bool)(((ibqp)->bwrptr == (ibqp)->brdptr) && ((ibqp)->bcounter != 0U))) \
+ /*lint -restore*/
+
+/**
+ * @brief Evaluates to @p true if the specified output buffers queue is empty.
+ *
+ * @param[in] obqp pointer to an @p output_buffers_queue_t structure
+ * @return The queue status.
+ * @retval false if the queue is not empty.
+ * @retval true if the queue is empty.
+ *
+ * @iclass
+ */
+#define obqIsEmptyI(obqp) \
+ /*lint -save -e9007 [13.5] No side effects, a pointer is passed.*/ \
+ ((bool)(((obqp)->bwrptr == (obqp)->brdptr) && ((obqp)->bcounter != 0U))) \
+ /*lint -restore*/
+
+/**
+ * @brief Evaluates to @p true if the specified output buffers queue is full.
+ *
+ * @param[in] obqp pointer to an @p output_buffers_queue_t structure
+ * @return The queue status.
+ * @retval false if the queue is not full.
+ * @retval true if the queue is full.
+ *
+ * @iclass
+ */
+#define obqIsFullI(obqp) ((bool)(bqSpaceI(obqp) == 0U))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ibqObjectInit(input_buffers_queue_t *ibqp, bool suspended, uint8_t *bp,
+ size_t size, size_t n, bqnotify_t infy, void *link);
+ void ibqResetI(input_buffers_queue_t *ibqp);
+ uint8_t *ibqGetEmptyBufferI(input_buffers_queue_t *ibqp);
+ void ibqPostFullBufferI(input_buffers_queue_t *ibqp, size_t size);
+ msg_t ibqGetFullBufferTimeout(input_buffers_queue_t *ibqp,
+ systime_t timeout);
+ msg_t ibqGetFullBufferTimeoutS(input_buffers_queue_t *ibqp,
+ systime_t timeout);
+ void ibqReleaseEmptyBuffer(input_buffers_queue_t *ibqp);
+ void ibqReleaseEmptyBufferS(input_buffers_queue_t *ibqp);
+ msg_t ibqGetTimeout(input_buffers_queue_t *ibqp, systime_t timeout);
+ size_t ibqReadTimeout(input_buffers_queue_t *ibqp, uint8_t *bp,
+ size_t n, systime_t timeout);
+ void obqObjectInit(output_buffers_queue_t *obqp, bool suspended, uint8_t *bp,
+ size_t size, size_t n, bqnotify_t onfy, void *link);
+ void obqResetI(output_buffers_queue_t *obqp);
+ uint8_t *obqGetFullBufferI(output_buffers_queue_t *obqp,
+ size_t *sizep);
+ void obqReleaseEmptyBufferI(output_buffers_queue_t *obqp);
+ msg_t obqGetEmptyBufferTimeout(output_buffers_queue_t *obqp,
+ systime_t timeout);
+ msg_t obqGetEmptyBufferTimeoutS(output_buffers_queue_t *obqp,
+ systime_t timeout);
+ void obqPostFullBuffer(output_buffers_queue_t *obqp, size_t size);
+ void obqPostFullBufferS(output_buffers_queue_t *obqp, size_t size);
+ msg_t obqPutTimeout(output_buffers_queue_t *obqp, uint8_t b,
+ systime_t timeout);
+ size_t obqWriteTimeout(output_buffers_queue_t *obqp, const uint8_t *bp,
+ size_t n, systime_t timeout);
+ bool obqTryFlushI(output_buffers_queue_t *obqp);
+ void obqFlush(output_buffers_queue_t *obqp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_BUFFERS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/can.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_can.h
similarity index 61%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/can.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_can.h
index 99d2604c10..24bd9efc10 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/can.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_can.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file can.h
+ * @file hal_can.h
* @brief CAN Driver macros and structures.
*
* @addtogroup CAN
* @{
*/
-#ifndef _CAN_H_
-#define _CAN_H_
+#ifndef HAL_CAN_H
+#define HAL_CAN_H
-#if HAL_USE_CAN || defined(__DOXYGEN__)
+#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -49,23 +38,23 @@
/**
* @brief Errors rate warning.
*/
-#define CAN_LIMIT_WARNING 1
+#define CAN_LIMIT_WARNING 1U
/**
* @brief Errors rate error.
*/
-#define CAN_LIMIT_ERROR 2
+#define CAN_LIMIT_ERROR 2U
/**
* @brief Bus off condition reached.
*/
-#define CAN_BUS_OFF_ERROR 4
+#define CAN_BUS_OFF_ERROR 4U
/**
* @brief Framing error of some kind on the CAN bus.
*/
-#define CAN_FRAMING_ERROR 8
+#define CAN_FRAMING_ERROR 8U
/**
* @brief Overflow in receive queue.
*/
-#define CAN_OVERFLOW_ERROR 16
+#define CAN_OVERFLOW_ERROR 16U
/** @} */
/**
@@ -96,10 +85,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS
-#error "CAN driver requires CH_USE_SEMAPHORES and CH_USE_EVENTS"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -115,7 +100,7 @@ typedef enum {
CAN_SLEEP = 4 /**< Sleep state. */
} canstate_t;
-#include "can_lld.h"
+#include "hal_can_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -128,7 +113,23 @@ typedef enum {
/**
* @brief Converts a mailbox index to a bit mask.
*/
-#define CAN_MAILBOX_TO_MASK(mbx) (1 << ((mbx) - 1))
+#define CAN_MAILBOX_TO_MASK(mbx) (1U << ((mbx) - 1U))
+
+/**
+ * @brief Legacy name for @p canTransmitTimeout().
+ *
+ * @deprecated
+ */
+#define canTransmit(canp, mailbox, ctfp, timeout) \
+ canTransmitTimeout(canp, mailbox, ctfp, timeout)
+
+/**
+ * @brief Legacy name for @p canReceiveTimeout().
+ *
+ * @deprecated
+ */
+#define canReceive(canp, mailbox, crfp, timeout) \
+ canReceiveTimeout(canp, mailbox, crfp, timeout)
/** @} */
/*===========================================================================*/
@@ -142,24 +143,30 @@ extern "C" {
void canObjectInit(CANDriver *canp);
void canStart(CANDriver *canp, const CANConfig *config);
void canStop(CANDriver *canp);
- msg_t canTransmit(CANDriver *canp,
- canmbx_t mailbox,
- const CANTxFrame *ctfp,
- systime_t timeout);
- msg_t canReceive(CANDriver *canp,
- canmbx_t mailbox,
- CANRxFrame *crfp,
- systime_t timeout);
+ bool canTryTransmitI(CANDriver *canp,
+ canmbx_t mailbox,
+ const CANTxFrame *ctfp);
+ bool canTryReceiveI(CANDriver *canp,
+ canmbx_t mailbox,
+ CANRxFrame *crfp);
+ msg_t canTransmitTimeout(CANDriver *canp,
+ canmbx_t mailbox,
+ const CANTxFrame *ctfp,
+ systime_t timeout);
+ msg_t canReceiveTimeout(CANDriver *canp,
+ canmbx_t mailbox,
+ CANRxFrame *crfp,
+ systime_t timeout);
#if CAN_USE_SLEEP_MODE
void canSleep(CANDriver *canp);
void canWakeup(CANDriver *canp);
-#endif /* CAN_USE_SLEEP_MODE */
+#endif
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_CAN */
+#endif /* HAL_USE_CAN == TRUE */
-#endif /* _CAN_H_ */
+#endif /* HAL_CAN_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/io_channel.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_channels.h
similarity index 81%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/io_channel.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_channels.h
index 7de6ea6c21..f92d4d8f59 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/io_channel.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_channels.h
@@ -1,32 +1,21 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file io_channel.h
+ * @file hal_channels.h
* @brief I/O channels access.
* @details This header defines an abstract interface useful to access generic
* I/O serial devices in a standardized way.
@@ -44,8 +33,8 @@
* @{
*/
-#ifndef _IO_CHANNEL_H_
-#define _IO_CHANNEL_H_
+#ifndef HAL_CHANNELS_H
+#define HAL_CHANNELS_H
/**
* @brief @p BaseChannel specific methods.
@@ -109,9 +98,9 @@ typedef struct {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval Q_OK if the operation succeeded.
- * @retval Q_TIMEOUT if the specified time expired.
- * @retval Q_RESET if the channel associated queue (if any) was reset.
+ * @retval STM_OK if the operation succeeded.
+ * @retval STM_TIMEOUT if the specified time expired.
+ * @retval STM_RESET if the channel associated queue (if any) was reset.
*
* @api
*/
@@ -129,8 +118,8 @@ typedef struct {
* - @a TIME_INFINITE no timeout.
* .
* @return A byte value from the queue.
- * @retval Q_TIMEOUT if the specified time expired.
- * @retval Q_RESET if the channel associated queue (if any) has been
+ * @retval STM_TIMEOUT if the specified time expired.
+ * @retval STM_RESET if the channel associated queue (if any) has been
* reset.
*
* @api
@@ -150,7 +139,7 @@ typedef struct {
*
* @api
*/
-#define chnWrite(ip, bp, n) chSequentialStreamWrite(ip, bp, n)
+#define chnWrite(ip, bp, n) streamWrite(ip, bp, n)
/**
* @brief Channel blocking write with timeout.
@@ -184,7 +173,7 @@ typedef struct {
*
* @api
*/
-#define chnRead(ip, bp, n) chSequentialStreamRead(ip, bp, n)
+#define chnRead(ip, bp, n) streamRead(ip, bp, n)
/**
* @brief Channel blocking read with timeout.
@@ -206,23 +195,22 @@ typedef struct {
#define chnReadTimeout(ip, bp, n, time) ((ip)->vmt->readt(ip, bp, n, time))
/** @} */
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
/**
* @name I/O status flags added to the event listener
* @{
*/
/** @brief No pending conditions.*/
-#define CHN_NO_ERROR 0
+#define CHN_NO_ERROR (eventflags_t)0
/** @brief Connection happened.*/
-#define CHN_CONNECTED 1
+#define CHN_CONNECTED (eventflags_t)1
/** @brief Disconnection happened.*/
-#define CHN_DISCONNECTED 2
+#define CHN_DISCONNECTED (eventflags_t)2
/** @brief Data available in the input queue.*/
-#define CHN_INPUT_AVAILABLE 4
+#define CHN_INPUT_AVAILABLE (eventflags_t)4
/** @brief Output queue empty.*/
-#define CHN_OUTPUT_EMPTY 8
+#define CHN_OUTPUT_EMPTY (eventflags_t)8
/** @brief Transmission end.*/
-#define CHN_TRANSMISSION_END 16
+#define CHN_TRANSMISSION_END (eventflags_t)16
/** @} */
/**
@@ -237,7 +225,7 @@ typedef struct {
#define _base_asynchronous_channel_data \
_base_channel_data \
/* I/O condition event source.*/ \
- EventSource event;
+ event_source_t event;
/**
* @extends BaseChannelVMT
@@ -290,12 +278,10 @@ typedef struct {
* @iclass
*/
#define chnAddFlagsI(ip, flags) { \
- chEvtBroadcastFlagsI(&(ip)->event, flags); \
+ osalEventBroadcastFlagsI(&(ip)->event, flags); \
}
/** @} */
-#endif /* CH_USE_EVENTS */
-
-#endif /* _IO_CHANNEL_H_ */
+#endif /* HAL_CHANNELS_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_dac.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_dac.h
new file mode 100644
index 0000000000..38d047ebea
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_dac.h
@@ -0,0 +1,267 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_dac.h
+ * @brief DAC Driver macros and structures.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#ifndef HAL_DAC_H
+#define HAL_DAC_H
+
+#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name DAC configuration options
+ * @{
+ */
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
+#define DAC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define DAC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ DAC_UNINIT = 0, /**< Not initialized. */
+ DAC_STOP = 1, /**< Stopped. */
+ DAC_READY = 2, /**< Ready. */
+ DAC_ACTIVE = 3, /**< Exchanging data. */
+ DAC_COMPLETE = 4, /**< Asynchronous operation complete. */
+ DAC_ERROR = 5 /**< Error. */
+} dacstate_t;
+
+#include "hal_dac_lld.h"
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Low level driver helper macros
+ * @{
+ */
+#if (DAC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Waits for operation completion.
+ * @details This function waits for the driver to complete the current
+ * operation.
+ * @pre An operation must be running while the function is invoked.
+ * @note No more than one thread can wait on a DAC driver using
+ * this function.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+#define _dac_wait_s(dacp) osalThreadSuspendS(&(dacp)->thread)
+
+/**
+ * @brief Resumes a thread waiting for a conversion completion.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+#define _dac_reset_i(dacp) osalThreadResumeI(&(dacp)->thread, MSG_RESET)
+
+/**
+ * @brief Resumes a thread waiting for a conversion completion.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+#define _dac_reset_s(dacp) osalThreadResumeS(&(dacp)->thread, MSG_RESET)
+
+/**
+ * @brief Wakes up the waiting thread.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+#define _dac_wakeup_isr(dacp) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(dacp)->thread, MSG_OK); \
+ osalSysUnlockFromISR(); \
+}
+
+/**
+ * @brief Wakes up the waiting thread with a timeout message.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+#define _dac_timeout_isr(dacp) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(dacp)->thread, MSG_TIMEOUT); \
+ osalSysUnlockFromISR(); \
+}
+
+#else /* !DAC_USE_WAIT */
+#define _dac_wait_s(dacp)
+#define _dac_reset_i(dacp)
+#define _dac_reset_s(dacp)
+#define _dac_wakeup_isr(dacp)
+#define _dac_timeout_isr(dacp)
+#endif /* !DAC_USE_WAIT */
+
+/**
+ * @brief Common ISR code, half buffer event.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+#define _dac_isr_half_code(dacp) { \
+ if ((dacp)->grpp->end_cb != NULL) { \
+ (dacp)->grpp->end_cb(dacp, (dacp)->samples, (dacp)->depth / 2); \
+ } \
+}
+
+/**
+ * @brief Common ISR code, full buffer event.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+#define _dac_isr_full_code(dacp) { \
+ if ((dacp)->grpp->end_cb != NULL) { \
+ if ((dacp)->depth > 1) { \
+ /* Invokes the callback passing the 2nd half of the buffer.*/ \
+ size_t half = (dacp)->depth / 2; \
+ size_t half_index = half * (dacp)->grpp->num_channels; \
+ (dacp)->grpp->end_cb(dacp, (dacp)->samples + half_index, half); \
+ } \
+ else { \
+ /* Invokes the callback passing the whole buffer.*/ \
+ (dacp)->grpp->end_cb(dacp, (dacp)->samples, (dacp)->depth); \
+ } \
+ } \
+}
+
+/**
+ * @brief Common ISR code, error event.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread timeout signaling, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] err platform dependent error code
+ *
+ * @notapi
+ */
+#define _dac_isr_error_code(dacp, err) { \
+ dac_lld_stop_conversion(dacp); \
+ if ((dacp)->grpp->error_cb != NULL) { \
+ (dacp)->state = DAC_ERROR; \
+ (dacp)->grpp->error_cb(dacp, err); \
+ if ((dacp)->state == DAC_ERROR) \
+ (dacp)->state = DAC_READY; \
+ } \
+ (dacp)->grpp = NULL; \
+ _dac_timeout_isr(dacp); \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void dacInit(void);
+ void dacObjectInit(DACDriver *dacp);
+ void dacStart(DACDriver *dacp, const DACConfig *config);
+ void dacStop(DACDriver *dacp);
+ void dacPutChannelX(DACDriver *dacp,
+ dacchannel_t channel,
+ dacsample_t sample);
+ void dacStartConversion(DACDriver *dacp, const DACConversionGroup *grpp,
+ dacsample_t *samples, size_t depth);
+ void dacStartConversionI(DACDriver *dacp, const DACConversionGroup *grpp,
+ dacsample_t *samples, size_t depth);
+ void dacStopConversion(DACDriver *dacp);
+ void dacStopConversionI(DACDriver *dacp);
+#if DAC_USE_WAIT
+ msg_t dacConvert(DACDriver *dacp, const DACConversionGroup *grpp,
+ dacsample_t *samples, size_t depth);
+#endif
+#if DAC_USE_MUTUAL_EXCLUSION
+ void dacAcquireBus(DACDriver *dacp);
+ void dacReleaseBus(DACDriver *dacp);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_DAC == TRUE */
+
+#endif /* HAL_DAC_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/ext.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_ext.h
similarity index 67%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/ext.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_ext.h
index 8665a5f5d1..ec7ca6de52 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/ext.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_ext.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file ext.h
+ * @file hal_ext.h
* @brief EXT Driver macros and structures.
*
* @addtogroup EXT
* @{
*/
-#ifndef _EXT_H_
-#define _EXT_H_
+#ifndef HAL_EXT_H
+#define HAL_EXT_H
-#if HAL_USE_EXT || defined(__DOXYGEN__)
+#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -46,13 +35,14 @@
* @name EXT channel modes
* @{
*/
-#define EXT_CH_MODE_EDGES_MASK 3 /**< @brief Mask of edges field. */
-#define EXT_CH_MODE_DISABLED 0 /**< @brief Channel disabled. */
-#define EXT_CH_MODE_RISING_EDGE 1 /**< @brief Rising edge callback. */
-#define EXT_CH_MODE_FALLING_EDGE 2 /**< @brief Falling edge callback. */
-#define EXT_CH_MODE_BOTH_EDGES 3 /**< @brief Both edges callback. */
-
-#define EXT_CH_MODE_AUTOSTART 4 /**< @brief Channel started
+#define EXT_CH_MODE_EDGES_MASK 3U /**< @brief Mask of edges field. */
+#define EXT_CH_MODE_DISABLED 0U /**< @brief Channel disabled. */
+#define EXT_CH_MODE_RISING_EDGE 1U /**< @brief Rising edge callback. */
+#define EXT_CH_MODE_FALLING_EDGE 2U /**< @brief Falling edge callback. */
+#define EXT_CH_MODE_BOTH_EDGES 3U /**< @brief Both edges callback. */
+#define EXT_CH_MODE_LOW_LEVEL 5U /**< @brief low level callback. */
+
+#define EXT_CH_MODE_AUTOSTART 4U /**< @brief Channel started
automatically on driver start. */
/** @} */
@@ -74,7 +64,7 @@
typedef enum {
EXT_UNINIT = 0, /**< Not initialized. */
EXT_STOP = 1, /**< Stopped. */
- EXT_ACTIVE = 2, /**< Active. */
+ EXT_ACTIVE = 2 /**< Active. */
} extstate_t;
/**
@@ -82,7 +72,7 @@ typedef enum {
*/
typedef struct EXTDriver EXTDriver;
-#include "ext_lld.h"
+#include "hal_ext_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -127,9 +117,9 @@ typedef struct EXTDriver EXTDriver;
* @api
*/
#define extSetChannelMode(extp, channel, extcp) { \
- chSysLock(); \
+ osalSysLock(); \
extSetChannelModeI(extp, channel, extcp); \
- chSysUnlock(); \
+ osalSysUnlock(); \
}
/** @} */
@@ -154,8 +144,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_EXT */
+#endif /* HAL_USE_EXT == TRUE */
-#endif /* _EXT_H_ */
+#endif /* HAL_EXT_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_files.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_files.h
new file mode 100644
index 0000000000..2b80aff26f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_files.h
@@ -0,0 +1,238 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_files.h
+ * @brief Data files.
+ * @details This header defines abstract interfaces useful to access generic
+ * data files in a standardized way.
+ *
+ * @addtogroup HAL_FILES
+ * @details This module define an abstract interface for generic data files by
+ * extending the @p BaseSequentialStream interface. Note that no code
+ * is present, data files are just abstract interface-like structures,
+ * you should look at the systems as to a set of abstract C++ classes
+ * (even if written in C). This system has the advantage to make the
+ * access to streams independent from the implementation logic.
+ * The data files interface can be used as base class for high level
+ * object types such as an API for a File System implementation.
+ * @{
+ */
+
+#ifndef HAL_FILES_H
+#define HAL_FILES_H
+
+/**
+ * @name Files return codes
+ * @{
+ */
+/**
+ * @brief No error return code.
+ */
+#define FILE_OK STM_OK
+
+/**
+ * @brief Error code from the file stream methods.
+ */
+#define FILE_ERROR STM_TIMEOUT
+
+/**
+ * @brief End-of-file condition for file get/put methods.
+ */
+#define FILE_EOF STM_RESET
+/** @} */
+
+/**
+ * @brief File offset type.
+ */
+typedef uint32_t fileoffset_t;
+
+/**
+ * @brief FileStream specific methods.
+ */
+#define _file_stream_methods \
+ _base_sequential_stream_methods \
+ /* File close method.*/ \
+ msg_t (*close)(void *instance); \
+ /* Get last error code method.*/ \
+ msg_t (*geterror)(void *instance); \
+ /* File get size method.*/ \
+ msg_t (*getsize)(void *instance); \
+ /* File get current position method.*/ \
+ msg_t (*getposition)(void *instance); \
+ /* File seek method.*/ \
+ msg_t (*lseek)(void *instance, fileoffset_t offset);
+
+/**
+ * @brief @p FileStream specific data.
+ * @note It is empty because @p FileStream is only an interface
+ * without implementation.
+ */
+#define _file_stream_data \
+ _base_sequential_stream_data
+
+/**
+ * @extends BaseSequentialStreamVMT
+ *
+ * @brief @p FileStream virtual methods table.
+ */
+struct FileStreamVMT {
+ _file_stream_methods
+};
+
+/**
+ * @extends BaseSequentialStream
+ *
+ * @brief Base file stream class.
+ * @details This class represents a generic file data stream.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct FileStreamVMT *vmt;
+ _file_stream_data
+} FileStream;
+
+/**
+ * @name Macro Functions (FileStream)
+ * @{
+ */
+/**
+ * @brief File stream write.
+ * @details The function writes data from a buffer to a file stream.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ * @param[in] bp pointer to the data buffer
+ * @param[in] n the maximum amount of data to be transferred
+ * @return The number of bytes transferred. The return value can
+ * be less than the specified number of bytes if an
+ * end-of-file condition has been met.
+ * @retval FILE_ERROR operation failed.
+ *
+ * @api
+ */
+#define fileStreamWrite(ip, bp, n) streamWrite(ip, bp, n)
+
+/**
+ * @brief File stream read.
+ * @details The function reads data from a file stream into a buffer.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ * @param[out] bp pointer to the data buffer
+ * @param[in] n the maximum amount of data to be transferred
+ * @return The number of bytes transferred. The return value can
+ * be less than the specified number of bytes if an
+ * end-of-file condition has been met.
+ * @retval FILE_ERROR operation failed.
+ *
+ * @api
+ */
+#define fileStreamRead(ip, bp, n) streamRead(ip, bp, n)
+
+/**
+ * @brief File stream blocking byte write.
+ * @details This function writes a byte value to a channel. If the channel
+ * is not ready to accept data then the calling thread is suspended.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ * @param[in] b the byte value to be written to the channel
+ *
+ * @return The operation status.
+ * @retval FILE_OK if the operation succeeded.
+ * @retval FILE_ERROR operation failed.
+ * @retval FILE_EOF if an end-of-file condition has been met.
+ *
+ * @api
+ */
+#define fileStreamPut(ip, b) streamPut(ip, b)
+
+/**
+ * @brief File stream blocking byte read.
+ * @details This function reads a byte value from a channel. If the data
+ * is not available then the calling thread is suspended.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ *
+ * @return A byte value from the queue.
+ * @retval FILE_ERROR operation failed.
+ * @retval FILE_EOF if an end-of-file condition has been met.
+ *
+ * @api
+ */
+#define fileStreamGet(ip) streamGet(ip)
+
+/**
+ * @brief File Stream close.
+ * @details The function closes a file stream.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ * @return The operation status.
+ * @retval FILE_OK no error.
+ * @retval FILE_ERROR operation failed.
+ *
+ * @api
+ */
+#define fileStreamClose(ip) ((ip)->vmt->close(ip))
+
+/**
+ * @brief Returns an implementation dependent error code.
+ * @pre The previously called function must have returned @p FILE_ERROR.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ * @return Implementation dependent error code.
+ *
+ * @api
+ */
+#define fileStreamGetError(ip) ((ip)->vmt->geterror(ip))
+
+/**
+ * @brief Returns the current file size.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ * @return The file size.
+ * @retval FILE_ERROR operation failed.
+ *
+ * @api
+ */
+#define fileStreamGetSize(ip) ((ip)->vmt->getsize(ip))
+
+/**
+ * @brief Returns the current file pointer position.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ * @return The current position inside the file.
+ * @retval FILE_ERROR operation failed.
+ *
+ * @api
+ */
+#define fileStreamGetPosition(ip) ((ip)->vmt->getposition(ip))
+
+/**
+ * @brief Moves the file current pointer to an absolute position.
+ *
+ * @param[in] ip pointer to a @p FileStream or derived class
+ * @param[in] offset new absolute position
+ * @return The operation status.
+ * @retval FILE_OK no error.
+ * @retval FILE_ERROR operation failed.
+ *
+ * @api
+ */
+#define fileStreamSeek(ip, offset) ((ip)->vmt->lseek(ip, offset))
+/** @} */
+
+#endif /* HAL_FILES_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/gpt.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_gpt.h
similarity index 67%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/gpt.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_gpt.h
index e9ac3a5c2f..a89fb6f5cf 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/gpt.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_gpt.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file gpt.h
+ * @file hal_gpt.h
* @brief GPT Driver macros and structures.
*
* @addtogroup GPT
* @{
*/
-#ifndef _GPT_H_
-#define _GPT_H_
+#ifndef HAL_GPT_H
+#define HAL_GPT_H
-#if HAL_USE_GPT || defined(__DOXYGEN__)
+#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -77,7 +66,7 @@ typedef struct GPTDriver GPTDriver;
*/
typedef void (*gptcallback_t)(GPTDriver *gptp);
-#include "gpt_lld.h"
+#include "hal_gpt_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -86,9 +75,7 @@ typedef void (*gptcallback_t)(GPTDriver *gptp);
/**
* @brief Changes the interval of GPT peripheral.
* @details This function changes the interval of a running GPT unit.
- * @pre The GPT unit must have been activated using @p gptStart().
- * @pre The GPT unit must have been running in continuous mode using
- * @p gptStartContinuous().
+ * @pre The GPT unit must be running in continuous mode.
* @post The GPT unit interval is changed to the new value.
*
* @param[in] gptp pointer to a @p GPTDriver object
@@ -96,10 +83,34 @@ typedef void (*gptcallback_t)(GPTDriver *gptp);
*
* @iclass
*/
-#define gptChangeIntervalI(gptp, interval) { \
- gpt_lld_change_interval(gptp, interval); \
+#define gptChangeIntervalI(gptp, interval) { \
+ gpt_lld_change_interval(gptp, interval); \
}
+/**
+ * @brief Returns the interval of GPT peripheral.
+ * @pre The GPT unit must be running in continuous mode.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @return The current interval.
+ *
+ * @xclass
+ */
+#define gptGetIntervalX(gptp) gpt_lld_get_interval(gptp)
+
+/**
+ * @brief Returns the counter value of GPT peripheral.
+ * @pre The GPT unit must be running in continuous mode.
+ * @note The nature of the counter is not defined, it may count upward
+ * or downward, it could be continuously running or not.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @return The current counter value.
+ *
+ * @xclass
+ */
+#define gptGetCounterX(gptp) gpt_lld_get_counter(gptp)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
@@ -123,8 +134,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_GPT */
+#endif /* HAL_USE_GPT == TRUE */
-#endif /* _GPT_H_ */
+#endif /* HAL_GPT_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/i2c.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_i2c.h
similarity index 63%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/i2c.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_i2c.h
index 048b57ef71..98bf498a98 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/i2c.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_i2c.h
@@ -1,28 +1,17 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Uladzimir Pylinsky
@@ -30,35 +19,36 @@
*/
/**
- * @file i2c.h
+ * @file hal_i2c.h
* @brief I2C Driver macros and structures.
*
* @addtogroup I2C
* @{
*/
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef HAL_I2C_H
+#define HAL_I2C_H
-#if HAL_USE_I2C || defined(__DOXYGEN__)
+#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
+/* TODO: To be reviewed, too STM32-centric.*/
/**
* @name I2C bus error conditions
* @{
*/
-#define I2CD_NO_ERROR 0x00 /**< @brief No error. */
-#define I2CD_BUS_ERROR 0x01 /**< @brief Bus Error. */
-#define I2CD_ARBITRATION_LOST 0x02 /**< @brief Arbitration Lost. */
-#define I2CD_ACK_FAILURE 0x04 /**< @brief Acknowledge Failure. */
-#define I2CD_OVERRUN 0x08 /**< @brief Overrun/Underrun. */
-#define I2CD_PEC_ERROR 0x10 /**< @brief PEC Error in
+#define I2C_NO_ERROR 0x00 /**< @brief No error. */
+#define I2C_BUS_ERROR 0x01 /**< @brief Bus Error. */
+#define I2C_ARBITRATION_LOST 0x02 /**< @brief Arbitration Lost. */
+#define I2C_ACK_FAILURE 0x04 /**< @brief Acknowledge Failure. */
+#define I2C_OVERRUN 0x08 /**< @brief Overrun/Underrun. */
+#define I2C_PEC_ERROR 0x10 /**< @brief PEC Error in
reception. */
-#define I2CD_TIMEOUT 0x20 /**< @brief Hardware timeout. */
-#define I2CD_SMB_ALERT 0x40 /**< @brief SMBus Alert. */
+#define I2C_TIMEOUT 0x20 /**< @brief Hardware timeout. */
+#define I2C_SMB_ALERT 0x40 /**< @brief SMBus Alert. */
/** @} */
/*===========================================================================*/
@@ -76,10 +66,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -96,12 +82,38 @@ typedef enum {
I2C_LOCKED = 5 /**> Bus or driver locked. */
} i2cstate_t;
-#include "i2c_lld.h"
+#include "hal_i2c_lld.h"
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
+/**
+ * @brief Wakes up the waiting thread notifying no errors.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2c_wakeup_isr(i2cp) do { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(i2cp)->thread, MSG_OK); \
+ osalSysUnlockFromISR(); \
+} while(0)
+
+/**
+ * @brief Wakes up the waiting thread notifying errors.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2c_wakeup_error_isr(i2cp) do { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(i2cp)->thread, MSG_RESET); \
+ osalSysUnlockFromISR(); \
+} while(0)
+
/**
* @brief Wrap i2cMasterTransmitTimeout function with TIME_INFINITE timeout.
* @api
@@ -138,17 +150,17 @@ extern "C" {
i2caddr_t addr,
uint8_t *rxbuf, size_t rxbytes,
systime_t timeout);
-#if I2C_USE_MUTUAL_EXCLUSION
+#if I2C_USE_MUTUAL_EXCLUSION == TRUE
void i2cAcquireBus(I2CDriver *i2cp);
void i2cReleaseBus(I2CDriver *i2cp);
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#endif
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_I2C */
+#endif /* HAL_USE_I2C == TRUE */
-#endif /* _I2C_H_ */
+#endif /* HAL_I2C_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_i2s.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_i2s.h
new file mode 100644
index 0000000000..50324228de
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_i2s.h
@@ -0,0 +1,167 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_i2s.h
+ * @brief I2S Driver macros and structures.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#ifndef HAL_I2S_H
+#define HAL_I2S_H
+
+#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name I2S modes
+ * @{
+ */
+#define I2S_MODE_SLAVE 0
+#define I2S_MODE_MASTER 1
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ I2S_UNINIT = 0, /**< Not initialized. */
+ I2S_STOP = 1, /**< Stopped. */
+ I2S_READY = 2, /**< Ready. */
+ I2S_ACTIVE = 3, /**< Active. */
+ I2S_COMPLETE = 4 /**< Transmission complete. */
+} i2sstate_t;
+
+#include "hal_i2s_lld.h"
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Starts a I2S data exchange.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @iclass
+ */
+#define i2sStartExchangeI(i2sp) { \
+ i2s_lld_start_exchange(i2sp); \
+ (i2sp)->state = I2S_ACTIVE; \
+}
+
+/**
+ * @brief Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ * was not active the function does nothing.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @iclass
+ */
+#define i2sStopExchangeI(i2sp) { \
+ i2s_lld_stop_exchange(i2sp); \
+ (i2sp)->state = I2S_READY; \
+}
+
+/**
+ * @brief Common ISR code, half buffer event.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] i2sp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2s_isr_half_code(i2sp) { \
+ if ((i2sp)->config->end_cb != NULL) { \
+ (i2sp)->config->end_cb(i2sp, 0, (i2sp)->config->size / 2); \
+ } \
+}
+
+/**
+ * @brief Common ISR code.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] i2sp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2s_isr_full_code(i2sp) { \
+ if ((i2sp)->config->end_cb) { \
+ (i2sp)->state = I2S_COMPLETE; \
+ (i2sp)->config->end_cb(i2sp, \
+ (i2sp)->config->size / 2, \
+ (i2sp)->config->size / 2); \
+ if ((i2sp)->state == I2S_COMPLETE) \
+ (i2sp)->state = I2S_READY; \
+ } \
+ else \
+ (i2sp)->state = I2S_READY; \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2sInit(void);
+ void i2sObjectInit(I2SDriver *i2sp);
+ void i2sStart(I2SDriver *i2sp, const I2SConfig *config);
+ void i2sStop(I2SDriver *i2sp);
+ void i2sStartExchange(I2SDriver *i2sp);
+ void i2sStopExchange(I2SDriver *i2sp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2S == TRUE */
+
+#endif /* HAL_I2S_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/icu.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_icu.h
similarity index 52%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/icu.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_icu.h
index f759648cdd..7967c9efe7 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/icu.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_icu.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file icu.h
+ * @file hal_icu.h
* @brief ICU Driver macros and structures.
*
* @addtogroup ICU
* @{
*/
-#ifndef _ICU_H_
-#define _ICU_H_
+#ifndef HAL_ICU_H
+#define HAL_ICU_H
-#if HAL_USE_ICU || defined(__DOXYGEN__)
+#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -61,9 +50,8 @@ typedef enum {
ICU_UNINIT = 0, /**< Not initialized. */
ICU_STOP = 1, /**< Stopped. */
ICU_READY = 2, /**< Ready. */
- ICU_WAITING = 3, /**< Waiting first edge. */
- ICU_ACTIVE = 4, /**< Active cycle phase. */
- ICU_IDLE = 5, /**< Idle cycle phase. */
+ ICU_WAITING = 3, /**< Waiting for first front. */
+ ICU_ACTIVE = 4 /**< First front detected. */
} icustate_t;
/**
@@ -78,7 +66,7 @@ typedef struct ICUDriver ICUDriver;
*/
typedef void (*icucallback_t)(ICUDriver *icup);
-#include "icu_lld.h"
+#include "hal_icu_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -89,54 +77,95 @@ typedef void (*icucallback_t)(ICUDriver *icup);
* @{
*/
/**
- * @brief Enables the input capture.
+ * @brief Starts the input capture.
*
* @param[in] icup pointer to the @p ICUDriver object
*
* @iclass
*/
-#define icuEnableI(icup) icu_lld_enable(icup)
+#define icuStartCaptureI(icup) do { \
+ icu_lld_start_capture(icup); \
+ (icup)->state = ICU_WAITING; \
+} while (false)
/**
- * @brief Disables the input capture.
+ * @brief Stops the input capture.
*
* @param[in] icup pointer to the @p ICUDriver object
*
* @iclass
*/
-#define icuDisableI(icup) icu_lld_disable(icup)
+#define icuStopCaptureI(icup) do { \
+ icu_lld_stop_capture(icup); \
+ (icup)->state = ICU_READY; \
+} while (false)
+
+/**
+ * @brief Enables notifications.
+ * @pre The ICU unit must have been activated using @p icuStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @iclass
+ */
+#define icuEnableNotificationsI(icup) icu_lld_enable_notifications(icup)
+
+/**
+ * @brief Disables notifications.
+ * @pre The ICU unit must have been activated using @p icuStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @iclass
+ */
+#define icuDisableNotificationsI(icup) icu_lld_disable_notifications(icup)
+
+/**
+ * @brief Check on notifications status.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The notifications status.
+ * @retval false if notifications are not enabled.
+ * @retval true if notifications are enabled.
+ *
+ * @notapi
+ */
+#define icuAreNotificationsEnabledX(icup) \
+ icu_lld_are_notifications_enabled(icup)
/**
* @brief Returns the width of the latest pulse.
* @details The pulse width is defined as number of ticks between the start
* edge and the stop edge.
* @note This function is meant to be invoked from the width capture
- * callback only.
+ * callback.
*
* @param[in] icup pointer to the @p ICUDriver object
* @return The number of ticks.
*
- * @special
+ * @xclass
*/
-#define icuGetWidth(icup) icu_lld_get_width(icup)
+#define icuGetWidthX(icup) icu_lld_get_width(icup)
/**
* @brief Returns the width of the latest cycle.
* @details The cycle width is defined as number of ticks between a start
* edge and the next start edge.
* @note This function is meant to be invoked from the width capture
- * callback only.
+ * callback.
*
* @param[in] icup pointer to the @p ICUDriver object
* @return The number of ticks.
*
- * @special
+ * @xclass
*/
-#define icuGetPeriod(icup) icu_lld_get_period(icup)
+#define icuGetPeriodX(icup) icu_lld_get_period(icup)
/** @} */
/**
- * @name Low Level driver helper macros
+ * @name Low level driver helper macros
* @{
*/
/**
@@ -146,37 +175,40 @@ typedef void (*icucallback_t)(ICUDriver *icup);
*
* @notapi
*/
-#define _icu_isr_invoke_width_cb(icup) { \
- if ((icup)->state != ICU_WAITING) { \
- (icup)->state = ICU_IDLE; \
+#define _icu_isr_invoke_width_cb(icup) do { \
+ if (((icup)->state == ICU_ACTIVE) && \
+ ((icup)->config->width_cb != NULL)) \
(icup)->config->width_cb(icup); \
- } \
-}
+} while (0)
/**
* @brief Common ISR code, ICU period event.
+ * @note A period event brings the driver into the @p ICU_ACTIVE state.
*
* @param[in] icup pointer to the @p ICUDriver object
*
* @notapi
*/
-#define _icu_isr_invoke_period_cb(icup) { \
- icustate_t previous_state = (icup)->state; \
- (icup)->state = ICU_ACTIVE; \
- if (previous_state != ICU_WAITING) \
+#define _icu_isr_invoke_period_cb(icup) do { \
+ if (((icup)->state == ICU_ACTIVE) && \
+ ((icup)->config->period_cb != NULL)) \
(icup)->config->period_cb(icup); \
-}
+ (icup)->state = ICU_ACTIVE; \
+} while (0)
/**
* @brief Common ISR code, ICU timer overflow event.
+ * @note An overflow always brings the driver back to the @p ICU_WAITING
+ * state.
*
* @param[in] icup pointer to the @p ICUDriver object
*
* @notapi
*/
-#define _icu_isr_invoke_overflow_cb(icup) { \
+#define _icu_isr_invoke_overflow_cb(icup) do { \
(icup)->config->overflow_cb(icup); \
-}
+ (icup)->state = ICU_WAITING; \
+} while (0)
/** @} */
/*===========================================================================*/
@@ -190,14 +222,17 @@ extern "C" {
void icuObjectInit(ICUDriver *icup);
void icuStart(ICUDriver *icup, const ICUConfig *config);
void icuStop(ICUDriver *icup);
- void icuEnable(ICUDriver *icup);
- void icuDisable(ICUDriver *icup);
+ void icuStartCapture(ICUDriver *icup);
+ bool icuWaitCapture(ICUDriver *icup);
+ void icuStopCapture(ICUDriver *icup);
+ void icuEnableNotifications(ICUDriver *icup);
+ void icuDisableNotifications(ICUDriver *icup);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_ICU */
+#endif /* HAL_USE_ICU == TRUE */
-#endif /* _ICU_H_ */
+#endif /* HAL_ICU_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/io_block.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_ioblock.h
similarity index 76%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/io_block.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_ioblock.h
index 70da543b41..4bc022c1f4 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/io_block.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_ioblock.h
@@ -1,32 +1,21 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file io_block.h
+ * @file hal_ioblock.h
* @brief I/O block devices access.
* @details This header defines an abstract interface useful to access generic
* I/O block devices in a standardized way.
@@ -42,8 +31,8 @@
* @{
*/
-#ifndef _IO_BLOCK_H_
-#define _IO_BLOCK_H_
+#ifndef HAL_IOBLOCK_H
+#define HAL_IOBLOCK_H
/**
* @brief Driver state machine possible states.
@@ -73,23 +62,23 @@ typedef struct {
*/
#define _base_block_device_methods \
/* Removable media detection.*/ \
- bool_t (*is_inserted)(void *instance); \
+ bool (*is_inserted)(void *instance); \
/* Removable write protection detection.*/ \
- bool_t (*is_protected)(void *instance); \
+ bool (*is_protected)(void *instance); \
/* Connection to the block device.*/ \
- bool_t (*connect)(void *instance); \
+ bool (*connect)(void *instance); \
/* Disconnection from the block device.*/ \
- bool_t (*disconnect)(void *instance); \
+ bool (*disconnect)(void *instance); \
/* Reads one or more blocks.*/ \
- bool_t (*read)(void *instance, uint32_t startblk, \
+ bool (*read)(void *instance, uint32_t startblk, \
uint8_t *buffer, uint32_t n); \
/* Writes one or more blocks.*/ \
- bool_t (*write)(void *instance, uint32_t startblk, \
+ bool (*write)(void *instance, uint32_t startblk, \
const uint8_t *buffer, uint32_t n); \
/* Write operations synchronization.*/ \
- bool_t (*sync)(void *instance); \
+ bool (*sync)(void *instance); \
/* Obtains info about the media.*/ \
- bool_t (*get_info)(void *instance, BlockDeviceInfo *bdip);
+ bool (*get_info)(void *instance, BlockDeviceInfo *bdip);
/**
* @brief @p BaseBlockDevice specific data.
@@ -187,8 +176,8 @@ typedef struct {
* @param[in] ip pointer to a @p BaseBlockDevice or derived class
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @api
*/
@@ -201,8 +190,8 @@ typedef struct {
* @param[in] ip pointer to a @p BaseBlockDevice or derived class
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @api
*/
@@ -217,8 +206,8 @@ typedef struct {
* @param[in] n number of blocks to read
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @api
*/
@@ -234,8 +223,8 @@ typedef struct {
* @param[in] n number of blocks to write
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @api
*/
@@ -248,8 +237,8 @@ typedef struct {
* @param[in] ip pointer to a @p BaseBlockDevice or derived class
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @api
*/
@@ -262,8 +251,8 @@ typedef struct {
* @param[out] bdip pointer to a @p BlockDeviceInfo structure
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @api
*/
@@ -271,6 +260,6 @@ typedef struct {
/** @} */
-#endif /* _IO_BLOCK_H_ */
+#endif /* HAL_IOBLOCK_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mac.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mac.h
similarity index 78%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mac.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mac.h
index 590e880d61..0798bb5dee 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mac.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mac.h
@@ -1,41 +1,30 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file mac.h
+ * @file hal_mac.h
* @brief MAC Driver macros and structures.
* @addtogroup MAC
* @{
*/
-#ifndef _MAC_H_
-#define _MAC_H_
+#ifndef HAL_MAC_H
+#define HAL_MAC_H
-#if HAL_USE_MAC || defined(__DOXYGEN__)
+#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -68,14 +57,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS
-#error "the MAC driver requires CH_USE_SEMAPHORES"
-#endif
-
-#if MAC_USE_EVENTS && !CH_USE_EVENTS
-#error "the MAC driver requires CH_USE_EVENTS"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -94,7 +75,7 @@ typedef enum {
*/
typedef struct MACDriver MACDriver;
-#include "mac_lld.h"
+#include "hal_mac_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -112,7 +93,7 @@ typedef struct MACDriver MACDriver;
*
* @api
*/
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
+#if (MAC_USE_EVENTS == TRUE) || defined(__DOXYGEN__)
#define macGetReceiveEventSource(macp) (&(macp)->rdevent)
#endif
@@ -147,7 +128,7 @@ typedef struct MACDriver MACDriver;
#define macReadReceiveDescriptor(rdp, buf, size) \
mac_lld_read_receive_descriptor(rdp, buf, size)
-#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
+#if (MAC_USE_ZERO_COPY == TRUE) || defined(__DOXYGEN__)
/**
* @brief Returns a pointer to the next transmit buffer in the descriptor
* chain.
@@ -203,19 +184,19 @@ extern "C" {
void macSetAddress(MACDriver *macp, const uint8_t *p);
msg_t macWaitTransmitDescriptor(MACDriver *macp,
MACTransmitDescriptor *tdp,
- systime_t time);
+ systime_t timeout);
void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp);
msg_t macWaitReceiveDescriptor(MACDriver *macp,
MACReceiveDescriptor *rdp,
- systime_t time);
+ systime_t timeout);
void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp);
- bool_t macPollLinkStatus(MACDriver *macp);
+ bool macPollLinkStatus(MACDriver *macp);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_MAC */
+#endif /* HAL_USE_MAC == TRUE */
-#endif /* _MAC_H_ */
+#endif /* HAL_MAC_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mii.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mii.h
similarity index 78%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mii.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mii.h
index 7eb26c0e10..2cfee661c2 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mii.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mii.h
@@ -1,44 +1,33 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
-/*-*
- * @file mii.h
- * @brief MII Driver macros and structures.
+/**
+ * @file hal_mii.h
+ * @brief MII macros and structures.
*
* @addtogroup MII
* @{
*/
-#ifndef _MII_H_
-#define _MII_H_
+#ifndef MII_H
+#define MII_H
-/*
- * Generic MII registers. Note, not all registers are present on all PHY
- * devices and some extra registers may be present.
+/**
+ * @name Generic MII registers
+ * @{
*/
#define MII_BMCR 0x00 /**< Basic mode control register. */
#define MII_BMSR 0x01 /**< Basic mode status register. */
@@ -64,9 +53,11 @@
#define MII_RESV2 0x1a /**< Reserved. */
#define MII_TPISTATUS 0x1b /**< TPI status for 10Mbps. */
#define MII_NCONFIG 0x1c /**< Network interface config. */
+/** @} */
-/*
- * Basic mode control register.
+/**
+ * @name Basic mode control register
+ * @{
*/
#define BMCR_RESV 0x007f /**< Unused. */
#define BMCR_CTST 0x0080 /**< Collision test. */
@@ -78,9 +69,11 @@
#define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */
#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bit. */
#define BMCR_RESET 0x8000 /**< Reset. */
+/** @} */
-/*
- * Basic mode status register.
+/**
+ * @name Basic mode status register
+ * @{
*/
#define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */
#define BMSR_JCD 0x0002 /**< Jabber detected. */
@@ -95,9 +88,11 @@
#define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */
#define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */
#define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */
+/** @} */
-/*
- * Advertisement control register.
+/**
+ * @name Advertisement control register
+ * @{
*/
#define ADVERTISE_SLCT 0x001f /**< Selector bits. */
#define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */
@@ -117,9 +112,11 @@
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
+/** @} */
-/*
- * Link partner ability register.
+/**
+ * @name Link partner ability register
+ * @{
*/
#define LPA_SLCT 0x001f /**< Same as advertise selector. */
#define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */
@@ -136,9 +133,11 @@
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+/** @} */
-/*
- * Expansion register for auto-negotiation.
+/**
+ * @name Expansion register for auto-negotiation
+ * @{
*/
#define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */
#define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */
@@ -146,24 +145,31 @@
#define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */
#define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */
#define EXPANSION_RESV 0xffe0 /**< Unused. */
+/** @} */
-/*
- * N-way test register.
+/**
+ * @name N-way test register
+ * @{
*/
#define NWAYTEST_RESV1 0x00ff /**< Unused. */
#define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */
#define NWAYTEST_RESV2 0xfe00 /**< Unused. */
+/** @} */
-/*
- * PHY identifiers.
+/**
+ * @name PHY identifiers
+ * @{
*/
-#define MII_DM9161_ID 0x0181b8a0
-#define MII_AM79C875_ID 0x00225540
-#define MII_KS8721_ID 0x00221610
-#define MII_STE101P_ID 0x00061C50
-#define MII_DP83848I_ID 0x20005C90
-#define MII_LAN8710A_ID 0x0007C0F1
-
-#endif /* _MII_H_ */
+#define MII_DM9161_ID 0x0181b8a0
+#define MII_AM79C875_ID 0x00225540
+#define MII_KS8721_ID 0x00221610
+#define MII_STE101P_ID 0x00061C50
+#define MII_DP83848I_ID 0x20005C90
+#define MII_LAN8710A_ID 0x0007C0F1
+#define MII_LAN8720_ID 0x0007C0F0
+#define MII_LAN8742A_ID 0x0007C130
+/** @} */
+
+#endif /* MII_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mmc_spi.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mmc_spi.h
similarity index 66%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mmc_spi.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mmc_spi.h
index 9c976a87ad..c0a275e880 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mmc_spi.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mmc_spi.h
@@ -1,51 +1,40 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file mmc_spi.h
+ * @file hal_mmc_spi.h
* @brief MMC over SPI driver header.
*
* @addtogroup MMC_SPI
* @{
*/
-#ifndef _MMC_SPI_H_
-#define _MMC_SPI_H_
+#ifndef HAL_MMC_SPI_H
+#define HAL_MMC_SPI_H
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+#if (HAL_USE_MMC_SPI == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
-#define MMC_CMD0_RETRY 10
-#define MMC_CMD1_RETRY 100
-#define MMC_ACMD41_RETRY 100
-#define MMC_WAIT_DATA 10000
+#define MMC_CMD0_RETRY 10U
+#define MMC_CMD1_RETRY 100U
+#define MMC_ACMD41_RETRY 100U
+#define MMC_WAIT_DATA 10000U
/*===========================================================================*/
/* Driver pre-compile time settings. */
@@ -72,7 +61,7 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if !HAL_USE_SPI || !SPI_USE_WAIT
+#if (HAL_USE_SPI == FALSE) || (SPI_USE_WAIT == FALSE)
#error "MMC_SPI driver requires HAL_USE_SPI and SPI_USE_WAIT"
#endif
@@ -131,7 +120,7 @@ typedef struct {
/***
* @brief Addresses use blocks instead of bytes.
*/
- bool_t block_addresses;
+ bool block_addresses;
} MMCDriver;
/*===========================================================================*/
@@ -182,25 +171,25 @@ extern "C" {
void mmcObjectInit(MMCDriver *mmcp);
void mmcStart(MMCDriver *mmcp, const MMCConfig *config);
void mmcStop(MMCDriver *mmcp);
- bool_t mmcConnect(MMCDriver *mmcp);
- bool_t mmcDisconnect(MMCDriver *mmcp);
- bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk);
- bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer);
- bool_t mmcStopSequentialRead(MMCDriver *mmcp);
- bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk);
- bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer);
- bool_t mmcStopSequentialWrite(MMCDriver *mmcp);
- bool_t mmcSync(MMCDriver *mmcp);
- bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip);
- bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk);
- bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp);
- bool_t mmc_lld_is_write_protected(MMCDriver *mmcp);
+ bool mmcConnect(MMCDriver *mmcp);
+ bool mmcDisconnect(MMCDriver *mmcp);
+ bool mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk);
+ bool mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer);
+ bool mmcStopSequentialRead(MMCDriver *mmcp);
+ bool mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk);
+ bool mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer);
+ bool mmcStopSequentialWrite(MMCDriver *mmcp);
+ bool mmcSync(MMCDriver *mmcp);
+ bool mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip);
+ bool mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk);
+ bool mmc_lld_is_card_inserted(MMCDriver *mmcp);
+ bool mmc_lld_is_write_protected(MMCDriver *mmcp);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_MMC_SPI */
+#endif /* HAL_USE_MMC_SPI == TRUE */
-#endif /* _MMC_SPI_H_ */
+#endif /* HAL_MMC_SPI_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mmcsd.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mmcsd.h
new file mode 100644
index 0000000000..26c0920053
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_mmcsd.h
@@ -0,0 +1,498 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_mmcsd.h
+ * @brief MMC/SD cards common header.
+ * @details This header defines an abstract interface useful to access MMC/SD
+ * I/O block devices in a standardized way.
+ *
+ * @addtogroup MMCSD
+ * @{
+ */
+
+#ifndef HAL_MMCSD_H
+#define HAL_MMCSD_H
+
+#if (HAL_USE_MMC_SPI == TRUE) || (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Fixed block size for MMC/SD block devices.
+ */
+#define MMCSD_BLOCK_SIZE 512U
+
+/**
+ * @brief Mask of error bits in R1 responses.
+ */
+#define MMCSD_R1_ERROR_MASK 0xFDFFE008U
+
+/**
+ * @brief Fixed pattern for CMD8.
+ */
+#define MMCSD_CMD8_PATTERN 0x000001AAU
+
+/**
+ * @name SD/MMC status conditions
+ * @{
+ */
+#define MMCSD_STS_IDLE 0U
+#define MMCSD_STS_READY 1U
+#define MMCSD_STS_IDENT 2U
+#define MMCSD_STS_STBY 3U
+#define MMCSD_STS_TRAN 4U
+#define MMCSD_STS_DATA 5U
+#define MMCSD_STS_RCV 6U
+#define MMCSD_STS_PRG 7U
+#define MMCSD_STS_DIS 8U
+/** @} */
+
+/**
+ * @name SD/MMC commands
+ * @{
+ */
+#define MMCSD_CMD_GO_IDLE_STATE 0U
+#define MMCSD_CMD_INIT 1U
+#define MMCSD_CMD_ALL_SEND_CID 2U
+#define MMCSD_CMD_SEND_RELATIVE_ADDR 3U
+#define MMCSD_CMD_SET_BUS_WIDTH 6U
+#define MMCSD_CMD_SWITCH MMCSD_CMD_SET_BUS_WIDTH
+#define MMCSD_CMD_SEL_DESEL_CARD 7U
+#define MMCSD_CMD_SEND_IF_COND 8U
+#define MMCSD_CMD_SEND_EXT_CSD MMCSD_CMD_SEND_IF_COND
+#define MMCSD_CMD_SEND_CSD 9U
+#define MMCSD_CMD_SEND_CID 10U
+#define MMCSD_CMD_STOP_TRANSMISSION 12U
+#define MMCSD_CMD_SEND_STATUS 13U
+#define MMCSD_CMD_SET_BLOCKLEN 16U
+#define MMCSD_CMD_READ_SINGLE_BLOCK 17U
+#define MMCSD_CMD_READ_MULTIPLE_BLOCK 18U
+#define MMCSD_CMD_SET_BLOCK_COUNT 23U
+#define MMCSD_CMD_WRITE_BLOCK 24U
+#define MMCSD_CMD_WRITE_MULTIPLE_BLOCK 25U
+#define MMCSD_CMD_ERASE_RW_BLK_START 32U
+#define MMCSD_CMD_ERASE_RW_BLK_END 33U
+#define MMCSD_CMD_ERASE 38U
+#define MMCSD_CMD_APP_OP_COND 41U
+#define MMCSD_CMD_LOCK_UNLOCK 42U
+#define MMCSD_CMD_APP_CMD 55U
+#define MMCSD_CMD_READ_OCR 58U
+/** @} */
+
+/**
+ * @name CSD record offsets
+ */
+/**
+ * @brief Slice position of values in CSD register.
+ */
+/* CSD for MMC */
+#define MMCSD_CSD_MMC_CSD_STRUCTURE_SLICE 127U,126U
+#define MMCSD_CSD_MMC_SPEC_VERS_SLICE 125U,122U
+#define MMCSD_CSD_MMC_TAAC_SLICE 119U,112U
+#define MMCSD_CSD_MMC_NSAC_SLICE 111U,104U
+#define MMCSD_CSD_MMC_TRAN_SPEED_SLICE 103U,96U
+#define MMCSD_CSD_MMC_CCC_SLICE 95U,84U
+#define MMCSD_CSD_MMC_READ_BL_LEN_SLICE 83U,80U
+#define MMCSD_CSD_MMC_READ_BL_PARTIAL_SLICE 79U,79U
+#define MMCSD_CSD_MMC_WRITE_BLK_MISALIGN_SLICE 78U,78U
+#define MMCSD_CSD_MMC_READ_BLK_MISALIGN_SLICE 77U,77U
+#define MMCSD_CSD_MMC_DSR_IMP_SLICE 76U,76U
+#define MMCSD_CSD_MMC_C_SIZE_SLICE 73U,62U
+#define MMCSD_CSD_MMC_VDD_R_CURR_MIN_SLICE 61U,59U
+#define MMCSD_CSD_MMC_VDD_R_CURR_MAX_SLICE 58U,56U
+#define MMCSD_CSD_MMC_VDD_W_CURR_MIN_SLICE 55U,53U
+#define MMCSD_CSD_MMC_VDD_W_CURR_MAX_SLICE 52U,50U
+#define MMCSD_CSD_MMC_C_SIZE_MULT_SLICE 49U,47U
+#define MMCSD_CSD_MMC_ERASE_GRP_SIZE_SLICE 46U,42U
+#define MMCSD_CSD_MMC_ERASE_GRP_MULT_SLICE 41U,37U
+#define MMCSD_CSD_MMC_WP_GRP_SIZE_SLICE 36U,32U
+#define MMCSD_CSD_MMC_WP_GRP_ENABLE_SLICE 31U,31U
+#define MMCSD_CSD_MMC_DEFAULT_ECC_SLICE 30U,29U
+#define MMCSD_CSD_MMC_R2W_FACTOR_SLICE 28U,26U
+#define MMCSD_CSD_MMC_WRITE_BL_LEN_SLICE 25U,22U
+#define MMCSD_CSD_MMC_WRITE_BL_PARTIAL_SLICE 21U,21U
+#define MMCSD_CSD_MMC_CONTENT_PROT_APP_SLICE 16U,16U
+#define MMCSD_CSD_MMC_FILE_FORMAT_GRP_SLICE 15U,15U
+#define MMCSD_CSD_MMC_COPY_SLICE 14U,14U
+#define MMCSD_CSD_MMC_PERM_WRITE_PROTECT_SLICE 13U,13U
+#define MMCSD_CSD_MMC_TMP_WRITE_PROTECT_SLICE 12U,12U
+#define MMCSD_CSD_MMC_FILE_FORMAT_SLICE 11U,10U
+#define MMCSD_CSD_MMC_ECC_SLICE 9U,8U
+#define MMCSD_CSD_MMC_CRC_SLICE 7U,1U
+
+/* CSD version 2.0 */
+#define MMCSD_CSD_20_CRC_SLICE 7U,1U
+#define MMCSD_CSD_20_FILE_FORMAT_SLICE 11U,10U
+#define MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE 12U,12U
+#define MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE 13U,13U
+#define MMCSD_CSD_20_COPY_SLICE 14U,14U
+#define MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE 15U,15U
+#define MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE 21U,21U
+#define MMCSD_CSD_20_WRITE_BL_LEN_SLICE 25U,12U
+#define MMCSD_CSD_20_R2W_FACTOR_SLICE 28U,26U
+#define MMCSD_CSD_20_WP_GRP_ENABLE_SLICE 31U,31U
+#define MMCSD_CSD_20_WP_GRP_SIZE_SLICE 38U,32U
+#define MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE 45U,39U
+#define MMCSD_CSD_20_ERASE_BLK_EN_SLICE 46U,46U
+#define MMCSD_CSD_20_C_SIZE_SLICE 69U,48U
+#define MMCSD_CSD_20_DSR_IMP_SLICE 76U,76U
+#define MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE 77U,77U
+#define MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE 78U,78U
+#define MMCSD_CSD_20_READ_BL_PARTIAL_SLICE 79U,79U
+#define MMCSD_CSD_20_READ_BL_LEN_SLICE 83U,80U
+#define MMCSD_CSD_20_CCC_SLICE 95U,84U
+#define MMCSD_CSD_20_TRANS_SPEED_SLICE 103U,96U
+#define MMCSD_CSD_20_NSAC_SLICE 111U,104U
+#define MMCSD_CSD_20_TAAC_SLICE 119U,112U
+#define MMCSD_CSD_20_CSD_STRUCTURE_SLICE 127U,126U
+
+/* CSD version 1.0 */
+#define MMCSD_CSD_10_CRC_SLICE MMCSD_CSD_20_CRC_SLICE
+#define MMCSD_CSD_10_FILE_FORMAT_SLICE MMCSD_CSD_20_FILE_FORMAT_SLICE
+#define MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE
+#define MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE
+#define MMCSD_CSD_10_COPY_SLICE MMCSD_CSD_20_COPY_SLICE
+#define MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE
+#define MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE
+#define MMCSD_CSD_10_WRITE_BL_LEN_SLICE MMCSD_CSD_20_WRITE_BL_LEN_SLICE
+#define MMCSD_CSD_10_R2W_FACTOR_SLICE MMCSD_CSD_20_R2W_FACTOR_SLICE
+#define MMCSD_CSD_10_WP_GRP_ENABLE_SLICE MMCSD_CSD_20_WP_GRP_ENABLE_SLICE
+#define MMCSD_CSD_10_WP_GRP_SIZE_SLICE MMCSD_CSD_20_WP_GRP_SIZE_SLICE
+#define MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE
+#define MMCSD_CSD_10_ERASE_BLK_EN_SLICE MMCSD_CSD_20_ERASE_BLK_EN_SLICE
+#define MMCSD_CSD_10_C_SIZE_MULT_SLICE 49U,47U
+#define MMCSD_CSD_10_VDD_W_CURR_MAX_SLICE 52U,50U
+#define MMCSD_CSD_10_VDD_W_CURR_MIN_SLICE 55U,53U
+#define MMCSD_CSD_10_VDD_R_CURR_MAX_SLICE 58U,56U
+#define MMCSD_CSD_10_VDD_R_CURR_MIX_SLICE 61U,59U
+#define MMCSD_CSD_10_C_SIZE_SLICE 73U,62U
+#define MMCSD_CSD_10_DSR_IMP_SLICE MMCSD_CSD_20_DSR_IMP_SLICE
+#define MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE
+#define MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE
+#define MMCSD_CSD_10_READ_BL_PARTIAL_SLICE MMCSD_CSD_20_READ_BL_PARTIAL_SLICE
+#define MMCSD_CSD_10_READ_BL_LEN_SLICE 83U,80U
+#define MMCSD_CSD_10_CCC_SLICE MMCSD_CSD_20_CCC_SLICE
+#define MMCSD_CSD_10_TRANS_SPEED_SLICE MMCSD_CSD_20_TRANS_SPEED_SLICE
+#define MMCSD_CSD_10_NSAC_SLICE MMCSD_CSD_20_NSAC_SLICE
+#define MMCSD_CSD_10_TAAC_SLICE MMCSD_CSD_20_TAAC_SLICE
+#define MMCSD_CSD_10_CSD_STRUCTURE_SLICE MMCSD_CSD_20_CSD_STRUCTURE_SLICE
+/** @} */
+
+/**
+ * @name CID record offsets
+ */
+/**
+ * @brief Slice position of values in CID register.
+ */
+/* CID for SDC */
+#define MMCSD_CID_SDC_CRC_SLICE 7U,1U
+#define MMCSD_CID_SDC_MDT_M_SLICE 11U,8U
+#define MMCSD_CID_SDC_MDT_Y_SLICE 19U,12U
+#define MMCSD_CID_SDC_PSN_SLICE 55U,24U
+#define MMCSD_CID_SDC_PRV_M_SLICE 59U,56U
+#define MMCSD_CID_SDC_PRV_N_SLICE 63U,60U
+#define MMCSD_CID_SDC_PNM0_SLICE 71U,64U
+#define MMCSD_CID_SDC_PNM1_SLICE 79U,72U
+#define MMCSD_CID_SDC_PNM2_SLICE 87U,80U
+#define MMCSD_CID_SDC_PNM3_SLICE 95U,88U
+#define MMCSD_CID_SDC_PNM4_SLICE 103U,96U
+#define MMCSD_CID_SDC_OID_SLICE 119U,104U
+#define MMCSD_CID_SDC_MID_SLICE 127U,120U
+
+/* CID for MMC */
+#define MMCSD_CID_MMC_CRC_SLICE 7U,1U
+#define MMCSD_CID_MMC_MDT_Y_SLICE 11U,8U
+#define MMCSD_CID_MMC_MDT_M_SLICE 15U,12U
+#define MMCSD_CID_MMC_PSN_SLICE 47U,16U
+#define MMCSD_CID_MMC_PRV_M_SLICE 51U,48U
+#define MMCSD_CID_MMC_PRV_N_SLICE 55U,52U
+#define MMCSD_CID_MMC_PNM0_SLICE 63U,56U
+#define MMCSD_CID_MMC_PNM1_SLICE 71U,64U
+#define MMCSD_CID_MMC_PNM2_SLICE 79U,72U
+#define MMCSD_CID_MMC_PNM3_SLICE 87U,80U
+#define MMCSD_CID_MMC_PNM4_SLICE 95U,88U
+#define MMCSD_CID_MMC_PNM5_SLICE 103U,96U
+#define MMCSD_CID_MMC_OID_SLICE 119U,104U
+#define MMCSD_CID_MMC_MID_SLICE 127U,120U
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief @p MMCSDBlockDevice specific methods.
+ */
+#define _mmcsd_block_device_methods \
+ _base_block_device_methods
+
+/**
+ * @brief @p MMCSDBlockDevice specific data.
+ * @note It is empty because @p MMCSDBlockDevice is only an interface
+ * without implementation.
+ */
+#define _mmcsd_block_device_data \
+ _base_block_device_data \
+ /* Card CID.*/ \
+ uint32_t cid[4]; \
+ /* Card CSD.*/ \
+ uint32_t csd[4]; \
+ /* Total number of blocks in card.*/ \
+ uint32_t capacity;
+
+/**
+ * @extends BaseBlockDeviceVMT
+ *
+ * @brief @p MMCSDBlockDevice virtual methods table.
+ */
+struct MMCSDBlockDeviceVMT {
+ _base_block_device_methods
+};
+
+/**
+ * @extends BaseBlockDevice
+ *
+ * @brief MCC/SD block device class.
+ * @details This class represents a, block-accessible, MMC/SD device.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct MMCSDBlockDeviceVMT *vmt;
+ _mmcsd_block_device_data
+} MMCSDBlockDevice;
+
+/**
+ * @brief Unpacked CID register from SDC.
+ */
+typedef struct {
+ uint8_t mid;
+ uint16_t oid;
+ char pnm[5];
+ uint8_t prv_n;
+ uint8_t prv_m;
+ uint32_t psn;
+ uint8_t mdt_m;
+ uint16_t mdt_y;
+ uint8_t crc;
+} unpacked_sdc_cid_t;
+
+/**
+ * @brief Unpacked CID register from MMC.
+ */
+typedef struct {
+ uint8_t mid;
+ uint16_t oid;
+ char pnm[6];
+ uint8_t prv_n;
+ uint8_t prv_m;
+ uint32_t psn;
+ uint8_t mdt_m;
+ uint16_t mdt_y;
+ uint8_t crc;
+} unpacked_mmc_cid_t;
+
+/**
+ * @brief Unpacked CSD v1.0 register from SDC.
+ */
+typedef struct {
+ uint8_t csd_structure;
+ uint8_t taac;
+ uint8_t nsac;
+ uint8_t tran_speed;
+ uint16_t ccc;
+ uint8_t read_bl_len;
+ uint8_t read_bl_partial;
+ uint8_t write_blk_misalign;
+ uint8_t read_blk_misalign;
+ uint8_t dsr_imp;
+ uint16_t c_size;
+ uint8_t vdd_r_curr_min;
+ uint8_t vdd_r_curr_max;
+ uint8_t vdd_w_curr_min;
+ uint8_t vdd_w_curr_max;
+ uint8_t c_size_mult;
+ uint8_t erase_blk_en;
+ uint8_t erase_sector_size;
+ uint8_t wp_grp_size;
+ uint8_t wp_grp_enable;
+ uint8_t r2w_factor;
+ uint8_t write_bl_len;
+ uint8_t write_bl_partial;
+ uint8_t file_format_grp;
+ uint8_t copy;
+ uint8_t perm_write_protect;
+ uint8_t tmp_write_protect;
+ uint8_t file_format;
+ uint8_t crc;
+} unpacked_sdc_csd_10_t;
+
+/**
+ * @brief Unpacked CSD v2.0 register from SDC.
+ */
+typedef struct {
+ uint8_t csd_structure;
+ uint8_t taac;
+ uint8_t nsac;
+ uint8_t tran_speed;
+ uint16_t ccc;
+ uint8_t read_bl_len;
+ uint8_t read_bl_partial;
+ uint8_t write_blk_misalign;
+ uint8_t read_blk_misalign;
+ uint8_t dsr_imp;
+ uint32_t c_size;
+ uint8_t erase_blk_en;
+ uint8_t erase_sector_size;
+ uint8_t wp_grp_size;
+ uint8_t wp_grp_enable;
+ uint8_t r2w_factor;
+ uint8_t write_bl_len;
+ uint8_t write_bl_partial;
+ uint8_t file_format_grp;
+ uint8_t copy;
+ uint8_t perm_write_protect;
+ uint8_t tmp_write_protect;
+ uint8_t file_format;
+ uint8_t crc;
+} unpacked_sdc_csd_20_t;
+
+/**
+ * @brief Unpacked CSD register from MMC.
+ */
+typedef struct {
+ uint8_t csd_structure;
+ uint8_t spec_vers;
+ uint8_t taac;
+ uint8_t nsac;
+ uint8_t tran_speed;
+ uint16_t ccc;
+ uint8_t read_bl_len;
+ uint8_t read_bl_partial;
+ uint8_t write_blk_misalign;
+ uint8_t read_blk_misalign;
+ uint8_t dsr_imp;
+ uint16_t c_size;
+ uint8_t vdd_r_curr_min;
+ uint8_t vdd_r_curr_max;
+ uint8_t vdd_w_curr_min;
+ uint8_t vdd_w_curr_max;
+ uint8_t c_size_mult;
+ uint8_t erase_grp_size;
+ uint8_t erase_grp_mult;
+ uint8_t wp_grp_size;
+ uint8_t wp_grp_enable;
+ uint8_t default_ecc;
+ uint8_t r2w_factor;
+ uint8_t write_bl_len;
+ uint8_t write_bl_partial;
+ uint8_t content_prot_app;
+ uint8_t file_format_grp;
+ uint8_t copy;
+ uint8_t perm_write_protect;
+ uint8_t tmp_write_protect;
+ uint8_t file_format;
+ uint8_t ecc;
+ uint8_t crc;
+} unpacked_mmc_csd_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name R1 response utilities
+ * @{
+ */
+/**
+ * @brief Evaluates to @p TRUE if the R1 response contains error flags.
+ *
+ * @param[in] r1 the r1 response
+ */
+#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0U)
+
+/**
+ * @brief Returns the status field of an R1 response.
+ *
+ * @param[in] r1 the r1 response
+ */
+#define MMCSD_R1_STS(r1) (((r1) >> 9U) & 15U)
+
+/**
+ * @brief Evaluates to @p TRUE if the R1 response indicates a locked card.
+ *
+ * @param[in] r1 the r1 response
+ */
+#define MMCSD_R1_IS_CARD_LOCKED(r1) ((((r1) >> 21U) & 1U) != 0U)
+/** @} */
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Returns the card capacity in blocks.
+ *
+ * @param[in] ip pointer to a @p MMCSDBlockDevice or derived class
+ *
+ * @return The card capacity.
+ *
+ * @api
+ */
+#define mmcsdGetCardCapacity(ip) ((ip)->capacity)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ uint32_t _mmcsd_get_slice(const uint32_t *data,
+ uint32_t end,
+ uint32_t start);
+ uint32_t _mmcsd_get_capacity(const uint32_t *csd);
+ uint32_t _mmcsd_get_capacity_ext(const uint8_t *ext_csd);
+ void _mmcsd_unpack_sdc_cid(const MMCSDBlockDevice *sdcp,
+ unpacked_sdc_cid_t *cidsdc);
+ void _mmcsd_unpack_mmc_cid(const MMCSDBlockDevice *sdcp,
+ unpacked_mmc_cid_t *cidmmc);
+ void _mmcsd_unpack_csd_mmc(const MMCSDBlockDevice *sdcp,
+ unpacked_mmc_csd_t *csdmmc);
+ void _mmcsd_unpack_csd_v10(const MMCSDBlockDevice *sdcp,
+ unpacked_sdc_csd_10_t *csd10);
+ void _mmcsd_unpack_csd_v20(const MMCSDBlockDevice *sdcp,
+ unpacked_sdc_csd_20_t *csd20);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_MMC_SPI == TRUE || HAL_USE_MMC_SDC == TRUE */
+
+#endif /* HAL_MMCSD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/pal.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_pal.h
similarity index 57%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/pal.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_pal.h
index db76efc369..00786b67d0 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/pal.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_pal.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file pal.h
+ * @file hal_pal.h
* @brief I/O Ports Abstraction Layer macros, types and structures.
*
* @addtogroup PAL
* @{
*/
-#ifndef _PAL_H_
-#define _PAL_H_
+#ifndef HAL_PAL_H
+#define HAL_PAL_H
-#if HAL_USE_PAL || defined(__DOXYGEN__)
+#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -52,7 +41,7 @@
* it is guaranteed to be equal to the after-reset state. It is
* usually an input state.
*/
-#define PAL_MODE_RESET 0
+#define PAL_MODE_RESET 0U
/**
* @brief Safe state for unconnected pads.
@@ -61,37 +50,37 @@
* @p PAL_MODE_INPUT_PULLDOWN or @p PAL_MODE_OUTPUT_PUSHPULL for
* example.
*/
-#define PAL_MODE_UNCONNECTED 1
+#define PAL_MODE_UNCONNECTED 1U
/**
* @brief Regular input high-Z pad.
*/
-#define PAL_MODE_INPUT 2
+#define PAL_MODE_INPUT 2U
/**
* @brief Input pad with weak pull up resistor.
*/
-#define PAL_MODE_INPUT_PULLUP 3
+#define PAL_MODE_INPUT_PULLUP 3U
/**
* @brief Input pad with weak pull down resistor.
*/
-#define PAL_MODE_INPUT_PULLDOWN 4
+#define PAL_MODE_INPUT_PULLDOWN 4U
/**
* @brief Analog input mode.
*/
-#define PAL_MODE_INPUT_ANALOG 5
+#define PAL_MODE_INPUT_ANALOG 5U
/**
* @brief Push-pull output pad.
*/
-#define PAL_MODE_OUTPUT_PUSHPULL 6
+#define PAL_MODE_OUTPUT_PUSHPULL 6U
/**
* @brief Open-drain output pad.
*/
-#define PAL_MODE_OUTPUT_OPENDRAIN 7
+#define PAL_MODE_OUTPUT_OPENDRAIN 7U
/** @} */
/**
@@ -101,12 +90,23 @@
/**
* @brief Logical low state.
*/
-#define PAL_LOW 0
+#define PAL_LOW 0U
/**
* @brief Logical high state.
*/
-#define PAL_HIGH 1
+#define PAL_HIGH 1U
+/** @} */
+
+/**
+ * @name PAL event modes
+ * @{
+ */
+#define PAL_EVENT_MODE_EDGES_MASK 3U /**< @brief Mask of edges field. */
+#define PAL_EVENT_MODE_DISABLED 0U /**< @brief Channel disabled. */
+#define PAL_EVENT_MODE_RISING_EDGE 1U /**< @brief Rising edge callback. */
+#define PAL_EVENT_MODE_FALLING_EDGE 2U /**< @brief Falling edge callback. */
+#define PAL_EVENT_MODE_BOTH_EDGES 3U /**< @brief Both edges callback. */
/** @} */
/*===========================================================================*/
@@ -121,7 +121,12 @@
/* Driver data structures and types. */
/*===========================================================================*/
-#include "pal_lld.h"
+/**
+ * @brief Type of a PAL event callback.
+ */
+typedef void (*palcallback_t)(void);
+
+#include "hal_pal_lld.h"
/**
* @brief I/O bus descriptor.
@@ -137,7 +142,7 @@ typedef struct {
ioportid_t portid;
/**
* @brief Bus mask aligned to port bit 0.
- * @note The bus mask implicitly define the bus width. A logical AND is
+ * @note The bus mask implicitly define the bus width. A logic AND is
* performed on the bus data.
*/
ioportmask_t mask;
@@ -159,7 +164,7 @@ typedef struct {
* @return The bit mask.
*/
#if !defined(PAL_PORT_BIT) || defined(__DOXYGEN__)
-#define PAL_PORT_BIT(n) ((ioportmask_t)(1 << (n)))
+#define PAL_PORT_BIT(n) ((ioportmask_t)(1U << (n)))
#endif
/**
@@ -170,7 +175,7 @@ typedef struct {
* @return The group mask.
*/
#if !defined(PAL_GROUP_MASK) || defined(__DOXYGEN__)
-#define PAL_GROUP_MASK(width) ((ioportmask_t)(1 << (width)) - 1)
+#define PAL_GROUP_MASK(width) ((ioportmask_t)(1U << (width)) - 1U)
#endif
/**
@@ -216,17 +221,15 @@ typedef struct {
/**
* @brief Reads the physical I/O port states.
- * @note The default implementation always return zero and computes the
- * parameter eventual side effects.
* @note The function can be called from any context.
*
* @param[in] port port identifier
- * @return The port logical states.
+ * @return The port logic states.
*
* @special
*/
#if !defined(pal_lld_readport) || defined(__DOXYGEN__)
-#define palReadPort(port) ((void)(port), 0)
+#define palReadPort(port) ((void)(port), 0U)
#else
#define palReadPort(port) pal_lld_readport(port)
#endif
@@ -235,25 +238,21 @@ typedef struct {
* @brief Reads the output latch.
* @details The purpose of this function is to read back the latched output
* value.
- * @note The default implementation always return zero and computes the
- * parameter eventual side effects.
* @note The function can be called from any context.
*
* @param[in] port port identifier
- * @return The latched logical states.
+ * @return The latched logic states.
*
* @special
*/
#if !defined(pal_lld_readlatch) || defined(__DOXYGEN__)
-#define palReadLatch(port) ((void)(port), 0)
+#define palReadLatch(port) ((void)(port), 0U)
#else
#define palReadLatch(port) pal_lld_readlatch(port)
#endif
/**
* @brief Writes a bits mask on a I/O port.
- * @note The default implementation does nothing except computing the
- * parameters eventual side effects.
* @note The function can be called from any context.
*
* @param[in] port port identifier
@@ -271,11 +270,8 @@ typedef struct {
* @brief Sets a bits mask on a I/O port.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
- * @note The default implementation is non atomic and not necessarily
- * optimal. Low level drivers may optimize the function by using
- * specific hardware or coding.
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function can be called from any context.
*
* @param[in] port port identifier
@@ -294,11 +290,8 @@ typedef struct {
* @brief Clears a bits mask on a I/O port.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
- * @note The default implementation is non atomic and not necessarily
- * optimal. Low level drivers may optimize the function by using
- * specific hardware or coding.
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function can be called from any context.
*
* @param[in] port port identifier
@@ -317,11 +310,8 @@ typedef struct {
* @brief Toggles a bits mask on a I/O port.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
- * @note The default implementation is non atomic and not necessarily
- * optimal. Low level drivers may optimize the function by using
- * specific hardware or coding.
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function can be called from any context.
*
* @param[in] port port identifier
@@ -341,10 +331,10 @@ typedef struct {
* @note The function can be called from any context.
*
* @param[in] port port identifier
- * @param[in] mask group mask, a logical AND is performed on the input
+ * @param[in] mask group mask, a logic AND is performed on the input
* data
* @param[in] offset group bit offset within the port
- * @return The group logical states.
+ * @return The group logic states.
*
* @special
*/
@@ -357,10 +347,14 @@ typedef struct {
/**
* @brief Writes a group of bits.
+ * @note The operation is not guaranteed to be atomic on all the
+ * architectures, for atomicity and/or portability reasons you may
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function can be called from any context.
*
* @param[in] port port identifier
- * @param[in] mask group mask, a logical AND is performed on the
+ * @param[in] mask group mask, a logic AND is performed on the
* output data
* @param[in] offset group bit offset within the port
* @param[in] bits bits to be written. Values exceeding the group
@@ -377,11 +371,14 @@ typedef struct {
pal_lld_writegroup(port, mask, offset, bits)
#endif
-
/**
* @brief Pads group mode setup.
* @details This function programs a pads group belonging to the same port
* with the specified mode.
+ * @note The operation is not guaranteed to be atomic on all the
+ * architectures, for atomicity and/or portability reasons you may
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note Programming an unknown or unsupported mode is silently ignored.
* @note The function can be called from any context.
*
@@ -400,43 +397,34 @@ typedef struct {
#endif
/**
- * @brief Reads an input pad logical state.
- * @note The default implementation not necessarily optimal. Low level
- * drivers may optimize the function by using specific hardware
- * or coding.
- * @note The default implementation internally uses the @p palReadPort().
+ * @brief Reads an input pad logic state.
* @note The function can be called from any context.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
- * @return The logical state.
- * @retval PAL_LOW low logical state.
- * @retval PAL_HIGH high logical state.
+ * @return The logic state.
+ * @retval PAL_LOW low logic state.
+ * @retval PAL_HIGH high logic state.
*
* @special
*/
#if !defined(pal_lld_readpad) || defined(__DOXYGEN__)
-#define palReadPad(port, pad) ((palReadPort(port) >> (pad)) & 1)
+#define palReadPad(port, pad) ((palReadPort(port) >> (pad)) & 1U)
#else
#define palReadPad(port, pad) pal_lld_readpad(port, pad)
#endif
/**
- * @brief Writes a logical state on an output pad.
+ * @brief Writes a logic state on an output pad.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
- * @note The default implementation is non atomic and not necessarily
- * optimal. Low level drivers may optimize the function by using
- * specific hardware or coding.
- * @note The default implementation internally uses the @p palReadLatch()
- * and @p palWritePort().
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function can be called from any context.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @param[in] bit logic value, the value must be @p PAL_LOW or
* @p PAL_HIGH
*
* @special
@@ -444,21 +432,17 @@ typedef struct {
#if !defined(pal_lld_writepad) || defined(__DOXYGEN__)
#define palWritePad(port, pad, bit) \
palWritePort(port, (palReadLatch(port) & ~PAL_PORT_BIT(pad)) | \
- (((bit) & 1) << pad))
+ (((bit) & 1U) << pad))
#else
#define palWritePad(port, pad, bit) pal_lld_writepad(port, pad, bit)
#endif
/**
- * @brief Sets a pad logical state to @p PAL_HIGH.
+ * @brief Sets a pad logic state to @p PAL_HIGH.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
- * @note The default implementation is non atomic and not necessarily
- * optimal. Low level drivers may optimize the function by using
- * specific hardware or coding.
- * @note The default implementation internally uses the @p palSetPort().
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function can be called from any context.
*
* @param[in] port port identifier
@@ -473,15 +457,11 @@ typedef struct {
#endif
/**
- * @brief Clears a pad logical state to @p PAL_LOW.
+ * @brief Clears a pad logic state to @p PAL_LOW.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
- * @note The default implementation is non atomic and not necessarily
- * optimal. Low level drivers may optimize the function by using
- * specific hardware or coding.
- * @note The default implementation internally uses the @p palClearPort().
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function can be called from any context.
*
* @param[in] port port identifier
@@ -496,15 +476,11 @@ typedef struct {
#endif
/**
- * @brief Toggles a pad logical state.
+ * @brief Toggles a pad logic state.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
- * @note The default implementation is non atomic and not necessarily
- * optimal. Low level drivers may optimize the function by using
- * specific hardware or coding.
- * @note The default implementation internally uses the @p palTogglePort().
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function can be called from any context.
*
* @param[in] port port identifier
@@ -521,9 +497,10 @@ typedef struct {
/**
* @brief Pad mode setup.
* @details This function programs a pad with the specified mode.
- * @note The default implementation not necessarily optimal. Low level
- * drivers may optimize the function by using specific hardware
- * or coding.
+ * @note The operation is not guaranteed to be atomic on all the
+ * architectures, for atomicity and/or portability reasons you may
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note Programming an unknown or unsupported mode is silently ignored.
* @note The function can be called from any context.
*
@@ -535,10 +512,188 @@ typedef struct {
*/
#if !defined(pal_lld_setpadmode) || defined(__DOXYGEN__)
#define palSetPadMode(port, pad, mode) \
- palSetGroupMode(port, PAL_PORT_BIT(pad), 0, mode)
+ palSetGroupMode(port, PAL_PORT_BIT(pad), 0U, mode)
#else
#define palSetPadMode(port, pad, mode) pal_lld_setpadmode(port, pad, mode)
#endif
+
+/**
+ * @brief Pad event enable.
+ * @details This function programs an event callback in the specified mode.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad event mode
+ * @param[in] callback event callback function
+ *
+ * @iclass
+ */
+#if !defined(pal_lld_enablepadevent) || defined(__DOXYGEN__)
+#define palPadEnableEventI(port, pad, mode, callback)
+#else
+#define palPadEnableEventI(port, pad, mode, callback) \
+ pal_lld_enablepadevent(port, pad, mode, callback)
+#endif
+
+/**
+ * @brief Pad event disable.
+ * @details This function disables previously programmed event callbacks.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @iclass
+ */
+#if !defined(pal_lld_disablepadevent) || defined(__DOXYGEN__)
+#define palPadDisableEventI(port, pad)
+#else
+#define palPadDisableEventI(port, pad) \
+ pal_lld_disablepadevent(port, pad)
+#endif
+
+/**
+ * @brief Reads an input line logic state.
+ * @note The function can be called from any context.
+ *
+ * @param[in] line line identifier
+ * @return The logic state.
+ * @retval PAL_LOW low logic state.
+ * @retval PAL_HIGH high logic state.
+ *
+ * @special
+ */
+#if !defined(pal_lld_readline) || defined(__DOXYGEN__)
+#define palReadLine(line) palReadPad(PAL_PORT(line), PAL_PAD(line))
+#else
+#define palReadLine(line) pal_lld_readline(line)
+#endif
+
+/**
+ * @brief Writes a logic state on an output line.
+ * @note The operation is not guaranteed to be atomic on all the
+ * architectures, for atomicity and/or portability reasons you may
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
+ * @note The function can be called from any context.
+ *
+ * @param[in] line line identifier
+ * @param[in] bit logic value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @special
+ */
+#if !defined(pal_lld_writeline) || defined(__DOXYGEN__)
+#define palWriteLine(line, bit) palWritePad(PAL_PORT(line), PAL_PAD(line), bit)
+#else
+#define palWriteLine(line, bit) pal_lld_writeline(line, bit)
+#endif
+
+/**
+ * @brief Sets a line logic state to @p PAL_HIGH.
+ * @note The operation is not guaranteed to be atomic on all the
+ * architectures, for atomicity and/or portability reasons you may
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
+ * @note The function can be called from any context.
+ *
+ * @param[in] line line identifier
+ *
+ * @special
+ */
+#if !defined(pal_lld_setline) || defined(__DOXYGEN__)
+#define palSetLine(line) palSetPad(PAL_PORT(line), PAL_PAD(line))
+#else
+#define palSetLine(line) pal_lld_setline(line)
+#endif
+
+/**
+ * @brief Clears a line logic state to @p PAL_LOW.
+ * @note The operation is not guaranteed to be atomic on all the
+ * architectures, for atomicity and/or portability reasons you may
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
+ * @note The function can be called from any context.
+ *
+ * @param[in] line line identifier
+ *
+ * @special
+ */
+#if !defined(pal_lld_clearline) || defined(__DOXYGEN__)
+#define palClearLine(line) palClearPad(PAL_PORT(line), PAL_PAD(line))
+#else
+#define palClearLine(line) pal_lld_clearline(line)
+#endif
+
+/**
+ * @brief Toggles a line logic state.
+ * @note The operation is not guaranteed to be atomic on all the
+ * architectures, for atomicity and/or portability reasons you may
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
+ * @note The function can be called from any context.
+ *
+ * @param[in] line line identifier
+ *
+ * @special
+ */
+#if !defined(pal_lld_toggleline) || defined(__DOXYGEN__)
+#define palToggleLine(line) palTogglePad(PAL_PORT(line), PAL_PAD(line))
+#else
+#define palToggleLine(line) pal_lld_toggleline(line)
+#endif
+
+/**
+ * @brief Line mode setup.
+ * @note The operation is not guaranteed to be atomic on all the
+ * architectures, for atomicity and/or portability reasons you may
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
+ * @note The function can be called from any context.
+ *
+ * @param[in] line line identifier
+ * @param[in] mode pad mode
+ *
+ * @special
+ */
+#if !defined(pal_lld_setlinemode) || defined(__DOXYGEN__)
+#define palSetLineMode(line, mode) \
+ palSetPadMode(PAL_PORT(line), PAL_PAD(line), mode)
+#else
+#define palSetLineMode(line, mode) pal_lld_setlinemode(line, mode)
+#endif
+
+/**
+ * @brief Line event enable.
+ *
+ * @param[in] line line identifier
+ * @param[in] mode line event mode
+ * @param[in] callback event callback function
+ *
+ * @iclass
+ */
+#if !defined(pal_lld_lineenableevent) || defined(__DOXYGEN__)
+#define palLineEnableEventI(line, mode, callback) \
+ palPadEnableEventI(PAL_PORT(line), PAL_PAD(line), mode, callback)
+#else
+#define palLineEnableEventI(line, mode, callback) \
+ pal_lld_lineenableevent(line, mode, callback)
+#endif
+
+/**
+ * @brief Line event disable.
+ *
+ * @param[in] line line identifier
+ *
+ * @iclass
+ */
+#if !defined(pal_lld_linedisableevent) || defined(__DOXYGEN__)
+#define palLineDisableEventI(line) \
+ palPadDisableEventI(PAL_PORT(line), PAL_PAD(line))
+#else
+#define palLineDisableEventI(line) pal_lld_linedisableevent(line)
+#endif
+
/** @} */
/*===========================================================================*/
@@ -555,8 +710,8 @@ extern "C" {
}
#endif
-#endif /* _PAL_H_ */
+#endif /* HAL_PAL_H */
-#endif /* HAL_USE_PAL */
+#endif /* HAL_USE_PAL == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/pwm.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_pwm.h
similarity index 63%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/pwm.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_pwm.h
index 9149944e7c..791f960501 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/pwm.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_pwm.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file pwm.h
+ * @file hal_pwm.h
* @brief PWM Driver macros and structures.
*
* @addtogroup PWM
* @{
*/
-#ifndef _PWM_H_
-#define _PWM_H_
+#ifndef HAL_PWM_H
+#define HAL_PWM_H
-#if HAL_USE_PWM || defined(__DOXYGEN__)
+#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -49,22 +38,22 @@
/**
* @brief Standard output modes mask.
*/
-#define PWM_OUTPUT_MASK 0x0F
+#define PWM_OUTPUT_MASK 0x0FU
/**
* @brief Output not driven, callback only.
*/
-#define PWM_OUTPUT_DISABLED 0x00
+#define PWM_OUTPUT_DISABLED 0x00U
/**
* @brief Positive PWM logic, active is logic level one.
*/
-#define PWM_OUTPUT_ACTIVE_HIGH 0x01
+#define PWM_OUTPUT_ACTIVE_HIGH 0x01U
/**
* @brief Inverse PWM logic, active is logic level zero.
*/
-#define PWM_OUTPUT_ACTIVE_LOW 0x02
+#define PWM_OUTPUT_ACTIVE_LOW 0x02U
/** @} */
/*===========================================================================*/
@@ -85,7 +74,7 @@
typedef enum {
PWM_UNINIT = 0, /**< Not initialized. */
PWM_STOP = 1, /**< Stopped. */
- PWM_READY = 2, /**< Ready. */
+ PWM_READY = 2 /**< Ready. */
} pwmstate_t;
/**
@@ -94,13 +83,13 @@ typedef enum {
typedef struct PWMDriver PWMDriver;
/**
- * @brief PWM notification callback type.
+ * @brief Type of a PWM notification callback.
*
* @param[in] pwmp pointer to a @p PWMDriver object
*/
typedef void (*pwmcallback_t)(PWMDriver *pwmp);
-#include "pwm_lld.h"
+#include "hal_pwm_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -194,13 +183,15 @@ typedef void (*pwmcallback_t)(PWMDriver *pwmp);
* or immediately (fallback implementation).
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] channel PWM channel identifier (0...channels-1)
* @param[in] width PWM pulse width as clock pulses number
*
* @iclass
*/
-#define pwmEnableChannelI(pwmp, channel, width) \
- pwm_lld_enable_channel(pwmp, channel, width)
+#define pwmEnableChannelI(pwmp, channel, width) do { \
+ (pwmp)->enabled |= ((pwmchnmsk_t)1U << (pwmchnmsk_t)(channel)); \
+ pwm_lld_enable_channel(pwmp, channel, width); \
+} while (false)
/**
* @brief Disables a PWM channel.
@@ -212,24 +203,78 @@ typedef void (*pwmcallback_t)(PWMDriver *pwmp);
* or immediately (fallback implementation).
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] channel PWM channel identifier (0...channels-1)
*
* @iclass
*/
-#define pwmDisableChannelI(pwmp, channel) \
- pwm_lld_disable_channel(pwmp, channel)
+#define pwmDisableChannelI(pwmp, channel) do { \
+ (pwmp)->enabled &= ~((pwmchnmsk_t)1U << (pwmchnmsk_t)(channel)); \
+ pwm_lld_disable_channel(pwmp, channel); \
+} while (false)
/**
* @brief Returns a PWM channel status.
* @pre The PWM unit must have been activated using @p pwmStart().
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] channel PWM channel identifier (0...channels-1)
*
* @iclass
*/
#define pwmIsChannelEnabledI(pwmp, channel) \
- pwm_lld_is_channel_enabled(pwmp, channel)
+ (((pwmp)->enabled & ((pwmchnmsk_t)1U << (pwmchnmsk_t)(channel))) != 0U)
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @iclass
+ */
+#define pwmEnablePeriodicNotificationI(pwmp) \
+ pwm_lld_enable_periodic_notification(pwmp)
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @iclass
+ */
+#define pwmDisablePeriodicNotificationI(pwmp) \
+ pwm_lld_disable_periodic_notification(pwmp)
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @iclass
+ */
+#define pwmEnableChannelNotificationI(pwmp, channel) \
+ pwm_lld_enable_channel_notification(pwmp, channel)
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @iclass
+ */
+#define pwmDisableChannelNotificationI(pwmp, channel) \
+ pwm_lld_disable_channel_notification(pwmp, channel)
/** @} */
/*===========================================================================*/
@@ -248,12 +293,16 @@ extern "C" {
pwmchannel_t channel,
pwmcnt_t width);
void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwmEnablePeriodicNotification(PWMDriver *pwmp);
+ void pwmDisablePeriodicNotification(PWMDriver *pwmp);
+ void pwmEnableChannelNotification(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwmDisableChannelNotification(PWMDriver *pwmp, pwmchannel_t channel);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_PWM */
+#endif /* HAL_USE_PWM == TRUE */
-#endif /* _PWM_H_ */
+#endif /* HAL_PWM_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_qspi.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_qspi.h
new file mode 100644
index 0000000000..cce8db9885
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_qspi.h
@@ -0,0 +1,321 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_qspi.h
+ * @brief QSPI Driver macros and structures.
+ *
+ * @addtogroup QSPI
+ * @{
+ */
+
+#ifndef HAL_QSPI_H
+#define HAL_QSPI_H
+
+#if (HAL_USE_QSPI == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Transfer options
+ * @{
+ */
+#define QSPI_CFG_CMD_MASK (0xFFLU << 0LU)
+#define QSPI_CFG_CMD(n) ((n) << 0LU)
+#define QSPI_CFG_CMD_MODE_MASK (3LU << 8LU)
+#define QSPI_CFG_CMD_MODE_NONE (0LU << 8LU)
+#define QSPI_CFG_CMD_MODE_ONE_LINE (1LU << 8LU)
+#define QSPI_CFG_CMD_MODE_TWO_LINES (2LU << 8LU)
+#define QSPI_CFG_CMD_MODE_FOUR_LINES (3LU << 8LU)
+#define QSPI_CFG_ADDR_MODE_MASK (3LU << 10LU)
+#define QSPI_CFG_ADDR_MODE_NONE (0LU << 10LU)
+#define QSPI_CFG_ADDR_MODE_ONE_LINE (1LU << 10LU)
+#define QSPI_CFG_ADDR_MODE_TWO_LINES (2LU << 10LU)
+#define QSPI_CFG_ADDR_MODE_FOUR_LINES (3LU << 10LU)
+#define QSPI_CFG_ADDR_SIZE_MASK (3LU << 12LU)
+#define QSPI_CFG_ADDR_SIZE_8 (0LU << 12LU)
+#define QSPI_CFG_ADDR_SIZE_16 (1LU << 12LU)
+#define QSPI_CFG_ADDR_SIZE_24 (2LU << 12LU)
+#define QSPI_CFG_ADDR_SIZE_32 (3LU << 12LU)
+#define QSPI_CFG_ALT_MODE_MASK (3LU << 14LU)
+#define QSPI_CFG_ALT_MODE_NONE (0LU << 14LU)
+#define QSPI_CFG_ALT_MODE_ONE_LINE (1LU << 14LU)
+#define QSPI_CFG_ALT_MODE_TWO_LINES (2LU << 14LU)
+#define QSPI_CFG_ALT_MODE_FOUR_LINES (3LU << 14LU)
+#define QSPI_CFG_ALT_SIZE_MASK (3LU << 16LU)
+#define QSPI_CFG_ALT_SIZE_8 (0LU << 16LU)
+
+#define QSPI_CFG_ALT_SIZE_16 (1LU << 16LU)
+#define QSPI_CFG_ALT_SIZE_24 (2LU << 16LU)
+#define QSPI_CFG_ALT_SIZE_32 (3LU << 16LU)
+#define QSPI_CFG_DUMMY_CYCLES_MASK (0x1FLU << 18LU)
+#define QSPI_CFG_DUMMY_CYCLES(n) ((n) << 18LU)
+#define QSPI_CFG_DATA_MODE_MASK (3LU << 24LU)
+#define QSPI_CFG_DATA_MODE_NONE (0LU << 24LU)
+#define QSPI_CFG_DATA_MODE_ONE_LINE (1LU << 24LU)
+#define QSPI_CFG_DATA_MODE_TWO_LINES (2LU << 24LU)
+#define QSPI_CFG_DATA_MODE_FOUR_LINES (3LU << 24LU)
+#define QSPI_CFG_SIOO (1LU << 28LU)
+#define QSPI_CFG_DDRM (1LU << 31LU)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name QSPI configuration options
+ * @{
+ */
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__)
+#define QSPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define QSPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ QSPI_UNINIT = 0, /**< Not initialized. */
+ QSPI_STOP = 1, /**< Stopped. */
+ QSPI_READY = 2, /**< Ready. */
+ QSPI_ACTIVE = 3, /**< Exchanging data. */
+ QSPI_COMPLETE = 4, /**< Asynchronous operation complete. */
+ QSPI_MEMMAP = 5 /**< In memory mapped mode. */
+} qspistate_t;
+
+/**
+ * @brief Type of a QSPI command descriptor.
+ */
+typedef struct {
+ uint32_t cfg;
+ uint32_t addr;
+ uint32_t alt;
+} qspi_command_t;
+
+#include "hal_qspi_lld.h"
+
+#if !defined(QSPI_SUPPORTS_MEMMAP)
+#error "low level does not define QSPI_SUPPORTS_MEMMAP"
+#endif
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Sends a command without data phase.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ *
+ * @iclass
+ */
+#define qspiStartCommandI(qspip, cmdp) { \
+ osalDbgAssert(((cmdp)->cfg & QSPI_CFG_DATA_MODE_MASK) == \
+ QSPI_CFG_DATA_MODE_NONE, \
+ "data mode specified"); \
+ (qspip)->state = QSPI_ACTIVE; \
+ qspi_lld_command(qspip, cmdp); \
+}
+
+/**
+ * @brief Sends data over the QSPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[in] n number of bytes to send or zero if no data phase
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @iclass
+ */
+#define qspiStartSendI(qspip, cmdp, n, txbuf) { \
+ osalDbgAssert(((cmdp)->cfg & QSPI_CFG_DATA_MODE_MASK) != \
+ QSPI_CFG_DATA_MODE_NONE, \
+ "data mode required"); \
+ (qspip)->state = QSPI_ACTIVE; \
+ qspi_lld_send(qspip, cmdp, n, txbuf); \
+}
+
+/**
+ * @brief Receives data from the QSPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[in] n number of bytes to receive or zero if no data phase
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @iclass
+ */
+#define qspiStartReceiveI(qspip, cmdp, n, rxbuf) { \
+ osalDbgAssert(((cmdp)->cfg & QSPI_CFG_DATA_MODE_MASK) != \
+ QSPI_CFG_DATA_MODE_NONE, \
+ "data mode required"); \
+ (qspip)->state = QSPI_ACTIVE; \
+ qspi_lld_receive(qspip, cmdp, n, rxbuf); \
+}
+
+#if (QSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Maps in memory space a QSPI flash device.
+ * @pre The memory flash device must be initialized appropriately
+ * before mapping it in memory space.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[out] addrp pointer to the memory start address of the mapped
+ * flash or @p NULL
+ *
+ * @iclass
+ */
+#define qspiMapFlashI(qspip, cmdp, addrp) \
+ qspi_lld_map_flash(qspip, cmdp, addrp)
+
+/**
+ * @brief Maps in memory space a QSPI flash device.
+ * @post The memory flash device must be re-initialized for normal
+ * commands exchange.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @iclass
+ */
+#define qspiUnmapFlashI(qspip) \
+ qspi_lld_unmap_flash(qspip)
+#endif /* QSPI_SUPPORTS_MEMMAP == TRUE */
+/** @} */
+
+/**
+ * @name Low level driver helper macros
+ * @{
+ */
+#if (QSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Wakes up the waiting thread.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @notapi
+ */
+#define _qspi_wakeup_isr(qspip) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(qspip)->thread, MSG_OK); \
+ osalSysUnlockFromISR(); \
+}
+#else /* !QSPI_USE_WAIT */
+#define _qspi_wakeup_isr(qspip)
+#endif /* !QSPI_USE_WAIT */
+
+/**
+ * @brief Common ISR code.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @notapi
+ */
+#define _qspi_isr_code(qspip) { \
+ if ((qspip)->config->end_cb) { \
+ (qspip)->state = QSPI_COMPLETE; \
+ (qspip)->config->end_cb(qspip); \
+ if ((qspip)->state == QSPI_COMPLETE) \
+ (qspip)->state = QSPI_READY; \
+ } \
+ else \
+ (qspip)->state = QSPI_READY; \
+ _qspi_wakeup_isr(qspip); \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void qspiInit(void);
+ void qspiObjectInit(QSPIDriver *qspip);
+ void qspiStart(QSPIDriver *qspip, const QSPIConfig *config);
+ void qspiStop(QSPIDriver *qspip);
+ void qspiStartCommand(QSPIDriver *qspip, const qspi_command_t *cmdp);
+ void qspiStartSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, const uint8_t *txbuf);
+ void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, uint8_t *rxbuf);
+#if QSPI_USE_WAIT == TRUE
+ void qspiCommand(QSPIDriver *qspip, const qspi_command_t *cmdp);
+ void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, const uint8_t *txbuf);
+ void qspiReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, uint8_t *rxbuf);
+#endif
+#if QSPI_SUPPORTS_MEMMAP == TRUE
+void qspiMapFlash(QSPIDriver *qspip,
+ const qspi_command_t *cmdp,
+ uint8_t **addrp);
+void qspiUnmapFlash(QSPIDriver *qspip);
+#endif
+#if QSPI_USE_MUTUAL_EXCLUSION == TRUE
+ void qspiAcquireBus(QSPIDriver *qspip);
+ void qspiReleaseBus(QSPIDriver *qspip);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_QSPI == TRUE */
+
+#endif /* HAL_QSPI_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_queues.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_queues.h
new file mode 100644
index 0000000000..6dc07949a8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_queues.h
@@ -0,0 +1,298 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_queues.h
+ * @brief I/O Queues macros and structures.
+ *
+ * @addtogroup HAL_QUEUES
+ * @{
+ */
+
+#ifndef HAL_QUEUES_H
+#define HAL_QUEUES_H
+
+/**
+ * @name Queue functions returned status value
+ * @{
+ */
+#define Q_OK MSG_OK /**< @brief Operation successful. */
+#define Q_TIMEOUT MSG_TIMEOUT /**< @brief Timeout condition. */
+#define Q_RESET MSG_RESET /**< @brief Queue has been reset. */
+#define Q_EMPTY MSG_TIMEOUT /**< @brief Queue empty. */
+#define Q_FULL MSG_TIMEOUT /**< @brief Queue full, */
+/** @} */
+
+/**
+ * @brief Type of a generic I/O queue structure.
+ */
+typedef struct io_queue io_queue_t;
+
+/**
+ * @brief Queue notification callback type.
+ *
+ * @param[in] qp the queue pointer
+ */
+typedef void (*qnotify_t)(io_queue_t *qp);
+
+/**
+ * @brief Generic I/O queue structure.
+ * @details This structure represents a generic Input or Output asymmetrical
+ * queue. The queue is asymmetrical because one end is meant to be
+ * accessed from a thread context, and thus can be blocking, the other
+ * end is accessible from interrupt handlers or from within a kernel
+ * lock zone and is non-blocking.
+ */
+struct io_queue {
+ threads_queue_t q_waiting; /**< @brief Queue of waiting threads. */
+ volatile size_t q_counter; /**< @brief Resources counter. */
+ uint8_t *q_buffer; /**< @brief Pointer to the queue buffer.*/
+ uint8_t *q_top; /**< @brief Pointer to the first
+ location after the buffer. */
+ uint8_t *q_wrptr; /**< @brief Write pointer. */
+ uint8_t *q_rdptr; /**< @brief Read pointer. */
+ qnotify_t q_notify; /**< @brief Data notification callback. */
+ void *q_link; /**< @brief Application defined field. */
+};
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Returns the queue's buffer size.
+ *
+ * @param[in] qp pointer to a @p io_queue_t structure
+ * @return The buffer size.
+ *
+ * @xclass
+ */
+#define qSizeX(qp) \
+ /*lint -save -e9033 [10.8] The cast is safe.*/ \
+ ((size_t)((qp)->q_top - (qp)->q_buffer)) \
+ /*lint -restore*/
+
+/**
+ * @brief Queue space.
+ * @details Returns the used space if used on an input queue or the empty
+ * space if used on an output queue.
+ *
+ * @param[in] qp pointer to a @p io_queue_t structure
+ * @return The buffer space.
+ *
+ * @iclass
+ */
+#define qSpaceI(qp) ((qp)->q_counter)
+
+/**
+ * @brief Returns the queue application-defined link.
+ * @note This function can be called in any context.
+ *
+ * @param[in] qp pointer to a @p io_queue_t structure
+ * @return The application-defined link.
+ *
+ * @special
+ */
+#define qGetLink(qp) ((qp)->q_link)
+/** @} */
+
+/**
+ * @extends io_queue_t
+ *
+ * @brief Type of an input queue structure.
+ * @details This structure represents a generic asymmetrical input queue.
+ * Writing to the queue is non-blocking and can be performed from
+ * interrupt handlers or from within a kernel lock zone.
+ * Reading the queue can be a blocking operation and is supposed to
+ * be performed by a system thread.
+ */
+typedef io_queue_t input_queue_t;
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Returns the filled space into an input queue.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ * @return The number of full bytes in the queue.
+ * @retval 0 if the queue is empty.
+ *
+ * @iclass
+ */
+#define iqGetFullI(iqp) qSpaceI(iqp)
+
+/**
+ * @brief Returns the empty space into an input queue.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ * @return The number of empty bytes in the queue.
+ * @retval 0 if the queue is full.
+ *
+ * @iclass
+ */
+#define iqGetEmptyI(iqp) (qSizeX(iqp) - qSpaceI(iqp))
+
+/**
+ * @brief Evaluates to @p true if the specified input queue is empty.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ * @return The queue status.
+ * @retval false if the queue is not empty.
+ * @retval true if the queue is empty.
+ *
+ * @iclass
+ */
+#define iqIsEmptyI(iqp) ((bool)(qSpaceI(iqp) == 0U))
+
+/**
+ * @brief Evaluates to @p true if the specified input queue is full.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ * @return The queue status.
+ * @retval false if the queue is not full.
+ * @retval true if the queue is full.
+ *
+ * @iclass
+ */
+#define iqIsFullI(iqp) \
+ /*lint -save -e9007 [13.5] No side effects, a pointer is passed.*/ \
+ ((bool)(((iqp)->q_wrptr == (iqp)->q_rdptr) && ((iqp)->q_counter != 0U))) \
+ /*lint -restore*/
+
+/**
+ * @brief Input queue read.
+ * @details This function reads a byte value from an input queue. If the queue
+ * is empty then the calling thread is suspended until a byte arrives
+ * in the queue.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ * @return A byte value from the queue.
+ * @retval MSG_RESET if the queue has been reset.
+ *
+ * @api
+ */
+#define iqGet(iqp) iqGetTimeout(iqp, TIME_INFINITE)
+/** @} */
+
+/**
+ * @extends io_queue_t
+ *
+ * @brief Type of an output queue structure.
+ * @details This structure represents a generic asymmetrical output queue.
+ * Reading from the queue is non-blocking and can be performed from
+ * interrupt handlers or from within a kernel lock zone.
+ * Writing the queue can be a blocking operation and is supposed to
+ * be performed by a system thread.
+ */
+typedef io_queue_t output_queue_t;
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Returns the filled space into an output queue.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ * @return The number of full bytes in the queue.
+ * @retval 0 if the queue is empty.
+ *
+ * @iclass
+ */
+#define oqGetFullI(oqp) (qSizeX(oqp) - qSpaceI(oqp))
+
+/**
+ * @brief Returns the empty space into an output queue.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ * @return The number of empty bytes in the queue.
+ * @retval 0 if the queue is full.
+ *
+ * @iclass
+ */
+#define oqGetEmptyI(oqp) qSpaceI(oqp)
+
+/**
+ * @brief Evaluates to @p true if the specified output queue is empty.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ * @return The queue status.
+ * @retval false if the queue is not empty.
+ * @retval true if the queue is empty.
+ *
+ * @iclass
+ */
+#define oqIsEmptyI(oqp) \
+ /*lint -save -e9007 [13.5] No side effects, a pointer is passed.*/ \
+ ((bool)(((oqp)->q_wrptr == (oqp)->q_rdptr) && ((oqp)->q_counter != 0U))) \
+ /*lint -restore*/
+
+/**
+ * @brief Evaluates to @p true if the specified output queue is full.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ * @return The queue status.
+ * @retval false if the queue is not full.
+ * @retval true if the queue is full.
+ *
+ * @iclass
+ */
+#define oqIsFullI(oqp) ((bool)(qSpaceI(oqp) == 0U))
+
+/**
+ * @brief Output queue write.
+ * @details This function writes a byte value to an output queue. If the queue
+ * is full then the calling thread is suspended until there is space
+ * in the queue.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ * @param[in] b the byte value to be written in the queue
+ * @return The operation status.
+ * @retval MSG_OK if the operation succeeded.
+ * @retval MSG_RESET if the queue has been reset.
+ *
+ * @api
+ */
+#define oqPut(oqp, b) oqPutTimeout(oqp, b, TIME_INFINITE)
+ /** @} */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void iqObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size,
+ qnotify_t infy, void *link);
+ void iqResetI(input_queue_t *iqp);
+ msg_t iqPutI(input_queue_t *iqp, uint8_t b);
+ msg_t iqGetTimeout(input_queue_t *iqp, systime_t timeout);
+ size_t iqReadTimeout(input_queue_t *iqp, uint8_t *bp,
+ size_t n, systime_t timeout);
+
+ void oqObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size,
+ qnotify_t onfy, void *link);
+ void oqResetI(output_queue_t *oqp);
+ msg_t oqPutTimeout(output_queue_t *oqp, uint8_t b, systime_t timeout);
+ msg_t oqGetI(output_queue_t *oqp);
+ size_t oqWriteTimeout(output_queue_t *oqp, const uint8_t *bp,
+ size_t n, systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_QUEUES_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_rtc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_rtc.h
new file mode 100644
index 0000000000..883b88e304
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_rtc.h
@@ -0,0 +1,144 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file hal_rtc.h
+ * @brief RTC Driver macros and structures.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#ifndef HAL_RTC_H
+#define HAL_RTC_H
+
+#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__)
+
+/*lint -save -e829 [21.10] The header is required.*/
+#include
+/*lint -restore*/
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Base year of the calendar.
+ */
+#define RTC_BASE_YEAR 1980U
+
+/**
+ * @name Date/Time bit masks for FAT format
+ * @{
+ */
+#define RTC_FAT_TIME_SECONDS_MASK 0x0000001FU
+#define RTC_FAT_TIME_MINUTES_MASK 0x000007E0U
+#define RTC_FAT_TIME_HOURS_MASK 0x0000F800U
+#define RTC_FAT_DATE_DAYS_MASK 0x001F0000U
+#define RTC_FAT_DATE_MONTHS_MASK 0x01E00000U
+#define RTC_FAT_DATE_YEARS_MASK 0xFE000000U
+/** @} */
+
+/**
+ * @name Day of week encoding
+ * @{
+ */
+#define RTC_DAY_CATURDAY 0U
+#define RTC_DAY_MONDAY 1U
+#define RTC_DAY_TUESDAY 2U
+#define RTC_DAY_WEDNESDAY 3U
+#define RTC_DAY_THURSDAY 4U
+#define RTC_DAY_FRIDAY 5U
+#define RTC_DAY_SATURDAY 6U
+#define RTC_DAY_SUNDAY 7U
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an RTC driver.
+ */
+typedef struct RTCDriver RTCDriver;
+
+/**
+ * @brief Type of a structure representing an RTC date/time stamp.
+ */
+typedef struct {
+ /*lint -save -e46 [6.1] In this case uint32_t is fine.*/
+ uint32_t year: 8; /**< @brief Years since 1980. */
+ uint32_t month: 4; /**< @brief Months 1..12. */
+ uint32_t dstflag: 1; /**< @brief DST correction flag. */
+ uint32_t dayofweek: 3; /**< @brief Day of week 1..7. */
+ uint32_t day: 5; /**< @brief Day of the month 1..31. */
+ uint32_t millisecond: 27; /**< @brief Milliseconds since midnight.*/
+ /*lint -restore*/
+} RTCDateTime;
+
+#include "hal_rtc_lld.h"
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void rtcInit(void);
+ void rtcObjectInit(RTCDriver *rtcp);
+ void rtcSetTime(RTCDriver *rtcp, const RTCDateTime *timespec);
+ void rtcGetTime(RTCDriver *rtcp, RTCDateTime *timespec);
+#if RTC_ALARMS > 0
+ void rtcSetAlarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ const RTCAlarm *alarmspec);
+ void rtcGetAlarm(RTCDriver *rtcp, rtcalarm_t alarm, RTCAlarm *alarmspec);
+#endif
+#if RTC_SUPPORTS_CALLBACKS == TRUE
+ void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback);
+#endif
+ void rtcConvertDateTimeToStructTm(const RTCDateTime *timespec,
+ struct tm *timp,
+ uint32_t *tv_msec);
+ void rtcConvertStructTmToDateTime(const struct tm *timp,
+ uint32_t tv_msec,
+ RTCDateTime *timespec);
+ uint32_t rtcConvertDateTimeToFAT(const RTCDateTime *timespec);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_RTC == TRUE */
+#endif /* HAL_RTC_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/sdc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_sdc.h
similarity index 55%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/sdc.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_sdc.h
index 1b74769a89..f7ddfd0d7a 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/sdc.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_sdc.h
@@ -1,72 +1,61 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file sdc.h
+ * @file hal_sdc.h
* @brief SDC Driver macros and structures.
*
* @addtogroup SDC
* @{
*/
-#ifndef _SDC_H_
-#define _SDC_H_
+#ifndef HAL_SDC_H
+#define HAL_SDC_H
-#if HAL_USE_SDC || defined(__DOXYGEN__)
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
- * @name SD cart types
+ * @name SD card types
* @{
*/
-#define SDC_MODE_CARDTYPE_MASK 0xF /**< @brief Card type mask. */
-#define SDC_MODE_CARDTYPE_SDV11 0 /**< @brief Card is SD V1.1.*/
-#define SDC_MODE_CARDTYPE_SDV20 1 /**< @brief Card is SD V2.0.*/
-#define SDC_MODE_CARDTYPE_MMC 2 /**< @brief Card is MMC. */
-#define SDC_MODE_HIGH_CAPACITY 0x10 /**< @brief High cap.card. */
+#define SDC_MODE_CARDTYPE_MASK 0xFU
+#define SDC_MODE_CARDTYPE_SDV11 0U
+#define SDC_MODE_CARDTYPE_SDV20 1U
+#define SDC_MODE_CARDTYPE_MMC 2U
+#define SDC_MODE_HIGH_CAPACITY 0x10U
/** @} */
/**
* @name SDC bus error conditions
* @{
*/
-#define SDC_NO_ERROR 0 /**< @brief No error. */
-#define SDC_CMD_CRC_ERROR 1 /**< @brief Command CRC error. */
-#define SDC_DATA_CRC_ERROR 2 /**< @brief Data CRC error. */
-#define SDC_DATA_TIMEOUT 4 /**< @brief HW write timeout. */
-#define SDC_COMMAND_TIMEOUT 8 /**< @brief HW read timeout. */
-#define SDC_TX_UNDERRUN 16 /**< @brief TX buffer underrun. */
-#define SDC_RX_OVERRUN 32 /**< @brief RX buffer overrun. */
-#define SDC_STARTBIT_ERROR 64 /**< @brief Start bit missing. */
-#define SDC_OVERFLOW_ERROR 128 /**< @brief Card overflow error. */
-#define SDC_UNHANDLED_ERROR 0xFFFFFFFF
+#define SDC_NO_ERROR 0U
+#define SDC_CMD_CRC_ERROR 1U
+#define SDC_DATA_CRC_ERROR 2U
+#define SDC_DATA_TIMEOUT 4U
+#define SDC_COMMAND_TIMEOUT 8U
+#define SDC_TX_UNDERRUN 16U
+#define SDC_RX_OVERRUN 32U
+#define SDC_STARTBIT_ERROR 64U
+#define SDC_OVERFLOW_ERROR 128U
+#define SDC_UNHANDLED_ERROR 0xFFFFFFFFU
/** @} */
/*===========================================================================*/
@@ -82,7 +71,7 @@
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
-#define SDC_INIT_RETRY 100
+#define SDC_INIT_RETRY 100
#endif
/**
@@ -91,7 +80,7 @@
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
-#define SDC_MMC_SUPPORT FALSE
+#define SDC_MMC_SUPPORT FALSE
#endif
/**
@@ -101,7 +90,21 @@
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
-#define SDC_NICE_WAITING TRUE
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/**
+ * @brief OCR initialization constant for V20 cards.
+ */
+#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
+#define SDC_INIT_OCR_V20 0x50FF8000U
+#endif
+
+/**
+ * @brief OCR initialization constant for non-V20 cards.
+ */
+#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
+#define SDC_INIT_OCR 0x80100000U
#endif
/** @} */
@@ -113,7 +116,24 @@
/* Driver data structures and types. */
/*===========================================================================*/
-#include "sdc_lld.h"
+/**
+ * @brief Type of SDIO bus mode.
+ */
+typedef enum {
+ SDC_MODE_1BIT = 0,
+ SDC_MODE_4BIT,
+ SDC_MODE_8BIT
+} sdcbusmode_t;
+
+/**
+ * @brief Max supported clock.
+ */
+typedef enum {
+ SDC_CLK_25MHz = 0,
+ SDC_CLK_50MHz
+} sdcbusclk_t;
+
+#include "hal_sdc_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -167,23 +187,23 @@ extern "C" {
void sdcObjectInit(SDCDriver *sdcp);
void sdcStart(SDCDriver *sdcp, const SDCConfig *config);
void sdcStop(SDCDriver *sdcp);
- bool_t sdcConnect(SDCDriver *sdcp);
- bool_t sdcDisconnect(SDCDriver *sdcp);
- bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk,
- uint8_t *buffer, uint32_t n);
- bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk,
- const uint8_t *buffer, uint32_t n);
+ bool sdcConnect(SDCDriver *sdcp);
+ bool sdcDisconnect(SDCDriver *sdcp);
+ bool sdcRead(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n);
+ bool sdcWrite(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n);
sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp);
- bool_t sdcSync(SDCDriver *sdcp);
- bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip);
- bool_t sdcErase(SDCDriver *mmcp, uint32_t startblk, uint32_t endblk);
- bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp);
+ bool sdcSync(SDCDriver *sdcp);
+ bool sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip);
+ bool sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk);
+ bool _sdc_wait_for_transfer_state(SDCDriver *sdcp);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_SDC */
+#endif /* HAL_USE_SDC == TRUE */
-#endif /* _SDC_H_ */
+#endif /* HAL_SDC_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/serial.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_serial.h
similarity index 71%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/serial.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_serial.h
index 396be5b3c5..9953447516 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/serial.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_serial.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file serial.h
+ * @file hal_serial.h
* @brief Serial Driver macros and structures.
*
* @addtogroup SERIAL
* @{
*/
-#ifndef _SERIAL_H_
-#define _SERIAL_H_
+#ifndef HAL_SERIAL_H
+#define HAL_SERIAL_H
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -46,11 +35,12 @@
* @name Serial status flags
* @{
*/
-#define SD_PARITY_ERROR 32 /**< @brief Parity error happened. */
-#define SD_FRAMING_ERROR 64 /**< @brief Framing error happened. */
-#define SD_OVERRUN_ERROR 128 /**< @brief Overflow happened. */
-#define SD_NOISE_ERROR 256 /**< @brief Noise on the line. */
-#define SD_BREAK_DETECTED 512 /**< @brief Break detected. */
+#define SD_PARITY_ERROR (eventflags_t)32 /**< @brief Parity. */
+#define SD_FRAMING_ERROR (eventflags_t)64 /**< @brief Framing. */
+#define SD_OVERRUN_ERROR (eventflags_t)128 /**< @brief Overflow. */
+#define SD_NOISE_ERROR (eventflags_t)256 /**< @brief Line noise. */
+#define SD_BREAK_DETECTED (eventflags_t)512 /**< @brief LIN Break. */
+#define SD_QUEUE_FULL_ERROR (eventflags_t)1024 /**< @brief Queue full. */
/** @} */
/*===========================================================================*/
@@ -76,6 +66,8 @@
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
+ * @note This is a global setting and it can be overridden by low level
+ * driver specific settings.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
@@ -86,10 +78,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if !CH_USE_QUEUES && !CH_USE_EVENTS
-#error "Serial Driver requires CH_USE_QUEUES and CH_USE_EVENTS"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -108,7 +96,7 @@ typedef enum {
*/
typedef struct SerialDriver SerialDriver;
-#include "serial_lld.h"
+#include "hal_serial_lld.h"
/**
* @brief @p SerialDriver specific methods.
@@ -146,30 +134,6 @@ struct SerialDriver {
* @name Macro Functions
* @{
*/
-/**
- * @brief Direct output check on a @p SerialDriver.
- * @note This function bypasses the indirect access to the channel and
- * checks directly the output queue. This is faster but cannot
- * be used to check different channels implementations.
- *
- * @deprecated
- *
- * @api
- */
-#define sdPutWouldBlock(sdp) chOQIsFullI(&(sdp)->oqueue)
-
-/**
- * @brief Direct input check on a @p SerialDriver.
- * @note This function bypasses the indirect access to the channel and
- * checks directly the input queue. This is faster but cannot
- * be used to check different channels implementations.
- *
- * @deprecated
- *
- * @api
- */
-#define sdGetWouldBlock(sdp) chIQIsEmptyI(&(sdp)->iqueue)
-
/**
* @brief Direct write to a @p SerialDriver.
* @note This function bypasses the indirect access to the channel and
@@ -180,7 +144,7 @@ struct SerialDriver {
*
* @api
*/
-#define sdPut(sdp, b) chOQPut(&(sdp)->oqueue, b)
+#define sdPut(sdp, b) oqPut(&(sdp)->oqueue, b)
/**
* @brief Direct write to a @p SerialDriver with timeout specification.
@@ -192,7 +156,7 @@ struct SerialDriver {
*
* @api
*/
-#define sdPutTimeout(sdp, b, t) chOQPutTimeout(&(sdp)->oqueue, b, t)
+#define sdPutTimeout(sdp, b, t) oqPutTimeout(&(sdp)->oqueue, b, t)
/**
* @brief Direct read from a @p SerialDriver.
@@ -204,7 +168,7 @@ struct SerialDriver {
*
* @api
*/
-#define sdGet(sdp) chIQGet(&(sdp)->iqueue)
+#define sdGet(sdp) iqGet(&(sdp)->iqueue)
/**
* @brief Direct read from a @p SerialDriver with timeout specification.
@@ -216,7 +180,7 @@ struct SerialDriver {
*
* @api
*/
-#define sdGetTimeout(sdp, t) chIQGetTimeout(&(sdp)->iqueue, t)
+#define sdGetTimeout(sdp, t) iqGetTimeout(&(sdp)->iqueue, t)
/**
* @brief Direct blocking write to a @p SerialDriver.
@@ -229,7 +193,7 @@ struct SerialDriver {
* @api
*/
#define sdWrite(sdp, b, n) \
- chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE)
+ oqWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE)
/**
* @brief Direct blocking write to a @p SerialDriver with timeout
@@ -243,7 +207,7 @@ struct SerialDriver {
* @api
*/
#define sdWriteTimeout(sdp, b, n, t) \
- chOQWriteTimeout(&(sdp)->oqueue, b, n, t)
+ oqWriteTimeout(&(sdp)->oqueue, b, n, t)
/**
* @brief Direct non-blocking write to a @p SerialDriver.
@@ -256,7 +220,7 @@ struct SerialDriver {
* @api
*/
#define sdAsynchronousWrite(sdp, b, n) \
- chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE)
+ oqWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE)
/**
* @brief Direct blocking read from a @p SerialDriver.
@@ -269,7 +233,7 @@ struct SerialDriver {
* @api
*/
#define sdRead(sdp, b, n) \
- chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE)
+ iqReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE)
/**
* @brief Direct blocking read from a @p SerialDriver with timeout
@@ -283,7 +247,7 @@ struct SerialDriver {
* @api
*/
#define sdReadTimeout(sdp, b, n, t) \
- chIQReadTimeout(&(sdp)->iqueue, b, n, t)
+ iqReadTimeout(&(sdp)->iqueue, b, n, t)
/**
* @brief Direct non-blocking read from a @p SerialDriver.
@@ -296,7 +260,7 @@ struct SerialDriver {
* @api
*/
#define sdAsynchronousRead(sdp, b, n) \
- chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE)
+ iqReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE)
/** @} */
/*===========================================================================*/
@@ -307,17 +271,24 @@ struct SerialDriver {
extern "C" {
#endif
void sdInit(void);
+#if !defined(SERIAL_ADVANCED_BUFFERING_SUPPORT) || \
+ (SERIAL_ADVANCED_BUFFERING_SUPPORT == FALSE)
void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify);
+#else
+ void sdObjectInit(SerialDriver *sdp);
+#endif
void sdStart(SerialDriver *sdp, const SerialConfig *config);
void sdStop(SerialDriver *sdp);
void sdIncomingDataI(SerialDriver *sdp, uint8_t b);
msg_t sdRequestDataI(SerialDriver *sdp);
+ bool sdPutWouldBlock(SerialDriver *sdp);
+ bool sdGetWouldBlock(SerialDriver *sdp);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_SERIAL */
+#endif /* HAL_USE_SERIAL == TRUE */
-#endif /* _SERIAL_H_ */
+#endif /* HAL_SERIAL_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/serial_usb.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_serial_usb.h
similarity index 59%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/serial_usb.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_serial_usb.h
index c031a9d9b1..0579a5e56e 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/serial_usb.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_serial_usb.h
@@ -1,87 +1,38 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file serial_usb.h
+ * @file hal_serial_usb.h
* @brief Serial over USB Driver macros and structures.
*
* @addtogroup SERIAL_USB
* @{
*/
-#ifndef _SERIAL_USB_H_
-#define _SERIAL_USB_H_
+#ifndef HAL_SERIAL_USB_H
+#define HAL_SERIAL_USB_H
-#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__)
+#if (HAL_USE_SERIAL_USB == TRUE) || defined(__DOXYGEN__)
+
+#include "hal_usb_cdc.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
-/**
- * @name CDC specific messages.
- * @{
- */
-#define CDC_SEND_ENCAPSULATED_COMMAND 0x00
-#define CDC_GET_ENCAPSULATED_RESPONSE 0x01
-#define CDC_SET_COMM_FEATURE 0x02
-#define CDC_GET_COMM_FEATURE 0x03
-#define CDC_CLEAR_COMM_FEATURE 0x04
-#define CDC_SET_AUX_LINE_STATE 0x10
-#define CDC_SET_HOOK_STATE 0x11
-#define CDC_PULSE_SETUP 0x12
-#define CDC_SEND_PULSE 0x13
-#define CDC_SET_PULSE_TIME 0x14
-#define CDC_RING_AUX_JACK 0x15
-#define CDC_SET_LINE_CODING 0x20
-#define CDC_GET_LINE_CODING 0x21
-#define CDC_SET_CONTROL_LINE_STATE 0x22
-#define CDC_SEND_BREAK 0x23
-#define CDC_SET_RINGER_PARMS 0x30
-#define CDC_GET_RINGER_PARMS 0x31
-#define CDC_SET_OPERATION_PARMS 0x32
-#define CDC_GET_OPERATION_PARMS 0x33
-/** @} */
-
-/**
- * @name Line Control bit definitions.
- * @{
- */
-#define LC_STOP_1 0
-#define LC_STOP_1P5 1
-#define LC_STOP_2 2
-
-#define LC_PARITY_NONE 0
-#define LC_PARITY_ODD 1
-#define LC_PARITY_EVEN 2
-#define LC_PARITY_MARK 3
-#define LC_PARITY_SPACE 4
-/** @} */
-
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -100,31 +51,28 @@
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
+
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
-#if !HAL_USE_USB || !CH_USE_QUEUES || !CH_USE_EVENTS
-#error "Serial over USB Driver requires HAL_USE_USB, CH_USE_QUEUES, "
- "CH_USE_EVENTS"
+#if HAL_USE_USB == FALSE
+#error "Serial over USB Driver requires HAL_USE_USB"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type of Line Coding structure.
- */
-typedef struct {
- uint8_t dwDTERate[4];
- uint8_t bCharFormat;
- uint8_t bParityType;
- uint8_t bDataBits;
-} cdc_linecoding_t;
-
/**
* @brief Driver state machine possible states.
*/
@@ -159,6 +107,8 @@ typedef struct {
usbep_t bulk_out;
/**
* @brief Interrupt IN endpoint used for notifications.
+ * @note If set to zero then the INT endpoint is assumed to be not
+ * present, USB descriptors must be changed accordingly.
*/
usbep_t int_in;
} SerialUSBConfig;
@@ -170,14 +120,16 @@ typedef struct {
_base_asynchronous_channel_data \
/* Driver state.*/ \
sdustate_t state; \
- /* Input queue.*/ \
- InputQueue iqueue; \
+ /* Input buffers queue.*/ \
+ input_buffers_queue_t ibqueue; \
/* Output queue.*/ \
- OutputQueue oqueue; \
+ output_buffers_queue_t obqueue; \
/* Input buffer.*/ \
- uint8_t ib[SERIAL_USB_BUFFERS_SIZE]; \
+ uint8_t ib[BQ_BUFFER_SIZE(SERIAL_USB_BUFFERS_NUMBER, \
+ SERIAL_USB_BUFFERS_SIZE)]; \
/* Output buffer.*/ \
- uint8_t ob[SERIAL_USB_BUFFERS_SIZE]; \
+ uint8_t ob[BQ_BUFFER_SIZE(SERIAL_USB_BUFFERS_NUMBER, \
+ SERIAL_USB_BUFFERS_SIZE)]; \
/* End of the mandatory fields.*/ \
/* Current configuration data.*/ \
const SerialUSBConfig *config;
@@ -222,11 +174,14 @@ struct SerialUSBDriver {
extern "C" {
#endif
void sduInit(void);
- void sduObjectInit(SerialUSBDriver *sdp);
+ void sduObjectInit(SerialUSBDriver *sdup);
void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config);
void sduStop(SerialUSBDriver *sdup);
+ void sduSuspendHookI(SerialUSBDriver *sdup);
+ void sduWakeupHookI(SerialUSBDriver *sdup);
void sduConfigureHookI(SerialUSBDriver *sdup);
- bool_t sduRequestsHook(USBDriver *usbp);
+ bool sduRequestsHook(USBDriver *usbp);
+ void sduSOFHookI(SerialUSBDriver *sdup);
void sduDataTransmitted(USBDriver *usbp, usbep_t ep);
void sduDataReceived(USBDriver *usbp, usbep_t ep);
void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep);
@@ -234,8 +189,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_SERIAL_USB */
+#endif /* HAL_USE_SERIAL_USB == TRUE */
-#endif /* _SERIAL_USB_H_ */
+#endif /* HAL_SERIAL_USB_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/spi.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_spi.h
similarity index 76%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/spi.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_spi.h
index 9b60b2b7a3..e2bfb7db13 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/spi.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_spi.h
@@ -1,42 +1,31 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file spi.h
+ * @file hal_spi.h
* @brief SPI Driver macros and structures.
*
* @addtogroup SPI
* @{
*/
-#ifndef _SPI_H_
-#define _SPI_H_
+#ifndef HAL_SPI_H
+#define HAL_SPI_H
-#if HAL_USE_SPI || defined(__DOXYGEN__)
+#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -71,10 +60,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if SPI_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "SPI_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -90,7 +75,7 @@ typedef enum {
SPI_COMPLETE = 4 /**< Asynchronous operation complete. */
} spistate_t;
-#include "spi_lld.h"
+#include "hal_spi_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -220,29 +205,10 @@ typedef enum {
/** @} */
/**
- * @name Low Level driver helper macros
+ * @name Low level driver helper macros
* @{
*/
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-/**
- * @brief Waits for operation completion.
- * @details This function waits for the driver to complete the current
- * operation.
- * @pre An operation must be running while the function is invoked.
- * @note No more than one thread can wait on a SPI driver using
- * this function.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-#define _spi_wait_s(spip) { \
- chDbgAssert((spip)->thread == NULL, \
- "_spi_wait(), #1", "already waiting"); \
- (spip)->thread = chThdSelf(); \
- chSchGoSleepS(THD_STATE_SUSPENDED); \
-}
-
+#if (SPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
/**
* @brief Wakes up the waiting thread.
*
@@ -251,17 +217,11 @@ typedef enum {
* @notapi
*/
#define _spi_wakeup_isr(spip) { \
- chSysLockFromIsr(); \
- if ((spip)->thread != NULL) { \
- Thread *tp = (spip)->thread; \
- (spip)->thread = NULL; \
- tp->p_u.rdymsg = RDY_OK; \
- chSchReadyI(tp); \
- } \
- chSysUnlockFromIsr(); \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(spip)->thread, MSG_OK); \
+ osalSysUnlockFromISR(); \
}
#else /* !SPI_USE_WAIT */
-#define _spi_wait_s(spip)
#define _spi_wakeup_isr(spip)
#endif /* !SPI_USE_WAIT */
@@ -310,22 +270,22 @@ extern "C" {
const void *txbuf, void *rxbuf);
void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf);
void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf);
-#if SPI_USE_WAIT
+#if SPI_USE_WAIT == TRUE
void spiIgnore(SPIDriver *spip, size_t n);
void spiExchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf);
void spiSend(SPIDriver *spip, size_t n, const void *txbuf);
void spiReceive(SPIDriver *spip, size_t n, void *rxbuf);
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION
+#endif
+#if SPI_USE_MUTUAL_EXCLUSION == TRUE
void spiAcquireBus(SPIDriver *spip);
void spiReleaseBus(SPIDriver *spip);
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#endif
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_SPI */
+#endif /* HAL_USE_SPI == TRUE */
-#endif /* _SPI_H_ */
+#endif /* HAL_SPI_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_st.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_st.h
new file mode 100644
index 0000000000..41cee3b76d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_st.h
@@ -0,0 +1,97 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_st.h
+ * @brief ST Driver macros and structures.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef HAL_ST_H
+#define HAL_ST_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+#include "hal_st_lld.h"
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Returns the time counter value.
+ * @note This functionality is only available in free running mode, the
+ * behaviour in periodic mode is undefined.
+ *
+ * @return The counter value.
+ *
+ * @api
+ */
+#define stGetCounter() st_lld_get_counter()
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @api
+ */
+#define stIsAlarmActive() st_lld_is_alarm_active()
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void stInit(void);
+ void stStartAlarm(systime_t abstime);
+ void stStopAlarm(void);
+ void stSetAlarm(systime_t abstime);
+ systime_t stGetAlarm(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_ST_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chstreams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_streams.h
similarity index 70%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chstreams.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_streams.h
index f581d6d3d4..cc07f391ed 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chstreams.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_streams.h
@@ -1,37 +1,26 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file chstreams.h
+ * @file hal_streams.h
* @brief Data streams.
* @details This header defines abstract interfaces useful to access generic
* data streams in a standardized way.
*
- * @addtogroup data_streams
+ * @addtogroup HAL_STREAMS
* @details This module define an abstract interface for generic data streams.
* Note that no code is present, just abstract interfaces-like
* structures, you should look at the system as to a set of
@@ -43,8 +32,17 @@
* @{
*/
-#ifndef _CHSTREAMS_H_
-#define _CHSTREAMS_H_
+#ifndef HAL_STREAMS_H
+#define HAL_STREAMS_H
+
+/**
+ * @name Streams return codes
+ * @{
+ */
+#define STM_OK MSG_OK
+#define STM_TIMEOUT MSG_TIMEOUT
+#define STM_RESET MSG_RESET
+/** @} */
/**
* @brief BaseSequentialStream specific methods.
@@ -101,7 +99,7 @@ typedef struct {
*
* @api
*/
-#define chSequentialStreamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n))
+#define streamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n))
/**
* @brief Sequential Stream read.
@@ -116,7 +114,7 @@ typedef struct {
*
* @api
*/
-#define chSequentialStreamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n))
+#define streamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n))
/**
* @brief Sequential Stream blocking byte write.
@@ -127,12 +125,12 @@ typedef struct {
* @param[in] b the byte value to be written to the channel
*
* @return The operation status.
- * @retval Q_OK if the operation succeeded.
- * @retval Q_RESET if an end-of-file condition has been met.
+ * @retval STM_OK if the operation succeeded.
+ * @retval STM_RESET if an end-of-file condition has been met.
*
* @api
*/
-#define chSequentialStreamPut(ip, b) ((ip)->vmt->put(ip, b))
+#define streamPut(ip, b) ((ip)->vmt->put(ip, b))
/**
* @brief Sequential Stream blocking byte read.
@@ -142,13 +140,13 @@ typedef struct {
* @param[in] ip pointer to a @p BaseChannel or derived class
*
* @return A byte value from the queue.
- * @retval Q_RESET if an end-of-file condition has been met.
+ * @retval STM_RESET if an end-of-file condition has been met.
*
* @api
*/
-#define chSequentialStreamGet(ip) ((ip)->vmt->get(ip))
+#define streamGet(ip) ((ip)->vmt->get(ip))
/** @} */
-#endif /* _CHSTREAMS_H_ */
+#endif /* HAL_STREAMS_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_uart.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_uart.h
new file mode 100644
index 0000000000..e6fc59684e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_uart.h
@@ -0,0 +1,380 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_uart.h
+ * @brief UART Driver macros and structures.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#ifndef HAL_UART_H
+#define HAL_UART_H
+
+#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name UART status flags
+ * @{
+ */
+#define UART_NO_ERROR 0 /**< @brief No pending conditions. */
+#define UART_PARITY_ERROR 4 /**< @brief Parity error happened. */
+#define UART_FRAMING_ERROR 8 /**< @brief Framing error happened. */
+#define UART_OVERRUN_ERROR 16 /**< @brief Overflow happened. */
+#define UART_NOISE_ERROR 32 /**< @brief Noise on the line. */
+#define UART_BREAK_DETECTED 64 /**< @brief Break detected. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name UART configuration options
+ * @{
+ */
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT FALSE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ UART_UNINIT = 0, /**< Not initialized. */
+ UART_STOP = 1, /**< Stopped. */
+ UART_READY = 2 /**< Ready. */
+} uartstate_t;
+
+/**
+ * @brief Transmitter state machine states.
+ */
+typedef enum {
+ UART_TX_IDLE = 0, /**< Not transmitting. */
+ UART_TX_ACTIVE = 1, /**< Transmitting. */
+ UART_TX_COMPLETE = 2 /**< Buffer complete. */
+} uarttxstate_t;
+
+/**
+ * @brief Receiver state machine states.
+ */
+typedef enum {
+ UART_RX_IDLE = 0, /**< Not receiving. */
+ UART_RX_ACTIVE = 1, /**< Receiving. */
+ UART_RX_COMPLETE = 2 /**< Buffer complete. */
+} uartrxstate_t;
+
+#include "hal_uart_lld.h"
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Low level driver helper macros
+ * @{
+ */
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Wakes up the waiting thread in case of early TX complete.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_wakeup_tx1_isr(uartp) { \
+ if ((uartp)->early == true) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(uartp)->threadtx, MSG_OK); \
+ osalSysUnlockFromISR(); \
+ } \
+}
+#else /* !UART_USE_WAIT */
+#define _uart_wakeup_tx1_isr(uartp)
+#endif /* !UART_USE_WAIT */
+
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Wakes up the waiting thread in case of late TX complete.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_wakeup_tx2_isr(uartp) { \
+ if ((uartp)->early == false) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(uartp)->threadtx, MSG_OK); \
+ osalSysUnlockFromISR(); \
+ } \
+}
+#else /* !UART_USE_WAIT */
+#define _uart_wakeup_tx2_isr(uartp)
+#endif /* !UART_USE_WAIT */
+
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Wakes up the waiting thread in case of RX complete.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_wakeup_rx_complete_isr(uartp) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(uartp)->threadrx, MSG_OK); \
+ osalSysUnlockFromISR(); \
+}
+#else /* !UART_USE_WAIT */
+#define _uart_wakeup_rx_complete_isr(uartp)
+#endif /* !UART_USE_WAIT */
+
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Wakes up the waiting thread in case of RX error.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_wakeup_rx_error_isr(uartp) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(uartp)->threadrx, MSG_RESET); \
+ osalSysUnlockFromISR(); \
+}
+#else /* !UART_USE_WAIT */
+#define _uart_wakeup_rx_error_isr(uartp)
+#endif /* !UART_USE_WAIT */
+
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Wakes up the waiting thread in case of RX timeout.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_wakeup_rx_timeout_isr(uartp) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(uartp)->threadrx, MSG_TIMEOUT); \
+ osalSysUnlockFromISR(); \
+}
+#else /* !UART_USE_WAIT */
+#define _uart_wakeup_rx_timeout_isr(uartp)
+#endif /* !UART_USE_WAIT */
+
+/**
+ * @brief Common ISR code for early TX.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_tx1_isr_code(uartp) { \
+ (uartp)->txstate = UART_TX_COMPLETE; \
+ if ((uartp)->config->txend1_cb != NULL) { \
+ (uartp)->config->txend1_cb(uartp); \
+ } \
+ if ((uartp)->txstate == UART_TX_COMPLETE) { \
+ (uartp)->txstate = UART_TX_IDLE; \
+ } \
+ _uart_wakeup_tx1_isr(uartp); \
+}
+
+/**
+ * @brief Common ISR code for late TX.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_tx2_isr_code(uartp) { \
+ if ((uartp)->config->txend2_cb != NULL) { \
+ (uartp)->config->txend2_cb(uartp); \
+ } \
+ _uart_wakeup_tx2_isr(uartp); \
+}
+
+/**
+ * @brief Common ISR code for RX complete.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_rx_complete_isr_code(uartp) { \
+ (uartp)->rxstate = UART_RX_COMPLETE; \
+ if ((uartp)->config->rxend_cb != NULL) { \
+ (uartp)->config->rxend_cb(uartp); \
+ } \
+ if ((uartp)->rxstate == UART_RX_COMPLETE) { \
+ (uartp)->rxstate = UART_RX_IDLE; \
+ uart_enter_rx_idle_loop(uartp); \
+ } \
+ _uart_wakeup_rx_complete_isr(uartp); \
+}
+
+/**
+ * @brief Common ISR code for RX error.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] errors mask of errors to be reported
+ *
+ * @notapi
+ */
+#define _uart_rx_error_isr_code(uartp, errors) { \
+ if ((uartp)->config->rxerr_cb != NULL) { \
+ (uartp)->config->rxerr_cb(uartp, errors); \
+ } \
+ _uart_wakeup_rx_error_isr(uartp); \
+}
+
+/**
+ * @brief Common ISR code for RX on idle.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_rx_idle_code(uartp) { \
+ if ((uartp)->config->rxchar_cb != NULL) \
+ (uartp)->config->rxchar_cb(uartp, (uartp)->rxbuf); \
+}
+
+/**
+ * @brief Timeout ISR code for receiver.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+#define _uart_timeout_isr_code(uartp) { \
+ if ((uartp)->config->timeout_cb != NULL) { \
+ (uartp)->config->timeout_cb(uartp); \
+ } \
+ _uart_wakeup_rx_timeout_isr(uartp); \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void uartInit(void);
+ void uartObjectInit(UARTDriver *uartp);
+ void uartStart(UARTDriver *uartp, const UARTConfig *config);
+ void uartStop(UARTDriver *uartp);
+ void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf);
+ void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf);
+ size_t uartStopSend(UARTDriver *uartp);
+ size_t uartStopSendI(UARTDriver *uartp);
+ void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf);
+ void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf);
+ size_t uartStopReceive(UARTDriver *uartp);
+ size_t uartStopReceiveI(UARTDriver *uartp);
+#if UART_USE_WAIT == TRUE
+ msg_t uartSendTimeout(UARTDriver *uartp, size_t *np,
+ const void *txbuf, systime_t timeout);
+ msg_t uartSendFullTimeout(UARTDriver *uartp, size_t *np,
+ const void *txbuf, systime_t timeout);
+ msg_t uartReceiveTimeout(UARTDriver *uartp, size_t *np,
+ void *rxbuf, systime_t timeout);
+#endif
+#if UART_USE_MUTUAL_EXCLUSION == TRUE
+ void uartAcquireBus(UARTDriver *uartp);
+ void uartReleaseBus(UARTDriver *uartp);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_UART == TRUE */
+
+#endif /* HAL_UART_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/usb.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_usb.h
similarity index 63%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/usb.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_usb.h
index 9ccb199723..a450334d41 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/usb.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_usb.h
@@ -1,86 +1,78 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file usb.h
+ * @file hal_usb.h
* @brief USB Driver macros and structures.
*
* @addtogroup USB
* @{
*/
-#ifndef _USB_H_
-#define _USB_H_
+#ifndef HAL_USB_H
+#define HAL_USB_H
-#if HAL_USE_USB || defined(__DOXYGEN__)
+#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
-#define USB_RTYPE_DIR_MASK 0x80
-#define USB_RTYPE_DIR_HOST2DEV 0x00
-#define USB_RTYPE_DIR_DEV2HOST 0x80
-#define USB_RTYPE_TYPE_MASK 0x60
-#define USB_RTYPE_TYPE_STD 0x00
-#define USB_RTYPE_TYPE_CLASS 0x20
-#define USB_RTYPE_TYPE_VENDOR 0x40
-#define USB_RTYPE_TYPE_RESERVED 0x60
-#define USB_RTYPE_RECIPIENT_MASK 0x1F
-#define USB_RTYPE_RECIPIENT_DEVICE 0x00
-#define USB_RTYPE_RECIPIENT_INTERFACE 0x01
-#define USB_RTYPE_RECIPIENT_ENDPOINT 0x02
-#define USB_RTYPE_RECIPIENT_OTHER 0x03
-
-#define USB_REQ_GET_STATUS 0
-#define USB_REQ_CLEAR_FEATURE 1
-#define USB_REQ_SET_FEATURE 3
-#define USB_REQ_SET_ADDRESS 5
-#define USB_REQ_GET_DESCRIPTOR 6
-#define USB_REQ_SET_DESCRIPTOR 7
-#define USB_REQ_GET_CONFIGURATION 8
-#define USB_REQ_SET_CONFIGURATION 9
-#define USB_REQ_GET_INTERFACE 10
-#define USB_REQ_SET_INTERFACE 11
-#define USB_REQ_SYNCH_FRAME 12
-
-#define USB_DESCRIPTOR_DEVICE 1
-#define USB_DESCRIPTOR_CONFIGURATION 2
-#define USB_DESCRIPTOR_STRING 3
-#define USB_DESCRIPTOR_INTERFACE 4
-#define USB_DESCRIPTOR_ENDPOINT 5
-#define USB_DESCRIPTOR_DEVICE_QUALIFIER 6
-#define USB_DESCRIPTOR_OTHER_SPEED_CFG 7
-#define USB_DESCRIPTOR_INTERFACE_POWER 8
-#define USB_DESCRIPTOR_INTERFACE_ASSOCIATION 11
-
-#define USB_FEATURE_ENDPOINT_HALT 0
-#define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1
-#define USB_FEATURE_TEST_MODE 2
+#define USB_ENDPOINT_OUT(ep) (ep)
+#define USB_ENDPOINT_IN(ep) ((ep) | 0x80U)
+
+#define USB_RTYPE_DIR_MASK 0x80U
+#define USB_RTYPE_DIR_HOST2DEV 0x00U
+#define USB_RTYPE_DIR_DEV2HOST 0x80U
+#define USB_RTYPE_TYPE_MASK 0x60U
+#define USB_RTYPE_TYPE_STD 0x00U
+#define USB_RTYPE_TYPE_CLASS 0x20U
+#define USB_RTYPE_TYPE_VENDOR 0x40U
+#define USB_RTYPE_TYPE_RESERVED 0x60U
+#define USB_RTYPE_RECIPIENT_MASK 0x1FU
+#define USB_RTYPE_RECIPIENT_DEVICE 0x00U
+#define USB_RTYPE_RECIPIENT_INTERFACE 0x01U
+#define USB_RTYPE_RECIPIENT_ENDPOINT 0x02U
+#define USB_RTYPE_RECIPIENT_OTHER 0x03U
+
+#define USB_REQ_GET_STATUS 0U
+#define USB_REQ_CLEAR_FEATURE 1U
+#define USB_REQ_SET_FEATURE 3U
+#define USB_REQ_SET_ADDRESS 5U
+#define USB_REQ_GET_DESCRIPTOR 6U
+#define USB_REQ_SET_DESCRIPTOR 7U
+#define USB_REQ_GET_CONFIGURATION 8U
+#define USB_REQ_SET_CONFIGURATION 9U
+#define USB_REQ_GET_INTERFACE 10U
+#define USB_REQ_SET_INTERFACE 11U
+#define USB_REQ_SYNCH_FRAME 12U
+
+#define USB_DESCRIPTOR_DEVICE 1U
+#define USB_DESCRIPTOR_CONFIGURATION 2U
+#define USB_DESCRIPTOR_STRING 3U
+#define USB_DESCRIPTOR_INTERFACE 4U
+#define USB_DESCRIPTOR_ENDPOINT 5U
+#define USB_DESCRIPTOR_DEVICE_QUALIFIER 6U
+#define USB_DESCRIPTOR_OTHER_SPEED_CFG 7U
+#define USB_DESCRIPTOR_INTERFACE_POWER 8U
+#define USB_DESCRIPTOR_INTERFACE_ASSOCIATION 11U
+
+#define USB_FEATURE_ENDPOINT_HALT 0U
+#define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1U
+#define USB_FEATURE_TEST_MODE 2U
#define USB_EARLY_SET_ADDRESS 0
#define USB_LATE_SET_ADDRESS 1
@@ -109,16 +101,21 @@
* @brief Helper macro for word values into descriptor strings.
*/
#define USB_DESC_WORD(w) \
- (uint8_t)((w) & 255), \
- (uint8_t)(((w) >> 8) & 255)
+ (uint8_t)((w) & 255U), \
+ (uint8_t)(((w) >> 8) & 255U)
/**
* @brief Helper macro for BCD values into descriptor strings.
*/
#define USB_DESC_BCD(bcd) \
- (uint8_t)((bcd) & 255), \
+ (uint8_t)((bcd) & 255U), \
(uint8_t)(((bcd) >> 8) & 255)
+/*
+ * @define Device Descriptor size.
+ */
+#define USB_DESC_DEVICE_SIZE 18U
+
/**
* @brief Device Descriptor helper macro.
*/
@@ -126,7 +123,7 @@
bDeviceProtocol, bMaxPacketSize, idVendor, \
idProduct, bcdDevice, iManufacturer, \
iProduct, iSerialNumber, bNumConfigurations) \
- USB_DESC_BYTE(18), \
+ USB_DESC_BYTE(USB_DESC_DEVICE_SIZE), \
USB_DESC_BYTE(USB_DESCRIPTOR_DEVICE), \
USB_DESC_BCD(bcdUSB), \
USB_DESC_BYTE(bDeviceClass), \
@@ -141,13 +138,18 @@
USB_DESC_INDEX(iSerialNumber), \
USB_DESC_BYTE(bNumConfigurations)
+/**
+ * @brief Configuration Descriptor size.
+ */
+#define USB_DESC_CONFIGURATION_SIZE 9U
+
/**
* @brief Configuration Descriptor helper macro.
*/
#define USB_DESC_CONFIGURATION(wTotalLength, bNumInterfaces, \
bConfigurationValue, iConfiguration, \
bmAttributes, bMaxPower) \
- USB_DESC_BYTE(9), \
+ USB_DESC_BYTE(USB_DESC_CONFIGURATION_SIZE), \
USB_DESC_BYTE(USB_DESCRIPTOR_CONFIGURATION), \
USB_DESC_WORD(wTotalLength), \
USB_DESC_BYTE(bNumInterfaces), \
@@ -156,6 +158,11 @@
USB_DESC_BYTE(bmAttributes), \
USB_DESC_BYTE(bMaxPower)
+/**
+ * @brief Interface Descriptor size.
+ */
+#define USB_DESC_INTERFACE_SIZE 9U
+
/**
* @brief Interface Descriptor helper macro.
*/
@@ -163,7 +170,7 @@
bNumEndpoints, bInterfaceClass, \
bInterfaceSubClass, bInterfaceProtocol, \
iInterface) \
- USB_DESC_BYTE(9), \
+ USB_DESC_BYTE(USB_DESC_INTERFACE_SIZE), \
USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE), \
USB_DESC_BYTE(bInterfaceNumber), \
USB_DESC_BYTE(bAlternateSetting), \
@@ -173,6 +180,11 @@
USB_DESC_BYTE(bInterfaceProtocol), \
USB_DESC_INDEX(iInterface)
+/**
+ * @brief Interface Association Descriptor size.
+ */
+#define USB_DESC_INTERFACE_ASSOCIATION_SIZE 8U
+
/**
* @brief Interface Association Descriptor helper macro.
*/
@@ -180,7 +192,7 @@
bInterfaceCount, bFunctionClass, \
bFunctionSubClass, bFunctionProcotol, \
iInterface) \
- USB_DESC_BYTE(8), \
+ USB_DESC_BYTE(USB_DESC_INTERFACE_ASSOCIATION_SIZE), \
USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE_ASSOCIATION), \
USB_DESC_BYTE(bFirstInterface), \
USB_DESC_BYTE(bInterfaceCount), \
@@ -189,12 +201,17 @@
USB_DESC_BYTE(bFunctionProcotol), \
USB_DESC_INDEX(iInterface)
+/**
+ * @brief Endpoint Descriptor size.
+ */
+#define USB_DESC_ENDPOINT_SIZE 7U
+
/**
* @brief Endpoint Descriptor helper macro.
*/
#define USB_DESC_ENDPOINT(bEndpointAddress, bmAttributes, wMaxPacketSize, \
bInterval) \
- USB_DESC_BYTE(7), \
+ USB_DESC_BYTE(USB_DESC_ENDPOINT_SIZE), \
USB_DESC_BYTE(USB_DESCRIPTOR_ENDPOINT), \
USB_DESC_BYTE(bEndpointAddress), \
USB_DESC_BYTE(bmAttributes), \
@@ -206,19 +223,28 @@
* @name Endpoint types and settings
* @{
*/
-#define USB_EP_MODE_TYPE 0x0003 /**< Endpoint type mask. */
-#define USB_EP_MODE_TYPE_CTRL 0x0000 /**< Control endpoint. */
-#define USB_EP_MODE_TYPE_ISOC 0x0001 /**< Isochronous endpoint. */
-#define USB_EP_MODE_TYPE_BULK 0x0002 /**< Bulk endpoint. */
-#define USB_EP_MODE_TYPE_INTR 0x0003 /**< Interrupt endpoint. */
-#define USB_EP_MODE_LINEAR_BUFFER 0x0000 /**< Linear buffer mode. */
-#define USB_EP_MODE_QUEUE_BUFFER 0x0010 /**< Queue buffer mode. */
+#define USB_EP_MODE_TYPE 0x0003U /**< Endpoint type mask. */
+#define USB_EP_MODE_TYPE_CTRL 0x0000U /**< Control endpoint. */
+#define USB_EP_MODE_TYPE_ISOC 0x0001U /**< Isochronous endpoint. */
+#define USB_EP_MODE_TYPE_BULK 0x0002U /**< Bulk endpoint. */
+#define USB_EP_MODE_TYPE_INTR 0x0003U /**< Interrupt endpoint. */
/** @} */
+#define USB_IN_STATE 0x08U
+#define USB_OUT_STATE 0x10U
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -241,11 +267,12 @@ typedef uint8_t usbep_t;
* @brief Type of a driver state machine possible states.
*/
typedef enum {
- USB_UNINIT = 0, /**< Not initialized. */
- USB_STOP = 1, /**< Stopped. */
- USB_READY = 2, /**< Ready, after bus reset. */
- USB_SELECTED = 3, /**< Address assigned. */
- USB_ACTIVE = 4 /**< Active, configuration selected.*/
+ USB_UNINIT = 0, /**< Not initialized. */
+ USB_STOP = 1, /**< Stopped. */
+ USB_READY = 2, /**< Ready, after bus reset. */
+ USB_SELECTED = 3, /**< Address assigned. */
+ USB_ACTIVE = 4, /**< Active, configuration selected.*/
+ USB_SUSPENDED = 5 /**< Suspended, low power mode. */
} usbstate_t;
/**
@@ -261,13 +288,13 @@ typedef enum {
* @brief Type of an endpoint zero state machine states.
*/
typedef enum {
- USB_EP0_WAITING_SETUP, /**< Waiting for SETUP data. */
- USB_EP0_TX, /**< Transmitting. */
- USB_EP0_WAITING_TX0, /**< Waiting transmit 0. */
- USB_EP0_WAITING_STS, /**< Waiting status. */
- USB_EP0_RX, /**< Receiving. */
- USB_EP0_SENDING_STS, /**< Sending status. */
- USB_EP0_ERROR /**< Error, EP0 stalled. */
+ USB_EP0_STP_WAITING = 0U, /**< Waiting for SETUP data.*/
+ USB_EP0_IN_TX = USB_IN_STATE | 1U, /**< Transmitting. */
+ USB_EP0_IN_WAITING_TX0 = USB_IN_STATE | 2U, /**< Waiting transmit 0. */
+ USB_EP0_IN_SENDING_STS = USB_IN_STATE | 3U, /**< Sending status. */
+ USB_EP0_OUT_WAITING_STS = USB_OUT_STATE | 4U, /**< Waiting status. */
+ USB_EP0_OUT_RX = USB_OUT_STATE | 5U, /**< Receiving. */
+ USB_EP0_ERROR = 6U /**< Error, EP0 stalled. */
} usbep0state_t;
/**
@@ -277,9 +304,10 @@ typedef enum {
USB_EVENT_RESET = 0, /**< Driver has been reset by host. */
USB_EVENT_ADDRESS = 1, /**< Address assigned. */
USB_EVENT_CONFIGURED = 2, /**< Configuration selected. */
- USB_EVENT_SUSPEND = 3, /**< Entering suspend mode. */
- USB_EVENT_WAKEUP = 4, /**< Leaving suspend mode. */
- USB_EVENT_STALLED = 5 /**< Endpoint 0 error, stalled. */
+ USB_EVENT_UNCONFIGURED = 3, /**< Configuration removed. */
+ USB_EVENT_SUSPEND = 4, /**< Entering suspend mode. */
+ USB_EVENT_WAKEUP = 5, /**< Leaving suspend mode. */
+ USB_EVENT_STALLED = 6 /**< Endpoint 0 error, stalled. */
} usbevent_t;
/**
@@ -329,10 +357,10 @@ typedef void (*usbeventcb_t)(USBDriver *usbp, usbevent_t event);
* @param[in] usbp pointer to the @p USBDriver object triggering the
* callback
* @return The request handling exit code.
- * @retval FALSE Request not recognized by the handler.
- * @retval TRUE Request handled.
+ * @retval false Request not recognized by the handler.
+ * @retval true Request handled.
*/
-typedef bool_t (*usbreqhandler_t)(USBDriver *usbp);
+typedef bool (*usbreqhandler_t)(USBDriver *usbp);
/**
* @brief Type of an USB descriptor-retrieving callback.
@@ -342,7 +370,7 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
uint8_t dindex,
uint16_t lang);
-#include "usb_lld.h"
+#include "hal_usb_lld.h"
/*===========================================================================*/
/* Driver macros. */
@@ -362,15 +390,6 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
*/
#define usbGetDriverStateI(usbp) ((usbp)->state)
-/**
- * @brief Fetches a 16 bits word value from an USB message.
- *
- * @param[in] p pointer to the 16 bits word
- *
- * @notapi
- */
-#define usbFetchWord(p) ((uint16_t)*(p) | ((uint16_t)*((p) + 1) << 8))
-
/**
* @brief Connects the USB device.
*
@@ -395,9 +414,9 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
* @param[in] usbp pointer to the @p USBDriver object
* @return The current frame number.
*
- * @api
+ * @xclass
*/
-#define usbGetFrameNumber(usbp) usb_lld_get_frame_number(usbp)
+#define usbGetFrameNumberX(usbp) usb_lld_get_frame_number(usbp)
/**
* @brief Returns the status of an IN endpoint.
@@ -405,12 +424,13 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
* @return The operation status.
- * @retval FALSE Endpoint ready.
- * @retval TRUE Endpoint transmitting.
+ * @retval false Endpoint ready.
+ * @retval true Endpoint transmitting.
*
* @iclass
*/
-#define usbGetTransmitStatusI(usbp, ep) ((usbp)->transmitting & (1 << (ep)))
+#define usbGetTransmitStatusI(usbp, ep) \
+ (((usbp)->transmitting & (uint16_t)((unsigned)1U << (unsigned)(ep))) != 0U)
/**
* @brief Returns the status of an OUT endpoint.
@@ -418,12 +438,13 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
* @return The operation status.
- * @retval FALSE Endpoint ready.
- * @retval TRUE Endpoint receiving.
+ * @retval false Endpoint ready.
+ * @retval true Endpoint receiving.
*
* @iclass
*/
-#define usbGetReceiveStatusI(usbp, ep) ((usbp)->receiving & (1 << (ep)))
+#define usbGetReceiveStatusI(usbp, ep) \
+ (((usbp)->receiving & (uint16_t)((unsigned)1U << (unsigned)(ep))) != 0U)
/**
* @brief Returns the exact size of a receive transaction.
@@ -435,9 +456,9 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
* @param[in] ep endpoint number
* @return Received data size.
*
- * @iclass
+ * @xclass
*/
-#define usbGetReceiveTransactionSizeI(usbp, ep) \
+#define usbGetReceiveTransactionSizeX(usbp, ep) \
usb_lld_get_transaction_size(usbp, ep)
/**
@@ -450,7 +471,7 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
* @param[in] n number of bytes to be transferred
* @param[in] endcb callback to be invoked after the transfer or @p NULL
*
- * @api
+ * @special
*/
#define usbSetupTransfer(usbp, buf, n, endcb) { \
(usbp)->ep0next = (buf); \
@@ -476,7 +497,7 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
/** @} */
/**
- * @name Low Level driver helper macros
+ * @name Low level driver helper macros
* @{
*/
/**
@@ -488,8 +509,9 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
* @notapi
*/
#define _usb_isr_invoke_event_cb(usbp, evt) { \
- if (((usbp)->config->event_cb) != NULL) \
+ if (((usbp)->config->event_cb) != NULL) { \
(usbp)->config->event_cb(usbp, evt); \
+ } \
}
/**
@@ -500,8 +522,9 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
* @notapi
*/
#define _usb_isr_invoke_sof_cb(usbp) { \
- if (((usbp)->config->sof_cb) != NULL) \
+ if (((usbp)->config->sof_cb) != NULL) { \
(usbp)->config->sof_cb(usbp); \
+ } \
}
/**
@@ -524,10 +547,24 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
*
* @notapi
*/
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
#define _usb_isr_invoke_in_cb(usbp, ep) { \
(usbp)->transmitting &= ~(1 << (ep)); \
- (usbp)->epc[ep]->in_cb(usbp, ep); \
+ if ((usbp)->epc[ep]->in_cb != NULL) { \
+ (usbp)->epc[ep]->in_cb(usbp, ep); \
+ } \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(usbp)->epc[ep]->in_state->thread, MSG_OK); \
+ osalSysUnlockFromISR(); \
}
+#else
+#define _usb_isr_invoke_in_cb(usbp, ep) { \
+ (usbp)->transmitting &= ~(1 << (ep)); \
+ if ((usbp)->epc[ep]->in_cb != NULL) { \
+ (usbp)->epc[ep]->in_cb(usbp, ep); \
+ } \
+}
+#endif
/**
* @brief Common ISR code, OUT endpoint event.
@@ -537,10 +574,25 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
*
* @notapi
*/
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
#define _usb_isr_invoke_out_cb(usbp, ep) { \
(usbp)->receiving &= ~(1 << (ep)); \
- (usbp)->epc[ep]->out_cb(usbp, ep); \
+ if ((usbp)->epc[ep]->out_cb != NULL) { \
+ (usbp)->epc[ep]->out_cb(usbp, ep); \
+ } \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(usbp)->epc[ep]->out_state->thread, \
+ usbGetReceiveTransactionSizeX(usbp, ep)); \
+ osalSysUnlockFromISR(); \
}
+#else
+#define _usb_isr_invoke_out_cb(usbp, ep) { \
+ (usbp)->receiving &= ~(1 << (ep)); \
+ if ((usbp)->epc[ep]->out_cb != NULL) { \
+ (usbp)->epc[ep]->out_cb(usbp, ep); \
+ } \
+}
+#endif
/** @} */
/*===========================================================================*/
@@ -558,19 +610,20 @@ extern "C" {
const USBEndpointConfig *epcp);
void usbDisableEndpointsI(USBDriver *usbp);
void usbReadSetupI(USBDriver *usbp, usbep_t ep, uint8_t *buf);
- void usbPrepareReceive(USBDriver *usbp, usbep_t ep,
- uint8_t *buf, size_t n);
- void usbPrepareTransmit(USBDriver *usbp, usbep_t ep,
- const uint8_t *buf, size_t n);
- void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep,
- InputQueue *iqp, size_t n);
- void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep,
- OutputQueue *oqp, size_t n);
- bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep);
- bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep);
- bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep);
- bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep);
+ void usbStartReceiveI(USBDriver *usbp, usbep_t ep,
+ uint8_t *buf, size_t n);
+ void usbStartTransmitI(USBDriver *usbp, usbep_t ep,
+ const uint8_t *buf, size_t n);
+#if USB_USE_WAIT == TRUE
+ msg_t usbReceive(USBDriver *usbp, usbep_t ep, uint8_t *buf, size_t n);
+ msg_t usbTransmit(USBDriver *usbp, usbep_t ep, const uint8_t *buf, size_t n);
+#endif
+ bool usbStallReceiveI(USBDriver *usbp, usbep_t ep);
+ bool usbStallTransmitI(USBDriver *usbp, usbep_t ep);
+ void usbWakeupHost(USBDriver *usbp);
void _usb_reset(USBDriver *usbp);
+ void _usb_suspend(USBDriver *usbp);
+ void _usb_wakeup(USBDriver *usbp);
void _usb_ep0setup(USBDriver *usbp, usbep_t ep);
void _usb_ep0in(USBDriver *usbp, usbep_t ep);
void _usb_ep0out(USBDriver *usbp, usbep_t ep);
@@ -578,8 +631,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_USB */
+#endif /* HAL_USE_USB == TRUE */
-#endif /* _USB_H_ */
+#endif /* HAL_USB_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_usb_cdc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_usb_cdc.h
new file mode 100644
index 0000000000..ce2458f0e8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_usb_cdc.h
@@ -0,0 +1,136 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_usb_cdc.h
+ * @brief USB CDC macros and structures.
+ *
+ * @addtogroup USB_CDC
+ * @{
+ */
+
+#ifndef USB_CDC_H
+#define USB_CDC_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name CDC specific messages.
+ * @{
+ */
+#define CDC_SEND_ENCAPSULATED_COMMAND 0x00U
+#define CDC_GET_ENCAPSULATED_RESPONSE 0x01U
+#define CDC_SET_COMM_FEATURE 0x02U
+#define CDC_GET_COMM_FEATURE 0x03U
+#define CDC_CLEAR_COMM_FEATURE 0x04U
+#define CDC_SET_AUX_LINE_STATE 0x10U
+#define CDC_SET_HOOK_STATE 0x11U
+#define CDC_PULSE_SETUP 0x12U
+#define CDC_SEND_PULSE 0x13U
+#define CDC_SET_PULSE_TIME 0x14U
+#define CDC_RING_AUX_JACK 0x15U
+#define CDC_SET_LINE_CODING 0x20U
+#define CDC_GET_LINE_CODING 0x21U
+#define CDC_SET_CONTROL_LINE_STATE 0x22U
+#define CDC_SEND_BREAK 0x23U
+#define CDC_SET_RINGER_PARMS 0x30U
+#define CDC_GET_RINGER_PARMS 0x31U
+#define CDC_SET_OPERATION_PARMS 0x32U
+#define CDC_GET_OPERATION_PARMS 0x33U
+/** @} */
+
+/**
+ * @name CDC classes
+ * @{
+ */
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U
+#define CDC_DATA_INTERFACE_CLASS 0x0AU
+/** @} */
+
+/**
+ * @name CDC subclasses
+ * @{
+ */
+#define CDC_ABSTRACT_CONTROL_MODEL 0x02U
+/** @} */
+
+/**
+ * @name CDC descriptors
+ * @{
+ */
+#define CDC_CS_INTERFACE 0x24U
+/** @} */
+
+/**
+ * @name CDC subdescriptors
+ * @{
+ */
+#define CDC_HEADER 0x00U
+#define CDC_CALL_MANAGEMENT 0x01U
+#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02U
+#define CDC_UNION 0x06U
+/** @} */
+
+/**
+ * @name Line Control bit definitions.
+ * @{
+ */
+#define LC_STOP_1 0U
+#define LC_STOP_1P5 1U
+#define LC_STOP_2 2U
+
+#define LC_PARITY_NONE 0U
+#define LC_PARITY_ODD 1U
+#define LC_PARITY_EVEN 2U
+#define LC_PARITY_MARK 3U
+#define LC_PARITY_SPACE 4U
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of Line Coding structure.
+ */
+typedef struct {
+ uint8_t dwDTERate[4];
+ uint8_t bCharFormat;
+ uint8_t bParityType;
+ uint8_t bDataBits;
+} cdc_linecoding_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#endif /* USB_CDC_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_wdg.h
similarity index 73%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_wdg.h
index 11496a37ea..61beecd7f6 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/hal_wdg.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file xxx.h
- * @brief XXX Driver macros and structures.
+ * @file hal_wdg.h
+ * @brief WDG Driver macros and structures.
*
- * @addtogroup XXX
+ * @addtogroup WDG
* @{
*/
-#ifndef _XXX_H_
-#define _XXX_H_
+#ifndef HAL_WDG_H
+#define HAL_WDG_H
-#if HAL_USE_XXX || defined(__DOXYGEN__)
+#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -47,22 +47,26 @@
* @brief Driver state machine possible states.
*/
typedef enum {
- XXX_UNINIT = 0, /**< Not initialized. */
- XXX_STOP = 1, /**< Stopped. */
- XXX_READY = 2, /**< Ready. */
-} xxxstate_t;
+ WDG_UNINIT = 0, /**< Not initialized. */
+ WDG_STOP = 1, /**< Stopped. */
+ WDG_READY = 2 /**< Ready. */
+} wdgstate_t;
-/**
- * @brief Type of a structure representing a XXX driver.
- */
-typedef struct XXXDriver XXXDriver;
-
-#include "xxx_lld.h"
+#include "hal_wdg_lld.h"
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
+/**
+ * @brief Resets WDG's counter.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @iclass
+ */
+#define wdgResetI(wdgp) wdg_lld_reset(wdgp)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
@@ -70,16 +74,16 @@ typedef struct XXXDriver XXXDriver;
#ifdef __cplusplus
extern "C" {
#endif
- void xxxInit(void);
- void xxxObjectInit(XXXDriver *xxxp);
- void xxxStart(XXXDriver *xxxp, const XXXConfig *config);
- void xxxStop(XXXDriver *xxxp);
+ void wdgInit(void);
+ void wdgStart(WDGDriver *wdgp, const WDGConfig * config);
+ void wdgStop(WDGDriver *wdgp);
+ void wdgReset(WDGDriver *wdgp);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_XXX */
+#endif /* HAL_USE_WDG == TRUE */
-#endif /* _XXX_H_ */
+#endif /* HAL_WDG_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mmcsd.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mmcsd.h
deleted file mode 100644
index 866267babb..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/mmcsd.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file mmcsd.h
- * @brief MMC/SD cards common header.
- * @details This header defines an abstract interface useful to access MMC/SD
- * I/O block devices in a standardized way.
- *
- * @addtogroup MMCSD
- * @{
- */
-
-#ifndef _MMCSD_H_
-#define _MMCSD_H_
-
-#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Fixed block size for MMC/SD block devices.
- */
-#define MMCSD_BLOCK_SIZE 512
-
-/**
- * @brief Mask of error bits in R1 responses.
- */
-#define MMCSD_R1_ERROR_MASK 0xFDFFE008
-
-/**
- * @brief Fixed pattern for CMD8.
- */
-#define MMCSD_CMD8_PATTERN 0x000001AA
-
-/**
- * @name SD/MMC status conditions
- * @{
- */
-#define MMCSD_STS_IDLE 0
-#define MMCSD_STS_READY 1
-#define MMCSD_STS_IDENT 2
-#define MMCSD_STS_STBY 3
-#define MMCSD_STS_TRAN 4
-#define MMCSD_STS_DATA 5
-#define MMCSD_STS_RCV 6
-#define MMCSD_STS_PRG 7
-#define MMCSD_STS_DIS 8
-/** @} */
-
-/**
- * @name SD/MMC commands
- * @{
- */
-#define MMCSD_CMD_GO_IDLE_STATE 0
-#define MMCSD_CMD_INIT 1
-#define MMCSD_CMD_ALL_SEND_CID 2
-#define MMCSD_CMD_SEND_RELATIVE_ADDR 3
-#define MMCSD_CMD_SET_BUS_WIDTH 6
-#define MMCSD_CMD_SEL_DESEL_CARD 7
-#define MMCSD_CMD_SEND_IF_COND 8
-#define MMCSD_CMD_SEND_CSD 9
-#define MMCSD_CMD_SEND_CID 10
-#define MMCSD_CMD_STOP_TRANSMISSION 12
-#define MMCSD_CMD_SEND_STATUS 13
-#define MMCSD_CMD_SET_BLOCKLEN 16
-#define MMCSD_CMD_READ_SINGLE_BLOCK 17
-#define MMCSD_CMD_READ_MULTIPLE_BLOCK 18
-#define MMCSD_CMD_SET_BLOCK_COUNT 23
-#define MMCSD_CMD_WRITE_BLOCK 24
-#define MMCSD_CMD_WRITE_MULTIPLE_BLOCK 25
-#define MMCSD_CMD_ERASE_RW_BLK_START 32
-#define MMCSD_CMD_ERASE_RW_BLK_END 33
-#define MMCSD_CMD_ERASE 38
-#define MMCSD_CMD_APP_OP_COND 41
-#define MMCSD_CMD_LOCK_UNLOCK 42
-#define MMCSD_CMD_APP_CMD 55
-#define MMCSD_CMD_READ_OCR 58
-/** @} */
-
-/**
- * @name CSD record offsets
- */
-/**
- * @brief Slice position of values in CSD register.
- */
-/* CSD version 2.0 */
-#define MMCSD_CSD_20_CRC_SLICE 7,1
-#define MMCSD_CSD_20_FILE_FORMAT_SLICE 11,10
-#define MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE 12,12
-#define MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE 13,13
-#define MMCSD_CSD_20_COPY_SLICE 14,14
-#define MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE 15,15
-#define MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE 21,21
-#define MMCSD_CSD_20_WRITE_BL_LEN_SLICE 25,12
-#define MMCSD_CSD_20_R2W_FACTOR_SLICE 28,26
-#define MMCSD_CSD_20_WP_GRP_ENABLE_SLICE 31,31
-#define MMCSD_CSD_20_WP_GRP_SIZE_SLICE 38,32
-#define MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE 45,39
-#define MMCSD_CSD_20_ERASE_BLK_EN_SLICE 46,46
-#define MMCSD_CSD_20_C_SIZE_SLICE 69,48
-#define MMCSD_CSD_20_DSR_IMP_SLICE 76,76
-#define MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE 77,77
-#define MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE 78,78
-#define MMCSD_CSD_20_READ_BL_PARTIAL_SLICE 79,79
-#define MMCSD_CSD_20_READ_BL_LEN_SLICE 83,80
-#define MMCSD_CSD_20_CCC_SLICE 95,84
-#define MMCSD_CSD_20_TRANS_SPEED_SLICE 103,96
-#define MMCSD_CSD_20_NSAC_SLICE 111,104
-#define MMCSD_CSD_20_TAAC_SLICE 119,112
-#define MMCSD_CSD_20_STRUCTURE_SLICE 127,126
-
-/* CSD version 1.0 */
-#define MMCSD_CSD_10_CRC_SLICE MMCSD_CSD_20_CRC_SLICE
-#define MMCSD_CSD_10_FILE_FORMAT_SLICE MMCSD_CSD_20_FILE_FORMAT_SLICE
-#define MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE
-#define MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE
-#define MMCSD_CSD_10_COPY_SLICE MMCSD_CSD_20_COPY_SLICE
-#define MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE
-#define MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE
-#define MMCSD_CSD_10_WRITE_BL_LEN_SLICE MMCSD_CSD_20_WRITE_BL_LEN_SLICE
-#define MMCSD_CSD_10_R2W_FACTOR_SLICE MMCSD_CSD_20_R2W_FACTOR_SLICE
-#define MMCSD_CSD_10_WP_GRP_ENABLE_SLICE MMCSD_CSD_20_WP_GRP_ENABLE_SLICE
-#define MMCSD_CSD_10_WP_GRP_SIZE_SLICE MMCSD_CSD_20_WP_GRP_SIZE_SLICE
-#define MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE
-#define MMCSD_CSD_10_ERASE_BLK_EN_SLICE MMCSD_CSD_20_ERASE_BLK_EN_SLICE
-#define MMCSD_CSD_10_C_SIZE_MULT_SLICE 49,47
-#define MMCSD_CSD_10_VDD_W_CURR_MAX_SLICE 52,50
-#define MMCSD_CSD_10_VDD_W_CURR_MIN_SLICE 55,53
-#define MMCSD_CSD_10_VDD_R_CURR_MAX_SLICE 58,56
-#define MMCSD_CSD_10_VDD_R_CURR_MIX_SLICE 61,59
-#define MMCSD_CSD_10_C_SIZE_SLICE 73,62
-#define MMCSD_CSD_10_DSR_IMP_SLICE MMCSD_CSD_20_DSR_IMP_SLICE
-#define MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE
-#define MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE
-#define MMCSD_CSD_10_READ_BL_PARTIAL_SLICE MMCSD_CSD_20_READ_BL_PARTIAL_SLICE
-#define MMCSD_CSD_10_READ_BL_LEN_SLICE 83, 80
-#define MMCSD_CSD_10_CCC_SLICE MMCSD_CSD_20_CCC_SLICE
-#define MMCSD_CSD_10_TRANS_SPEED_SLICE MMCSD_CSD_20_TRANS_SPEED_SLICE
-#define MMCSD_CSD_10_NSAC_SLICE MMCSD_CSD_20_NSAC_SLICE
-#define MMCSD_CSD_10_TAAC_SLICE MMCSD_CSD_20_TAAC_SLICE
-#define MMCSD_CSD_10_STRUCTURE_SLICE MMCSD_CSD_20_STRUCTURE_SLICE
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief @p MMCSDBlockDevice specific methods.
- */
-#define _mmcsd_block_device_methods \
- _base_block_device_methods
-
-/**
- * @brief @p MMCSDBlockDevice specific data.
- * @note It is empty because @p MMCSDBlockDevice is only an interface
- * without implementation.
- */
-#define _mmcsd_block_device_data \
- _base_block_device_data \
- /* Card CID.*/ \
- uint32_t cid[4]; \
- /* Card CSD.*/ \
- uint32_t csd[4]; \
- /* Total number of blocks in card.*/ \
- uint32_t capacity;
-
-/**
- * @extends BaseBlockDeviceVMT
- *
- * @brief @p MMCSDBlockDevice virtual methods table.
- */
-struct MMCSDBlockDeviceVMT {
- _base_block_device_methods
-};
-
-/**
- * @extends BaseBlockDevice
- *
- * @brief MCC/SD block device class.
- * @details This class represents a, block-accessible, MMC/SD device.
- */
-typedef struct {
- /** @brief Virtual Methods Table.*/
- const struct MMCSDBlockDeviceVMT *vmt;
- _mmcsd_block_device_data
-} MMCSDBlockDevice;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name R1 response utilities
- * @{
- */
-/**
- * @brief Evaluates to @p TRUE if the R1 response contains error flags.
- *
- * @param[in] r1 the r1 response
- */
-#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0)
-
-/**
- * @brief Returns the status field of an R1 response.
- *
- * @param[in] r1 the r1 response
- */
-#define MMCSD_R1_STS(r1) (((r1) >> 9) & 15)
-
-/**
- * @brief Evaluates to @p TRUE if the R1 response indicates a locked card.
- *
- * @param[in] r1 the r1 response
- */
-#define MMCSD_R1_IS_CARD_LOCKED(r1) (((r1) >> 21) & 1)
-/** @} */
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns the card capacity in blocks.
- *
- * @param[in] ip pointer to a @p MMCSDBlockDevice or derived class
- *
- * @return The card capacity.
- *
- * @api
- */
-#define mmcsdGetCardCapacity(ip) ((ip)->capacity)
-/** @} */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- uint32_t mmcsdGetCapacity(uint32_t csd[4]);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MMC_SPI || HAL_USE_MMC_SDC*/
-
-#endif /* _MMCSD_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/rtc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/rtc.h
deleted file mode 100644
index 7fb53fd581..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/rtc.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file rtc.h
- * @brief RTC Driver macros and structures.
- *
- * @addtogroup RTC
- * @{
- */
-
-#ifndef _RTC_H_
-#define _RTC_H_
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Date/Time bit masks
- * @{
- */
-#define RTC_TIME_SECONDS_MASK 0x0000001F /* @brief Seconds mask. */
-#define RTC_TIME_MINUTES_MASK 0x000007E0 /* @brief Minutes mask. */
-#define RTC_TIME_HOURS_MASK 0x0000F800 /* @brief Hours mask. */
-#define RTC_DATE_DAYS_MASK 0x001F0000 /* @brief Days mask. */
-#define RTC_DATE_MONTHS_MASK 0x01E00000 /* @brief Months mask. */
-#define RTC_DATE_YEARS_MASK 0xFE000000 /* @brief Years mask. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an RTC driver.
- */
-typedef struct RTCDriver RTCDriver;
-
-/**
- * @brief Type of a structure representing an RTC time stamp.
- */
-typedef struct RTCTime RTCTime;
-
-#include "rtc_lld.h"
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Set current time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] timespec pointer to a @p RTCTime structure
- *
- * @iclass
- */
-#define rtcSetTimeI(rtcp, timespec) rtc_lld_set_time(rtcp, timespec)
-
-/**
- * @brief Get current time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @iclass
- */
-#define rtcGetTimeI(rtcp, timespec) rtc_lld_get_time(rtcp, timespec)
-
-#if (RTC_ALARMS > 0) || defined(__DOXYGEN__)
-/**
- * @brief Set alarm time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] alarm alarm identifier
- * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL
- *
- * @iclass
- */
-#define rtcSetAlarmI(rtcp, alarm, alarmspec) \
- rtc_lld_set_alarm(rtcp, alarm, alarmspec)
-
-/**
- * @brief Get current alarm.
- * @note If an alarm has not been set then the returned alarm specification
- * is not meaningful.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] alarm alarm identifier
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @iclass
- */
-#define rtcGetAlarmI(rtcp, alarm, alarmspec) \
- rtc_lld_get_alarm(rtcp, alarm, alarmspec)
-#endif /* RTC_ALARMS > 0 */
-
-#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__)
-/**
- * @brief Enables or disables RTC callbacks.
- * @details This function enables or disables the callback, use a @p NULL
- * pointer in order to disable it.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] callback callback function pointer or @p NULL
- *
- * @iclass
- */
-#define rtcSetCallbackI(rtcp, callback) rtc_lld_set_callback(rtcp, callback)
-#endif /* RTC_SUPPORTS_CALLBACKS */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void rtcInit(void);
- void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec);
- void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec);
-#if RTC_ALARMS > 0
- void rtcSetAlarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
- const RTCAlarm *alarmspec);
- void rtcGetAlarm(RTCDriver *rtcp, rtcalarm_t alarm, RTCAlarm *alarmspec);
-#endif
- uint32_t rtcGetTimeFat(RTCDriver *rtcp);
-#if RTC_SUPPORTS_CALLBACKS
- void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_RTC */
-#endif /* _RTC_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/tm.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/tm.h
deleted file mode 100644
index 2b9c2d8eb1..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/tm.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file tm.h
- * @brief Time Measurement driver header.
- *
- * @addtogroup TM
- * @{
- */
-
-#ifndef _TM_H_
-#define _TM_H_
-
-#if HAL_USE_TM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a Time Measurement object.
- * @note Start/stop of measurements is performed through the function
- * pointers in order to avoid inlining of those functions which
- * could compromise measurement accuracy.
- * @note The maximum measurable time period depends on the implementation
- * of the realtime counter in the HAL driver.
- * @note The measurement is not 100% cycle-accurate, it can be in excess
- * of few cycles depending on the compiler and target architecture.
- * @note Interrupts can affect measurement if the measurement is performed
- * with interrupts enabled.
- */
-typedef struct TimeMeasurement TimeMeasurement;
-
-/**
- * @brief Time Measurement structure.
- */
-struct TimeMeasurement {
- void (*start)(TimeMeasurement *tmp); /**< @brief Starts a measurement. */
- void (*stop)(TimeMeasurement *tmp); /**< @brief Stops a measurement. */
- halrtcnt_t last; /**< @brief Last measurement. */
- halrtcnt_t worst; /**< @brief Worst measurement. */
- halrtcnt_t best; /**< @brief Best measurement. */
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Starts a measurement.
- * @pre The @p TimeMeasurement must be initialized.
- * @note This function can be invoked in any context.
- *
- * @param[in,out] tmp pointer to a @p TimeMeasurement structure
- *
- * @special
- */
-#define tmStartMeasurement(tmp) (tmp)->start(tmp)
-
-/**
- * @brief Stops a measurement.
- * @pre The @p TimeMeasurement must be initialized.
- * @note This function can be invoked in any context.
- *
- * @param[in,out] tmp pointer to a @p TimeMeasurement structure
- *
- * @special
- */
-#define tmStopMeasurement(tmp) (tmp)->stop(tmp)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void tmInit(void);
- void tmObjectInit(TimeMeasurement *tmp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_TM */
-
-#endif /* _TM_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/uart.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/uart.h
deleted file mode 100644
index 4f4c2c158a..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/include/uart.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file uart.h
- * @brief UART Driver macros and structures.
- *
- * @addtogroup UART
- * @{
- */
-
-#ifndef _UART_H_
-#define _UART_H_
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name UART status flags
- * @{
- */
-#define UART_NO_ERROR 0 /**< @brief No pending conditions. */
-#define UART_PARITY_ERROR 4 /**< @brief Parity error happened. */
-#define UART_FRAMING_ERROR 8 /**< @brief Framing error happened. */
-#define UART_OVERRUN_ERROR 16 /**< @brief Overflow happened. */
-#define UART_NOISE_ERROR 32 /**< @brief Noise on the line. */
-#define UART_BREAK_DETECTED 64 /**< @brief Break detected. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver state machine possible states.
- */
-typedef enum {
- UART_UNINIT = 0, /**< Not initialized. */
- UART_STOP = 1, /**< Stopped. */
- UART_READY = 2 /**< Ready. */
-} uartstate_t;
-
-/**
- * @brief Transmitter state machine states.
- */
-typedef enum {
- UART_TX_IDLE = 0, /**< Not transmitting. */
- UART_TX_ACTIVE = 1, /**< Transmitting. */
- UART_TX_COMPLETE = 2 /**< Buffer complete. */
-} uarttxstate_t;
-
-/**
- * @brief Receiver state machine states.
- */
-typedef enum {
- UART_RX_IDLE = 0, /**< Not receiving. */
- UART_RX_ACTIVE = 1, /**< Receiving. */
- UART_RX_COMPLETE = 2 /**< Buffer complete. */
-} uartrxstate_t;
-
-#include "uart_lld.h"
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void uartInit(void);
- void uartObjectInit(UARTDriver *uartp);
- void uartStart(UARTDriver *uartp, const UARTConfig *config);
- void uartStop(UARTDriver *uartp);
- void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf);
- void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf);
- size_t uartStopSend(UARTDriver *uartp);
- size_t uartStopSendI(UARTDriver *uartp);
- void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf);
- void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf);
- size_t uartStopReceive(UARTDriver *uartp);
- size_t uartStopReceiveI(UARTDriver *uartp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_UART */
-
-#endif /* _UART_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/fallback/I2C/hal_i2c_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/fallback/I2C/hal_i2c_lld.c
new file mode 100644
index 0000000000..b4b0dc96b5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/fallback/I2C/hal_i2c_lld.c
@@ -0,0 +1,442 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file common/I2C/hal_i2c_lld.c
+ * @brief SW I2C subsystem low level driver source.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define CHECK_ERROR(msg) \
+ if ((msg) < (msg_t)0) { \
+ return MSG_TIMEOUT; \
+ }
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief I2C1 driver identifier.*/
+#if SW_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/** @brief I2C2 driver identifier.*/
+#if SW_I2C_USE_I2C2 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/** @brief I2C3 driver identifier.*/
+#if SW_I2C_USE_I2C3 || defined(__DOXYGEN__)
+I2CDriver I2CD3;
+#endif
+
+/** @brief I2C4 driver identifier.*/
+#if SW_I2C_USE_I2C4 || defined(__DOXYGEN__)
+I2CDriver I2CD4;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static msg_t i2c_write_stop(I2CDriver *i2cp);
+
+static inline void i2c_delay(I2CDriver *i2cp) {
+
+#if SW_I2C_USE_OSAL_DELAY || defined(__DOXYGEN__)
+ osalThreadSleep(i2cp->config->ticks);
+#else
+ i2cp->config->delay();
+#endif
+}
+
+static inline msg_t i2c_check_arbitration(I2CDriver *i2cp) {
+
+ if (palReadLine(i2cp->config->sda) == PAL_LOW) {
+ i2cp->errors |= I2C_ARBITRATION_LOST;
+ return MSG_RESET;
+ }
+
+ return MSG_OK;
+}
+
+static inline msg_t i2c_check_timeout(I2CDriver *i2cp) {
+
+ if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), i2cp->start, i2cp->end)) {
+ i2c_write_stop(i2cp);
+ return MSG_TIMEOUT;
+ }
+
+ return MSG_OK;
+}
+
+static msg_t i2c_wait_clock(I2CDriver *i2cp) {
+
+ while (palReadLine(i2cp->config->scl) == PAL_LOW) {
+ if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), i2cp->start, i2cp->end)) {
+ return MSG_TIMEOUT;
+ }
+ i2c_delay(i2cp);
+ }
+
+ return MSG_OK;
+}
+
+static inline msg_t i2c_write_start(I2CDriver *i2cp) {
+
+ /* Arbitration check.*/
+ CHECK_ERROR(i2c_check_arbitration(i2cp));
+
+ palClearLine(i2cp->config->sda);
+ i2c_delay(i2cp);
+ palClearLine(i2cp->config->scl);
+
+ return MSG_OK;
+}
+
+static msg_t i2c_write_restart(I2CDriver *i2cp) {
+
+ palSetLine(i2cp->config->sda);
+ i2c_delay(i2cp);
+ palSetLine(i2cp->config->scl);
+
+ /* Clock stretching.*/
+ CHECK_ERROR(i2c_wait_clock(i2cp));
+
+ i2c_delay(i2cp);
+ i2c_write_start(i2cp);
+
+ return MSG_OK;
+}
+
+static msg_t i2c_write_stop(I2CDriver *i2cp) {
+
+ palClearLine(i2cp->config->sda);
+ i2c_delay(i2cp);
+ palSetLine(i2cp->config->scl);
+
+ /* Clock stretching.*/
+ CHECK_ERROR(i2c_wait_clock(i2cp));
+
+ i2c_delay(i2cp);
+ palSetLine(i2cp->config->sda);
+ i2c_delay(i2cp);
+
+ /* Arbitration check.*/
+ CHECK_ERROR(i2c_check_arbitration(i2cp));
+
+ i2c_delay(i2cp);
+
+ return MSG_OK;
+}
+
+static msg_t i2c_write_bit(I2CDriver *i2cp, unsigned bit) {
+
+ palWriteLine(i2cp->config->sda, bit);
+ i2c_delay(i2cp);
+ palSetLine(i2cp->config->scl);
+ i2c_delay(i2cp);
+
+ /* Clock stretching.*/
+ CHECK_ERROR(i2c_wait_clock(i2cp));
+
+ /* Arbitration check.*/
+ if (bit == PAL_HIGH) {
+ CHECK_ERROR(i2c_check_arbitration(i2cp));
+ }
+
+ palClearLine(i2cp->config->scl);
+
+ return MSG_OK;
+}
+
+static msg_t i2c_read_bit(I2CDriver *i2cp) {
+ msg_t bit;
+
+ palSetLine(i2cp->config->sda);
+ i2c_delay(i2cp);
+ palSetLine(i2cp->config->scl);
+
+ /* Clock stretching.*/
+ CHECK_ERROR(i2c_wait_clock(i2cp));
+
+ i2c_delay(i2cp);
+ bit = palReadLine(i2cp->config->sda);
+ palClearLine(i2cp->config->scl);
+
+ return bit;
+}
+
+static msg_t i2c_write_byte(I2CDriver *i2cp, uint8_t byte) {
+ msg_t msg;
+ uint8_t mask;
+
+ CHECK_ERROR(i2c_check_timeout(i2cp));
+
+ for (mask = 0x80U; mask > 0U; mask >>= 1U) {
+ CHECK_ERROR(i2c_write_bit(i2cp, (byte & mask) != 0));
+ }
+
+ msg = i2c_read_bit(i2cp);
+ CHECK_ERROR(msg);
+
+ /* Checking for NACK.*/
+ if (msg == PAL_HIGH) {
+ i2cp->errors |= I2C_ACK_FAILURE;
+ return MSG_RESET;
+ }
+
+ return MSG_OK;
+}
+
+static msg_t i2c_read_byte(I2CDriver *i2cp, unsigned nack) {
+ msg_t byte;
+ unsigned i;
+
+ CHECK_ERROR(i2c_check_timeout(i2cp));
+
+ byte = 0U;
+ for (i = 0; i < 8; i++) {
+ msg_t msg = i2c_read_bit(i2cp);
+ CHECK_ERROR(msg);
+ byte = (byte << 1U) | msg;
+ }
+
+ CHECK_ERROR(i2c_write_bit(i2cp, nack));
+
+ return byte;
+}
+
+static msg_t i2c_write_header(I2CDriver *i2cp, i2caddr_t addr, bool rw) {
+
+ /* Check for 10 bits addressing.*/
+ if (i2cp->config->addr10) {
+ /* It is 10 bits.*/
+ uint8_t b1, b2;
+
+ b1 = 0xF0U | ((addr >> 8U) << 1U);
+ b2 = (uint8_t)(addr & 255U);
+ if (rw) {
+ b1 |= 1U;
+ }
+ CHECK_ERROR(i2c_write_byte(i2cp, b1));
+ CHECK_ERROR(i2c_write_byte(i2cp, b2));
+ }
+ else {
+ /* It is 7 bits.*/
+ if (rw) {
+ /* Read.*/
+ CHECK_ERROR(i2c_write_byte(i2cp, (addr << 1U) | 1U));
+ }
+ else {
+ /* Write.*/
+ CHECK_ERROR(i2c_write_byte(i2cp, (addr << 1U) | 0U));
+ }
+ }
+
+ return MSG_OK;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2C driver initialization.
+ *
+ * @notapi
+ */
+void i2c_lld_init(void) {
+
+#if SW_I2C_USE_I2C1
+ i2cObjectInit(&I2CD1);
+#endif
+#if SW_I2C_USE_I2C2
+ i2cObjectInit(&I2CD2);
+#endif
+#if SW_I2C_USE_I2C3
+ i2cObjectInit(&I2CD3);
+#endif
+#if SW_I2C_USE_I2C4
+ i2cObjectInit(&I2CD4);
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+
+ /* Does nothing.*/
+ (void)i2cp;
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+
+ /* Does nothing.*/
+ (void)i2cp;
+}
+
+/**
+ * @brief Receives data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ /* Setting timeout fields.*/
+ i2cp->start = osalOsGetSystemTimeX();
+ i2cp->end = i2cp->start;
+ if (timeout != TIME_INFINITE) {
+ i2cp->end += timeout;
+ }
+
+ CHECK_ERROR(i2c_write_start(i2cp));
+
+ /* Sending anddress and mode.*/
+ CHECK_ERROR(i2c_write_header(i2cp, addr, true));
+
+ do {
+ /* Last byte sends a NACK.*/
+ msg_t msg = i2c_read_byte(i2cp, rxbytes > 1U ? 0U : 1U);
+ CHECK_ERROR(msg);
+ *rxbuf++ = (uint8_t)msg;
+ } while (--rxbytes);
+
+ return i2c_write_stop(i2cp);
+}
+
+/**
+ * @brief Transmits data via the I2C bus as master.
+ * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
+ * This is hardware restriction.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[in] txbuf pointer to the transmit buffer
+ * @param[in] txbytes number of bytes to be transmitted
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ /* Setting timeout fields.*/
+ i2cp->start = osalOsGetSystemTimeX();
+ i2cp->end = i2cp->start;
+ if (timeout != TIME_INFINITE) {
+ i2cp->end += timeout;
+ }
+
+ /* send start condition */
+ CHECK_ERROR(i2c_write_start(i2cp));
+
+ /* Sending anddress and mode.*/
+ CHECK_ERROR(i2c_write_header(i2cp, addr, false));
+
+ do {
+ CHECK_ERROR(i2c_write_byte(i2cp, *txbuf++));
+ } while (--txbytes);
+
+ /* Is there a read phase? */
+ if (rxbytes > 0U) {
+
+ /* send restart condition */
+ CHECK_ERROR(i2c_write_restart(i2cp));
+ /* Sending anddress and mode.*/
+ CHECK_ERROR(i2c_write_header(i2cp, addr, true));
+
+ do {
+ /* Last byte sends a NACK.*/
+ msg_t msg = i2c_read_byte(i2cp, rxbytes > 1U ? 0U : 1U);
+ CHECK_ERROR(msg);
+ *rxbuf++ = (uint8_t)msg;
+ } while (--rxbytes);
+ }
+
+ return i2c_write_stop(i2cp);
+}
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/fallback/I2C/hal_i2c_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/fallback/I2C/hal_i2c_lld.h
new file mode 100644
index 0000000000..628c4ebfe8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/fallback/I2C/hal_i2c_lld.h
@@ -0,0 +1,232 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file common/I2C/hal_i2c_lld.h
+ * @brief SW I2C subsystem low level driver header.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef HAL_I2C_LLD_H
+#define HAL_I2C_LLD_H
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Use OSAL delays.
+ * @details If set to @p TRUE then delays are implemented using the
+ * thread-friendy delay function else a delay function must
+ * be provided extenally.
+ */
+#if !defined(SW_I2C_USE_OSAL_DELAY) || defined(__DOXYGEN__)
+#define SW_I2C_USE_OSAL_DELAY TRUE
+#endif
+
+/**
+ * @brief I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SW_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define SW_I2C_USE_I2C1 FALSE
+#endif
+
+/**
+ * @brief I2C2 driver enable switch.
+ * @details If set to @p TRUE the support for I2C2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SW_I2C_USE_I2C2) || defined(__DOXYGEN__)
+#define SW_I2C_USE_I2C2 FALSE
+#endif
+
+/**
+ * @brief I2C3 driver enable switch.
+ * @details If set to @p TRUE the support for I2C3 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SW_I2C_USE_I2C3) || defined(__DOXYGEN__)
+#define SW_I2C_USE_I2C3 FALSE
+#endif
+
+/**
+ * @brief I2C4 driver enable switch.
+ * @details If set to @p TRUE the support for I2C4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SW_I2C_USE_I2C4) || defined(__DOXYGEN__)
+#define SW_I2C_USE_I2C4 FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing an I2C address.
+ */
+typedef uint16_t i2caddr_t;
+
+/**
+ * @brief Type of I2C driver condition flags.
+ */
+typedef uint8_t i2cflags_t;
+
+/**
+ * @brief Type of a delay function.
+ */
+typedef void (*i2c_delay_t)(void);
+
+/**
+ * @brief Type of I2C driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief 10 bits addressing switch.
+ */
+ bool addr10;
+ /**
+ * @brief I2C clock line.
+ */
+ ioline_t scl;
+ /**
+ * @brief I2C data line.
+ */
+ ioline_t sda;
+#if SW_I2C_USE_OSAL_DELAY || defined(__DOXYGEN__)
+ /**
+ * @brief Delay of an half bit time in system ticks.
+ */
+ systime_t ticks;
+#else
+ /**
+ * @brief Pointer to an externally defined delay function.
+ */
+ i2c_delay_t delay;
+#endif
+} I2CConfig;
+
+/**
+ * @brief Type of a structure representing an I2C driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2cstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2CConfig *config;
+ /**
+ * @brief Error flags.
+ */
+ i2cflags_t errors;
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ mutex_t mutex;
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if defined(I2C_DRIVER_EXT_FIELDS)
+ I2C_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Time of operation begin.
+ */
+ systime_t start;
+ /**
+ * @brief Time of operation timeout.
+ */
+ systime_t end;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Get errors from I2C driver.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+#if SW_I2C_USE_I2C1
+extern I2CDriver I2CD1;
+#endif
+#if SW_I2C_USE_I2C2
+extern I2CDriver I2CD2;
+#endif
+#if SW_I2C_USE_I2C3
+extern I2CDriver I2CD3;
+#endif
+#if SW_I2C_USE_I2C4
+extern I2CDriver I2CD4;
+#endif
+#endif /* !defined(__DOXYGEN__) */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2c_lld_init(void);
+ void i2c_lld_start(I2CDriver *i2cp);
+ void i2c_lld_stop(I2CDriver *i2cp);
+ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout);
+ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2C */
+
+#endif /* HAL_I2C_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/displays/hal_displays.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/displays/hal_displays.h
new file mode 100644
index 0000000000..44db7aaf61
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/displays/hal_displays.h
@@ -0,0 +1,112 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_displays.h
+ * @brief Generic display interface header.
+ *
+ * @addtogroup HAL_DISPLAYS
+ * @{
+ */
+
+#ifndef HAL_DISPLAYS_H
+#define HAL_DISPLAYS_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief @p BaseDisplay specific methods.
+ * @note No methods so far, just a common ancestor interface.
+ */
+#define _base_display_methods_alone
+
+/**
+ * @brief @p BaseDisplay specific methods with inherited ones.
+ */
+#define _base_display_methods \
+ _base_display_methods_alone
+
+/**
+ * @brief @p BaseDisplay virtual methods table.
+ */
+struct BaseDisplayVMT {
+ _base_display_methods
+};
+
+/**
+ * @brief @p BaseDisplay specific data.
+ * @note It is empty because @p BaseDisplay is only an interface
+ * without implementation.
+ */
+#define _base_display_data
+
+/**
+ * @brief Base display class.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseDisplayVMT *vmt_basedisplay;
+ _base_display_data
+} BaseDisplay;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions (BaseDisplay)
+ * @{
+ */
+/**
+ * @brief Sensors get axes number.
+ *
+ * @param[in] ip pointer to a @p BaseDisplay or derived class.
+ * @return The number of axes of the BaseDisplay
+ *
+ * @api
+ */
+#define displayGetType(ip) (ip)->vmt_basedisplay->get_type(ip)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_DISPLAYS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_flash.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_flash.c
new file mode 100644
index 0000000000..e20c66b0b3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_flash.c
@@ -0,0 +1,124 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_flash.c
+ * @brief Generic flash driver class code.
+ *
+ * @addtogroup HAL_FLASH
+ * @{
+ */
+
+#include "hal.h"
+
+#include "hal_flash.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Waits until the current erase operation is finished.
+ *
+ * @param[in] devp pointer to a @p BaseFlash object
+ *
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_ERROR_ERASE if the erase operation failed.
+ */
+flash_error_t flashWaitErase(BaseFlash *devp) {
+
+ while (true) {
+ flash_error_t err;
+ uint32_t msec;
+
+ /* Checking operation state.*/
+ err = flashQueryErase(devp, &msec);
+ if (err != FLASH_BUSY_ERASING) {
+ return err;
+ }
+
+ /* Interval because nice waiting.*/
+ osalThreadSleepMilliseconds(msec);
+ }
+}
+
+/**
+ * @brief Returns the offset of a sector.
+ *
+ * @param[in] devp pointer to a @p BaseFlash object
+ * @param[in] sector flash sector number
+ *
+ * @return the offset of the sector
+ */
+flash_offset_t flashGetSectorOffset(BaseFlash *devp,
+ flash_sector_t sector) {
+ flash_offset_t offset;
+ const flash_descriptor_t *descriptor = flashGetDescriptor(devp);
+
+ osalDbgAssert(sector < descriptor->sectors_count, "invalid sector");
+
+ if (descriptor->sectors != NULL) {
+ offset = descriptor->sectors[sector].offset;
+ }
+ else {
+ offset = (flash_offset_t)sector * (flash_offset_t)descriptor->sectors_size;
+ }
+
+ return offset;
+}
+
+/**
+ * @brief Returns the size of a sector.
+ *
+ * @param[in] devp pointer to a @p BaseFlash object
+ * @param[in] sector flash sector number
+ *
+ * @return the size of the sector
+ */
+uint32_t flashGetSectorSize(BaseFlash *devp,
+ flash_sector_t sector) {
+ uint32_t size;
+ const flash_descriptor_t *descriptor = flashGetDescriptor(devp);
+
+ osalDbgAssert(sector < descriptor->sectors_count, "invalid sector");
+
+ if (descriptor->sectors != NULL) {
+ size = descriptor->sectors[sector].size;
+ }
+ else {
+ size = descriptor->sectors_size;
+ }
+
+ return size;
+}
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_flash.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_flash.h
new file mode 100644
index 0000000000..5076ea4211
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_flash.h
@@ -0,0 +1,319 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_flash.h
+ * @brief Generic flash driver class header.
+ *
+ * @addtogroup HAL_FLASH
+ * @{
+ */
+
+#ifndef HAL_FLASH_H
+#define HAL_FLASH_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Flash attributes
+ * @{
+ */
+#define FLASH_ATTR_ERASED_IS_ONE 0x00000001
+#define FLASH_ATTR_MEMORY_MAPPED 0x00000002
+#define FLASH_ATTR_REWRITABLE 0x00000004
+#define FLASH_ATTR_READ_ECC_CAPABLE 0x00000008
+#define FLASH_ATTR_SUSPEND_ERASE_CAPABLE 0x00000010
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ FLASH_UNINIT = 0,
+ FLASH_STOP = 1,
+ FLASH_READY = 2,
+ FLASH_READ = 3,
+ FLASH_PGM = 4,
+ FLASH_ERASE = 5
+} flash_state_t;
+
+/**
+ * @brief Type of a flash error code.
+ */
+typedef enum {
+ FLASH_NO_ERROR = 0, /* No error. */
+ FLASH_BUSY_ERASING = 1, /* Erase operation in progress. */
+ FLASH_ERROR_READ = 2, /* ECC or other error during read operation.*/
+ FLASH_ERROR_PROGRAM = 3, /* Program operation failed. */
+ FLASH_ERROR_ERASE = 4, /* Erase operation failed. */
+ FLASH_ERROR_VERIFY = 5, /* Verify operation failed. */
+ FLASH_ERROR_HW_FAILURE = 6 /* Controller or communication error. */
+} flash_error_t;
+
+/**
+ * @brief Type of a flash offset.
+ */
+typedef uint32_t flash_offset_t;
+
+/**
+ * @brief Type of a flash sector number.
+ */
+typedef uint32_t flash_sector_t;
+
+/**
+ * @brief Flash sector descriptor.
+ */
+typedef struct {
+ /**
+ * @brief Sector offset.
+ */
+ flash_offset_t offset;
+ /**
+ * @brief Sector size.
+ */
+ uint32_t size;
+} flash_sector_descriptor_t;
+
+/**
+ * @brief Type of a flash device descriptor.
+ */
+typedef struct {
+ /**
+ * @brief Device_attributes.
+ */
+ uint32_t attributes;
+ /**
+ * @brief Size of write page.
+ */
+ uint32_t page_size;
+ /**
+ * @brief Number of sectors in the device.
+ */
+ flash_sector_t sectors_count;
+ /**
+ * @brief List of sectors for devices with non-uniform sector sizes.
+ * @note If @p NULL then the device has uniform sectors size equal
+ * to @p sector_size.
+ */
+ const flash_sector_descriptor_t *sectors;
+ /**
+ * @brief Size of sectors for devices with uniform sector size.
+ * @note If zero then the device has non uniform sectors described
+ * by the @p sectors array.
+ */
+ uint32_t sectors_size;
+ /**
+ * @brief Flash address if memory mapped or zero.
+ * @note Conventionally, non memory mapped devices have address zero.
+ */
+ flash_offset_t address;
+} flash_descriptor_t;
+
+/**
+ * @brief @p BaseFlash specific methods.
+ * @note No methods so far, just a common ancestor interface.
+ */
+#define _base_flash_methods_alone \
+ /* Get flash device attributes.*/ \
+ const flash_descriptor_t * (*get_descriptor)(void *instance); \
+ /* Read operation.*/ \
+ flash_error_t (*read)(void *instance, flash_offset_t offset, \
+ size_t n, uint8_t *rp); \
+ /* Program operation.*/ \
+ flash_error_t (*program)(void *instance, flash_offset_t offset, \
+ size_t n, const uint8_t *pp); \
+ /* Erase whole flash device.*/ \
+ flash_error_t (*start_erase_all)(void *instance); \
+ /* Erase single sector.*/ \
+ flash_error_t (*start_erase_sector)(void *instance, \
+ flash_sector_t sector); \
+ flash_error_t (*query_erase)(void *instance, uint32_t *wait_time); \
+ /* Verify erase single sector.*/ \
+ flash_error_t (*verify_erase)(void *instance, flash_sector_t sector);
+
+/**
+ * @brief @p BaseFlash specific methods with inherited ones.
+ */
+#define _base_flash_methods \
+ _base_flash_methods_alone
+
+/**
+ * @brief @p BaseFlash virtual methods table.
+ */
+struct BaseFlashVMT {
+ _base_flash_methods
+};
+
+/**
+ * @brief @p BaseFlash specific data.
+ */
+#define _base_flash_data \
+ /* Driver state.*/ \
+ flash_state_t state;
+
+
+/**
+ * @brief Base flash class.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseFlashVMT *vmt;
+ _base_flash_data
+} BaseFlash;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions (BaseFlash)
+ * @{
+ */
+/**
+ * @brief Sensors get axes number.
+ *
+ * @param[in] ip pointer to a @p BaseFlash or derived class
+ * @return A flash device descriptor.
+ *
+ * @api
+ */
+#define flashGetDescriptor(ip) \
+ (ip)->vmt->get_descriptor(ip)
+
+/**
+ * @brief Read operation.
+ *
+ * @param[in] ip pointer to a @p BaseFlash or derived class
+ * @param[in] offset flash offset
+ * @param[in] n number of bytes to be read
+ * @param[out] rp pointer to the data buffer
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_READ if the read operation failed.
+ *
+ * @api
+ */
+#define flashRead(ip, offset, n, rp) \
+ (ip)->vmt->read(ip, offset, n, rp)
+
+/**
+ * @brief Program operation.
+ *
+ * @param[in] ip pointer to a @p BaseFlash or derived class
+ * @param[in] offset flash offset
+ * @param[in] n number of bytes to be programmed
+ * @param[in] pp pointer to the data buffer
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_PROGRAM if the program operation failed.
+ *
+ * @api
+ */
+#define flashProgram(ip, offset, n, pp) \
+ (ip)->vmt->program(ip, offset, n, pp)
+
+/**
+ * @brief Starts a whole-device erase operation.
+ *
+ * @param[in] ip pointer to a @p BaseFlash or derived class
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ *
+ * @api
+ */
+#define flashStartEraseAll(ip) \
+ (ip)->vmt->start_erase_all(ip)
+
+/**
+ * @brief Starts an sector erase operation.
+ *
+ * @param[in] ip pointer to a @p BaseFlash or derived class
+ * @param[in] sector sector to be erased
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ *
+ * @api
+ */
+#define flashStartEraseSector(ip, sector) \
+ (ip)->vmt->start_erase_sector(ip, sector)
+
+/**
+ * @brief Queries the driver for erase operation progress.
+ *
+ * @param[in] ip pointer to a @p BaseFlash or derived class
+ * @param[out] msec recommended time, in milliseconds, that what should be
+ * spent before calling this function again, can be @p NULL
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_ERASE if the erase operation failed.
+ *
+ * @api
+ */
+#define flashQueryErase(ip, msec) \
+ (ip)->vmt->query_erase(ip, msec)
+
+/**
+ * @brief Returns the erase state of a sector.
+ *
+ * @param[in] ip pointer to a @p BaseFlash or derived class
+ * @param[in] sector sector to be verified
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_VERIFY if the verify operation failed.
+ *
+ * @api
+ */
+#define flashVerifyErase(ip, sector) \
+ (ip)->vmt->verify_erase(ip, sector)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ flash_error_t flashWaitErase(BaseFlash *devp);
+ flash_offset_t flashGetSectorOffset(BaseFlash *devp, flash_sector_t sector);
+ uint32_t flashGetSectorSize(BaseFlash *devp, flash_sector_t sector);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_FLASH_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_jesd216_flash.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_jesd216_flash.c
new file mode 100644
index 0000000000..b7e12d77d2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_jesd216_flash.c
@@ -0,0 +1,368 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_jesd216_flash.c
+ * @brief JESD216 compliant flash driver class code.
+ *
+ * @addtogroup HAL_JESD216_FLASH
+ * @{
+ */
+
+#include "hal.h"
+
+#include "hal_jesd216_flash.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+void jesd216_start(BUSDriver *busp, const BUSConfig *config) {
+
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_SPI
+ spiStart(busp, config);
+#else
+ qspiStart(busp, config);
+#endif
+}
+
+void jesd216_stop(BUSDriver *busp) {
+
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_SPI
+ spiStop(busp);
+#else
+ qspiStop(busp);
+#endif
+}
+
+void jesd216_cmd(BUSDriver *busp, uint32_t cmd) {
+#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI
+ qspi_command_t mode;
+
+ mode.cfg = QSPI_CFG_CMD(cmd) |
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L
+ QSPI_CFG_CMD_MODE_ONE_LINE;
+#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L
+ QSPI_CFG_CMD_MODE_TWO_LINES;
+#else
+ QSPI_CFG_CMD_MODE_FOUR_LINES;
+#endif
+ mode.addr = 0U;
+ mode.alt = 0U;
+ qspiCommand(busp, &mode);
+#else
+ uint8_t buf[1];
+
+ spiSelect(busp);
+ buf[0] = cmd;
+ spiSend(busp, 1, buf);
+ spiUnselect(busp);
+#endif
+}
+
+void jesd216_cmd_receive(BUSDriver *busp,
+ uint32_t cmd,
+ size_t n,
+ uint8_t *p) {
+#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI
+ qspi_command_t mode;
+
+ mode.cfg = QSPI_CFG_CMD(cmd) |
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L
+ QSPI_CFG_CMD_MODE_ONE_LINE |
+ QSPI_CFG_DATA_MODE_ONE_LINE;
+#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L
+ QSPI_CFG_CMD_MODE_TWO_LINES |
+ QSPI_CFG_DATA_MODE_TWO_LINES;
+#else
+ QSPI_CFG_CMD_MODE_FOUR_LINES |
+ QSPI_CFG_DATA_MODE_FOUR_LINES;
+
+#endif
+ mode.addr = 0U;
+ mode.alt = 0U;
+ qspiReceive(busp, &mode, n, p);
+#else
+ uint8_t buf[1];
+
+ spiSelect(busp);
+ buf[0] = cmd;
+ spiSend(busp, 1, buf);
+ spiReceive(busp, n, p);
+ spiUnselect(busp);
+#endif
+}
+
+void jesd216_cmd_send(BUSDriver *busp,
+ uint32_t cmd,
+ size_t n,
+ const uint8_t *p) {
+#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI
+ qspi_command_t mode;
+
+ mode.cfg = QSPI_CFG_CMD(cmd) |
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L
+ QSPI_CFG_CMD_MODE_ONE_LINE |
+ QSPI_CFG_DATA_MODE_ONE_LINE;
+#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L
+ QSPI_CFG_CMD_MODE_TWO_LINES |
+ QSPI_CFG_DATA_MODE_TWO_LINES;
+#else
+ QSPI_CFG_CMD_MODE_FOUR_LINES |
+ QSPI_CFG_DATA_MODE_FOUR_LINES;
+
+#endif
+ mode.addr = 0U;
+ mode.alt = 0U;
+ qspiSend(busp, &mode, n, p);
+#else
+ uint8_t buf[1];
+
+ spiSelect(busp);
+ buf[0] = cmd;
+ spiSend(busp, 1, buf);
+ spiSend(busp, n, p);
+ spiUnselect(busp);
+#endif
+}
+
+void jesd216_cmd_addr(BUSDriver *busp,
+ uint32_t cmd,
+ flash_offset_t offset) {
+#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI
+ qspi_command_t mode;
+
+ mode.cfg = QSPI_CFG_CMD(cmd) |
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L
+ QSPI_CFG_CMD_MODE_ONE_LINE |
+ QSPI_CFG_ADDR_MODE_ONE_LINE |
+ QSPI_CFG_ADDR_SIZE_24;
+#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L
+ QSPI_CFG_CMD_MODE_TWO_LINES |
+ QSPI_CFG_ADDR_MODE_TWO_LINES |
+ QSPI_CFG_ADDR_SIZE_24;
+#else
+ QSPI_CFG_CMD_MODE_FOUR_LINES |
+ QSPI_CFG_ADDR_MODE_FOUR_LINES |
+ QSPI_CFG_ADDR_SIZE_24;
+
+#endif
+ mode.addr = offset;
+ mode.alt = 0U;
+ qspiCommand(busp, &mode);
+#else
+ uint8_t buf[4];
+
+ spiSelect(busp);
+ buf[0] = cmd;
+ buf[1] = (uint8_t)(addr >> 16);
+ buf[2] = (uint8_t)(addr >> 8);
+ buf[3] = (uint8_t)(addr >> 0);
+ spiSend(busp, 4, buf);
+ spiUnselect(busp);
+#endif
+}
+
+void jesd216_cmd_addr_send(BUSDriver *busp,
+ uint32_t cmd,
+ flash_offset_t offset,
+ size_t n,
+ const uint8_t *p) {
+#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI
+ qspi_command_t mode;
+
+ mode.cfg = QSPI_CFG_CMD(cmd & 0xFFU) |
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L
+ QSPI_CFG_CMD_MODE_ONE_LINE |
+ QSPI_CFG_ADDR_MODE_ONE_LINE |
+ QSPI_CFG_DATA_MODE_ONE_LINE;
+#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L
+ QSPI_CFG_CMD_MODE_TWO_LINES |
+ QSPI_CFG_ADDR_MODE_TWO_LINES |
+ QSPI_CFG_DATA_MODE_TWO_LINES;
+#else
+ QSPI_CFG_CMD_MODE_FOUR_LINES |
+ QSPI_CFG_ADDR_MODE_FOUR_LINES |
+ QSPI_CFG_DATA_MODE_FOUR_LINES;
+#endif
+
+ /* Handling 32 bits addressing.*/
+ if ((cmd & JESD216_CMD_EXTENDED_ADDRESSING) == 0) {
+ mode .cfg |= QSPI_CFG_ADDR_SIZE_24;
+ }
+ else {
+ mode .cfg |= QSPI_CFG_ADDR_SIZE_32;
+ }
+
+ mode.addr = offset;
+ mode.alt = 0U;
+ qspiSend(busp, &mode, n, p);
+#else
+ uint8_t buf[4];
+
+ spiSelect(busp);
+ buf[0] = cmd;
+ buf[1] = (uint8_t)(addr >> 16);
+ buf[2] = (uint8_t)(addr >> 8);
+ buf[3] = (uint8_t)(addr >> 0);
+ spiSend(busp, 4, buf);
+ spiSend(busp, n, p);
+ spiUnselect(busp);
+#endif
+}
+
+void jesd216_cmd_addr_receive(BUSDriver *busp,
+ uint32_t cmd,
+ flash_offset_t offset,
+ size_t n,
+ uint8_t *p) {
+#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI
+ qspi_command_t mode;
+
+ mode.cfg = QSPI_CFG_CMD(cmd & 0xFFU) |
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L
+ QSPI_CFG_CMD_MODE_ONE_LINE |
+ QSPI_CFG_ADDR_MODE_ONE_LINE |
+ QSPI_CFG_DATA_MODE_ONE_LINE;
+#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L
+ QSPI_CFG_CMD_MODE_TWO_LINES |
+ QSPI_CFG_ADDR_MODE_TWO_LINES |
+ QSPI_CFG_ADDR_SIZE_24 |
+ QSPI_CFG_DATA_MODE_TWO_LINES;
+#else
+ QSPI_CFG_CMD_MODE_FOUR_LINES |
+ QSPI_CFG_ADDR_MODE_FOUR_LINES |
+ QSPI_CFG_DATA_MODE_FOUR_LINES;
+#endif
+
+ /* Handling 32 bits addressing.*/
+ if ((cmd & JESD216_CMD_EXTENDED_ADDRESSING) == 0) {
+ mode .cfg |= QSPI_CFG_ADDR_SIZE_24;
+ }
+ else {
+ mode .cfg |= QSPI_CFG_ADDR_SIZE_32;
+ }
+
+ mode.addr = offset;
+ mode.alt = 0U;
+ qspiReceive(busp, &mode, n, p);
+#else
+ uint8_t buf[4];
+
+ spiSelect(busp);
+ buf[0] = cmd;
+ buf[1] = (uint8_t)(addr >> 16);
+ buf[2] = (uint8_t)(addr >> 8);
+ buf[3] = (uint8_t)(addr >> 0);
+ spiSend(busp, 4, buf);
+ spiReceive(busp, n, p);
+ spiUnselect(busp);
+#endif
+}
+
+#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__)
+void jesd216_cmd_addr_dummy_receive(BUSDriver *busp,
+ uint32_t cmd,
+ flash_offset_t offset,
+ uint8_t dummy,
+ size_t n,
+ uint8_t *p) {
+ qspi_command_t mode;
+
+ mode.cfg = QSPI_CFG_CMD(cmd & 0xFFU) |
+#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L
+ QSPI_CFG_CMD_MODE_ONE_LINE |
+ QSPI_CFG_ADDR_MODE_ONE_LINE |
+ QSPI_CFG_DUMMY_CYCLES(dummy) |
+ QSPI_CFG_DATA_MODE_ONE_LINE;
+#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L
+ QSPI_CFG_CMD_MODE_TWO_LINES |
+ QSPI_CFG_ADDR_MODE_TWO_LINES |
+ QSPI_CFG_DUMMY_CYCLES(dummy) |
+ QSPI_CFG_DATA_MODE_TWO_LINES;
+#else
+ QSPI_CFG_CMD_MODE_FOUR_LINES |
+ QSPI_CFG_ADDR_MODE_FOUR_LINES |
+ QSPI_CFG_DUMMY_CYCLES(dummy) |
+ QSPI_CFG_DATA_MODE_FOUR_LINES;
+#endif
+
+ /* Handling 32 bits addressing.*/
+ if ((cmd & JESD216_CMD_EXTENDED_ADDRESSING) == 0) {
+ mode .cfg |= QSPI_CFG_ADDR_SIZE_24;
+ }
+ else {
+ mode .cfg |= QSPI_CFG_ADDR_SIZE_32;
+ }
+
+ mode.addr = offset;
+ mode.alt = 0U;
+ qspiReceive(busp, &mode, n, p);
+}
+#endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */
+
+#if ((JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) && \
+ (JESD216_SHARED_BUS == TRUE)) || defined(__DOXYGEN__)
+void jesd216_bus_acquire(BUSDriver *busp, const BUSConfig *config) {
+
+ (void)config;
+
+ qspiAcquireBus(busp);
+ if (busp->config != config) {
+ qspiStart(busp, config);
+ }
+}
+
+void jesd216_bus_release(BUSDriver *busp) {
+
+ qspiReleaseBus(busp);
+}
+#elif (JESD216_BUS_MODE == JESD216_BUS_MODE_SPI) && \
+ (JESD216_SHARED_BUS == TRUE)
+void jesd216_bus_acquire(BUSDriver *busp, const BUSConfig *config) {
+
+ spiAcquireBus(busp);
+ if (busp->config != config) {
+ spiStart(busp, config);
+ }
+}
+
+void jesd216_bus_release(BUSDriver *busp) {
+
+ spiReleaseBus(busp);
+}
+#else
+#define jesd216_bus_acquire(busp)
+#define jesd216_bus_release(busp)
+#endif
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_jesd216_flash.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_jesd216_flash.h
new file mode 100644
index 0000000000..3f63593359
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/flash/hal_jesd216_flash.h
@@ -0,0 +1,222 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_jesd216_flash.h
+ * @brief JESD216 compliant flash driver class header.
+ *
+ * @addtogroup HAL_JESD216_FLASH
+ * @{
+ */
+
+#ifndef HAL_JESD216_FLASH_H
+#define HAL_JESD216_FLASH_H
+
+#include "hal_flash.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Common command codes
+ * @{
+ */
+#define JESD216_CMD_READ_ID 0x9FU
+#define JESD216_CMD_READ 0x03U
+#define JESD216_CMD_WRITE_ENABLE 0x06U
+#define JESD216_CMD_WRITE_DISABLE 0x04U
+#define JESD216_CMD_READ_STATUS_REGISTER 0x05U
+#define JESD216_CMD_WRITE_STATUS_REGISTER 0x01U
+#define JESD216_CMD_PAGE_PROGRAM 0x02U
+#define JESD216_CMD_ERASE_4K 0x20U
+#define JESD216_CMD_ERASE_BULK 0xC7U
+#define JESD216_CMD_PROGRAM_ERASE_RESUME 0x7AU
+#define JESD216_CMD_PROGRAM_ERASE_SUSPEND 0x75U
+#define JESD216_CMD_READ_OTP_ARRAY 0x4BU
+#define JESD216_CMD_PROGRAM_OTP_ARRAY 0x42U
+/** @} */
+
+/**
+ * @name Command options
+ * @{
+ */
+#define JESD216_CMD_EXTENDED_ADDRESSING 0x80000000U
+/** @} */
+
+/**
+ * @name Bus interface.
+ * @{
+ */
+#define JESD216_BUS_MODE_SPI 0U
+#define JESD216_BUS_MODE_QSPI1L 1U
+#define JESD216_BUS_MODE_QSPI2L 2U
+#define JESD216_BUS_MODE_QSPI4L 4U
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Physical transport interface.
+ */
+#if !defined(JESD216_BUS_MODE) || defined(__DOXYGEN__)
+#define JESD216_BUS_MODE JESD216_BUS_MODE_QSPI4L
+#endif
+
+/**
+ * @brief Shared bus switch.
+ * @details If set to @p TRUE the device acquires bus ownership
+ * on each transaction.
+ * @note Requires @p SPI_USE_MUTUAL_EXCLUSION or
+ * @p SPI_USE_MUTUAL_EXCLUSION.
+ */
+#if !defined(JESD216_SHARED_BUS) || defined(__DOXYGEN__)
+#define JESD216_SHARED_BUS TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if (JESD216_BUS_MODE == JESD216_BUS_MODE_SPI) && (HAL_USE_SPI == FALSE)
+#error "JESD216_BUS_MODE_SPI requires HAL_USE_SPI"
+#endif
+
+#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) && (HAL_USE_QSPI == FALSE)
+#error "JESD216_BUS_MODE_QSPIxL requires HAL_USE_QSPI"
+#endif
+
+#if (JESD216_BUS_MODE == JESD216_BUS_MODE_SPI) && \
+ (JESD216_SHARED_BUS == TRUE) && \
+ (SPI_USE_MUTUAL_EXCLUSION == FALSE)
+#error "JESD216_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION"
+#endif
+
+#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) && \
+ (JESD216_BUS_MODE != JESD216_BUS_MODE_QSPI1L) && \
+ (JESD216_BUS_MODE != JESD216_BUS_MODE_QSPI2L) && \
+ (JESD216_BUS_MODE != JESD216_BUS_MODE_QSPI4L)
+#error "invalid JESD216_BUS_MODE selected"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__)
+#define BUSConfig QSPIConfig
+#define BUSDriver QSPIDriver
+#else
+#define BUSConfig SPIConfig
+#define BUSDriver SPIDriver
+#endif
+
+#define _jesd216_config \
+ BUSDriver *busp; \
+ const BUSConfig *buscfg;
+
+/**
+ * @brief @p JESD215Flash specific methods.
+ * @note No methods so far, just a common ancestor interface.
+ */
+#define _jesd216_flash_methods_alone \
+ /* Read SFDP.*/ \
+ flash_error_t (*read_sfdp)(void *instance, \
+ flash_offset_t offset, \
+ size_t n, \
+ uint8_t *rp);
+
+/**
+ * @brief @p JESD215Flash specific methods with inherited ones.
+ */
+#define _jesd216_flash_methods \
+ _base_flash_methods \
+ _jesd216_flash_methods_alone
+
+/**
+ * @brief @p JESD215Flash virtual methods table.
+ */
+struct JESD215FlashVMT {
+ _jesd216_flash_methods
+};
+
+/**
+ * @brief @p JESD215Flash specific data.
+ */
+#define _jesd216_flash_data \
+ _base_flash_data
+
+/**
+ * @brief Base flash class.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct JESD215FlashVMT *vmt;
+ _jesd216_flash_data
+} JESD215Flash;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions (BaseFlash)
+ * @{
+ */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void jesd216_start(BUSDriver *busp, const BUSConfig *config);
+ void jesd216_stop(BUSDriver *busp);
+ void jesd216_cmd(BUSDriver *busp, uint32_t cmd);
+ void jesd216_cmd_receive(BUSDriver *busp, uint32_t cmd,
+ size_t n, uint8_t *p);
+ void jesd216_cmd_send(BUSDriver *busp, uint32_t cmd,
+ size_t n, const uint8_t *p);
+ void jesd216_cmd_addr(BUSDriver *busp, uint32_t cmd, flash_offset_t offset);
+ void jesd216_cmd_addr_send(BUSDriver *busp, uint32_t cmd,
+ flash_offset_t offset, size_t n, const uint8_t *p);
+ void jesd216_cmd_addr_receive(BUSDriver *busp, uint32_t cmd,
+ flash_offset_t offset, size_t n, uint8_t *p);
+#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI
+ void jesd216_cmd_addr_dummy_receive(BUSDriver *busp, uint32_t cmd,
+ flash_offset_t offset, uint8_t dummy,
+ size_t n, uint8_t *p);
+#endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */
+#if JESD216_SHARED_BUS == TRUE
+ void jesd216_bus_acquire(BUSDriver *busp, const BUSConfig *config);
+ void jesd216_bus_release(BUSDriver *busp);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_JESD216_FLASH_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_accelerometer.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_accelerometer.h
new file mode 100644
index 0000000000..7e0141561e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_accelerometer.h
@@ -0,0 +1,217 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_accelerometer.h
+ * @brief Generic accelerometer interface header.
+ *
+ * @addtogroup HAL_ACCELEROMETER
+ * @{
+ */
+
+#ifndef HAL_ACCELEROMETER_H
+#define HAL_ACCELEROMETER_H
+
+#include "hal_sensors.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief BaseAccelerometer specific methods.
+ */
+#define _base_accelerometer_methods_alone \
+ /* Invoke the set bias procedure.*/ \
+ msg_t (*set_bias)(void *instance, float biases[]); \
+ /* Remove bias stored data.*/ \
+ msg_t (*reset_bias)(void *instance); \
+ /* Invoke the set sensitivity procedure.*/ \
+ msg_t (*set_sensitivity)(void *instance, float sensitivities[]); \
+ /* Restore sensitivity stored data to default.*/ \
+ msg_t (*reset_sensitivity)(void *instance);
+
+/**
+ * @brief BaseAccelerometer specific methods with inherited ones.
+ */
+#define _base_accelerometer_methods \
+ _base_sensor_methods \
+ _base_accelerometer_methods_alone
+
+/**
+ * @brief @p BaseAccelerometer virtual methods table.
+ */
+struct BaseAccelerometerVMT {
+ _base_accelerometer_methods
+};
+
+/**
+ * @brief @p BaseAccelerometer specific data.
+ */
+#define _base_accelerometer_data \
+ _base_sensor_data
+
+/**
+ * @brief Base accelerometer class.
+ * @details This class represents a generic a generic accelerometer.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseAccelerometerVMT *vmt_baseaccelerometer;
+ _base_sensor_data
+} BaseAccelerometer;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions (BaseAccelerometer)
+ * @{
+ */
+/**
+ * @brief Accelerometer get axes number.
+ *
+ * @param[in] ip pointer to a @p BaseAccelerometer class.
+ * @return The number of axes of the BaseAccelerometer
+ *
+ * @api
+ */
+#define accelerometerGetAxesNumber(ip) \
+ (ip)->vmt_baseaccelerometer->get_channels_number(ip)
+
+/**
+ * @brief Accelerometer read raw data.
+ *
+ * @param[in] ip pointer to a @p BaseAccelerometer class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define accelerometerReadRaw(ip, dp) \
+ (ip)->vmt_baseaccelerometer->read_raw(ip, dp)
+
+/**
+ * @brief Accelerometer read cooked data.
+ *
+ * @param[in] ip pointer to a @p BaseAccelerometer class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define accelerometerReadCooked(ip, dp) \
+ (ip)->vmt_baseaccelerometer->read_cooked(ip, dp)
+
+/**
+ * @brief Updates accelerometer bias data from received buffer.
+ * @note The bias buffer must have the same length of the
+ * the accelerometer axes number.
+ *
+ *
+ * @param[in] ip pointer to a @p BaseAccelerometer class.
+ * @param[in] bp pointer to a buffer of bias values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define accelerometerSetBias(ip, bp) \
+ (ip)->vmt_baseaccelerometer->set_bias(ip, bp)
+
+/**
+ * @brief Reset accelerometer bias data restoring it to zero.
+ *
+ * @param[in] ip pointer to a @p BaseAccelerometer class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define accelerometerResetBias(ip) \
+ (ip)->vmt_baseaccelerometer->reset_bias(ip)
+
+/**
+ * @brief Updates accelerometer sensitivity data from received buffer.
+ * @note The sensitivity buffer must have the same length of the
+ * the accelerometer axes number.
+ *
+ * @param[in] ip pointer to a @p BaseAccelerometer class.
+ * @param[in] sp pointer to a buffer of sensitivity values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define accelerometerSetSensitivity(ip, sp) \
+ (ip)->vmt_baseaccelerometer->set_sensitivity(ip, sp)
+
+/**
+ * @brief Reset accelerometer sensitivity data restoring it to its typical
+ * value.
+ *
+ * @param[in] ip pointer to a @p BaseAccelerometer class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define accelerometerResetSensitivity(ip) \
+ (ip)->vmt_baseaccelerometer->reset_sensitivity(ip)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_ACCELEROMETER_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_barometer.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_barometer.h
new file mode 100644
index 0000000000..c9daa7e7b2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_barometer.h
@@ -0,0 +1,216 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_barometer.h
+ * @brief Generic barometer interface header.
+ *
+ * @addtogroup HAL_BAROMETER
+ * @{
+ */
+
+#ifndef HAL_BAROMETER_H
+#define HAL_BAROMETER_H
+
+#include "hal_sensors.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief BaseBarometer specific methods.
+ */
+#define _base_barometer_methods_alone \
+ /* Invoke the set bias procedure.*/ \
+ msg_t (*set_bias)(void *instance, float biases[]); \
+ /* Remove bias stored data.*/ \
+ msg_t (*reset_bias)(void *instance); \
+ /* Invoke the set sensitivity procedure.*/ \
+ msg_t (*set_sensitivity)(void *instance, float sensitivities[]); \
+ /* Restore sensitivity stored data to default.*/ \
+ msg_t (*reset_sensitivity)(void *instance);
+
+
+/**
+ * @brief BaseBarometer specific methods with inherited ones.
+ */
+#define _base_barometer_methods \
+ _base_sensor_methods \
+ _base_barometer_methods_alone
+
+/**
+ * @brief @p BaseBarometer virtual methods table.
+ */
+struct BaseBarometerVMT {
+ _base_barometer_methods
+};
+
+/**
+ * @brief @p BaseBarometer specific data.
+ */
+#define _base_barometer_data \
+ _base_sensor_data
+
+/**
+ * @brief Base barometer class.
+ * @details This class represents a generic barometer.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseBarometerVMT *vmt_basebarometer;
+ _base_barometer_data
+} BaseBarometer;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+/**
+ * @name Macro Functions (BaseBarometer)
+ * @{
+ */
+/**
+ * @brief Barometer get channels number.
+ *
+ * @param[in] ip pointer to a @p BaseBarometer class.
+ * @return The number of channels of the BaseBarometer
+ *
+ * @api
+ */
+#define barometerGetChannelsNumber(ip) \
+ (ip)->vmt_basebarometer->get_channels_number(ip)
+
+/**
+ * @brief Barometer read raw data.
+ *
+ * @param[in] ip pointer to a @p BaseBarometer class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define barometerReadRaw(ip, dp) \
+ (ip)->vmt_basebarometer->read_raw(ip, dp)
+
+/**
+ * @brief Barometer read cooked data.
+ *
+ * @param[in] ip pointer to a @p BaseBarometer class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define barometerReadCooked(ip, dp) \
+ (ip)->vmt_basebarometer->read_cooked(ip, dp)
+
+/**
+ * @brief Updates barometer bias data from received buffer.
+ * @note The bias buffer must have the same length of the
+ * the barometer channels number.
+ *
+ * @param[in] ip pointer to a @p BaseBarometer class.
+ * @param[in] bp pointer to a buffer of bias values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define barometerSetBias(ip, bp) \
+ (ip)->vmt_basebarometer->set_bias(ip, bp)
+
+/**
+ * @brief Reset barometer bias data restoring it to zero.
+ *
+ * @param[in] ip pointer to a @p BaseBarometer class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define barometerResetBias(ip) \
+ (ip)->vmt_basebarometer->reset_bias(ip)
+
+/**
+ * @brief Updates barometer sensitivity data from received buffer.
+ * @note The sensitivity buffer must have the same length of the
+ * the barometer channels number.
+ *
+ * @param[in] ip pointer to a @p BaseBarometer class.
+ * @param[in] sp pointer to a buffer of sensitivity values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define barometerSetSensitivity(ip, sp) \
+ (ip)->vmt_basebarometer->set_sensitivity(ip, sp)
+
+/**
+ * @brief Reset barometer sensitivity data restoring it to its typical
+ * value.
+ *
+ * @param[in] ip pointer to a @p BaseBarometer class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define barometerResetSensitivity(ip) \
+ (ip)->vmt_basebarometer->reset_sensitivity(ip)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_BAROMETER_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_compass.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_compass.h
new file mode 100644
index 0000000000..1814bc07fb
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_compass.h
@@ -0,0 +1,216 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_compass.h
+ * @brief Generic compass interface header.
+ *
+ * @addtogroup HAL_COMPASS
+ * @{
+ */
+
+#ifndef HAL_COMPASS_H
+#define HAL_COMPASS_H
+
+#include "hal_sensors.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief BaseCompass specific methods.
+ */
+#define _base_compass_methods_alone \
+ /* Invoke the set bias procedure.*/ \
+ msg_t (*set_bias)(void *instance, float biases[]); \
+ /* Remove bias stored data.*/ \
+ msg_t (*reset_bias)(void *instance); \
+ /* Invoke the set sensitivity procedure.*/ \
+ msg_t (*set_sensitivity)(void *instance, float sensitivities[]); \
+ /* Restore sensitivity stored data to default.*/ \
+ msg_t (*reset_sensitivity)(void *instance);
+
+
+/**
+ * @brief BaseCompass specific methods with inherited ones.
+ */
+#define _base_compass_methods \
+ _base_sensor_methods \
+ _base_compass_methods_alone
+
+/**
+ * @brief @p BaseCompass virtual methods table.
+ */
+struct BaseCompassVMT {
+ _base_compass_methods
+};
+
+/**
+ * @brief @p BaseCompass specific data.
+ */
+#define _base_compass_data \
+ _base_sensor_data
+
+/**
+ * @brief Base compass class.
+ * @details This class represents a generic compass.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseCompassVMT *vmt_basecompass;
+ _base_compass_data
+} BaseCompass;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+/**
+ * @name Macro Functions (BaseCompass)
+ * @{
+ */
+/**
+ * @brief Compass get axes number.
+ *
+ * @param[in] ip pointer to a @p BaseCompass class.
+ * @return The number of axes of the BaseCompass
+ *
+ * @api
+ */
+#define compassGetAxesNumber(ip) \
+ (ip)->vmt_basecompass->get_channels_number(ip)
+
+/**
+ * @brief Compass read raw data.
+ *
+ * @param[in] ip pointer to a @p BaseCompass class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define compassReadRaw(ip, dp) \
+ (ip)->vmt_basecompass->read_raw(ip, dp)
+
+/**
+ * @brief Compass read cooked data.
+ *
+ * @param[in] ip pointer to a @p BaseCompass class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define compassReadCooked(ip, dp) \
+ (ip)->vmt_basecompass->read_cooked(ip, dp)
+
+/**
+ * @brief Updates compass bias data from received buffer.
+ * @note The bias buffer must have the same length of the
+ * the compass axes number.
+ *
+ * @param[in] ip pointer to a @p BaseCompass class.
+ * @param[in] bp pointer to a buffer of bias values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define compassSetBias(ip, bp) \
+ (ip)->vmt_basecompass->set_bias(ip, bp)
+
+/**
+ * @brief Reset compass bias data restoring it to zero.
+ *
+ * @param[in] ip pointer to a @p BaseCompass class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define compassResetBias(ip) \
+ (ip)->vmt_basecompass->reset_bias(ip)
+
+/**
+ * @brief Updates compass sensitivity data from received buffer.
+ * @note The sensitivity buffer must have the same length of the
+ * the compass axes number.
+ *
+ * @param[in] ip pointer to a @p BaseCompass class.
+ * @param[in] sp pointer to a buffer of sensitivity values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define compassSetSensitivity(ip, sp) \
+ (ip)->vmt_basecompass->set_sensitivity(ip, sp)
+
+/**
+ * @brief Reset compass sensitivity data restoring it to its typical
+ * value.
+ *
+ * @param[in] ip pointer to a @p BaseCompass class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define compassResetSensitivity(ip) \
+ (ip)->vmt_basecompass->reset_sensitivity(ip)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_COMPASS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_gyroscope.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_gyroscope.h
new file mode 100644
index 0000000000..18ce625b90
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_gyroscope.h
@@ -0,0 +1,236 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_gyroscope.h
+ * @brief Generic gyroscope interface header.
+ *
+ * @addtogroup HAL_GYROSCOPE
+ * @{
+ */
+
+#ifndef HAL_GYROSCOPE_H
+#define HAL_GYROSCOPE_H
+
+#include "hal_sensors.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief BaseGyroscope specific methods.
+ */
+#define _base_gyroscope_methods_alone \
+ /* Invoke the sample bias procedure.*/ \
+ msg_t (*sample_bias)(void *instance); \
+ /* Invoke the set bias procedure.*/ \
+ msg_t (*set_bias)(void *instance, float biases[]); \
+ /* Remove bias stored data.*/ \
+ msg_t (*reset_bias)(void *instance); \
+ /* Invoke the set sensitivity procedure.*/ \
+ msg_t (*set_sensitivity)(void *instance, float sensitivities[]); \
+ /* Restore sensitivity stored data to default.*/ \
+ msg_t (*reset_sensitivity)(void *instance);
+
+
+/**
+ * @brief BaseGyroscope specific methods with inherited ones.
+ */
+#define _base_gyroscope_methods \
+ _base_sensor_methods \
+ _base_gyroscope_methods_alone
+
+/**
+ * @brief @p BaseGyroscope virtual methods table.
+ */
+struct BaseGyroscopeVMT {
+ _base_gyroscope_methods
+};
+
+/**
+ * @brief @p BaseGyroscope specific data.
+ */
+#define _base_gyroscope_data \
+ _base_sensor_data
+
+/**
+ * @brief Base gyroscope class.
+ * @details This class represents a generic gyroscope.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseGyroscopeVMT *vmt_basegyroscope;
+ _base_gyroscope_data
+} BaseGyroscope;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions (BaseGyroscope)
+ * @{
+ */
+/**
+ * @brief Gyroscope get axes number.
+ *
+ * @param[in] ip pointer to a @p BaseGyroscope class.
+ * @return The number of axes of the BaseGyroscope
+ *
+ * @api
+ */
+#define gyroscopeGetAxesNumber(ip) \
+ (ip)->vmt_basegyroscope->get_channels_number(ip)
+
+/**
+ * @brief Gyroscope read raw data.
+ *
+ * @param[in] ip pointer to a @p BaseGyroscope class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define gyroscopeReadRaw(ip, dp) \
+ (ip)->vmt_basegyroscope->read_raw(ip, dp)
+
+/**
+ * @brief Gyroscope read cooked data.
+ *
+ * @param[in] ip pointer to a @p BaseGyroscope class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define gyroscopeReadCooked(ip, dp) \
+ (ip)->vmt_basegyroscope->read_cooked(ip, dp)
+
+/**
+ * @brief Gyroscope bias sampling procedure.
+ * @note During this procedure gyroscope must be kept hold in the rest
+ * position. Sampled bias will be automatically removed after
+ * calling this procedure.
+ *
+ * @param[in] ip pointer to a @p BaseGyroscope class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define gyroscopeSampleBias(ip) \
+ (ip)->vmt_basegyroscope->sample_bias(ip)
+
+/**
+ * @brief Updates gyroscope bias data from received buffer.
+ * @note The bias buffer must have the same length of the
+ * the gyroscope axes number.
+ *
+ * @param[in] ip pointer to a @p BaseGyroscope class.
+ * @param[in] bp pointer to a buffer of bias values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define gyroscopeSetBias(ip, bp) \
+ (ip)->vmt_basegyroscope->set_bias(ip, bp)
+
+/**
+ * @brief Reset gyroscope bias data restoring it to zero.
+ *
+ * @param[in] ip pointer to a @p BaseGyroscope class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define gyroscopeResetBias(ip) \
+ (ip)->vmt_basegyroscope->reset_bias(ip)
+
+/**
+ * @brief Updates gyroscope sensitivity data from received buffer.
+ * @note The sensitivity buffer must have the same length of the
+ * the gyroscope axes number.
+ *
+ * @param[in] ip pointer to a @p BaseGyroscope class.
+ * @param[in] sp pointer to a buffer of sensitivity values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define gyroscopeSetSensitivity(ip, sp) \
+ (ip)->vmt_basegyroscope->set_sensitivity(ip, sp)
+
+/**
+ * @brief Reset gyroscope sensitivity data restoring it to its typical
+ * value.
+ *
+ * @param[in] ip pointer to a @p BaseGyroscope class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define gyroscopeResetSensitivity(ip) \
+ (ip)->vmt_basegyroscope->reset_sensitivity(ip)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_GYROSCOPE_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_hygrometer.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_hygrometer.h
new file mode 100644
index 0000000000..59f067a502
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_hygrometer.h
@@ -0,0 +1,216 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_hygrometer.h
+ * @brief Generic hygrometer interface header.
+ *
+ * @addtogroup HAL_HYGROMETER
+ * @{
+ */
+
+#ifndef HAL_HYGROMETER_H
+#define HAL_HYGROMETER_H
+
+#include "hal_sensors.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief BaseHygrometer specific methods.
+ */
+#define _base_hygrometer_methods_alone \
+ /* Invoke the set bias procedure.*/ \
+ msg_t (*set_bias)(void *instance, float biases[]); \
+ /* Remove bias stored data.*/ \
+ msg_t (*reset_bias)(void *instance); \
+ /* Invoke the set sensitivity procedure.*/ \
+ msg_t (*set_sensitivity)(void *instance, float sensitivities[]); \
+ /* Restore sensitivity stored data to default.*/ \
+ msg_t (*reset_sensitivity)(void *instance);
+
+
+/**
+ * @brief BaseHygrometer specific methods with inherited ones.
+ */
+#define _base_hygrometer_methods \
+ _base_sensor_methods \
+ _base_hygrometer_methods_alone
+
+/**
+ * @brief @p BaseHygrometer virtual methods table.
+ */
+struct BaseHygrometerVMT {
+ _base_hygrometer_methods
+};
+
+/**
+ * @brief @p BaseHygrometer specific data.
+ */
+#define _base_hygrometer_data \
+ _base_sensor_data
+
+/**
+ * @brief Base hygrometer class.
+ * @details This class represents a generic hygrometer.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseHygrometerVMT *vmt_basehygrometer;
+ _base_hygrometer_data
+} BaseHygrometer;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+/**
+ * @name Macro Functions (BaseHygrometer)
+ * @{
+ */
+/**
+ * @brief Hygrometer get channels number.
+ *
+ * @param[in] ip pointer to a @p BaseHygrometer class.
+ * @return The number of channels of the BaseHygrometer
+ *
+ * @api
+ */
+#define hygrometerGetChannelsNumber(ip) \
+ (ip)->vmt_basehygrometer->get_channels_number(ip)
+
+/**
+ * @brief Hygrometer read raw data.
+ *
+ * @param[in] ip pointer to a @p BaseHygrometer class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define hygrometerReadRaw(ip, dp) \
+ (ip)->vmt_basehygrometer->read_raw(ip, dp)
+
+/**
+ * @brief Hygrometer read cooked data.
+ *
+ * @param[in] ip pointer to a @p BaseHygrometer class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define hygrometerReadCooked(ip, dp) \
+ (ip)->vmt_basehygrometer->read_cooked(ip, dp)
+
+/**
+ * @brief Updates hygrometer bias data from received buffer.
+ * @note The bias buffer must have the same length of the
+ * the hygrometer channels number.
+ *
+ * @param[in] ip pointer to a @p BaseHygrometer class.
+ * @param[in] bp pointer to a buffer of bias values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define hygrometerSetBias(ip, bp) \
+ (ip)->vmt_basehygrometer->set_bias(ip, bp)
+
+/**
+ * @brief Reset hygrometer bias data restoring it to zero.
+ *
+ * @param[in] ip pointer to a @p BaseHygrometer class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define hygrometerResetBias(ip) \
+ (ip)->vmt_basehygrometer->reset_bias(ip)
+
+/**
+ * @brief Updates hygrometer sensitivity data from received buffer.
+ * @note The sensitivity buffer must have the same length of the
+ * the hygrometer channels number.
+ *
+ * @param[in] ip pointer to a @p BaseHygrometer class.
+ * @param[in] sp pointer to a buffer of sensitivity values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define hygrometerSetSensitivity(ip, sp) \
+ (ip)->vmt_basehygrometer->set_sensitivity(ip, sp)
+
+/**
+ * @brief Reset hygrometer sensitivity data restoring it to its typical
+ * value.
+ *
+ * @param[in] ip pointer to a @p BaseHygrometer class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define hygrometerResetSensitivity(ip) \
+ (ip)->vmt_basehygrometer->reset_sensitivity(ip)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_HYGROMETER_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_sensors.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_sensors.h
new file mode 100644
index 0000000000..ad07d93ab7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_sensors.h
@@ -0,0 +1,147 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_sensors.h
+ * @brief Generic sensors interface header.
+ *
+ * @addtogroup HAL_SENSORS
+ * @{
+ */
+
+#ifndef HAL_SENSORS_H
+#define HAL_SENSORS_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief BaseSensor specific methods.
+ */
+#define _base_sensor_methods_alone \
+ /* Get number of channels.*/ \
+ size_t (*get_channels_number)(void *instance); \
+ /* Reads the sensor raw data.*/ \
+ msg_t (*read_raw)(void *instance, int32_t axes[]); \
+ /* Reads the sensor returning normalized data.*/ \
+ msg_t (*read_cooked)(void *instance, float axes[]);
+
+/**
+ * @brief BaseSensor specific methods with inherited ones.
+ */
+#define _base_sensor_methods \
+ _base_sensor_methods_alone
+
+/**
+ * @brief @p BaseSensor virtual methods table.
+ */
+struct BaseSensorVMT {
+ _base_sensor_methods
+};
+
+/**
+ * @brief @p BaseSensor specific data.
+ * @note It is empty because @p BaseSensor is only an interface
+ * without implementation.
+ */
+#define _base_sensor_data
+
+/**
+ * @brief Base stream class.
+ * @details This class represents a generic blocking unbuffered sequential
+ * data stream.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseSensorVMT *vmt_basesensor;
+ _base_sensor_data
+} BaseSensor;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions (BaseSensor)
+ * @{
+ */
+/**
+ * @brief Sensors get channels number.
+ *
+ * @param[in] ip pointer to a @p BaseSensor or derived class.
+ * @return The number of channels of the BaseSensor
+ *
+ * @api
+ */
+#define sensorGetChannelNumber(ip) (ip)->vmt_basesensor->get_channels_number(ip)
+
+/**
+ * @brief Sensors read raw data.
+ *
+ * @param[in] ip pointer to a @p BaseSensor or derived class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define sensorReadRaw(ip, dp) (ip)->vmt_basesensor->read_raw(ip, dp)
+
+/**
+ * @brief Sensors read cooked data.
+ *
+ * @param[in] ip pointer to a @p BaseSensor or derived class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define sensorReadCooked(ip, dp) (ip)->vmt_basesensor->read_cooked(ip, dp)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_SENSORS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_thermometer.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_thermometer.h
new file mode 100644
index 0000000000..20457287c2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/peripherals/sensors/hal_thermometer.h
@@ -0,0 +1,216 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_thermometer.h
+ * @brief Generic thermometer interface header.
+ *
+ * @addtogroup HAL_THERMOMETER
+ * @{
+ */
+
+#ifndef HAL_THERMOMETER_H
+#define HAL_THERMOMETER_H
+
+#include "hal_sensors.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief BaseThermometer specific methods.
+ */
+#define _base_thermometer_methods_alone \
+ /* Invoke the set bias procedure.*/ \
+ msg_t (*set_bias)(void *instance, float biases[]); \
+ /* Remove bias stored data.*/ \
+ msg_t (*reset_bias)(void *instance); \
+ /* Invoke the set sensitivity procedure.*/ \
+ msg_t (*set_sensitivity)(void *instance, float sensitivities[]); \
+ /* Restore sensitivity stored data to default.*/ \
+ msg_t (*reset_sensitivity)(void *instance);
+
+
+/**
+ * @brief BaseThermometer specific methods with inherited ones.
+ */
+#define _base_thermometer_methods \
+ _base_sensor_methods \
+ _base_thermometer_methods_alone
+
+/**
+ * @brief @p BaseThermometer virtual methods table.
+ */
+struct BaseThermometerVMT {
+ _base_thermometer_methods
+};
+
+/**
+ * @brief @p BaseThermometer specific data.
+ */
+#define _base_thermometer_data \
+ _base_sensor_data
+
+/**
+ * @brief Base thermometer class.
+ * @details This class represents a generic thermometer.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct BaseThermometerVMT *vmt_basethermometer;
+ _base_thermometer_data
+} BaseThermometer;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+/**
+ * @name Macro Functions (BaseThermometer)
+ * @{
+ */
+/**
+ * @brief Thermometer get channels number.
+ *
+ * @param[in] ip pointer to a @p BaseThermometer class.
+ * @return The number of channels of the BaseThermometer
+ *
+ * @api
+ */
+#define thermometerGetChannelsNumber(ip) \
+ (ip)->vmt_basethermometer->get_channels_number(ip)
+
+/**
+ * @brief Thermometer read raw data.
+ *
+ * @param[in] ip pointer to a @p BaseThermometer class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define thermometerReadRaw(ip, dp) \
+ (ip)->vmt_basethermometer->read_raw(ip, dp)
+
+/**
+ * @brief Thermometer read cooked data.
+ *
+ * @param[in] ip pointer to a @p BaseThermometer class.
+ * @param[in] dp pointer to a data array.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define thermometerReadCooked(ip, dp) \
+ (ip)->vmt_basethermometer->read_cooked(ip, dp)
+
+/**
+ * @brief Updates thermometer bias data from received buffer.
+ * @note The bias buffer must have the same length of the
+ * the thermometer channels number.
+ *
+ * @param[in] ip pointer to a @p BaseThermometer class.
+ * @param[in] bp pointer to a buffer of bias values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define thermometerSetBias(ip, bp) \
+ (ip)->vmt_basethermometer->set_bias(ip, bp)
+
+/**
+ * @brief Reset thermometer bias data restoring it to zero.
+ *
+ * @param[in] ip pointer to a @p BaseThermometer class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define thermometerResetBias(ip) \
+ (ip)->vmt_basethermometer->reset_bias(ip)
+
+/**
+ * @brief Updates thermometer sensitivity data from received buffer.
+ * @note The sensitivity buffer must have the same length of the
+ * the thermometer channels number.
+ *
+ * @param[in] ip pointer to a @p BaseThermometer class.
+ * @param[in] sp pointer to a buffer of sensitivity values.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define thermometerSetSensitivity(ip, sp) \
+ (ip)->vmt_basethermometer->set_sensitivity(ip, sp)
+
+/**
+ * @brief Reset thermometer sensitivity data restoring it to its typical
+ * value.
+ *
+ * @param[in] ip pointer to a @p BaseThermometer class.
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more errors occurred.
+ *
+ * @api
+ */
+#define thermometerResetSensitivity(ip) \
+ (ip)->vmt_basethermometer->reset_sensitivity(ip)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_THERMOMETER_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/chprintf.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/chprintf.c
similarity index 67%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/various/chprintf.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/chprintf.c
index 83d79457df..d40f967a2c 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/chprintf.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/chprintf.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -27,12 +27,12 @@
* @{
*/
-#include "ch.h"
+#include "hal.h"
#include "chprintf.h"
#include "memstreams.h"
#define MAX_FILLER 11
-#define FLOAT_PRECISION 100000
+#define FLOAT_PRECISION 9
static char *long_to_string_with_divisor(char *p,
long num,
@@ -67,15 +67,22 @@ static char *long_to_string_with_divisor(char *p,
return p;
}
-static char *ltoa(char *p, long num, unsigned radix) {
+static char *ch_ltoa(char *p, long num, unsigned radix) {
return long_to_string_with_divisor(p, num, radix, 0);
}
#if CHPRINTF_USE_FLOAT
-static char *ftoa(char *p, double num) {
+static const long pow10[FLOAT_PRECISION] = {
+ 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000
+};
+
+static char *ftoa(char *p, double num, unsigned long precision) {
long l;
- unsigned long precision = FLOAT_PRECISION;
+
+ if ((precision == 0) || (precision > FLOAT_PRECISION))
+ precision = FLOAT_PRECISION;
+ precision = pow10[precision - 1];
l = (long)num;
p = long_to_string_with_divisor(p, l, 10, 0);
@@ -106,13 +113,16 @@ static char *ftoa(char *p, double num) {
* @param[in] chp pointer to a @p BaseSequentialStream implementing object
* @param[in] fmt formatting string
* @param[in] ap list of parameters
+ * @return The number of bytes that would have been
+ * written to @p chp if no stream error occurs
*
* @api
*/
-void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
+int chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
char *p, *s, c, filler;
int i, precision, width;
- bool_t is_long, left_align;
+ int n = 0;
+ bool is_long, left_align;
long l;
#if CHPRINTF_USE_FLOAT
float f;
@@ -121,12 +131,13 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
char tmpbuf[MAX_FILLER + 1];
#endif
- while (TRUE) {
+ while (true) {
c = *fmt++;
if (c == 0)
- return;
+ return n;
if (c != '%') {
- chSequentialStreamPut(chp, (uint8_t)c);
+ streamPut(chp, (uint8_t)c);
+ n++;
continue;
}
p = tmpbuf;
@@ -137,7 +148,7 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
left_align = TRUE;
}
filler = ' ';
- if ((*fmt == '.') || (*fmt == '0')) {
+ if (*fmt == '0') {
fmt++;
filler = '0';
}
@@ -202,7 +213,7 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
*p++ = '-';
l = -l;
}
- p = ltoa(p, l, 10);
+ p = ch_ltoa(p, l, 10);
break;
#if CHPRINTF_USE_FLOAT
case 'f':
@@ -211,7 +222,7 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
*p++ = '-';
f = -f;
}
- p = ftoa(p, f);
+ p = ftoa(p, f, precision);
break;
#endif
case 'X':
@@ -230,7 +241,7 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
l = va_arg(ap, unsigned long);
else
l = va_arg(ap, unsigned int);
- p = ltoa(p, l, c);
+ p = ch_ltoa(p, l, c);
break;
default:
*p++ = c;
@@ -243,18 +254,23 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
width = -width;
if (width < 0) {
if (*s == '-' && filler == '0') {
- chSequentialStreamPut(chp, (uint8_t)*s++);
+ streamPut(chp, (uint8_t)*s++);
+ n++;
i--;
}
do {
- chSequentialStreamPut(chp, (uint8_t)filler);
+ streamPut(chp, (uint8_t)filler);
+ n++;
} while (++width != 0);
}
- while (--i >= 0)
- chSequentialStreamPut(chp, (uint8_t)*s++);
+ while (--i >= 0) {
+ streamPut(chp, (uint8_t)*s++);
+ n++;
+ }
while (width) {
- chSequentialStreamPut(chp, (uint8_t)filler);
+ streamPut(chp, (uint8_t)filler);
+ n++;
width--;
}
}
@@ -262,7 +278,7 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
/**
* @brief System formatted output function.
- * @details This function implements a minimal @p vprintf()-like functionality
+ * @details This function implements a minimal @p printf() like functionality
* with output on a @p BaseSequentialStream.
* The general parameters format is: %[-][width|*][.precision|*][l|L]p.
* The following parameter types (p) are supported:
@@ -278,10 +294,46 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
* - s string.
* .
*
+ * @param[in] chp pointer to a @p BaseSequentialStream implementing object
+ * @param[in] fmt formatting string
+ *
+ * @api
+ */
+int chprintf(BaseSequentialStream *chp, const char *fmt, ...) {
+ va_list ap;
+ int formatted_bytes;
+
+ va_start(ap, fmt);
+ formatted_bytes = chvprintf(chp, fmt, ap);
+ va_end(ap);
+
+ return formatted_bytes;
+}
+
+/**
+ * @brief System formatted output function.
+ * @details This function implements a minimal @p snprintf()-like functionality.
+ * The general parameters format is: %[-][width|*][.precision|*][l|L]p.
+ * The following parameter types (p) are supported:
+ * - x hexadecimal integer.
+ * - X hexadecimal long.
+ * - o octal integer.
+ * - O octal long.
+ * - d decimal signed integer.
+ * - D decimal signed long.
+ * - u decimal unsigned integer.
+ * - U decimal unsigned long.
+ * - c character.
+ * - s string.
+ * .
+ * @post @p str is NUL-terminated, unless @p size is 0.
+ *
* @param[in] str pointer to a buffer
* @param[in] size maximum size of the buffer
* @param[in] fmt formatting string
- * @return The size of the generated string.
+ * @return The number of characters (excluding the
+ * terminating NUL byte) that would have been
+ * stored in @p str if there was room.
*
* @api
*/
@@ -289,19 +341,30 @@ int chsnprintf(char *str, size_t size, const char *fmt, ...) {
va_list ap;
MemoryStream ms;
BaseSequentialStream *chp;
+ size_t size_wo_nul;
+ int retval;
- /* Memory stream object to be used as a string writer.*/
- msObjectInit(&ms, (uint8_t *)str, size, 0);
+ if (size > 0)
+ size_wo_nul = size - 1;
+ else
+ size_wo_nul = 0;
+
+ /* Memory stream object to be used as a string writer, reserving one
+ byte for the final zero.*/
+ msObjectInit(&ms, (uint8_t *)str, size_wo_nul, 0);
/* Performing the print operation using the common code.*/
- chp = (BaseSequentialStream *)&ms;
+ chp = (BaseSequentialStream *)(void *)&ms;
va_start(ap, fmt);
- chvprintf(chp, fmt, ap);
+ retval = chvprintf(chp, fmt, ap);
va_end(ap);
- /* Final zero and size return.*/
- chSequentialStreamPut(chp, 0);
- return ms.eos - 1;
+ /* Terminate with a zero, unless size==0.*/
+ if (ms.eos < size)
+ str[ms.eos] = 0;
+
+ /* Return number of bytes that would have been written.*/
+ return retval;
}
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/chprintf.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/chprintf.h
new file mode 100644
index 0000000000..0005e8f077
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/chprintf.h
@@ -0,0 +1,49 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file chprintf.h
+ * @brief Mini printf-like functionality.
+ *
+ * @addtogroup chprintf
+ * @{
+ */
+
+#ifndef CHPRINTF_H
+#define CHPRINTF_H
+
+#include
+
+/**
+ * @brief Float type support.
+ */
+#if !defined(CHPRINTF_USE_FLOAT) || defined(__DOXYGEN__)
+#define CHPRINTF_USE_FLOAT FALSE
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ int chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap);
+ int chprintf(BaseSequentialStream *chp, const char *fmt, ...);
+ int chsnprintf(char *str, size_t size, const char *fmt, ...);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CHPRINTF_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/memstreams.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/memstreams.c
similarity index 89%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/various/memstreams.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/memstreams.c
index 095c65e0f5..8547b60dac 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/memstreams.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/memstreams.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -24,7 +24,7 @@
#include
-#include "ch.h"
+#include "hal.h"
#include "memstreams.h"
/*===========================================================================*/
@@ -43,7 +43,7 @@
/* Driver local functions. */
/*===========================================================================*/
-static size_t writes(void *ip, const uint8_t *bp, size_t n) {
+static size_t _writes(void *ip, const uint8_t *bp, size_t n) {
MemoryStream *msp = ip;
if (msp->size - msp->eos < n)
@@ -53,7 +53,7 @@ static size_t writes(void *ip, const uint8_t *bp, size_t n) {
return n;
}
-static size_t reads(void *ip, uint8_t *bp, size_t n) {
+static size_t _reads(void *ip, uint8_t *bp, size_t n) {
MemoryStream *msp = ip;
if (msp->eos - msp->offset < n)
@@ -63,28 +63,28 @@ static size_t reads(void *ip, uint8_t *bp, size_t n) {
return n;
}
-static msg_t put(void *ip, uint8_t b) {
+static msg_t _put(void *ip, uint8_t b) {
MemoryStream *msp = ip;
if (msp->size - msp->eos <= 0)
- return RDY_RESET;
+ return MSG_RESET;
*(msp->buffer + msp->eos) = b;
msp->eos += 1;
- return RDY_OK;
+ return MSG_OK;
}
-static msg_t get(void *ip) {
+static msg_t _get(void *ip) {
uint8_t b;
MemoryStream *msp = ip;
if (msp->eos - msp->offset <= 0)
- return RDY_RESET;
+ return MSG_RESET;
b = *(msp->buffer + msp->offset);
msp->offset += 1;
return b;
}
-static const struct MemStreamVMT vmt = {writes, reads, put, get};
+static const struct MemStreamVMT vmt = {_writes, _reads, _put, _get};
/*===========================================================================*/
/* Driver exported functions. */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/memstreams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/memstreams.h
similarity index 95%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/various/memstreams.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/memstreams.h
index 9a1da6c585..90bd2d9e97 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/memstreams.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/memstreams.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,8 +22,8 @@
* @{
*/
-#ifndef _MEMSTREAMS_H_
-#define _MEMSTREAMS_H_
+#ifndef MEMSTREAMS_H
+#define MEMSTREAMS_H
/*===========================================================================*/
/* Driver constants. */
@@ -42,7 +42,7 @@
/*===========================================================================*/
/**
- * @brief @p RamStream specific data.
+ * @brief @p MemStream specific data.
*/
#define _memory_stream_data \
_base_sequential_stream_data \
@@ -90,6 +90,6 @@ extern "C" {
}
#endif
-#endif /* _MEMSTREAMS_H_ */
+#endif /* MEMSTREAMS_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/nullstreams.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/nullstreams.c
new file mode 100644
index 0000000000..5d4958b232
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/nullstreams.c
@@ -0,0 +1,92 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file nullstreams.c
+ * @brief Null streams code.
+ *
+ * @addtogroup null_streams
+ * @{
+ */
+
+#include "hal.h"
+#include "nullstreams.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static size_t writes(void *ip, const uint8_t *bp, size_t n) {
+
+ (void)ip;
+ (void)bp;
+
+ return n;
+}
+
+static size_t reads(void *ip, uint8_t *bp, size_t n) {
+
+ (void)ip;
+ (void)bp;
+ (void)n;
+
+ return 0;
+}
+
+static msg_t put(void *ip, uint8_t b) {
+
+ (void)ip;
+ (void)b;
+
+ return MSG_OK;
+}
+
+static msg_t get(void *ip) {
+
+ (void)ip;
+
+ return 4;
+}
+
+static const struct NullStreamVMT vmt = {writes, reads, put, get};
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Null stream object initialization.
+ *
+ * @param[out] nsp pointer to the @p NullStream object to be initialized
+ */
+void nullObjectInit(NullStream *nsp) {
+
+ nsp->vmt = &vmt;
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/nullstreams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/nullstreams.h
new file mode 100644
index 0000000000..b0c46c9cf0
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/nullstreams.h
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file nullstreams.h
+ * @brief Null streams structures and macros.
+
+ * @addtogroup null_streams
+ * @{
+ */
+
+#ifndef NULLSTREAMS_H
+#define NULLSTREAMS_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief @p NullStream specific data.
+ */
+#define _null_stream_data \
+ _base_sequential_stream_data
+
+/**
+ * @brief @p NullStream virtual methods table.
+ */
+struct NullStreamVMT {
+ _base_sequential_stream_methods
+};
+
+/**
+ * @extends BaseSequentialStream
+ *
+ * @brief Null stream object.
+ */
+typedef struct {
+ /** @brief Virtual Methods Table.*/
+ const struct NullStreamVMT *vmt;
+ _null_stream_data
+} NullStream;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void nullObjectInit(NullStream *nsp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NULLSTREAMS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/streams.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/streams.mk
new file mode 100644
index 0000000000..31204bba39
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/lib/streams/streams.mk
@@ -0,0 +1,6 @@
+# RT Shell files.
+STREAMSSRC = $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ $(CHIBIOS)/os/hal/lib/streams/memstreams.c \
+ $(CHIBIOS)/os/hal/lib/streams/nullstreams.c
+
+STREAMSINC = $(CHIBIOS)/os/hal/lib/streams
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/lib/osal_vt.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/lib/osal_vt.c
new file mode 100644
index 0000000000..6c4a9ab11d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/lib/osal_vt.c
@@ -0,0 +1,168 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal_vt.c
+ * @brief OSAL Virtual Timers module code.
+ * @details This module can be used in an OSAL implementation whenever an
+ * underlying RTOS is unable to provide timeout services or there
+ * is no underlying RTOS.
+ *
+ * @addtogroup OSAL_VT
+ * @{
+ */
+
+#include "osal.h"
+#include "osal_vt.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief Virtual timers delta list header.
+ */
+virtual_timers_list_t vtlist;
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Timers initialization.
+ *
+ * @init
+ */
+void vtInit(void) {
+
+ /* Virtual Timers initialization.*/
+ vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist;
+ vtlist.vt_time = (systime_t)-1;
+ vtlist.vt_systime = 0;
+}
+
+/**
+ * @brief Returns @p TRUE if the specified timer is armed.
+ *
+ * @param[out] vtp the @p virtual_timer_t structure pointer
+ *
+ * @iclass
+ */
+bool vtIsArmedI(virtual_timer_t *vtp) {
+
+ return vtp->vt_func != NULL;
+}
+
+/**
+ * @brief Virtual timers ticker.
+ * @note The system lock is released before entering the callback and
+ * re-acquired immediately after. It is callback's responsibility
+ * to acquire the lock if needed. This is done in order to reduce
+ * interrupts jitter when many timers are in use.
+ *
+ * @iclass
+ */
+void vtDoTickI(void) {
+
+ vtlist.vt_systime++;
+ if (&vtlist != (virtual_timers_list_t *)vtlist.vt_next) {
+ virtual_timer_t *vtp;
+
+ --vtlist.vt_next->vt_time;
+ while (!(vtp = vtlist.vt_next)->vt_time) {
+ vtfunc_t fn = vtp->vt_func;
+ vtp->vt_func = (vtfunc_t)NULL;
+ vtp->vt_next->vt_prev = (void *)&vtlist;
+ (&vtlist)->vt_next = vtp->vt_next;
+ osalSysUnlockFromISR();
+ fn(vtp->vt_par);
+ osalSysLockFromISR();
+ }
+ }
+}
+
+/**
+ * @brief Enables a virtual timer.
+ * @note The associated function is invoked from interrupt context.
+ *
+ * @param[out] vtp the @p virtual_timer_t structure pointer
+ * @param[in] time the number of ticks before the operation timeouts, the
+ * special values are handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ * @param[in] vtfunc the timer callback function. After invoking the
+ * callback the timer is disabled and the structure can
+ * be disposed or reused.
+ * @param[in] par a parameter that will be passed to the callback
+ * function
+ *
+ * @iclass
+ */
+void vtSetI(virtual_timer_t *vtp, systime_t time,
+ vtfunc_t vtfunc, void *par) {
+ virtual_timer_t *p;
+
+ vtp->vt_par = par;
+ vtp->vt_func = vtfunc;
+ p = vtlist.vt_next;
+ while (p->vt_time < time) {
+ time -= p->vt_time;
+ p = p->vt_next;
+ }
+
+ vtp->vt_prev = (vtp->vt_next = p)->vt_prev;
+ vtp->vt_prev->vt_next = p->vt_prev = vtp;
+ vtp->vt_time = time;
+ if (p != (void *)&vtlist)
+ p->vt_time -= time;
+}
+
+/**
+ * @brief Disables a Virtual Timer.
+ * @note The timer MUST be active when this function is invoked.
+ *
+ * @param[in] vtp the @p virtual_timer_t structure pointer
+ *
+ * @iclass
+ */
+void vtResetI(virtual_timer_t *vtp) {
+
+ if (vtp->vt_next != (void *)&vtlist)
+ vtp->vt_next->vt_time += vtp->vt_time;
+ vtp->vt_prev->vt_next = vtp->vt_next;
+ vtp->vt_next->vt_prev = vtp->vt_prev;
+ vtp->vt_func = (vtfunc_t)NULL;
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/lib/osal_vt.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/lib/osal_vt.h
new file mode 100644
index 0000000000..9b78ca08c8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/lib/osal_vt.h
@@ -0,0 +1,131 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal_vt.h
+ * @brief OSAL Virtual Timers module header.
+ *
+ * @addtogroup OSAL_VT
+ * @{
+ */
+
+#ifndef _OSAL_VT_H_
+#define _OSAL_VT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE ((systime_t)0)
+#define TIME_INFINITE ((systime_t)-1)
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a Virtual Timer callback function.
+ */
+typedef void (*vtfunc_t)(void *);
+
+/**
+ * @brief Type of a Virtual Timer structure.
+ */
+typedef struct virtual_timer virtual_timer_t;
+
+/**
+ * @brief Virtual timers list header.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note The delta list is implemented as a double link bidirectional list
+ * in order to make the unlink time constant, the reset of a virtual
+ * timer is often used in the code.
+ */
+typedef struct {
+ virtual_timer_t *vt_next; /**< @brief Next timer in the timers
+ list. */
+ virtual_timer_t *vt_prev; /**< @brief Last timer in the timers
+ list. */
+ systime_t vt_time; /**< @brief Must be initialized to -1. */
+ volatile systime_t vt_systime; /**< @brief System Time counter. */
+} virtual_timers_list_t;
+
+/**
+ * @extends virtual_timers_list_t
+ *
+ * @brief Virtual Timer descriptor structure.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ */
+struct virtual_timer {
+ virtual_timer_t *vt_next; /**< @brief Next timer in the timers
+ list. */
+ virtual_timer_t *vt_prev; /**< @brief Previous timer in the timers
+ list. */
+ systime_t vt_time; /**< @brief Time delta before timeout. */
+ vtfunc_t vt_func; /**< @brief Timer callback function
+ pointer. */
+ void *vt_par; /**< @brief Timer callback function
+ parameter. */
+};
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern virtual_timers_list_t vtlist;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void vtInit(void);
+ bool vtIsArmedI(virtual_timer_t *vtp);
+ void vtDoTickI(void);
+ void vtSetI(virtual_timer_t *vtp, systime_t time,
+ vtfunc_t vtfunc, void *par);
+ void vtResetI(virtual_timer_t *vtp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _OSAL_VT_H_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.c
new file mode 100644
index 0000000000..32db7dcc4b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.c
@@ -0,0 +1,51 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.c
+ * @brief OSAL module code.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#include "osal.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.h
new file mode 100644
index 0000000000..cc53981080
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.h
@@ -0,0 +1,952 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.h
+ * @brief OSAL module header.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#ifndef _OSAL_H_
+#define _OSAL_H_
+
+#include
+#include
+#include
+
+#include "ch.h"
+
+#if defined(__SPC5_HAL__)
+#include "platform.h"
+#endif
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Common constants
+ * @{
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE (!FALSE)
+#endif
+
+#define OSAL_SUCCESS FALSE
+#define OSAL_FAILED TRUE
+/** @} */
+
+#if 0
+/**
+ * @name Messages
+ * @{
+ */
+#define MSG_OK RDY_OK
+#define MSG_RESET RDY_RESET
+#define MSG_TIMEOUT RDY_TIMEOUT
+/** @} */
+#endif
+
+#if 0
+/**
+ * @name Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE ((systime_t)0)
+#define TIME_INFINITE ((systime_t)-1)
+/** @} */
+#endif
+
+/**
+ * @name Systick modes.
+ * @{
+ */
+#define OSAL_ST_MODE_NONE 0
+#define OSAL_ST_MODE_PERIODIC 1
+#define OSAL_ST_MODE_FREERUNNING 2
+/** @} */
+
+/**
+ * @name Systick parameters.
+ * @{
+ */
+/**
+ * @brief Size in bits of the @p systick_t type.
+ */
+#define OSAL_ST_RESOLUTION CH_CFG_ST_RESOLUTION
+
+/**
+ * @brief Required systick frequency or resolution.
+ */
+#define OSAL_ST_FREQUENCY CH_CFG_ST_FREQUENCY
+
+/**
+ * @brief Systick mode required by the underlying OS.
+ */
+#if (CH_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__)
+#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC
+#else
+#define OSAL_ST_MODE OSAL_ST_MODE_FREERUNNING
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if CH_CFG_USE_SEMAPHORES == FALSE
+#error "OSAL requires CH_CFG_USE_SEMAPHORES=TRUE"
+#endif
+
+#if CH_CFG_USE_EVENTS == FALSE
+#error "OSAL requires CH_CFG_USE_EVENTS=TRUE"
+#endif
+
+#if !(OSAL_ST_MODE == OSAL_ST_MODE_NONE) && \
+ !(OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) && \
+ !(OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING)
+#error "invalid OSAL_ST_MODE setting in osal.h"
+#endif
+
+#if (OSAL_ST_RESOLUTION != 16) && (OSAL_ST_RESOLUTION != 32)
+#error "invalid OSAL_ST_RESOLUTION, must be 16 or 32"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+#if 0
+/**
+ * @brief Type of a system status word.
+ */
+typedef uint32_t syssts_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of a message.
+ */
+typedef int32_t msg_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of system time counter.
+ */
+typedef uint32_t systime_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of realtime counter.
+ */
+typedef uint32_t rtcnt_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+#endif
+
+/**
+ * @brief Type of an event flags object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+typedef struct event_source event_source_t;
+
+/**
+ * @brief Type of an event source callback.
+ * @note This type is not part of the OSAL API and is provided
+ * exclusively as an example and for convenience.
+ */
+typedef void (*eventcallback_t)(event_source_t *p);
+
+#if 0
+/**
+ * @brief Type of an event flags mask.
+ */
+typedef uint32_t eventflags_t;
+#endif
+
+/**
+ * @brief Events source object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+struct event_source {
+ volatile eventflags_t flags; /**< @brief Stored event flags. */
+ eventcallback_t cb; /**< @brief Event source callback. */
+ void *param; /**< @brief User defined field. */
+};
+
+/**
+ * @brief Type of a mutex.
+ * @note If the OS does not support mutexes or there is no OS then them
+ * mechanism can be simulated.
+ */
+typedef semaphore_t mutex_t;
+
+
+#if 0
+/**
+ * @brief Type of a thread queue.
+ * @details A thread queue is a queue of sleeping threads, queued threads
+ * can be dequeued one at time or all together.
+ * @note In this implementation it is implemented as a single reference
+ * because there are no real threads.
+ */
+typedef struct {
+ thread_reference_t tr;
+} threads_queue_t;
+#endif
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name Debug related macros
+ * @{
+ */
+/**
+ * @brief Condition assertion.
+ * @details If the condition check fails then the OSAL panics with a
+ * message and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS
+ * switch is enabled.
+ * @note The remark string is not currently used except for putting a
+ * comment in the code about the assertion.
+ *
+ * @param[in] c the condition to be verified to be true
+ * @param[in] remark a remark string
+ *
+ * @api
+ */
+#define osalDbgAssert(c, remark) chDbgAssert(c, remark)
+
+/**
+ * @brief Function parameters check.
+ * @details If the condition check fails then the OSAL panics and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch
+ * is enabled.
+ *
+ * @param[in] c the condition to be verified to be true
+ *
+ * @api
+ */
+#define osalDbgCheck(c) chDbgCheck(c)
+
+/**
+ * @brief I-Class state check.
+ */
+#define osalDbgCheckClassI() chDbgCheckClassI()
+
+/**
+ * @brief S-Class state check.
+ */
+#define osalDbgCheckClassS() chDbgCheckClassS()
+/** @} */
+
+/**
+ * @name IRQ service routines wrappers
+ * @{
+ */
+/**
+ * @brief Priority level verification macro.
+ */
+#define OSAL_IRQ_IS_VALID_PRIORITY(n) CH_IRQ_IS_VALID_KERNEL_PRIORITY(n)
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers.
+ */
+#define OSAL_IRQ_PROLOGUE() CH_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers.
+ */
+#define OSAL_IRQ_EPILOGUE() CH_IRQ_EPILOGUE()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @details This macro hides the details of an ISR function declaration.
+ *
+ * @param[in] id a vector name as defined in @p vectors.s
+ */
+#define OSAL_IRQ_HANDLER(id) CH_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name Time conversion utilities
+ * @{
+ */
+/**
+ * @brief Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec number of seconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_S2ST(sec) S2ST(sec)
+
+/**
+ * @brief Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec number of milliseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_MS2ST(msec) MS2ST(msec)
+
+/**
+ * @brief Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec number of microseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_US2ST(usec) US2ST(usec)
+/** @} */
+
+/**
+ * @name Time conversion utilities for the realtime counter
+ * @{
+ */
+/**
+ * @brief Seconds to realtime counter.
+ * @details Converts from seconds to realtime counter cycles.
+ * @note The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] sec number of seconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_S2RTC(freq, sec) S2RTC(freq, sec)
+
+/**
+ * @brief Milliseconds to realtime counter.
+ * @details Converts from milliseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next millisecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] msec number of milliseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_MS2RTC(freq, msec) MS2RTC(freq, msec)
+
+/**
+ * @brief Microseconds to realtime counter.
+ * @details Converts from microseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next microsecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] usec number of microseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_US2RTC(freq, usec) US2RTC(freq, usec)
+/** @} */
+
+/**
+ * @name Sleep macros using absolute time
+ * @{
+ */
+/**
+ * @brief Delays the invoking thread for the specified number of seconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] sec time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * milliseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] msec time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * microseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] usec time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief OSAL module initialization.
+ *
+ * @api
+ */
+static inline void osalInit(void) {
+
+}
+
+/**
+ * @brief System halt with error message.
+ *
+ * @param[in] reason the halt message pointer
+ *
+ * @api
+ */
+static inline void osalSysHalt(const char *reason) {
+
+ chSysHalt(reason);
+}
+
+/**
+ * @brief Disables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysDisable(void) {
+
+ chSysDisable();
+}
+
+/**
+ * @brief Enables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysEnable(void) {
+
+ chSysEnable();
+}
+
+/**
+ * @brief Enters a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLock(void) {
+
+ chSysLock();
+}
+
+/**
+ * @brief Leaves a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlock(void) {
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Enters a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLockFromISR(void) {
+
+ chSysLockFromISR();
+}
+
+/**
+ * @brief Leaves a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlockFromISR(void) {
+
+ chSysUnlockFromISR();
+}
+
+/**
+ * @brief Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ * from any context. Because its flexibility it is less efficient
+ * than @p chSysLock() which is preferable when the calling context
+ * is known.
+ * @post The system is in a critical zone.
+ *
+ * @return The previous system status, the encoding of this
+ * status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+static inline syssts_t osalSysGetStatusAndLockX(void) {
+
+ return chSysGetStatusAndLockX();
+}
+
+/**
+ * @brief Restores the specified execution status and leaves a critical zone.
+ * @note A call to @p chSchRescheduleS() is automatically performed
+ * if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts the system status to be restored.
+ *
+ * @xclass
+ */
+static inline void osalSysRestoreStatusX(syssts_t sts) {
+
+ chSysRestoreStatusX(sts);
+}
+
+/**
+ * @brief Polled delay.
+ * @note The real delay is always few cycles in excess of the specified
+ * value.
+ *
+ * @param[in] cycles number of cycles
+ *
+ * @xclass
+ */
+#if (PORT_SUPPORTS_RT == TRUE) || defined(__DOXYGEN__)
+static inline void osalSysPolledDelayX(rtcnt_t cycles) {
+
+ chSysPolledDelayX(cycles);
+}
+#endif
+
+/**
+ * @brief Systick callback for the underlying OS.
+ * @note This callback is only defined if the OSAL requires such a
+ * service from the HAL.
+ */
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+static inline void osalOsTimerHandlerI(void) {
+
+ chSysTimerHandlerI();
+}
+#endif
+
+/**
+ * @brief Checks if a reschedule is required and performs it.
+ * @note I-Class functions invoked from thread context must not reschedule
+ * by themselves, an explicit reschedule using this function is
+ * required in this scenario.
+ * @note Not implemented in this simplified OSAL.
+ *
+ * @sclass
+ */
+static inline void osalOsRescheduleS(void) {
+
+ chSchRescheduleS();
+}
+
+/**
+ * @brief Current system time.
+ * @details Returns the number of system ticks since the @p osalInit()
+ * invocation.
+ * @note The counter can reach its maximum and then restart from zero.
+ * @note This function can be called from any context but its atomicity
+ * is not guaranteed on architectures whose word size is less than
+ * @p systime_t size.
+ *
+ * @return The system time in ticks.
+ *
+ * @xclass
+ */
+static inline systime_t osalOsGetSystemTimeX(void) {
+
+ return chVTGetSystemTimeX();
+}
+
+/**
+ * @brief Checks if the specified time is within the specified time window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ * @note This function can be called from any context.
+ *
+ * @param[in] time the time to be verified
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool osalOsIsTimeWithinX(systime_t time,
+ systime_t start,
+ systime_t end) {
+
+ return chVTIsTimeWithinX(time, start, end);
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @sclass
+ */
+static inline void osalThreadSleepS(systime_t time) {
+
+ chThdSleepS(time);
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @api
+ */
+static inline void osalThreadSleep(systime_t time) {
+
+ chThdSleep(time);
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @return The wake up message.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadSuspendS(thread_reference_t *trp) {
+
+ return chThdSuspendTimeoutS(trp, TIME_INFINITE);
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The wake up message.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp,
+ systime_t timeout) {
+
+ return chThdSuspendTimeoutS(trp, timeout);
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must not reschedule because it can be called from
+ * ISR context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadResumeI(thread_reference_t *trp, msg_t msg) {
+
+ chThdResumeI(trp, msg);
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadResumeS(thread_reference_t *trp, msg_t msg) {
+
+ chThdResumeI(trp, msg);
+ chSchRescheduleS();
+}
+
+/**
+ * @brief Initializes a threads queue object.
+ *
+ * @param[out] tqp pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) {
+
+ chThdQueueObjectInit(tqp);
+}
+
+/**
+ * @brief Enqueues the caller thread.
+ * @details The caller thread is enqueued and put to sleep until it is
+ * dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] time the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The message from @p osalQueueWakeupOneI() or
+ * @p osalQueueWakeupAllI() functions.
+ * @retval MSG_TIMEOUT if the thread has not been dequeued within the
+ * specified timeout or if the function has been
+ * invoked with @p TIME_IMMEDIATE as timeout
+ * specification.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp,
+ systime_t time) {
+
+ return chThdEnqueueTimeoutS(tqp, time);
+}
+
+/**
+ * @brief Dequeues and wakes up one thread from the queue, if any.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+
+ chThdDequeueNextI(tqp, msg);
+}
+
+/**
+ * @brief Dequeues and wakes up all threads from the queue.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+
+ chThdDequeueAllI(tqp, msg);
+}
+
+/**
+ * @brief Initializes an event flags object.
+ *
+ * @param[out] esp pointer to the event flags object
+ *
+ * @init
+ */
+static inline void osalEventObjectInit(event_source_t *esp) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->flags = 0;
+ esp->cb = NULL;
+ esp->param = NULL;
+}
+
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlagsI(event_source_t *esp,
+ eventflags_t flags) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->flags |= flags;
+ if (esp->cb != NULL) {
+ esp->cb(esp);
+ }
+}
+
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlags(event_source_t *esp,
+ eventflags_t flags) {
+
+ osalDbgCheck(esp != NULL);
+
+ chSysLock();
+ osalEventBroadcastFlagsI(esp, flags);
+ chSchRescheduleS();
+ chSysUnlock();
+}
+
+/**
+ * @brief Event callback setup.
+ * @note The callback is invoked from ISR context and can
+ * only invoke I-Class functions. The callback is meant
+ * to wakeup the task that will handle the event by
+ * calling @p osalEventGetAndClearFlagsI().
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] cb pointer to the callback function
+ * @param[in] param parameter to be passed to the callback function
+ *
+ * @api
+ */
+static inline void osalEventSetCallback(event_source_t *esp,
+ eventcallback_t cb,
+ void *param) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->cb = cb;
+ esp->param = param;
+}
+
+/**
+ * @brief Initializes s @p mutex_t object.
+ *
+ * @param[out] mp pointer to the @p mutex_t object
+ *
+ * @init
+ */
+static inline void osalMutexObjectInit(mutex_t *mp) {
+
+ chSemObjectInit((semaphore_t *)mp, (cnt_t)1);
+}
+
+/**
+ * @brief Locks the specified mutex.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexLock(mutex_t *mp) {
+
+ (void) chSemWait((semaphore_t *)mp);
+}
+
+/**
+ * @brief Unlocks the specified mutex.
+ * @note The HAL guarantees to release mutex in reverse lock order. The
+ * mutex being unlocked is guaranteed to be the last locked mutex
+ * by the invoking thread.
+ * The implementation can rely on this behavior and eventually
+ * ignore the @p mp parameter which is supplied in order to support
+ * those OSes not supporting a stack of the owned mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexUnlock(mutex_t *mp) {
+
+ chSemSignal((semaphore_t *)mp);
+}
+
+#endif /* _OSAL_H_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.mk
new file mode 100644
index 0000000000..d104bd6945
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/nil/osal.mk
@@ -0,0 +1,5 @@
+# OSAL files.
+OSALSRC += ${CHIBIOS}/os/hal/osal/nil/osal.c
+
+# Required include directories
+OSALINC += ${CHIBIOS}/os/hal/osal/nil
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.c
new file mode 100644
index 0000000000..bb45845362
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.c
@@ -0,0 +1,467 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.c
+ * @brief OSAL module code.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#include "osal.h"
+#include "osal_vt.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief Pointer to a halt error message.
+ * @note The message is meant to be retrieved by the debugger after the
+ * system halt caused by an unexpected error.
+ */
+const char *osal_halt_msg;
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+static void callback_timeout(void *p) {
+ osalSysLockFromISR();
+ osalThreadResumeI((thread_reference_t *)p, MSG_TIMEOUT);
+ osalSysUnlockFromISR();
+}
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief OSAL module initialization.
+ *
+ * @api
+ */
+void osalInit(void) {
+
+ vtInit();
+
+ OSAL_INIT_HOOK();
+}
+
+/**
+ * @brief System halt with error message.
+ *
+ * @param[in] reason the halt message pointer
+ *
+ * @api
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak, noreturn))
+#endif
+void osalSysHalt(const char *reason) {
+
+ osalSysDisable();
+ osal_halt_msg = reason;
+ while (true) {
+ }
+}
+
+/**
+ * @brief Polled delay.
+ * @note The real delay is always few cycles in excess of the specified
+ * value.
+ *
+ * @param[in] cycles number of cycles
+ *
+ * @xclass
+ */
+void osalSysPolledDelayX(rtcnt_t cycles) {
+
+ (void)cycles;
+}
+
+/**
+ * @brief System timer handler.
+ * @details The handler is used for scheduling and Virtual Timers management.
+ *
+ * @iclass
+ */
+void osalOsTimerHandlerI(void) {
+
+ osalDbgCheckClassI();
+
+ vtDoTickI();
+}
+
+/**
+ * @brief Checks if a reschedule is required and performs it.
+ * @note I-Class functions invoked from thread context must not reschedule
+ * by themselves, an explicit reschedule using this function is
+ * required in this scenario.
+ * @note Not implemented in this simplified OSAL.
+ *
+ * @sclass
+ */
+void osalOsRescheduleS(void) {
+
+}
+
+/**
+ * @brief Current system time.
+ * @details Returns the number of system ticks since the @p osalInit()
+ * invocation.
+ * @note The counter can reach its maximum and then restart from zero.
+ * @note This function can be called from any context but its atomicity
+ * is not guaranteed on architectures whose word size is less than
+ * @p systime_t size.
+ *
+ * @return The system time in ticks.
+ *
+ * @xclass
+ */
+systime_t osalOsGetSystemTimeX(void) {
+
+ return vtlist.vt_systime;
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @sclass
+ */
+void osalThreadSleepS(systime_t time) {
+ virtual_timer_t vt;
+ thread_reference_t tr;
+
+ tr = NULL;
+ vtSetI(&vt, time, callback_timeout, (void *)&tr);
+ osalThreadSuspendS(&tr);
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @api
+ */
+void osalThreadSleep(systime_t time) {
+
+ osalSysLock();
+ osalThreadSleepS(time);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @return The wake up message.
+ *
+ * @sclass
+ */
+msg_t osalThreadSuspendS(thread_reference_t *trp) {
+ thread_t self = {MSG_WAIT};
+
+ osalDbgCheck(trp != NULL);
+
+ *trp = &self;
+ while (self.message == MSG_WAIT) {
+ osalSysUnlock();
+ /* A state-changing interrupt could occur here and cause the loop to
+ terminate, an hook macro is executed while waiting.*/
+ OSAL_IDLE_HOOK();
+ osalSysLock();
+ }
+
+ return self.message;
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The wake up message.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ *
+ * @sclass
+ */
+msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) {
+ msg_t msg;
+ virtual_timer_t vt;
+
+ osalDbgCheck(trp != NULL);
+
+ if (TIME_INFINITE == timeout)
+ return osalThreadSuspendS(trp);
+
+ vtSetI(&vt, timeout, callback_timeout, (void *)trp);
+ msg = osalThreadSuspendS(trp);
+ if (vtIsArmedI(&vt))
+ vtResetI(&vt);
+
+ return msg;
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must not reschedule because it can be called from
+ * ISR context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadResumeI(thread_reference_t *trp, msg_t msg) {
+
+ osalDbgCheck(trp != NULL);
+
+ if (*trp != NULL) {
+ (*trp)->message = msg;
+ *trp = NULL;
+ }
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadResumeS(thread_reference_t *trp, msg_t msg) {
+
+ osalDbgCheck(trp != NULL);
+
+ if (*trp != NULL) {
+ (*trp)->message = msg;
+ *trp = NULL;
+ }
+}
+
+/**
+ * @brief Enqueues the caller thread.
+ * @details The caller thread is enqueued and put to sleep until it is
+ * dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The message from @p osalQueueWakeupOneI() or
+ * @p osalQueueWakeupAllI() functions.
+ * @retval MSG_TIMEOUT if the thread has not been dequeued within the
+ * specified timeout or if the function has been
+ * invoked with @p TIME_IMMEDIATE as timeout
+ * specification.
+ *
+ * @sclass
+ */
+msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) {
+ msg_t msg;
+ virtual_timer_t vt;
+
+ osalDbgCheck(tqp != NULL);
+
+ if (TIME_IMMEDIATE == timeout)
+ return MSG_TIMEOUT;
+
+ tqp->tr = NULL;
+
+ if (TIME_INFINITE == timeout)
+ return osalThreadSuspendS(&tqp->tr);
+
+ vtSetI(&vt, timeout, callback_timeout, (void *)&tqp->tr);
+ msg = osalThreadSuspendS(&tqp->tr);
+ if (vtIsArmedI(&vt))
+ vtResetI(&vt);
+
+ return msg;
+}
+
+/**
+ * @brief Dequeues and wakes up one thread from the queue, if any.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+
+ osalDbgCheck(tqp != NULL);
+
+ osalThreadResumeI(&tqp->tr, msg);
+}
+
+/**
+ * @brief Dequeues and wakes up all threads from the queue.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+
+ osalDbgCheck(tqp != NULL);
+
+ osalThreadResumeI(&tqp->tr, msg);
+}
+
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->flags |= flags;
+ if (esp->cb != NULL) {
+ esp->cb(esp);
+ }
+}
+
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags) {
+
+ osalDbgCheck(esp != NULL);
+
+ osalSysLock();
+ osalEventBroadcastFlagsI(esp, flags);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Event callback setup.
+ * @note The callback is invoked from ISR context and can
+ * only invoke I-Class functions. The callback is meant
+ * to wakeup the task that will handle the event by
+ * calling @p osalEventGetAndClearFlagsI().
+ * @note This function is not part of the OSAL API and is provided
+ * exclusively as an example and for convenience.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] cb pointer to the callback function
+ * @param[in] param parameter to be passed to the callback function
+ *
+ * @api
+ */
+void osalEventSetCallback(event_source_t *esp,
+ eventcallback_t cb,
+ void *param) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->cb = cb;
+ esp->param = param;
+}
+
+/**
+ * @brief Locks the specified mutex.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+void osalMutexLock(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 1;
+}
+
+/**
+ * @brief Unlocks the specified mutex.
+ * @note The HAL guarantees to release mutex in reverse lock order. The
+ * mutex being unlocked is guaranteed to be the last locked mutex
+ * by the invoking thread.
+ * The implementation can rely on this behavior and eventually
+ * ignore the @p mp parameter which is supplied in order to support
+ * those OSes not supporting a stack of the owned mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+void osalMutexUnlock(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 0;
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.h
new file mode 100644
index 0000000000..a2c11b035e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.h
@@ -0,0 +1,720 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.h
+ * @brief OSAL module header.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#ifndef _OSAL_H_
+#define _OSAL_H_
+
+#include
+#include
+#include
+
+#include "cmparams.h"
+
+#include "osalconf.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Common constants
+ * @{
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define OSAL_SUCCESS false
+#define OSAL_FAILED true
+/** @} */
+
+/**
+ * @name Messages
+ * @{
+ */
+#define MSG_OK (msg_t)0
+#define MSG_RESET (msg_t)-1
+#define MSG_TIMEOUT (msg_t)-2
+#define MSG_WAIT (msg_t)-10
+/** @} */
+
+/**
+ * @name Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE ((systime_t)0)
+#define TIME_INFINITE ((systime_t)-1)
+/** @} */
+
+/**
+ * @name Systick modes.
+ * @{
+ */
+#define OSAL_ST_MODE_NONE 0
+#define OSAL_ST_MODE_PERIODIC 1
+#define OSAL_ST_MODE_FREERUNNING 2
+/** @} */
+
+/**
+ * @name Systick parameters.
+ * @{
+ */
+/**
+ * @brief Size in bits of the @p systick_t type.
+ */
+#define OSAL_ST_RESOLUTION 32
+
+/**
+ * @brief Systick mode required by the underlying OS.
+ */
+#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC
+/** @} */
+
+/**
+ * @name IRQ-related constants
+ * @{
+ */
+/**
+ * @brief Total priority levels.
+ */
+#define OSAL_IRQ_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS)
+
+/**
+ * @brief Highest IRQ priority for HAL drivers.
+ */
+#if (CORTEX_MODEL == 0) || defined(__DOXYGEN__)
+#define OSAL_IRQ_MAXIMUM_PRIORITY 0
+#else
+#define OSAL_IRQ_MAXIMUM_PRIORITY 1
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Frequency in Hertz of the system tick.
+ */
+#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__)
+#define OSAL_ST_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Enables OSAL assertions.
+ */
+#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define OSAL_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Enables OSAL functions parameters checks.
+ */
+#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define OSAL_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief OSAL initialization hook.
+ */
+#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__)
+#define OSAL_INIT_HOOK()
+#endif
+
+/**
+ * @brief Idle loop hook macro.
+ */
+#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__)
+#define OSAL_IDLE_HOOK()
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a system status word.
+ */
+typedef uint32_t syssts_t;
+
+/**
+ * @brief Type of a message.
+ */
+typedef int32_t msg_t;
+
+/**
+ * @brief Type of system time counter.
+ */
+typedef uint32_t systime_t;
+
+/**
+ * @brief Type of realtime counter.
+ */
+typedef uint32_t rtcnt_t;
+
+/**
+ * @brief Type of a thread.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ */
+typedef struct {
+ volatile msg_t message;
+} thread_t;
+
+/**
+ * @brief Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+
+/**
+ * @brief Type of an event flags object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+typedef struct event_source event_source_t;
+
+/**
+ * @brief Type of an event source callback.
+ * @note This type is not part of the OSAL API and is provided
+ * exclusively as an example and for convenience.
+ */
+typedef void (*eventcallback_t)(event_source_t *esp);
+
+/**
+ * @brief Type of an event flags mask.
+ */
+typedef uint32_t eventflags_t;
+
+/**
+ * @brief Events source object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+struct event_source {
+ volatile eventflags_t flags; /**< @brief Stored event flags. */
+ eventcallback_t cb; /**< @brief Event source callback. */
+ void *param; /**< @brief User defined field. */
+};
+
+/**
+ * @brief Type of a mutex.
+ * @note If the OS does not support mutexes or there is no OS then them
+ * mechanism can be simulated.
+ */
+typedef uint32_t mutex_t;
+
+/**
+ * @brief Type of a thread queue.
+ * @details A thread queue is a queue of sleeping threads, queued threads
+ * can be dequeued one at time or all together.
+ * @note If the OSAL is implemented on a bare metal machine without RTOS
+ * then the queue can be implemented as a single thread reference.
+ */
+typedef struct {
+ thread_reference_t tr;
+} threads_queue_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name Debug related macros
+ * @{
+ */
+/**
+ * @brief Condition assertion.
+ * @details If the condition check fails then the OSAL panics with a
+ * message and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS
+ * switch is enabled.
+ * @note The remark string is not currently used except for putting a
+ * comment in the code about the assertion.
+ *
+ * @param[in] c the condition to be verified to be true
+ * @param[in] remark a remark string
+ *
+ * @api
+ */
+#define osalDbgAssert(c, remark) do { \
+ /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
+ if (OSAL_DBG_ENABLE_ASSERTS != FALSE) { \
+ if (!(c)) { \
+ /*lint -restore*/ \
+ osalSysHalt(__func__); \
+ } \
+ } \
+} while (false)
+
+
+/**
+ * @brief Function parameters check.
+ * @details If the condition check fails then the OSAL panics and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch
+ * is enabled.
+ *
+ * @param[in] c the condition to be verified to be true
+ *
+ * @api
+ */
+#define osalDbgCheck(c) do { \
+ /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
+ if (OSAL_DBG_ENABLE_CHECKS != FALSE) { \
+ if (!(c)) { \
+ /*lint -restore*/ \
+ osalSysHalt(__func__); \
+ } \
+ } \
+} while (false)
+
+
+/**
+ * @brief I-Class state check.
+ * @note Implementation is optional.
+ */
+#define osalDbgCheckClassI()
+
+/**
+ * @brief S-Class state check.
+ * @note Implementation is optional.
+ */
+#define osalDbgCheckClassS()
+/** @} */
+
+/**
+ * @name IRQ service routines wrappers
+ * @{
+ */
+/**
+ * @brief Priority level verification macro.
+ */
+#define OSAL_IRQ_IS_VALID_PRIORITY(n) \
+ (((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS))
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers.
+ */
+#define OSAL_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers.
+ */
+#define OSAL_IRQ_EPILOGUE()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @details This macro hides the details of an ISR function declaration.
+ *
+ * @param[in] id a vector name as defined in @p vectors.s
+ */
+#define OSAL_IRQ_HANDLER(id) void id(void)
+/** @} */
+
+/**
+ * @name Time conversion utilities
+ * @{
+ */
+/**
+ * @brief Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec number of seconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_S2ST(sec) \
+ ((systime_t)((uint32_t)(sec) * (uint32_t)OSAL_ST_FREQUENCY))
+
+/**
+ * @brief Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec number of milliseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_MS2ST(msec) \
+ ((systime_t)((((uint32_t)(msec)) * \
+ ((uint32_t)OSAL_ST_FREQUENCY) + 999UL) / 1000UL))
+
+/**
+ * @brief Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec number of microseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_US2ST(usec) \
+ ((systime_t)((((uint32_t)(usec)) * \
+ ((uint32_t)OSAL_ST_FREQUENCY) + 999999UL) / 1000000UL))
+/** @} */
+
+/**
+ * @name Time conversion utilities for the realtime counter
+ * @{
+ */
+/**
+ * @brief Seconds to realtime counter.
+ * @details Converts from seconds to realtime counter cycles.
+ * @note The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] sec number of seconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_S2RTC(freq, sec) ((freq) * (sec))
+
+/**
+ * @brief Milliseconds to realtime counter.
+ * @details Converts from milliseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next millisecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] msec number of milliseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec))
+
+/**
+ * @brief Microseconds to realtime counter.
+ * @details Converts from microseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next microsecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] usec number of microseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec))
+/** @} */
+
+/**
+ * @name Sleep macros using absolute time
+ * @{
+ */
+/**
+ * @brief Delays the invoking thread for the specified number of seconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] sec time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * milliseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] msec time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * microseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] usec time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+extern const char *osal_halt_msg;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void osalInit(void);
+ void osalSysHalt(const char *reason);
+ void osalSysPolledDelayX(rtcnt_t cycles);
+ void osalOsTimerHandlerI(void);
+ void osalOsRescheduleS(void);
+ systime_t osalOsGetSystemTimeX(void);
+ void osalThreadSleepS(systime_t time);
+ void osalThreadSleep(systime_t time);
+ msg_t osalThreadSuspendS(thread_reference_t *trp);
+ msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
+ void osalThreadResumeI(thread_reference_t *trp, msg_t msg);
+ void osalThreadResumeS(thread_reference_t *trp, msg_t msg);
+ msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout);
+ void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg);
+ void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg);
+ void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags);
+ void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags);
+ void osalEventSetCallback(event_source_t *esp,
+ eventcallback_t cb,
+ void *param);
+ void osalMutexLock(mutex_t *mp);
+ void osalMutexUnlock(mutex_t *mp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysDisable(void) {
+
+ __disable_irq();
+}
+
+/**
+ * @brief Enables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysEnable(void) {
+
+ __enable_irq();
+}
+
+/**
+ * @brief Enters a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLock(void) {
+
+#if CORTEX_MODEL == 0
+ __disable_irq();
+#else
+ __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Leaves a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlock(void) {
+
+#if CORTEX_MODEL == 0
+ __enable_irq();
+#else
+ __set_BASEPRI(0);
+#endif
+}
+
+/**
+ * @brief Enters a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLockFromISR(void) {
+
+#if CORTEX_MODEL == 0
+ __disable_irq();
+#else
+ __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Leaves a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlockFromISR(void) {
+
+#if CORTEX_MODEL == 0
+ __enable_irq();
+#else
+ __set_BASEPRI(0);
+#endif
+}
+
+/**
+ * @brief Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ * from any context. Because its flexibility it is less efficient
+ * than @p chSysLock() which is preferable when the calling context
+ * is known.
+ * @post The system is in a critical zone.
+ *
+ * @return The previous system status, the encoding of this
+ * status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+static inline syssts_t osalSysGetStatusAndLockX(void) {
+ syssts_t sts;
+
+#if CORTEX_MODEL == 0
+ sts = (syssts_t)__get_PRIMASK();
+ __disable_irq();
+#else
+ sts = (syssts_t)__get_BASEPRI();
+ __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);
+#endif
+ return sts;
+}
+
+/**
+ * @brief Restores the specified execution status and leaves a critical zone.
+ * @note A call to @p chSchRescheduleS() is automatically performed
+ * if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts the system status to be restored.
+ *
+ * @xclass
+ */
+static inline void osalSysRestoreStatusX(syssts_t sts) {
+
+#if CORTEX_MODEL == 0
+ if ((sts & (syssts_t)1) == (syssts_t)0) {
+ __enable_irq();
+ }
+#else
+ if (sts == (syssts_t)0) {
+ __set_BASEPRI(0);
+ }
+#endif
+}
+
+/**
+ * @brief Checks if the specified time is within the specified time window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ * @note This function can be called from any context.
+ *
+ * @param[in] time the time to be verified
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool osalOsIsTimeWithinX(systime_t time,
+ systime_t start,
+ systime_t end) {
+
+ return (bool)((time - start) < (end - start));
+}
+
+/**
+ * @brief Initializes a threads queue object.
+ *
+ * @param[out] tqp pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) {
+
+ osalDbgCheck(tqp != NULL);
+
+ (void)tqp;
+}
+
+/**
+ * @brief Initializes an event flags object.
+ *
+ * @param[out] esp pointer to the event flags object
+ *
+ * @init
+ */
+static inline void osalEventObjectInit(event_source_t *esp) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->flags = (eventflags_t)0;
+ esp->cb = NULL;
+ esp->param = NULL;
+}
+
+/**
+ * @brief Initializes s @p mutex_t object.
+ *
+ * @param[out] mp pointer to the @p mutex_t object
+ *
+ * @init
+ */
+static inline void osalMutexObjectInit(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 0;
+}
+
+#endif /* _OSAL_H_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.mk
new file mode 100644
index 0000000000..d7ea0edbda
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/ARMCMx/osal.mk
@@ -0,0 +1,7 @@
+# OSAL files.
+OSALSRC += ${CHIBIOS}/os/hal/osal/os-less/ARMCMx/osal.c \
+ ${CHIBIOS}/os/hal/osal/lib/osal_vt.c
+
+# Required include directories
+OSALINC += ${CHIBIOS}/os/hal/osal/os-less/ARMCMx \
+ ${CHIBIOS}/os/hal/osal/lib
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.c
new file mode 100644
index 0000000000..b4407525e4
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.c
@@ -0,0 +1,467 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.c
+ * @brief OSAL module code.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#include "osal.h"
+#include "osal_vt.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief Pointer to a halt error message.
+ * @note The message is meant to be retrieved by the debugger after the
+ * system halt caused by an unexpected error.
+ */
+const char *osal_halt_msg;
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+static void callback_timeout(void *p) {
+ osalSysLockFromISR();
+ osalThreadResumeI((thread_reference_t *)p, MSG_TIMEOUT);
+ osalSysUnlockFromISR();
+}
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief OSAL module initialization.
+ *
+ * @api
+ */
+void osalInit(void) {
+
+ vtInit();
+
+ OSAL_INIT_HOOK();
+}
+
+/**
+ * @brief System halt with error message.
+ *
+ * @param[in] reason the halt message pointer
+ *
+ * @api
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak, noreturn))
+#endif
+void osalSysHalt(const char *reason) {
+
+ osalSysDisable();
+ osal_halt_msg = reason;
+ while (true) {
+ }
+}
+
+/**
+ * @brief Polled delay.
+ * @note The real delay is always few cycles in excess of the specified
+ * value.
+ *
+ * @param[in] cycles number of cycles
+ *
+ * @xclass
+ */
+void osalSysPolledDelayX(rtcnt_t cycles) {
+
+ (void)cycles;
+}
+
+/**
+ * @brief System timer handler.
+ * @details The handler is used for scheduling and Virtual Timers management.
+ *
+ * @iclass
+ */
+void osalOsTimerHandlerI(void) {
+
+ osalDbgCheckClassI();
+
+ vtDoTickI();
+}
+
+/**
+ * @brief Checks if a reschedule is required and performs it.
+ * @note I-Class functions invoked from thread context must not reschedule
+ * by themselves, an explicit reschedule using this function is
+ * required in this scenario.
+ * @note Not implemented in this simplified OSAL.
+ *
+ * @sclass
+ */
+void osalOsRescheduleS(void) {
+
+}
+
+/**
+ * @brief Current system time.
+ * @details Returns the number of system ticks since the @p osalInit()
+ * invocation.
+ * @note The counter can reach its maximum and then restart from zero.
+ * @note This function can be called from any context but its atomicity
+ * is not guaranteed on architectures whose word size is less than
+ * @p systime_t size.
+ *
+ * @return The system time in ticks.
+ *
+ * @xclass
+ */
+systime_t osalOsGetSystemTimeX(void) {
+
+ return vtlist.vt_systime;
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @sclass
+ */
+void osalThreadSleepS(systime_t time) {
+ virtual_timer_t vt;
+ thread_reference_t tr;
+
+ tr = NULL;
+ vtSetI(&vt, time, callback_timeout, (void *)&tr);
+ osalThreadSuspendS(&tr);
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @api
+ */
+void osalThreadSleep(systime_t time) {
+
+ osalSysLock();
+ osalThreadSleepS(time);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @return The wake up message.
+ *
+ * @sclass
+ */
+msg_t osalThreadSuspendS(thread_reference_t *trp) {
+ thread_t self = {MSG_WAIT};
+
+ osalDbgCheck(trp != NULL);
+
+ *trp = &self;
+ while (self.message == MSG_WAIT) {
+ osalSysUnlock();
+ /* A state-changing interrupt could occur here and cause the loop to
+ terminate, an hook macro is executed while waiting.*/
+ OSAL_IDLE_HOOK();
+ osalSysLock();
+ }
+
+ return self.message;
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The wake up message.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ *
+ * @sclass
+ */
+msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) {
+ msg_t msg;
+ virtual_timer_t vt;
+
+ osalDbgCheck(trp != NULL);
+
+ if (TIME_INFINITE == timeout)
+ return osalThreadSuspendS(trp);
+
+ vtSetI(&vt, timeout, callback_timeout, (void *)trp);
+ msg = osalThreadSuspendS(trp);
+ if (vtIsArmedI(&vt))
+ vtResetI(&vt);
+
+ return msg;
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must not reschedule because it can be called from
+ * ISR context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadResumeI(thread_reference_t *trp, msg_t msg) {
+
+ osalDbgCheck(trp != NULL);
+
+ if (*trp != NULL) {
+ (*trp)->message = msg;
+ *trp = NULL;
+ }
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadResumeS(thread_reference_t *trp, msg_t msg) {
+
+ osalDbgCheck(trp != NULL);
+
+ if (*trp != NULL) {
+ (*trp)->message = msg;
+ *trp = NULL;
+ }
+}
+
+/**
+ * @brief Enqueues the caller thread.
+ * @details The caller thread is enqueued and put to sleep until it is
+ * dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The message from @p osalQueueWakeupOneI() or
+ * @p osalQueueWakeupAllI() functions.
+ * @retval MSG_TIMEOUT if the thread has not been dequeued within the
+ * specified timeout or if the function has been
+ * invoked with @p TIME_IMMEDIATE as timeout
+ * specification.
+ *
+ * @sclass
+ */
+msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) {
+ msg_t msg;
+ virtual_timer_t vt;
+
+ osalDbgCheck(tqp != NULL);
+
+ if (TIME_IMMEDIATE == timeout)
+ return MSG_TIMEOUT;
+
+ tqp->tr = NULL;
+
+ if (TIME_INFINITE == timeout)
+ return osalThreadSuspendS(&tqp->tr);
+
+ vtSetI(&vt, timeout, callback_timeout, (void *)&tqp->tr);
+ msg = osalThreadSuspendS(&tqp->tr);
+ if (vtIsArmedI(&vt))
+ vtResetI(&vt);
+
+ return msg;
+}
+
+/**
+ * @brief Dequeues and wakes up one thread from the queue, if any.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+
+ osalDbgCheck(tqp != NULL);
+
+ osalThreadResumeI(&tqp->tr, msg);
+}
+
+/**
+ * @brief Dequeues and wakes up all threads from the queue.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+
+ osalDbgCheck(tqp != NULL);
+
+ osalThreadResumeI(&tqp->tr, msg);
+}
+
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->flags |= flags;
+ if (esp->cb != NULL) {
+ esp->cb(esp);
+ }
+}
+
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags) {
+
+ osalDbgCheck(esp != NULL);
+
+ osalSysLock();
+ osalEventBroadcastFlagsI(esp, flags);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Event callback setup.
+ * @note The callback is invoked from ISR context and can
+ * only invoke I-Class functions. The callback is meant
+ * to wakeup the task that will handle the event by
+ * calling @p osalEventGetAndClearFlagsI().
+ * @note This function is not part of the OSAL API and is provided
+ * exclusively as an example and for convenience.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] cb pointer to the callback function
+ * @param[in] param parameter to be passed to the callback function
+ *
+ * @api
+ */
+void osalEventSetCallback(event_source_t *esp,
+ eventcallback_t cb,
+ void *param) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->cb = cb;
+ esp->param = param;
+}
+
+/**
+ * @brief Locks the specified mutex.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+void osalMutexLock(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 1;
+}
+
+/**
+ * @brief Unlocks the specified mutex.
+ * @note The HAL guarantees to release mutex in reverse lock order. The
+ * mutex being unlocked is guaranteed to be the last locked mutex
+ * by the invoking thread.
+ * The implementation can rely on this behavior and eventually
+ * ignore the @p mp parameter which is supplied in order to support
+ * those OSes not supporting a stack of the owned mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+void osalMutexUnlock(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 0;
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.h
new file mode 100644
index 0000000000..4a2fc3afd6
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.h
@@ -0,0 +1,678 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.h
+ * @brief OSAL module header.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#ifndef _OSAL_H_
+#define _OSAL_H_
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include "osalconf.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Common constants
+ * @{
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define OSAL_SUCCESS false
+#define OSAL_FAILED true
+/** @} */
+
+/**
+ * @name Messages
+ * @{
+ */
+#define MSG_OK (msg_t)0
+#define MSG_RESET (msg_t)-1
+#define MSG_TIMEOUT (msg_t)-2
+#define MSG_WAIT (msg_t)-10
+/** @} */
+
+
+/**
+ * @name Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE ((systime_t)0)
+#define TIME_INFINITE ((systime_t)-1)
+/** @} */
+
+/**
+ * @name Systick modes.
+ * @{
+ */
+#define OSAL_ST_MODE_NONE 0
+#define OSAL_ST_MODE_PERIODIC 1
+#define OSAL_ST_MODE_FREERUNNING 2
+/** @} */
+
+/**
+ * @name Systick parameters.
+ * @{
+ */
+/**
+ * @brief Size in bits of the @p systick_t type.
+ */
+#define OSAL_ST_RESOLUTION 32
+
+/**
+ * @brief Systick mode required by the underlying OS.
+ */
+#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC
+/** @} */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Frequency in Hertz of the system tick.
+ */
+#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__)
+#define OSAL_ST_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Enables OSAL assertions.
+ */
+#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define OSAL_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Enables OSAL functions parameters checks.
+ */
+#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define OSAL_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief OSAL initialization hook.
+ */
+#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__)
+#define OSAL_INIT_HOOK()
+#endif
+
+/**
+ * @brief Idle loop hook macro.
+ */
+#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__)
+#define OSAL_IDLE_HOOK()
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a system status word.
+ */
+typedef uint8_t syssts_t;
+
+/**
+ * @brief Type of a message.
+ */
+typedef int16_t msg_t;
+
+/**
+ * @brief Type of system time counter.
+ */
+typedef uint32_t systime_t;
+
+/**
+ * @brief Type of realtime counter.
+ */
+typedef uint32_t rtcnt_t;
+
+/**
+ * @brief Type of a thread.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ */
+typedef struct {
+ volatile msg_t message;
+} thread_t;
+
+/**
+ * @brief Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+
+/**
+ * @brief Type of an event flags object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+typedef struct event_source event_source_t;
+
+/**
+ * @brief Type of an event source callback.
+ * @note This type is not part of the OSAL API and is provided
+ * exclusively as an example and for convenience.
+ */
+typedef void (*eventcallback_t)(event_source_t *esp);
+
+/**
+ * @brief Type of an event flags mask.
+ */
+typedef uint8_t eventflags_t;
+
+/**
+ * @brief Events source object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+struct event_source {
+ volatile eventflags_t flags; /**< @brief Stored event flags. */
+ eventcallback_t cb; /**< @brief Event source callback. */
+ void *param; /**< @brief User defined field. */
+};
+
+/**
+ * @brief Type of a mutex.
+ * @note If the OS does not support mutexes or there is no OS then them
+ * mechanism can be simulated.
+ */
+typedef uint8_t mutex_t;
+
+/**
+ * @brief Type of a thread queue.
+ * @details A thread queue is a queue of sleeping threads, queued threads
+ * can be dequeued one at time or all together.
+ * @note If the OSAL is implemented on a bare metal machine without RTOS
+ * then the queue can be implemented as a single thread reference.
+ */
+typedef struct {
+ thread_reference_t tr;
+} threads_queue_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name Debug related macros
+ * @{
+ */
+/**
+ * @brief Condition assertion.
+ * @details If the condition check fails then the OSAL panics with a
+ * message and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS
+ * switch is enabled.
+ * @note The remark string is not currently used except for putting a
+ * comment in the code about the assertion.
+ *
+ * @param[in] c the condition to be verified to be true
+ * @param[in] remark a remark string
+ *
+ * @api
+ */
+#define osalDbgAssert(c, remark) do { \
+ /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
+ if (OSAL_DBG_ENABLE_ASSERTS != FALSE) { \
+ if (!(c)) { \
+ /*lint -restore*/ \
+ osalSysHalt(__func__); \
+ } \
+ } \
+} while (false)
+
+/**
+ * @brief Function parameters check.
+ * @details If the condition check fails then the OSAL panics and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch
+ * is enabled.
+ *
+ * @param[in] c the condition to be verified to be true
+ *
+ * @api
+ */
+#define osalDbgCheck(c) do { \
+ /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
+ if (OSAL_DBG_ENABLE_CHECKS != FALSE) { \
+ if (!(c)) { \
+ /*lint -restore*/ \
+ osalSysHalt(__func__); \
+ } \
+ } \
+} while (false)
+
+/**
+ * @brief I-Class state check.
+ * @note Implementation is optional.
+ */
+#define osalDbgCheckClassI()
+
+/**
+ * @brief S-Class state check.
+ * @note Implementation is optional.
+ */
+#define osalDbgCheckClassS()
+/** @} */
+
+/**
+ * @name IRQ service routines wrappers
+ * @{
+ */
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers.
+ */
+#define OSAL_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers.
+ */
+#define OSAL_IRQ_EPILOGUE()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @details This macro hides the details of an ISR function declaration.
+ *
+ * @param[in] id a vector name as defined in @p vectors.s
+ */
+#define OSAL_IRQ_HANDLER(id) ISR(id)
+/** @} */
+
+/**
+ * @name Time conversion utilities
+ * @{
+ */
+/**
+ * @brief Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec number of seconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_S2ST(sec) \
+ ((systime_t)((uint32_t)(sec) * (uint32_t)OSAL_ST_FREQUENCY))
+
+/**
+ * @brief Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec number of milliseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_MS2ST(msec) \
+ ((systime_t)((((uint32_t)(msec)) * \
+ ((uint32_t)OSAL_ST_FREQUENCY) + 999UL) / 1000UL))
+
+/**
+ * @brief Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec number of microseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_US2ST(usec) \
+ ((systime_t)((((uint32_t)(usec)) * \
+ ((uint32_t)OSAL_ST_FREQUENCY) + 999999UL) / 1000000UL))
+/** @} */
+
+/**
+ * @name Time conversion utilities for the realtime counter
+ * @{
+ */
+/**
+ * @brief Seconds to realtime counter.
+ * @details Converts from seconds to realtime counter cycles.
+ * @note The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] sec number of seconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_S2RTC(freq, sec) ((freq) * (sec))
+
+/**
+ * @brief Milliseconds to realtime counter.
+ * @details Converts from milliseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next millisecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] msec number of milliseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec))
+
+/**
+ * @brief Microseconds to realtime counter.
+ * @details Converts from microseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next microsecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] usec number of microseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec))
+/** @} */
+
+/**
+ * @name Sleep macros using absolute time
+ * @{
+ */
+/**
+ * @brief Delays the invoking thread for the specified number of seconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] sec time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * milliseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] msec time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * microseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] usec time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+extern const char *osal_halt_msg;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void osalInit(void);
+ void osalSysHalt(const char *reason);
+ void osalSysPolledDelayX(rtcnt_t cycles);
+ void osalOsTimerHandlerI(void);
+ void osalOsRescheduleS(void);
+ systime_t osalOsGetSystemTimeX(void);
+ void osalThreadSleepS(systime_t time);
+ void osalThreadSleep(systime_t time);
+ msg_t osalThreadSuspendS(thread_reference_t *trp);
+ msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
+ void osalThreadResumeI(thread_reference_t *trp, msg_t msg);
+ void osalThreadResumeS(thread_reference_t *trp, msg_t msg);
+ msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout);
+ void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg);
+ void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg);
+ void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags);
+ void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags);
+ void osalEventSetCallback(event_source_t *esp,
+ eventcallback_t cb,
+ void *param);
+ void osalMutexLock(mutex_t *mp);
+ void osalMutexUnlock(mutex_t *mp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysDisable(void) {
+
+ asm volatile ("cli" : : : "memory");
+}
+
+/**
+ * @brief Enables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysEnable(void) {
+
+ asm volatile ("sei" : : : "memory");
+ asm volatile ("nop");
+}
+
+/**
+ * @brief Enters a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLock(void) {
+
+ asm volatile ("cli" : : : "memory");
+}
+
+/**
+ * @brief Leaves a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlock(void) {
+
+ asm volatile ("sei" : : : "memory");
+ asm volatile ("nop");
+}
+
+/**
+ * @brief Enters a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ * @note This function is empty in this port.
+ *
+ * @special
+ */
+static inline void osalSysLockFromISR(void) {
+
+}
+
+/**
+ * @brief Leaves a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ * @note This function is empty in this port.
+ *
+ * @special
+ */
+static inline void osalSysUnlockFromISR(void) {
+
+}
+
+/**
+ * @brief Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ * from any context. Because its flexibility it is less efficient
+ * than @p chSysLock() which is preferable when the calling context
+ * is known.
+ * @post The system is in a critical zone.
+ *
+ * @return The previous system status, the encoding of this
+ * status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+static inline syssts_t osalSysGetStatusAndLockX(void) {
+ syssts_t sts;
+
+ sts = SREG;
+ asm volatile ("cli" : : : "memory");
+
+ return sts;
+}
+
+/**
+ * @brief Restores the specified execution status and leaves a critical zone.
+ * @note A call to @p chSchRescheduleS() is automatically performed
+ * if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts the system status to be restored.
+ *
+ * @xclass
+ */
+static inline void osalSysRestoreStatusX(syssts_t sts) {
+
+ if ((sts & 0x80) != 0) {
+ asm volatile ("sei" : : : "memory");
+ asm volatile ("nop");
+ }
+}
+
+/**
+ * @brief Checks if the specified time is within the specified time window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ * @note This function can be called from any context.
+ *
+ * @param[in] time the time to be verified
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool osalOsIsTimeWithinX(systime_t time,
+ systime_t start,
+ systime_t end) {
+
+ return (bool)((time - start) < (end - start));
+}
+
+/**
+ * @brief Initializes a threads queue object.
+ *
+ * @param[out] tqp pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) {
+
+ osalDbgCheck(tqp != NULL);
+
+ (void)tqp;
+}
+
+/**
+ * @brief Initializes an event flags object.
+ *
+ * @param[out] esp pointer to the event flags object
+ *
+ * @init
+ */
+static inline void osalEventObjectInit(event_source_t *esp) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->flags = (eventflags_t)0;
+ esp->cb = NULL;
+ esp->param = NULL;
+}
+
+/**
+ * @brief Initializes s @p mutex_t object.
+ *
+ * @param[out] mp pointer to the @p mutex_t object
+ *
+ * @init
+ */
+static inline void osalMutexObjectInit(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 0;
+}
+
+#endif /* _OSAL_H_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.mk
new file mode 100644
index 0000000000..387598ed97
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/os-less/AVR/osal.mk
@@ -0,0 +1,5 @@
+# OSAL files.
+OSALSRC += ${CHIBIOS}/os/hal/osal/os-less/AVR/osal.c
+
+# Required include directories
+OSALINC += ${CHIBIOS}/os/hal/osal/os-less/AVR
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.c
new file mode 100644
index 0000000000..32db7dcc4b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.c
@@ -0,0 +1,51 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.c
+ * @brief OSAL module code.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#include "osal.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.h
new file mode 100644
index 0000000000..ca6baa3bc8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.h
@@ -0,0 +1,941 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.h
+ * @brief OSAL module header.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#ifndef _OSAL_H_
+#define _OSAL_H_
+
+#include
+#include
+#include
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Common constants
+ * @{
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE (!FALSE)
+#endif
+
+#define OSAL_SUCCESS FALSE
+#define OSAL_FAILED TRUE
+/** @} */
+
+#if 0
+/**
+ * @name Messages
+ * @{
+ */
+#define MSG_OK RDY_OK
+#define MSG_RESET RDY_RESET
+#define MSG_TIMEOUT RDY_TIMEOUT
+/** @} */
+#endif
+
+#if 0
+/**
+ * @name Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE ((systime_t)0)
+#define TIME_INFINITE ((systime_t)-1)
+/** @} */
+#endif
+
+/**
+ * @name Systick modes.
+ * @{
+ */
+#define OSAL_ST_MODE_NONE 0
+#define OSAL_ST_MODE_PERIODIC 1
+#define OSAL_ST_MODE_FREERUNNING 2
+/** @} */
+
+/**
+ * @name Systick parameters.
+ * @{
+ */
+/**
+ * @brief Size in bits of the @p systick_t type.
+ */
+#define OSAL_ST_RESOLUTION CH_CFG_ST_RESOLUTION
+
+/**
+ * @brief Required systick frequency or resolution.
+ */
+#define OSAL_ST_FREQUENCY CH_CFG_ST_FREQUENCY
+
+/**
+ * @brief Systick mode required by the underlying OS.
+ */
+#if (CH_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__)
+#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC
+#else
+#define OSAL_ST_MODE OSAL_ST_MODE_FREERUNNING
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !(OSAL_ST_MODE == OSAL_ST_MODE_NONE) && \
+ !(OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) && \
+ !(OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING)
+#error "invalid OSAL_ST_MODE setting in osal.h"
+#endif
+
+#if (OSAL_ST_RESOLUTION != 16) && (OSAL_ST_RESOLUTION != 32)
+#error "invalid OSAL_ST_RESOLUTION, must be 16 or 32"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+#if 0
+/**
+ * @brief Type of a system status word.
+ */
+typedef uint32_t syssts_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of a message.
+ */
+typedef int32_t msg_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of system time counter.
+ */
+typedef uint32_t systime_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of realtime counter.
+ */
+typedef uint32_t rtcnt_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of an event flags mask.
+ */
+typedef uint32_t eventflags_t;
+#endif
+
+#if !CH_CFG_USE_EVENTS
+/**
+ * @brief Type of an event flags object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+typedef struct {
+ volatile eventflags_t flags; /**< @brief Flags stored into the
+ object. */
+} event_source_t;
+#endif
+
+/**
+ * @brief Type of a mutex.
+ * @note If the OS does not support mutexes or there is no OS then them
+ * mechanism can be simulated.
+ */
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+#elif CH_CFG_USE_SEMAPHORES
+typedef semaphore_t mutex_t;
+#else
+typedef uint32_t mutex_t;
+#endif
+
+#if 0
+/**
+ * @brief Type of a thread queue.
+ * @details A thread queue is a queue of sleeping threads, queued threads
+ * can be dequeued one at time or all together.
+ * @note In this implementation it is implemented as a single reference
+ * because there are no real threads.
+ */
+typedef struct {
+ thread_reference_t tr;
+} threads_queue_t;
+#endif
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/* Temporary names provided for ChibiOS 2.x compatibility.*/
+#define osalQueueInit osalThreadQueueObjectInit
+#define osalQueueWakeupAllI osalThreadDequeueAllI
+#define osalQueueWakeupOneI osalThreadDequeueNextI
+#define osalQueueGoSleepTimeoutS osalThreadEnqueueTimeoutS
+#define osalEventInit osalEventObjectInit
+
+/**
+ * @name Debug related macros
+ * @{
+ */
+/**
+ * @brief Condition assertion.
+ * @details If the condition check fails then the OSAL panics with a
+ * message and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS
+ * switch is enabled.
+ * @note The remark string is not currently used except for putting a
+ * comment in the code about the assertion.
+ *
+ * @param[in] c the condition to be verified to be true
+ * @param[in] remark a remark string
+ *
+ * @api
+ */
+#define osalDbgAssert(c, remark) chDbgAssert(c, remark)
+
+/**
+ * @brief Function parameters check.
+ * @details If the condition check fails then the OSAL panics and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch
+ * is enabled.
+ *
+ * @param[in] c the condition to be verified to be true
+ *
+ * @api
+ */
+#define osalDbgCheck(c) chDbgCheck(c)
+
+/**
+ * @brief I-Class state check.
+ * @note Not implemented in this simplified OSAL.
+ */
+#define osalDbgCheckClassI() chDbgCheckClassI()
+
+/**
+ * @brief S-Class state check.
+ * @note Not implemented in this simplified OSAL.
+ */
+#define osalDbgCheckClassS() chDbgCheckClassS()
+/** @} */
+
+/**
+ * @name IRQ service routines wrappers
+ * @{
+ */
+/**
+ * @brief Priority level verification macro.
+ */
+#define OSAL_IRQ_IS_VALID_PRIORITY(n) CH_IRQ_IS_VALID_KERNEL_PRIORITY(n)
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers.
+ */
+#define OSAL_IRQ_PROLOGUE() CH_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers.
+ */
+#define OSAL_IRQ_EPILOGUE() CH_IRQ_EPILOGUE()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @details This macro hides the details of an ISR function declaration.
+ *
+ * @param[in] id a vector name as defined in @p vectors.s
+ */
+#define OSAL_IRQ_HANDLER(id) CH_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name Time conversion utilities
+ * @{
+ */
+/**
+ * @brief Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec number of seconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_S2ST(sec) S2ST(sec)
+
+/**
+ * @brief Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec number of milliseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_MS2ST(msec) MS2ST(msec)
+
+/**
+ * @brief Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec number of microseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_US2ST(usec) US2ST(usec)
+/** @} */
+
+/**
+ * @name Time conversion utilities for the realtime counter
+ * @{
+ */
+/**
+ * @brief Seconds to realtime counter.
+ * @details Converts from seconds to realtime counter cycles.
+ * @note The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] sec number of seconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_S2RTC(freq, sec) S2RTC(freq, sec)
+
+/**
+ * @brief Milliseconds to realtime counter.
+ * @details Converts from milliseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next millisecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] msec number of milliseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_MS2RTC(freq, msec) MS2RTC(freq, msec)
+
+/**
+ * @brief Microseconds to realtime counter.
+ * @details Converts from microseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next microsecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] usec number of microseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_US2RTC(freq, usec) US2RTC(freq, usec)
+/** @} */
+
+/**
+ * @name Sleep macros using absolute time
+ * @{
+ */
+/**
+ * @brief Delays the invoking thread for the specified number of seconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] sec time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * milliseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] msec time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * microseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] usec time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief OSAL module initialization.
+ *
+ * @api
+ */
+static inline void osalInit(void) {
+
+}
+
+/**
+ * @brief System halt with error message.
+ *
+ * @param[in] reason the halt message pointer
+ *
+ * @api
+ */
+static inline void osalSysHalt(const char *reason) {
+
+ chSysHalt(reason);
+}
+
+/**
+ * @brief Disables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysDisable(void) {
+
+ chSysDisable();
+}
+
+/**
+ * @brief Enables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysEnable(void) {
+
+ chSysEnable();
+}
+
+/**
+ * @brief Enters a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLock(void) {
+
+ chSysLock();
+}
+
+/**
+ * @brief Leaves a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlock(void) {
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Enters a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLockFromISR(void) {
+
+ chSysLockFromISR();
+}
+
+/**
+ * @brief Leaves a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlockFromISR(void) {
+
+ chSysUnlockFromISR();
+}
+
+/**
+ * @brief Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ * from any context. Because its flexibility it is less efficient
+ * than @p chSysLock() which is preferable when the calling context
+ * is known.
+ * @post The system is in a critical zone.
+ *
+ * @return The previous system status, the encoding of this
+ * status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+static inline syssts_t osalSysGetStatusAndLockX(void) {
+
+ return chSysGetStatusAndLockX();
+}
+
+/**
+ * @brief Restores the specified execution status and leaves a critical zone.
+ * @note A call to @p chSchRescheduleS() is automatically performed
+ * if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts the system status to be restored.
+ *
+ * @xclass
+ */
+static inline void osalSysRestoreStatusX(syssts_t sts) {
+
+ chSysRestoreStatusX(sts);
+}
+
+/**
+ * @brief Polled delay.
+ * @note The real delay is always few cycles in excess of the specified
+ * value.
+ *
+ * @param[in] cycles number of cycles
+ *
+ * @xclass
+ */
+#if PORT_SUPPORTS_RT || defined(__DOXYGEN__)
+static inline void osalSysPolledDelayX(rtcnt_t cycles) {
+
+ chSysPolledDelayX(cycles);
+}
+#endif
+
+/**
+ * @brief Systick callback for the underlying OS.
+ * @note This callback is only defined if the OSAL requires such a
+ * service from the HAL.
+ */
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+static inline void osalOsTimerHandlerI(void) {
+
+ chSysTimerHandlerI();
+}
+#endif
+
+/**
+ * @brief Checks if a reschedule is required and performs it.
+ * @note I-Class functions invoked from thread context must not reschedule
+ * by themselves, an explicit reschedule using this function is
+ * required in this scenario.
+ * @note Not implemented in this simplified OSAL.
+ *
+ * @sclass
+ */
+static inline void osalOsRescheduleS(void) {
+
+ chSchRescheduleS();
+}
+
+/**
+ * @brief Current system time.
+ * @details Returns the number of system ticks since the @p osalInit()
+ * invocation.
+ * @note The counter can reach its maximum and then restart from zero.
+ * @note This function can be called from any context but its atomicity
+ * is not guaranteed on architectures whose word size is less than
+ * @p systime_t size.
+ *
+ * @return The system time in ticks.
+ *
+ * @xclass
+ */
+static inline systime_t osalOsGetSystemTimeX(void) {
+
+ return chVTGetSystemTimeX();
+}
+
+/**
+ * @brief Checks if the specified time is within the specified time window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ * @note This function can be called from any context.
+ *
+ * @param[in] time the time to be verified
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool osalOsIsTimeWithinX(systime_t time,
+ systime_t start,
+ systime_t end) {
+
+ return chVTIsTimeWithinX(time, start, end);
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @sclass
+ */
+static inline void osalThreadSleepS(systime_t time) {
+
+ chThdSleepS(time);
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @api
+ */
+static inline void osalThreadSleep(systime_t time) {
+
+ chThdSleep(time);
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @return The wake up message.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadSuspendS(thread_reference_t *trp) {
+
+ return chThdSuspendS(trp);
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The wake up message.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp,
+ systime_t timeout) {
+
+ return chThdSuspendTimeoutS(trp, timeout);
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must not reschedule because it can be called from
+ * ISR context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadResumeI(thread_reference_t *trp, msg_t msg) {
+
+ chThdResumeI(trp, msg);
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadResumeS(thread_reference_t *trp, msg_t msg) {
+
+ chThdResumeS(trp, msg);
+}
+
+/**
+ * @brief Initializes a threads queue object.
+ *
+ * @param[out] tqp pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) {
+
+ chThdQueueObjectInit(tqp);
+}
+
+/**
+ * @brief Enqueues the caller thread.
+ * @details The caller thread is enqueued and put to sleep until it is
+ * dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] time the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The message from @p osalQueueWakeupOneI() or
+ * @p osalQueueWakeupAllI() functions.
+ * @retval MSG_TIMEOUT if the thread has not been dequeued within the
+ * specified timeout or if the function has been
+ * invoked with @p TIME_IMMEDIATE as timeout
+ * specification.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp,
+ systime_t time) {
+
+ return chThdEnqueueTimeoutS(tqp, time);
+}
+
+/**
+ * @brief Dequeues and wakes up one thread from the queue, if any.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+
+ chThdDequeueNextI(tqp, msg);
+}
+
+/**
+ * @brief Dequeues and wakes up all threads from the queue.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+
+ chThdDequeueAllI(tqp, msg);
+}
+
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
+/**
+ * @brief Initializes an event flags object.
+ *
+ * @param[out] esp pointer to the event flags object
+ *
+ * @init
+ */
+static inline void osalEventObjectInit(event_source_t *esp) {
+
+ chEvtObjectInit(esp);
+}
+#else
+static inline void osalEventObjectInit(event_source_t *esp) {
+
+ esp->flags = 0;
+}
+#endif
+
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlagsI(event_source_t *esp,
+ eventflags_t flags) {
+
+ chEvtBroadcastFlagsI(esp, flags);
+}
+#else
+static inline void osalEventBroadcastFlagsI(event_source_t *esp,
+ eventflags_t flags) {
+
+ esp->flags |= flags;
+}
+#endif
+
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlags(event_source_t *esp,
+ eventflags_t flags) {
+
+ chEvtBroadcastFlags(esp, flags);
+}
+#else
+static inline void osalEventBroadcastFlags(event_source_t *esp,
+ eventflags_t flags) {
+ osalSysLock();
+ esp->flags |= flags;
+ osalSysUnlock();
+}
+#endif
+
+/**
+ * @brief Initializes s @p mutex_t object.
+ *
+ * @param[out] mp pointer to the @p mutex_t object
+ *
+ * @init
+ */
+static inline void osalMutexObjectInit(mutex_t *mp) {
+
+#if CH_CFG_USE_MUTEXES
+ chMtxObjectInit(mp);
+#elif CH_CFG_USE_SEMAPHORES
+ chSemObjectInit((semaphore_t *)mp, 1);
+#else
+ *mp = 0;
+#endif
+}
+
+/**
+ * @brief Locks the specified mutex.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexLock(mutex_t *mp) {
+
+#if CH_CFG_USE_MUTEXES
+ chMtxLock(mp);
+#elif CH_CFG_USE_SEMAPHORES
+ chSemWait((semaphore_t *)mp);
+#else
+ *mp = 1;
+#endif
+}
+
+/**
+ * @brief Unlocks the specified mutex.
+ * @note The HAL guarantees to release mutex in reverse lock order. The
+ * mutex being unlocked is guaranteed to be the last locked mutex
+ * by the invoking thread.
+ * The implementation can rely on this behavior and eventually
+ * ignore the @p mp parameter which is supplied in order to support
+ * those OSes not supporting a stack of the owned mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexUnlock(mutex_t *mp) {
+
+#if CH_CFG_USE_MUTEXES
+ chMtxUnlock(mp);
+#elif CH_CFG_USE_SEMAPHORES
+ chSemSignal((semaphore_t *)mp);
+#else
+ *mp = 0;
+#endif
+}
+
+#endif /* _OSAL_H_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.mk
new file mode 100644
index 0000000000..f1559d9d51
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/osal/rt/osal.mk
@@ -0,0 +1,5 @@
+# OSAL files.
+OSALSRC += ${CHIBIOS}/os/hal/osal/rt/osal.c
+
+# Required include directories
+OSALINC += ${CHIBIOS}/os/hal/osal/rt
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv2/i2c_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv2/i2c_lld.c
deleted file mode 100644
index d02ba2319e..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv2/i2c_lld.c
+++ /dev/null
@@ -1,789 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file STM32/I2Cv2/i2c_lld.c
- * @brief STM32 I2C subsystem low level driver source.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define DMAMODE_COMMON \
- (STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | \
- STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | \
- STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE)
-
-#define I2C1_RX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \
- STM32_I2C1_RX_DMA_CHN)
-
-#define I2C1_TX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \
- STM32_I2C1_TX_DMA_CHN)
-
-#define I2C2_RX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \
- STM32_I2C2_RX_DMA_CHN)
-
-#define I2C2_TX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \
- STM32_I2C2_TX_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define I2C_MASTER_TC \
- ((uint32_t)(I2C_ISR_BUSY | I2C_ISR_TC))
-
-#define I2C_ERROR_MASK \
- ((uint32_t)(I2C_ISR_BERR | I2C_ISR_ARLO | I2C_ISR_OVR | I2C_ISR_PECERR | \
- I2C_ISR_TIMEOUT | I2C_ISR_ALERT))
-
-#define I2C_INT_MASK \
- ((uint32_t)(I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF | I2C_ISR_NACKF | \
- I2C_ISR_ADDR | I2C_ISR_RXNE | I2C_ISR_TXIS))
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief I2C1 driver identifier.*/
-#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/** @brief I2C2 driver identifier.*/
-#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
-I2CDriver I2CD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Wakes up the waiting thread.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] msg wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) { \
- chSysLockFromIsr(); \
- if ((i2cp)->thread != NULL) { \
- Thread *tp = (i2cp)->thread; \
- (i2cp)->thread = NULL; \
- tp->p_u.rdymsg = (msg); \
- chSchReadyI(tp); \
- } \
- chSysUnlockFromIsr(); \
-}
-
-/**
- * @brief Aborts an I2C transaction.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_abort_operation(I2CDriver *i2cp) {
- I2C_TypeDef *dp = i2cp->i2c;
-
- if (dp->CR1 & I2C_CR1_PE) {
- /* Stops the I2C peripheral.*/
- dp->CR1 &= ~I2C_CR1_PE;
- while (dp->CR1 & I2C_CR1_PE)
- dp->CR1 &= ~I2C_CR1_PE;
- dp->CR1 |= I2C_CR1_PE;
- }
-
- /* Stops the associated DMA streams.*/
- dmaStreamDisable(i2cp->dmatx);
- dmaStreamDisable(i2cp->dmarx);
-}
-
-/**
- * @brief Handling of stalled I2C transactions.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_safety_timeout(void *p) {
- I2CDriver *i2cp = (I2CDriver *)p;
-
- chSysLockFromIsr();
- if (i2cp->thread) {
- Thread *tp = i2cp->thread;
- i2c_lld_abort_operation(i2cp);
- i2cp->thread = NULL;
- tp->p_u.rdymsg = RDY_TIMEOUT;
- chSchReadyI(tp);
- }
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief I2C shared ISR code.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] isr content of the ISR register to be decoded
- *
- * @notapi
- */
-static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t isr) {
- I2C_TypeDef *dp = i2cp->i2c;
-
- if ((isr & I2C_ISR_TC) && (i2cp->state == I2C_ACTIVE_TX)) {
- size_t rxbytes;
-
- /* Make sure no more 'Transfer complete' interrupts.*/
- dp->CR1 &= ~I2C_CR1_TCIE;
-
- rxbytes = dmaStreamGetTransactionSize(i2cp->dmarx);
- if (rxbytes > 0) {
- i2cp->state = I2C_ACTIVE_RX;
-
- /* Enable RX DMA */
- dmaStreamEnable(i2cp->dmarx);
-
- dp->CR2 &= ~I2C_CR2_NBYTES;
- dp->CR2 |= rxbytes << 16;
-
- /* Starts the read operation.*/
- dp->CR2 |= I2C_CR2_RD_WRN;
- dp->CR2 |= I2C_CR2_START;
- }
- else {
- /* Nothing to receive - send STOP immediately.*/
- dp->CR2 |= I2C_CR2_STOP;
- }
- }
- if (isr & I2C_ISR_NACKF) {
- /* Starts a STOP sequence immediately on error.*/
- dp->CR2 |= I2C_CR2_STOP;
-
- i2cp->errors |= I2CD_ACK_FAILURE;
- }
- if (isr & I2C_ISR_STOPF) {
- /* Stops the associated DMA streams.*/
- dmaStreamDisable(i2cp->dmatx);
- dmaStreamDisable(i2cp->dmarx);
-
- if (i2cp->errors) {
- wakeup_isr(i2cp, RDY_RESET);
- }
- else {
- wakeup_isr(i2cp, RDY_OK);
- }
- }
-}
-
-/**
- * @brief DMA RX end IRQ handler.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] flags pre-shifted content of the ISR register
- *
- * @notapi
- */
-static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
- I2C_TypeDef *dp = i2cp->i2c;
-
- /* DMA errors handling.*/
-#if defined(STM32_I2C_DMA_ERROR_HOOK)
- if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
- STM32_I2C_DMA_ERROR_HOOK(i2cp);
- }
-#else
- (void)flags;
-#endif
-
- dmaStreamDisable(i2cp->dmarx);
- dp->CR2 |= I2C_CR2_STOP;
- wakeup_isr(i2cp, RDY_OK);
-}
-
-/**
- * @brief DMA TX end IRQ handler.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
-
- /* DMA errors handling.*/
-#if defined(STM32_I2C_DMA_ERROR_HOOK)
- if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
- STM32_I2C_DMA_ERROR_HOOK(i2cp);
- }
-#else
- (void)flags;
-#endif
-
- dmaStreamDisable(i2cp->dmatx);
-}
-
-/**
- * @brief I2C error handler.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] isr content of the ISR register to be decoded
- *
- * @notapi
- */
-static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t isr) {
-
- /* Clears interrupt flags just to be safe.*/
- dmaStreamDisable(i2cp->dmatx);
- dmaStreamDisable(i2cp->dmarx);
-
- if (isr & I2C_ISR_BERR)
- i2cp->errors |= I2CD_BUS_ERROR;
-
- if (isr & I2C_ISR_ARLO)
- i2cp->errors |= I2CD_ARBITRATION_LOST;
-
- if (isr & I2C_ISR_OVR)
- i2cp->errors |= I2CD_OVERRUN;
-
- if (isr & I2C_ISR_TIMEOUT)
- i2cp->errors |= I2CD_TIMEOUT;
-
- /* If some error has been identified then sends wakes the waiting thread.*/
- if (i2cp->errors != I2CD_NO_ERROR)
- wakeup_isr(i2cp, RDY_RESET);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
-#if defined(STM32_I2C1_GLOBAL_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief I2C1 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(STM32_I2C1_GLOBAL_HANDLER) {
- uint32_t isr = I2CD1.i2c->ISR;
-
- CH_IRQ_PROLOGUE();
-
- /* Clearing IRQ bits.*/
- I2CD1.i2c->ICR = isr;
-
- if (isr & I2C_ERROR_MASK)
- i2c_lld_serve_error_interrupt(&I2CD1, isr);
- else if (isr & I2C_INT_MASK)
- i2c_lld_serve_interrupt(&I2CD1, isr);
-
- CH_IRQ_EPILOGUE();
-}
-
-#elif defined(STM32_I2C1_EVENT_HANDLER) && defined(STM32_I2C1_ERROR_HANDLER)
-CH_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) {
- uint32_t isr = I2CD1.i2c->ISR;
-
- CH_IRQ_PROLOGUE();
-
- /* Clearing IRQ bits.*/
- I2CD1.i2c->ICR = isr & I2C_INT_MASK;
-
- i2c_lld_serve_interrupt(&I2CD1, isr);
-
- CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) {
- uint32_t isr = I2CD1.i2c->ISR;
-
- CH_IRQ_PROLOGUE();
-
- /* Clearing IRQ bits.*/
- I2CD1.i2c->ICR = isr & I2C_ERROR_MASK;
-
- i2c_lld_serve_error_interrupt(&I2CD1, isr);
-
- CH_IRQ_EPILOGUE();
-}
-
-#else
-#error "I2C1 interrupt handlers not defined"
-#endif
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
-#if defined(STM32_I2C2_GLOBAL_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief I2C2 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(STM32_I2C2_GLOBAL_HANDLER) {
- uint32_t isr = I2CD2.i2c->ISR;
-
- CH_IRQ_PROLOGUE();
-
- /* Clearing IRQ bits.*/
- I2CD2.i2c->ICR = isr;
-
- if (isr & I2C_ERROR_MASK)
- i2c_lld_serve_error_interrupt(&I2CD2, isr);
- else if (isr & I2C_INT_MASK)
- i2c_lld_serve_interrupt(&I2CD2, isr);
-
- CH_IRQ_EPILOGUE();
-}
-
-#elif defined(STM32_I2C2_EVENT_HANDLER) && defined(STM32_I2C2_ERROR_HANDLER)
-CH_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) {
- uint32_t isr = I2CD2.i2c->ISR;
-
- CH_IRQ_PROLOGUE();
-
- /* Clearing IRQ bits.*/
- I2CD2.i2c->ICR = isr & I2C_INT_MASK;
-
- i2c_lld_serve_interrupt(&I2CD2, isr);
-
- CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) {
- uint32_t isr = I2CD2.i2c->ISR;
-
- CH_IRQ_PROLOGUE();
-
- /* Clearing IRQ bits.*/
- I2CD2.i2c->ICR = isr & I2C_ERROR_MASK;
-
- i2c_lld_serve_error_interrupt(&I2CD2, isr);
-
- CH_IRQ_EPILOGUE();
-}
-
-#else
-#error "I2C2 interrupt handlers not defined"
-#endif
-#endif /* STM32_I2C_USE_I2C2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if STM32_I2C_USE_I2C1
- i2cObjectInit(&I2CD1);
- I2CD1.thread = NULL;
- I2CD1.i2c = I2C1;
- I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
- I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2
- i2cObjectInit(&I2CD2);
- I2CD2.thread = NULL;
- I2CD2.i2c = I2C2;
- I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
- I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
-#endif /* STM32_I2C_USE_I2C2 */
-}
-
-/**
- * @brief Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
- I2C_TypeDef *dp = i2cp->i2c;
-
- i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P;
- i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M;
-
- /* Make sure I2C peripheral is disabled */
- dp->CR1 &= ~I2C_CR1_PE;
-
- /* If in stopped state then enables the I2C and DMA clocks.*/
- if (i2cp->state == I2C_STOP) {
-
-#if STM32_I2C_USE_I2C1
- if (&I2CD1 == i2cp) {
- bool_t b;
-
- rccResetI2C1();
- b = dmaStreamAllocate(i2cp->dmarx,
- STM32_I2C_I2C1_IRQ_PRIORITY,
- (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
- (void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated");
- b = dmaStreamAllocate(i2cp->dmatx,
- STM32_I2C_I2C1_IRQ_PRIORITY,
- (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
- (void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated");
- rccEnableI2C1(FALSE);
-
-#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
- nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
-#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER)
- nvicEnableVector(STM32_I2C1_EVENT_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
- nvicEnableVector(STM32_I2C1_ERROR_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
-#else
-#error "I2C1 interrupt numbers not defined"
-#endif
-
- i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
- i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
- }
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2
- if (&I2CD2 == i2cp) {
- bool_t b;
-
- rccResetI2C2();
- b = dmaStreamAllocate(i2cp->dmarx,
- STM32_I2C_I2C2_IRQ_PRIORITY,
- (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
- (void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated");
- b = dmaStreamAllocate(i2cp->dmatx,
- STM32_I2C_I2C2_IRQ_PRIORITY,
- (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
- (void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated");
- rccEnableI2C2(FALSE);
-
-#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
- nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
-#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER)
- nvicEnableVector(STM32_I2C2_EVENT_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
- nvicEnableVector(STM32_I2C2_ERROR_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
-#else
-#error "I2C2 interrupt numbers not defined"
-#endif
-
- i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
- i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
- }
-#endif /* STM32_I2C_USE_I2C2 */
- }
-
- /* I2C registers pointed by the DMA.*/
- dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR);
- dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR);
-
- /* Reset i2c peripheral, the TCIE bit will be handled separately.*/
- dp->CR1 = i2cp->config->cr1 | I2C_CR1_ERRIE | I2C_CR1_STOPIE |
- I2C_CR1_NACKIE | I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN;
-
- /* Set slave address field (master mode) */
- dp->CR2 = (i2cp->config->cr2 & ~I2C_CR2_SADD);
-
- /* Setup I2C parameters.*/
- dp->TIMINGR = i2cp->config->timingr;
-
- /* Ready to go.*/
- dp->CR1 |= I2C_CR1_PE;
-}
-
-/**
- * @brief Deactivates the I2C peripheral.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
- /* If not in stopped state then disables the I2C clock.*/
- if (i2cp->state != I2C_STOP) {
-
- /* I2C disable.*/
- i2c_lld_abort_operation(i2cp);
- dmaStreamRelease(i2cp->dmatx);
- dmaStreamRelease(i2cp->dmarx);
-
-#if STM32_I2C_USE_I2C1
- if (&I2CD1 == i2cp) {
-#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
- nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER);
-#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER)
- nvicDisableVector(STM32_I2C1_EVENT_NUMBER);
- nvicDisableVector(STM32_I2C1_ERROR_NUMBER);
-#else
-#error "I2C1 interrupt numbers not defined"
-#endif
-
- rccDisableI2C1(FALSE);
- }
-#endif
-
-#if STM32_I2C_USE_I2C2
- if (&I2CD2 == i2cp) {
-#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
- nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER);
-#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER)
- nvicDisableVector(STM32_I2C2_EVENT_NUMBER);
- nvicDisableVector(STM32_I2C2_ERROR_NUMBER);
-#else
-#error "I2C2 interrupt numbers not defined"
-#endif
-
- rccDisableI2C2(FALSE);
- }
-#endif
- }
-}
-
-/**
- * @brief Receives data via the I2C bus as master.
- * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
- * hardware restriction.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a
- * timeout the driver must be stopped and restarted
- * because the bus is in an uncertain state.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
- I2C_TypeDef *dp = i2cp->i2c;
- VirtualTimer vt;
- uint32_t addr_cr2 = addr & I2C_CR2_SADD;
-
- chDbgCheck((rxbytes > 0), "i2c_lld_master_receive_timeout");
-
- /* Resetting error flags for this transfer.*/
- i2cp->errors = I2CD_NO_ERROR;
-
- /* Global timeout for the whole operation.*/
- if (timeout != TIME_INFINITE)
- chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
- /* Releases the lock from high level driver.*/
- chSysUnlock();
-
- /* Waits until BUSY flag is reset and the STOP from the previous operation
- is completed, alternatively for a timeout condition.*/
- while (dp->ISR & I2C_ISR_BUSY) {
- chSysLock();
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
- chSysUnlock();
- }
-
- /* This lock will be released in high level driver.*/
- chSysLock();
-
- /* Adjust slave address (master mode) for 7-bit address mode */
- if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
- addr_cr2 = (addr_cr2 & 0x7f) << 1;
-
- /* Set slave address field (master mode) */
- dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES);
- dp->CR2 |= (rxbytes << 16) | addr_cr2;
-
- /* Initializes driver fields */
- i2cp->errors = 0;
-
- /* RX DMA setup.*/
- dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
- dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
- dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
-
- /* Enable RX DMA */
- dmaStreamEnable(i2cp->dmarx);
-
- /* Atomic check on the timer in order to make sure that a timeout didn't
- happen outside the critical zone.*/
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
-
- /* Starts the operation.*/
- dp->CR2 |= I2C_CR2_RD_WRN;
- dp->CR2 |= I2C_CR2_START;
-
- /* Waits for the operation completion or a timeout.*/
- i2cp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
- chVTResetI(&vt);
-
- return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief Transmits data via the I2C bus as master.
- * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
- * This is hardware restriction.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[in] txbuf pointer to the transmit buffer
- * @param[in] txbytes number of bytes to be transmitted
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a
- * timeout the driver must be stopped and restarted
- * because the bus is in an uncertain state.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
- I2C_TypeDef *dp = i2cp->i2c;
- VirtualTimer vt;
- uint32_t addr_cr2 = addr & I2C_CR2_SADD;
-
- chDbgCheck(((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))),
- "i2c_lld_master_transmit_timeout");
-
- /* Resetting error flags for this transfer.*/
- i2cp->errors = I2CD_NO_ERROR;
-
- /* Global timeout for the whole operation.*/
- if (timeout != TIME_INFINITE)
- chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
- /* Releases the lock from high level driver.*/
- chSysUnlock();
-
- /* Waits until BUSY flag is reset and the STOP from the previous operation
- is completed, alternatively for a timeout condition.*/
- while (dp->ISR & I2C_ISR_BUSY) {
- chSysLock();
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
- chSysUnlock();
- }
-
- /* This lock will be released in high level driver.*/
- chSysLock();
-
- /* Adjust slave address (master mode) for 7-bit address mode */
- if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
- addr_cr2 = (addr_cr2 & 0x7f) << 1;
-
- /* Set slave address field (master mode) */
- dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES);
- dp->CR2 |= (txbytes << 16) | addr_cr2;
-
- /* Initializes driver fields */
- i2cp->errors = 0;
-
- /* TX DMA setup.*/
- dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
- dmaStreamSetMemory0(i2cp->dmatx, txbuf);
- dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
-
- /* RX DMA setup.*/
- dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
- dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
- dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
-
- /* Enable TX DMA */
- dmaStreamEnable(i2cp->dmatx);
-
- /* Atomic check on the timer in order to make sure that a timeout didn't
- happen outside the critical zone.*/
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
-
- /* Transmission complete interrupt enabled.*/
- dp->CR1 |= I2C_CR1_TCIE;
-
- /* Starts the operation as the very last thing.*/
- dp->CR2 &= ~I2C_CR2_RD_WRN;
- dp->CR2 |= I2C_CR2_START;
-
- /* Waits for the operation completion or a timeout.*/
- i2cp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
- chVTResetI(&vt);
-
- return chThdSelf()->p_u.rdymsg;
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv2/rtc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv2/rtc_lld.c
deleted file mode 100644
index c853fee697..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv2/rtc_lld.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file STM32/RTCv2/rtc_lld.c
- * @brief RTC low level driver.
- *
- * @addtogroup RTC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief RTC driver identifier.
- */
-RTCDriver RTCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Wait for synchronization of RTC registers with APB1 bus.
- * @details This function must be invoked before trying to read RTC registers.
- *
- * @notapi
- */
-#define rtc_lld_apb1_sync() {while ((RTCD1.id_rtc->ISR & RTC_ISR_RSF) == 0);}
-
-/**
- * @brief Beginning of configuration procedure.
- *
- * @notapi
- */
-#define rtc_lld_enter_init() { \
- RTCD1.id_rtc->ISR |= RTC_ISR_INIT; \
- while ((RTCD1.id_rtc->ISR & RTC_ISR_INITF) == 0) \
- ; \
-}
-
-/**
- * @brief Finalizing of configuration procedure.
- *
- * @notapi
- */
-#define rtc_lld_exit_init() {RTCD1.id_rtc->ISR &= ~RTC_ISR_INIT;}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Enable access to registers.
- *
- * @api
- */
-void rtc_lld_init(void){
- RTCD1.id_rtc = RTC;
-
- /* Asynchronous part of preloader. Set it to maximum value. */
- uint32_t prediv_a = 0x7F;
-
- /* Disable write protection. */
- RTCD1.id_rtc->WPR = 0xCA;
- RTCD1.id_rtc->WPR = 0x53;
-
- /* If calendar not init yet. */
- if (!(RTC->ISR & RTC_ISR_INITS)){
- rtc_lld_enter_init();
-
- /* Prescaler register must be written in two SEPARATE writes. */
- prediv_a = (prediv_a << 16) |
- (((STM32_RTCCLK / (prediv_a + 1)) - 1) & 0x7FFF);
- RTCD1.id_rtc->PRER = prediv_a;
- RTCD1.id_rtc->PRER = prediv_a;
- rtc_lld_exit_init();
- }
-}
-
-/**
- * @brief Set current time.
- * @note Fractional part will be silently ignored. There is no possibility
- * to set it on STM32 platform.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
- (void)rtcp;
-
- rtc_lld_enter_init();
- if (timespec->h12)
- RTCD1.id_rtc->CR |= RTC_CR_FMT;
- else
- RTCD1.id_rtc->CR &= ~RTC_CR_FMT;
- RTCD1.id_rtc->TR = timespec->tv_time;
- RTCD1.id_rtc->DR = timespec->tv_date;
- rtc_lld_exit_init();
-}
-
-/**
- * @brief Get current time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
- (void)rtcp;
-
- rtc_lld_apb1_sync();
-
-#if STM32_RTC_HAS_SUBSECONDS
- timespec->tv_msec =
- (1000 * ((RTCD1.id_rtc->PRER & 0x7FFF) - RTCD1.id_rtc->SSR)) /
- ((RTCD1.id_rtc->PRER & 0x7FFF) + 1);
-#endif /* STM32_RTC_HAS_SUBSECONDS */
- timespec->tv_time = RTCD1.id_rtc->TR;
- timespec->tv_date = RTCD1.id_rtc->DR;
-}
-
-/**
- * @brief Set alarm time.
- *
- * @note Default value after BKP domain reset for both comparators is 0.
- * @note Function does not performs any checks of alarm time validity.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] alarm alarm identifier starting from zero
- * @param[in] alarmspec pointer to a @p RTCAlarm structure
- *
- * @api
- */
-void rtc_lld_set_alarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
- const RTCAlarm *alarmspec) {
-
- if (alarm == 0) {
- if (alarmspec != NULL){
- rtcp->id_rtc->CR &= ~RTC_CR_ALRAE;
- while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRAWF))
- ;
- rtcp->id_rtc->ALRMAR = alarmspec->tv_datetime;
- rtcp->id_rtc->CR |= RTC_CR_ALRAE;
- rtcp->id_rtc->CR |= RTC_CR_ALRAIE;
- }
- else {
- rtcp->id_rtc->CR &= ~RTC_CR_ALRAIE;
- rtcp->id_rtc->CR &= ~RTC_CR_ALRAE;
- }
- }
-#if RTC_ALARMS == 2
- else{
- if (alarmspec != NULL){
- rtcp->id_rtc->CR &= ~RTC_CR_ALRBE;
- while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRBWF))
- ;
- rtcp->id_rtc->ALRMBR = alarmspec->tv_datetime;
- rtcp->id_rtc->CR |= RTC_CR_ALRBE;
- rtcp->id_rtc->CR |= RTC_CR_ALRBIE;
- }
- else {
- rtcp->id_rtc->CR &= ~RTC_CR_ALRBIE;
- rtcp->id_rtc->CR &= ~RTC_CR_ALRBE;
- }
- }
-#endif /* RTC_ALARMS == 2 */
-}
-
-/**
- * @brief Get alarm time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] alarm alarm identifier starting from zero
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @api
- */
-void rtc_lld_get_alarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
- RTCAlarm *alarmspec) {
-
- if (alarm == 0)
- alarmspec->tv_datetime = rtcp->id_rtc->ALRMAR;
-#if RTC_ALARMS == 2
- else
- alarmspec->tv_datetime = rtcp->id_rtc->ALRMBR;
-#endif
-}
-
-/**
- * @brief Sets time of periodic wakeup.
- *
- * @note Default value after BKP domain reset is 0x0000FFFF
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] wakeupspec pointer to a @p RTCWakeup structure
- *
- * @api
- */
-#if RTC_HAS_PERIODIC_WAKEUPS
-void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, const RTCWakeup *wakeupspec) {
-
- if (wakeupspec != NULL){
- chDbgCheck((wakeupspec->wakeup != 0x30000),
- "rtc_lld_set_periodic_wakeup, forbidden combination");
-
- rtcp->id_rtc->CR &= ~RTC_CR_WUTE;
- while(!(rtcp->id_rtc->ISR & RTC_ISR_WUTWF))
- ;
- rtcp->id_rtc->WUTR = wakeupspec->wakeup & 0xFFFF;
- rtcp->id_rtc->CR = (wakeupspec->wakeup >> 16) & 0x7;
- rtcp->id_rtc->CR |= RTC_CR_WUTIE;
- rtcp->id_rtc->CR |= RTC_CR_WUTE;
- }
- else {
- rtcp->id_rtc->CR &= ~RTC_CR_WUTIE;
- rtcp->id_rtc->CR &= ~RTC_CR_WUTE;
- }
-}
-#endif /* RTC_HAS_PERIODIC_WAKEUPS */
-
-/**
- * @brief Gets time of periodic wakeup.
- *
- * @note Default value after BKP domain reset is 0x0000FFFF
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[out] wakeupspec pointer to a @p RTCWakeup structure
- *
- * @api
- */
-#if RTC_HAS_PERIODIC_WAKEUPS
-void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec) {
-
- wakeupspec->wakeup = 0;
- wakeupspec->wakeup |= rtcp->id_rtc->WUTR;
- wakeupspec->wakeup |= (((uint32_t)rtcp->id_rtc->CR) & 0x7) << 16;
-}
-#endif /* RTC_HAS_PERIODIC_WAKEUPS */
-
-/**
- * @brief Get current time in format suitable for usage in FatFS.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @return FAT time value.
- *
- * @api
- */
-uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
- uint32_t fattime;
- RTCTime timespec;
- uint32_t tv_time;
- uint32_t tv_date;
- uint32_t v;
-
- chSysLock();
- rtcGetTimeI(rtcp, ×pec);
- chSysUnlock();
-
- tv_time = timespec.tv_time;
- tv_date = timespec.tv_date;
-
- v = (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET;
- v += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10;
- fattime = v >> 1;
-
- v = (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET;
- v += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10;
- fattime |= v << 5;
-
- v = (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET;
- v += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10;
- v += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET);
- fattime |= v << 11;
-
- v = (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET;
- v += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10;
- fattime |= v << 16;
-
- v = (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET;
- v += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10;
- fattime |= v << 21;
-
- v = (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET;
- v += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10;
- v += 2000 - 1900 - 80;
- fattime |= v << 25;
-
- return fattime;
-}
-
-#endif /* HAL_USE_RTC */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv2/rtc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv2/rtc_lld.h
deleted file mode 100644
index 84cd6efe94..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv2/rtc_lld.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file STM32/RTCv2/rtc_lld.h
- * @brief RTC low level driver header.
- *
- * @addtogroup RTC
- * @{
- */
-
-#ifndef _RTC_LLD_H_
-#define _RTC_LLD_H_
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Two alarm comparators available on STM32F4x and STM32F2x.
- */
-#if !defined(STM32F0XX)
-#define RTC_ALARMS 2
-#else
-#define RTC_ALARMS 1
-#endif
-
-/**
- * @brief STM32F0x has no periodic wakeups.
- */
-#if !defined(STM32F0XX)
-#define RTC_HAS_PERIODIC_WAKEUPS TRUE
-#else
-#define RTC_HAS_PERIODIC_WAKEUPS FALSE
-#endif
-
-/**
- * @brief Data offsets in RTC date and time registers.
- */
-#define RTC_TR_PM_OFFSET 22
-#define RTC_TR_HT_OFFSET 20
-#define RTC_TR_HU_OFFSET 16
-#define RTC_TR_MNT_OFFSET 12
-#define RTC_TR_MNU_OFFSET 8
-#define RTC_TR_ST_OFFSET 4
-#define RTC_TR_SU_OFFSET 0
-
-#define RTC_DR_YT_OFFSET 20
-#define RTC_DR_YU_OFFSET 16
-#define RTC_DR_WDU_OFFSET 13
-#define RTC_DR_MT_OFFSET 12
-#define RTC_DR_MU_OFFSET 8
-#define RTC_DR_DT_OFFSET 4
-#define RTC_DR_DU_OFFSET 0
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if HAL_USE_RTC && !STM32_HAS_RTC
-#error "RTC not present in the selected device"
-#endif
-
-#if !(STM32_RTCSEL == STM32_RTCSEL_LSE) && \
- !(STM32_RTCSEL == STM32_RTCSEL_LSI) && \
- !(STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
-#error "invalid source selected for RTC clock"
-#endif
-
-#if !defined(RTC_USE_INTERRUPTS) || defined(__DOXYGEN__)
-#define RTC_USE_INTERRUPTS FALSE
-#endif
-
-#if defined(STM32_PCLK1) /* For devices without STM32_PCLK1 (STM32F0xx) */
-#if STM32_PCLK1 < (STM32_RTCCLK * 7)
-#error "STM32_PCLK1 frequency is too low to handle RTC without ugly workaround"
-#endif
-#endif /* defined(STM32_PCLK1) */
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an RTC alarm time stamp.
- */
-typedef struct RTCAlarm RTCAlarm;
-
-/**
- * @brief Type of a structure representing an RTC wakeup period.
- */
-typedef struct RTCWakeup RTCWakeup;
-
-/**
- * @brief Type of a structure representing an RTC callbacks config.
- */
-typedef struct RTCCallbackConfig RTCCallbackConfig;
-
-/**
- * @brief Type of an RTC alarm.
- * @details Meaningful on platforms with more than 1 alarm comparator.
- */
-typedef uint32_t rtcalarm_t;
-
-/**
- * @brief Structure representing an RTC time stamp.
- */
-struct RTCTime {
- /**
- * @brief RTC date register in STM32 BCD format.
- */
- uint32_t tv_date;
- /**
- * @brief RTC time register in STM32 BCD format.
- */
- uint32_t tv_time;
- /**
- * @brief Set this to TRUE to use 12 hour notation.
- */
- bool_t h12;
- /**
- * @brief Fractional part of time.
- */
-#if STM32_RTC_HAS_SUBSECONDS
- uint32_t tv_msec;
-#endif
-};
-
-/**
- * @brief Structure representing an RTC alarm time stamp.
- */
-struct RTCAlarm {
- /**
- * @brief Date and time of alarm in STM32 BCD.
- */
- uint32_t tv_datetime;
-};
-
-#if RTC_HAS_PERIODIC_WAKEUPS
-/**
- * @brief Structure representing an RTC periodic wakeup period.
- */
-struct RTCWakeup {
- /**
- * @brief RTC WUTR register.
- * @details Bits [15:0] contain value of WUTR register
- * Bits [18:16] contain value of WUCKSEL bits in CR register
- *
- * @note ((WUTR == 0) || (WUCKSEL == 3)) is forbidden combination.
- */
- uint32_t wakeup;
-};
-#endif /* RTC_HAS_PERIODIC_WAKEUPS */
-
-/**
- * @brief Structure representing an RTC driver.
- */
-struct RTCDriver{
- /**
- * @brief Pointer to the RTC registers block.
- */
- RTC_TypeDef *id_rtc;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern RTCDriver RTCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void rtc_lld_init(void);
- void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec);
- void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec);
- void rtc_lld_set_alarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
- const RTCAlarm *alarmspec);
- void rtc_lld_get_alarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
- RTCAlarm *alarmspec);
-#if RTC_HAS_PERIODIC_WAKEUPS
- void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, const RTCWakeup *wakeupspec);
- void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec);
-#endif /* RTC_HAS_PERIODIC_WAKEUPS */
- uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_RTC */
-
-#endif /* _RTC_LLD_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/serial_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/serial_lld.c
deleted file mode 100644
index c19ac260e1..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/serial_lld.c
+++ /dev/null
@@ -1,534 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32/USARTv2/serial_lld.c
- * @brief STM32 low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief USART1 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/** @brief USART2 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/** @brief USART3 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/** @brief UART4 serial driver identifier.*/
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-SerialDriver SD4;
-#endif
-
-/** @brief UART5 serial driver identifier.*/
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-SerialDriver SD5;
-#endif
-
-/** @brief USART6 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-SerialDriver SD6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config =
-{
- SERIAL_DEFAULT_BITRATE,
- 0,
- USART_CR2_STOP1_BITS | USART_CR2_LINEN,
- 0
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief USART initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration
- */
-static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
- USART_TypeDef *u = sdp->usart;
-
- /* Baud rate setting.*/
- u->BRR = (uint16_t)(sdp->clock / config->speed);
-
- /* Note that some bits are enforced.*/
- u->CR2 = config->cr2 | USART_CR2_LBDIE;
- u->CR3 = config->cr3 | USART_CR3_EIE;
- u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
- USART_CR1_RXNEIE | USART_CR1_TE |
- USART_CR1_RE;
- u->ICR = 0xFFFFFFFF;
-}
-
-/**
- * @brief USART de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] u pointer to an USART I/O block
- */
-static void usart_deinit(USART_TypeDef *u) {
-
- u->CR1 = 0;
- u->CR2 = 0;
- u->CR3 = 0;
-}
-
-/**
- * @brief Error handling routine.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] isr USART ISR register value
- */
-static void set_error(SerialDriver *sdp, uint32_t isr) {
- flagsmask_t sts = 0;
-
- if (isr & USART_ISR_ORE)
- sts |= SD_OVERRUN_ERROR;
- if (isr & USART_ISR_PE)
- sts |= SD_PARITY_ERROR;
- if (isr & USART_ISR_FE)
- sts |= SD_FRAMING_ERROR;
- if (isr & USART_ISR_NE)
- sts |= SD_NOISE_ERROR;
- chSysLockFromIsr();
- chnAddFlagsI(sdp, sts);
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief Common IRQ handler.
- *
- * @param[in] sdp communication channel associated to the USART
- */
-static void serve_interrupt(SerialDriver *sdp) {
- USART_TypeDef *u = sdp->usart;
- uint32_t cr1 = u->CR1;
- uint32_t isr;
-
- /* Reading and clearing status.*/
- isr = u->ISR;
- u->ICR = isr;
-
- /* Error condition detection.*/
- if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE))
- set_error(sdp, isr);
-
- /* Special case, LIN break detection.*/
- if (isr & USART_ISR_LBD) {
- chSysLockFromIsr();
- chnAddFlagsI(sdp, SD_BREAK_DETECTED);
- chSysUnlockFromIsr();
- }
-
- /* Data available.*/
- if (isr & USART_ISR_RXNE) {
- chSysLockFromIsr();
- sdIncomingDataI(sdp, (uint8_t)u->RDR);
- chSysUnlockFromIsr();
- }
-
- /* Transmission buffer empty.*/
- if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
- msg_t b;
- chSysLockFromIsr();
- b = chOQGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
- }
- else
- u->TDR = b;
- chSysUnlockFromIsr();
- }
-
- /* Physical transmission end.*/
- if (isr & USART_ISR_TC) {
- chSysLockFromIsr();
- if (chOQIsEmptyI(&sdp->oqueue))
- chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
- u->CR1 = cr1 & ~USART_CR1_TCIE;
- chSysUnlockFromIsr();
- }
-}
-
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
- (void)qp;
- USART1->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
- (void)qp;
- USART2->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
- (void)qp;
- USART3->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-static void notify4(GenericQueue *qp) {
-
- (void)qp;
- UART4->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-static void notify5(GenericQueue *qp) {
-
- (void)qp;
- UART5->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-static void notify6(GenericQueue *qp) {
-
- (void)qp;
- USART6->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-#if !defined(STM32_USART1_HANDLER)
-#error "STM32_USART1_HANDLER not defined"
-#endif
-/**
- * @brief USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt(&SD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-#if !defined(STM32_USART2_HANDLER)
-#error "STM32_USART2_HANDLER not defined"
-#endif
-/**
- * @brief USART2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt(&SD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-#if !defined(STM32_USART3_HANDLER)
-#error "STM32_USART3_HANDLER not defined"
-#endif
-/**
- * @brief USART3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt(&SD3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-#if !defined(STM32_UART4_HANDLER)
-#error "STM32_UART4_HANDLER not defined"
-#endif
-/**
- * @brief UART4 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt(&SD4);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-#if !defined(STM32_UART5_HANDLER)
-#error "STM32_UART5_HANDLER not defined"
-#endif
-/**
- * @brief UART5 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt(&SD5);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-#if !defined(STM32_USART6_HANDLER)
-#error "STM32_USART6_HANDLER not defined"
-#endif
-/**
- * @brief USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt(&SD6);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if STM32_SERIAL_USE_USART1
- sdObjectInit(&SD1, NULL, notify1);
- SD1.usart = USART1;
- SD1.clock = STM32_USART1CLK;
-#endif
-
-#if STM32_SERIAL_USE_USART2
- sdObjectInit(&SD2, NULL, notify2);
- SD2.usart = USART2;
- SD2.clock = STM32_USART2CLK;
-#endif
-
-#if STM32_SERIAL_USE_USART3
- sdObjectInit(&SD3, NULL, notify3);
- SD3.usart = USART3;
- SD3.clock = STM32_USART3CLK;
-#endif
-
-#if STM32_SERIAL_USE_UART4
- sdObjectInit(&SD4, NULL, notify4);
- SD4.usart = UART4;
- SD4.clock = STM32_UART4CLK;
-#endif
-
-#if STM32_SERIAL_USE_UART5
- sdObjectInit(&SD5, NULL, notify5);
- SD5.usart = UART5;
- SD5.clock = STM32_UART5CLK;
-#endif
-
-#if STM32_SERIAL_USE_USART6
- sdObjectInit(&SD6, NULL, notify6);
- SD6.usart = USART6;
- SD6.clock = STM32_USART6CLK;
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- if (sdp->state == SD_STOP) {
-#if STM32_SERIAL_USE_USART1
- if (&SD1 == sdp) {
- rccEnableUSART1(FALSE);
- nvicEnableVector(STM32_USART1_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
- }
-#endif
-#if STM32_SERIAL_USE_USART2
- if (&SD2 == sdp) {
- rccEnableUSART2(FALSE);
- nvicEnableVector(STM32_USART2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
- }
-#endif
-#if STM32_SERIAL_USE_USART3
- if (&SD3 == sdp) {
- rccEnableUSART3(FALSE);
- nvicEnableVector(STM32_USART3_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
- }
-#endif
-#if STM32_SERIAL_USE_UART4
- if (&SD4 == sdp) {
- rccEnableUART4(FALSE);
- nvicEnableVector(STM32_UART4_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
- }
-#endif
-#if STM32_SERIAL_USE_UART5
- if (&SD5 == sdp) {
- rccEnableUART5(FALSE);
- nvicEnableVector(STM32_UART5_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
- }
-#endif
-#if STM32_SERIAL_USE_USART6
- if (&SD6 == sdp) {
- rccEnableUSART6(FALSE);
- nvicEnableVector(STM32_USART6_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY));
- }
-#endif
- }
- usart_init(sdp, config);
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
- usart_deinit(sdp->usart);
-#if STM32_SERIAL_USE_USART1
- if (&SD1 == sdp) {
- rccDisableUSART1(FALSE);
- nvicDisableVector(STM32_USART1_NUMBER);
- return;
- }
-#endif
-#if STM32_SERIAL_USE_USART2
- if (&SD2 == sdp) {
- rccDisableUSART2(FALSE);
- nvicDisableVector(STM32_USART2_NUMBER);
- return;
- }
-#endif
-#if STM32_SERIAL_USE_USART3
- if (&SD3 == sdp) {
- rccDisableUSART3(FALSE);
- nvicDisableVector(STM32_USART3_NUMBER);
- return;
- }
-#endif
-#if STM32_SERIAL_USE_UART4
- if (&SD4 == sdp) {
- rccDisableUART4(FALSE);
- nvicDisableVector(STM32_UART4_NUMBER);
- return;
- }
-#endif
-#if STM32_SERIAL_USE_UART5
- if (&SD5 == sdp) {
- rccDisableUART5(FALSE);
- nvicDisableVector(STM32_UART5_NUMBER);
- return;
- }
-#endif
-#if STM32_SERIAL_USE_USART6
- if (&SD6 == sdp) {
- rccDisableUSART6(FALSE);
- nvicDisableVector(STM32_USART6_NUMBER);
- return;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/uart_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/uart_lld.c
deleted file mode 100644
index 37305bbee0..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/uart_lld.c
+++ /dev/null
@@ -1,594 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32/USARTv2/uart_lld.c
- * @brief STM32 low level UART driver code.
- *
- * @addtogroup UART
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define USART1_RX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \
- STM32_USART1_RX_DMA_CHN)
-
-#define USART1_TX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \
- STM32_USART1_TX_DMA_CHN)
-
-#define USART2_RX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \
- STM32_USART2_RX_DMA_CHN)
-
-#define USART2_TX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \
- STM32_USART2_TX_DMA_CHN)
-
-#define USART3_RX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \
- STM32_USART3_RX_DMA_CHN)
-
-#define USART3_TX_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
- STM32_USART3_TX_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief USART1 UART driver identifier.*/
-#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
-UARTDriver UARTD1;
-#endif
-
-/** @brief USART2 UART driver identifier.*/
-#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
-UARTDriver UARTD2;
-#endif
-
-/** @brief USART3 UART driver identifier.*/
-#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
-UARTDriver UARTD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Status bits translation.
- *
- * @param[in] sr USART SR register value
- *
- * @return The error flags.
- */
-static uartflags_t translate_errors(uint32_t isr) {
- uartflags_t sts = 0;
-
- if (isr & USART_ISR_ORE)
- sts |= UART_OVERRUN_ERROR;
- if (isr & USART_ISR_PE)
- sts |= UART_PARITY_ERROR;
- if (isr & USART_ISR_FE)
- sts |= UART_FRAMING_ERROR;
- if (isr & USART_ISR_NE)
- sts |= UART_NOISE_ERROR;
- if (isr & USART_ISR_LBD)
- sts |= UART_BREAK_DETECTED;
- return sts;
-}
-
-/**
- * @brief Puts the receiver in the UART_RX_IDLE state.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- */
-static void set_rx_idle_loop(UARTDriver *uartp) {
- uint32_t mode;
-
- /* RX DMA channel preparation, if the char callback is defined then the
- TCIE interrupt is enabled too.*/
- if (uartp->config->rxchar_cb == NULL)
- mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
- else
- mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
- dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
- dmaStreamSetTransactionSize(uartp->dmarx, 1);
- dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
- dmaStreamEnable(uartp->dmarx);
-}
-
-/**
- * @brief USART de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- */
-static void usart_stop(UARTDriver *uartp) {
-
- /* Stops RX and TX DMA channels.*/
- dmaStreamDisable(uartp->dmarx);
- dmaStreamDisable(uartp->dmatx);
-
- /* Stops USART operations.*/
- uartp->usart->CR1 = 0;
- uartp->usart->CR2 = 0;
- uartp->usart->CR3 = 0;
-}
-
-/**
- * @brief USART initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- */
-static void usart_start(UARTDriver *uartp) {
- uint32_t cr1;
- USART_TypeDef *u = uartp->usart;
-
- /* Defensive programming, starting from a clean state.*/
- usart_stop(uartp);
-
- /* Baud rate setting.*/
-#if defined(STM32F0XX)
- if (uartp->usart == USART1)
- u->BRR = STM32_USART1CLK / uartp->config->speed;
- else
- u->BRR = STM32_PCLK / uartp->config->speed;
-#else /* !defined(STM32F0XX) */
- if (uartp->usart == USART1)
- u->BRR = STM32_PCLK2 / uartp->config->speed;
- else
- u->BRR = STM32_PCLK1 / uartp->config->speed;
-#endif /* !defined(STM32F0XX) */
-
- /* Resetting eventual pending status flags.*/
- u->ICR = 0xFFFFFFFF;
-
- /* Note that some bits are enforced because required for correct driver
- operations.*/
- u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
- u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
- USART_CR3_EIE;
- if (uartp->config->txend2_cb == NULL)
- cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
- else
- cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
- USART_CR1_TCIE;
- u->CR1 = uartp->config->cr1 | cr1;
-
- /* Starting the receiver idle loop.*/
- set_rx_idle_loop(uartp);
-}
-
-/**
- * @brief RX DMA common service routine.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] flags pre-shifted content of the ISR register
- */
-static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
-
- /* DMA errors handling.*/
-#if defined(STM32_UART_DMA_ERROR_HOOK)
- if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
- STM32_UART_DMA_ERROR_HOOK(uartp);
- }
-#else
- (void)flags;
-#endif
-
- if (uartp->rxstate == UART_RX_IDLE) {
- /* Receiver in idle state, a callback is generated, if enabled, for each
- received character and then the driver stays in the same state.*/
- if (uartp->config->rxchar_cb != NULL)
- uartp->config->rxchar_cb(uartp, uartp->rxbuf);
- }
- else {
- /* Receiver in active state, a callback is generated, if enabled, after
- a completed transfer.*/
- dmaStreamDisable(uartp->dmarx);
- uartp->rxstate = UART_RX_COMPLETE;
- if (uartp->config->rxend_cb != NULL)
- uartp->config->rxend_cb(uartp);
-
- /* If the callback didn't explicitly change state then the receiver
- automatically returns to the idle state.*/
- if (uartp->rxstate == UART_RX_COMPLETE) {
- uartp->rxstate = UART_RX_IDLE;
- set_rx_idle_loop(uartp);
- }
- }
-}
-
-/**
- * @brief TX DMA common service routine.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] flags pre-shifted content of the ISR register
- */
-static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
-
- /* DMA errors handling.*/
-#if defined(STM32_UART_DMA_ERROR_HOOK)
- if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
- STM32_UART_DMA_ERROR_HOOK(uartp);
- }
-#else
- (void)flags;
-#endif
-
- dmaStreamDisable(uartp->dmatx);
-
- /* A callback is generated, if enabled, after a completed transfer.*/
- uartp->txstate = UART_TX_COMPLETE;
- if (uartp->config->txend1_cb != NULL)
- uartp->config->txend1_cb(uartp);
-
- /* If the callback didn't explicitly change state then the transmitter
- automatically returns to the idle state.*/
- if (uartp->txstate == UART_TX_COMPLETE)
- uartp->txstate = UART_TX_IDLE;
-}
-
-/**
- * @brief USART common service routine.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- */
-static void serve_usart_irq(UARTDriver *uartp) {
- uint32_t isr;
- USART_TypeDef *u = uartp->usart;
-
- /* Reading and clearing status.*/
- isr = u->ISR;
- u->ICR = isr;
-
- if (isr & (USART_ISR_LBD | USART_ISR_ORE | USART_ISR_NE |
- USART_ISR_FE | USART_ISR_PE)) {
- if (uartp->config->rxerr_cb != NULL)
- uartp->config->rxerr_cb(uartp, translate_errors(isr));
- }
- if (isr & USART_ISR_TC) {
- /* End of transmission, a callback is generated.*/
- if (uartp->config->txend2_cb != NULL)
- uartp->config->txend2_cb(uartp);
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
-#if !defined(STM32_USART1_HANDLER)
-#error "STM32_USART1_HANDLER not defined"
-#endif
-/**
- * @brief USART1 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_usart_irq(&UARTD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART1 */
-
-#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
-#if !defined(STM32_USART2_HANDLER)
-#error "STM32_USART2_HANDLER not defined"
-#endif
-/**
- * @brief USART2 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_usart_irq(&UARTD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART2 */
-
-#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
-#if !defined(STM32_USART3_HANDLER)
-#error "STM32_USART3_HANDLER not defined"
-#endif
-/**
- * @brief USART3 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_usart_irq(&UARTD3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART3 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level UART driver initialization.
- *
- * @notapi
- */
-void uart_lld_init(void) {
-
-#if STM32_UART_USE_USART1
- uartObjectInit(&UARTD1);
- UARTD1.usart = USART1;
- UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
- UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
- UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_USART2
- uartObjectInit(&UARTD2);
- UARTD2.usart = USART2;
- UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
- UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
- UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_USART3
- uartObjectInit(&UARTD3);
- UARTD3.usart = USART3;
- UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
- UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
- UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
-#endif
-}
-
-/**
- * @brief Configures and activates the UART peripheral.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @notapi
- */
-void uart_lld_start(UARTDriver *uartp) {
-
- if (uartp->state == UART_STOP) {
-#if STM32_UART_USE_USART1
- if (&UARTD1 == uartp) {
- bool_t b;
- b = dmaStreamAllocate(uartp->dmarx,
- STM32_UART_USART1_IRQ_PRIORITY,
- (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
- (void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");
- b = dmaStreamAllocate(uartp->dmatx,
- STM32_UART_USART1_IRQ_PRIORITY,
- (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
- (void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
- rccEnableUSART1(FALSE);
- nvicEnableVector(STM32_USART1_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
- uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
- }
-#endif
-
-#if STM32_UART_USE_USART2
- if (&UARTD2 == uartp) {
- bool_t b;
- b = dmaStreamAllocate(uartp->dmarx,
- STM32_UART_USART2_IRQ_PRIORITY,
- (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
- (void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");
- b = dmaStreamAllocate(uartp->dmatx,
- STM32_UART_USART2_IRQ_PRIORITY,
- (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
- (void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
- rccEnableUSART2(FALSE);
- nvicEnableVector(STM32_USART2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
- uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
- }
-#endif
-
-#if STM32_UART_USE_USART3
- if (&UARTD3 == uartp) {
- bool_t b;
- b = dmaStreamAllocate(uartp->dmarx,
- STM32_UART_USART3_IRQ_PRIORITY,
- (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
- (void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
- b = dmaStreamAllocate(uartp->dmatx,
- STM32_UART_USART3_IRQ_PRIORITY,
- (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
- (void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
- rccEnableUSART3(FALSE);
- nvicEnableVector(STM32_USART3_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
- uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
- }
-#endif
-
- /* Static DMA setup, the transfer size depends on the USART settings,
- it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
- if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
- uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
- dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
- dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
- uartp->rxbuf = 0;
- }
-
- uartp->rxstate = UART_RX_IDLE;
- uartp->txstate = UART_TX_IDLE;
- usart_start(uartp);
-}
-
-/**
- * @brief Deactivates the UART peripheral.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @notapi
- */
-void uart_lld_stop(UARTDriver *uartp) {
-
- if (uartp->state == UART_READY) {
- usart_stop(uartp);
- dmaStreamRelease(uartp->dmarx);
- dmaStreamRelease(uartp->dmatx);
-
-#if STM32_UART_USE_USART1
- if (&UARTD1 == uartp) {
- nvicDisableVector(STM32_USART1_NUMBER);
- rccDisableUSART1(FALSE);
- return;
- }
-#endif
-
-#if STM32_UART_USE_USART2
- if (&UARTD2 == uartp) {
- nvicDisableVector(STM32_USART2_NUMBER);
- rccDisableUSART2(FALSE);
- return;
- }
-#endif
-
-#if STM32_UART_USE_USART3
- if (&UARTD3 == uartp) {
- nvicDisableVector(STM32_USART3_NUMBER);
- rccDisableUSART3(FALSE);
- return;
- }
-#endif
- }
-}
-
-/**
- * @brief Starts a transmission on the UART peripheral.
- * @note The buffers are organized as uint8_t arrays for data sizes below
- * or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] n number of data frames to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
-
- /* TX DMA channel preparation and start.*/
- dmaStreamSetMemory0(uartp->dmatx, txbuf);
- dmaStreamSetTransactionSize(uartp->dmatx, n);
- dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P |
- STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
- dmaStreamEnable(uartp->dmatx);
-}
-
-/**
- * @brief Stops any ongoing transmission.
- * @note Stopping a transmission also suppresses the transmission callbacks.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @return The number of data frames not transmitted by the
- * stopped transmit operation.
- *
- * @notapi
- */
-size_t uart_lld_stop_send(UARTDriver *uartp) {
-
- dmaStreamDisable(uartp->dmatx);
- return dmaStreamGetTransactionSize(uartp->dmatx);
-}
-
-/**
- * @brief Starts a receive operation on the UART peripheral.
- * @note The buffers are organized as uint8_t arrays for data sizes below
- * or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] n number of data frames to send
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
-
- /* Stopping previous activity (idle state).*/
- dmaStreamDisable(uartp->dmarx);
-
- /* RX DMA channel preparation and start.*/
- dmaStreamSetMemory0(uartp->dmarx, rxbuf);
- dmaStreamSetTransactionSize(uartp->dmarx, n);
- dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M |
- STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
- dmaStreamEnable(uartp->dmarx);
-}
-
-/**
- * @brief Stops any ongoing receive operation.
- * @note Stopping a receive operation also suppresses the receive callbacks.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @return The number of data frames not received by the
- * stopped receive operation.
- *
- * @notapi
- */
-size_t uart_lld_stop_receive(UARTDriver *uartp) {
- size_t n;
-
- dmaStreamDisable(uartp->dmarx);
- n = dmaStreamGetTransactionSize(uartp->dmarx);
- set_rx_idle_loop(uartp);
- return n;
-}
-
-#endif /* HAL_USE_UART */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/uart_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/uart_lld.h
deleted file mode 100644
index 8d8392f2a6..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/uart_lld.h
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32/USARTv2/uart_lld.h
- * @brief STM32 low level UART driver header.
- *
- * @addtogroup UART
- * @{
- */
-
-#ifndef _UART_LLD_H_
-#define _UART_LLD_H_
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief UART driver on USART1 enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART1 FALSE
-#endif
-
-/**
- * @brief UART driver on USART2 enable switch.
- * @details If set to @p TRUE the support for USART2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART2 FALSE
-#endif
-
-/**
- * @brief UART driver on USART3 enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART3 FALSE
-#endif
-
-/**
- * @brief USART1 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_IRQ_PRIORITY 12
-#endif
-
-/**
- * @brief USART2 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_IRQ_PRIORITY 12
-#endif
-
-/**
- * @brief USART3 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_IRQ_PRIORITY 12
-#endif
-
-/**
- * @brief USART1 DMA priority (0..3|lowest..highest).
- * @note The priority level is used for both the TX and RX DMA channels but
- * because of the channels ordering the RX channel has always priority
- * over the TX channel.
- */
-#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_DMA_PRIORITY 0
-#endif
-
-/**
- * @brief USART2 DMA priority (0..3|lowest..highest).
- * @note The priority level is used for both the TX and RX DMA channels but
- * because of the channels ordering the RX channel has always priority
- * over the TX channel.
- */
-#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_DMA_PRIORITY 0
-#endif
-
-/**
- * @brief USART3 DMA priority (0..3|lowest..highest).
- * @note The priority level is used for both the TX and RX DMA channels but
- * because of the channels ordering the RX channel has always priority
- * over the TX channel.
- */
-#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_DMA_PRIORITY 0
-#endif
-
-/**
- * @brief USART1 DMA error hook.
- * @note The default action for DMA errors is a system halt because DMA
- * error can only happen because programming errors.
- */
-#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief DMA stream used for USART1 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
-#endif
-
-/**
- * @brief DMA stream used for USART1 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
-#endif
-
-/**
- * @brief DMA stream used for USART2 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#endif
-
-/**
- * @brief DMA stream used for USART2 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
-#endif
-
-/**
- * @brief DMA stream used for USART3 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
-#endif
-
-/**
- * @brief DMA stream used for USART3 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#endif
-
-#else /* !STM32_ADVANCED_DMA*/
-
-#if defined(STM32F0XX)
-/* Fixed values for STM32F0xx devices.*/
-#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#endif /* defined(STM32F0XX) */
-
-#if defined(STM32F30X)|| defined(STM32F37X)
-/* Fixed values for STM32F3xx devices.*/
-#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#endif /* defined(STM32F30X) */
-
-#endif /* !STM32_ADVANCED_DMA*/
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
-#error "USART1 not present in the selected device"
-#endif
-
-#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
-#error "USART2 not present in the selected device"
-#endif
-
-#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
-#error "USART3 not present in the selected device"
-#endif
-
-#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
- !STM32_UART_USE_USART3
-#error "UART driver activated but no USART/UART peripheral assigned"
-#endif
-
-#if STM32_UART_USE_USART1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART1"
-#endif
-
-#if STM32_UART_USE_USART2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART2"
-#endif
-
-#if STM32_UART_USE_USART3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART3"
-#endif
-
-#if STM32_UART_USE_USART1 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART1"
-#endif
-
-#if STM32_UART_USE_USART2 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART2"
-#endif
-
-#if STM32_UART_USE_USART3 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART3"
-#endif
-
-#if STM32_UART_USE_USART1 && \
- !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
- STM32_USART1_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART1 RX"
-#endif
-
-#if STM32_UART_USE_USART1 && \
- !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \
- STM32_USART1_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART1 TX"
-#endif
-
-#if STM32_UART_USE_USART2 && \
- !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \
- STM32_USART2_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART2 RX"
-#endif
-
-#if STM32_UART_USE_USART2 && \
- !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \
- STM32_USART2_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART2 TX"
-#endif
-
-#if STM32_UART_USE_USART3 && \
- !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \
- STM32_USART3_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART3 RX"
-#endif
-
-#if STM32_UART_USE_USART3 && \
- !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \
- STM32_USART3_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART3 TX"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief UART driver condition flags type.
- */
-typedef uint32_t uartflags_t;
-
-/**
- * @brief Structure representing an UART driver.
- */
-typedef struct UARTDriver UARTDriver;
-
-/**
- * @brief Generic UART notification callback type.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- */
-typedef void (*uartcb_t)(UARTDriver *uartp);
-
-/**
- * @brief Character received UART notification callback type.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] c received character
- */
-typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
-
-/**
- * @brief Receive error UART notification callback type.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] e receive error mask
- */
-typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief End of transmission buffer callback.
- */
- uartcb_t txend1_cb;
- /**
- * @brief Physical end of transmission callback.
- */
- uartcb_t txend2_cb;
- /**
- * @brief Receive buffer filled callback.
- */
- uartcb_t rxend_cb;
- /**
- * @brief Character received while out if the @p UART_RECEIVE state.
- */
- uartccb_t rxchar_cb;
- /**
- * @brief Receive error callback.
- */
- uartecb_t rxerr_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief Bit rate.
- */
- uint32_t speed;
- /**
- * @brief Initialization value for the CR1 register.
- */
- uint32_t cr1;
- /**
- * @brief Initialization value for the CR2 register.
- */
- uint32_t cr2;
- /**
- * @brief Initialization value for the CR3 register.
- */
- uint32_t cr3;
-} UARTConfig;
-
-/**
- * @brief Structure representing an UART driver.
- */
-struct UARTDriver {
- /**
- * @brief Driver state.
- */
- uartstate_t state;
- /**
- * @brief Transmitter state.
- */
- uarttxstate_t txstate;
- /**
- * @brief Receiver state.
- */
- uartrxstate_t rxstate;
- /**
- * @brief Current configuration data.
- */
- const UARTConfig *config;
-#if defined(UART_DRIVER_EXT_FIELDS)
- UART_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the USART registers block.
- */
- USART_TypeDef *usart;
- /**
- * @brief DMA mode bit mask.
- */
- uint32_t dmamode;
- /**
- * @brief Receive DMA channel.
- */
- const stm32_dma_stream_t *dmarx;
- /**
- * @brief Transmit DMA channel.
- */
- const stm32_dma_stream_t *dmatx;
- /**
- * @brief Default receive buffer while into @p UART_RX_IDLE state.
- */
- volatile uint16_t rxbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD1;
-#endif
-
-#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD2;
-#endif
-
-#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void uart_lld_init(void);
- void uart_lld_start(UARTDriver *uartp);
- void uart_lld_stop(UARTDriver *uartp);
- void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
- size_t uart_lld_stop_send(UARTDriver *uartp);
- void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
- size_t uart_lld_stop_receive(UARTDriver *uartp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_UART */
-
-#endif /* _UART_LLD_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/i2s_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/i2s_lld.h
deleted file mode 100644
index ce73129fa4..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/i2s_lld.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32/i2s_lld.h
- * @brief I2S Driver subsystem low level driver header template.
- *
- * @addtogroup I2S
- * @{
- */
-
-#ifndef _I2S_LLD_H_
-#define _I2S_LLD_H_
-
-#if HAL_USE_I2S || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief I2S2 driver enable switch.
- * @details If set to @p TRUE the support for I2S2 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_I2S_USE_I2S2) || defined(__DOXYGEN__)
-#define STM32_I2S_USE_I2S2 FALSE
-#endif
-
-/**
- * @brief I2S3 driver enable switch.
- * @details If set to @p TRUE the support for I2S3 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_I2S_USE_I2S3) || defined(__DOXYGEN__)
-#define STM32_I2S_USE_I2S3 FALSE
-#endif
-
-/**
- * @brief I2S2 interrupt priority level setting.
- */
-#if !defined(STM32_I2S_I2S2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2S_I2S2_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief I2S3 interrupt priority level setting.
- */
-#if !defined(STM32_I2S_I2S3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2S_I2S3_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief I2S2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_I2S_I2S2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2S_I2S2_DMA_PRIORITY 1
-#endif
-
-/**
- * @brief I2S3 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_I2S_I2S2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2S_I2S2_DMA_PRIORITY 1
-#endif
-
-/**
- * @brief I2S DMA error hook.
- */
-#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_I2S_DMA_ERROR_HOOK(i2sp) chSysHalt()
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief DMA stream used for I2S2 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2S_I2S2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2S_I2S2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
-#endif
-
-/**
- * @brief DMA stream used for I2S2 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2S_I2S2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2S_I2S2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#endif
-
-/**
- * @brief DMA stream used for I2S3 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2S_I2S3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2S_I2S3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
-#endif
-
-/**
- * @brief DMA stream used for I2S3 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2S_I2S3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2S_I2S3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#endif
-
-#else /* !STM32_ADVANCED_DMA */
-
-/* Fixed streams for platforms using the old DMA peripheral, the values are
- valid for both STM32F1xx and STM32L1xx.*/
-#define STM32_I2S_I2S2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#define STM32_I2S_I2S2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2S_I2S3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#define STM32_I2S_I2S3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
-
-#endif /* !STM32_ADVANCED_DMA */
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if STM32_I2S_USE_I2S2 && !STM32_HAS_SPI2
-#error "SPI2 not present in the selected device"
-#endif
-
-#if STM32_I2S_USE_I2S3 && !STM32_HAS_SPI3
-#error "SPI3 not present in the selected device"
-#endif
-
-#if !STM32_I2S_USE_I2S2 && !STM32_I2S_USE_I2S3
-#error "I2S driver activated but no I2S peripheral assigned"
-#endif
-
-#if STM32_I2S_USE_I2S2 && \
- !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
-#error "invalid DMA stream associated to I2S2 RX"
-#endif
-
-#if STM32_I2S_USE_I2S2 && \
- !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
-#error "invalid DMA stream associated to I2S2 TX"
-#endif
-
-#if STM32_I2S_USE_I2S3 && \
- !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
-#error "invalid DMA stream associated to I2S3 RX"
-#endif
-
-#if STM32_I2S_USE_I2S3 && \
- !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
-#error "invalid DMA stream associated to I2S3 TX"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief I2S mode type.
- */
-typedef uint32_t i2smode_t;
-
-/**
- * @brief Type of a structure representing an I2S driver.
- */
-typedef struct I2SDriver I2SDriver;
-
-/**
- * @brief I2S notification callback type.
- *
- * @param[in] i2sp pointer to the @p I2SDriver object
- * @param[in] buffer pointer to the buffer
- * @param[in] n number of sample positions starting from @p buffer
- */
-typedef void (*i2scallback_t)(I2SDriver *i2sp, void *buffer, size_t n);
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief I2S mode selection.
- */
- i2smode_t mode;
- /**
- * @brief Transmission buffer pointer.
- */
- const void *tx_buffer;
- /**
- * @brief Transmission buffer size in number of samples.
- */
- size_t tx_size;
- /**
- * @brief Callback function associated to the transmission or @p NULL.
- */
- i2scallback_t tx_cb;
- /**
- * @brief Receive buffer pointer.
- */
- void *rx_buffer;
- /**
- * @brief Receive buffer size in number of samples.
- */
- size_t rx_size;
- /**
- * @brief Callback function associated to the reception or @p NULL.
- */
- i2scallback_t rx_cb;;
- /* End of the mandatory fields.*/
- /**
- * @brief Configuration of the I2SCFGR register.
- * @details See the STM32 reference manual, this register is used for
- * the I2S configuration, the following bits must not be
- * specified because handled directly by the driver:
- * - I2SMOD
- * - I2SE
- * - I2SCFG
- * .
- */
- int16_t i2scfgr;
- /**
- * @brief Configuration of the I2SPR register.
- * @details See the STM32 reference manual, this register is used for
- * the I2S clock setup.
- */
- int16_t i2spr;
-} I2SConfig;
-
-/**
- * @brief Structure representing an I2S driver.
- */
-struct I2SDriver {
- /**
- * @brief Driver state.
- */
- i2sstate_t state;
- /**
- * @brief Current configuration data.
- */
- const I2SConfig *config;
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the SPIx registers block.
- */
- SPI_TypeDef *spi;
- /**
- * @brief DMA stream.
- */
- const stm32_dma_stream_t *dma;
- /**
- * @brief DMA mode bit mask.
- */
- uint32_t dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_I2S_USE_I2S2 && !defined(__DOXYGEN__)
-extern I2SDriver I2SD2;
-#endif
-
-#if STM32_I2S_USE_I2S3 && !defined(__DOXYGEN__)
-extern I2SDriver I2SD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void i2s_lld_init(void);
- void i2s_lld_start(I2SDriver *i2sp);
- void i2s_lld_stop(I2SDriver *i2sp);
- void i2s_lld_start_exchange(I2SDriver *i2sp);
- void i2s_lld_start_exchange_continuous(I2SDriver *i2sp);
- void i2s_lld_stop_exchange(I2SDriver *i2sp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2S */
-
-#endif /* _I2S_LLD_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/stm32.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/stm32.h
deleted file mode 100644
index c3b7d27e9c..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/stm32.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32/stm32.h
- * @brief STM32 common header.
- * @pre One of the following macros must be defined before including
- * this header, the macro selects the inclusion of the appropriate
- * vendor header:
- * - STM32F0XX for Entry Level devices.
- * - STM32F10X_LD_VL for Value Line Low Density devices.
- * - STM32F10X_MD_VL for Value Line Medium Density devices.
- * - STM32F10X_LD for Performance Low Density devices.
- * - STM32F10X_MD for Performance Medium Density devices.
- * - STM32F10X_HD for Performance High Density devices.
- * - STM32F10X_XL for Performance eXtra Density devices.
- * - STM32F10X_CL for Connectivity Line devices.
- * - STM32F2XX for High-performance STM32 F-2 devices.
- * - STM32F30X for Analog & DSP devices.
- * - STM32F37X for Analog & DSP devices.
- * - STM32F4XX for High-performance STM32 F-4 devices.
- * - STM32L1XX_MD for Ultra Low Power Medium-density devices.
- * - STM32L1XX_MDP for Ultra Low Power Medium-density Plus devices.
- * - STM32L1XX_HD for Ultra Low Power High-density devices.
- * .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _STM32_H_
-#define _STM32_H_
-
-#if defined(STM32F030) || defined(STM32F0XX_LD) || \
- defined(STM32F0XX_MD)
-#include "stm32f0xx.h"
-
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \
- defined(STM32F10X_MD) || defined(STM32F10X_HD) || \
- defined(STM32F10X_XL) || defined(STM32F10X_CL) || \
- defined(__DOXYGEN__)
-#include "stm32f10x.h"
-
-#elif defined(STM32F2XX)
-#include "stm32f2xx.h"
-
-#elif defined(STM32F30X)
-#include "stm32f30x.h"
-
-#elif defined(STM32F37X)
-#include "stm32f37x.h"
-
-#elif defined(STM32F401xx) || defined(STM32F40_41xxx) || \
- defined(STM32F427_437xx) || defined(STM32F429_439xx) || \
- defined(STM32F446xx)
-#include "stm32f4xx.h"
-
-#elif defined(STM32L1XX_MD) || defined(STM32L1XX_MDP) || \
- defined(STM32L1XX_HD)
-#include "stm32l1xx.h"
-
-#else
-#error "STM32 device not specified"
-#endif
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#endif /* _STM32_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f103.h
deleted file mode 100644
index 55c8e96818..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f103.h
+++ /dev/null
@@ -1,1308 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @defgroup STM32F103_HAL STM32F103 HAL Support
- * @details HAL support for STM32 Performance Line LD, MD and HD sub-families.
- *
- * @ingroup HAL
- */
-
-/**
- * @file STM32F1xx/hal_lld_f103.h
- * @brief STM32F103 Performance Line HAL subsystem low level driver header.
- *
- * @addtogroup STM32F103_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_F103_H_
-#define _HAL_LLD_F103_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Platform identification
- * @{
- */
-#if defined(__DOXYGEN__)
-#define PLATFORM_NAME "STM32F10x Performance Line"
-
-#elif defined(STM32F10X_LD)
-#define PLATFORM_NAME "STM32F10x Performance Line Low Density"
-
-#elif defined(STM32F10X_MD)
-#define PLATFORM_NAME "STM32F10x Performance Line Medium Density"
-
-#elif defined(STM32F10X_HD)
-#define PLATFORM_NAME "STM32F10x Performance Line High Density"
-
-#elif defined(STM32F10X_XL)
-#define PLATFORM_NAME "STM32F10x Performance Line eXtra Density"
-
-#else
-#error "unsupported STM32 Performance Line member"
-#endif
-/** @} */
-
-/**
- * @name Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief Maximum system clock frequency.
- */
-#define STM32_SYSCLK_MAX 72000000
-
-/**
- * @brief Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX 25000000
-
-/**
- * @brief Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN 1000000
-
-/**
- * @brief Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX 1000000
-
-/**
- * @brief Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN 32768
-
-/**
- * @brief Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX 25000000
-
-/**
- * @brief Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN 1000000
-
-/**
- * @brief Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX 72000000
-
-/**
- * @brief Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN 16000000
-
-/**
- * @brief Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX 36000000
-
-/**
- * @brief Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX 72000000
-
-/**
- * @brief Maximum ADC clock frequency.
- */
-#define STM32_ADCCLK_MAX 14000000
-/** @} */
-
-/**
- * @name RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
-#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
-#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
-
-#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
-#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
-#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
-#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
-#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
-#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
-#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
-#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
-#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
-
-#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
-#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
-#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
-#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
-#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
-
-#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
-#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
-#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
-#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
-#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
-
-#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
-#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
-#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
-#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
-
-#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
-#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
-
-#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
-#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
-
-#define STM32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */
-#define STM32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */
-
-#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
-#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
-#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
-#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
-#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
-/** @} */
-
-/**
- * @name RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
-#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
-#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
-#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
-#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
- RTC clock. */
-/** @} */
-
-/*===========================================================================*/
-/* Platform capabilities. */
-/*===========================================================================*/
-
-#if defined(STM32F10X_LD) || defined(__DOXYGEN__)
-/**
- * @name STM32F103 LD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_HAS_ADC2 TRUE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_CAN_MAX_FILTERS 14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE FALSE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOH FALSE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 FALSE
-#define STM32_I2C2_RX_DMA_MSK 0
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK 0
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_SPI3_RX_DMA_MSK 0
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK 0
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 FALSE
-#define STM32_SPI2_RX_DMA_MSK 0
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK 0
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 FALSE
-#define STM32_SPI3_RX_DMA_MSK 0
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK 0
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 FALSE
-#define STM32_HAS_TIM5 FALSE
-#define STM32_HAS_TIM6 FALSE
-#define STM32_HAS_TIM7 FALSE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM9 FALSE
-#define STM32_HAS_TIM10 FALSE
-#define STM32_HAS_TIM11 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 FALSE
-#define STM32_USART3_RX_DMA_MSK 0
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK 0
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 FALSE
-#define STM32_UART4_RX_DMA_MSK 0
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK 0
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 FALSE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-#endif /* defined(STM32F10X_LD) */
-
-#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
-/**
- * @name STM32F103 MD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_HAS_ADC2 TRUE
-#define STM32_HAS_ADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_CAN_MAX_FILTERS 14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOH FALSE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_I2C3_RX_DMA_MSK 0
-#define STM32_I2C3_RX_DMA_CHN 0x00000000
-#define STM32_I2C3_TX_DMA_MSK 0
-#define STM32_I2C3_TX_DMA_CHN 0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 FALSE
-#define STM32_SPI3_RX_DMA_MSK 0
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK 0
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 TRUE
-#define STM32_HAS_TIM5 FALSE
-#define STM32_HAS_TIM6 FALSE
-#define STM32_HAS_TIM7 FALSE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM9 FALSE
-#define STM32_HAS_TIM10 FALSE
-#define STM32_HAS_TIM11 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 FALSE
-#define STM32_UART4_RX_DMA_MSK 0
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK 0
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 FALSE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB TRUE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-#endif /* defined(STM32F10X_MD) */
-
-#if defined(STM32F10X_HD) || defined(__DOXYGEN__)
-/**
- * @name STM32F103 HD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_HAS_ADC2 TRUE
-#define STM32_HAS_ADC3 TRUE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_CAN_MAX_FILTERS 14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOH FALSE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_I2C3_RX_DMA_MSK 0
-#define STM32_I2C3_RX_DMA_CHN 0x00000000
-#define STM32_I2C3_TX_DMA_MSK 0
-#define STM32_I2C3_TX_DMA_CHN 0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 TRUE
-#define STM32_HAS_TIM5 TRUE
-#define STM32_HAS_TIM6 TRUE
-#define STM32_HAS_TIM7 TRUE
-#define STM32_HAS_TIM8 TRUE
-#define STM32_HAS_TIM9 TRUE
-#define STM32_HAS_TIM10 TRUE
-#define STM32_HAS_TIM11 TRUE
-#define STM32_HAS_TIM12 TRUE
-#define STM32_HAS_TIM13 TRUE
-#define STM32_HAS_TIM14 TRUE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB TRUE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-#endif /* defined(STM32F10X_HD) */
-
-#if defined(STM32F10X_XL) || defined(__DOXYGEN__)
-/**
- * @name STM32F103 XL capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_HAS_ADC2 TRUE
-#define STM32_HAS_ADC3 TRUE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_CAN_MAX_FILTERS 14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOH FALSE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_I2C3_RX_DMA_MSK 0
-#define STM32_I2C3_RX_DMA_CHN 0x00000000
-#define STM32_I2C3_TX_DMA_MSK 0
-#define STM32_I2C3_TX_DMA_CHN 0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 FALSE
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 TRUE
-#define STM32_HAS_TIM5 TRUE
-#define STM32_HAS_TIM6 TRUE
-#define STM32_HAS_TIM7 TRUE
-#define STM32_HAS_TIM8 TRUE
-#define STM32_HAS_TIM9 FALSE
-#define STM32_HAS_TIM10 FALSE
-#define STM32_HAS_TIM11 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB TRUE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-#endif /* defined(STM32F10X_XL) */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names. */
-/*===========================================================================*/
-
-/**
- * @name IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
-#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
- detect. */
-#define TAMPER_IRQHandler Vector48 /**< Tamper. */
-#define RTC_IRQHandler Vector4C /**< RTC. */
-#define FLASH_IRQHandler Vector50 /**< Flash. */
-#define RCC_IRQHandler Vector54 /**< RCC. */
-#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
-#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
-#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
-#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
-#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
-#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */
-#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */
-#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */
-#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */
-#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */
-#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
-#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
-#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */
-#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */
-#define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/
-#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */
-#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/
-#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */
-#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */
-#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
-#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */
-#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */
-#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and
- Commutation. */
-#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */
-#define TIM2_IRQHandler VectorB0 /**< TIM2. */
-#define TIM3_IRQHandler VectorB4 /**< TIM3. */
-#define TIM4_IRQHandler VectorB8 /**< TIM4. */
-#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
-#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
-#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
-#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */
-#define SPI1_IRQHandler VectorCC /**< SPI1. */
-#define SPI2_IRQHandler VectorD0 /**< SPI2. */
-#define USART1_IRQHandler VectorD4 /**< USART1. */
-#define USART2_IRQHandler VectorD8 /**< USART2. */
-#define USART3_IRQHandler VectorDC /**< USART3. */
-#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
-#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */
-#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */
-#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */
-#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */
-#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and
- Commutation. */
-#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */
-#define ADC3_IRQHandler VectorFC /**< ADC3. */
-#define FSMC_IRQHandler Vector100 /**< FSMC. */
-#define SDIO_IRQHandler Vector104 /**< SDIO. */
-#define TIM5_IRQHandler Vector108 /**< TIM5. */
-#define SPI3_IRQHandler Vector10C /**< SPI3. */
-#define UART4_IRQHandler Vector110 /**< UART4. */
-#define UART5_IRQHandler Vector114 /**< UART5. */
-#define TIM6_IRQHandler Vector118 /**< TIM6. */
-#define TIM7_IRQHandler Vector11C /**< TIM7. */
-#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */
-#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */
-#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */
-#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief Main clock source selection.
- * @note If the selected clock source is not the PLL then the PLL is not
- * initialized and started.
- * @note The default value is calculated for a 72MHz system clock from
- * a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW STM32_SW_PLL
-#endif
-
-/**
- * @brief Clock source for the PLL.
- * @note This setting has only effect if the PLL is selected as the
- * system clock source.
- * @note The default value is calculated for a 72MHz system clock from
- * a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief Crystal PLL pre-divider.
- * @note This setting has only effect if the PLL is selected as the
- * system clock source.
- * @note The default value is calculated for a 72MHz system clock from
- * a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
-#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
-#endif
-
-/**
- * @brief PLL multiplier value.
- * @note The allowed range is 2...16.
- * @note The default value is calculated for a 72MHz system clock from
- * a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE 9
-#endif
-
-/**
- * @brief AHB prescaler value.
- * @note The default value is calculated for a 72MHz system clock from
- * a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1 STM32_PPRE1_DIV2
-#endif
-
-/**
- * @brief APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2 STM32_PPRE2_DIV2
-#endif
-
-/**
- * @brief ADC prescaler value.
- */
-#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADCPRE STM32_ADCPRE_DIV4
-#endif
-
-/**
- * @brief USB clock setting.
- */
-#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_USB_CLOCK_REQUIRED TRUE
-#endif
-
-/**
- * @brief USB prescaler initialization.
- */
-#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
-#define STM32_USBPRE STM32_USBPRE_DIV1P5
-#endif
-
-/**
- * @brief MCO pin setting.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL STM32_RTCSEL_LSI
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F103_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F103_MCUCONF not defined"
-#endif
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
- ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCOSEL"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
- ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if (STM32_LSECLK == 0)
-#error "LSE frequency not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL activation conditions.*/
-#if STM32_USB_CLOCK_REQUIRED || \
- (STM32_SW == STM32_SW_PLL) || \
- (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
- defined(__DOXYGEN__)
-/**
- * @brief PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL TRUE
-#else
-#define STM32_ACTIVATE_PLL FALSE
-#endif
-
-/* HSE prescaler setting check.*/
-#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
- (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
-#error "invalid STM32_PLLXTPRE value specified"
-#endif
-
-/**
- * @brief PLLMUL field.
- */
-#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
-#define STM32_PLLCLKIN (STM32_HSECLK / 1)
-#else
-#define STM32_PLLCLKIN (STM32_HSECLK / 2)
-#endif
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN (STM32_HSICLK / 2)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/**
- * @brief PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief System clock source.
- */
-#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
-#define STM32_SYSCLK STM32_PLLCLKOUT
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK STM32_HSECLK
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1 (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1 (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1 (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1 (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2 (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2 (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2 (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2 (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/**
- * @brief RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
-#define STM32_RTCCLK STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK (STM32_HSECLK / 128)
-#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-#define STM32_RTCCLK 0
-#else
-#error "invalid source selected for RTC clock"
-#endif
-
-/**
- * @brief ADC frequency.
- */
-#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_ADCCLK (STM32_PCLK2 / 2)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
-#define STM32_ADCCLK (STM32_PCLK2 / 4)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
-#define STM32_ADCCLK (STM32_PCLK2 / 6)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
-#define STM32_ADCCLK (STM32_PCLK2 / 8)
-#else
-#error "invalid STM32_ADCPRE value specified"
-#endif
-
-/* ADC frequency check.*/
-#if STM32_ADCCLK > STM32_ADCCLK_MAX
-#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/**
- * @brief USB frequency.
- */
-#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
-#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3)
-#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
-#define STM32_USBCLK STM32_PLLCLKOUT
-#else
-#error "invalid STM32_USBPRE value specified"
-#endif
-
-/**
- * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief Timers 1, 8, 9, 10, 11 clock.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief Flash settings.
- */
-#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS 0x00000010
-#elif STM32_HCLK <= 48000000
-#define STM32_FLASHBITS 0x00000011
-#else
-#define STM32_FLASHBITS 0x00000012
-#endif
-
-#endif /* _HAL_LLD_F103_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform.dox
deleted file mode 100644
index f5fb63d8a9..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform.dox
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers
- * @details This section describes all the supported drivers on the STM32F1xx
- * platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup STM32F1xx_HAL STM32F1xx Initialization Support
- * @details The STM32F1xx HAL support is responsible for system initialization.
- *
- * @section stm32f1xx_hal_1 Supported HW resources
- * - PLL1.
- * - PLL2 (where present).
- * - RCC.
- * - Flash.
- * .
- * @section stm32f1xx_hal_2 STM32F1xx HAL driver implementation features
- * - PLLs startup and stabilization.
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash wait states initialization based on the selected clock options.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * - DMA support initialization.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_ADC STM32F1xx ADC Support
- * @details The STM32F1xx ADC driver supports the ADC peripherals using DMA
- * channels for maximum performance.
- *
- * @section stm32f1xx_adc_1 Supported HW resources
- * - ADC1.
- * - DMA1.
- * .
- * @section stm32f1xx_adc_2 STM32F1xx ADC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Streaming conversion using DMA for maximum performance.
- * - Programmable ADC interrupt priority level.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - DMA errors detection.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_CAN STM32F1xx CAN Support
- * @details The STM32F1xx CAN driver uses the CAN peripherals.
- *
- * @section stm32f1xx_can_1 Supported HW resources
- * - bxCAN1.
- * .
- * @section stm32f1xx_can_2 STM32F1xx CAN driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Support for bxCAN sleep mode.
- * - Programmable bxCAN interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_EXT STM32F1xx EXT Support
- * @details The STM32F1xx EXT driver uses the EXTI peripheral.
- *
- * @section stm32f1xx_ext_1 Supported HW resources
- * - EXTI.
- * .
- * @section stm32f1xx_ext_2 STM32F1xx EXT driver implementation features
- * - Each EXTI channel can be independently enabled and programmed.
- * - Programmable EXTI interrupts priority level.
- * - Capability to work as event sources (WFE) rather than interrupt sources.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_GPT STM32F1xx GPT Support
- * @details The STM32F1xx GPT driver uses the TIMx peripherals.
- *
- * @section stm32f1xx_gpt_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32f1xx_gpt_2 STM32F1xx GPT driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_I2C STM32F1xx I2C Support
- * @details The STM32F1xx I2C driver uses the I2Cx peripherals.
- *
- * @section stm32f1xx_i2c_1 Supported HW resources
- * - I2C1.
- * - I2C2.
- * .
- * @section stm32f1xx_i2c_2 STM32F1xx I2C driver implementation features
- * - Each I2C port can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable I2Cx interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_ICU STM32F1xx ICU Support
- * @details The STM32F1xx ICU driver uses the TIMx peripherals.
- *
- * @section stm32f1xx_icu_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32f1xx_icu_2 STM32F1xx ICU driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_MAC STM32F1xx MAC Support
- * @details The STM32 MAC driver supports the ETH peripheral.
- *
- * @section at91sam7_mac_1 Supported HW resources
- * - ETH.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_PAL STM32F1xx PAL Support
- * @details The STM32F1xx PAL driver uses the GPIO peripherals.
- *
- * @section stm32f1xx_pal_1 Supported HW resources
- * - AFIO.
- * - GPIOA.
- * - GPIOB.
- * - GPIOC.
- * - GPIOD.
- * - GPIOE (where present).
- * - GPIOF (where present).
- * - GPIOG (where present).
- * .
- * @section stm32f1xx_pal_2 STM32F1xx PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 16 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section stm32f1xx_pal_3 Supported PAL setup modes
- * The STM32F1xx PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_INPUT_PULLDOWN.
- * - @p PAL_MODE_INPUT_ANALOG.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard).
- * - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard).
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section stm32f1xx_pal_4 Suboptimal behavior
- * The STM32F1xx GPIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * - Writing on pads/groups/ports programmed as input with pull-up/down
- * resistor can change the resistor setting because the output latch is
- * used for resistor selection.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_PWM STM32F1xx PWM Support
- * @details The STM32F1xx PWM driver uses the TIMx peripherals.
- *
- * @section stm32f1xx_pwm_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32f1xx_pwm_2 STM32F1xx PWM driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Four independent PWM channels per timer.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_RTC STM32F1xx RTC Support
- * @details The STM32F1xx RTC driver uses the RTC peripheral.
- *
- * @section stm32f1xx_rtc_1 Supported HW resources
- * - RTC.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_SDC STM32F1xx SDC Support
- * @details The STM32F1xx SDC driver uses the SDIO peripheral.
- *
- * @section stm32f1xx_sdc_1 Supported HW resources
- * - SDIO.
- * - DMA2.
- * .
- * @section stm32f1xx_sdc_2 STM32F1xx SDC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support
- * @details The STM32F1xx Serial driver uses the USART/UART peripherals in a
- * buffered, interrupt driven, implementation.
- *
- * @section stm32f1xx_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3 (where present).
- * - UART4 (where present).
- * - UART5 (where present).
- * .
- * @section stm32f1xx_serial_2 STM32F1xx Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each UART/USART.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_SPI STM32F1xx SPI Support
- * @details The SPI driver supports the STM32F1xx SPI peripherals using DMA
- * channels for maximum performance.
- *
- * @section stm32f1xx_spi_1 Supported HW resources
- * - SPI1.
- * - SPI2.
- * - SPI3 (where present).
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32f1xx_spi_2 STM32F1xx SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SPI can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each SPI.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_UART STM32F1xx UART Support
- * @details The UART driver supports the STM32F1xx USART peripherals using DMA
- * channels for maximum performance.
- *
- * @section stm32f1xx_uart_1 Supported HW resources
- * The UART driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3 (where present).
- * - UART4 (where present).
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32f1xx_uart_2 STM32F1xx UART driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each UART/USART.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_USB STM32F1xx USB Support
- * @details The USB driver supports the STM32F1xx USB peripheral.
- *
- * @section stm32f1xx_usb_1 Supported HW resources
- * The USB driver can support any of the following hardware resources:
- * - USB.
- * .
- * @section stm32f1xx_usb_2 STM32F1xx USB driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority levels.
- * - Each endpoint programmable in Control, Bulk and Interrupt modes.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_PLATFORM_DRIVERS STM32F1xx Platform Drivers
- * @details Platform support drivers. Platform drivers do not implement HAL
- * standard driver templates, their role is to support platform
- * specific functionalities.
- *
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_DMA STM32F1xx DMA Support
- * @details This DMA helper driver is used by the other drivers in order to
- * access the shared DMA resources in a consistent way.
- *
- * @section stm32f1xx_dma_1 Supported HW resources
- * The DMA driver can support any of the following hardware resources:
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features
- * - Exports helper functions/macros to the other drivers that share the
- * DMA resource.
- * - Automatic DMA clock stop when not in use by any driver.
- * - DMA streams and interrupt vectors sharing among multiple drivers.
- * .
- * @ingroup STM32F1xx_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_ISR STM32F1xx ISR Support
- * @details This ISR helper driver is used by the other drivers in order to
- * map ISR names to physical vector names.
- *
- * @ingroup STM32F1xx_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_RCC STM32F1xx RCC Support
- * @details This RCC helper driver is used by the other drivers in order to
- * access the shared RCC resources in a consistent way.
- *
- * @section stm32f1xx_rcc_1 Supported HW resources
- * - RCC.
- * .
- * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features
- * - Peripherals reset.
- * - Peripherals clock enable.
- * - Peripherals clock disable.
- * .
- * @ingroup STM32F1xx_PLATFORM_DRIVERS
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform.mk
deleted file mode 100644
index 9111e49545..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-# List of all the STM32F1xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
- ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \
- ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
- ${CHIBIOS}/os/hal/platforms/STM32 \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/USBv1
-
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform_f105_f107.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform_f105_f107.mk
deleted file mode 100644
index 43017f9791..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/platform_f105_f107.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-# List of all the STM32F1xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
- ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \
- ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
- ${CHIBIOS}/os/hal/platforms/STM32 \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/OTGv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_dma.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_dma.c
deleted file mode 100644
index 9a50379021..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_dma.c
+++ /dev/null
@@ -1,503 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F1xx/stm32_dma.c
- * @brief DMA helper driver code.
- *
- * @addtogroup STM32F1xx_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- * shared resource, this driver allows to allocate and free DMA
- * streams at runtime in order to allow all the other device
- * drivers to coordinate the access to the resource.
- * @note The DMA ISR handlers are all declared into this module because
- * sharing, the various device drivers can associate a callback to
- * ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
- has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/**
- * @brief Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK 0x0000007F
-
-/**
- * @brief Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK 0x00000F80
-
-/**
- * @brief Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE 0x00000000
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- * identifier and the involved physical registers.
- * @note Don't use this array directly, use the appropriate wrapper macros
- * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
- {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
- {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
- {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
- {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
- {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
- {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
- {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
- {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
- {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
- {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
-#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
- {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
- {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
-#else /* !STM32F10X_CL */
- {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn},
- {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn},
-#endif /* !STM32F10X_CL */
-#endif /* STM32_HAS_DMA2 */
-};
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief DMA ISR redirector type.
- */
-typedef struct {
- stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
- void *dma_param; /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 0;
- if (dma_isr_redir[0].dma_func)
- dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 4;
- if (dma_isr_redir[1].dma_func)
- dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 8;
- if (dma_isr_redir[2].dma_func)
- dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 12;
- if (dma_isr_redir[3].dma_func)
- dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 16;
- if (dma_isr_redir[4].dma_func)
- dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 20;
- if (dma_isr_redir[5].dma_func)
- dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 24;
- if (dma_isr_redir[6].dma_func)
- dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 0;
- if (dma_isr_redir[7].dma_func)
- dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 4;
- if (dma_isr_redir[8].dma_func)
- dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 8;
- if (dma_isr_redir[9].dma_func)
- dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 12;
- if (dma_isr_redir[10].dma_func)
- dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 16;
- if (dma_isr_redir[11].dma_func)
- dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-#else /* !STM32F10X_CL */
-/**
- * @brief DMA2 streams 4 and 5 shared interrupt handler.
- * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a
- * bit less efficient because an extra check.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- /* Check on channel 4.*/
- flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
- if (flags & STM32_DMA_ISR_MASK) {
- DMA2->IFCR = flags << 12;
- if (dma_isr_redir[10].dma_func)
- dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
- }
-
- /* Check on channel 5.*/
- flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
- if (flags & STM32_DMA_ISR_MASK) {
- DMA2->IFCR = flags << 16;
- if (dma_isr_redir[11].dma_func)
- dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* !STM32F10X_CL */
-#endif /* STM32_HAS_DMA2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
- int i;
-
- dma_streams_mask = 0;
- for (i = 0; i < STM32_DMA_STREAMS; i++) {
- _stm32_dma_streams[i].channel->CCR = 0;
- dma_isr_redir[i].dma_func = NULL;
- }
- DMA1->IFCR = 0xFFFFFFFF;
-#if STM32_HAS_DMA2
- DMA2->IFCR = 0xFFFFFFFF;
-#endif
-}
-
-/**
- * @brief Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- * The function also enables the IRQ vector associated to the stream
- * and initializes its priority.
- * @pre The stream must not be already in use or an error is returned.
- * @post The stream is allocated and the default ISR handler redirected
- * to the specified function.
- * @post The stream ISR vector is enabled and its priority configured.
- * @post The stream must be freed using @p dmaStreamRelease() before it can
- * be reused with another peripheral.
- * @post The stream is in its post-reset state.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] priority IRQ priority mask for the DMA stream
- * @param[in] func handling function pointer, can be @p NULL
- * @param[in] param a parameter to be passed to the handling function
- * @return The operation status.
- * @retval FALSE no error, stream taken.
- * @retval TRUE error, stream already taken.
- *
- * @special
- */
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param) {
-
- chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
-
- /* Checks if the stream is already taken.*/
- if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
- return TRUE;
-
- /* Marks the stream as allocated.*/
- dma_isr_redir[dmastp->selfindex].dma_func = func;
- dma_isr_redir[dmastp->selfindex].dma_param = param;
- dma_streams_mask |= (1 << dmastp->selfindex);
-
- /* Enabling DMA clocks required by the current streams set.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
- rccEnableDMA1(FALSE);
-#if STM32_HAS_DMA2
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
- rccEnableDMA2(FALSE);
-#endif
-
- /* Putting the stream in a safe state.*/
- dmaStreamDisable(dmastp);
- dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
- /* Enables the associated IRQ vector if a callback is defined.*/
- if (func != NULL)
- nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
-
- return FALSE;
-}
-
-/**
- * @brief Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- * Trying to release a unallocated stream is an illegal operation
- * and is trapped if assertions are enabled.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post The stream is again available.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
- chDbgCheck(dmastp != NULL, "dmaStreamRelease");
-
- /* Check if the streams is not taken.*/
- chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
- "dmaStreamRelease(), #1", "not allocated");
-
- /* Marks the stream as not allocated.*/
- dma_streams_mask &= ~(1 << dmastp->selfindex);
-
- /* Disables the associated IRQ vector.*/
-#if !(STM32_HAS_DMA2 && !defined(STM32F10X_CL))
- nvicDisableVector(dmastp->vector);
-#else
- /* Check unless it is 10 or 11 stream. If yes, make additional check before
- disabling IRQ.*/
- if (dmastp->selfindex < 10)
- nvicDisableVector(dmastp->vector);
- else {
- if ((dma_streams_mask & (3 << 10)) == 0)
- nvicDisableVector(dmastp->vector);
- }
-#endif /* STM32_HAS_DMA2 && !STM32F10X_CL */
-
- /* Shutting down clocks that are no more required, if any.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
- rccDisableDMA1(FALSE);
-#if STM32_HAS_DMA2
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
- rccDisableDMA2(FALSE);
-#endif
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_dma.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_dma.h
deleted file mode 100644
index 8bbd8b637e..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_dma.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F1xx/stm32_dma.h
- * @brief DMA helper driver header.
- * @note This file requires definitions from the ST header file stm32f10x.h.
- * @note This driver uses the new naming convention used for the STM32F2xx
- * so the "DMA channels" are referred as "DMA streams".
- *
- * @addtogroup STM32F1xx_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Total number of DMA streams.
- * @note This is the total number of streams among all the DMA units.
- */
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-#define STM32_DMA_STREAMS 12
-#else
-#define STM32_DMA_STREAMS 7
-#endif
-
-/**
- * @brief Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK 0x0F
-
-/**
- * @brief Returns the channel associated to the specified stream.
- *
- * @param[in] n the stream number (0...STM32_DMA_STREAMS-1)
- * @param[in] c a stream/channel association word, one channel per
- * nibble, not associated channels must be set to 0xF
- * @return Always zero, in this platform there is no dynamic
- * association between streams and channels.
- */
-#define STM32_DMA_GETCHANNEL(n, c) 0
-
-/**
- * @brief Checks if a DMA priority is within the valid range.
- * @param[in] prio DMA priority
- *
- * @retval The check result.
- * @retval FALSE invalid DMA priority.
- * @retval TRUE correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma the DMA unit number
- * @param[in] stream the stream number
- * @return An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
-
-/**
- * @brief Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma the DMA unit number
- * @param[in] stream the stream number
- * @return A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
- (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id the stream numeric identifier
- * @param[in] mask the stream numeric identifiers mask
- *
- * @retval The check result.
- * @retval FALSE id does not belong to the mask.
- * @retval TRUE id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name DMA streams identifiers
- * @{
- */
-/**
- * @brief Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id the stream numeric identifier
- * @return A pointer to the stm32_dma_stream_t constant structure
- * associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
-#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7)
-#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8)
-#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9)
-#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10)
-#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11)
-/** @} */
-
-/**
- * @name CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN DMA_CCR1_EN
-#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE
-#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE
-#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE
-#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M 0
-#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR
-#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM
-#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC
-#define STM32_DMA_CR_PINC DMA_CCR1_PINC
-#define STM32_DMA_CR_MINC DMA_CCR1_MINC
-#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE 0
-#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE 0
-#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
- STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL
-#define STM32_DMA_CR_PL(n) ((n) << 12)
-/** @} */
-
-/**
- * @name CR register constants only found in enhanced DMA
- * @{
- */
-#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */
-#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
-#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
-/** @} */
-
-/**
- * @name Status flags passed to the ISR callbacks
- * @{
- */
-#define STM32_DMA_ISR_FEIF 0
-#define STM32_DMA_ISR_DMEIF 0
-#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
-#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
-#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 DMA stream descriptor structure.
- */
-typedef struct {
- DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
- volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
- uint8_t ishift; /**< @brief Bits offset in xIFCR
- register. */
- uint8_t selfindex; /**< @brief Index to self in array. */
- uint8_t vector; /**< @brief Associated IRQ vector. */
-} stm32_dma_stream_t;
-
-/**
- * @brief STM32 DMA ISR function type.
- *
- * @param[in] p parameter for the registered function
- * @param[in] flags pre-shifted content of the ISR register, the bits
- * are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Associates a peripheral data register to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] addr value to be written in the CPAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) { \
- (dmastp)->channel->CPAR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Associates a memory destination to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] addr value to be written in the CMAR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) { \
- (dmastp)->channel->CMAR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Sets the number of transfers to be performed.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] size value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) { \
- (dmastp)->channel->CNDTR = (uint32_t)(size); \
-}
-
-/**
- * @brief Returns the number of transfers to be performed.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @return The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
-
-/**
- * @brief Programs the stream mode settings.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] mode value to be written in the CCR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) { \
- (dmastp)->channel->CCR = (uint32_t)(mode); \
-}
-
-/**
- * @brief DMA stream enable.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) { \
- (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
-}
-
-/**
- * @brief DMA stream disable.
- * @details The function disables the specified stream and then clears any
- * pending interrupt.
- * @note This function can be invoked in both ISR or thread context.
- * @note Interrupts enabling flags are set to zero after this call, see
- * bug 3607518.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) { \
- (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
- STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \
- dmaStreamClearInterrupt(dmastp); \
-}
-
-/**
- * @brief DMA stream interrupt sources clear.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) { \
- *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
-}
-
-/**
- * @brief Starts a memory to memory operation using the specified stream.
- * @note The default transfer data mode is "byte to byte" but it can be
- * changed by specifying extra options in the @p mode parameter.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] mode value to be written in the CCR register, this value
- * is implicitly ORed with:
- * - @p STM32_DMA_CR_MINC
- * - @p STM32_DMA_CR_PINC
- * - @p STM32_DMA_CR_DIR_M2M
- * - @p STM32_DMA_CR_EN
- * .
- * @param[in] src source address
- * @param[in] dst destination address
- * @param[in] n number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
- dmaStreamSetPeripheral(dmastp, src); \
- dmaStreamSetMemory0(dmastp, dst); \
- dmaStreamSetTransactionSize(dmastp, n); \
- dmaStreamSetMode(dmastp, (mode) | \
- STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
- STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
-}
-
-/**
- * @brief Polled wait for DMA transfer end.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) { \
- while ((dmastp)->channel->CNDTR > 0) \
- ; \
- dmaStreamDisable(dmastp); \
-}
-
-/** @} */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void dmaInit(void);
- bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param);
- void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32f10x.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32f10x.h
deleted file mode 100644
index ab2d175859..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32f10x.h
+++ /dev/null
@@ -1,8357 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x.h
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F10x Connectivity line,
- * High density, High density value line, Medium density,
- * Medium density Value line, Low density, Low density Value line
- * and XL-density devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripheral�s drivers in application code(i.e.
- * code will be based on direct access to peripheral�s registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral�s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * © COPYRIGHT 2011 STMicroelectronics
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f10x
- * @{
- */
-
-#ifndef __STM32F10x_H
-#define __STM32F10x_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32 device used in your
- application
- */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
- /* CHIBIOS FIX */
-#include "board.h"
- /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
- /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
- /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
- /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
- /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
- /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
- /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */
- /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
-#endif
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
-
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
- where the Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density value line devices are STM32F100xx microcontrollers where the Flash
- memory density ranges between 16 and 32 Kbytes.
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
- where the Flash memory density ranges between 64 and 128 Kbytes.
- - Medium-density value line devices are STM32F100xx microcontrollers where the
- Flash memory density ranges between 64 and 128 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
- the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density value line devices are STM32F100xx microcontrollers where the
- Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
- the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
- */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
- #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
-#endif
-
-#if !defined USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_STDPERIPH_DRIVER*/
-#endif
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#if !defined HSE_VALUE
- #ifdef STM32F10X_CL
- #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
- #else
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
- #endif /* STM32F10X_CL */
-#endif /* HSE_VALUE */
-
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
-
-#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
-
-/**
- * @brief STM32F10x Standard Peripheral Library version number
- */
-#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
-#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
-#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
- |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
- |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
- |(__STM32F10X_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
- */
-#ifdef STM32F10X_XL
- #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
-#else
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#endif /* STM32F10X_XL */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * @brief STM32F10x Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-
-/****** STM32 specific Interrupt Numbers *********************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMPER_IRQn = 2, /*!< Tamper Interrupt */
- RTC_IRQn = 3, /*!< RTC global Interrupt */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
-
-#ifdef STM32F10X_LD
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-#endif /* STM32F10X_LD */
-
-#ifdef STM32F10X_LD_VL
- ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
- TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
- TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
- TIM7_IRQn = 55 /*!< TIM7 Interrupt */
-#endif /* STM32F10X_LD_VL */
-
-#ifdef STM32F10X_MD
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-#endif /* STM32F10X_MD */
-
-#ifdef STM32F10X_MD_VL
- ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
- TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
- TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
- TIM7_IRQn = 55 /*!< TIM7 Interrupt */
-#endif /* STM32F10X_MD_VL */
-
-#ifdef STM32F10X_HD
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
- TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
- TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
- TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
-#endif /* STM32F10X_HD */
-
-#ifdef STM32F10X_HD_VL
- ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
- TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
- TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
- TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
- TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
- TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
- TIM7_IRQn = 55, /*!< TIM7 Interrupt */
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
- DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
- mapped at position 60 only if the MISC_REMAP bit in
- the AFIO_MAPR2 register is set) */
-#endif /* STM32F10X_HD_VL */
-
-#ifdef STM32F10X_XL
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
-#endif /* STM32F10X_XL */
-
-#ifdef STM32F10X_CL
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
- CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
- DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
-#endif /* STM32F10X_CL */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm3.h"
-/* CHIBIOS FIX */
-/*#include "system_stm32f10x.h"*/
-#include
-
-/** @addtogroup Exported_types
- * @{
- */
-
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef const int32_t sc32; /*!< Read Only */
-typedef const int16_t sc16; /*!< Read Only */
-typedef const int8_t sc8; /*!< Read Only */
-
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef __I int32_t vsc32; /*!< Read Only */
-typedef __I int16_t vsc16; /*!< Read Only */
-typedef __I int8_t vsc8; /*!< Read Only */
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef const uint32_t uc32; /*!< Read Only */
-typedef const uint16_t uc16; /*!< Read Only */
-typedef const uint8_t uc8; /*!< Read Only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef __I uint32_t vuc32; /*!< Read Only */
-typedef __I uint16_t vuc16; /*!< Read Only */
-typedef __I uint8_t vuc8; /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
-#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
-#define HSE_Value HSE_VALUE
-#define HSI_Value HSI_VALUE
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR;
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t SMPR1;
- __IO uint32_t SMPR2;
- __IO uint32_t JOFR1;
- __IO uint32_t JOFR2;
- __IO uint32_t JOFR3;
- __IO uint32_t JOFR4;
- __IO uint32_t HTR;
- __IO uint32_t LTR;
- __IO uint32_t SQR1;
- __IO uint32_t SQR2;
- __IO uint32_t SQR3;
- __IO uint32_t JSQR;
- __IO uint32_t JDR1;
- __IO uint32_t JDR2;
- __IO uint32_t JDR3;
- __IO uint32_t JDR4;
- __IO uint32_t DR;
-} ADC_TypeDef;
-
-/**
- * @brief Backup Registers
- */
-
-typedef struct
-{
- uint32_t RESERVED0;
- __IO uint16_t DR1;
- uint16_t RESERVED1;
- __IO uint16_t DR2;
- uint16_t RESERVED2;
- __IO uint16_t DR3;
- uint16_t RESERVED3;
- __IO uint16_t DR4;
- uint16_t RESERVED4;
- __IO uint16_t DR5;
- uint16_t RESERVED5;
- __IO uint16_t DR6;
- uint16_t RESERVED6;
- __IO uint16_t DR7;
- uint16_t RESERVED7;
- __IO uint16_t DR8;
- uint16_t RESERVED8;
- __IO uint16_t DR9;
- uint16_t RESERVED9;
- __IO uint16_t DR10;
- uint16_t RESERVED10;
- __IO uint16_t RTCCR;
- uint16_t RESERVED11;
- __IO uint16_t CR;
- uint16_t RESERVED12;
- __IO uint16_t CSR;
- uint16_t RESERVED13[5];
- __IO uint16_t DR11;
- uint16_t RESERVED14;
- __IO uint16_t DR12;
- uint16_t RESERVED15;
- __IO uint16_t DR13;
- uint16_t RESERVED16;
- __IO uint16_t DR14;
- uint16_t RESERVED17;
- __IO uint16_t DR15;
- uint16_t RESERVED18;
- __IO uint16_t DR16;
- uint16_t RESERVED19;
- __IO uint16_t DR17;
- uint16_t RESERVED20;
- __IO uint16_t DR18;
- uint16_t RESERVED21;
- __IO uint16_t DR19;
- uint16_t RESERVED22;
- __IO uint16_t DR20;
- uint16_t RESERVED23;
- __IO uint16_t DR21;
- uint16_t RESERVED24;
- __IO uint16_t DR22;
- uint16_t RESERVED25;
- __IO uint16_t DR23;
- uint16_t RESERVED26;
- __IO uint16_t DR24;
- uint16_t RESERVED27;
- __IO uint16_t DR25;
- uint16_t RESERVED28;
- __IO uint16_t DR26;
- uint16_t RESERVED29;
- __IO uint16_t DR27;
- uint16_t RESERVED30;
- __IO uint16_t DR28;
- uint16_t RESERVED31;
- __IO uint16_t DR29;
- uint16_t RESERVED32;
- __IO uint16_t DR30;
- uint16_t RESERVED33;
- __IO uint16_t DR31;
- uint16_t RESERVED34;
- __IO uint16_t DR32;
- uint16_t RESERVED35;
- __IO uint16_t DR33;
- uint16_t RESERVED36;
- __IO uint16_t DR34;
- uint16_t RESERVED37;
- __IO uint16_t DR35;
- uint16_t RESERVED38;
- __IO uint16_t DR36;
- uint16_t RESERVED39;
- __IO uint16_t DR37;
- uint16_t RESERVED40;
- __IO uint16_t DR38;
- uint16_t RESERVED41;
- __IO uint16_t DR39;
- uint16_t RESERVED42;
- __IO uint16_t DR40;
- uint16_t RESERVED43;
- __IO uint16_t DR41;
- uint16_t RESERVED44;
- __IO uint16_t DR42;
- uint16_t RESERVED45;
-} BKP_TypeDef;
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct
-{
- __IO uint32_t TIR;
- __IO uint32_t TDTR;
- __IO uint32_t TDLR;
- __IO uint32_t TDHR;
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct
-{
- __IO uint32_t RIR;
- __IO uint32_t RDTR;
- __IO uint32_t RDLR;
- __IO uint32_t RDHR;
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct
-{
- __IO uint32_t FR1;
- __IO uint32_t FR2;
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t MCR;
- __IO uint32_t MSR;
- __IO uint32_t TSR;
- __IO uint32_t RF0R;
- __IO uint32_t RF1R;
- __IO uint32_t IER;
- __IO uint32_t ESR;
- __IO uint32_t BTR;
- uint32_t RESERVED0[88];
- CAN_TxMailBox_TypeDef sTxMailBox[3];
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
- uint32_t RESERVED1[12];
- __IO uint32_t FMR;
- __IO uint32_t FM1R;
- uint32_t RESERVED2;
- __IO uint32_t FS1R;
- uint32_t RESERVED3;
- __IO uint32_t FFA1R;
- uint32_t RESERVED4;
- __IO uint32_t FA1R;
- uint32_t RESERVED5[8];
-#ifndef STM32F10X_CL
- CAN_FilterRegister_TypeDef sFilterRegister[14];
-#else
- CAN_FilterRegister_TypeDef sFilterRegister[28];
-#endif /* STM32F10X_CL */
-} CAN_TypeDef;
-
-/**
- * @brief Consumer Electronics Control (CEC)
- */
-typedef struct
-{
- __IO uint32_t CFGR;
- __IO uint32_t OAR;
- __IO uint32_t PRES;
- __IO uint32_t ESR;
- __IO uint32_t CSR;
- __IO uint32_t TXD;
- __IO uint32_t RXD;
-} CEC_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR;
- __IO uint8_t IDR;
- uint8_t RESERVED0;
- uint16_t RESERVED1;
- __IO uint32_t CR;
-} CRC_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t SWTRIGR;
- __IO uint32_t DHR12R1;
- __IO uint32_t DHR12L1;
- __IO uint32_t DHR8R1;
- __IO uint32_t DHR12R2;
- __IO uint32_t DHR12L2;
- __IO uint32_t DHR8R2;
- __IO uint32_t DHR12RD;
- __IO uint32_t DHR12LD;
- __IO uint32_t DHR8RD;
- __IO uint32_t DOR1;
- __IO uint32_t DOR2;
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- __IO uint32_t SR;
-#endif
-} DAC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE;
- __IO uint32_t CR;
-}DBGMCU_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CCR;
- __IO uint32_t CNDTR;
- __IO uint32_t CPAR;
- __IO uint32_t CMAR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR;
- __IO uint32_t IFCR;
-} DMA_TypeDef;
-
-/**
- * @brief Ethernet MAC
- */
-
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACFFR;
- __IO uint32_t MACHTHR;
- __IO uint32_t MACHTLR;
- __IO uint32_t MACMIIAR;
- __IO uint32_t MACMIIDR;
- __IO uint32_t MACFCR;
- __IO uint32_t MACVLANTR; /* 8 */
- uint32_t RESERVED0[2];
- __IO uint32_t MACRWUFFR; /* 11 */
- __IO uint32_t MACPMTCSR;
- uint32_t RESERVED1[2];
- __IO uint32_t MACSR; /* 15 */
- __IO uint32_t MACIMR;
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR; /* 24 */
- uint32_t RESERVED2[40];
- __IO uint32_t MMCCR; /* 65 */
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR; /* 69 */
- uint32_t RESERVED3[14];
- __IO uint32_t MMCTGFSCCR; /* 84 */
- __IO uint32_t MMCTGFMSCCR;
- uint32_t RESERVED4[5];
- __IO uint32_t MMCTGFCR;
- uint32_t RESERVED5[10];
- __IO uint32_t MMCRFCECR;
- __IO uint32_t MMCRFAECR;
- uint32_t RESERVED6[10];
- __IO uint32_t MMCRGUFCR;
- uint32_t RESERVED7[334];
- __IO uint32_t PTPTSCR;
- __IO uint32_t PTPSSIR;
- __IO uint32_t PTPTSHR;
- __IO uint32_t PTPTSLR;
- __IO uint32_t PTPTSHUR;
- __IO uint32_t PTPTSLUR;
- __IO uint32_t PTPTSAR;
- __IO uint32_t PTPTTHR;
- __IO uint32_t PTPTTLR;
- uint32_t RESERVED8[567];
- __IO uint32_t DMABMR;
- __IO uint32_t DMATPDR;
- __IO uint32_t DMARPDR;
- __IO uint32_t DMARDLAR;
- __IO uint32_t DMATDLAR;
- __IO uint32_t DMASR;
- __IO uint32_t DMAOMR;
- __IO uint32_t DMAIER;
- __IO uint32_t DMAMFBOCR;
- uint32_t RESERVED9[9];
- __IO uint32_t DMACHTDR;
- __IO uint32_t DMACHRDR;
- __IO uint32_t DMACHTBAR;
- __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR;
- __IO uint32_t EMR;
- __IO uint32_t RTSR;
- __IO uint32_t FTSR;
- __IO uint32_t SWIER;
- __IO uint32_t PR;
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR;
- __IO uint32_t KEYR;
- __IO uint32_t OPTKEYR;
- __IO uint32_t SR;
- __IO uint32_t CR;
- __IO uint32_t AR;
- __IO uint32_t RESERVED;
- __IO uint32_t OBR;
- __IO uint32_t WRPR;
-#ifdef STM32F10X_XL
- uint32_t RESERVED1[8];
- __IO uint32_t KEYR2;
- uint32_t RESERVED2;
- __IO uint32_t SR2;
- __IO uint32_t CR2;
- __IO uint32_t AR2;
-#endif /* STM32F10X_XL */
-} FLASH_TypeDef;
-
-/**
- * @brief Option Bytes Registers
- */
-
-typedef struct
-{
- __IO uint16_t RDP;
- __IO uint16_t USER;
- __IO uint16_t Data0;
- __IO uint16_t Data1;
- __IO uint16_t WRP0;
- __IO uint16_t WRP1;
- __IO uint16_t WRP2;
- __IO uint16_t WRP3;
-} OB_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8];
-} FSMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7];
-} FSMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2;
- __IO uint32_t SR2;
- __IO uint32_t PMEM2;
- __IO uint32_t PATT2;
- uint32_t RESERVED0;
- __IO uint32_t ECCR2;
-} FSMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3;
- __IO uint32_t SR3;
- __IO uint32_t PMEM3;
- __IO uint32_t PATT3;
- uint32_t RESERVED0;
- __IO uint32_t ECCR3;
-} FSMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4;
- __IO uint32_t SR4;
- __IO uint32_t PMEM4;
- __IO uint32_t PATT4;
- __IO uint32_t PIO4;
-} FSMC_Bank4_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t CRL;
- __IO uint32_t CRH;
- __IO uint32_t IDR;
- __IO uint32_t ODR;
- __IO uint32_t BSRR;
- __IO uint32_t BRR;
- __IO uint32_t LCKR;
-} GPIO_TypeDef;
-
-/**
- * @brief Alternate Function I/O
- */
-
-typedef struct
-{
- __IO uint32_t EVCR;
- __IO uint32_t MAPR;
- __IO uint32_t EXTICR[4];
- uint32_t RESERVED0;
- __IO uint32_t MAPR2;
-} AFIO_TypeDef;
-/**
- * @brief Inter Integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1;
- uint16_t RESERVED0;
- __IO uint16_t CR2;
- uint16_t RESERVED1;
- __IO uint16_t OAR1;
- uint16_t RESERVED2;
- __IO uint16_t OAR2;
- uint16_t RESERVED3;
- __IO uint16_t DR;
- uint16_t RESERVED4;
- __IO uint16_t SR1;
- uint16_t RESERVED5;
- __IO uint16_t SR2;
- uint16_t RESERVED6;
- __IO uint16_t CCR;
- uint16_t RESERVED7;
- __IO uint16_t TRISE;
- uint16_t RESERVED8;
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR;
- __IO uint32_t PR;
- __IO uint32_t RLR;
- __IO uint32_t SR;
-} IWDG_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CSR;
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CFGR;
- __IO uint32_t CIR;
- __IO uint32_t APB2RSTR;
- __IO uint32_t APB1RSTR;
- __IO uint32_t AHBENR;
- __IO uint32_t APB2ENR;
- __IO uint32_t APB1ENR;
- __IO uint32_t BDCR;
- __IO uint32_t CSR;
-
-#ifdef STM32F10X_CL
- __IO uint32_t AHBRSTR;
- __IO uint32_t CFGR2;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- uint32_t RESERVED0;
- __IO uint32_t CFGR2;
-#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint16_t CRH;
- uint16_t RESERVED0;
- __IO uint16_t CRL;
- uint16_t RESERVED1;
- __IO uint16_t PRLH;
- uint16_t RESERVED2;
- __IO uint16_t PRLL;
- uint16_t RESERVED3;
- __IO uint16_t DIVH;
- uint16_t RESERVED4;
- __IO uint16_t DIVL;
- uint16_t RESERVED5;
- __IO uint16_t CNTH;
- uint16_t RESERVED6;
- __IO uint16_t CNTL;
- uint16_t RESERVED7;
- __IO uint16_t ALRH;
- uint16_t RESERVED8;
- __IO uint16_t ALRL;
- uint16_t RESERVED9;
-} RTC_TypeDef;
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER;
- __IO uint32_t CLKCR;
- __IO uint32_t ARG;
- __IO uint32_t CMD;
- __I uint32_t RESPCMD;
- __I uint32_t RESP1;
- __I uint32_t RESP2;
- __I uint32_t RESP3;
- __I uint32_t RESP4;
- __IO uint32_t DTIMER;
- __IO uint32_t DLEN;
- __IO uint32_t DCTRL;
- __I uint32_t DCOUNT;
- __I uint32_t STA;
- __IO uint32_t ICR;
- __IO uint32_t MASK;
- uint32_t RESERVED0[2];
- __I uint32_t FIFOCNT;
- uint32_t RESERVED1[13];
- __IO uint32_t FIFO;
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1;
- uint16_t RESERVED0;
- __IO uint16_t CR2;
- uint16_t RESERVED1;
- __IO uint16_t SR;
- uint16_t RESERVED2;
- __IO uint16_t DR;
- uint16_t RESERVED3;
- __IO uint16_t CRCPR;
- uint16_t RESERVED4;
- __IO uint16_t RXCRCR;
- uint16_t RESERVED5;
- __IO uint16_t TXCRCR;
- uint16_t RESERVED6;
- __IO uint16_t I2SCFGR;
- uint16_t RESERVED7;
- __IO uint16_t I2SPR;
- uint16_t RESERVED8;
-} SPI_TypeDef;
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1;
- uint16_t RESERVED0;
- __IO uint16_t CR2;
- uint16_t RESERVED1;
- __IO uint16_t SMCR;
- uint16_t RESERVED2;
- __IO uint16_t DIER;
- uint16_t RESERVED3;
- __IO uint16_t SR;
- uint16_t RESERVED4;
- __IO uint16_t EGR;
- uint16_t RESERVED5;
- __IO uint16_t CCMR1;
- uint16_t RESERVED6;
- __IO uint16_t CCMR2;
- uint16_t RESERVED7;
- __IO uint16_t CCER;
- uint16_t RESERVED8;
- __IO uint16_t CNT;
- uint16_t RESERVED9;
- __IO uint16_t PSC;
- uint16_t RESERVED10;
- __IO uint16_t ARR;
- uint16_t RESERVED11;
- __IO uint16_t RCR;
- uint16_t RESERVED12;
- __IO uint16_t CCR1;
- uint16_t RESERVED13;
- __IO uint16_t CCR2;
- uint16_t RESERVED14;
- __IO uint16_t CCR3;
- uint16_t RESERVED15;
- __IO uint16_t CCR4;
- uint16_t RESERVED16;
- __IO uint16_t BDTR;
- uint16_t RESERVED17;
- __IO uint16_t DCR;
- uint16_t RESERVED18;
- __IO uint16_t DMAR;
- uint16_t RESERVED19;
-} TIM_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint16_t SR;
- uint16_t RESERVED0;
- __IO uint16_t DR;
- uint16_t RESERVED1;
- __IO uint16_t BRR;
- uint16_t RESERVED2;
- __IO uint16_t CR1;
- uint16_t RESERVED3;
- __IO uint16_t CR2;
- uint16_t RESERVED4;
- __IO uint16_t CR3;
- uint16_t RESERVED5;
- __IO uint16_t GTPR;
- uint16_t RESERVED6;
-} USART_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CFR;
- __IO uint32_t SR;
-} WWDG_TypeDef;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
-
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
-#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
-
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
-
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
-
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
-
-#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)
-
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
-
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define ETH ((ETH_TypeDef *) ETH_BASE)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* CRC calculation unit */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
-
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
-
-/******************************************************************************/
-/* */
-/* Power Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
-#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
-
-#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
-
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
-#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
-
-/******************************************************************************/
-/* */
-/* Backup registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for BKP_DR1 register ********************/
-#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR2 register ********************/
-#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR3 register ********************/
-#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR4 register ********************/
-#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR5 register ********************/
-#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR6 register ********************/
-#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR7 register ********************/
-#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR8 register ********************/
-#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR9 register ********************/
-#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR10 register *******************/
-#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR11 register *******************/
-#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR12 register *******************/
-#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR13 register *******************/
-#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR14 register *******************/
-#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR15 register *******************/
-#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR16 register *******************/
-#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR17 register *******************/
-#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/****************** Bit definition for BKP_DR18 register ********************/
-#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR19 register *******************/
-#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR20 register *******************/
-#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR21 register *******************/
-#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR22 register *******************/
-#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR23 register *******************/
-#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR24 register *******************/
-#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR25 register *******************/
-#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR26 register *******************/
-#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR27 register *******************/
-#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR28 register *******************/
-#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR29 register *******************/
-#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR30 register *******************/
-#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR31 register *******************/
-#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR32 register *******************/
-#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR33 register *******************/
-#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR34 register *******************/
-#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR35 register *******************/
-#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR36 register *******************/
-#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR37 register *******************/
-#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR38 register *******************/
-#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR39 register *******************/
-#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR40 register *******************/
-#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR41 register *******************/
-#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/******************* Bit definition for BKP_DR42 register *******************/
-#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
-
-/****************** Bit definition for BKP_RTCCR register *******************/
-#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
-#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
-#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
-#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
-
-/******************** Bit definition for BKP_CR register ********************/
-#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
-#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
-
-/******************* Bit definition for BKP_CSR register ********************/
-#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
-#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
-#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
-#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
-#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
-
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
-#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
-
-#ifdef STM32F10X_CL
- #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
- #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
- #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
- #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
-#endif /* STM32F10X_CL */
-
-/******************* Bit definition for RCC_CFGR register *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
-
-/*!< ADCPPRE configuration */
-#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
-#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
-
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
-
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
-
-#ifdef STM32F10X_CL
- #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
-
- #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
- #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
-
- #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
- #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
- #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
- #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
- #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
- #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
- #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
-
- #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */
-
-/*!< MCO configuration */
- #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
- #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
- #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
- #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
- #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
- #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
- #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
- #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
- #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
- #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
- #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
- #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
- #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
- #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
-
- #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
- #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
-
- #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
- #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
- #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
- #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
- #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
- #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
- #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
- #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
- #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
- #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
- #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
- #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
- #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
- #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
- #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
-
-/*!< MCO configuration */
- #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
- #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
- #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
- #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-
- #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
- #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
- #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
- #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
- #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
-#else
- #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
-
- #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
- #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
-
- #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
- #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
- #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
- #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
- #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
- #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
- #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
- #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
- #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
- #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
- #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
- #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
- #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
- #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
- #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
- #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
-
-/*!< MCO configuration */
- #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
- #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
- #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
- #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-
- #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
- #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
- #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
- #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
- #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
-#endif /* STM32F10X_CL */
-
-/*!<****************** Bit definition for RCC_CIR register ********************/
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
-
-#ifdef STM32F10X_CL
- #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
- #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
- #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
- #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
- #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
- #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
-#endif /* STM32F10X_CL */
-
-/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
-#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
-#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
-#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
-#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
-#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
-#endif
-
-#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
-#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
-#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
-#endif
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
- #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
- #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
- #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
- #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
-#endif
-
-#ifdef STM32F10X_XL
- #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */
- #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */
- #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */
-#endif /* STM32F10X_XL */
-
-/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
-#endif
-
-#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
- #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
- #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
- #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
- #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
-#endif
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
- #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
- #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
- #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
- #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
- #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
- #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
- #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
-#endif
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
- #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
- #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
- #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
- #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
- #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
- #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
- #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
- #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
- #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
-#endif
-
-#ifdef STM32F10X_CL
- #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */
-#endif /* STM32F10X_CL */
-
-#ifdef STM32F10X_XL
- #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
- #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
- #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
-#endif /* STM32F10X_XL */
-
-/****************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
-#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
-#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
-#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
-
-/* CHIBIOS FIX */
-//#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_XL)
- #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
-#endif
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
- #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
-#endif
-
-#ifdef STM32F10X_CL
- #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
- #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
- #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
- #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
-#endif /* STM32F10X_CL */
-
-/****************** Bit definition for RCC_APB2ENR register *****************/
-#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
-#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
-#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
-#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
-#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
-#endif
-
-#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
-#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
-#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
-#endif
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
- #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
- #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
- #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
- #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
-#endif
-
-#ifdef STM32F10X_XL
- #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */
- #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */
- #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */
-#endif
-
-/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
-#endif
-
-#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
- #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
- #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
- #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-/* CHIBIOS FIX */
-//#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
-#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
- #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
-#endif
-
-/* CHIBIOS FIX */
-//#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
-#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_CL)
- #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
- #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
- #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
- #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
- #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
- #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
- #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
-#endif
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
- #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
- #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
- #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
-#endif
-
-#ifdef STM32F10X_HD_VL
- #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
- #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
- #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
- #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
- #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
- #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
- #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
-#endif /* STM32F10X_HD_VL */
-
-#ifdef STM32F10X_CL
- #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */
-#endif /* STM32F10X_CL */
-
-#ifdef STM32F10X_XL
- #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
- #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
- #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
-#endif /* STM32F10X_XL */
-
-/******************* Bit definition for RCC_BDCR register *******************/
-#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
-#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
-#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
-
-#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
-
-#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
-#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
-
-/******************* Bit definition for RCC_CSR register ********************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
-
-#ifdef STM32F10X_CL
-/******************* Bit definition for RCC_AHBRSTR register ****************/
- #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
- #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
-
-/******************* Bit definition for RCC_CFGR2 register ******************/
-/*!< PREDIV1 configuration */
- #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
- #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
- #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
- #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
- #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
- #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
- #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
- #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
- #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
- #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
- #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
- #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
- #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
- #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
- #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
- #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
- #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
- #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
- #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
- #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
- #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
-
-/*!< PREDIV2 configuration */
- #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
- #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
- #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
- #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
- #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
- #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
- #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
- #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
- #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
- #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
- #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
- #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
- #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
- #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
- #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
- #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
- #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
- #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
- #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
- #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
- #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
-
-/*!< PLL2MUL configuration */
- #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
- #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
- #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
- #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
- #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
- #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
- #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
- #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
- #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
- #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
- #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
- #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
- #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
- #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
-
-/*!< PLL3MUL configuration */
- #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
- #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
- #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
- #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
- #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
-
- #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
- #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
- #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
- #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
- #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
- #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
- #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
- #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
- #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
-
- #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
- #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
- #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
- #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
- #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/******************* Bit definition for RCC_CFGR2 register ******************/
-/*!< PREDIV1 configuration */
- #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
- #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
- #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
- #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
- #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
- #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
- #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
- #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
- #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
- #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
- #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
- #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
- #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
- #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
- #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
- #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
- #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
- #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
- #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
- #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
- #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
-#endif
-
-/******************************************************************************/
-/* */
-/* General Purpose and Alternate Function I/O */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for GPIO_CRL register *******************/
-#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
-
-#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
-#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
-#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
-#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
-#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-
-#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
-#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
-#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-
-#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
-#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-
-#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
-#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
-
-#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
-#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
-#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
-#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-
-#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
-#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
-
-#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
-#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-
-#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
-#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
-#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-
-#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
-#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-
-#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
-#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
-#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
-
-/******************* Bit definition for GPIO_CRH register *******************/
-#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
-
-#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
-#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
-#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
-#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
-#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-
-#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
-#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
-#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-
-#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
-#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-
-#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
-#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
-
-#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
-#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
-#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
-#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-
-#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
-#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
-
-#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
-#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-
-#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
-#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
-#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-
-#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
-#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-
-#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
-#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
-#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
-
-/*!<****************** Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
-#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
-#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
-#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
-#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
-#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
-#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
-#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
-#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
-#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
-#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
-#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
-#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
-#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
-#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
-#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
-
-/******************* Bit definition for GPIO_ODR register *******************/
-#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
-#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
-#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
-#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
-#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
-#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
-#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
-#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
-#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
-#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
-#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
-#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
-#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
-#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
-#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
-#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
-
-/****************** Bit definition for GPIO_BSRR register *******************/
-#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
-#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
-#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
-#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
-#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
-#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
-#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
-#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
-#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
-#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
-#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
-#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
-#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
-#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
-#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
-#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
-
-#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
-#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
-#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
-#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
-#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
-#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
-#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
-#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
-#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
-#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
-#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
-#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
-#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
-#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
-#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
-#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
-
-/******************* Bit definition for GPIO_BRR register *******************/
-#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
-#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
-#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
-#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
-#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
-#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
-#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
-#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
-#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
-#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
-#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
-#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
-#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
-#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
-#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
-#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
-
-/****************** Bit definition for GPIO_LCKR register *******************/
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
-
-/*----------------------------------------------------------------------------*/
-
-/****************** Bit definition for AFIO_EVCR register *******************/
-#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
-#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
-#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
-#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
-#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
-
-/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
-#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
-#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
-#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
-#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
-#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
-#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
-#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
-#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
-#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
-#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
-#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
-#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
-#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
-#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
-#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
-
-#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
-#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
-#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
-#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
-
-/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
-#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
-#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
-#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
-#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
-
-#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
-
-/****************** Bit definition for AFIO_MAPR register *******************/
-#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
-#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
-#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
-#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
-
-#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
-#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-
-#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
-#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-
-#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
-#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-
-#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
-#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-
-/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-
-#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
-
-#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
-#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-
-/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
-
-#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
-
-/*!< SWJ_CFG configuration */
-#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
-#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
-#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
-
-#ifdef STM32F10X_CL
-/*!< ETH_REMAP configuration */
- #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
-
-/*!< CAN2_REMAP configuration */
- #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
-
-/*!< MII_RMII_SEL configuration */
- #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
-
-/*!< SPI3_REMAP configuration */
- #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */
-
-/*!< TIM2ITR1_IREMAP configuration */
- #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
-
-/*!< PTP_PPS_REMAP configuration */
- #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
-#endif
-
-/***************** Bit definition for AFIO_EXTICR1 register *****************/
-#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
-#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
-#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
-
-/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
-#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
-#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
-
-/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
-#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
-#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
-
-/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
-#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
-#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
-
-/***************** Bit definition for AFIO_EXTICR2 register *****************/
-#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
-#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
-#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
-
-/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
-#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
-#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
-
-/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
-#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
-#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
-
-/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
-#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
-#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
-
-/***************** Bit definition for AFIO_EXTICR3 register *****************/
-#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
-#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
-#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
-
-/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
-#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
-#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
-
-/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
-#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
-#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
-#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
-
-/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
-#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
-#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
-
-/***************** Bit definition for AFIO_EXTICR4 register *****************/
-#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
-#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
-#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
-
-/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
-#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
-#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
-
-/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
-#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
-#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
-
-/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
-#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
-#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/****************** Bit definition for AFIO_MAPR2 register ******************/
-#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
-#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
-#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
-#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
-#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
-#endif
-
-#ifdef STM32F10X_HD_VL
-#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
-#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
-#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
-#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
-#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */
-#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */
-#endif
-
-#ifdef STM32F10X_XL
-/****************** Bit definition for AFIO_MAPR2 register ******************/
-#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */
-#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */
-#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */
-#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
-#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
-#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
-#endif
-
-/******************************************************************************/
-/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
-#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
-#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
-#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-
-/******************* Bit definition for EXTI_EMR register *******************/
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-
-/****************** Bit definition for EXTI_RTSR register *******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-
-/****************** Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-
-/****************** Bit definition for EXTI_SWIER register ******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-
-/******************* Bit definition for EXTI_PR register ********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
-
-/******************************************************************************/
-/* */
-/* DMA Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
-
-/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
-
-/******************* Bit definition for DMA_CCR1 register *******************/
-#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
-#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/******************* Bit definition for DMA_CCR2 register *******************/
-#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/******************* Bit definition for DMA_CCR3 register *******************/
-#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/*!<****************** Bit definition for DMA_CCR4 register *******************/
-#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/****************** Bit definition for DMA_CCR5 register *******************/
-#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
-
-/******************* Bit definition for DMA_CCR6 register *******************/
-#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/******************* Bit definition for DMA_CCR7 register *******************/
-#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
-
-/****************** Bit definition for DMA_CNDTR1 register ******************/
-#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR2 register ******************/
-#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR3 register ******************/
-#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR4 register ******************/
-#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR5 register ******************/
-#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR6 register ******************/
-#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR7 register ******************/
-#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CPAR1 register *******************/
-#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CPAR2 register *******************/
-#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CPAR3 register *******************/
-#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR4 register *******************/
-#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CPAR5 register *******************/
-#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CPAR6 register *******************/
-#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR7 register *******************/
-#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CMAR1 register *******************/
-#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR2 register *******************/
-#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR3 register *******************/
-#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-
-/****************** Bit definition for DMA_CMAR4 register *******************/
-#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR5 register *******************/
-#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR6 register *******************/
-#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR7 register *******************/
-#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */
-#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */
-#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */
-#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */
-#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */
-
-/******************* Bit definition for ADC_CR1 register ********************/
-#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
-#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
-#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
-#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
-#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
-#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
-#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
-#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
-
-#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */
-#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-
-#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
-#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
-
-
-/******************* Bit definition for ADC_CR2 register ********************/
-#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
-#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
-#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
-#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
-#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
-#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
-
-#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
-#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-
-#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
-
-#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-
-#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
-#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
-#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
-#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
-
-/****************** Bit definition for ADC_SMPR1 register *******************/
-#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-
-/****************** Bit definition for ADC_SMPR2 register *******************/
-#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
-
-/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
-
-/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
-
-/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
-
-/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
-
-/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
-
-/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
-
-/******************* Bit definition for ADC_SQR1 register *******************/
-#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
-#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-/******************* Bit definition for ADC_SQR2 register *******************/
-#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
-#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
-#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
-#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
-
-/******************* Bit definition for ADC_SQR3 register *******************/
-#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
-#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
-#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
-#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
-
-/******************* Bit definition for ADC_JSQR register *******************/
-#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
-#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-
-/******************* Bit definition for ADC_JDR1 register *******************/
-#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
-
-/******************* Bit definition for ADC_JDR2 register *******************/
-#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
-
-/******************* Bit definition for ADC_JDR3 register *******************/
-#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
-
-/******************* Bit definition for ADC_JDR4 register *******************/
-#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
-#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */
-
-/******************************************************************************/
-/* */
-/* Digital to Analog Converter */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
-
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
-
-/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12R2 register ******************/
-#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L2 register ******************/
-#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R2 register ******************/
-#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12RD register ******************/
-#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12LD register ******************/
-#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8RD register ******************/
-#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
-
-/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
-
-/******************* Bit definition for DAC_DOR2 register *******************/
-#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
-
-/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/* */
-/* CEC */
-/* */
-/******************************************************************************/
-/******************** Bit definition for CEC_CFGR register ******************/
-#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
-#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
-#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
-#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
-
-/******************** Bit definition for CEC_OAR register ******************/
-#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
-#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
-
-/******************** Bit definition for CEC_PRES register ******************/
-#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
-
-/******************** Bit definition for CEC_ESR register ******************/
-#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
-#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
-#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
-#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
-#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
-#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
-#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */
-
-/******************** Bit definition for CEC_CSR register ******************/
-#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
-#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
-#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
-#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
-#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
-#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
-#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
-#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
-
-/******************** Bit definition for CEC_TXD register ******************/
-#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
-
-/******************** Bit definition for CEC_RXD register ******************/
-#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
-
-/******************************************************************************/
-/* */
-/* TIM */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */
-
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */
-
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */
-
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */
-
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */
-
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */
-
-/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */
-
-/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */
-#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */
-
-/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
-
-/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
-
-/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */
-
-/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
-
-/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
-
-/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */
-
-/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */
-
-#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */
-#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */
-#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */
-#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */
-
-/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */
-
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */
-
-/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for RTC_CRH register ********************/
-#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */
-#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */
-#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */
-
-/******************* Bit definition for RTC_CRL register ********************/
-#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */
-#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */
-#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */
-#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */
-#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */
-#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */
-
-/******************* Bit definition for RTC_PRLH register *******************/
-#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */
-
-/******************* Bit definition for RTC_PRLL register *******************/
-#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */
-
-/******************* Bit definition for RTC_DIVH register *******************/
-#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */
-
-/******************* Bit definition for RTC_DIVL register *******************/
-#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */
-
-/******************* Bit definition for RTC_CNTH register *******************/
-#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */
-
-/******************* Bit definition for RTC_CNTL register *******************/
-#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */
-
-/******************* Bit definition for RTC_ALRH register *******************/
-#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */
-
-/******************* Bit definition for RTC_ALRL register *******************/
-#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
-
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
-
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/* */
-/* Flexible Static Memory Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for FSMC_BCR1 register *******************/
-#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
-#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
-
-#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
-#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
-#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
-#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
-#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
-#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
-#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
-#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
-#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
-#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
-
-/****************** Bit definition for FSMC_BCR2 register *******************/
-#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
-#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
-
-#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
-#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
-#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
-#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
-#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
-#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
-#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
-#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
-#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
-#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
-
-/****************** Bit definition for FSMC_BCR3 register *******************/
-#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
-#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
-
-#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
-#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
-#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
-#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
-#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
-#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
-#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
-#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
-#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
-#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
-
-/****************** Bit definition for FSMC_BCR4 register *******************/
-#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
-#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
-
-#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
-#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
-#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
-#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
-#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
-#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
-#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
-#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
-#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
-#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
-
-/****************** Bit definition for FSMC_BTR1 register ******************/
-#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-
-#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-/****************** Bit definition for FSMC_BTR2 register *******************/
-#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-
-#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-/******************* Bit definition for FSMC_BTR3 register *******************/
-#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-
-#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-/****************** Bit definition for FSMC_BTR4 register *******************/
-#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-
-#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-/****************** Bit definition for FSMC_BWTR1 register ******************/
-#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-/****************** Bit definition for FSMC_BWTR2 register ******************/
-#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
-#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-/****************** Bit definition for FSMC_BWTR3 register ******************/
-#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-/****************** Bit definition for FSMC_BWTR4 register ******************/
-#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-/****************** Bit definition for FSMC_PCR2 register *******************/
-#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
-#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */
-
-#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
-
-#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
-
-#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
-
-#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
-#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-
-/****************** Bit definition for FSMC_PCR3 register *******************/
-#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
-#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */
-
-#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
-
-#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
-
-#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
-
-#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-
-/****************** Bit definition for FSMC_PCR4 register *******************/
-#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
-#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */
-
-#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-
-#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
-
-#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
-
-#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
-
-#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-
-/******************* Bit definition for FSMC_SR2 register *******************/
-#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
-#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
-#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
-#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
-#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
-
-/******************* Bit definition for FSMC_SR3 register *******************/
-#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
-#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
-#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
-#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
-#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
-
-/******************* Bit definition for FSMC_SR4 register *******************/
-#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
-#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
-#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
-#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
-#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
-
-/****************** Bit definition for FSMC_PMEM2 register ******************/
-#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-
-#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-
-#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-
-#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
-#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
-#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
-#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
-
-/****************** Bit definition for FSMC_PMEM3 register ******************/
-#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-
-#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-
-#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-
-#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
-#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
-#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
-#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
-
-/****************** Bit definition for FSMC_PMEM4 register ******************/
-#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-
-#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-
-#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-
-#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
-#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
-#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
-#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
-
-/****************** Bit definition for FSMC_PATT2 register ******************/
-#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-
-#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-
-#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-
-#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
-#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
-#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
-#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
-
-/****************** Bit definition for FSMC_PATT3 register ******************/
-#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-
-#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-
-#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-
-#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
-#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
-#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
-#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
-
-/****************** Bit definition for FSMC_PATT4 register ******************/
-#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-
-#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-
-#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-
-#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
-#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
-#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
-#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
-
-/****************** Bit definition for FSMC_PIO4 register *******************/
-#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */
-#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-
-#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-
-#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-
-#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
-#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
-#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
-#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
-
-/****************** Bit definition for FSMC_ECCR2 register ******************/
-#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
-
-/****************** Bit definition for FSMC_ECCR3 register ******************/
-#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
-
-/******************************************************************************/
-/* */
-/* SD host Interface */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for SDIO_POWER register ******************/
-#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */
-#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */
-
-/****************** Bit definition for SDIO_CLKCR register ******************/
-#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */
-#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */
-#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */
-#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */
-
-#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */
-
-/******************* Bit definition for SDIO_ARG register *******************/
-#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
-
-/******************* Bit definition for SDIO_CMD register *******************/
-#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */
-
-#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
-#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
-
-#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */
-#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */
-
-/***************** Bit definition for SDIO_RESPCMD register *****************/
-#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */
-
-/****************** Bit definition for SDIO_RESP0 register ******************/
-#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP1 register ******************/
-#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP2 register ******************/
-#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP3 register ******************/
-#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP4 register ******************/
-#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
-
-/****************** Bit definition for SDIO_DTIMER register *****************/
-#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
-
-/****************** Bit definition for SDIO_DLEN register *******************/
-#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
-
-/****************** Bit definition for SDIO_DCTRL register ******************/
-#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */
-#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */
-
-#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */
-#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */
-#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */
-#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */
-
-/****************** Bit definition for SDIO_DCOUNT register *****************/
-#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
-
-/****************** Bit definition for SDIO_STA register ********************/
-#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
-#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
-#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
-#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
-#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
-#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
-#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
-#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
-#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
-#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
-#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
-#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
-#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
-
-/******************* Bit definition for SDIO_ICR register *******************/
-#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
-
-/****************** Bit definition for SDIO_MASK register *******************/
-#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/***************** Bit definition for SDIO_FIFOCNT register *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
-
-/****************** Bit definition for SDIO_FIFO register *******************/
-#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/* */
-/* USB Device FS */
-/* */
-/******************************************************************************/
-
-/*!< Endpoint-specific registers */
-/******************* Bit definition for USB_EP0R register *******************/
-#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-
-#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-
-#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-
-#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP1R register *******************/
-#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-
-#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-
-#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-
-#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP2R register *******************/
-#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-
-#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-
-#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-
-#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP3R register *******************/
-#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-
-#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-
-#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-
-#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP4R register *******************/
-#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-
-#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-
-#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-
-#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP5R register *******************/
-#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-
-#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-
-#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-
-#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP6R register *******************/
-#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-
-#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-
-#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-
-#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP7R register *******************/
-#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-
-#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-
-#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-
-#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-
-/*!< Common registers */
-/******************* Bit definition for USB_CNTR register *******************/
-#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */
-#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
-#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */
-#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */
-#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
-#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
-
-/******************* Bit definition for USB_ISTR register *******************/
-#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
-#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */
-#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */
-#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */
-#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */
-#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */
-#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */
-#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */
-#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */
-
-/******************* Bit definition for USB_FNR register ********************/
-#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
-#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
-#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */
-#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */
-#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */
-
-/****************** Bit definition for USB_DADDR register *******************/
-#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */
-#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */
-#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */
-#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */
-#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */
-#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */
-#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */
-
-#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */
-
-/****************** Bit definition for USB_BTABLE register ******************/
-#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */
-
-/*!< Buffer descriptor table */
-/***************** Bit definition for USB_ADDR0_TX register *****************/
-#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
-
-/***************** Bit definition for USB_ADDR1_TX register *****************/
-#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
-
-/***************** Bit definition for USB_ADDR2_TX register *****************/
-#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
-
-/***************** Bit definition for USB_ADDR3_TX register *****************/
-#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
-
-/***************** Bit definition for USB_ADDR4_TX register *****************/
-#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
-
-/***************** Bit definition for USB_ADDR5_TX register *****************/
-#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
-
-/***************** Bit definition for USB_ADDR6_TX register *****************/
-#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
-
-/***************** Bit definition for USB_ADDR7_TX register *****************/
-#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_COUNT0_TX register ****************/
-#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
-
-/***************** Bit definition for USB_COUNT1_TX register ****************/
-#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
-
-/***************** Bit definition for USB_COUNT2_TX register ****************/
-#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
-
-/***************** Bit definition for USB_COUNT3_TX register ****************/
-#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
-
-/***************** Bit definition for USB_COUNT4_TX register ****************/
-#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
-
-/***************** Bit definition for USB_COUNT5_TX register ****************/
-#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
-
-/***************** Bit definition for USB_COUNT6_TX register ****************/
-#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
-
-/***************** Bit definition for USB_COUNT7_TX register ****************/
-#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
-
-/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
-
-/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
-
-/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
-
-/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
-
-/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
-
-/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
-
-/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
-
-/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
-
-/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
-
-/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
-
-/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
-
-/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
-
-/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
-
-/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
-
-/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_ADDR0_RX register *****************/
-#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
-
-/***************** Bit definition for USB_ADDR1_RX register *****************/
-#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
-
-/***************** Bit definition for USB_ADDR2_RX register *****************/
-#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
-
-/***************** Bit definition for USB_ADDR3_RX register *****************/
-#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
-
-/***************** Bit definition for USB_ADDR4_RX register *****************/
-#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
-
-/***************** Bit definition for USB_ADDR5_RX register *****************/
-#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
-
-/***************** Bit definition for USB_ADDR6_RX register *****************/
-#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
-
-/***************** Bit definition for USB_ADDR7_RX register *****************/
-#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_COUNT0_RX register ****************/
-#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT1_RX register ****************/
-#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT2_RX register ****************/
-#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT3_RX register ****************/
-#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT4_RX register ****************/
-#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT5_RX register ****************/
-#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT6_RX register ****************/
-#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT7_RX register ****************/
-#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/* */
-/* Controller Area Network */
-/* */
-/******************************************************************************/
-
-/*!< CAN control and status registers */
-/******************* Bit definition for CAN_MCR register ********************/
-#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */
-#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */
-#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */
-#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */
-#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */
-#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
-#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
-#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
-#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */
-
-/******************* Bit definition for CAN_MSR register ********************/
-#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
-#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */
-#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */
-#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */
-#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */
-#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */
-#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */
-#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */
-
-/******************* Bit definition for CAN_TSR register ********************/
-#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
-
-#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
-#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
-#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
-
-/******************* Bit definition for CAN_RF0R register *******************/
-#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */
-#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */
-
-/******************* Bit definition for CAN_RF1R register *******************/
-#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */
-#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */
-
-/******************** Bit definition for CAN_IER register *******************/
-#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
-#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
-
-/******************** Bit definition for CAN_ESR register *******************/
-#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */
-#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */
-#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
-
-#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-
-#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
-
-/******************* Bit definition for CAN_BTR register ********************/
-#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
-#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
-#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
-#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
-#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
-#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */
-
-/*!< Mailbox registers */
-/****************** Bit definition for CAN_TI0R register ********************/
-#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
-#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
-#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
-#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
-#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
-
-/****************** Bit definition for CAN_TDT0R register *******************/
-#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
-#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
-#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
-
-/****************** Bit definition for CAN_TDL0R register *******************/
-#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
-#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
-#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
-#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
-
-/****************** Bit definition for CAN_TDH0R register *******************/
-#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
-#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
-#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
-#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_TI1R register *******************/
-#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
-#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
-#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
-#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
-#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT1R register ******************/
-#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
-#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
-#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL1R register ******************/
-#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
-#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
-#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
-#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_TDH1R register ******************/
-#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
-#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
-#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
-#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_TI2R register *******************/
-#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
-#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
-#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
-#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
-#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT2R register ******************/
-#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
-#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
-#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL2R register ******************/
-#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
-#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
-#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
-#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_TDH2R register ******************/
-#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
-#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
-#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
-#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_RI0R register *******************/
-#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
-#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
-#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
-#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT0R register ******************/
-#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
-#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
-#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL0R register ******************/
-#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
-#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
-#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
-#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_RDH0R register ******************/
-#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
-#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
-#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
-#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_RI1R register *******************/
-#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
-#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
-#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
-#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT1R register ******************/
-#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
-#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
-#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL1R register ******************/
-#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
-#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
-#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
-#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_RDH1R register ******************/
-#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
-#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
-#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
-#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
-
-/*!< CAN filter registers */
-/******************* Bit definition for CAN_FMR register ********************/
-#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */
-
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */
-#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
-
-/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
-
-/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */
-
-/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */
-#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */
-
-/******************* Bit definition for CAN_F0R1 register *******************/
-#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R1 register *******************/
-#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R1 register *******************/
-#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R1 register *******************/
-#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R1 register *******************/
-#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R1 register *******************/
-#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R1 register *******************/
-#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R1 register *******************/
-#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R1 register *******************/
-#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R1 register *******************/
-#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R1 register ******************/
-#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R1 register ******************/
-#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R1 register ******************/
-#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R1 register ******************/
-#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F0R2 register *******************/
-#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R2 register *******************/
-#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R2 register *******************/
-#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R2 register *******************/
-#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R2 register *******************/
-#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R2 register *******************/
-#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R2 register *******************/
-#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R2 register *******************/
-#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R2 register *******************/
-#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R2 register *******************/
-#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R2 register ******************/
-#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R2 register ******************/
-#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R2 register ******************/
-#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R2 register ******************/
-#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
-#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
-#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
-#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
-#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
-#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
-#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
-#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
-#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
-#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
-#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
-#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
-#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
-#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
-#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
-#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
-#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
-#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
-#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
-#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
-#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
-#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
-#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
-#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
-#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
-#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
-#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
-#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
-#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
-#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
-#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
-#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
-
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
-
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
-#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
-#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */
-#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */
-#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
-#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
-#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
-#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
-
-/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */
-
-#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */
-
-#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */
-
-/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for I2C_CR1 register ********************/
-#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
-#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
-#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
-#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
-#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
-#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
-#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
-#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
-#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
-
-/******************* Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
-
-#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
-#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
-
-/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
-
-#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
-#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
-#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
-#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
-
-/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
-
-/******************** Bit definition for I2C_DR register ********************/
-#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
-
-/******************* Bit definition for I2C_SR1 register ********************/
-#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
-#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
-#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
-
-/******************* Bit definition for I2C_SR2 register ********************/
-#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
-#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
-#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
-
-/******************* Bit definition for I2C_CCR register ********************/
-#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
-
-/****************** Bit definition for I2C_TRISE register *******************/
-#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for USART_SR register *******************/
-#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
-#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
-#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
-#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
-#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
-#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
-#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
-#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
-#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
-#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
-
-/******************* Bit definition for USART_DR register *******************/
-#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
-#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
-#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
-#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
-#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
-#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
-#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
-#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
-#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
-#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
-#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
-#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
-#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
-
-#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
-#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
-#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
-#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
-#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
-#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
-#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
-#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
-
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
-
-/******************************************************************************/
-/* */
-/* Debug MCU */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */
-
-/******************************************************************************/
-/* */
-/* FLASH and Option Bytes Registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
-#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */
-#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */
-#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */
-
-#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */
-#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */
-
-/****************** Bit definition for FLASH_KEYR register ******************/
-#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
-
-/***************** Bit definition for FLASH_OPTKEYR register ****************/
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
-
-/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */
-#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */
-#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */
-#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */
-
-/******************* Bit definition for FLASH_CR register *******************/
-#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */
-#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */
-#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */
-#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */
-#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */
-#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */
-#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */
-#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
-#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */
-#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */
-
-/******************* Bit definition for FLASH_AR register *******************/
-#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
-
-/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */
-#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */
-
-#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */
-#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */
-#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
-#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */
-
-/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/****************** Bit definition for FLASH_RDP register *******************/
-#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
-#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
-
-/****************** Bit definition for FLASH_USER register ******************/
-#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
-#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
-
-/****************** Bit definition for FLASH_Data0 register *****************/
-#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
-#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
-
-/****************** Bit definition for FLASH_Data1 register *****************/
-#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
-#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
-
-/****************** Bit definition for FLASH_WRP0 register ******************/
-#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
-#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP1 register ******************/
-#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
-#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP2 register ******************/
-#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
-#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP3 register ******************/
-#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
-#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
-
-#ifdef STM32F10X_CL
-/******************************************************************************/
-/* Ethernet MAC Registers bits definitions */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
-#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
-#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
- #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
- #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
- #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
- #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
- #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
- #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
- #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
- #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
-#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
-#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
-#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
-#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
-#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
-#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
-#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
- a transmission attempt during retries after a collision: 0 =< r <2^k */
- #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
- #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
- #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
- #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
-#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
-#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
-#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
-#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
-#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
-#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
-#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
- #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
- #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
- #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
-#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
-#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
-#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
-#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
-#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
-#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
-#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
-#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
- #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
- #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
- #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
-#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
-
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
-#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
- #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
- #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
- #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
- #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
-#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
-#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
-#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
- Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
- Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
- Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
- Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
- Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
- RSVD - Filter1 Command - RSVD - Filter0 Command
- Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
- Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
- Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
-#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
-#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
-#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
-#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
-#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
-#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
- #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
- #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
- #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
- #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
- #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
- #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
-#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
-#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
-#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
- #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
- #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
- #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
- #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
- #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
- #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
-#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
-#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
- #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
- #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
- #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
- #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
- #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
- #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
-
-/******************************************************************************/
-/* Ethernet MMC Registers bits definition */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
-#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
-#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/* Ethernet PTP Registers bits definition */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
-#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
-
-/******************************************************************************/
-/* Ethernet DMA Registers bits definition */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
-#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
-#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
-#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
- #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
- #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
- #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
- #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
- #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
- #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
- #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
- #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
- #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
- #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
- #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
- #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
-#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
-#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
- #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
- #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
- #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
- #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
-#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
- #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
- #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
- #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
- #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
- #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
- #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
- #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
- #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
- #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
- #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
- #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
- #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
-#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
-#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
-#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
-#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
- /* combination with EBS[2:0] for GetFlagStatus function */
- #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
- #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
- #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
- #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
- #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
- #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
- #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
- #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
- #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
- #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
- #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
- #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
- #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
- #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
- #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
-#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
-#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
-#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
-#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
-#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
-#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
-#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
-#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
-#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
-#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
-#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
-#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
- #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
- #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
- #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
- #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
- #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
- #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
- #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
- #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
-#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
- #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
- #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
- #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
- #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
-#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
-#endif /* STM32F10X_CL */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-#ifdef USE_STDPERIPH_DRIVER
- #include "stm32f10x_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
- * @{
- */
-
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_H */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/platform.mk
deleted file mode 100644
index d7a1d29607..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/platform.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# List of all the STM32F30x platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F30x/stm32_dma.c \
- ${CHIBIOS}/os/hal/platforms/STM32F30x/hal_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F30x \
- ${CHIBIOS}/os/hal/platforms/STM32 \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/USBv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_dma.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_dma.c
deleted file mode 100644
index 2ef1329a38..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_dma.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F30x/stm32_dma.c
- * @brief DMA helper driver code.
- *
- * @addtogroup STM32F30x_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- * shared resource, this driver allows to allocate and free DMA
- * streams at runtime in order to allow all the other device
- * drivers to coordinate the access to the resource.
- * @note The DMA ISR handlers are all declared into this module because
- * sharing, the various device drivers can associate a callback to
- * ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
- has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/**
- * @brief Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK 0x0000007F
-
-/**
- * @brief Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK 0x00000F80
-
-/**
- * @brief Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE 0x00000000
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- * identifier and the involved physical registers.
- * @note Don't use this array directly, use the appropriate wrapper macros
- * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
- {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
- {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
- {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
- {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
- {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
- {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
- {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
- {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
- {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
- {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
- {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
- {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
-};
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief DMA ISR redirector type.
- */
-typedef struct {
- stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
- void *dma_param; /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector6C) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 0;
- if (dma_isr_redir[0].dma_func)
- dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector70) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 4;
- if (dma_isr_redir[1].dma_func)
- dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector74) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 8;
- if (dma_isr_redir[2].dma_func)
- dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 12;
- if (dma_isr_redir[3].dma_func)
- dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector7C) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 16;
- if (dma_isr_redir[4].dma_func)
- dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector80) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 20;
- if (dma_isr_redir[5].dma_func)
- dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector84) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 24;
- if (dma_isr_redir[6].dma_func)
- dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector120) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 0;
- if (dma_isr_redir[7].dma_func)
- dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector124) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 4;
- if (dma_isr_redir[8].dma_func)
- dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector128) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 8;
- if (dma_isr_redir[9].dma_func)
- dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector12C) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 12;
- if (dma_isr_redir[10].dma_func)
- dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector130) {
- uint32_t flags;
-
- CH_IRQ_PROLOGUE();
-
- flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 16;
- if (dma_isr_redir[11].dma_func)
- dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-
- CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
- int i;
-
- dma_streams_mask = 0;
- for (i = 0; i < STM32_DMA_STREAMS; i++) {
- _stm32_dma_streams[i].channel->CCR = 0;
- dma_isr_redir[i].dma_func = NULL;
- }
- DMA1->IFCR = 0xFFFFFFFF;
-#if STM32_HAS_DMA2
- DMA2->IFCR = 0xFFFFFFFF;
-#endif
-}
-
-/**
- * @brief Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- * The function also enables the IRQ vector associated to the stream
- * and initializes its priority.
- * @pre The stream must not be already in use or an error is returned.
- * @post The stream is allocated and the default ISR handler redirected
- * to the specified function.
- * @post The stream ISR vector is enabled and its priority configured.
- * @post The stream must be freed using @p dmaStreamRelease() before it can
- * be reused with another peripheral.
- * @post The stream is in its post-reset state.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] priority IRQ priority mask for the DMA stream
- * @param[in] func handling function pointer, can be @p NULL
- * @param[in] param a parameter to be passed to the handling function
- * @return The operation status.
- * @retval FALSE no error, stream taken.
- * @retval TRUE error, stream already taken.
- *
- * @special
- */
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param) {
-
- chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
-
- /* Checks if the stream is already taken.*/
- if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
- return TRUE;
-
- /* Marks the stream as allocated.*/
- dma_isr_redir[dmastp->selfindex].dma_func = func;
- dma_isr_redir[dmastp->selfindex].dma_param = param;
- dma_streams_mask |= (1 << dmastp->selfindex);
-
- /* Enabling DMA clocks required by the current streams set.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
- rccEnableDMA1(FALSE);
-#if STM32_HAS_DMA2
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
- rccEnableDMA2(FALSE);
-#endif
-
- /* Putting the stream in a safe state.*/
- dmaStreamDisable(dmastp);
- dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
- /* Enables the associated IRQ vector if a callback is defined.*/
- if (func != NULL)
- nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
-
- return FALSE;
-}
-
-/**
- * @brief Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- * Trying to release a unallocated stream is an illegal operation
- * and is trapped if assertions are enabled.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post The stream is again available.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
- chDbgCheck(dmastp != NULL, "dmaStreamRelease");
-
- /* Check if the streams is not taken.*/
- chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
- "dmaStreamRelease(), #1", "not allocated");
-
- /* Disables the associated IRQ vector.*/
- nvicDisableVector(dmastp->vector);
-
- /* Marks the stream as not allocated.*/
- dma_streams_mask &= ~(1 << dmastp->selfindex);
-
- /* Shutting down clocks that are no more required, if any.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
- rccDisableDMA1(FALSE);
-#if STM32_HAS_DMA2
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
- rccDisableDMA2(FALSE);
-#endif
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_registry.h
deleted file mode 100644
index 9c9e2d32e8..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_registry.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F30x/stm32_registry.h
- * @brief STM32F30x capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _STM32_REGISTRY_H_
-#define _STM32_REGISTRY_H_
-
-/*===========================================================================*/
-/* Platform capabilities. */
-/*===========================================================================*/
-
-/**
- * @name STM32F30x capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 TRUE
-#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC3 TRUE
-#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_ADC3_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC4 TRUE
-#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC4_DMA_CHN 0x00000000
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_SDADC1_DMA_MSK 0
-#define STM32_SDADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_SDADC2_DMA_MSK 0
-#define STM32_SDADC2_DMA_CHN 0x00000000
-
-#define STM32_HAS_SDADC3 FALSE
-#define STM32_SDADC3_DMA_MSK 0
-#define STM32_SDADC3_DMA_CHN 0x00000000
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_CAN_MAX_FILTERS 14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 34
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOH FALSE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_I2C3_RX_DMA_MSK 0
-#define STM32_I2C3_RX_DMA_CHN 0x00000000
-#define STM32_I2C3_TX_DMA_MSK 0
-#define STM32_I2C3_TX_DMA_CHN 0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_IS_CALENDAR TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 FALSE
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 TRUE
-#define STM32_HAS_TIM5 FALSE
-#define STM32_HAS_TIM6 TRUE
-#define STM32_HAS_TIM7 TRUE
-#define STM32_HAS_TIM8 TRUE
-#define STM32_HAS_TIM9 FALSE
-#define STM32_HAS_TIM10 FALSE
-#define STM32_HAS_TIM11 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 TRUE
-#define STM32_HAS_TIM16 TRUE
-#define STM32_HAS_TIM17 TRUE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB TRUE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-
-#endif /* _STM32_REGISTRY_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/ext_lld_isr.c
deleted file mode 100644
index 9b56f4ddb3..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/ext_lld_isr.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F4xx/ext_lld_isr.c
- * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief EXTI[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI0_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 0);
- EXTD1.config->channels[0].cb(&EXTD1, 0);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI1_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 1);
- EXTD1.config->channels[1].cb(&EXTD1, 1);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[2] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI2_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 2);
- EXTD1.config->channels[2].cb(&EXTD1, 2);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI3_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 3);
- EXTD1.config->channels[3].cb(&EXTD1, 3);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[4] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI4_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 4);
- EXTD1.config->channels[4].cb(&EXTD1, 4);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[5]...EXTI[9] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
- uint32_t pr;
-
- CH_IRQ_PROLOGUE();
-
- pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
- EXTI->PR = pr;
- if (pr & (1 << 5))
- EXTD1.config->channels[5].cb(&EXTD1, 5);
- if (pr & (1 << 6))
- EXTD1.config->channels[6].cb(&EXTD1, 6);
- if (pr & (1 << 7))
- EXTD1.config->channels[7].cb(&EXTD1, 7);
- if (pr & (1 << 8))
- EXTD1.config->channels[8].cb(&EXTD1, 8);
- if (pr & (1 << 9))
- EXTD1.config->channels[9].cb(&EXTD1, 9);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[10]...EXTI[15] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
- uint32_t pr;
-
- CH_IRQ_PROLOGUE();
-
- pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
- (1 << 15));
- EXTI->PR = pr;
- if (pr & (1 << 10))
- EXTD1.config->channels[10].cb(&EXTD1, 10);
- if (pr & (1 << 11))
- EXTD1.config->channels[11].cb(&EXTD1, 11);
- if (pr & (1 << 12))
- EXTD1.config->channels[12].cb(&EXTD1, 12);
- if (pr & (1 << 13))
- EXTD1.config->channels[13].cb(&EXTD1, 13);
- if (pr & (1 << 14))
- EXTD1.config->channels[14].cb(&EXTD1, 14);
- if (pr & (1 << 15))
- EXTD1.config->channels[15].cb(&EXTD1, 15);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[16] interrupt handler (PVD).
- *
- * @isr
- */
-CH_IRQ_HANDLER(PVD_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 16);
- EXTD1.config->channels[16].cb(&EXTD1, 16);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[17] interrupt handler (RTC).
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 17);
- EXTD1.config->channels[17].cb(&EXTD1, 17);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 18);
- EXTD1.config->channels[18].cb(&EXTD1, 18);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[19] interrupt handler (ETH_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 19);
- EXTD1.config->channels[19].cb(&EXTD1, 19);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(STM32F401xx)
-/**
- * @brief EXTI[20] interrupt handler (OTG_HS_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 20);
- EXTD1.config->channels[20].cb(&EXTD1, 20);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EXTI[21] interrupt handler (TAMPER_STAMP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 21);
- EXTD1.config->channels[21].cb(&EXTD1, 21);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* !defined(STM32F401xx) */
-
-/**
- * @brief EXTI[22] interrupt handler (RTC_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- EXTI->PR = (1 << 22);
- EXTD1.config->channels[22].cb(&EXTD1, 22);
-
- CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
- nvicEnableVector(EXTI0_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
- nvicEnableVector(EXTI1_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
- nvicEnableVector(EXTI2_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
- nvicEnableVector(EXTI3_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
- nvicEnableVector(EXTI4_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
- nvicEnableVector(EXTI9_5_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
- nvicEnableVector(EXTI15_10_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
- nvicEnableVector(PVD_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
- nvicEnableVector(RTC_Alarm_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
- nvicEnableVector(OTG_FS_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
-#if !defined(STM32F401xx)
- nvicEnableVector(ETH_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
- nvicEnableVector(OTG_HS_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
- nvicEnableVector(TAMP_STAMP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
-#endif /* !defined(STM32F401xx) */
- nvicEnableVector(RTC_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY));
-}
-
-/**
- * @brief Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
- nvicDisableVector(EXTI0_IRQn);
- nvicDisableVector(EXTI1_IRQn);
- nvicDisableVector(EXTI2_IRQn);
- nvicDisableVector(EXTI3_IRQn);
- nvicDisableVector(EXTI4_IRQn);
- nvicDisableVector(EXTI9_5_IRQn);
- nvicDisableVector(EXTI15_10_IRQn);
- nvicDisableVector(PVD_IRQn);
- nvicDisableVector(RTC_Alarm_IRQn);
- nvicDisableVector(OTG_FS_WKUP_IRQn);
-#if !defined(STM32F401xx)
- nvicDisableVector(ETH_WKUP_IRQn);
- nvicDisableVector(OTG_HS_WKUP_IRQn);
- nvicDisableVector(TAMP_STAMP_IRQn);
-#endif /* !defined(STM32F401xx) */
- nvicDisableVector(RTC_WKUP_IRQn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/platform.mk
deleted file mode 100644
index bb18745efe..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/platform.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# List of all the STM32F2xx/STM32F4xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
- ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \
- ${CHIBIOS}/os/hal/platforms/STM32 \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32f2xx.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32f2xx.h
deleted file mode 100644
index 3f1fa54cb6..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32f2xx.h
+++ /dev/null
@@ -1,6878 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 18-April-2011
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F2xx devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripheral�s drivers in application code(i.e.
- * code will be based on direct access to peripheral�s registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral�s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * © COPYRIGHT 2011 STMicroelectronics
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f2xx
- * @{
- */
-
-#ifndef __STM32F2xx_H
-#define __STM32F2xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32 device used in your
- application
- */
-
-#if !defined (STM32F2XX)
- #define STM32F2XX
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-#if !defined (STM32F2XX)
- #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)"
-#endif
-
-#if !defined (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
-#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-
-/**
- * @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0
- */
-#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\
- |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\
- |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\
- |(__STM32F2XX_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
- */
-#define __MPU_PRESENT 1 /*!< STM32F2XX provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * @brief STM32F2XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm3.h"
-/* CHIBIOS FIX */
-/* #include "system_stm32f2xx.h" */
-#include
-
-/** @addtogroup Exported_types
- * @{
- */
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef const int32_t sc32; /*!< Read Only */
-typedef const int16_t sc16; /*!< Read Only */
-typedef const int8_t sc8; /*!< Read Only */
-
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef __I int32_t vsc32; /*!< Read Only */
-typedef __I int16_t vsc16; /*!< Read Only */
-typedef __I int8_t vsc8; /*!< Read Only */
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef const uint32_t uc32; /*!< Read Only */
-typedef const uint16_t uc16; /*!< Read Only */
-typedef const uint8_t uc8; /*!< Read Only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef __I uint32_t vuc32; /*!< Read Only */
-typedef __I uint16_t vuc16; /*!< Read Only */
-typedef __I uint8_t vuc8; /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
- __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
- __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
- __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
- __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
- __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
- __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
- __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
- __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
- __IO uint32_t CDR; /*!< ADC common regular data register for dual
- AND triple modes, Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct
-{
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct
-{
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct
-{
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2; /*!< Reserved, 0x208 */
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3; /*!< Reserved, 0x210 */
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
- uint32_t RESERVED4; /*!< Reserved, 0x218 */
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
-} CAN_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
-} DAC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
- * @brief Ethernet MAC
- */
-
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACFFR;
- __IO uint32_t MACHTHR;
- __IO uint32_t MACHTLR;
- __IO uint32_t MACMIIAR;
- __IO uint32_t MACMIIDR;
- __IO uint32_t MACFCR;
- __IO uint32_t MACVLANTR; /* 8 */
- uint32_t RESERVED0[2];
- __IO uint32_t MACRWUFFR; /* 11 */
- __IO uint32_t MACPMTCSR;
- uint32_t RESERVED1[2];
- __IO uint32_t MACSR; /* 15 */
- __IO uint32_t MACIMR;
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR; /* 24 */
- uint32_t RESERVED2[40];
- __IO uint32_t MMCCR; /* 65 */
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR; /* 69 */
- uint32_t RESERVED3[14];
- __IO uint32_t MMCTGFSCCR; /* 84 */
- __IO uint32_t MMCTGFMSCCR;
- uint32_t RESERVED4[5];
- __IO uint32_t MMCTGFCR;
- uint32_t RESERVED5[10];
- __IO uint32_t MMCRFCECR;
- __IO uint32_t MMCRFAECR;
- uint32_t RESERVED6[10];
- __IO uint32_t MMCRGUFCR;
- uint32_t RESERVED7[334];
- __IO uint32_t PTPTSCR;
- __IO uint32_t PTPSSIR;
- __IO uint32_t PTPTSHR;
- __IO uint32_t PTPTSLR;
- __IO uint32_t PTPTSHUR;
- __IO uint32_t PTPTSLUR;
- __IO uint32_t PTPTSAR;
- __IO uint32_t PTPTTHR;
- __IO uint32_t PTPTTLR;
- __IO uint32_t RESERVED8;
- __IO uint32_t PTPTSSR; /* added for STM32F2xx */
- uint32_t RESERVED9[565];
- __IO uint32_t DMABMR;
- __IO uint32_t DMATPDR;
- __IO uint32_t DMARPDR;
- __IO uint32_t DMARDLAR;
- __IO uint32_t DMATDLAR;
- __IO uint32_t DMASR;
- __IO uint32_t DMAOMR;
- __IO uint32_t DMAIER;
- __IO uint32_t DMAMFBOCR;
- __IO uint32_t DMARSWTR; /* added for STM32F2xx */
- uint32_t RESERVED10[8];
- __IO uint32_t DMACHTDR;
- __IO uint32_t DMACHRDR;
- __IO uint32_t DMACHTBAR;
- __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
- __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */
-} FLASH_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FSMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED0; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FSMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */
-} GPIO_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
- __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
- uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< Reserved, 0x1C */
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
- uint32_t RESERVED2; /*!< Reserved, 0x3C */
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
- uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, 0x5C */
- __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
- uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
- __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
- __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- uint32_t RESERVED1; /*!< Reserved, 0x28 */
- uint32_t RESERVED2; /*!< Reserved, 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- uint32_t RESERVED3; /*!< Reserved, 0x38 */
- uint32_t RESERVED4; /*!< Reserved, 0x3C */
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- uint32_t RESERVED5; /*!< Reserved, 0x44 */
- uint32_t RESERVED6; /*!< Reserved, 0x48 */
- uint32_t RESERVED7; /*!< Reserved, 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
-} RTC_TypeDef;
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
- uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
- __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} SPI_TypeDef;
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- uint16_t RESERVED9; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED10; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- uint16_t RESERVED11; /*!< Reserved, 0x46 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED12; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint16_t RESERVED13; /*!< Reserved, 0x4E */
- __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
- uint16_t RESERVED14; /*!< Reserved, 0x52 */
-} TIM_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
-} USART_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief Crypto Processor
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
- __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
- __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
- __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
- __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
- __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
- __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
- __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
- __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
- __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
- __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
- __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
- __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
- __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
- __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
- __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
- __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
- __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
-} CRYP_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
- __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
- __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
- __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
- __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
- __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
- uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
- __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */
-} HASH_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
-#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000)
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
-#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0xE0042000)
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH ((ETH_TypeDef *) ETH_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH ((HASH_TypeDef *) HASH_BASE)
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint8_t)0x01) /*!© COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx
- * @{
- */
-
-#ifndef __STM32F4xx_H
-#define __STM32F4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32 device used in your
- application
- */
-
-#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
- !defined(STM32F411xE) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
- /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,
- STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE,
- STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
-
- /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,
- STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
-
- /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,
- STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI,
- STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
- STM32F439IG and STM32F439II Devices */
-
- /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC
- STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */
-
- /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */
-
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
-
- /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC
- and STM32F446ZE Devices */
-
- /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG,
- STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */
-#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F446xx && STM32F469_479xx */
-
-/* Old STM32F40XX definition, maintained for legacy purpose */
-#ifdef STM32F40XX
- #define STM32F40_41xxx
-#endif /* STM32F40XX */
-
-/* Old STM32F427X definition, maintained for legacy purpose */
-#ifdef STM32F427X
- #define STM32F427_437xx
-#endif /* STM32F427X */
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
- !defined(STM32F411xE) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
- #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
-#endif
-
-#if !defined (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_STDPERIPH_DRIVER */
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \
- defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
- #if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
- #endif /* HSE_VALUE */
-#elif defined(STM32F446xx)
- #if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
- #endif /* HSE_VALUE */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief STM32F4XX Standard Peripherals Library version number V1.6.0
- */
-#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
- |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
- |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
- |(__STM32F4XX_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
- */
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum IRQn
-{
-/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
-
-#if defined(STM32F40_41xxx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81 /*!< FPU global interrupt */
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
-#endif /* STM32F427_437xx */
-
-#if defined(STM32F429_439xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
-#endif /* STM32F429_439xx */
-
-#if defined(STM32F410xx)
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- RNG_IRQn = 80, /*!< RNG global Interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
- FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
- LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
-#endif /* STM32F410xx */
-
-#if defined(STM32F401xx) || defined(STM32F411xE)
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
-#if defined(STM32F401xx)
- SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
-#endif /* STM32F411xE */
-#if defined(STM32F411xE)
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
-#endif /* STM32F411xE */
-#endif /* STM32F401xx || STM32F411xE */
-
-#if defined(STM32F469_479xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
- QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
- DSI_IRQn = 92 /*!< DSI global Interrupt */
-#endif /* STM32F469_479xx */
-
-#if defined(STM32F446xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
- QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
- CEC_IRQn = 93, /*!< QuadSPI global Interrupt */
- SPDIF_RX_IRQn = 94, /*!< QuadSPI global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C Event Interrupt */
- FMPI2C1_ER_IRQn = 96 /*!< FMPCI2C Error Interrupt */
-#endif /* STM32F446xx */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include
-
-/** @addtogroup Exported_types
- * @{
- */
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef const int32_t sc32; /*!< Read Only */
-typedef const int16_t sc16; /*!< Read Only */
-typedef const int8_t sc8; /*!< Read Only */
-
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef __I int32_t vsc32; /*!< Read Only */
-typedef __I int16_t vsc16; /*!< Read Only */
-typedef __I int8_t vsc8; /*!< Read Only */
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef const uint32_t uc32; /*!< Read Only */
-typedef const uint16_t uc16; /*!< Read Only */
-typedef const uint8_t uc8; /*!< Read Only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef __I uint32_t vuc32; /*!< Read Only */
-typedef __I uint16_t vuc16; /*!< Read Only */
-typedef __I uint8_t vuc8; /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
- __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
- __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
- __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
- __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
- __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
- __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
- __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
- __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
- __IO uint32_t CDR; /*!< ADC common regular data register for dual
- AND triple modes, Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct
-{
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct
-{
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct
-{
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2; /*!< Reserved, 0x208 */
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3; /*!< Reserved, 0x210 */
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
- uint32_t RESERVED4; /*!< Reserved, 0x218 */
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
-} CAN_TypeDef;
-
-#if defined(STM32F446xx)
-/**
- * @brief Consumer Electronics Control
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-#endif /* STM32F446xx */
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
-} DAC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
- * @brief DMA2D Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
- __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
- __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
- __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
- __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
- __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
- __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
- __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
- __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
- __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
- __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
- __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
- __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
- __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
- __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
- __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
- __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
- __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
- __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
- __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
- uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
- __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
- __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-#if defined(STM32F469_479xx)
-/**
- * @brief DSI Controller
- */
-
-typedef struct
-{
- __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
- __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
- __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
- __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
- __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
- __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
- __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
- uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
- __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
- __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
- __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
- __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
- __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
- __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
- __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
- __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
- __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
- __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
- __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
- __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
- __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
- __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
- __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
- __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
- __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
- __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
- __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
- __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
- __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
- __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
- __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
- __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
- __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
- __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
- __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
- __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
- __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
- __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
- __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
- uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
- __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
- uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
- __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
- uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
- __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
- __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
- uint32_t RESERVED5; /*!< Reserved, 0x114 */
- __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
- uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
- __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
- __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
- __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
- __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
- __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
- __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
- __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
- __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
- __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
- __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
- __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
- uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
- __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
- uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
- __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
- __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
- __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
- __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
- __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
- uint32_t RESERVED9; /*!< Reserved, 0x414 */
- __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
- uint32_t RESERVED10; /*!< Reserved, 0x42C */
- __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
-} DSI_TypeDef;
-#endif /* STM32F469_479xx */
-
-/**
- * @brief Ethernet MAC
- */
-
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACFFR;
- __IO uint32_t MACHTHR;
- __IO uint32_t MACHTLR;
- __IO uint32_t MACMIIAR;
- __IO uint32_t MACMIIDR;
- __IO uint32_t MACFCR;
- __IO uint32_t MACVLANTR; /* 8 */
- uint32_t RESERVED0[2];
- __IO uint32_t MACRWUFFR; /* 11 */
- __IO uint32_t MACPMTCSR;
- uint32_t RESERVED1[2];
- __IO uint32_t MACSR; /* 15 */
- __IO uint32_t MACIMR;
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR; /* 24 */
- uint32_t RESERVED2[40];
- __IO uint32_t MMCCR; /* 65 */
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR; /* 69 */
- uint32_t RESERVED3[14];
- __IO uint32_t MMCTGFSCCR; /* 84 */
- __IO uint32_t MMCTGFMSCCR;
- uint32_t RESERVED4[5];
- __IO uint32_t MMCTGFCR;
- uint32_t RESERVED5[10];
- __IO uint32_t MMCRFCECR;
- __IO uint32_t MMCRFAECR;
- uint32_t RESERVED6[10];
- __IO uint32_t MMCRGUFCR;
- uint32_t RESERVED7[334];
- __IO uint32_t PTPTSCR;
- __IO uint32_t PTPSSIR;
- __IO uint32_t PTPTSHR;
- __IO uint32_t PTPTSLR;
- __IO uint32_t PTPTSHUR;
- __IO uint32_t PTPTSLUR;
- __IO uint32_t PTPTSAR;
- __IO uint32_t PTPTTHR;
- __IO uint32_t PTPTTLR;
- __IO uint32_t RESERVED8;
- __IO uint32_t PTPTSSR;
- uint32_t RESERVED9[565];
- __IO uint32_t DMABMR;
- __IO uint32_t DMATPDR;
- __IO uint32_t DMARPDR;
- __IO uint32_t DMARDLAR;
- __IO uint32_t DMATDLAR;
- __IO uint32_t DMASR;
- __IO uint32_t DMAOMR;
- __IO uint32_t DMAIER;
- __IO uint32_t DMAMFBOCR;
- __IO uint32_t DMARSWTR;
- uint32_t RESERVED10[8];
- __IO uint32_t DMACHTDR;
- __IO uint32_t DMACHRDR;
- __IO uint32_t DMACHTBAR;
- __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
- __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
- __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-#if defined(STM32F40_41xxx)
-/**
- * @brief Flexible Static Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FSMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED0; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FSMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef;
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief Flexible Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED0; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
-} FMC_Bank4_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank5_6
- */
-
-typedef struct
-{
- __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
- __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
- __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
- __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
- __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
-} FMC_Bank5_6_TypeDef;
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
- __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-#if defined (STM32F410xx)
- uint32_t RESERVED; /*!< Reserved, 0x18 */
- uint32_t CFGR2; /*!< Reserved, 0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
- __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
-#else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
- uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
-#endif /* STM32F410xx */
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
- uint16_t RESERVED9; /*!< Reserved, 0x26 */
-} I2C_TypeDef;
-
-#if defined(STM32F410xx) || defined(STM32F446xx)
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
-}FMPI2C_TypeDef;
-#endif /* STM32F410xx || STM32F446xx */
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/**
- * @brief LCD-TFT Display Controller
- */
-
-typedef struct
-{
- uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
- __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
- __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
- __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
- __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
- __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
- __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
- uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
- __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
- uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
- __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
- __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
- __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
- __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
- __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
- __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
- * @brief LCD-TFT Display layer x Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
- __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
- __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
- __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
- __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
- __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
- __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
- __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
- uint32_t RESERVED0[2]; /*!< Reserved */
- __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
- __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
- __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
- uint32_t RESERVED1[3]; /*!< Reserved */
- __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< Reserved, 0x1C */
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
- uint32_t RESERVED2; /*!< Reserved, 0x3C */
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
- uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, 0x5C */
- __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
- uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
- __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
- __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
- __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
- __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
- __IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F446xx devices */
- __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F446xx devices and STM32F410xx devices */
-
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
- uint32_t RESERVED7; /*!< Reserved, 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/**
- * @brief Serial Audio Interface
- */
-
-typedef struct
-{
- __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
- __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
- __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
- __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
- __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
- __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
- uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
- __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} SPI_TypeDef;
-
-#if defined(STM32F446xx)
-/**
- * @brief SPDIFRX Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- uint16_t RESERVED0; /*!< Reserved, 0x06 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- uint16_t RESERVED1; /*!< Reserved, 0x0E */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint16_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIFRX_TypeDef;
-#endif /* STM32F446xx */
-
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief QUAD Serial Peripheral Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
- __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
- __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
- __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
- __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
- __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
- __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
- __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
- __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
- __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
-} QUADSPI_TypeDef;
-#endif /* STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F446xx)
-/**
- * @brief SPDIF-RX Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- uint16_t RESERVED0; /*!< Reserved, 0x06 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- uint16_t RESERVED1; /*!< Reserved, 0x0E */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint16_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIF_TypeDef;
-#endif /* STM32F446xx */
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- uint16_t RESERVED9; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED10; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- uint16_t RESERVED11; /*!< Reserved, 0x46 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED12; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint16_t RESERVED13; /*!< Reserved, 0x4E */
- __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
- uint16_t RESERVED14; /*!< Reserved, 0x52 */
-} TIM_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
-} USART_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief Crypto Processor
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
- __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
- __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
- __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
- __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
- __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
- __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
- __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
- __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
- __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
- __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
- __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
- __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
- __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
- __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
- __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
- __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
- __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
- __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
- __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
- __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
- __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
- __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
- __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
- __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
- __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
- __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
- __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
- __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
- __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
- __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
- __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
- __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
- __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
- __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
- __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
- __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
- __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
- __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
- uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
- __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/**
- * @brief HASH_DIGEST
- */
-
-typedef struct
-{
- __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
-} HASH_DIGEST_TypeDef;
-
-/**
- * @brief RNG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-#if defined(STM32F410xx)
-/**
- * @brief LPTIMER
- */
-typedef struct
-{
- __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
- __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
- __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
- __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
- __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
- __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
- __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
-} LPTIM_TypeDef;
-#endif /* STM32F410xx */
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
-#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
-#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-
-#if defined(STM32F40_41xxx)
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
-#endif /* STM32F446xx || STM32F469_479xx */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
-
-/* Legacy defines */
-#define SRAM_BASE SRAM1_BASE
-#define SRAM_BB_BASE SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#if defined(STM32F410xx)
-#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
-#endif /* STM32F410xx */
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#if defined(STM32F446xx)
-#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
-#endif /* STM32F446xx */
-#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
-#if defined(STM32F410xx) || defined(STM32F446xx)
-#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
-#endif /* STM32F410xx || STM32F446xx */
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
-#if defined(STM32F446xx)
-#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
-#endif /* STM32F446xx */
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
-#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
-#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
-#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
-#if defined(STM32F446xx)
-#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
-#endif /* STM32F446xx */
-#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
-#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
-#if defined(STM32F469_479xx)
-#define DSI_BASE (APB2PERIPH_BASE + 0x6C00)
-#endif /* STM32F469_479xx */
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
-#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
-#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)
-#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
-#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
-#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
-
-#if defined(STM32F40_41xxx)
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
-#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
-#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0xE0042000)
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#endif /* STM32F446xx || STM32F469_479xx */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#if defined(STM32F446xx)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#endif /* STM32F446xx */
-#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#if defined(STM32F410xx) || defined(STM32F446xx)
-#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#endif /* STM32F410xx || STM32F446xx */
-#if defined(STM32F410xx)
-#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
-#endif /* STM32F410xx */
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
-#if defined(STM32F446xx)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#endif /* STM32F446xx */
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define UART7 ((USART_TypeDef *) UART7_BASE)
-#define UART8 ((USART_TypeDef *) UART8_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#if defined(STM32F446xx)
-#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#endif /* STM32F446xx */
-#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#if defined(STM32F469_479xx)
-#define DSI ((DSI_TypeDef *)DSI_BASE)
-#endif /* STM32F469_479xx */
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH ((ETH_TypeDef *) ETH_BASE)
-#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-
-#if defined(STM32F40_41xxx)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
-#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
-#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint8_t)0x01) /*!CR & ADC_CR_ADSTART) {
+ adc->CR |= ADC_CR_ADSTP;
+ while (adc->CR & ADC_CR_ADSTP)
+ ;
+ }
+}
+
+/**
+ * @brief ADC DMA ISR service routine.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+ /* DMA errors handling.*/
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ /* DMA, this could help only if the DMA tries to access an unmapped
+ address space or violates alignment rules.*/
+ _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+ }
+ else {
+ /* It is possible that the conversion group has already be reset by the
+ ADC error handler, in this case this interrupt is spurious.*/
+ if (adcp->grpp != NULL) {
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _adc_isr_full_code(adcp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _adc_isr_half_code(adcp);
+ }
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (STM32_ADC_USE_ADC1 && (STM32_ADC1_IRQ_SHARED_WITH_EXTI == FALSE)) || \
+ defined(__DOXYGEN__)
+#if !defined(STM32_ADC1_HANDLER)
+#error "STM32_ADC1_HANDLER not defined"
+#endif
+/**
+ * @brief ADC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ adc_lld_serve_interrupt(&ADCD1);
+
+#if defined(STM32_ADC_ADC1_IRQ_HOOK)
+ STM32_ADC_ADC1_IRQ_HOOK
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.adc = ADC1;
+ ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
+ ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+
+#if STM32_ADC1_IRQ_SHARED_WITH_EXTI == FALSE
+ /* The shared vector is initialized on driver initialization and never
+ disabled.*/
+ nvicEnableVector(12, STM32_ADC_ADC1_IRQ_PRIORITY);
+#endif
+#endif
+
+ /* Calibration procedure.*/
+ rccEnableADC1(FALSE);
+
+ /* CCR setup.*/
+#if STM32_ADC_SUPPORTS_PRESCALER
+ ADC->CCR = STM32_ADC_PRESC << 18;
+#else
+ ADC->CCR = 0;
+#endif
+
+ osalDbgAssert(ADC1->CR == 0, "invalid register state");
+ ADC1->CR |= ADC_CR_ADCAL;
+ osalDbgAssert(ADC1->CR != 0, "invalid register state");
+ while (ADC1->CR & ADC_CR_ADCAL)
+ ;
+ rccDisableADC1(FALSE);
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+ /* If in stopped state then enables the ADC and DMA clocks.*/
+ if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+ if (&ADCD1 == adcp) {
+ bool b;
+ b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
+ dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+ rccEnableADC1(FALSE);
+
+ /* Clock settings.*/
+ adcp->adc->CFGR2 = STM32_ADC_ADC1_CKMODE;
+ }
+#endif /* STM32_ADC_USE_ADC1 */
+
+ /* ADC initial setup, starting the analog part here in order to reduce
+ the latency when starting a conversion.*/
+ adcp->adc->CR = ADC_CR_ADEN;
+ while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
+ ;
+ }
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+ /* If in ready state then disables the ADC clock and analog part.*/
+ if (adcp->state == ADC_READY) {
+
+ dmaStreamRelease(adcp->dmastp);
+
+ /* Restoring CCR default.*/
+#if STM32_ADC_SUPPORTS_PRESCALER
+ ADC->CCR = STM32_ADC_PRESC << 18;
+#else
+ ADC->CCR = 0;
+#endif
+
+ /* Disabling ADC.*/
+ if (adcp->adc->CR & ADC_CR_ADEN) {
+ adc_lld_stop_adc(adcp->adc);
+ adcp->adc->CR |= ADC_CR_ADDIS;
+ while (adcp->adc->CR & ADC_CR_ADDIS)
+ ;
+ }
+
+#if STM32_ADC_USE_ADC1
+ if (&ADCD1 == adcp)
+ rccDisableADC1(FALSE);
+#endif
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+ uint32_t mode, cfgr1;
+ const ADCConversionGroup *grpp = adcp->grpp;
+
+ /* DMA setup.*/
+ mode = adcp->dmamode;
+ cfgr1 = grpp->cfgr1 | ADC_CFGR1_DMAEN;
+ if (grpp->circular) {
+ mode |= STM32_DMA_CR_CIRC;
+ cfgr1 |= ADC_CFGR1_DMACFG;
+ if (adcp->depth > 1) {
+ /* If circular buffer depth > 1, then the half transfer interrupt
+ is enabled in order to allow streaming processing.*/
+ mode |= STM32_DMA_CR_HTIE;
+ }
+ }
+ dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+ dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+ (uint32_t)adcp->depth);
+ dmaStreamSetMode(adcp->dmastp, mode);
+ dmaStreamEnable(adcp->dmastp);
+
+ /* ADC setup, if it is defined a callback for the analog watch dog then it
+ is enabled.*/
+ adcp->adc->ISR = adcp->adc->ISR;
+ adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWDIE;
+ adcp->adc->TR = grpp->tr;
+ adcp->adc->SMPR = grpp->smpr;
+ adcp->adc->CHSELR = grpp->chselr;
+
+ /* ADC configuration and start.*/
+ adcp->adc->CFGR1 = cfgr1;
+#if STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE
+ {
+ uint32_t cfgr2 = adcp->adc->CFGR2 & STM32_ADC_CKMODE_MASK;
+ adcp->adc->CFGR2 = cfgr2 | grpp->cfgr2;
+ }
+#endif
+
+ /* ADC conversion start.*/
+ adcp->adc->CR |= ADC_CR_ADSTART;
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+ dmaStreamDisable(adcp->dmastp);
+ adc_lld_stop_adc(adcp->adc);
+}
+
+/**
+ * @brief ISR code.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_serve_interrupt(ADCDriver *adcp) {
+ uint32_t isr;
+
+ isr = adcp->adc->ISR;
+ adcp->adc->ISR = isr;
+
+ /* It could be a spurious interrupt caused by overflows after DMA disabling,
+ just ignore it in this case.*/
+ if (adcp->grpp != NULL) {
+ /* Note, an overflow may occur after the conversion ended before the driver
+ is able to stop the ADC, this is why the DMA channel is checked too.*/
+ if ((isr & ADC_ISR_OVR) &&
+ (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
+ /* ADC overflow condition, this could happen only if the DMA is unable
+ to read data fast enough.*/
+ _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
+ }
+ if (isr & ADC_ISR_AWD) {
+ /* Analog watchdog error.*/
+ _adc_isr_error_code(adcp, ADC_ERR_AWD);
+ }
+ }
+}
+
+/**
+ * @brief Enables the VREFEN bit.
+ * @details The VREFEN bit is required in order to sample the VREF channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32EnableVREF(void) {
+
+ ADC->CCR |= ADC_CCR_VREFEN;
+}
+
+/**
+ * @brief Disables the VREFEN bit.
+ * @details The VREFEN bit is required in order to sample the VREF channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32DisableVREF(void) {
+
+ ADC->CCR &= ~ADC_CCR_VREFEN;
+}
+
+/**
+ * @brief Enables the TSEN bit.
+ * @details The TSEN bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32EnableTS(void) {
+
+ ADC->CCR |= ADC_CCR_TSEN;
+}
+
+/**
+ * @brief Disables the TSEN bit.
+ * @details The TSEN bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32DisableTS(void) {
+
+ ADC->CCR &= ~ADC_CCR_TSEN;
+}
+
+#ifdef STM32F0XX
+/**
+ * @brief Enables the VBATEN bit.
+ * @details The VBATEN bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32EnableVBAT(void) {
+
+ ADC->CCR |= ADC_CCR_VBATEN;
+}
+
+/**
+ * @brief Disables the VBATEN bit.
+ * @details The VBATEN bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32DisableVBAT(void) {
+
+ ADC->CCR &= ~ADC_CCR_VBATEN;
+}
+#endif /* STM32F0XX */
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h
new file mode 100644
index 0000000000..657fa5643f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h
@@ -0,0 +1,449 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ADCv1/hal_adc_lld.h
+ * @brief STM32 ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Sampling rates
+ * @{
+ */
+#define ADC_SMPR_SMP_1P5 0U /**< @brief 14 cycles conversion time */
+#define ADC_SMPR_SMP_7P5 1U /**< @brief 21 cycles conversion time. */
+#define ADC_SMPR_SMP_13P5 2U /**< @brief 28 cycles conversion time. */
+#define ADC_SMPR_SMP_28P5 3U /**< @brief 41 cycles conversion time. */
+#define ADC_SMPR_SMP_41P5 4U /**< @brief 54 cycles conversion time. */
+#define ADC_SMPR_SMP_55P5 5U /**< @brief 68 cycles conversion time. */
+#define ADC_SMPR_SMP_71P5 6U /**< @brief 84 cycles conversion time. */
+#define ADC_SMPR_SMP_239P5 7U /**< @brief 252 cycles conversion time. */
+/** @} */
+
+/**
+ * @name CFGR1 register configuration helpers
+ * @{
+ */
+#define ADC_CFGR1_RES_12BIT (0U << 3U)
+#define ADC_CFGR1_RES_10BIT (1U << 3U)
+#define ADC_CFGR1_RES_8BIT (2U << 3U)
+#define ADC_CFGR1_RES_6BIT (3U << 3U)
+
+#define ADC_CFGR1_EXTSEL_MASK (15U << 6U)
+#define ADC_CFGR1_EXTSEL_SRC(n) ((n) << 6U)
+
+#define ADC_CFGR1_EXTEN_MASK (3U << 10U)
+#define ADC_CFGR1_EXTEN_DISABLED (0U << 10U)
+#define ADC_CFGR1_EXTEN_RISING (1U << 10U)
+#define ADC_CFGR1_EXTEN_FALLING (2U << 10U)
+#define ADC_CFGR1_EXTEN_BOTH (3U << 10U)
+/** @} */
+
+/**
+ * @name CFGR2 register configuration helpers
+ * @{
+ */
+#define STM32_ADC_CKMODE_MASK (3U << 30U)
+#define STM32_ADC_CKMODE_ADCCLK (0U << 30U)
+#define STM32_ADC_CKMODE_PCLK_DIV2 (1U << 30U)
+#define STM32_ADC_CKMODE_PCLK_DIV4 (2U << 30U)
+#define STM32_ADC_CKMODE_PCLK (3U << 30U)
+
+#if (STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE) || defined(__DOXYGEN__)
+#define ADC_CFGR2_OVSR_MASK (7U << 2U)
+#define ADC_CFGR2_OVSR_2X (0U << 2U)
+#define ADC_CFGR2_OVSR_4X (1U << 2U)
+#define ADC_CFGR2_OVSR_8X (2U << 2U)
+#define ADC_CFGR2_OVSR_16X (3U << 2U)
+#define ADC_CFGR2_OVSR_32X (4U << 2U)
+#define ADC_CFGR2_OVSR_64X (5U << 2U)
+#define ADC_CFGR2_OVSR_128X (6U << 2U)
+#define ADC_CFGR2_OVSR_256X (7U << 2U)
+
+#define ADC_CFGR2_OVSS_MASK (15 << 5U)
+#define ADC_CFGR2_OVSS_SHIFT(n) ((n) << 5U)
+#endif
+/** @} */
+
+/**
+ * @name Threashold register initializer
+ * @{
+ */
+#define ADC_TR(low, high) (((uint32_t)(high) << 16U) | \
+ (uint32_t)(low))
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1 FALSE
+#endif
+
+/**
+ * @brief ADC1 clock source selection.
+ */
+#if !defined(STM32_ADC_ADC1_CKMODE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
+#endif
+
+/**
+ * @brief ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief ADC interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief ADC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
+#endif
+
+#if (STM32_ADC_SUPPORTS_PRESCALER == TRUE) || defined(__DOXYGEN__)
+/*
+ * @brief ADC prescaler setting.
+ * @note This setting has effect only in asynchronous clock mode (the
+ * default, @p STM32_ADC_CKMODE_ADCCLK).
+ */
+#if !defined(STM32_ADC_PRESCALER_VALUE) || defined(__DOXYGEN__)
+#define STM32_ADC_PRESCALER_VALUE 1
+#endif
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if STM32_ADC1_IRQ_SHARED_WITH_EXTI == FALSE
+#if STM32_ADC_USE_ADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_SUPPORTS_PRESCALER == TRUE
+#if STM32_ADC_PRESCALER_VALUE == 1
+#define STM32_ADC_PRESC 0U
+#elif STM32_ADC_PRESCALER_VALUE == 2
+#define STM32_ADC_PRESC 1U
+#elif STM32_ADC_PRESCALER_VALUE == 4
+#define STM32_ADC_PRESC 2U
+#elif STM32_ADC_PRESCALER_VALUE == 6
+#define STM32_ADC_PRESC 3U
+#elif STM32_ADC_PRESCALER_VALUE == 8
+#define STM32_ADC_PRESC 4U
+#elif STM32_ADC_PRESCALER_VALUE == 10
+#define STM32_ADC_PRESC 5U
+#elif STM32_ADC_PRESCALER_VALUE == 12
+#define STM32_ADC_PRESC 6U
+#elif STM32_ADC_PRESCALER_VALUE == 16
+#define STM32_ADC_PRESC 7U
+#elif STM32_ADC_PRESCALER_VALUE == 32
+#define STM32_ADC_PRESC 8U
+#elif STM32_ADC_PRESCALER_VALUE == 64
+#define STM32_ADC_PRESC 9U
+#elif STM32_ADC_PRESCALER_VALUE == 128
+#define STM32_ADC_PRESC 10U
+#elif STM32_ADC_PRESCALER_VALUE == 256
+#define STM32_ADC_PRESC 11U
+#else
+#error "Invalid value assigned to STM32_ADC_PRESCALER_VALUE"
+#endif
+#endif
+
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM)
+#error "ADC DMA stream not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_ADC_USE_ADC1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
+#error "invalid DMA stream associated to ADC1"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
+ ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ * @note The use of this configuration structure requires knowledge of
+ * STM32 ADC cell registers interface, please refer to the STM32
+ * reference manual for details.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief ADC CFGR1 register initialization data.
+ * @note The bits DMAEN and DMACFG are enforced internally
+ * to the driver, keep them to zero.
+ * @note The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be
+ * specified in continuous more or if the buffer depth is
+ * greater than one.
+ */
+ uint32_t cfgr1;
+#if (STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief ADC CFGR2 register initialization data.
+ * @note CKMODE bits must not be specified in this field and left to
+ * zero.
+ */
+ uint32_t cfgr2;
+#endif
+ /**
+ * @brief ADC TR register initialization data.
+ */
+ uint32_t tr;
+ /**
+ * @brief ADC SMPR register initialization data.
+ */
+ uint32_t smpr;
+ /**
+ * @brief ADC CHSELR register initialization data.
+ * @details The number of bits at logic level one in this register must
+ * be equal to the number in the @p num_channels field.
+ */
+ uint32_t chselr;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ uint32_t dummy;
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig *config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t *samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the ADCx registers block.
+ */
+ ADC_TypeDef *adc;
+ /**
+ * @brief Pointer to associated DMA channel.
+ */
+ const stm32_dma_stream_t *dmastp;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the value of the ADC CCR register.
+ * @details Use this function in order to enable or disable the internal
+ * analog sources. See the documentation in the STM32 Reference
+ * Manual.
+ * @note PRESC bits must not be specified and left to zero.
+ */
+#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void adc_lld_init(void);
+ void adc_lld_start(ADCDriver *adcp);
+ void adc_lld_stop(ADCDriver *adcp);
+ void adc_lld_start_conversion(ADCDriver *adcp);
+ void adc_lld_stop_conversion(ADCDriver *adcp);
+ void adc_lld_serve_interrupt(ADCDriver *adcp);
+ void adcSTM32EnableVREF(void);
+ void adcSTM32DisableVREF(void);
+ void adcSTM32EnableTS(void);
+ void adcSTM32DisableTS(void);
+#ifdef STM32F0XX
+ void adcSTM32EnableVBAT(void);
+ void adcSTM32DisableVBAT(void);
+#endif /* STM32F0XX */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* HAL_ADC_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv1/notes.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv1/notes.txt
new file mode 100644
index 0000000000..ec7103c3e5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv1/notes.txt
@@ -0,0 +1,16 @@
+STM32 ADCv1 driver.
+
+Driver capability:
+
+- Supports the STM32 "simple" ADC, the one found on small devices (F0, L0).
+
+The file registry must export:
+
+STM32_HAS_ADC1 - ADC1 presence flag.
+STM32_ADC_SUPPORTS_PRESCALER - Support of CCR PRESC field.
+STM32_ADC_SUPPORTS_OVERSAMPLING - Support of oversampling-related fields.
+STM32_ADC1_IRQ_SHARED_WITH_EXTI - TRUE if the IRQ is shared with EXTI.
+STM32_ADC1_HANDLER - IRQ vector name.
+STM32_ADC1_NUMBER - IRQ vector number.
+STM32_ADC1_DMA_MSK - Mask of the compatible DMA channels.
+STM32_ADC1_DMA_CHN - Mask of the channels mapping.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/driver.mk
new file mode 100644
index 0000000000..c3fa0ada15
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/adc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
similarity index 90%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/adc_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
index 11bdefb3f0..0d770e54ae 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32F4xx/adc_lld.c
- * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver source.
+ * @file ADCv2/hal_adc_lld.c
+ * @brief STM32 ADC subsystem low level driver source.
*
* @addtogroup ADC
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_ADC || defined(__DOXYGEN__)
@@ -85,6 +84,7 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
/* It is possible that the conversion group has already be reset by the
ADC error handler, in this case this interrupt is spurious.*/
if (adcp->grpp != NULL) {
+
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_adc_isr_full_code(adcp);
@@ -108,10 +108,10 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
*
* @isr
*/
-CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_ADC_HANDLER) {
uint32_t sr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
#if STM32_ADC_USE_ADC1
sr = ADC1->SR;
@@ -125,6 +125,9 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
}
/* TODO: Add here analog watchdog handling.*/
+#if defined(STM32_ADC_ADC1_IRQ_HOOK)
+ STM32_ADC_ADC1_IRQ_HOOK
+#endif
#endif /* STM32_ADC_USE_ADC1 */
#if STM32_ADC_USE_ADC2
@@ -139,6 +142,9 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
_adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW);
}
/* TODO: Add here analog watchdog handling.*/
+#if defined(STM32_ADC_ADC2_IRQ_HOOK)
+ STM32_ADC_ADC2_IRQ_HOOK
+#endif
#endif /* STM32_ADC_USE_ADC2 */
#if STM32_ADC_USE_ADC3
@@ -153,9 +159,12 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
_adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW);
}
/* TODO: Add here analog watchdog handling.*/
+#if defined(STM32_ADC_ADC3_IRQ_HOOK)
+ STM32_ADC_ADC3_IRQ_HOOK
+#endif
#endif /* STM32_ADC_USE_ADC3 */
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -210,8 +219,8 @@ void adc_lld_init(void) {
#endif
/* The shared vector is initialized on driver initialization and never
- disabled.*/
- nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
+ disabled because sharing.*/
+ nvicEnableVector(STM32_ADC_NUMBER, STM32_ADC_IRQ_PRIORITY);
}
/**
@@ -227,12 +236,12 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
- chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(FALSE);
}
@@ -240,12 +249,12 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC2
if (&ADCD2 == adcp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
- chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
rccEnableADC2(FALSE);
}
@@ -253,12 +262,12 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC3
if (&ADCD3 == adcp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
- chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
rccEnableADC3(FALSE);
}
@@ -318,6 +327,7 @@ void adc_lld_stop(ADCDriver *adcp) {
*/
void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode;
+ uint32_t cr2;
const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/
@@ -340,19 +350,27 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adc->SR = 0;
adcp->adc->SMPR1 = grpp->smpr1;
adcp->adc->SMPR2 = grpp->smpr2;
- adcp->adc->SQR1 = grpp->sqr1;
+ adcp->adc->SQR1 = grpp->sqr1 | ADC_SQR1_NUM_CH(grpp->num_channels);
adcp->adc->SQR2 = grpp->sqr2;
adcp->adc->SQR3 = grpp->sqr3;
- /* ADC configuration and start, the start is performed using the method
- specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
+ /* ADC configuration and start.*/
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
- if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
- adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA |
- ADC_CR2_DDS | ADC_CR2_ADON;
+
+ /* Enforcing the mandatory bits in CR2.*/
+ cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
+
+ /* The start method is different dependign if HW or SW triggered, the
+ start is performed using the method specified in the CR2 configuration.*/
+ if ((cr2 & ADC_CR2_SWSTART) != 0) {
+ /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
+ adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
+
+ /* Finally enabling ADC_CR2_SWSTART.*/
+ adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
+ }
else
- adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA |
- ADC_CR2_DDS | ADC_CR2_ADON;
+ adcp->adc->CR2 = cr2;
}
/**
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/adc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.h
similarity index 96%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/adc_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.h
index 28d16b3217..8bc3736bfb 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/adc_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32F4xx/adc_lld.h
- * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver header.
+ * @file ADCv2/hal_adc_lld.h
+ * @brief STM32 ADC subsystem low level driver header.
*
* @addtogroup ADC
* @{
*/
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
#if HAL_USE_ADC || defined(__DOXYGEN__)
@@ -54,7 +54,14 @@
* @name Triggers selection
* @{
*/
-#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */
+#define ADC_CR2_EXTEN_MASK (3U << 28U)
+#define ADC_CR2_EXTEN_DISABLED (0U << 28U)
+#define ADC_CR2_EXTEN_RISING (1U << 28U)
+#define ADC_CR2_EXTEN_FALLING (2U << 28U)
+#define ADC_CR2_EXTEN_BOTH (3U << 28U)
+
+#define ADC_CR2_EXTSEL_MASK (15U << 24U)
+#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24U)
/** @} */
/**
@@ -345,7 +352,7 @@ typedef struct {
/**
* @brief Enables the circular buffer mode for the group.
*/
- bool_t circular;
+ bool circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
@@ -437,17 +444,13 @@ struct ADCDriver {
/**
* @brief Waiting thread.
*/
- Thread *thread;
+ thread_reference_t thread;
#endif
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the peripheral.
*/
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
+ mutex_t mutex;
#endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS)
ADC_DRIVER_EXT_FIELDS
@@ -562,6 +565,6 @@ extern "C" {
#endif /* HAL_USE_ADC */
-#endif /* _ADC_LLD_H_ */
+#endif /* HAL_ADC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/notes.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/notes.txt
new file mode 100644
index 0000000000..4b79a3467c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv2/notes.txt
@@ -0,0 +1,13 @@
+STM32 ADCv2 driver.
+
+Driver capability:
+
+- Supports the STM32 "advanced" ADC found on F2, F4 and F7 sub-families.
+
+The file registry must export:
+
+STM32_HAS_ADCx - ADCx presence flag (1..3).
+STM32_ADC_HANDLER - IRQ vector name for ADCs (shared).
+STM32_ADC_NUMBER - IRQ vector number for ADCs (shared).
+STM32_ADCx_DMA_MSK - Mask of the compatible DMA channels.
+STM32_ADCx_DMA_CHN - Mask of the channels mapping.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/driver.mk
new file mode 100644
index 0000000000..5812df4a24
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/adc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
similarity index 50%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/adc_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
index 188a77f370..d287a34d2d 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/adc_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32F30x/adc_lld.c
- * @brief STM32F30x ADC subsystem low level driver source.
+ * @file ADCv3/hal_adc_lld.c
+ * @brief STM32 ADC subsystem low level driver source.
*
* @addtogroup ADC
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_ADC || defined(__DOXYGEN__)
@@ -31,6 +30,18 @@
/* Driver local definitions. */
/*===========================================================================*/
+#define ADC1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
+
+#define ADC2_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
+
+#define ADC3_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
+
+#define ADC4_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_CHN)
+
#if STM32_ADC_DUAL_MODE
#if STM32_ADC_COMPACT_SAMPLES
/* Compact type dual mode.*/
@@ -65,15 +76,31 @@
ADCDriver ADCD1;
#endif
-/** @brief ADC1 driver identifier.*/
+/** @brief ADC2 driver identifier.*/
+#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
+ADCDriver ADCD2;
+#endif
+
+/** @brief ADC3 driver identifier.*/
#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
ADCDriver ADCD3;
#endif
+/** @brief ADC4 driver identifier.*/
+#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__)
+ADCDriver ADCD4;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
+static const ADCConfig default_config = {
+ difsel: 0
+};
+
+static uint32_t clkmask;
+
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@@ -85,12 +112,23 @@ ADCDriver ADCD3;
*/
static void adc_lld_vreg_on(ADCDriver *adcp) {
+#if defined(STM32F3XX)
adcp->adcm->CR = 0; /* RM 12.4.3.*/
adcp->adcm->CR = ADC_CR_ADVREGEN_0;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADVREGEN_0;
#endif
- halPolledDelay(US2RTT(10));
+ osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10));
+#endif
+
+#if defined(STM32L4XX)
+ adcp->adcm->CR = 0; /* RM 16.3.6.*/
+ adcp->adcm->CR = ADC_CR_ADVREGEN;
+#if STM32_ADC_DUAL_MODE
+ adcp->adcs->CR = ADC_CR_ADVREGEN;
+#endif
+ osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20));
+#endif
}
/**
@@ -100,11 +138,23 @@ static void adc_lld_vreg_on(ADCDriver *adcp) {
*/
static void adc_lld_vreg_off(ADCDriver *adcp) {
+#if defined(STM32F3XX)
adcp->adcm->CR = 0; /* RM 12.4.3.*/
adcp->adcm->CR = ADC_CR_ADVREGEN_1;
#if STM32_ADC_DUAL_MODE
+ adcp->adcs->CR = 0;
adcp->adcs->CR = ADC_CR_ADVREGEN_1;
#endif
+#endif
+
+#if defined(STM32L4XX)
+ adcp->adcm->CR = 0; /* RM 12.4.3.*/
+ adcp->adcm->CR = ADC_CR_DEEPPWD;
+#if STM32_ADC_DUAL_MODE
+ adcp->adcs->CR = 0;
+ adcp->adcs->CR = ADC_CR_DEEPPWD;
+#endif
+#endif
}
/**
@@ -114,6 +164,18 @@ static void adc_lld_vreg_off(ADCDriver *adcp) {
*/
static void adc_lld_analog_on(ADCDriver *adcp) {
+#if defined(STM32F3XX)
+ adcp->adcm->CR |= ADC_CR_ADEN;
+ while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0)
+ ;
+#if STM32_ADC_DUAL_MODE
+ adcp->adcs->CR |= ADC_CR_ADEN;
+ while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0)
+ ;
+#endif
+#endif
+
+#if defined(STM32L4XX)
adcp->adcm->CR |= ADC_CR_ADEN;
while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0)
;
@@ -122,6 +184,7 @@ static void adc_lld_analog_on(ADCDriver *adcp) {
while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0)
;
#endif
+#endif
}
/**
@@ -148,18 +211,31 @@ static void adc_lld_analog_off(ADCDriver *adcp) {
*/
static void adc_lld_calibrate(ADCDriver *adcp) {
- chDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #1",
- "invalid register state");
+#if defined(STM32F3XX)
+ osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");
adcp->adcm->CR |= ADC_CR_ADCAL;
while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
;
#if STM32_ADC_DUAL_MODE
- chDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #2",
- "invalid register state");
+ osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");
adcp->adcs->CR |= ADC_CR_ADCAL;
while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
;
#endif
+#endif
+
+#if defined(STM32L4XX)
+ osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN, "invalid register state");
+ adcp->adcm->CR |= ADC_CR_ADCAL;
+ while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
+ ;
+#if STM32_ADC_DUAL_MODE
+ osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN, "invalid register state");
+ adcp->adcs->CR |= ADC_CR_ADCAL;
+ while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
+ ;
+#endif
+#endif
}
/**
@@ -244,30 +320,51 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
/* Driver interrupt handlers. */
/*===========================================================================*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
/**
* @brief ADC1/ADC2 interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(Vector88) {
+OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) {
uint32_t isr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
#if STM32_ADC_DUAL_MODE
+
isr = ADC1->ISR;
isr |= ADC2->ISR;
ADC1->ISR = isr;
ADC2->ISR = isr;
+#if defined(STM32_ADC_ADC12_IRQ_HOOK)
+ STM32_ADC_ADC12_IRQ_HOOK
+#endif
+ adc_lld_serve_interrupt(&ADCD1, isr);
+
#else /* !STM32_ADC_DUAL_MODE */
+
+#if STM32_ADC_USE_ADC1
isr = ADC1->ISR;
ADC1->ISR = isr;
-#endif /* !STM32_ADC_DUAL_MODE */
-
+#if defined(STM32_ADC_ADC1_IRQ_HOOK)
+ STM32_ADC_ADC1_IRQ_HOOK
+#endif
adc_lld_serve_interrupt(&ADCD1, isr);
+#endif
+
+#if STM32_ADC_USE_ADC2
+ isr = ADC2->ISR;
+ ADC2->ISR = isr;
+#if defined(STM32_ADC_ADC2_IRQ_HOOK)
+ STM32_ADC_ADC2_IRQ_HOOK
+#endif
+ adc_lld_serve_interrupt(&ADCD2, isr);
+#endif
+
+#endif /* !STM32_ADC_DUAL_MODE */
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_ADC_USE_ADC1 */
@@ -277,17 +374,19 @@ CH_IRQ_HANDLER(Vector88) {
*
* @isr
*/
-CH_IRQ_HANDLER(VectorFC) {
+OSAL_IRQ_HANDLER(STM32_ADC3_HANDLER) {
uint32_t isr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
isr = ADC3->ISR;
ADC3->ISR = isr;
-
+#if defined(STM32_ADC_ADC3_IRQ_HOOK)
+ STM32_ADC_ADC3_IRQ_HOOK
+#endif
adc_lld_serve_interrupt(&ADCD3, isr);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#if STM32_ADC_DUAL_MODE
@@ -296,21 +395,41 @@ CH_IRQ_HANDLER(VectorFC) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector134) {
+OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {
uint32_t isr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
isr = ADC4->ISR;
ADC4->ISR = isr;
adc_lld_serve_interrupt(&ADCD3, isr);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_ADC_DUAL_MODE */
#endif /* STM32_ADC_USE_ADC3 */
+#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__)
+/**
+ * @brief ADC4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {
+ uint32_t isr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ isr = ADC4->ISR;
+ ADC4->ISR = isr;
+
+ adc_lld_serve_interrupt(&ADCD4, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_ADC4 */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -322,45 +441,135 @@ CH_IRQ_HANDLER(Vector134) {
*/
void adc_lld_init(void) {
+ clkmask = 0;
+
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
- ADCD1.adcc = ADC1_2;
- ADCD1.adcm = ADC1;
+#if defined(ADC1_2_COMMON)
+ ADCD1.adcc = ADC1_2_COMMON;
+#elif defined(ADC123_COMMON)
+ ADCD1.adcc = ADC123_COMMON;
+#else
+ ADCD1.adcc = ADC1_COMMON;
+#endif
+ ADCD1.adcm = ADC1;
#if STM32_ADC_DUAL_MODE
- ADCD1.adcs = ADC2;
+ ADCD1.adcs = ADC2;
#endif
- ADCD1.dmastp = STM32_DMA1_STREAM1;
+ ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
ADCD1.dmamode = ADC_DMA_SIZE |
- STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
+ STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
- nvicEnableVector(ADC1_2_IRQn,
- CORTEX_PRIORITY_MASK(STM32_ADC_ADC12_IRQ_PRIORITY));
#endif /* STM32_ADC_USE_ADC1 */
+#if STM32_ADC_USE_ADC2
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD2);
+#if defined(ADC1_2_COMMON)
+ ADCD2.adcc = ADC1_2_COMMON;
+#elif defined(ADC123_COMMON)
+ ADCD2.adcc = ADC123_COMMON;
+#endif
+ ADCD2.adcm = ADC2;
+ ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
+ ADCD2.dmamode = ADC_DMA_SIZE |
+ STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif /* STM32_ADC_USE_ADC2 */
+
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD3);
- ADCD3.adcc = ADC3_4;
- ADCD3.adcm = ADC3;
+#if defined(ADC3_4_COMMON)
+ ADCD3.adcc = ADC3_4_COMMON;
+#elif defined(ADC123_COMMON)
+ ADCD1.adcc = ADC123_COMMON;
+#else
+ ADCD3.adcc = ADC3_COMMON;
+#endif
+ ADCD3.adcm = ADC3;
#if STM32_ADC_DUAL_MODE
- ADCD3.adcs = ADC4;
+ ADCD3.adcs = ADC4;
#endif
- ADCD3.dmastp = STM32_DMA2_STREAM5;
+ ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
ADCD3.dmamode = ADC_DMA_SIZE |
- STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
+ STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif /* STM32_ADC_USE_ADC3 */
+
+#if STM32_ADC_USE_ADC4
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD4);
+ ADCD4.adcc = ADC3_4_COMMON;
+ ADCD4.adcm = ADC4;
+ ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);
+ ADCD4.dmamode = ADC_DMA_SIZE |
+ STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
- nvicEnableVector(ADC3_IRQn,
- CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
+#endif /* STM32_ADC_USE_ADC4 */
+
+ /* IRQs setup.*/
+#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
+ nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);
+#endif
+#if STM32_ADC_USE_ADC3
+ nvicEnableVector(STM32_ADC3_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
#if STM32_ADC_DUAL_MODE
- nvicEnableVector(ADC4_IRQn,
- CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
+ nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
+#endif
+#endif
+#if STM32_ADC_USE_ADC4
+ nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
+#endif
+
+ /* ADC units pre-initializations.*/
+#if defined(STM32F3XX)
+#if STM32_HAS_ADC1 && STM32_HAS_ADC2
+#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
+ rccEnableADC12(FALSE);
+ rccResetADC12();
+ ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+ rccDisableADC12(FALSE);
+#endif
+#else
+#if STM32_ADC_USE_ADC1
+ rccEnableADC12(FALSE);
+ rccResetADC12();
+ ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+ rccDisableADC12(FALSE);
+#endif
+#endif
+#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
+ rccEnableADC34(FALSE);
+ rccResetADC34();
+ ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
+ rccDisableADC34(FALSE);
+#endif
+#endif
+
+#if defined(STM32L4XX)
+ rccEnableADC123(FALSE);
+ rccResetADC123();
+
+#if defined(ADC1_2_COMMON)
+ ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
+#elif defined(ADC123_COMMON)
+ ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
+#else
+ ADC1_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
+
+ rccDisableADC123(FALSE);
#endif
-#endif /* STM32_ADC_USE_ADC3 */
}
/**
@@ -372,41 +581,103 @@ void adc_lld_init(void) {
*/
void adc_lld_start(ADCDriver *adcp) {
+ /* Handling the default configuration.*/
+ if (adcp->config == NULL) {
+ adcp->config = &default_config;
+ }
+
/* If in stopped state then enables the ADC and DMA clocks.*/
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(adcp->dmastp,
- STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
+ STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
- chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
+
+ clkmask |= (1 << 0);
+#if defined(STM32F3XX)
rccEnableADC12(FALSE);
+#endif
+#if defined(STM32L4XX)
+ rccEnableADC123(FALSE);
+#endif
}
#endif /* STM32_ADC_USE_ADC1 */
+#if STM32_ADC_USE_ADC2
+ if (&ADCD2 == adcp) {
+ bool b;
+ b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ clkmask |= (1 << 1);
+#if defined(STM32F3XX)
+ rccEnableADC12(FALSE);
+#endif
+#if defined(STM32L4XX)
+ rccEnableADC123(FALSE);
+#endif
+ }
+#endif /* STM32_ADC_USE_ADC2 */
+
#if STM32_ADC_USE_ADC3
if (&ADCD3 == adcp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(adcp->dmastp,
- STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
+ STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
- chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
+
+ clkmask |= (1 << 2);
+#if defined(STM32F3XX)
rccEnableADC34(FALSE);
+#endif
+#if defined(STM32L4XX)
+ rccEnableADC123(FALSE);
+#endif
}
-#endif /* STM32_ADC_USE_ADC2 */
+#endif /* STM32_ADC_USE_ADC3 */
+
+#if STM32_ADC_USE_ADC4
+ if (&ADCD4 == adcp) {
+ bool b;
+ b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_ADC4_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ clkmask |= (1 << 3);
+#if defined(STM32F3XX)
+ rccEnableADC34(FALSE);
+#endif
+#if defined(STM32L4XX)
+ rccEnableADC123(FALSE);
+#endif
+ }
+#endif /* STM32_ADC_USE_ADC4 */
/* Setting DMA peripheral-side pointer.*/
#if STM32_ADC_DUAL_MODE
- dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
+ dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
#else
- dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
+ dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
#endif
- /* Clock source setting.*/
- adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+ /* Differential channels setting.*/
+#if STM32_ADC_DUAL_MODE
+ adcp->adcm->DIFSEL = adcp->config->difsel;
+ adcp->adcs->DIFSEL = adcp->config->difsel;
+#else
+ adcp->adcm->DIFSEL = adcp->config->difsel;
+#endif
/* Master ADC calibration.*/
adc_lld_vreg_on(adcp);
@@ -439,14 +710,69 @@ void adc_lld_stop(ADCDriver *adcp) {
adc_lld_analog_off(adcp);
adc_lld_vreg_off(adcp);
+#if defined(STM32L4XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
+
#if STM32_ADC_USE_ADC1
- if (&ADCD1 == adcp)
- rccDisableADC12(FALSE);
+ if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
+ clkmask &= ~(1 << 0);
+ }
+#endif
+
+#if STM32_ADC_USE_ADC2
+ if (&ADCD2 == adcp) {
+#if defined(STM32F3XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
+ clkmask &= ~(1 << 1);
+ }
#endif
#if STM32_ADC_USE_ADC3
- if (&ADCD3 == adcp)
+ if (&ADCD3 == adcp) {
+#if defined(STM32F3XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
+ clkmask &= ~(1 << 2);
+ }
+#endif
+
+#if STM32_ADC_USE_ADC4
+ if (&ADCD4 == adcp) {
+#if defined(STM32F3XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
+ clkmask &= ~(1 << 3);
+ }
+#endif
+
+#if defined(STM32F3XX)
+#if STM32_HAS_ADC1 || STM32_HAS_ADC2
+ if ((clkmask & 0x3) == 0) {
+ rccDisableADC12(FALSE);
+ }
+#endif
+
+#if STM32_HAS_ADC3 || STM32_HAS_ADC4
+ if ((clkmask & 0xC) == 0) {
rccDisableADC34(FALSE);
+ }
+#endif
+#endif
+
+#if defined(STM32L4XX)
+ if ((clkmask & 0x7) == 0) {
+ rccDisableADC123(FALSE);
+ }
#endif
}
}
@@ -459,17 +785,17 @@ void adc_lld_stop(ADCDriver *adcp) {
* @notapi
*/
void adc_lld_start_conversion(ADCDriver *adcp) {
- uint32_t dmamode, ccr, cfgr;
+ uint32_t dmamode, cfgr;
const ADCConversionGroup *grpp = adcp->grpp;
+#if STM32_ADC_DUAL_MODE
+ uint32_t ccr = grpp->ccr & ~(ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK);
+#endif
- chDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
- "adc_lld_start_conversion(), #1",
- "odd number of channels in dual mode");
+ osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
+ "odd number of channels in dual mode");
/* Calculating control registers values.*/
dmamode = adcp->dmamode;
- ccr = grpp->ccr | (adcp->adcc->CCR & (ADC_CCR_CKMODE_MASK |
- ADC_CCR_MDMA_MASK));
cfgr = grpp->cfgr | ADC_CFGR_DMAEN;
if (grpp->circular) {
dmamode |= STM32_DMA_CR_CIRC;
@@ -491,23 +817,25 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *
(uint32_t)adcp->depth);
#else
- dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
- (uint32_t)adcp->depth);
+ dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+ (uint32_t)adcp->depth);
#endif
dmaStreamSetMode(adcp->dmastp, dmamode);
dmaStreamEnable(adcp->dmastp);
- /* Configuring the CCR register with the static settings ORed with
- the user-specified settings in the conversion group configuration
- structure.*/
- adcp->adcc->CCR = ccr;
-
/* ADC setup, if it is defined a callback for the analog watch dog then it
is enabled.*/
adcp->adcm->ISR = adcp->adcm->ISR;
adcp->adcm->IER = ADC_IER_OVR | ADC_IER_AWD1;
adcp->adcm->TR1 = grpp->tr1;
#if STM32_ADC_DUAL_MODE
+
+ /* Configuring the CCR register with the user-specified settings
+ in the conversion group configuration structure, static settings are
+ preserved.*/
+ adcp->adcc->CCR = (adcp->adcc->CCR &
+ (ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK)) | ccr;
+
adcp->adcm->SMPR1 = grpp->smpr[0];
adcp->adcm->SMPR2 = grpp->smpr[1];
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
@@ -550,6 +878,96 @@ void adc_lld_stop_conversion(ADCDriver *adcp) {
adc_lld_stop_adc(adcp);
}
+/**
+ * @brief Enables the VREFEN bit.
+ * @details The VREFEN bit is required in order to sample the VREF channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32EnableVREF(ADCDriver *adcp) {
+
+ adcp->adcc->CCR |= ADC_CCR_VREFEN;
+}
+
+/**
+ * @brief Disables the VREFEN bit.
+ * @details The VREFEN bit is required in order to sample the VREF channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32DisableVREF(ADCDriver *adcp) {
+
+ adcp->adcc->CCR &= ~ADC_CCR_VREFEN;
+}
+
+/**
+ * @brief Enables the TSEN bit.
+ * @details The TSEN bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32EnableTS(ADCDriver *adcp) {
+
+ adcp->adcc->CCR |= ADC_CCR_TSEN;
+}
+
+/**
+ * @brief Disables the TSEN bit.
+ * @details The TSEN bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32DisableTS(ADCDriver *adcp) {
+
+ adcp->adcc->CCR &= ~ADC_CCR_TSEN;
+}
+
+/**
+ * @brief Enables the VBATEN bit.
+ * @details The VBATEN bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32EnableVBAT(ADCDriver *adcp) {
+
+ adcp->adcc->CCR |= ADC_CCR_VBATEN;
+}
+
+/**
+ * @brief Disables the VBATEN bit.
+ * @details The VBATEN bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adcSTM32DisableVBAT(ADCDriver *adcp) {
+
+ adcp->adcc->CCR &= ~ADC_CCR_VBATEN;
+}
+
#endif /* HAL_USE_ADC */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/adc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
similarity index 61%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/adc_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
index bbe1135d49..2457e4e5e6 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/adc_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32F30x/adc_lld.h
- * @brief STM32F30x ADC subsystem low level driver header.
+ * @file ADCv3/hal_adc_lld.h
+ * @brief STM32 ADC subsystem low level driver header.
*
* @addtogroup ADC
* @{
*/
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
#if HAL_USE_ADC || defined(__DOXYGEN__)
@@ -35,6 +35,7 @@
* @name Available analog channels
* @{
*/
+#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
@@ -59,6 +60,7 @@
* @name Sampling rates
* @{
*/
+#if defined(STM32F3XX)
#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */
#define ADC_SMPR_SMP_2P5 1 /**< @brief 15 cycles conversion time. */
#define ADC_SMPR_SMP_4P5 2 /**< @brief 17 cycles conversion time. */
@@ -67,6 +69,17 @@
#define ADC_SMPR_SMP_61P5 5 /**< @brief 74 cycles conversion time. */
#define ADC_SMPR_SMP_181P5 6 /**< @brief 194 cycles conversion time. */
#define ADC_SMPR_SMP_601P5 7 /**< @brief 614 cycles conversion time. */
+#endif
+#if defined(STM32L4XX)
+#define ADC_SMPR_SMP_2P5 0 /**< @brief 15 cycles conversion time */
+#define ADC_SMPR_SMP_6P5 1 /**< @brief 19 cycles conversion time. */
+#define ADC_SMPR_SMP_12P5 2 /**< @brief 25 cycles conversion time. */
+#define ADC_SMPR_SMP_24P5 3 /**< @brief 37 cycles conversion time. */
+#define ADC_SMPR_SMP_47P5 4 /**< @brief 60 cycles conversion time. */
+#define ADC_SMPR_SMP_92P5 5 /**< @brief 105 cycles conversion time. */
+#define ADC_SMPR_SMP_247P5 6 /**< @brief 260 cycles conversion time. */
+#define ADC_SMPR_SMP_640P5 7 /**< @brief 653 cycles conversion time. */
+#endif
/** @} */
/**
@@ -123,9 +136,9 @@
* @{
*/
#define ADC_CCR_DUAL_MASK (31 << 0)
-#define ADC_CCR_DUAL(n) ((n) << 0)
+#define ADC_CCR_DUAL_FIELD(n) ((n) << 0)
#define ADC_CCR_DELAY_MASK (15 << 8)
-#define ADC_CCR_DELAY(n) ((n) << 8)
+#define ADC_CCR_DELAY_FIELD(n) ((n) << 8)
#define ADC_CCR_DMACFG_MASK (1 << 13)
#define ADC_CCR_DMACFG_ONESHOT (0 << 13)
#define ADC_CCR_DMACFG_CIRCULAR (1 << 13)
@@ -138,9 +151,19 @@
#define ADC_CCR_CKMODE_AHB_DIV1 (1 << 16)
#define ADC_CCR_CKMODE_AHB_DIV2 (2 << 16)
#define ADC_CCR_CKMODE_AHB_DIV4 (3 << 16)
+
+/* F3 headers do not define the following macros, L4 headers do.*/
+#if !defined(ADC_CCR_VREFEN) || defined(__DOXYGEN__)
#define ADC_CCR_VREFEN (1 << 22)
+#endif
+
+#if !defined(ADC_CCR_TSEN) || defined(__DOXYGEN__)
#define ADC_CCR_TSEN (1 << 23)
+#endif
+
+#if !defined(ADC_CCR_VBATEN) || defined(__DOXYGEN__)
#define ADC_CCR_VBATEN (1 << 24)
+#endif
/** @} */
/*===========================================================================*/
@@ -151,6 +174,23 @@
* @name Configuration options
* @{
*/
+/**
+ * @brief Enables the ADC master/slave mode.
+ * @note In dual mode only ADCD1 and ADCD3 are available.
+ */
+#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
+#define STM32_ADC_DUAL_MODE FALSE
+#endif
+
+/**
+ * @brief Makes the ADC samples type an 8bits one.
+ * @note 10 and 12 bits sampling mode must not be used when this option
+ * is enabled.
+ */
+#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
+#define STM32_ADC_COMPACT_SAMPLES FALSE
+#endif
+
/**
* @brief ADC1 driver enable switch.
* @details If set to @p TRUE the support for ADC1 is included.
@@ -160,6 +200,15 @@
#define STM32_ADC_USE_ADC1 FALSE
#endif
+/**
+ * @brief ADC2 driver enable switch.
+ * @details If set to @p TRUE the support for ADC2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC2 FALSE
+#endif
+
/**
* @brief ADC3 driver enable switch.
* @details If set to @p TRUE the support for ADC3 is included.
@@ -168,19 +217,41 @@
#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
#define STM32_ADC_USE_ADC3 FALSE
#endif
+/**
+ * @brief ADC4 driver enable switch.
+ * @details If set to @p TRUE the support for ADC4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_ADC_USE_ADC4) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC4 FALSE
+#endif
+
+/**
+ * @brief ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief ADC2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#endif
/**
- * @brief ADC1/ADC2 DMA priority (0..3|lowest..highest).
+ * @brief ADC3 DMA priority (0..3|lowest..highest).
*/
-#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
+#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
#endif
/**
- * @brief ADC3/ADC4 DMA priority (0..3|lowest..highest).
+ * @brief ADC4 DMA priority (0..3|lowest..highest).
*/
-#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#if !defined(STM32_ADC_ADC4_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#endif
/**
@@ -191,26 +262,48 @@
#endif
/**
- * @brief ADC3/ADC4 interrupt priority level setting.
+ * @brief ADC3 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief ADC4 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief ADC1 DMA interrupt priority level setting.
*/
-#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#endif
/**
- * @brief ADC1/ADC2 DMA interrupt priority level setting.
+ * @brief ADC2 DMA interrupt priority level setting.
*/
-#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
+#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#endif
/**
- * @brief ADC3/ADC4 DMA interrupt priority level setting.
+ * @brief ADC3 DMA interrupt priority level setting.
*/
-#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#endif
+/**
+ * @brief ADC4 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC4_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
+#endif
+
+#if defined(STM32F3XX) || defined(__DOXYGEN__)
/**
* @brief ADC1/ADC2 clock source and mode.
*/
@@ -224,68 +317,212 @@
#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#endif
+#endif /* defined(STM32F3XX) */
+#if defined(STM32L4XX) || defined(__DOXYGEN__)
/**
- * @brief Enables the ADC master/slave mode.
+ * @brief ADC1/ADC2/ADC3 clock source and mode.
*/
-#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_DUAL_MODE FALSE
+#if !defined(STM32_ADC_ADC123_CLOCK_MODE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#endif
+#endif /* defined(STM32L4XX) */
-/**
- * @brief Makes the ADC samples type an 8bits one.
- */
-#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
-#define STM32_ADC_COMPACT_SAMPLES FALSE
-#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+/* Supported devices checks.*/
+#if !defined(STM32F3XX) && !defined(STM32L4XX)
+#error "ADCv3 only supports F3 and L4 STM32 devices"
+#endif
+
+/* Registry checks.*/
+#if !defined(STM32_HAS_ADC1) || !defined(STM32_HAS_ADC2) || \
+ !defined(STM32_HAS_ADC3) || !defined(STM32_HAS_ADC4)
+#error "STM32_ADC_USE_ADCx not defined in registry"
+#endif
+
+#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_HANDLER)) || \
+ (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_HANDLER)) || \
+ (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_HANDLER)) || \
+ (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_HANDLER))
+#error "STM32_ADCx_HANDLER not defined in registry"
+#endif
+
+#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_NUMBER)) || \
+ (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_NUMBER)) || \
+ (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_NUMBER)) || \
+ (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_NUMBER))
+#error "STM32_ADCx_NUMBER not defined in registry"
+#endif
+
+#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_DMA_MSK)) || \
+ (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_DMA_MSK)) || \
+ (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_DMA_MSK)) || \
+ (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_DMA_MSK))
+#error "STM32_ADCx_DMA_MSK not defined in registry"
+#endif
+
+#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_DMA_CHN)) || \
+ (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_DMA_CHN)) || \
+ (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_DMA_CHN)) || \
+ (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_DMA_CHN))
+#error "STM32_ADCx_DMA_CHN not defined in registry"
+#endif
+
+/* Units checks.*/
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
#error "ADC1 not present in the selected device"
#endif
+#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2
+#error "ADC2 not present in the selected device"
+#endif
+
#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
#error "ADC3 not present in the selected device"
#endif
-#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3
+#if STM32_ADC_USE_ADC4 && !STM32_HAS_ADC4
+#error "ADC4 not present in the selected device"
+#endif
+
+/* Units checks related to dual mode.*/
+#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC1 && !STM32_HAS_ADC2
+#error "ADC2 not present in the selected device, required for dual mode"
+#endif
+
+#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC3 && !STM32_HAS_ADC4
+#error "ADC4 not present in the selected device, required for dual mode"
+#endif
+
+#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC2
+#error "ADC2 cannot be used in dual mode"
+#endif
+
+#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC4
+#error "ADC4 cannot be used in dual mode"
+#endif
+
+/* At least one ADC must be assigned.*/
+#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && \
+ !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4
#error "ADC driver activated but no ADC peripheral assigned"
#endif
+/* ISR arrangments checks.*/
+#if STM32_HAS_ADC1 && STM32_HAS_ADC2
+#if STM32_ADC1_NUMBER != STM32_ADC2_NUMBER
+#error "ADCv3 driver expects STM32_ADC1_NUMBER == STM32_ADC2_NUMBER from registry"
+#endif
+#endif
+
+/* ADC IRQ priority tests.*/
#if STM32_ADC_USE_ADC1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1"
#endif
+#if STM32_ADC_USE_ADC2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC2"
+#endif
+
+#if STM32_ADC_USE_ADC3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC3"
+#endif
+
+#if STM32_ADC_USE_ADC4 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC4"
+#endif
+
+/* DMA IRQ priority tests.*/
#if STM32_ADC_USE_ADC1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1 DMA"
#endif
+#if STM32_ADC_USE_ADC2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC2 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC3 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC4 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC4 DMA"
+#endif
+
+/* DMA priority tests.*/
#if STM32_ADC_USE_ADC1 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to ADC1"
#endif
-#if STM32_ADC_USE_ADC3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC3"
+#if STM32_ADC_USE_ADC2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC2"
#endif
#if STM32_ADC_USE_ADC3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC3 DMA"
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC3"
+#endif
+
+#if STM32_ADC_USE_ADC4 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC4"
+#endif
+
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM)
+#error "ADC1 DMA stream not defined"
+#endif
+
+#if STM32_ADC_USE_ADC2 && !defined(STM32_ADC_ADC2_DMA_STREAM)
+#error "ADC2 DMA stream not defined"
+#endif
+
+#if STM32_ADC_USE_ADC3 && !defined(STM32_ADC_ADC3_DMA_STREAM)
+#error "ADC3 DMA stream not defined"
+#endif
+
+#if STM32_ADC_USE_ADC4 && !defined(STM32_ADC_ADC4_DMA_STREAM)
+#error "ADC4 DMA stream not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_ADC_USE_ADC1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
+#error "invalid DMA stream associated to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK)
+#error "invalid DMA stream associated to ADC2"
#endif
#if STM32_ADC_USE_ADC3 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC3"
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK)
+#error "invalid DMA stream associated to ADC3"
+#endif
+
+#if STM32_ADC_USE_ADC4 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_MSK)
+#error "invalid DMA stream associated to ADC4"
#endif
+/* ADC clock source checks.*/
+#if defined(STM32F3XX)
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC12_CLOCK STM32_ADC12CLK
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
@@ -310,13 +547,32 @@
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
#endif
-#if STM32_ADC12_CLOCK > 72000000
-#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
+#if STM32_ADC12_CLOCK > STM32_ADCCLK_MAX
+#error "STM32_ADC12_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+#if STM32_ADC34_CLOCK > STM32_ADCCLK_MAX
+#error "STM32_ADC34_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+#endif /* defined(STM32F3XX) */
+
+#if defined(STM32L4XX)
+#if STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
+#define STM32_ADC123_CLOCK STM32_ADC12CLK
+#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC123_CLOCK (STM32_HCLK / 1)
+#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
+#define STM32_ADC123_CLOCK (STM32_HCLK / 2)
+#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC123_CLOCK (STM32_HCLK / 4)
+#else
+#error "invalid clock mode selected for STM32_ADC_ADC123_CLOCK_MODE"
#endif
-#if STM32_ADC34_CLOCK > 72000000
-#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
+#if STM32_ADC123_CLOCK > STM32_ADCCLK_MAX
+#error "STM32_ADC123_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
#endif
+#endif /* defined(STM32L4XX) */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
@@ -389,7 +645,7 @@ typedef struct {
/**
* @brief Enables the circular buffer mode for the group.
*/
- bool_t circular;
+ bool circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
@@ -408,7 +664,7 @@ typedef struct {
* @note The bits DMAEN and DMACFG are enforced internally
* to the driver, keep them to zero.
* @note The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be
- * specified in continuous more or if the buffer depth is
+ * specified in continuous mode or if the buffer depth is
* greater than one.
*/
uint32_t cfgr;
@@ -416,12 +672,15 @@ typedef struct {
* @brief ADC TR1 register initialization data.
*/
uint32_t tr1;
+#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
/**
* @brief ADC CCR register initialization data.
* @note The bits CKMODE, MDMA, DMACFG are enforced internally to the
* driver, keep them to zero.
+ * @note This field is only present in dual mode.
*/
uint32_t ccr;
+#endif
/**
* @brief ADC SMPRx registers initialization data.
*/
@@ -433,10 +692,12 @@ typedef struct {
#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
/**
* @brief Slave ADC SMPRx registers initialization data.
+ * @note This field is only present in dual mode.
*/
uint32_t ssmpr[2];
/**
* @brief Slave ADC SQRx register initialization data.
+ * @note This field is only present in dual mode.
*/
uint32_t ssqr[4];
#endif /* STM32_ADC_DUAL_MODE */
@@ -444,10 +705,12 @@ typedef struct {
/**
* @brief Driver configuration structure.
- * @note It could be empty on some architectures.
*/
typedef struct {
- uint32_t dummy;
+ /**
+ * @brief ADC DIFSEL register initialization data.
+ */
+ uint32_t difsel;
} ADCConfig;
/**
@@ -478,26 +741,18 @@ struct ADCDriver {
/**
* @brief Waiting thread.
*/
- Thread *thread;
+ thread_reference_t thread;
#endif
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the peripheral.
*/
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
+ mutex_t mutex;
#endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS)
ADC_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
- /**
- * @brief Pointer to the common ADCx_y registers block.
- */
- ADC_Common_TypeDef *adcc;
/**
* @brief Pointer to the master ADCx registers block.
*/
@@ -508,6 +763,10 @@ struct ADCDriver {
*/
ADC_TypeDef *adcs;
#endif /* STM32_ADC_DUAL_MODE */
+ /**
+ * @brief Pointer to the common ADCx_y registers block.
+ */
+ ADC_Common_TypeDef *adcc;
/**
* @brief Pointer to associated DMA channel.
*/
@@ -563,6 +822,7 @@ struct ADCDriver {
* @name Sampling rate settings helper macros
* @{
*/
+#define ADC_SMPR1_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
#define ADC_SMPR1_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
#define ADC_SMPR1_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
#define ADC_SMPR1_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
@@ -592,10 +852,18 @@ struct ADCDriver {
extern ADCDriver ADCD1;
#endif
+#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD2;
+#endif
+
#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
extern ADCDriver ADCD3;
#endif
+#if STM32_ADC_USE_ADC4 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD4;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -604,12 +872,18 @@ extern "C" {
void adc_lld_stop(ADCDriver *adcp);
void adc_lld_start_conversion(ADCDriver *adcp);
void adc_lld_stop_conversion(ADCDriver *adcp);
+ void adcSTM32EnableVREF(ADCDriver *adcp);
+ void adcSTM32DisableVREF(ADCDriver *adcp);
+ void adcSTM32EnableTS(ADCDriver *adcp);
+ void adcSTM32DisableTS(ADCDriver *adcp);
+ void adcSTM32EnableVBAT(ADCDriver *adcp);
+ void adcSTM32DisableVBAT(ADCDriver *adcp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_ADC */
-#endif /* _ADC_LLD_H_ */
+#endif /* HAL_ADC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/notes.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/notes.txt
new file mode 100644
index 0000000000..37155ca0ab
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/ADCv3/notes.txt
@@ -0,0 +1,19 @@
+STM32 ADCv3 driver.
+
+Driver capability:
+
+- Supports the STM32 "fast" ADC found on F3 and L4 sub-families.
+
+The file registry must export:
+
+STM32_HAS_ADCx - ADCx presence flag (1..4).
+STM32_ADC1_HANDLER - IRQ vector name for ADC1.
+STM32_ADC1_NUMBER - IRQ vector number for ADC1.
+STM32_ADC2_HANDLER - IRQ vector name for ADC2.
+STM32_ADC2_NUMBER - IRQ vector number for ADC2.
+STM32_ADC3_HANDLER - IRQ vector name for ADC3.
+STM32_ADC3_NUMBER - IRQ vector number for ADC3.
+STM32_ADC4_HANDLER - IRQ vector name for ADC4.
+STM32_ADC4_NUMBER - IRQ vector number for ADC4.
+STM32_ADCx_DMA_MSK - Mask of the compatible DMA channels (1..4).
+STM32_ADCx_DMA_CHN - Mask of the channels mapping (1..4).
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/driver.mk
new file mode 100644
index 0000000000..6db597adb8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/can_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c
similarity index 52%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/can_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c
index 4c02c006bc..19f5c6df37 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/can_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/can_lld.c
+ * @file CANv1/hal_can_lld.c
* @brief STM32 CAN subsystem low level driver source.
*
* @addtogroup CAN
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_CAN || defined(__DOXYGEN__)
@@ -31,6 +30,15 @@
/* Driver local definitions. */
/*===========================================================================*/
+/*
+ * Addressing differences in the headers, they seem unable to agree on names.
+ */
+#if STM32_CAN_USE_CAN1
+#if !defined(CAN1)
+#define CAN1 CAN
+#endif
+#endif
+
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -45,6 +53,11 @@ CANDriver CAND1;
CANDriver CAND2;
#endif
+/** @brief CAN3 driver identifier.*/
+#if STM32_CAN_USE_CAN3 || defined(__DOXYGEN__)
+CANDriver CAND3;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -52,10 +65,10 @@ CANDriver CAND2;
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
-
/**
- * @brief Programs the filters.
+ * @brief Programs the filters of CAN 1 and CAN 2.
*
+ * @param[in] canp pointer to the @p CANDriver object
* @param[in] can2sb number of the first filter assigned to CAN2
* @param[in] num number of entries in the filters array, if zero then
* a default filter is programmed
@@ -64,66 +77,114 @@ CANDriver CAND2;
*
* @notapi
*/
-static void can_lld_set_filters(uint32_t can2sb,
+static void can_lld_set_filters(CANDriver* canp,
+ uint32_t can2sb,
uint32_t num,
const CANFilter *cfp) {
- /* Temporarily enabling CAN1 clock.*/
- rccEnableCAN1(FALSE);
+#if STM32_CAN_USE_CAN2
+ if(canp == &CAND2) {
+ /* Set handle to CAN1, because CAN1 manages the filters of CAN2.*/
+ canp = &CAND1;
+ }
+#endif
+
+ /* Temporarily enabling CAN clock.*/
+#if STM32_CAN_USE_CAN1
+ if(canp == &CAND1) {
+ rccEnableCAN1(FALSE);
+ /* Filters initialization.*/
+ canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT;
+ canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT;
+ }
+#endif
+
+#if STM32_CAN_USE_CAN3
+ if(canp == &CAND3) {
+ rccEnableCAN3(FALSE);
+ /* Filters initialization.*/
+ canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT;
+ }
+#endif
- /* Filters initialization.*/
- CAN1->FMR = (CAN1->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT;
if (num > 0) {
uint32_t i, fmask;
/* All filters cleared.*/
- CAN1->FA1R = 0;
- CAN1->FM1R = 0;
- CAN1->FS1R = 0;
- CAN1->FFA1R = 0;
- for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) {
- CAN1->sFilterRegister[i].FR1 = 0;
- CAN1->sFilterRegister[i].FR2 = 0;
+ canp->can->FA1R = 0;
+ canp->can->FM1R = 0;
+ canp->can->FS1R = 0;
+ canp->can->FFA1R = 0;
+
+#if STM32_CAN_USE_CAN1
+ if(canp == &CAND1) {
+ for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) {
+ canp->can->sFilterRegister[i].FR1 = 0;
+ canp->can->sFilterRegister[i].FR2 = 0;
+ }
}
+#endif
+
+#if STM32_CAN_USE_CAN3
+ if(canp == &CAND3) {
+ for (i = 0; i < STM32_CAN3_MAX_FILTERS; i++) {
+ canp->can->sFilterRegister[i].FR1 = 0;
+ canp->can->sFilterRegister[i].FR2 = 0;
+ }
+ }
+#endif
/* Scanning the filters array.*/
for (i = 0; i < num; i++) {
fmask = 1 << cfp->filter;
if (cfp->mode)
- CAN1->FM1R |= fmask;
+ canp->can->FM1R |= fmask;
if (cfp->scale)
- CAN1->FS1R |= fmask;
+ canp->can->FS1R |= fmask;
if (cfp->assignment)
- CAN1->FFA1R |= fmask;
- CAN1->sFilterRegister[cfp->filter].FR1 = cfp->register1;
- CAN1->sFilterRegister[cfp->filter].FR2 = cfp->register2;
- CAN1->FA1R |= fmask;
+ canp->can->FFA1R |= fmask;
+ canp->can->sFilterRegister[cfp->filter].FR1 = cfp->register1;
+ canp->can->sFilterRegister[cfp->filter].FR2 = cfp->register2;
+ canp->can->FA1R |= fmask;
cfp++;
}
}
else {
/* Setting up a single default filter that enables everything for both
CANs.*/
- CAN1->sFilterRegister[0].FR1 = 0;
- CAN1->sFilterRegister[0].FR2 = 0;
-#if STM32_HAS_CAN2
- CAN1->sFilterRegister[can2sb].FR1 = 0;
- CAN1->sFilterRegister[can2sb].FR2 = 0;
+ canp->can->sFilterRegister[0].FR1 = 0;
+ canp->can->sFilterRegister[0].FR2 = 0;
+#if STM32_CAN_USE_CAN2
+ if(canp == &CAND1) {
+ canp->can->sFilterRegister[can2sb].FR1 = 0;
+ canp->can->sFilterRegister[can2sb].FR2 = 0;
+ }
#endif
- CAN1->FM1R = 0;
- CAN1->FFA1R = 0;
-#if STM32_HAS_CAN2
- CAN1->FS1R = 1 | (1 << can2sb);
- CAN1->FA1R = 1 | (1 << can2sb);
-#else
- CAN1->FS1R = 1;
- CAN1->FA1R = 1;
+ canp->can->FM1R = 0;
+ canp->can->FFA1R = 0;
+ canp->can->FS1R = 1;
+ canp->can->FA1R = 1;
+#if STM32_CAN_USE_CAN2
+ if(canp == &CAND1) {
+ canp->can->FS1R |= 1 << can2sb;
+ canp->can->FA1R |= 1 << can2sb;
+ }
#endif
}
- CAN1->FMR &= ~CAN_FMR_FINIT;
+ canp->can->FMR &= ~CAN_FMR_FINIT;
/* Clock disabled, it will be enabled again in can_lld_start().*/
- rccDisableCAN1(FALSE);
+ /* Temporarily enabling CAN clock.*/
+#if STM32_CAN_USE_CAN1
+ if(canp == &CAND1) {
+ rccDisableCAN1(FALSE);
+ }
+#endif
+#if STM32_CAN_USE_CAN3
+ if(canp == &CAND3) {
+ rccDisableCAN3(FALSE);
+ }
+#endif
}
/**
@@ -134,14 +195,51 @@ static void can_lld_set_filters(uint32_t can2sb,
* @notapi
*/
static void can_lld_tx_handler(CANDriver *canp) {
+ uint32_t tsr;
+ eventflags_t flags;
+
+ /* Clearing IRQ sources.*/
+ tsr = canp->can->TSR;
+ canp->can->TSR = tsr;
+
+ /* Flags to be signaled through the TX event source.*/
+ flags = 0U;
- /* No more events until a message is transmitted.*/
- canp->can->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2;
- chSysLockFromIsr();
- while (chSemGetCounterI(&canp->txsem) < 0)
- chSemSignalI(&canp->txsem);
- chEvtBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1));
- chSysUnlockFromIsr();
+ /* Checking mailbox 0.*/
+ if ((tsr & CAN_TSR_RQCP0) != 0U) {
+ if ((tsr & (CAN_TSR_ALST0 | CAN_TSR_TERR0)) != 0U) {
+ flags |= CAN_MAILBOX_TO_MASK(1U) << 16U;
+ }
+ else {
+ flags |= CAN_MAILBOX_TO_MASK(1U);
+ }
+ }
+
+ /* Checking mailbox 1.*/
+ if ((tsr & CAN_TSR_RQCP1) != 0U) {
+ if ((tsr & (CAN_TSR_ALST1 | CAN_TSR_TERR1)) != 0U) {
+ flags |= CAN_MAILBOX_TO_MASK(2U) << 16U;
+ }
+ else {
+ flags |= CAN_MAILBOX_TO_MASK(2U);
+ }
+ }
+
+ /* Checking mailbox 2.*/
+ if ((tsr & CAN_TSR_RQCP2) != 0U) {
+ if ((tsr & (CAN_TSR_ALST2 | CAN_TSR_TERR2)) != 0U) {
+ flags |= CAN_MAILBOX_TO_MASK(3U) << 16U;
+ }
+ else {
+ flags |= CAN_MAILBOX_TO_MASK(3U);
+ }
+ }
+
+ /* Signaling flags and waking up threads waiting for a transmission slot.*/
+ osalSysLockFromISR();
+ osalThreadDequeueAllI(&canp->txqueue, MSG_OK);
+ osalEventBroadcastFlagsI(&canp->txempty_event, flags);
+ osalSysUnlockFromISR();
}
/**
@@ -158,18 +256,17 @@ static void can_lld_rx0_handler(CANDriver *canp) {
if ((rf0r & CAN_RF0R_FMP0) > 0) {
/* No more receive events until the queue 0 has been emptied.*/
canp->can->IER &= ~CAN_IER_FMPIE0;
- chSysLockFromIsr();
- while (chSemGetCounterI(&canp->rxsem) < 0)
- chSemSignalI(&canp->rxsem);
- chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1));
- chSysUnlockFromIsr();
+ osalSysLockFromISR();
+ osalThreadDequeueAllI(&canp->rxqueue, MSG_OK);
+ osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1U));
+ osalSysUnlockFromISR();
}
if ((rf0r & CAN_RF0R_FOVR0) > 0) {
/* Overflow events handling.*/
canp->can->RF0R = CAN_RF0R_FOVR0;
- chSysLockFromIsr();
- chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
- chSysUnlockFromIsr();
+ osalSysLockFromISR();
+ osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
+ osalSysUnlockFromISR();
}
}
@@ -187,18 +284,17 @@ static void can_lld_rx1_handler(CANDriver *canp) {
if ((rf1r & CAN_RF1R_FMP1) > 0) {
/* No more receive events until the queue 0 has been emptied.*/
canp->can->IER &= ~CAN_IER_FMPIE1;
- chSysLockFromIsr();
- while (chSemGetCounterI(&canp->rxsem) < 0)
- chSemSignalI(&canp->rxsem);
- chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2));
- chSysUnlockFromIsr();
+ osalSysLockFromISR();
+ osalThreadDequeueAllI(&canp->rxqueue, MSG_OK);
+ osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2U));
+ osalSysUnlockFromISR();
}
if ((rf1r & CAN_RF1R_FOVR1) > 0) {
/* Overflow events handling.*/
canp->can->RF1R = CAN_RF1R_FOVR1;
- chSysLockFromIsr();
- chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
- chSysUnlockFromIsr();
+ osalSysLockFromISR();
+ osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
+ osalSysUnlockFromISR();
}
}
@@ -212,33 +308,39 @@ static void can_lld_rx1_handler(CANDriver *canp) {
static void can_lld_sce_handler(CANDriver *canp) {
uint32_t msr;
+ /* Clearing IRQ sources.*/
msr = canp->can->MSR;
- canp->can->MSR = CAN_MSR_ERRI | CAN_MSR_WKUI | CAN_MSR_SLAKI;
+ canp->can->MSR = msr;
+
/* Wakeup event.*/
#if CAN_USE_SLEEP_MODE
if (msr & CAN_MSR_WKUI) {
canp->state = CAN_READY;
canp->can->MCR &= ~CAN_MCR_SLEEP;
- chSysLockFromIsr();
- chEvtBroadcastI(&canp->wakeup_event);
- chSysUnlockFromIsr();
+ osalSysLockFromISR();
+ osalEventBroadcastFlagsI(&canp->wakeup_event, 0);
+ osalSysUnlockFromISR();
}
#endif /* CAN_USE_SLEEP_MODE */
/* Error event.*/
if (msr & CAN_MSR_ERRI) {
- flagsmask_t flags;
+ eventflags_t flags;
uint32_t esr = canp->can->ESR;
- canp->can->ESR &= ~CAN_ESR_LEC;
- flags = (flagsmask_t)(esr & 7);
+#if STM32_CAN_REPORT_ALL_ERRORS
+ flags = (eventflags_t)(esr & 7);
if ((esr & CAN_ESR_LEC) > 0)
flags |= CAN_FRAMING_ERROR;
+#else
+ flags = 0;
+#endif
- chSysLockFromIsr();
+ osalSysLockFromISR();
/* The content of the ESR register is copied unchanged in the upper
half word of the listener flags mask.*/
- chEvtBroadcastFlagsI(&canp->error_event, flags | (flagsmask_t)(esr << 16));
- chSysUnlockFromIsr();
+ osalEventBroadcastFlagsI(&canp->error_event,
+ flags | (eventflags_t)(esr << 16U));
+ osalSysUnlockFromISR();
}
}
@@ -247,32 +349,64 @@ static void can_lld_sce_handler(CANDriver *canp) {
/*===========================================================================*/
#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)
+#if defined(STM32_CAN1_UNIFIED_HANDLER)
+/**
+ * @brief CAN1 unified interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN1_UNIFIED_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND1);
+ can_lld_rx0_handler(&CAND1);
+ can_lld_rx1_handler(&CAND1);
+ can_lld_sce_handler(&CAND1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#else /* !defined(STM32_CAN1_UNIFIED_HANDLER) */
+
+#if !defined(STM32_CAN1_TX_HANDLER)
+#error "STM32_CAN1_TX_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN1_RX0_HANDLER)
+#error "STM32_CAN1_RX0_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN1_RX1_HANDLER)
+#error "STM32_CAN1_RX1_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN1_SCE_HANDLER)
+#error "STM32_CAN1_SCE_HANDLER not defined"
+#endif
+
/**
* @brief CAN1 TX interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
can_lld_tx_handler(&CAND1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
-/*
+/**
* @brief CAN1 RX0 interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
can_lld_rx0_handler(&CAND1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -280,13 +414,13 @@ CH_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
can_lld_rx1_handler(&CAND1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -294,43 +428,76 @@ CH_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
can_lld_sce_handler(&CAND1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_CAN1_UNIFIED_HANDLER) */
#endif /* STM32_CAN_USE_CAN1 */
#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)
+#if defined(STM32_CAN2_UNIFIED_HANDLER)
+/**
+ * @brief CAN1 unified interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN2_UNIFIED_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND2);
+ can_lld_rx0_handler(&CAND2);
+ can_lld_rx1_handler(&CAND2);
+ can_lld_sce_handler(&CAND2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#else /* !defined(STM32_CAN2_UNIFIED_HANDLER) */
+
+#if !defined(STM32_CAN1_TX_HANDLER)
+#error "STM32_CAN1_TX_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN1_RX0_HANDLER)
+#error "STM32_CAN1_RX0_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN1_RX1_HANDLER)
+#error "STM32_CAN1_RX1_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN1_SCE_HANDLER)
+#error "STM32_CAN1_SCE_HANDLER not defined"
+#endif
+
/**
* @brief CAN2 TX interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
can_lld_tx_handler(&CAND2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
-/*
+/**
* @brief CAN2 RX0 interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
can_lld_rx0_handler(&CAND2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -338,13 +505,13 @@ CH_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
can_lld_rx1_handler(&CAND2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -352,16 +519,108 @@ CH_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
can_lld_sce_handler(&CAND2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_CAN2_UNIFIED_HANDLER) */
#endif /* STM32_CAN_USE_CAN2 */
+#if STM32_CAN_USE_CAN3 || defined(__DOXYGEN__)
+#if defined(STM32_CAN3_UNIFIED_HANDLER)
+/**
+ * @brief CAN1 unified interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN3_UNIFIED_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND3);
+ can_lld_rx0_handler(&CAND3);
+ can_lld_rx1_handler(&CAND3);
+ can_lld_sce_handler(&CAND3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#else /* !defined(STM32_CAN3_UNIFIED_HANDLER) */
+
+#if !defined(STM32_CAN3_TX_HANDLER)
+#error "STM32_CAN3_TX_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN3_RX0_HANDLER)
+#error "STM32_CAN3_RX0_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN3_RX1_HANDLER)
+#error "STM32_CAN3_RX1_HANDLER not defined"
+#endif
+#if !defined(STM32_CAN3_SCE_HANDLER)
+#error "STM32_CAN3_SCE_HANDLER not defined"
+#endif
+
+/**
+ * @brief CAN3 TX interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN3_TX_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN3 RX0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN3_RX0_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ can_lld_rx0_handler(&CAND3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN1 RX3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN3_RX1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ can_lld_rx1_handler(&CAND3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN1 SCE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN3_SCE_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ can_lld_sce_handler(&CAND3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* !defined(STM32_CAN1_UNIFIED_HANDLER) */
+#endif /* STM32_CAN_USE_CAN1 */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -383,12 +642,23 @@ void can_lld_init(void) {
canObjectInit(&CAND2);
CAND2.can = CAN2;
#endif
+#if STM32_CAN_USE_CAN3
+ /* Driver initialization.*/
+ canObjectInit(&CAND3);
+ CAND3.can = CAN3;
+#endif
/* Filters initialization.*/
#if STM32_HAS_CAN2
- can_lld_set_filters(STM32_CAN_MAX_FILTERS / 2, 0, NULL);
+ can_lld_set_filters(&CAND1, STM32_CAN_MAX_FILTERS / 2, 0, NULL);
#else
- can_lld_set_filters(STM32_CAN_MAX_FILTERS, 0, NULL);
+ can_lld_set_filters(&CAND1, STM32_CAN_MAX_FILTERS, 0, NULL);
+#endif
+
+#if STM32_HAS_CAN3
+#if STM32_CAN_USE_CAN3
+ can_lld_set_filters(&CAND3, STM32_CAN3_MAX_FILTERS, 0, NULL);
+#endif
#endif
}
@@ -404,50 +674,68 @@ void can_lld_start(CANDriver *canp) {
/* Clock activation.*/
#if STM32_CAN_USE_CAN1
if (&CAND1 == canp) {
- nvicEnableVector(STM32_CAN1_TX_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
- nvicEnableVector(STM32_CAN1_RX0_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
- nvicEnableVector(STM32_CAN1_RX1_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
- nvicEnableVector(STM32_CAN1_SCE_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
+#if defined(STM32_CAN1_UNIFIED_NUMBER)
+ nvicEnableVector(STM32_CAN1_UNIFIED_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+#else
+ nvicEnableVector(STM32_CAN1_TX_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN1_RX0_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN1_RX1_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN1_SCE_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+#endif
rccEnableCAN1(FALSE);
}
#endif
+
#if STM32_CAN_USE_CAN2
if (&CAND2 == canp) {
- chDbgAssert(CAND1.state != CAN_STOP,
- "can_lld_start(), #1", "CAN1 must be started");
-
- nvicEnableVector(STM32_CAN2_TX_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
- nvicEnableVector(STM32_CAN2_RX0_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
- nvicEnableVector(STM32_CAN2_RX1_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
- nvicEnableVector(STM32_CAN2_SCE_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
+ osalDbgAssert(CAND1.state != CAN_STOP, "CAN1 must be started");
+
+#if defined(STM32_CAN2_UNIFIED_NUMBER)
+ nvicEnableVector(STM32_CAN2_UNIFIED_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+#else
+ nvicEnableVector(STM32_CAN2_TX_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN2_RX0_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN2_RX1_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN2_SCE_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+#endif
rccEnableCAN2(FALSE);
}
#endif
- /* Entering initialization mode. */
- canp->state = CAN_STARTING;
+#if STM32_CAN_USE_CAN3
+ if (&CAND3 == canp) {
+#if defined(STM32_CAN3_UNIFIED_NUMBER)
+ nvicEnableVector(STM32_CAN3_UNIFIED_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY);
+#else
+ nvicEnableVector(STM32_CAN3_TX_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN3_RX0_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN3_RX1_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY);
+ nvicEnableVector(STM32_CAN3_SCE_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY);
+#endif
+ rccEnableCAN3(FALSE);
+ }
+#endif
+
+ /* Configuring CAN. */
canp->can->MCR = CAN_MCR_INRQ;
while ((canp->can->MSR & CAN_MSR_INAK) == 0)
- chThdSleepS(1);
- /* BTR initialization.*/
+ osalThreadSleepS(1);
canp->can->BTR = canp->config->btr;
- /* MCR initialization.*/
canp->can->MCR = canp->config->mcr;
/* Interrupt sources initialization.*/
+#if STM32_CAN_REPORT_ALL_ERRORS
canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE |
CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE |
CAN_IER_FOVIE0 | CAN_IER_FOVIE1;
+#else
+ canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
+ CAN_IER_WKUIE | CAN_IER_ERRIE |
+ CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE |
+ CAN_IER_FOVIE0 | CAN_IER_FOVIE1;
+#endif
}
/**
@@ -465,30 +753,54 @@ void can_lld_stop(CANDriver *canp) {
if (&CAND1 == canp) {
#if STM32_CAN_USE_CAN2
- chDbgAssert(CAND2.state == CAN_STOP,
- "can_lld_stop(), #1", "CAN2 must be stopped");
+ osalDbgAssert(CAND2.state == CAN_STOP, "CAN2 must be stopped");
#endif
CAN1->MCR = 0x00010002; /* Register reset value. */
CAN1->IER = 0x00000000; /* All sources disabled. */
+#if defined(STM32_CAN1_UNIFIED_NUMBER)
+ nvicDisableVector(STM32_CAN1_UNIFIED_NUMBER);
+#else
nvicDisableVector(STM32_CAN1_TX_NUMBER);
nvicDisableVector(STM32_CAN1_RX0_NUMBER);
nvicDisableVector(STM32_CAN1_RX1_NUMBER);
nvicDisableVector(STM32_CAN1_SCE_NUMBER);
+#endif
rccDisableCAN1(FALSE);
}
#endif
+
#if STM32_CAN_USE_CAN2
if (&CAND2 == canp) {
CAN2->MCR = 0x00010002; /* Register reset value. */
CAN2->IER = 0x00000000; /* All sources disabled. */
+#if defined(STM32_CAN2_UNIFIED_NUMBER)
+ nvicDisableVector(STM32_CAN2_UNIFIED_NUMBER);
+#else
nvicDisableVector(STM32_CAN2_TX_NUMBER);
nvicDisableVector(STM32_CAN2_RX0_NUMBER);
nvicDisableVector(STM32_CAN2_RX1_NUMBER);
nvicDisableVector(STM32_CAN2_SCE_NUMBER);
+#endif
rccDisableCAN2(FALSE);
}
#endif
+
+#if STM32_CAN_USE_CAN3
+ if (&CAND3 == canp) {
+ CAN3->MCR = 0x00010002; /* Register reset value. */
+ CAN3->IER = 0x00000000; /* All sources disabled. */
+#if defined(STM32_CAN3_UNIFIED_NUMBER)
+ nvicDisableVector(STM32_CAN3_UNIFIED_NUMBER);
+#else
+ nvicDisableVector(STM32_CAN3_TX_NUMBER);
+ nvicDisableVector(STM32_CAN3_RX0_NUMBER);
+ nvicDisableVector(STM32_CAN3_RX1_NUMBER);
+ nvicDisableVector(STM32_CAN3_SCE_NUMBER);
+#endif
+ rccDisableCAN3(FALSE);
+ }
+#endif
}
}
@@ -504,7 +816,7 @@ void can_lld_stop(CANDriver *canp) {
*
* @notapi
*/
-bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
+bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
switch (mailbox) {
case CAN_ANY_MAILBOX:
@@ -577,7 +889,7 @@ void can_lld_transmit(CANDriver *canp,
*
* @notapi
*/
-bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
+bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
switch (mailbox) {
case CAN_ANY_MAILBOX:
@@ -694,6 +1006,7 @@ void can_lld_wakeup(CANDriver *canp) {
* @brief Programs the filters.
* @note This is an STM32-specific API.
*
+ * @param[in] canp pointer to the @p CANDriver object
* @param[in] can2sb number of the first filter assigned to CAN2
* @param[in] num number of entries in the filters array, if zero then
* a default filter is programmed
@@ -702,22 +1015,34 @@ void can_lld_wakeup(CANDriver *canp) {
*
* @api
*/
-void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp) {
+void canSTM32SetFilters(CANDriver *canp, uint32_t can2sb,
+ uint32_t num, const CANFilter *cfp) {
- chDbgCheck((can2sb >= 1) && (can2sb < STM32_CAN_MAX_FILTERS) &&
- (num <= STM32_CAN_MAX_FILTERS),
- "canSTM32SetFilters");
+#if STM32_CAN_USE_CAN2
+ osalDbgCheck((can2sb <= STM32_CAN_MAX_FILTERS) &&
+ (num <= STM32_CAN_MAX_FILTERS));
+#endif
#if STM32_CAN_USE_CAN1
- chDbgAssert(CAND1.state == CAN_STOP,
- "canSTM32SetFilters(), #1", "invalid state");
+ osalDbgAssert(CAND1.state == CAN_STOP, "invalid state");
#endif
#if STM32_CAN_USE_CAN2
- chDbgAssert(CAND2.state == CAN_STOP,
- "canSTM32SetFilters(), #2", "invalid state");
+ osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");
+#endif
+#if STM32_CAN_USE_CAN3
+ osalDbgAssert(CAND3.state == CAN_STOP, "invalid state");
#endif
- can_lld_set_filters(can2sb, num, cfp);
+#if STM32_CAN_USE_CAN1
+ if(canp == &CAND1) {
+ can_lld_set_filters(canp, can2sb, num, cfp);
+ }
+#endif
+#if STM32_CAN_USE_CAN3
+ if(canp == &CAND3) {
+ can_lld_set_filters(canp, can2sb, num, cfp);
+ }
+#endif
}
#endif /* HAL_USE_CAN */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/can_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.h
similarity index 80%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/can_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.h
index 7a037c4a35..3e3d2e7130 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/can_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/can_lld.h
+ * @file CANv1/hal_can_lld.h
* @brief STM32 CAN subsystem low level driver header.
*
* @addtogroup CAN
* @{
*/
-#ifndef _CAN_LLD_H_
-#define _CAN_LLD_H_
+#ifndef HAL_CAN_LLD_H
+#define HAL_CAN_LLD_H
#if HAL_USE_CAN || defined(__DOXYGEN__)
@@ -80,6 +80,14 @@
* @name Configuration options
* @{
*/
+/**
+ * @brief CAN pedantic errors report.
+ * @details Use of this option is IRQ-intensive.
+ */
+#if !defined(STM32_CAN_REPORT_ALL_ERRORS) || defined(__DOXYGEN__)
+#define STM32_CAN_REPORT_ALL_ERRORS FALSE
+#endif
+
/**
* @brief CAN1 driver enable switch.
* @details If set to @p TRUE the support for CAN1 is included.
@@ -96,6 +104,14 @@
#define STM32_CAN_USE_CAN2 FALSE
#endif
+/**
+ * @brief CAN3 driver enable switch.
+ * @details If set to @p TRUE the support for CAN3 is included.
+ */
+#if !defined(STM32_CAN_USE_CAN3) || defined(__DOXYGEN__)
+#define STM32_CAN_USE_CAN3 FALSE
+#endif
+
/**
* @brief CAN1 interrupt priority level setting.
*/
@@ -112,10 +128,38 @@
#endif
/** @} */
+/**
+ * @brief CAN3 interrupt priority level setting.
+ */
+#if !defined(STM32_CAN_CAN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_CAN_CAN3_IRQ_PRIORITY 11
+#endif
+/** @} */
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+#if !defined(STM32_HAS_CAN1)
+#error "STM32_HAS_CAN1 not defined in registry"
+#endif
+
+#if !defined(STM32_HAS_CAN2)
+#error "STM32_HAS_CAN2 not defined in registry"
+#endif
+
+#if !defined(STM32_HAS_CAN3)
+#error "STM32_HAS_CAN3 not defined in registry"
+#endif
+
+#if (STM32_HAS_CAN1 | STM32_HAS_CAN2) && !defined(STM32_CAN_MAX_FILTERS)
+#error "STM32_CAN_MAX_FILTERS not defined in registry"
+#endif
+
+#if STM32_HAS_CAN3 && !defined(STM32_CAN3_MAX_FILTERS)
+#error "STM32_CAN3_MAX_FILTERS not defined in registry"
+#endif
+
#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1
#error "CAN1 not present in the selected device"
#endif
@@ -124,7 +168,11 @@
#error "CAN2 not present in the selected device"
#endif
-#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2
+#if STM32_CAN_USE_CAN3 && !STM32_HAS_CAN3
+#error "CAN2 not present in the selected device"
+#endif
+
+#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2 && !STM32_CAN_USE_CAN3
#error "CAN driver activated but no CAN peripheral assigned"
#endif
@@ -168,6 +216,7 @@ typedef struct {
uint8_t data8[8]; /**< @brief Frame data. */
uint16_t data16[4]; /**< @brief Frame data. */
uint32_t data32[2]; /**< @brief Frame data. */
+ uint64_t data64[1]; /**< @brief Frame data. */
};
} CANTxFrame;
@@ -198,6 +247,7 @@ typedef struct {
uint8_t data8[8]; /**< @brief Frame data. */
uint16_t data16[4]; /**< @brief Frame data. */
uint32_t data32[2]; /**< @brief Frame data. */
+ uint64_t data64[1]; /**< @brief Frame data. */
};
} CANRxFrame;
@@ -269,48 +319,52 @@ typedef struct {
*/
const CANConfig *config;
/**
- * @brief Transmission queue semaphore.
+ * @brief Transmission threads queue.
*/
- Semaphore txsem;
+ threads_queue_t txqueue;
/**
- * @brief Receive queue semaphore.
+ * @brief Receive threads queue.
*/
- Semaphore rxsem;
+ threads_queue_t rxqueue;
/**
* @brief One or more frames become available.
* @note After broadcasting this event it will not be broadcasted again
* until the received frames queue has been completely emptied. It
* is not broadcasted for each received frame. It is
* responsibility of the application to empty the queue by
- * repeatedly invoking @p chReceive() when listening to this event.
+ * repeatedly invoking @p canReceive() when listening to this event.
* This behavior minimizes the interrupt served by the system
* because CAN traffic.
* @note The flags associated to the listeners will indicate which
* receive mailboxes become non-empty.
*/
- EventSource rxfull_event;
+ event_source_t rxfull_event;
/**
* @brief One or more transmission mailbox become available.
* @note The flags associated to the listeners will indicate which
* transmit mailboxes become empty.
+ * @note The upper 16 bits are transmission error flags associated
+ * to the transmit mailboxes.
*
*/
- EventSource txempty_event;
+ event_source_t txempty_event;
/**
* @brief A CAN bus error happened.
- * @note The flags associated to the listeners will indicate the
- * error(s) that have occurred.
+ * @note The flags associated to the listeners will indicate that
+ * receive error(s) have occurred.
+ * @note In this implementation the upper 16 bits are filled with the
+ * unprocessed content of the ESR register.
*/
- EventSource error_event;
+ event_source_t error_event;
#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
/**
* @brief Entering sleep state event.
*/
- EventSource sleep_event;
+ event_source_t sleep_event;
/**
* @brief Exiting sleep state event.
*/
- EventSource wakeup_event;
+ event_source_t wakeup_event;
#endif /* CAN_USE_SLEEP_MODE */
/* End of the mandatory fields.*/
/**
@@ -335,19 +389,21 @@ extern CANDriver CAND1;
extern CANDriver CAND2;
#endif
+#if STM32_CAN_USE_CAN3 && !defined(__DOXYGEN__)
+extern CANDriver CAND3;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
void can_lld_init(void);
void can_lld_start(CANDriver *canp);
void can_lld_stop(CANDriver *canp);
- bool_t can_lld_is_tx_empty(CANDriver *canp,
- canmbx_t mailbox);
+ bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox);
void can_lld_transmit(CANDriver *canp,
canmbx_t mailbox,
const CANTxFrame *crfp);
- bool_t can_lld_is_rx_nonempty(CANDriver *canp,
- canmbx_t mailbox);
+ bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox);
void can_lld_receive(CANDriver *canp,
canmbx_t mailbox,
CANRxFrame *ctfp);
@@ -355,13 +411,14 @@ extern "C" {
void can_lld_sleep(CANDriver *canp);
void can_lld_wakeup(CANDriver *canp);
#endif /* CAN_USE_SLEEP_MODE */
- void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp);
+ void canSTM32SetFilters(CANDriver *canp, uint32_t can2sb,
+ uint32_t num, const CANFilter *cfp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_CAN */
-#endif /* _CAN_LLD_H_ */
+#endif /* HAL_CAN_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/driver.mk
new file mode 100644
index 0000000000..7807214bac
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
new file mode 100644
index 0000000000..8b096642ed
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
@@ -0,0 +1,536 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file DACv1/hal_dac_lld.c
+ * @brief STM32 DAC subsystem low level driver source.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_DAC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/* Because ST headers naming inconsistencies.*/
+#if !defined(DAC1)
+#define DAC1 DAC
+#endif
+
+#define DAC1_CH1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH1_DMA_STREAM, \
+ STM32_DAC1_CH1_DMA_CHN)
+
+#define DAC1_CH2_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH2_DMA_STREAM, \
+ STM32_DAC1_CH2_DMA_CHN)
+
+#define DAC2_CH1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH1_DMA_STREAM, \
+ STM32_DAC2_CH1_DMA_CHN)
+
+#define DAC2_CH2_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \
+ STM32_DAC2_CH2_DMA_CHN)
+
+#define CHANNEL_DATA_OFFSET 3U
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief DAC1 CH1 driver identifier.*/
+#if STM32_DAC_USE_DAC1_CH1 || defined(__DOXYGEN__)
+DACDriver DACD1;
+#endif
+
+/** @brief DAC1 CH2 driver identifier.*/
+#if (STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
+DACDriver DACD2;
+#endif
+
+/** @brief DAC2 CH1 driver identifier.*/
+#if STM32_DAC_USE_DAC2_CH1 || defined(__DOXYGEN__)
+DACDriver DACD3;
+#endif
+
+/** @brief DAC2 CH2 driver identifier.*/
+#if (STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
+DACDriver DACD4;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+#if STM32_DAC_USE_DAC1_CH1 == TRUE
+static const dacparams_t dma1_ch1_params = {
+ .dac = DAC1,
+ .dataoffset = 0U,
+ .regshift = 0U,
+ .regmask = 0xFFFF0000U,
+ .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
+ .dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE,
+ .dmairqprio = STM32_DAC_DAC1_CH1_IRQ_PRIORITY
+};
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 == TRUE
+static const dacparams_t dma1_ch2_params = {
+ .dac = DAC1,
+ .dataoffset = CHANNEL_DATA_OFFSET,
+ .regshift = 16U,
+ .regmask = 0x0000FFFFU,
+ .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
+ .dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE,
+ .dmairqprio = STM32_DAC_DAC1_CH2_IRQ_PRIORITY
+};
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 == TRUE
+static const dacparams_t dma2_ch1_params = {
+ .dac = DAC2,
+ .dataoffset = 0U,
+ .regshift = 0U,
+ .regmask = 0xFFFF0000U,
+ .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM),
+ .dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE,
+ .dmairqprio = STM32_DAC_DAC2_CH1_IRQ_PRIORITY
+};
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 == TRUE
+static const dacparams_t dma1_ch2_params = {
+ .dac = DAC2,
+ .dataoffset = CHANNEL_DATA_OFFSET,
+ .regshift = 16U,
+ .regmask = 0x0000FFFFU,
+ .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM),
+ .dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE,
+ .dmairqprio = STM32_DAC_DAC2_CH2_IRQ_PRIORITY
+};
+#endif
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Shared end/half-of-tx service routine.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
+
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ /* DMA errors handling.*/
+ _dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE);
+ }
+ else {
+ if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _dac_isr_half_code(dacp);
+ }
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _dac_isr_full_code(dacp);
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level DAC driver initialization.
+ *
+ * @notapi
+ */
+void dac_lld_init(void) {
+
+#if STM32_DAC_USE_DAC1_CH1
+ dacObjectInit(&DACD1);
+ DACD1.params = &dma1_ch1_params;
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2
+ dacObjectInit(&DACD2);
+ DACD2.params = &dma1_ch2_params;
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1
+ dacObjectInit(&DACD3);
+ DACD3.params = &dma2_ch1_params;
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2
+ dacObjectInit(&DACD4);
+ DACD4.params = &dma2_ch2_params;
+#endif
+}
+
+/**
+ * @brief Configures and activates the DAC peripheral.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_start(DACDriver *dacp) {
+
+ /* If the driver is in DAC_STOP state then a full initialization is
+ required.*/
+ if (dacp->state == DAC_STOP) {
+ dacchannel_t channel = 0;
+
+ /* Enabling the clock source.*/
+#if STM32_DAC_USE_DAC1_CH1
+ if (&DACD1 == dacp) {
+ rccEnableDAC1(false);
+ }
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2
+ if (&DACD2 == dacp) {
+ rccEnableDAC1(false);
+ channel = 1;
+ }
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1
+ if (&DACD3 == dacp) {
+ rccEnableDAC2(false);
+ }
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2
+ if (&DACD4 == dacp) {
+ rccEnableDAC2(false);
+ channel = 1;
+ }
+#endif
+ /* Enabling DAC in SW triggering mode initially, initializing data to
+ zero.*/
+#if STM32_DAC_DUAL_MODE == FALSE
+ dacp->params->dac->CR &= dacp->params->regmask;
+ dacp->params->dac->CR |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
+ dac_lld_put_channel(dacp, channel, dacp->config->init);
+#else
+ if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
+ (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
+ (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
+ dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) | DAC_CR_EN1 | dacp->config->cr;
+ dac_lld_put_channel(dacp, 1U, dacp->config->init);
+ }
+ else {
+ dacp->params->dac->CR = DAC_CR_EN1 | dacp->config->cr;
+ }
+ dac_lld_put_channel(dacp, channel, dacp->config->init);
+#endif
+ }
+}
+
+/**
+ * @brief Deactivates the DAC peripheral.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_stop(DACDriver *dacp) {
+
+ /* If in ready state then disables the DAC clock.*/
+ if (dacp->state == DAC_READY) {
+
+ /* Disabling DAC.*/
+ dacp->params->dac->CR &= dacp->params->regmask;
+
+#if STM32_DAC_USE_DAC1_CH1
+ if (&DACD1 == dacp) {
+ if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
+ rccDisableDAC1(false);
+ }
+ }
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2
+ if (&DACD2 == dacp) {
+ if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
+ rccDisableDAC1(false);
+ }
+ }
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1
+ if (&DACD3 == dacp) {
+ if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
+ rccDisableDAC2(false);
+ }
+ }
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2
+ if (&DACD4 == dacp) {
+ if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
+ rccDisableDAC2(false);
+ }
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Outputs a value directly on a DAC channel.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] channel DAC channel number
+ * @param[in] sample value to be output
+ *
+ * @api
+ */
+void dac_lld_put_channel(DACDriver *dacp,
+ dacchannel_t channel,
+ dacsample_t sample) {
+
+ switch (dacp->config->datamode) {
+ case DAC_DHRM_12BIT_RIGHT:
+#if STM32_DAC_DUAL_MODE
+ case DAC_DHRM_12BIT_RIGHT_DUAL:
+#endif
+ if (channel == 0U) {
+#if STM32_DAC_DUAL_MODE
+ dacp->params->dac->DHR12R1 = (uint32_t)sample;
+#else
+ *(&dacp->params->dac->DHR12R1 + dacp->params->dataoffset) = (uint32_t)sample;
+#endif
+ }
+#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2)
+ else {
+ dacp->params->dac->DHR12R2 = (uint32_t)sample;
+ }
+#endif
+ break;
+ case DAC_DHRM_12BIT_LEFT:
+#if STM32_DAC_DUAL_MODE
+ case DAC_DHRM_12BIT_LEFT_DUAL:
+#endif
+ if (channel == 0U) {
+#if STM32_DAC_DUAL_MODE
+ dacp->params->dac->DHR12L1 = (uint32_t)sample;
+#else
+ *(&dacp->params->dac->DHR12L1 + dacp->params->dataoffset) = (uint32_t)sample;
+#endif
+ }
+#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2)
+ else {
+ dacp->params->dac->DHR12L2 = (uint32_t)sample;
+ }
+#endif
+ break;
+ case DAC_DHRM_8BIT_RIGHT:
+#if STM32_DAC_DUAL_MODE
+ case DAC_DHRM_8BIT_RIGHT_DUAL:
+#endif
+ if (channel == 0U) {
+#if STM32_DAC_DUAL_MODE
+ dacp->params->dac->DHR8R1 = (uint32_t)sample;
+#else
+ *(&dacp->params->dac->DHR8R1 + dacp->params->dataoffset) = (uint32_t)sample;
+#endif
+ }
+#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2)
+ else {
+ dacp->params->dac->DHR8R2 = (uint32_t)sample;
+ }
+#endif
+ break;
+ default:
+ osalDbgAssert(false, "unexpected DAC mode");
+ break;
+ }
+}
+
+/**
+ * @brief Starts a DAC conversion.
+ * @details Starts an asynchronous conversion operation.
+ * @note In @p DAC_DHRM_8BIT_RIGHT mode the parameters passed to the
+ * callback are wrong because two samples are packed in a single
+ * dacsample_t element. This will not be corrected, do not rely
+ * on those parameters.
+ * @note In @p DAC_DHRM_8BIT_RIGHT_DUAL mode two samples are treated
+ * as a single 16 bits sample and packed into a single dacsample_t
+ * element. The num_channels must be set to one in the group
+ * conversion configuration structure.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_start_conversion(DACDriver *dacp) {
+ uint32_t n, cr, dmamode;
+
+ /* Number of DMA operations per buffer.*/
+ n = dacp->depth * dacp->grpp->num_channels;
+
+ /* Allocating the DMA channel.*/
+ bool b = dmaStreamAllocate(dacp->params->dma, dacp->params->dmairqprio,
+ (stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
+ (void *)dacp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* DMA settings depend on the chosed DAC mode.*/
+ switch (dacp->config->datamode) {
+ /* Sets the DAC data register */
+ case DAC_DHRM_12BIT_RIGHT:
+ osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12R1 +
+ dacp->params->dataoffset);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+ break;
+ case DAC_DHRM_12BIT_LEFT:
+ osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12L1 +
+ dacp->params->dataoffset);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+ break;
+ case DAC_DHRM_8BIT_RIGHT:
+ osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR8R1 +
+ dacp->params->dataoffset);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+
+ /* In this mode the size of the buffer is halved because two samples
+ packed in a single dacsample_t element.*/
+ n = (n + 1) / 2;
+ break;
+#if STM32_DAC_DUAL_MODE == TRUE
+ case DAC_DHRM_12BIT_RIGHT_DUAL:
+ osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12RD);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
+ n /= 2;
+ break;
+ case DAC_DHRM_12BIT_LEFT_DUAL:
+ osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12LD);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
+ n /= 2;
+ break;
+ case DAC_DHRM_8BIT_RIGHT_DUAL:
+ osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR8RD);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+ n /= 2;
+ break;
+#endif
+ default:
+ osalDbgAssert(false, "unexpected DAC mode");
+ return;
+ }
+
+ dmaStreamSetMemory0(dacp->params->dma, dacp->samples);
+ dmaStreamSetTransactionSize(dacp->params->dma, n);
+ dmaStreamSetMode(dacp->params->dma, dmamode |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
+ STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE);
+ dmaStreamEnable(dacp->params->dma);
+
+ /* DAC configuration.*/
+#if STM32_DAC_DUAL_MODE == FALSE
+ cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << 3) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr;
+ dacp->params->dac->CR &= dacp->params->regmask;
+ dacp->params->dac->CR |= cr << dacp->params->regshift;
+#else
+ dacp->params->dac->CR = 0;
+ cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << 3) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr
+ | (dacp->grpp->trigger << 19) | DAC_CR_TEN2 | DAC_CR_EN2 | (dacp->config->cr << 16);
+ dacp->params->dac->CR = cr;
+#endif
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ * @details This function stops the currently ongoing conversion and returns
+ * the driver in the @p DAC_READY state. If there was no conversion
+ * being processed then the function does nothing.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @iclass
+ */
+void dac_lld_stop_conversion(DACDriver *dacp) {
+
+ /* DMA channel disabled and released.*/
+ dmaStreamDisable(dacp->params->dma);
+ dmaStreamRelease(dacp->params->dma);
+
+#if STM32_DAC_DUAL_MODE == FALSE
+ dacp->params->dac->CR &= dacp->params->regmask;
+ dacp->params->dac->CR |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
+#else
+ if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
+ (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
+ (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
+ dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) | DAC_CR_EN1 | dacp->config->cr;
+ }
+ else {
+ dacp->params->dac->CR = DAC_CR_EN1 | dacp->config->cr;
+ }
+#endif
+}
+
+#endif /* HAL_USE_DAC */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
new file mode 100644
index 0000000000..604a0b8aa7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
@@ -0,0 +1,467 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file DACv1/hal_dac_lld.h
+ * @brief STM32 DAC subsystem low level driver header.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#ifndef HAL_DAC_LLD_H
+#define HAL_DAC_LLD_H
+
+#if HAL_USE_DAC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name DAC trigger modes
+ * @{
+ */
+#define DAC_TRG_MASK 7U
+#define DAC_TRG(n) (n)
+#define DAC_TRG_EXT 6U
+#define DAC_TRG_SW 7U
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Enables the DAC dual mode.
+ * @note In dual mode DAC second channels cannot be accessed individually.
+ */
+#if !defined(STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
+#define STM32_DAC_DUAL_MODE FALSE
+#endif
+
+/**
+ * @brief DAC1 CH1 driver enable switch.
+ * @details If set to @p TRUE the support for DAC1 channel 1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#endif
+
+/**
+ * @brief DAC1 CH2 driver enable switch.
+ * @details If set to @p TRUE the support for DAC1 channel 2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#endif
+
+/**
+ * @brief DAC2 CH1 driver enable switch.
+ * @details If set to @p TRUE the support for DAC2 channel 1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_DAC_USE_DAC2_CH1) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_DAC2_CH1 FALSE
+#endif
+
+/**
+ * @brief DAC2 CH2 driver enable switch.
+ * @details If set to @p TRUE the support for DAC2 channel 2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_DAC_USE_DAC2_CH2) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_DAC2_CH2 FALSE
+#endif
+
+/**
+ * @brief DAC1 CH1 interrupt priority level setting.
+ */
+#if !defined(STM32_DAC_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief DAC1 CH2 interrupt priority level setting.
+ */
+#if !defined(STM32_DAC_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief DAC2 CH1 interrupt priority level setting.
+ */
+#if !defined(STM32_DAC_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief DAC2 CH2 interrupt priority level setting.
+ */
+#if !defined(STM32_DAC_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC2_CH2_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_DAC_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief DAC1 CH2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_DAC_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief DAC2 CH1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_DAC_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief DAC2 CH2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_DAC_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_DAC_USE_DAC1_CH1 && !STM32_HAS_DAC1_CH1
+#error "DAC1 CH1 not present in the selected device"
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && !STM32_HAS_DAC1_CH2
+#error "DAC1 CH2 not present in the selected device"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 && !STM32_HAS_DAC2_CH1
+#error "DAC2 CH1 not present in the selected device"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 && !STM32_HAS_DAC2_CH2
+#error "DAC2 CH2 not present in the selected device"
+#endif
+
+#if (STM32_DAC_USE_DAC1_CH2 || STM32_DAC_USE_DAC2_CH2) && STM32_DAC_DUAL_MODE
+#error "DACx CH2 cannot be used independently in dual mode"
+#endif
+
+#if !STM32_DAC_USE_DAC1_CH1 && !STM32_DAC_USE_DAC1_CH2 && \
+ !STM32_DAC_USE_DAC2_CH1 && !STM32_DAC_USE_DAC2_CH2
+#error "DAC driver activated but no DAC peripheral assigned"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_STREAM)
+#error "DAC1 CH1 DMA stream not defined"
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC_DAC1_CH2_DMA_STREAM)
+#error "DAC1 CH2 DMA stream not defined"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC_DAC2_CH1_DMA_STREAM)
+#error "DAC2 CH1 DMA stream not defined"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC_DAC2_CH2_DMA_STREAM)
+#error "DAC2 CH2 DMA stream not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_DAC_USE_DAC1_CH1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
+#error "invalid DMA stream associated to DAC1 CH1"
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
+#error "invalid DMA stream associated to DAC1 CH2"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
+#error "invalid DMA stream associated to DAC2 CH1"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
+#error "invalid DMA stream associated to DAC2 CH2"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/**
+ * @brief Max DAC channels.
+ */
+#if STM32_DAC_DUAL_MODE == FALSE
+#define DAC_MAX_CHANNELS 1
+#else
+#define DAC_MAX_CHANNELS 2
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a DAC channel index.
+ */
+typedef uint32_t dacchannel_t;
+
+/**
+ * @brief DAC channel parameters type.
+ */
+typedef struct {
+ /**
+ * @brief Pointer to the DAC registers block.
+ */
+ DAC_TypeDef *dac;
+ /**
+ * @brief DAC data registers offset.
+ */
+ uint32_t dataoffset;
+ /**
+ * @brief DAC CR register bit offset.
+ */
+ uint32_t regshift;
+ /**
+ * @brief DAC CR register mask.
+ */
+ uint32_t regmask;
+ /**
+ * @brief Associated DMA.
+ */
+ const stm32_dma_stream_t *dma;
+ /**
+ * @brief Mode bits for the DMA.
+ */
+ uint32_t dmamode;
+ /**
+ * @brief DMA channel IRQ priority.
+ */
+ uint32_t dmairqprio;
+} dacparams_t;
+
+/**
+ * @brief Type of a structure representing an DAC driver.
+ */
+typedef struct DACDriver DACDriver;
+
+/**
+ * @brief Type representing a DAC sample.
+ */
+typedef uint16_t dacsample_t;
+
+/**
+ * @brief Possible DAC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ DAC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ DAC_ERR_UNDERFLOW = 1 /**< DAC overflow condition. */
+} dacerror_t;
+
+/**
+ * @brief DAC notification callback type.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object triggering the
+ * @param[in] buffer pointer to the next semi-buffer to be filled
+ * @param[in] n number of buffer rows available starting from @p buffer
+ * callback
+ */
+typedef void (*daccallback_t)(DACDriver *dacp, dacsample_t *buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*dacerrorcallback_t)(DACDriver *dacp, dacerror_t err);
+
+/**
+ * @brief Samples alignment and size mode.
+ */
+typedef enum {
+ DAC_DHRM_12BIT_RIGHT = 0,
+ DAC_DHRM_12BIT_LEFT = 1,
+ DAC_DHRM_8BIT_RIGHT = 2,
+#if STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
+ DAC_DHRM_12BIT_RIGHT_DUAL = 3,
+ DAC_DHRM_12BIT_LEFT_DUAL = 4,
+ DAC_DHRM_8BIT_RIGHT_DUAL = 5
+#endif
+} dacdhrmode_t;
+
+/**
+ * @brief DAC Conversion group structure.
+ */
+typedef struct {
+ /**
+ * @brief Number of DAC channels.
+ */
+ uint32_t num_channels;
+ /**
+ * @brief Operation complete callback or @p NULL.
+ */
+ daccallback_t end_cb;
+ /**
+ * @brief Error handling callback or @p NULL.
+ */
+ dacerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief DAC initialization data.
+ * @note This field contains the (not shifted) value to be put into the
+ * TSEL field of the DAC CR register during initialization. All
+ * other fields are handled internally.
+ */
+ uint32_t trigger;
+} DACConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Initial output on DAC channels.
+ */
+ dacsample_t init;
+ /**
+ * @brief DAC data holding register mode.
+ */
+ dacdhrmode_t datamode;
+ /**
+ * @brief DAC control register.
+ */
+ uint16_t cr;
+} DACConfig;
+
+/**
+ * @brief Structure representing a DAC driver.
+ */
+struct DACDriver {
+ /**
+ * @brief Driver state.
+ */
+ dacstate_t state;
+ /**
+ * @brief Conversion group.
+ */
+ const DACConversionGroup *grpp;
+ /**
+ * @brief Samples buffer pointer.
+ */
+ dacsample_t *samples;
+ /**
+ * @brief Samples buffer size.
+ */
+ uint16_t depth;
+ /**
+ * @brief Current configuration data.
+ */
+ const DACConfig *config;
+#if DAC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif /* DAC_USE_WAIT */
+#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#endif /* DAC_USE_MUTUAL_EXCLUSION */
+#if defined(DAC_DRIVER_EXT_FIELDS)
+ DAC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief DAC channel parameters.
+ */
+ const dacparams_t *params;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__)
+extern DACDriver DACD1;
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
+extern DACDriver DACD2;
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 && !defined(__DOXYGEN__)
+extern DACDriver DACD3;
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
+extern DACDriver DACD4;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void dac_lld_init(void);
+ void dac_lld_start(DACDriver *dacp);
+ void dac_lld_stop(DACDriver *dacp);
+ void dac_lld_put_channel(DACDriver *dacp,
+ dacchannel_t channel,
+ dacsample_t sample);
+ void dac_lld_start_conversion(DACDriver *dacp);
+ void dac_lld_stop_conversion(DACDriver *dacp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_DAC */
+
+#endif /* HAL_DAC_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/driver.mk
new file mode 100644
index 0000000000..b4be3ab9da
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/driver.mk
@@ -0,0 +1,2 @@
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/notes.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/notes.txt
new file mode 100644
index 0000000000..376c69fc7b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/notes.txt
@@ -0,0 +1,25 @@
+STM32 DMAv1 driver.
+
+Driver capability:
+
+- The driver supports the STM32 traditional DMA controller in the following
+ configurations: 5ch, 7ch, 7ch+5ch, 7ch+7ch.
+- Support for automatic the channel selection through the CSELR register.
+- For devices without CSELR register it is possible to select channels but
+ the SYSCFG CFGR register is not configured, the user has to configure it
+ before starting the DMA driver.
+- The driver supports shared ISR handlers with a quirk: the IRQ priority is
+ established by the first allocated channel among the channels sharing the
+ ISR.
+
+The file registry must export:
+
+STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other
+ drivers use it to enable checks on DMA
+ channels. Probably will be removed in the
+ future.
+STM32_DMA_SUPPORTS_CSELR - TRUE if the DMA have a CSELR register.
+STM32_DMAn_NUM_CHANNELS - Number of channels in DMAs "n" (1..2).
+STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x" (1..7). If the macro
+ is not exported then the ISR is not declared.
+STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x" (1..7).
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
new file mode 100644
index 0000000000..0e430be538
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
@@ -0,0 +1,570 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file DMAv1/stm32_dma.c
+ * @brief DMA helper driver code.
+ *
+ * @addtogroup STM32_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ * shared resource, this driver allows to allocate and free DMA
+ * streams at runtime in order to allow all the other device
+ * drivers to coordinate the access to the resource.
+ * @note The DMA ISR handlers are all declared into this module because
+ * sharing, the various device drivers can associate a callback to
+ * ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+ has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/**
+ * @brief Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK ((1U << STM32_DMA1_NUM_CHANNELS) - 1U)
+
+/**
+ * @brief Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK (((1U << STM32_DMA2_NUM_CHANNELS) - \
+ 1U) << STM32_DMA1_NUM_CHANNELS)
+
+/**
+ * @brief Post-reset value of the stream CCR register.
+ */
+#define STM32_DMA_CCR_RESET_VALUE 0x00000000U
+
+#if STM32_DMA_SUPPORTS_CSELR == TRUE
+
+#if defined(DMA1_CSELR)
+#define ADDR_DMA1_CSELR &DMA1_CSELR->CSELR
+#else
+#define ADDR_DMA1_CSELR &DMA1->CSELR
+#endif
+
+#if defined(DMA2_CSELR)
+#define ADDR_DMA2_CSELR &DMA2_CSELR->CSELR
+#else
+#define ADDR_DMA2_CSELR &DMA2->CSELR
+#endif
+
+#else /* !defined(DMA1_CSELR) */
+
+#define ADDR_DMA1_CSELR NULL
+#define ADDR_DMA2_CSELR NULL
+
+#endif /* !defined(DMA1_CSELR) */
+
+/*
+ * Default ISR collision masks.
+ */
+#if !defined(DMA1_CH1_CMASK)
+#define DMA1_CH1_CMASK 0x00000001U
+#endif
+
+#if !defined(DMA1_CH2_CMASK)
+#define DMA1_CH2_CMASK 0x00000002U
+#endif
+
+#if !defined(DMA1_CH3_CMASK)
+#define DMA1_CH3_CMASK 0x00000004U
+#endif
+
+#if !defined(DMA1_CH4_CMASK)
+#define DMA1_CH4_CMASK 0x00000008U
+#endif
+
+#if !defined(DMA1_CH5_CMASK)
+#define DMA1_CH5_CMASK 0x00000010U
+#endif
+
+#if !defined(DMA1_CH6_CMASK)
+#define DMA1_CH6_CMASK 0x00000020U
+#endif
+
+#if !defined(DMA1_CH7_CMASK)
+#define DMA1_CH7_CMASK 0x00000040U
+#endif
+
+#if !defined(DMA2_CH1_CMASK)
+#define DMA2_CH1_CMASK 0x00000080U
+#endif
+
+#if !defined(DMA2_CH2_CMASK)
+#define DMA2_CH2_CMASK 0x00000100U
+#endif
+
+#if !defined(DMA2_CH3_CMASK)
+#define DMA2_CH3_CMASK 0x00000200U
+#endif
+
+#if !defined(DMA2_CH4_CMASK)
+#define DMA2_CH4_CMASK 0x00000400U
+#endif
+
+#if !defined(DMA2_CH5_CMASK)
+#define DMA2_CH5_CMASK 0x00000800U
+#endif
+
+#if !defined(DMA2_CH6_CMASK)
+#define DMA2_CH6_CMASK 0x00001000U
+#endif
+
+#if !defined(DMA2_CH7_CMASK)
+#define DMA2_CH7_CMASK 0x00002000U
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ * identifier and the involved physical registers.
+ * @note Don't use this array directly, use the appropriate wrapper macros
+ * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+ {DMA1, DMA1_Channel1, DMA1_CH1_CMASK, ADDR_DMA1_CSELR, 0, 0, STM32_DMA1_CH1_NUMBER},
+ {DMA1, DMA1_Channel2, DMA1_CH2_CMASK, ADDR_DMA1_CSELR, 4, 1, STM32_DMA1_CH2_NUMBER},
+ {DMA1, DMA1_Channel3, DMA1_CH3_CMASK, ADDR_DMA1_CSELR, 8, 2, STM32_DMA1_CH3_NUMBER},
+ {DMA1, DMA1_Channel4, DMA1_CH4_CMASK, ADDR_DMA1_CSELR, 12, 3, STM32_DMA1_CH4_NUMBER},
+ {DMA1, DMA1_Channel5, DMA1_CH5_CMASK, ADDR_DMA1_CSELR, 16, 4, STM32_DMA1_CH5_NUMBER},
+#if STM32_DMA1_NUM_CHANNELS > 5
+ {DMA1, DMA1_Channel6, DMA1_CH6_CMASK, ADDR_DMA1_CSELR, 20, 5, STM32_DMA1_CH6_NUMBER},
+#if STM32_DMA1_NUM_CHANNELS > 6
+ {DMA1, DMA1_Channel7, DMA1_CH7_CMASK, ADDR_DMA1_CSELR, 24, 6, STM32_DMA1_CH7_NUMBER},
+#if STM32_DMA2_NUM_CHANNELS > 0
+ {DMA2, DMA2_Channel1, DMA2_CH1_CMASK, ADDR_DMA2_CSELR, 0, 7, STM32_DMA2_CH1_NUMBER},
+ {DMA2, DMA2_Channel2, DMA2_CH2_CMASK, ADDR_DMA2_CSELR, 4, 8, STM32_DMA2_CH2_NUMBER},
+ {DMA2, DMA2_Channel3, DMA2_CH3_CMASK, ADDR_DMA2_CSELR, 8, 9, STM32_DMA2_CH3_NUMBER},
+ {DMA2, DMA2_Channel4, DMA2_CH4_CMASK, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER},
+ {DMA2, DMA2_Channel5, DMA2_CH5_CMASK, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER},
+#if STM32_DMA2_NUM_CHANNELS > 5
+ {DMA2, DMA2_Channel6, DMA2_CH6_CMASK, ADDR_DMA2_CSELR, 20, 12, STM32_DMA2_CH6_NUMBER},
+#if STM32_DMA2_NUM_CHANNELS > 6
+ {DMA2, DMA2_Channel7, DMA2_CH7_CMASK, ADDR_DMA2_CSELR, 24, 13, STM32_DMA2_CH7_NUMBER},
+#endif
+#endif
+#endif
+#endif
+#endif
+};
+
+/**
+ * @brief DMA IRQ redirectors.
+ */
+dma_isr_redir_t _stm32_dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Masks regarding the allocated streams.
+ */
+static struct {
+ /**
+ * @brief Mask of the enabled streams.
+ */
+ uint32_t streams_mask;
+ /**
+ * @brief Mask of the enabled stream ISRs.
+ */
+ uint32_t isr_mask;
+} dma;
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if defined(STM32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 stream 1 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA1_STREAM1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 stream 2 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA1_STREAM2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 stream 3 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA1_STREAM3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 stream 4 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA1_STREAM4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA1_CH5_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 stream 5 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA1_STREAM5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA1_CH6_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 stream 6 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA1_STREAM6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA1_CH7_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 stream 7 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA1_STREAM7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA2_CH1_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 stream 1 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA2_STREAM1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA2_CH2_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 stream 2 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA2_STREAM2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA2_CH3_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 stream 3 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA2_STREAM3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA2_CH4_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 stream 4 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA2_STREAM4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA2_CH5_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 stream 5 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA2_STREAM5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA2_CH6_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 stream 6 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA2_STREAM6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA2_CH7_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 stream 7 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ dmaServeInterrupt(STM32_DMA2_STREAM7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+ int i;
+
+ dma.streams_mask = 0U;
+ dma.isr_mask = 0U;
+ for (i = 0; i < STM32_DMA_STREAMS; i++) {
+ _stm32_dma_streams[i].channel->CCR = 0U;
+ _stm32_dma_isr_redir[i].dma_func = NULL;
+ }
+ DMA1->IFCR = 0xFFFFFFFFU;
+#if STM32_DMA2_NUM_CHANNELS > 0
+ DMA2->IFCR = 0xFFFFFFFFU;
+#endif
+}
+
+/**
+ * @brief Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ * The function also enables the IRQ vector associated to the stream
+ * and initializes its priority.
+ * @pre The stream must not be already in use or an error is returned.
+ * @post The stream is allocated and the default ISR handler redirected
+ * to the specified function.
+ * @post The stream ISR vector is enabled and its priority configured.
+ * @post The stream must be freed using @p dmaStreamRelease() before it can
+ * be reused with another peripheral.
+ * @post The stream is in its post-reset state.
+ * @note This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] priority IRQ priority for the DMA stream
+ * @param[in] func handling function pointer, can be @p NULL
+ * @param[in] param a parameter to be passed to the handling function
+ * @return The operation status.
+ * @retval false no error, stream taken.
+ * @retval true error, stream already taken.
+ *
+ * @special
+ */
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+ uint32_t priority,
+ stm32_dmaisr_t func,
+ void *param) {
+
+ osalDbgCheck(dmastp != NULL);
+
+ /* Checks if the stream is already taken.*/
+ if ((dma.streams_mask & (1U << dmastp->selfindex)) != 0U)
+ return true;
+
+ /* Installs the DMA handler.*/
+ _stm32_dma_isr_redir[dmastp->selfindex].dma_func = func;
+ _stm32_dma_isr_redir[dmastp->selfindex].dma_param = param;
+
+ /* Enabling DMA clocks required by the current streams set.*/
+ if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
+ rccEnableDMA1(false);
+ }
+#if STM32_DMA2_NUM_CHANNELS > 0
+ if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
+ rccEnableDMA2(false);
+ }
+#endif
+
+ /* Putting the stream in a safe state.*/
+ dmaStreamDisable(dmastp);
+ dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
+
+ /* Enables the associated IRQ vector if not already enabled and if a
+ callback is defined.*/
+ if (func != NULL) {
+ if ((dma.isr_mask & dmastp->cmask) == 0U) {
+ nvicEnableVector(dmastp->vector, priority);
+ }
+ dma.isr_mask |= (1U << dmastp->selfindex);
+ }
+
+ /* Marks the stream as allocated.*/
+ dma.streams_mask |= (1U << dmastp->selfindex);
+
+ return false;
+}
+
+/**
+ * @brief Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ * Trying to release a unallocated stream is an illegal operation
+ * and is trapped if assertions are enabled.
+ * @pre The stream must have been allocated using @p dmaStreamAllocate().
+ * @post The stream is again available.
+ * @note This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+ osalDbgCheck(dmastp != NULL);
+
+ /* Check if the streams is not taken.*/
+ osalDbgAssert((dma.streams_mask & (1 << dmastp->selfindex)) != 0U,
+ "not allocated");
+
+ /* Marks the stream as not allocated.*/
+ dma.streams_mask &= ~(1U << dmastp->selfindex);
+ dma.isr_mask &= ~(1U << dmastp->selfindex);
+
+ /* Disables the associated IRQ vector if it is no more in use.*/
+ if ((dma.streams_mask & dmastp->cmask) == 0U) {
+ nvicDisableVector(dmastp->vector);
+ }
+
+ /* Removes the DMA handler.*/
+ _stm32_dma_isr_redir[dmastp->selfindex].dma_func = NULL;
+ _stm32_dma_isr_redir[dmastp->selfindex].dma_param = NULL;
+
+ /* Shutting down clocks that are no more required, if any.*/
+ if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
+ rccDisableDMA1(false);
+ }
+#if STM32_DMA2_NUM_CHANNELS > 0
+ if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
+ rccDisableDMA2(false);
+ }
+#endif
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_dma.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h
similarity index 71%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_dma.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h
index 0f99ec51b0..f35a4b129b 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_dma.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,58 +15,67 @@
*/
/**
- * @file STM32F30x/stm32_dma.h
+ * @file DMAv1/stm32_dma.h
* @brief DMA helper driver header.
- * @note This file requires definitions from the ST header file stm32f30x.h.
* @note This driver uses the new naming convention used for the STM32F2xx
* so the "DMA channels" are referred as "DMA streams".
*
- * @addtogroup STM32F30x_DMA
+ * @addtogroup STM32_DMA
* @{
*/
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
+#ifndef STM32_DMA_H
+#define STM32_DMA_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
+/**
+ * @brief DMA capability.
+ * @details if @p TRUE then the DMA is able of burst transfers, FIFOs,
+ * scatter gather and other advanced features.
+ */
+#define STM32_DMA_ADVANCED FALSE
+
/**
* @brief Total number of DMA streams.
- * @note This is the total number of streams among all the DMA units.
+ * @details This is the total number of streams among all the DMA units.
*/
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-#define STM32_DMA_STREAMS 12
-#else
-#define STM32_DMA_STREAMS 7
-#endif
+#define STM32_DMA_STREAMS (STM32_DMA1_NUM_CHANNELS + \
+ STM32_DMA2_NUM_CHANNELS)
/**
* @brief Mask of the ISR bits passed to the DMA callback functions.
*/
-#define STM32_DMA_ISR_MASK 0x0F
+#define STM32_DMA_ISR_MASK 0x0E
/**
- * @brief Returns the channel associated to the specified stream.
+ * @brief From stream number to shift factor in @p ISR and @p IFCR registers.
+ */
+#define STM32_DMA_ISR_SHIFT(stream) (((stream) - 1U) * 4U)
+
+/**
+ * @brief Returns the request line associated to the specified stream.
+ * @note In some STM32 manuals the request line is named confusingly
+ * channel.
*
- * @param[in] n the stream number (0...STM32_DMA_STREAMS-1)
- * @param[in] c a stream/channel association word, one channel per
- * nibble, not associated channels must be set to 0xF
- * @return Always zero, in this platform there is no dynamic
- * association between streams and channels.
+ * @param[in] id the unique numeric stream identifier
+ * @param[in] c a stream/request association word, one request per
+ * nibble
+ * @return Returns the request associated to the stream.
*/
-#define STM32_DMA_GETCHANNEL(n, c) 0
+#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) % 7U) * 4U)) & 15U)
/**
* @brief Checks if a DMA priority is within the valid range.
* @param[in] prio DMA priority
*
* @retval The check result.
- * @retval FALSE invalid DMA priority.
- * @retval TRUE correct DMA priority.
+ * @retval false invalid DMA priority.
+ * @retval true correct DMA priority.
*/
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
/**
* @brief Returns an unique numeric identifier for a DMA stream.
@@ -75,7 +84,7 @@
* @param[in] stream the stream number
* @return An unique numeric stream identifier.
*/
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
+#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1U) * 7U) + ((stream) - 1U))
/**
* @brief Returns a DMA stream identifier mask.
@@ -86,18 +95,19 @@
* @return A DMA stream identifier mask.
*/
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
- (1 << STM32_DMA_STREAM_ID(dma, stream))
+ (1U << STM32_DMA_STREAM_ID(dma, stream))
/**
* @brief Checks if a DMA stream unique identifier belongs to a mask.
+ *
* @param[in] id the stream numeric identifier
* @param[in] mask the stream numeric identifiers mask
*
* @retval The check result.
- * @retval FALSE id does not belong to the mask.
- * @retval TRUE id belongs to the mask.
+ * @retval false id does not belong to the mask.
+ * @retval true id belongs to the mask.
*/
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
/**
* @name DMA streams identifiers
@@ -124,6 +134,8 @@
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9)
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10)
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11)
+#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(12)
+#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(13)
/** @} */
/**
@@ -135,41 +147,52 @@
#define STM32_DMA_CR_HTIE DMA_CCR_HTIE
#define STM32_DMA_CR_TCIE DMA_CCR_TCIE
#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M 0
+#define STM32_DMA_CR_DIR_P2M 0U
#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR
#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM
#define STM32_DMA_CR_CIRC DMA_CCR_CIRC
#define STM32_DMA_CR_PINC DMA_CCR_PINC
#define STM32_DMA_CR_MINC DMA_CCR_MINC
#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE 0
+#define STM32_DMA_CR_PSIZE_BYTE 0U
#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1
#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE 0
+#define STM32_DMA_CR_MSIZE_BYTE 0U
#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
STM32_DMA_CR_MSIZE_MASK)
#define STM32_DMA_CR_PL_MASK DMA_CCR_PL
-#define STM32_DMA_CR_PL(n) ((n) << 12)
+#define STM32_DMA_CR_PL(n) ((n) << 12U)
+/** @} */
+
+/**
+ * @name Request line selector macro
+ * @{
+ */
+#if STM32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__)
+#define STM32_DMA_CR_CHSEL_MASK (15U << 16U)
+#define STM32_DMA_CR_CHSEL(n) ((n) << 16U)
+#else
+#define STM32_DMA_CR_CHSEL_MASK 0U
+#define STM32_DMA_CR_CHSEL(n) 0U
+#endif
/** @} */
/**
* @name CR register constants only found in enhanced DMA
* @{
*/
-#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */
-#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
-#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
+#define STM32_DMA_CR_DMEIE 0U /**< @brief Ignored by normal DMA. */
/** @} */
/**
* @name Status flags passed to the ISR callbacks
* @{
*/
-#define STM32_DMA_ISR_FEIF 0
-#define STM32_DMA_ISR_DMEIF 0
+#define STM32_DMA_ISR_FEIF 0U
+#define STM32_DMA_ISR_DMEIF 0U
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
@@ -183,6 +206,18 @@
/* Derived constants and error checks. */
/*===========================================================================*/
+#if !defined(STM32_DMA_SUPPORTS_CSELR)
+#error "STM32_DMA_SUPPORTS_CSELR not defined in registry"
+#endif
+
+#if !defined(STM32_DMA1_NUM_CHANNELS)
+#error "STM32_DMA1_NUM_CHANNELS not defined in registry"
+#endif
+
+#if !defined(STM32_DMA2_NUM_CHANNELS)
+#error "STM32_DMA2_NUM_CHANNELS not defined in registry"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -191,10 +226,13 @@
* @brief STM32 DMA stream descriptor structure.
*/
typedef struct {
+ DMA_TypeDef *dma ; /**< @brief Associated DMA. */
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
- volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
- uint8_t ishift; /**< @brief Bits offset in xIFCR
- register. */
+ uint32_t cmask; /**< @brief Mask of streams sharing
+ the same ISR. */
+ volatile uint32_t *cselr; /**< @brief Associated CSELR reg. */
+ uint8_t shift; /**< @brief Bit offset in ISR, IFCR
+ and CSELR registers. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
} stm32_dma_stream_t;
@@ -208,6 +246,14 @@ typedef struct {
*/
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+/**
+ * @brief DMA ISR redirector type.
+ */
+typedef struct {
+ stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
+ void *dma_param; /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
@@ -285,9 +331,19 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
*
* @special
*/
+#if STM32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__)
+#define dmaStreamSetMode(dmastp, mode) { \
+ uint32_t cselr = *(dmastp)->cselr; \
+ cselr &= ~(0x0000000FU << (dmastp)->shift); \
+ cselr |= (((uint32_t)(mode) >> 16U) << (dmastp)->shift); \
+ *(dmastp)->cselr = cselr; \
+ (dmastp)->channel->CCR = (uint32_t)(mode); \
+}
+#else
#define dmaStreamSetMode(dmastp, mode) { \
(dmastp)->channel->CCR = (uint32_t)(mode); \
}
+#endif
/**
* @brief DMA stream enable.
@@ -334,7 +390,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
- *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
+ (dmastp)->dma->IFCR = STM32_DMA_ISR_MASK << (dmastp)->shift; \
}
/**
@@ -373,11 +429,28 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*/
#define dmaWaitCompletion(dmastp) { \
- while ((dmastp)->channel->CNDTR > 0) \
+ while ((dmastp)->channel->CNDTR > 0U) \
; \
dmaStreamDisable(dmastp); \
}
+/**
+ * @brief Serves a DMA IRQ.
+ *
+ * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ */
+#define dmaServeInterrupt(dmastp) { \
+ uint32_t flags; \
+ uint32_t idx = (dmastp)->selfindex; \
+ \
+ flags = ((dmastp)->dma->ISR >> (dmastp)->shift) & STM32_DMA_ISR_MASK; \
+ if (flags & (dmastp)->channel->CCR) { \
+ (dmastp)->dma->IFCR = flags << (dmastp)->shift; \
+ if (_stm32_dma_isr_redir[idx].dma_func) { \
+ _stm32_dma_isr_redir[idx].dma_func(_stm32_dma_isr_redir[idx].dma_param, flags); \
+ } \
+ } \
+}
/** @} */
/*===========================================================================*/
@@ -386,21 +459,22 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
#if !defined(__DOXYGEN__)
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+extern dma_isr_redir_t _stm32_dma_isr_redir[STM32_DMA_STREAMS];
#endif
#ifdef __cplusplus
extern "C" {
#endif
void dmaInit(void);
- bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param);
+ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+ uint32_t priority,
+ stm32_dmaisr_t func,
+ void *param);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
#ifdef __cplusplus
}
#endif
-#endif /* _STM32_DMA_H_ */
+#endif /* STM32_DMA_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/driver.mk
new file mode 100644
index 0000000000..0bc685374a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/driver.mk
@@ -0,0 +1,2 @@
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/notes.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/notes.txt
new file mode 100644
index 0000000000..7242e8e528
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/notes.txt
@@ -0,0 +1,20 @@
+STM32 DMAv2 driver.
+
+Driver capability:
+
+- The driver supports the STM32 enhanced DMA controller found on F2, F4 and
+ F7 sub-families.
+- Support for automatic the channel selection.
+- Support for cache flushing and invalidation.
+
+The file registry must export:
+
+STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other
+ drivers use it to enable checks on DMA
+ channels. Probably will be removed in the
+ future.
+STM32_HAS_DMAx - Support for DMA unit "x" (1..2).
+STM32_DMAx_CHn_HANDLER - Vector name for channel "n" (0..7).
+STM32_DMAn_CHx_NUMBER - Vector number for channel "n" (0..7).
+STM32_DMA_CACHE_HANDLING - TRUE if the device requires explicit cache
+ handling on DMA buffers.
\ No newline at end of file
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_dma.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c
similarity index 63%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_dma.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c
index a601e7c83b..d41fa00960 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_dma.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
*/
/**
- * @file STM32F4xx/stm32_dma.c
+ * @file DMAv2/stm32_dma.c
* @brief Enhanced DMA helper driver code.
*
- * @addtogroup STM32F4xx_DMA
+ * @addtogroup STM32_DMA
* @details DMA sharing helper driver. In the STM32 the DMA streams are a
* shared resource, this driver allows to allocate and free DMA
* streams at runtime in order to allow all the other device
@@ -29,7 +29,6 @@
* @{
*/
-#include "ch.h"
#include "hal.h"
/* The following macro is only defined if some driver requiring DMA services
@@ -43,22 +42,12 @@
/**
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
*/
-#define STM32_DMA1_STREAMS_MASK 0x000000FF
+#define STM32_DMA1_STREAMS_MASK 0x000000FFU
/**
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
*/
-#define STM32_DMA2_STREAMS_MASK 0x0000FF00
-
-/**
- * @brief Post-reset value of the stream CR register.
- */
-#define STM32_DMA_CR_RESET_VALUE 0x00000000
-
-/**
- * @brief Post-reset value of the stream FCR register.
- */
-#define STM32_DMA_FCR_RESET_VALUE 0x00000021
+#define STM32_DMA2_STREAMS_MASK 0x0000FF00U
/*===========================================================================*/
/* Driver exported variables. */
@@ -72,22 +61,22 @@
* instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
- {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn},
- {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn},
- {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn},
- {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn},
- {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn},
- {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn},
- {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn},
- {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn},
- {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn},
- {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn},
- {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn},
- {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn},
- {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn},
- {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn},
- {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn},
- {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn},
+ {DMA1_Stream0, &DMA1->LIFCR, 0, 0, STM32_DMA1_CH0_NUMBER},
+ {DMA1_Stream1, &DMA1->LIFCR, 6, 1, STM32_DMA1_CH1_NUMBER},
+ {DMA1_Stream2, &DMA1->LIFCR, 16, 2, STM32_DMA1_CH2_NUMBER},
+ {DMA1_Stream3, &DMA1->LIFCR, 22, 3, STM32_DMA1_CH3_NUMBER},
+ {DMA1_Stream4, &DMA1->HIFCR, 0, 4, STM32_DMA1_CH4_NUMBER},
+ {DMA1_Stream5, &DMA1->HIFCR, 6, 5, STM32_DMA1_CH5_NUMBER},
+ {DMA1_Stream6, &DMA1->HIFCR, 16, 6, STM32_DMA1_CH6_NUMBER},
+ {DMA1_Stream7, &DMA1->HIFCR, 22, 7, STM32_DMA1_CH7_NUMBER},
+ {DMA2_Stream0, &DMA2->LIFCR, 0, 8, STM32_DMA2_CH0_NUMBER},
+ {DMA2_Stream1, &DMA2->LIFCR, 6, 9, STM32_DMA2_CH1_NUMBER},
+ {DMA2_Stream2, &DMA2->LIFCR, 16, 10, STM32_DMA2_CH2_NUMBER},
+ {DMA2_Stream3, &DMA2->LIFCR, 22, 11, STM32_DMA2_CH3_NUMBER},
+ {DMA2_Stream4, &DMA2->HIFCR, 0, 12, STM32_DMA2_CH4_NUMBER},
+ {DMA2_Stream5, &DMA2->HIFCR, 6, 13, STM32_DMA2_CH5_NUMBER},
+ {DMA2_Stream6, &DMA2->HIFCR, 16, 14, STM32_DMA2_CH6_NUMBER},
+ {DMA2_Stream7, &DMA2->HIFCR, 22, 15, STM32_DMA2_CH7_NUMBER},
};
/*===========================================================================*/
@@ -125,17 +114,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
*
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA1_CH0_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 0;
+ flags = (DMA1->LISR >> 0U) & STM32_DMA_ISR_MASK;
+ DMA1->LIFCR = flags << 0U;
if (dma_isr_redir[0].dma_func)
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -143,17 +132,17 @@ CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 6;
+ flags = (DMA1->LISR >> 6U) & STM32_DMA_ISR_MASK;
+ DMA1->LIFCR = flags << 6U;
if (dma_isr_redir[1].dma_func)
dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -161,17 +150,17 @@ CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 16;
+ flags = (DMA1->LISR >> 16U) & STM32_DMA_ISR_MASK;
+ DMA1->LIFCR = flags << 16U;
if (dma_isr_redir[2].dma_func)
dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -179,17 +168,17 @@ CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 22;
+ flags = (DMA1->LISR >> 22U) & STM32_DMA_ISR_MASK;
+ DMA1->LIFCR = flags << 22U;
if (dma_isr_redir[3].dma_func)
dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -197,17 +186,17 @@ CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 0;
+ flags = (DMA1->HISR >> 0U) & STM32_DMA_ISR_MASK;
+ DMA1->HIFCR = flags << 0U;
if (dma_isr_redir[4].dma_func)
dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -215,17 +204,17 @@ CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 6;
+ flags = (DMA1->HISR >> 6U) & STM32_DMA_ISR_MASK;
+ DMA1->HIFCR = flags << 6U;
if (dma_isr_redir[5].dma_func)
dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -233,17 +222,17 @@ CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 16;
+ flags = (DMA1->HISR >> 16U) & STM32_DMA_ISR_MASK;
+ DMA1->HIFCR = flags << 16U;
if (dma_isr_redir[6].dma_func)
dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -251,17 +240,17 @@ CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 22;
+ flags = (DMA1->HISR >> 22U) & STM32_DMA_ISR_MASK;
+ DMA1->HIFCR = flags << 22U;
if (dma_isr_redir[7].dma_func)
dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -269,17 +258,17 @@ CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA2_CH0_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 0;
+ flags = (DMA2->LISR >> 0U) & STM32_DMA_ISR_MASK;
+ DMA2->LIFCR = flags << 0U;
if (dma_isr_redir[8].dma_func)
dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -287,17 +276,17 @@ CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 6;
+ flags = (DMA2->LISR >> 6U) & STM32_DMA_ISR_MASK;
+ DMA2->LIFCR = flags << 6U;
if (dma_isr_redir[9].dma_func)
dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -305,17 +294,17 @@ CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 16;
+ flags = (DMA2->LISR >> 16U) & STM32_DMA_ISR_MASK;
+ DMA2->LIFCR = flags << 16U;
if (dma_isr_redir[10].dma_func)
dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -323,17 +312,17 @@ CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 22;
+ flags = (DMA2->LISR >> 22U) & STM32_DMA_ISR_MASK;
+ DMA2->LIFCR = flags << 22U;
if (dma_isr_redir[11].dma_func)
dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -341,17 +330,17 @@ CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 0;
+ flags = (DMA2->HISR >> 0U) & STM32_DMA_ISR_MASK;
+ DMA2->HIFCR = flags << 0U;
if (dma_isr_redir[12].dma_func)
dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -359,17 +348,17 @@ CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 6;
+ flags = (DMA2->HISR >> 6U) & STM32_DMA_ISR_MASK;
+ DMA2->HIFCR = flags << 6U;
if (dma_isr_redir[13].dma_func)
dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -377,17 +366,17 @@ CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 16;
+ flags = (DMA2->HISR >> 16U) & STM32_DMA_ISR_MASK;
+ DMA2->HIFCR = flags << 16U;
if (dma_isr_redir[14].dma_func)
dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -395,17 +384,17 @@ CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 22;
+ flags = (DMA2->HISR >> 22U) & STM32_DMA_ISR_MASK;
+ DMA2->HIFCR = flags << 22U;
if (dma_isr_redir[15].dma_func)
dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
@@ -418,17 +407,17 @@ CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {
* @init
*/
void dmaInit(void) {
- int i;
+ unsigned i;
- dma_streams_mask = 0;
- for (i = 0; i < STM32_DMA_STREAMS; i++) {
- _stm32_dma_streams[i].stream->CR = 0;
+ dma_streams_mask = 0U;
+ for (i = 0U; i < STM32_DMA_STREAMS; i++) {
+ _stm32_dma_streams[i].stream->CR = 0U;
dma_isr_redir[i].dma_func = NULL;
}
- DMA1->LIFCR = 0xFFFFFFFF;
- DMA1->HIFCR = 0xFFFFFFFF;
- DMA2->LIFCR = 0xFFFFFFFF;
- DMA2->HIFCR = 0xFFFFFFFF;
+ DMA1->LIFCR = 0xFFFFFFFFU;
+ DMA1->HIFCR = 0xFFFFFFFFU;
+ DMA2->LIFCR = 0xFFFFFFFFU;
+ DMA2->HIFCR = 0xFFFFFFFFU;
}
/**
@@ -446,36 +435,38 @@ void dmaInit(void) {
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] priority IRQ priority mask for the DMA stream
+ * @param[in] priority IRQ priority for the DMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
- * @retval FALSE no error, stream taken.
- * @retval TRUE error, stream already taken.
+ * @retval false no error, stream taken.
+ * @retval true error, stream already taken.
*
* @special
*/
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param) {
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+ uint32_t priority,
+ stm32_dmaisr_t func,
+ void *param) {
- chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
+ osalDbgCheck(dmastp != NULL);
/* Checks if the stream is already taken.*/
- if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
- return TRUE;
+ if ((dma_streams_mask & (1U << dmastp->selfindex)) != 0U)
+ return true;
/* Marks the stream as allocated.*/
dma_isr_redir[dmastp->selfindex].dma_func = func;
dma_isr_redir[dmastp->selfindex].dma_param = param;
- dma_streams_mask |= (1 << dmastp->selfindex);
+ dma_streams_mask |= (1U << dmastp->selfindex);
/* Enabling DMA clocks required by the current streams set.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
- rccEnableDMA1(FALSE);
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
- rccEnableDMA2(FALSE);
+ if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) {
+ rccEnableDMA1(false);
+ }
+ if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) {
+ rccEnableDMA2(false);
+ }
/* Putting the stream in a safe state.*/
dmaStreamDisable(dmastp);
@@ -483,10 +474,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
/* Enables the associated IRQ vector if a callback is defined.*/
- if (func != NULL)
- nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
+ if (func != NULL) {
+ nvicEnableVector(dmastp->vector, priority);
+ }
- return FALSE;
+ return false;
}
/**
@@ -504,23 +496,25 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
- chDbgCheck(dmastp != NULL, "dmaStreamRelease");
+ osalDbgCheck(dmastp != NULL);
/* Check if the streams is not taken.*/
- chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
- "dmaStreamRelease(), #1", "not allocated");
+ osalDbgAssert((dma_streams_mask & (1U << dmastp->selfindex)) != 0U,
+ "not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector);
/* Marks the stream as not allocated.*/
- dma_streams_mask &= ~(1 << dmastp->selfindex);
+ dma_streams_mask &= ~(1U << dmastp->selfindex);
/* Shutting down clocks that are no more required, if any.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
- rccDisableDMA1(FALSE);
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
- rccDisableDMA2(FALSE);
+ if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
+ rccDisableDMA1(false);
+ }
+ if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
+ rccDisableDMA2(false);
+ }
}
#endif /* STM32_DMA_REQUIRED */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_dma.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
similarity index 66%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_dma.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
index 05e4927607..7a3e46c025 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_dma.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,32 +15,37 @@
*/
/**
- * @file STM32F4xx/stm32_dma.h
+ * @file DMAv2/stm32_dma.h
* @brief Enhanced-DMA helper driver header.
- * @note This file requires definitions from the ST STM32F4xx header file
- * stm32f4xx.h.
*
- * @addtogroup STM32F4xx_DMA
+ * @addtogroup STM32_DMA
* @{
*/
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
+#ifndef STM32_DMA_H
+#define STM32_DMA_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
+/**
+ * @brief DMA capability.
+ * @details if @p TRUE then the DMA is able of burst transfers, FIFOs,
+ * scatter gather and other advanced features.
+ */
+#define STM32_DMA_ADVANCED TRUE
+
/**
* @brief Total number of DMA streams.
- * @note This is the total number of streams among all the DMA units.
+ * @details This is the total number of streams among all the DMA units.
*/
-#define STM32_DMA_STREAMS 16
+#define STM32_DMA_STREAMS 16U
/**
* @brief Mask of the ISR bits passed to the DMA callback functions.
*/
-#define STM32_DMA_ISR_MASK 0x3D
+#define STM32_DMA_ISR_MASK 0x3DU
/**
* @brief Returns the channel associated to the specified stream.
@@ -50,7 +55,7 @@
* nibble
* @return Returns the channel associated to the stream.
*/
-#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7)
+#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7U) * 4U)) & 15U)
/**
* @brief Checks if a DMA priority is within the valid range.
@@ -60,7 +65,7 @@
* @retval FALSE invalid DMA priority.
* @retval TRUE correct DMA priority.
*/
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
/**
* @brief Returns an unique numeric identifier for a DMA stream.
@@ -69,7 +74,7 @@
* @param[in] stream the stream number
* @return An unique numeric stream identifier.
*/
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream))
+#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1U) * 8U) + (stream))
/**
* @brief Returns a DMA stream identifier mask.
@@ -80,7 +85,7 @@
* @return A DMA stream identifier mask.
*/
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
- (1 << STM32_DMA_STREAM_ID(dma, stream))
+ (1U << STM32_DMA_STREAM_ID(dma, stream))
/**
* @brief Checks if a DMA stream unique identifier belongs to a mask.
@@ -91,7 +96,7 @@
* @retval FALSE id does not belong to the mask.
* @retval TRUE id belongs to the mask.
*/
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
/**
* @name DMA streams identifiers
@@ -128,6 +133,7 @@
* @name CR register constants common to all DMA types
* @{
*/
+#define STM32_DMA_CR_RESET_VALUE 0x00000000U
#define STM32_DMA_CR_EN DMA_SxCR_EN
#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE
#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE
@@ -150,7 +156,7 @@
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
STM32_DMA_CR_MSIZE_MASK)
#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL
-#define STM32_DMA_CR_PL(n) ((n) << 16)
+#define STM32_DMA_CR_PL(n) ((n) << 16U)
/** @} */
/**
@@ -173,13 +179,14 @@
#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1
#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL
-#define STM32_DMA_CR_CHSEL(n) ((n) << 25)
+#define STM32_DMA_CR_CHSEL(n) ((n) << 25U)
/** @} */
/**
* @name FCR register constants only found in STM32F2xx/STM32F4xx
* @{
*/
+#define STM32_DMA_FCR_RESET_VALUE 0x00000021U
#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE
#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS
#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS
@@ -208,6 +215,146 @@
/* Derived constants and error checks. */
/*===========================================================================*/
+#if !defined(STM32_DMA_CACHE_HANDLING)
+#error "STM32_DMA_CACHE_HANDLING missing in registry"
+#endif
+
+#if !defined(STM32_HAS_DMA1)
+#error "STM32_HAS_DMA1 missing in registry"
+#endif
+
+#if !defined(STM32_HAS_DMA2)
+#error "STM32_HAS_DMA2 missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH0_HANDLER)
+#error "STM32_DMA1_CH0_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH1_HANDLER)
+#error "STM32_DMA1_CH1_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH2_HANDLER)
+#error "STM32_DMA1_CH2_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH3_HANDLER)
+#error "STM32_DMA1_CH3_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH4_HANDLER)
+#error "STM32_DMA1_CH4_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH5_HANDLER)
+#error "STM32_DMA1_CH5_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH6_HANDLER)
+#error "STM32_DMA1_CH6_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH7_HANDLER)
+#error "STM32_DMA1_CH7_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH0_HANDLER)
+#error "STM32_DMA2_CH0_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH1_HANDLER)
+#error "STM32_DMA2_CH1_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH2_HANDLER)
+#error "STM32_DMA2_CH2_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH3_HANDLER)
+#error "STM32_DMA2_CH3_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH4_HANDLER)
+#error "STM32_DMA2_CH4_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH5_HANDLER)
+#error "STM32_DMA2_CH5_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH6_HANDLER)
+#error "STM32_DMA2_CH6_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH7_HANDLER)
+#error "STM32_DMA2_CH7_HANDLER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH0_NUMBER)
+#error "STM32_DMA1_CH0_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH1_NUMBER)
+#error "STM32_DMA1_CH1_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH2_NUMBER)
+#error "STM32_DMA1_CH2_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH3_NUMBER)
+#error "STM32_DMA1_CH3_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH4_NUMBER)
+#error "STM32_DMA1_CH4_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH5_NUMBER)
+#error "STM32_DMA1_CH5_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH6_NUMBER)
+#error "STM32_DMA1_CH6_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA1_CH7_NUMBER)
+#error "STM32_DMA1_CH7_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH0_NUMBER)
+#error "STM32_DMA2_CH0_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH1_NUMBER)
+#error "STM32_DMA2_CH1_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH2_NUMBER)
+#error "STM32_DMA2_CH2_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH3_NUMBER)
+#error "STM32_DMA2_CH3_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH4_NUMBER)
+#error "STM32_DMA2_CH4_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH5_NUMBER)
+#error "STM32_DMA2_CH5_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH6_NUMBER)
+#error "STM32_DMA2_CH6_NUMBER missing in registry"
+#endif
+
+#if !defined(STM32_DMA2_CH7_NUMBER)
+#error "STM32_DMA2_CH7_NUMBER missing in registry"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -237,6 +384,71 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/* Driver macros. */
/*===========================================================================*/
+#if STM32_DMA_CACHE_HANDLING || defined(__DOXYGEN__)
+/**
+ * @brief Invalidates the data cache lines overlapping a DMA buffer.
+ * @details This function is meant to make sure that data written in
+ * data cache is invalidated. It is used for DMA buffers that
+ * must have been written by a DMA stream.
+ * @note On devices without data cache this function does nothing.
+ * @note The function does not consider the lower 5 bits of addresses,
+ * the buffers are meant to be aligned to a 32 bytes boundary or
+ * adjacent data can be invalidated as side effect.
+ *
+ * @param[in] saddr start address of the DMA buffer
+ * @param[in] n size of the DMA buffer in bytes
+ *
+ * @api
+ */
+#define dmaBufferInvalidate(saddr, n) { \
+ uint8_t *start = (uint8_t *)(saddr); \
+ uint8_t *end = start + (size_t)(n); \
+ __DSB(); \
+ while (start < end) { \
+ SCB->DCIMVAC = (uint32_t)start; \
+ start += 32U; \
+ } \
+ __DSB(); \
+ __ISB(); \
+}
+
+/**
+ * @brief Flushes the data cache lines overlapping a DMA buffer.
+ * @details This function is meant to make sure that data written in
+ * data cache is flushed to RAM. It is used for DMA buffers that
+ * must be read by a DMA stream.
+ * @note On devices without data cache this function does nothing.
+ * @note The function does not consider the lower 5 bits of addresses,
+ * the buffers are meant to be aligned to a 32 bytes boundary or
+ * adjacent data can be flushed as side effect.
+ *
+ * @param[in] saddr start address of the DMA buffer
+ * @param[in] n size of the DMA buffer in bytes
+ *
+ * @api
+ */
+#define dmaBufferFlush(saddr, n) { \
+ uint8_t *start = (uint8_t *)(saddr); \
+ uint8_t *end = start + (size_t)(n); \
+ __DSB(); \
+ while (start < end) { \
+ SCB->DCCIMVAC = (uint32_t)start; \
+ start += 32U; \
+ } \
+ __DSB(); \
+ __ISB(); \
+}
+#else
+#define dmaBufferInvalidate(addr, size) { \
+ (void)(addr); \
+ (void)(size); \
+}
+#define dmaBufferFlush(addr, size) { \
+ (void)(addr); \
+ (void)(size); \
+}
+#endif
+
/**
* @name Macro Functions
* @{
@@ -418,7 +630,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
dmaStreamSetTransactionSize(dmastp, n); \
dmaStreamSetMode(dmastp, (mode) | \
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
- STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
+ STM32_DMA_CR_DIR_M2M); \
+ dmaStreamEnable(dmastp); \
}
/**
@@ -429,9 +642,11 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*/
#define dmaWaitCompletion(dmastp) { \
- while ((dmastp)->stream->NDTR > 0) \
+ (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE); \
+ while ((dmastp)->stream->CR & STM32_DMA_CR_EN) \
; \
- dmaStreamDisable(dmastp); \
+ dmaStreamClearInterrupt(dmastp); \
}
/** @} */
@@ -447,15 +662,15 @@ extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
extern "C" {
#endif
void dmaInit(void);
- bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param);
+ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+ uint32_t priority,
+ stm32_dmaisr_t func,
+ void *param);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
#ifdef __cplusplus
}
#endif
-#endif /* _STM32_DMA_H_ */
+#endif /* STM32_DMA_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
new file mode 100644
index 0000000000..b81c090348
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/ext_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c
similarity index 71%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/ext_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c
index 6dee976196..000db13e02 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/ext_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,24 +15,30 @@
*/
/**
- * @file STM32/ext_lld.c
+ * @file EXTIv1/hal_ext_lld.c
* @brief STM32 EXT subsystem low level driver source.
*
* @addtogroup EXT
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
-#include "ext_lld_isr.h"
-
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
+/* Handling a difference in ST headers.*/
+#if defined(STM32L4XX)
+#define EMR EMR1
+#define IMR IMR1
+#define PR PR1
+#define RTSR RTSR1
+#define FTSR FTSR1
+#endif
+
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -77,17 +83,17 @@ void ext_lld_init(void) {
* @notapi
*/
void ext_lld_start(EXTDriver *extp) {
- unsigned i;
+ expchannel_t line;
if (extp->state == EXT_STOP)
ext_lld_exti_irq_enable();
/* Configuration of automatic channels.*/
- for (i = 0; i < EXT_MAX_CHANNELS; i++)
- if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
- ext_lld_channel_enable(extp, i);
+ for (line = 0; line < EXT_MAX_CHANNELS; line++)
+ if (extp->config->channels[line].mode & EXT_CH_MODE_AUTOSTART)
+ ext_lld_channel_enable(extp, line);
else
- ext_lld_channel_disable(extp, i);
+ ext_lld_channel_disable(extp, line);
}
/**
@@ -103,10 +109,11 @@ void ext_lld_stop(EXTDriver *extp) {
ext_lld_exti_irq_disable();
EXTI->EMR = 0;
- EXTI->IMR = 0;
- EXTI->PR = 0xFFFFFFFF;
-#if STM32_EXTI_NUM_CHANNELS > 32
- EXTI->PR2 = 0xFFFFFFFF;
+ EXTI->IMR = STM32_EXTI_IMR_MASK;
+ EXTI->PR = ~STM32_EXTI_IMR_MASK;
+#if STM32_EXTI_NUM_LINES > 32
+ EXTI->IMR2 = STM32_EXTI_IMR2_MASK;
+ EXTI->PR2 = ~STM32_EXTI_IMR2_MASK;
#endif
}
@@ -119,6 +126,7 @@ void ext_lld_stop(EXTDriver *extp) {
* @notapi
*/
void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
+ uint32_t cmask = (1 << (channel & 0x1F));
/* Setting the associated GPIO for external channels.*/
if (channel < 16) {
@@ -128,59 +136,66 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
EXT_MODE_GPIO_MASK) >>
EXT_MODE_GPIO_OFF) << ((channel & 3) * 4);
-#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \
- defined(STM32F10X_MD) || defined(STM32F10X_HD) || \
- defined(STM32F10X_XL) || defined(STM32F10X_CL)
+#if defined(STM32F1XX)
AFIO->EXTICR[n] = (AFIO->EXTICR[n] & mask) | port;
#else /* !defined(STM32F1XX) */
SYSCFG->EXTICR[n] = (SYSCFG->EXTICR[n] & mask) | port;
#endif /* !defined(STM32F1XX) */
}
-#if STM32_EXTI_NUM_CHANNELS > 32
+#if STM32_EXTI_NUM_LINES > 32
if (channel < 32) {
#endif
+ /* Masked out lines must not be touched by this driver.*/
+ if ((cmask & STM32_EXTI_IMR_MASK) != 0U) {
+ return;
+ }
+
/* Programming edge registers.*/
if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
- EXTI->RTSR |= (1 << channel);
+ EXTI->RTSR |= cmask;
else
- EXTI->RTSR &= ~(1 << channel);
+ EXTI->RTSR &= ~cmask;
if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
- EXTI->FTSR |= (1 << channel);
+ EXTI->FTSR |= cmask;
else
- EXTI->FTSR &= ~(1 << channel);
+ EXTI->FTSR &= ~cmask;
/* Programming interrupt and event registers.*/
if (extp->config->channels[channel].cb != NULL) {
- EXTI->IMR |= (1 << channel);
- EXTI->EMR &= ~(1 << channel);
+ EXTI->IMR |= cmask;
+ EXTI->EMR &= ~cmask;
}
else {
- EXTI->EMR |= (1 << channel);
- EXTI->IMR &= ~(1 << channel);
+ EXTI->EMR |= cmask;
+ EXTI->IMR &= ~cmask;
}
-#if STM32_EXTI_NUM_CHANNELS > 32
+#if STM32_EXTI_NUM_LINES > 32
}
else {
+ /* Masked out lines must not be touched by this driver.*/
+ if ((cmask & STM32_EXTI_IMR2_MASK) != 0U) {
+ return;
+ }
+
/* Programming edge registers.*/
if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
- EXTI->RTSR2 |= (1 << (32 - channel));
+ EXTI->RTSR2 |= cmask;
else
- EXTI->RTSR2 &= ~(1 << (32 - channel));
+ EXTI->RTSR2 &= ~cmask;
if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
- EXTI->FTSR2 |= (1 << (32 - channel));
+ EXTI->FTSR2 |= cmask;
else
- EXTI->FTSR2 &= ~(1 << (32 - channel));
+ EXTI->FTSR2 &= ~cmask;
/* Programming interrupt and event registers.*/
if (extp->config->channels[channel].cb != NULL) {
- EXTI->IMR2 |= (1 << (32 - channel));
- EXTI->EMR2 &= ~(1 << (32 - channel));
+ EXTI->IMR2 |= cmask;
+ EXTI->EMR2 &= ~cmask;
}
else {
- EXTI->EMR2 |= (1 << (32 - channel));
- EXTI->IMR2 &= ~(1 << (32 - channel));
+ EXTI->EMR2 |= cmask;
+ EXTI->IMR2 &= ~cmask;
}
}
#endif
@@ -195,25 +210,26 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
* @notapi
*/
void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
+ uint32_t cmask = (1 << (channel & 0x1F));
(void)extp;
-#if STM32_EXTI_NUM_CHANNELS > 32
+#if STM32_EXTI_NUM_LINES > 32
if (channel < 32) {
#endif
- EXTI->IMR &= ~(1 << channel);
- EXTI->EMR &= ~(1 << channel);
- EXTI->RTSR &= ~(1 << channel);
- EXTI->FTSR &= ~(1 << channel);
- EXTI->PR = (1 << channel);
-#if STM32_EXTI_NUM_CHANNELS > 32
+ EXTI->IMR &= ~cmask;
+ EXTI->EMR &= ~cmask;
+ EXTI->RTSR &= ~cmask;
+ EXTI->FTSR &= ~cmask;
+ EXTI->PR = cmask;
+#if STM32_EXTI_NUM_LINES > 32
}
else {
- EXTI->IMR2 &= ~(1 << (32 - channel));
- EXTI->EMR2 &= ~(1 << (32 - channel));
- EXTI->RTSR2 &= ~(1 << (32 - channel));
- EXTI->FTSR2 &= ~(1 << (32 - channel));
- EXTI->PR2 = (1 << (32 - channel));
+ EXTI->IMR2 &= ~cmask;
+ EXTI->EMR2 &= ~cmask;
+ EXTI->RTSR2 &= ~cmask;
+ EXTI->FTSR2 &= ~cmask;
+ EXTI->PR2 = cmask;
}
#endif
}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/ext_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.h
similarity index 95%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/ext_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.h
index 9736b9796c..ea1b3a98a5 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/ext_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,18 +15,20 @@
*/
/**
- * @file STM32/ext_lld.h
+ * @file EXTIv1/hal_ext_lld.h
* @brief STM32 EXT subsystem low level driver header.
*
* @addtogroup EXT
* @{
*/
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
+#ifndef HAL_EXT_LLD_H
+#define HAL_EXT_LLD_H
#if HAL_USE_EXT || defined(__DOXYGEN__)
+#include "hal_ext_lld_isr.h"
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@@ -34,7 +36,7 @@
/**
* @brief Available number of EXT channels.
*/
-#define EXT_MAX_CHANNELS STM32_EXTI_NUM_CHANNELS
+#define EXT_MAX_CHANNELS STM32_EXTI_NUM_LINES
/**
* @name STM32-specific EXT channel modes
@@ -148,6 +150,6 @@ extern "C" {
#endif /* HAL_USE_EXT */
-#endif /* _EXT_LLD_H_ */
+#endif /* HAL_EXT_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/notes.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/notes.txt
new file mode 100644
index 0000000000..138f97e043
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/EXTIv1/notes.txt
@@ -0,0 +1,23 @@
+STM32 EXT driver implementation through EXTI unit.
+
+There are several kind of EXTI lines:
+
+1) GPIO lines. Always in range 0..15, always handled by the EXT driver.
+2) Configurable peripheral events not shared, always handled by the EXT driver.
+3) Configurable peripheral events shared with other, non EXTI, interrupts.
+ The EXTI driver declares the ISR and has to call the IRQ handler of the
+ other driver.
+4) Direct lines (1 in IMR register after reset). The EXTI driver never touches
+ the default configuration for direct lines and does not declare ISRs.
+5) Unused lines. The EXTI driver does not declare ISRs.
+
+The file registry must export:
+STM32_EXTI_NUM_LINES - Range of configurable lines, it can have holes of
+ unused or direct lines. Configurable line numbers go
+ from 0 to STM32_EXTI_NUM_LINES-1.
+STM32_EXTI_IMR_MASK - Direct lines and unused lines marked as 1 in this
+ mask, configurable lines marked as 0.
+STM32_EXTI_IMR2_MASK - Optional, for lines 32...63.
+
+ISRs are not declared inside the driver, each sub-family must have its own
+ext_lld_isr.h and ext_lld_isr.c files.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/driver.mk
new file mode 100644
index 0000000000..3a9768ee69
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv1/pal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
similarity index 97%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv1/pal_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
index f442dee7f7..2a0684a0c5 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv1/pal_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/GPIOv1/pal_lld.c
- * @brief STM32F1xx GPIO low level driver code.
+ * @file GPIOv1/hal_pal_lld.c
+ * @brief STM32 PAL low level driver code.
*
* @addtogroup PAL
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv1/pal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.h
similarity index 88%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv1/pal_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.h
index 3beae53499..15165fc76b 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv1/pal_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/GPIOv1/pal_lld.h
- * @brief STM32F1xx GPIO low level driver header.
+ * @file GPIOv1/hal_pal_lld.h
+ * @brief STM32 PAL low level driver header.
*
* @addtogroup PAL
* @{
*/
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
+#ifndef HAL_PAL_LLD_H
+#define HAL_PAL_LLD_H
#if HAL_USE_PAL || defined(__DOXYGEN__)
@@ -50,6 +50,54 @@
/* I/O Ports Types and constants. */
/*===========================================================================*/
+/**
+ * @name Port related definitions
+ * @{
+ */
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 16
+
+/**
+ * @brief Whole port mask.
+ * @details This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
+/** @} */
+
+/**
+ * @name Line handling macros
+ * @{
+ */
+/**
+ * @brief Forms a line identifier.
+ * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
+ * of this type is platform-dependent.
+ * @note In this driver the pad number is encoded in the lower 4 bits of
+ * the GPIO address which are guaranteed to be zero.
+ */
+#define PAL_LINE(port, pad) \
+ ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
+
+/**
+ * @brief Decodes a port identifier from a line identifier.
+ */
+#define PAL_PORT(line) \
+ ((GPIO_TypeDef *)(((uint32_t)(line)) & 0xFFFFFFF0U))
+
+/**
+ * @brief Decodes a pad identifier from a line identifier.
+ */
+#define PAL_PAD(line) \
+ ((uint32_t)((uint32_t)(line) & 0x0000000FU))
+
+/**
+ * @brief Value identifying an invalid line.
+ */
+#define PAL_NOLINE 0U
+/** @} */
+
/**
* @brief GPIO port setup info.
*/
@@ -92,17 +140,6 @@ typedef struct {
#endif
} PALConfig;
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 16
-
-/**
- * @brief Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
-
/**
* @brief Digital I/O port sized unsigned type.
*/
@@ -113,6 +150,11 @@ typedef uint32_t ioportmask_t;
*/
typedef uint32_t iomode_t;
+/**
+ * @brief Type of an I/O line.
+ */
+typedef uint32_t ioline_t;
+
/**
* @brief Port Identifier.
* @details This type can be a scalar or some kind of pointer, do not make
@@ -329,6 +371,6 @@ extern "C" {
#endif /* HAL_USE_PAL */
-#endif /* _PAL_LLD_H_ */
+#endif /* HAL_PAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
new file mode 100644
index 0000000000..304546bba6
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
similarity index 58%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv2/pal_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
index 2600f1f3e1..76d0bebee7 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv2/pal_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/GPIOv2/pal_lld.c
- * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code.
+ * @file GPIOv2/hal_pal_lld.c
+ * @brief STM32 PAL low level driver code.
*
* @addtogroup PAL
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
@@ -31,40 +30,16 @@
/* Driver local definitions. */
/*===========================================================================*/
-#if defined(STM32L1XX)
-#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
- RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
- RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
+#if defined(STM32L0XX) || defined(STM32L1XX)
+#define AHB_EN_MASK STM32_GPIO_EN_MASK
#define AHB_LPEN_MASK AHB_EN_MASK
-#elif defined(STM32F030) || defined(STM32F0XX_MD)
-#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
- RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
- RCC_AHBENR_GPIOFEN)
-
-#elif defined(STM32F0XX_LD)
-#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
- RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN)
-
-#elif defined(STM32F2XX)
-#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
- RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
- RCC_AHB1ENR_GPIOIEN)
-#define AHB1_LPEN_MASK AHB1_EN_MASK
+#elif defined(STM32F0XX) || defined(STM32F3XX) || defined(STM32F37X)
+#define AHB_EN_MASK STM32_GPIO_EN_MASK
+#define AHB_LPEN_MASK 0
-#elif defined(STM32F30X) || defined(STM32F37X)
-#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
- RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
- RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
-
-#elif defined(STM32F4XX)
-#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
- RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
- RCC_AHB1ENR_GPIOIEN)
+#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)
+#define AHB1_EN_MASK STM32_GPIO_EN_MASK
#define AHB1_LPEN_MASK AHB1_EN_MASK
#else
@@ -83,7 +58,7 @@
/* Driver local functions. */
/*===========================================================================*/
-static void initgpio(GPIO_TypeDef *gpiop, const stm32_gpio_setup_t *config) {
+static void initgpio(stm32_gpio_t *gpiop, const stm32_gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
@@ -115,14 +90,17 @@ void _pal_lld_init(const PALConfig *config) {
/*
* Enables the GPIO related clocks.
*/
-#if defined(STM32L1XX)
+#if defined(STM32L0XX)
+ RCC->IOPENR |= AHB_EN_MASK;
+ RCC->IOPSMENR |= AHB_LPEN_MASK;
+#elif defined(STM32L1XX)
rccEnableAHB(AHB_EN_MASK, TRUE);
RCC->AHBLPENR |= AHB_LPEN_MASK;
#elif defined(STM32F0XX)
rccEnableAHB(AHB_EN_MASK, TRUE);
-#elif defined(STM32F30X) || defined(STM32F37X)
+#elif defined(STM32F3XX) || defined(STM32F37X)
rccEnableAHB(AHB_EN_MASK, TRUE);
-#elif defined(STM32F2XX) || defined(STM32F4XX)
+#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)
RCC->AHB1ENR |= AHB1_EN_MASK;
RCC->AHB1LPENR |= AHB1_LPEN_MASK;
#endif
@@ -157,6 +135,12 @@ void _pal_lld_init(const PALConfig *config) {
#if STM32_HAS_GPIOI
initgpio(GPIOI, &config->PIData);
#endif
+#if STM32_HAS_GPIOJ
+ initgpio(GPIOJ, &config->PJData);
+#endif
+#if STM32_HAS_GPIOK
+ initgpio(GPIOK, &config->PKData);
+#endif
}
/**
@@ -172,7 +156,6 @@ void _pal_lld_init(const PALConfig *config) {
*
* @notapi
*/
-#if 1
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode) {
@@ -180,25 +163,38 @@ void _pal_lld_setgroupmode(ioportid_t port,
uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0;
uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2;
uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3;
- uint32_t pupdr = (mode & PAL_STM32_PUDR_MASK) >> 5;
+ uint32_t pupdr = (mode & PAL_STM32_PUPDR_MASK) >> 5;
uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
uint32_t bit = 0;
- while (TRUE) {
+ while (true) {
if ((mask & 1) != 0) {
uint32_t altrmask, m1, m2, m4;
altrmask = altr << ((bit & 7) * 4);
- m4 = 15 << ((bit & 7) * 4);
- if (bit < 8)
- port->AFRL = (port->AFRL & ~m4) | altrmask;
- else
- port->AFRH = (port->AFRH & ~m4) | altrmask;
m1 = 1 << bit;
- port->OTYPER = (port->OTYPER & ~m1) | otyper;
m2 = 3 << (bit * 2);
+ m4 = 15 << ((bit & 7) * 4);
+ port->OTYPER = (port->OTYPER & ~m1) | otyper;
port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
port->PUPDR = (port->PUPDR & ~m2) | pupdr;
- port->MODER = (port->MODER & ~m2) | moder;
+ if ((mode & PAL_STM32_MODE_MASK) == PAL_STM32_MODE_ALTERNATE) {
+ /* If going in alternate mode then the alternate number is set
+ before switching mode in order to avoid glitches.*/
+ if (bit < 8)
+ port->AFRL = (port->AFRL & ~m4) | altrmask;
+ else
+ port->AFRH = (port->AFRH & ~m4) | altrmask;
+ port->MODER = (port->MODER & ~m2) | moder;
+ }
+ else {
+ /* If going into a non-alternate mode then the mode is switched
+ before setting the alternate mode in order to avoid glitches.*/
+ port->MODER = (port->MODER & ~m2) | moder;
+ if (bit < 8)
+ port->AFRL = (port->AFRL & ~m4) | altrmask;
+ else
+ port->AFRH = (port->AFRH & ~m4) | altrmask;
+ }
}
mask >>= 1;
if (!mask)
@@ -210,45 +206,6 @@ void _pal_lld_setgroupmode(ioportid_t port,
bit++;
}
}
-#else
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode) {
- uint32_t afrm, moderm, pupdrm, otyperm, ospeedrm;
- uint32_t m1 = (uint32_t)mask;
- uint32_t m2 = 0;
- uint32_t m4l = 0;
- uint32_t m4h = 0;
- uint32_t bit = 0;
- do {
- if ((mask & 1) != 0) {
- m2 |= 3 << bit;
- if (bit < 16)
- m4l |= 15 << ((bit & 14) * 2);
- else
- m4h |= 15 << ((bit & 14) * 2);
- }
- bit += 2;
- mask >>= 1;
- } while (mask);
-
- afrm = ((mode & PAL_STM32_ALTERNATE_MASK) >> 7) * 0x1111;
- port->AFRL = (port->AFRL & ~m4l) | (afrm & m4l);
- port->AFRH = (port->AFRH & ~m4h) | (afrm & m4h);
-
- ospeedrm = ((mode & PAL_STM32_OSPEED_MASK) >> 3) * 0x5555;
- port->OSPEEDR = (port->OSPEEDR & ~m2) | (ospeedrm & m2);
-
- otyperm = ((mode & PAL_STM32_OTYPE_MASK) >> 2) * 0xffff;
- port->OTYPER = (port->OTYPER & ~m1) | (otyperm & m1);
-
- pupdrm = ((mode & PAL_STM32_PUDR_MASK) >> 5) * 0x5555;
- port->PUPDR = (port->PUPDR & ~m2) | (pupdrm & m2);
-
- moderm = ((mode & PAL_STM32_MODE_MASK) >> 0) * 0x5555;
- port->MODER = (port->MODER & ~m2) | (moderm & m2);
-}
-#endif
#endif /* HAL_USE_PAL */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.h
similarity index 70%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv2/pal_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.h
index 3c74c5ff61..de1d96338a 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/GPIOv2/pal_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/GPIOv2/pal_lld.h
- * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header.
+ * @file GPIOv2/hal_pal_lld.h
+ * @brief STM32 PAL low level driver header.
*
* @addtogroup PAL
* @{
*/
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
+#ifndef HAL_PAL_LLD_H
+#define HAL_PAL_LLD_H
#if HAL_USE_PAL || defined(__DOXYGEN__)
@@ -44,33 +44,33 @@
* @name STM32-specific I/O mode flags
* @{
*/
-#define PAL_STM32_MODE_MASK (3 << 0)
-#define PAL_STM32_MODE_INPUT (0 << 0)
-#define PAL_STM32_MODE_OUTPUT (1 << 0)
-#define PAL_STM32_MODE_ALTERNATE (2 << 0)
-#define PAL_STM32_MODE_ANALOG (3 << 0)
+#define PAL_STM32_MODE_MASK (3U << 0U)
+#define PAL_STM32_MODE_INPUT (0U << 0U)
+#define PAL_STM32_MODE_OUTPUT (1U << 0U)
+#define PAL_STM32_MODE_ALTERNATE (2U << 0U)
+#define PAL_STM32_MODE_ANALOG (3U << 0U)
-#define PAL_STM32_OTYPE_MASK (1 << 2)
-#define PAL_STM32_OTYPE_PUSHPULL (0 << 2)
-#define PAL_STM32_OTYPE_OPENDRAIN (1 << 2)
+#define PAL_STM32_OTYPE_MASK (1U << 2U)
+#define PAL_STM32_OTYPE_PUSHPULL (0U << 2U)
+#define PAL_STM32_OTYPE_OPENDRAIN (1U << 2U)
-#define PAL_STM32_OSPEED_MASK (3 << 3)
-#define PAL_STM32_OSPEED_LOWEST (0 << 3)
+#define PAL_STM32_OSPEED_MASK (3U << 3U)
+#define PAL_STM32_OSPEED_LOWEST (0U << 3U)
#if defined(STM32F0XX) || defined(STM32F30X) || defined(STM32F37X)
-#define PAL_STM32_OSPEED_MID (1 << 3)
+#define PAL_STM32_OSPEED_MID (1U << 3U)
#else
-#define PAL_STM32_OSPEED_MID1 (1 << 3)
-#define PAL_STM32_OSPEED_MID2 (2 << 3)
+#define PAL_STM32_OSPEED_MID1 (1U << 3U)
+#define PAL_STM32_OSPEED_MID2 (2U << 3U)
#endif
-#define PAL_STM32_OSPEED_HIGHEST (3 << 3)
+#define PAL_STM32_OSPEED_HIGHEST (3U << 3U)
-#define PAL_STM32_PUDR_MASK (3 << 5)
-#define PAL_STM32_PUDR_FLOATING (0 << 5)
-#define PAL_STM32_PUDR_PULLUP (1 << 5)
-#define PAL_STM32_PUDR_PULLDOWN (2 << 5)
+#define PAL_STM32_PUPDR_MASK (3U << 5U)
+#define PAL_STM32_PUPDR_FLOATING (0U << 5U)
+#define PAL_STM32_PUPDR_PULLUP (1U << 5U)
+#define PAL_STM32_PUPDR_PULLDOWN (2U << 5U)
-#define PAL_STM32_ALTERNATE_MASK (15 << 7)
-#define PAL_STM32_ALTERNATE(n) ((n) << 7)
+#define PAL_STM32_ALTERNATE_MASK (15U << 7U)
+#define PAL_STM32_ALTERNATE(n) ((n) << 7U)
/**
* @brief Alternate function.
@@ -104,13 +104,13 @@
* @brief Input pad with weak pull up resistor.
*/
#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \
- PAL_STM32_PUDR_PULLUP)
+ PAL_STM32_PUPDR_PULLUP)
/**
* @brief Input pad with weak pull down resistor.
*/
#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \
- PAL_STM32_PUDR_PULLDOWN)
+ PAL_STM32_PUPDR_PULLDOWN)
/**
* @brief Analog input mode.
@@ -130,10 +130,91 @@
PAL_STM32_OTYPE_OPENDRAIN)
/** @} */
+/* Discarded definitions from the ST headers, the PAL driver uses its own
+ definitions in order to have an unified handling for all devices.
+ Unfortunately the ST headers have no uniform definitions for the same
+ objects across the various sub-families.*/
+#undef GPIOA
+#undef GPIOB
+#undef GPIOC
+#undef GPIOD
+#undef GPIOE
+#undef GPIOF
+#undef GPIOG
+#undef GPIOH
+#undef GPIOI
+#undef GPIOJ
+#undef GPIOK
+
+/**
+ * @name GPIO ports definitions
+ * @{
+ */
+#define GPIOA ((stm32_gpio_t *)GPIOA_BASE)
+#define GPIOB ((stm32_gpio_t *)GPIOB_BASE)
+#define GPIOC ((stm32_gpio_t *)GPIOC_BASE)
+#define GPIOD ((stm32_gpio_t *)GPIOD_BASE)
+#define GPIOE ((stm32_gpio_t *)GPIOE_BASE)
+#define GPIOF ((stm32_gpio_t *)GPIOF_BASE)
+#define GPIOG ((stm32_gpio_t *)GPIOG_BASE)
+#define GPIOH ((stm32_gpio_t *)GPIOH_BASE)
+#define GPIOI ((stm32_gpio_t *)GPIOI_BASE)
+#define GPIOJ ((stm32_gpio_t *)GPIOJ_BASE)
+#define GPIOK ((stm32_gpio_t *)GPIOK_BASE)
+/** @} */
+
/*===========================================================================*/
/* I/O Ports Types and constants. */
/*===========================================================================*/
+/**
+ * @name Port related definitions
+ * @{
+ */
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 16
+
+/**
+ * @brief Whole port mask.
+ * @details This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
+/** @} */
+
+/**
+ * @name Line handling macros
+ * @{
+ */
+/**
+ * @brief Forms a line identifier.
+ * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
+ * of this type is platform-dependent.
+ * @note In this driver the pad number is encoded in the lower 4 bits of
+ * the GPIO address which are guaranteed to be zero.
+ */
+#define PAL_LINE(port, pad) \
+ ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
+
+/**
+ * @brief Decodes a port identifier from a line identifier.
+ */
+#define PAL_PORT(line) \
+ ((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U))
+
+/**
+ * @brief Decodes a pad identifier from a line identifier.
+ */
+#define PAL_PAD(line) \
+ ((uint32_t)((uint32_t)(line) & 0x0000000FU))
+
+/**
+ * @brief Value identifying an invalid line.
+ */
+#define PAL_NOLINE 0U
+/** @} */
+
/**
* @brief STM32 GPIO registers block.
*/
@@ -155,7 +236,8 @@ typedef struct {
volatile uint32_t LCKR;
volatile uint32_t AFRL;
volatile uint32_t AFRH;
-} CH_GPIO_TypeDef;
+ volatile uint32_t BRR;
+} stm32_gpio_t;
/**
* @brief GPIO port setup info.
@@ -221,28 +303,30 @@ typedef struct {
/** @brief Port I setup data.*/
stm32_gpio_setup_t PIData;
#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ /** @brief Port I setup data.*/
+ stm32_gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ /** @brief Port I setup data.*/
+ stm32_gpio_setup_t PKData;
+#endif
} PALConfig;
/**
- * @brief Width, in bits, of an I/O port.
+ * @brief Type of digital I/O port sized unsigned integer.
*/
-#define PAL_IOPORTS_WIDTH 16
-
-/**
- * @brief Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
+typedef uint32_t ioportmask_t;
/**
- * @brief Digital I/O port sized unsigned type.
+ * @brief Type of digital I/O modes.
*/
-typedef uint32_t ioportmask_t;
+typedef uint32_t iomode_t;
/**
- * @brief Digital I/O modes.
+ * @brief Type of an I/O line.
*/
-typedef uint32_t iomode_t;
+typedef uint32_t ioline_t;
/**
* @brief Port Identifier.
@@ -250,7 +334,7 @@ typedef uint32_t iomode_t;
* any assumption about it, use the provided macros when populating
* variables of this type.
*/
-typedef CH_GPIO_TypeDef * ioportid_t;
+typedef stm32_gpio_t * ioportid_t;
/*===========================================================================*/
/* I/O Ports Identifiers. */
@@ -321,6 +405,20 @@ typedef CH_GPIO_TypeDef * ioportid_t;
#define IOPORT9 GPIOI
#endif
+/**
+ * @brief GPIO port J identifier.
+ */
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+#define IOPORT10 GPIOJ
+#endif
+
+/**
+ * @brief GPIO port K identifier.
+ */
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+#define IOPORT11 GPIOK
+#endif
+
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */
@@ -345,7 +443,7 @@ typedef CH_GPIO_TypeDef * ioportid_t;
*
* @notapi
*/
-#define pal_lld_readport(port) (((ioportid_t)(port))->IDR)
+#define pal_lld_readport(port) ((port)->IDR)
/**
* @brief Reads the output latch.
@@ -359,7 +457,7 @@ typedef CH_GPIO_TypeDef * ioportid_t;
*
* @notapi
*/
-#define pal_lld_readlatch(port) (((ioportid_t)(port))->ODR)
+#define pal_lld_readlatch(port) ((port)->ODR)
/**
* @brief Writes on a I/O port.
@@ -371,7 +469,7 @@ typedef CH_GPIO_TypeDef * ioportid_t;
*
* @notapi
*/
-#define pal_lld_writeport(port, bits) (((ioportid_t)(port))->ODR = (bits))
+#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
/**
* @brief Sets a bits mask on a I/O port.
@@ -383,7 +481,7 @@ typedef CH_GPIO_TypeDef * ioportid_t;
*
* @notapi
*/
-#define pal_lld_setport(port, bits) (((ioportid_t)(port))->BSRR.H.set = (uint16_t)(bits))
+#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits))
/**
* @brief Clears a bits mask on a I/O port.
@@ -395,7 +493,7 @@ typedef CH_GPIO_TypeDef * ioportid_t;
*
* @notapi
*/
-#define pal_lld_clearport(port, bits) (((ioportid_t)(port))->BSRR.H.clear = (uint16_t)(bits))
+#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits))
/**
* @brief Writes a group of bits.
@@ -411,7 +509,7 @@ typedef CH_GPIO_TypeDef * ioportid_t;
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) \
- (((ioportid_t)(port))->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | \
+ ((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \
(((bits) & (mask)) << (offset)))
/**
@@ -456,6 +554,6 @@ extern "C" {
#endif /* HAL_USE_PAL */
-#endif /* _PAL_LLD_H_ */
+#endif /* HAL_PAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
new file mode 100644
index 0000000000..39e4d7bb75
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
new file mode 100644
index 0000000000..bfcf1c9b79
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
@@ -0,0 +1,199 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file GPIOv3/hal_pal_lld.c
+ * @brief STM32 PAL low level driver code.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if defined(STM32L4XX)
+#define AHB2_EN_MASK STM32_GPIO_EN_MASK
+#define AHB2_LPEN_MASK 0
+
+#else
+#error "missing or unsupported platform for GPIOv3 PAL driver"
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void initgpio(stm32_gpio_t *gpiop, const stm32_gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->ASCR = config->ascr;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+ gpiop->LOCKR = config->lockr;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief STM32 I/O ports configuration.
+ * @details Ports A-D(E, F, G, H) clocks enabled.
+ *
+ * @param[in] config the STM32 ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+
+ /*
+ * Enables the GPIO related clocks.
+ */
+#if defined(STM32L4XX)
+ RCC->AHB2ENR |= AHB2_EN_MASK;
+#endif
+
+ /*
+ * Initial GPIO setup.
+ */
+#if STM32_HAS_GPIOA
+ initgpio(GPIOA, &config->PAData);
+#endif
+#if STM32_HAS_GPIOB
+ initgpio(GPIOB, &config->PBData);
+#endif
+#if STM32_HAS_GPIOC
+ initgpio(GPIOC, &config->PCData);
+#endif
+#if STM32_HAS_GPIOD
+ initgpio(GPIOD, &config->PDData);
+#endif
+#if STM32_HAS_GPIOE
+ initgpio(GPIOE, &config->PEData);
+#endif
+#if STM32_HAS_GPIOF
+ initgpio(GPIOF, &config->PFData);
+#endif
+#if STM32_HAS_GPIOG
+ initgpio(GPIOG, &config->PGData);
+#endif
+#if STM32_HAS_GPIOH
+ initgpio(GPIOH, &config->PHData);
+#endif
+#if STM32_HAS_GPIOI
+ initgpio(GPIOI, &config->PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ initgpio(GPIOJ, &config->PJData);
+#endif
+#if STM32_HAS_GPIOK
+ initgpio(GPIOK, &config->PKData);
+#endif
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
+ * speed.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode) {
+
+ uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0;
+ uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2;
+ uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3;
+ uint32_t pupdr = (mode & PAL_STM32_PUPDR_MASK) >> 5;
+ uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
+ uint32_t ascr = (mode & PAL_STM32_ASCR_MASK) >> 11;
+ uint32_t lockr = (mode & PAL_STM32_LOCKR_MASK) >> 12;
+ uint32_t bit = 0;
+ while (true) {
+ if ((mask & 1) != 0) {
+ uint32_t altrmask, m1, m2, m4;
+
+ altrmask = altr << ((bit & 7) * 4);
+ m1 = 1 << bit;
+ m2 = 3 << (bit * 2);
+ m4 = 15 << ((bit & 7) * 4);
+ port->OTYPER = (port->OTYPER & ~m1) | otyper;
+ port->ASCR = (port->ASCR & ~m1) | ascr;
+ port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
+ port->PUPDR = (port->PUPDR & ~m2) | pupdr;
+ if ((mode & PAL_STM32_MODE_MASK) == PAL_STM32_MODE_ALTERNATE) {
+ /* If going in alternate mode then the alternate number is set
+ before switching mode in order to avoid glitches.*/
+ if (bit < 8)
+ port->AFRL = (port->AFRL & ~m4) | altrmask;
+ else
+ port->AFRH = (port->AFRH & ~m4) | altrmask;
+ port->MODER = (port->MODER & ~m2) | moder;
+ }
+ else {
+ /* If going into a non-alternate mode then the mode is switched
+ before setting the alternate mode in order to avoid glitches.*/
+ port->MODER = (port->MODER & ~m2) | moder;
+ if (bit < 8)
+ port->AFRL = (port->AFRL & ~m4) | altrmask;
+ else
+ port->AFRH = (port->AFRH & ~m4) | altrmask;
+ }
+ port->LOCKR = (port->LOCKR & ~m1) | lockr;
+ }
+ mask >>= 1;
+ if (!mask)
+ return;
+ otyper <<= 1;
+ ospeedr <<= 2;
+ pupdr <<= 2;
+ moder <<= 2;
+ bit++;
+ }
+}
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.h
new file mode 100644
index 0000000000..93f188e4df
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.h
@@ -0,0 +1,571 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file GPIOv3/hal_pal_lld.h
+ * @brief STM32 PAL low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef HAL_PAL_LLD_H
+#define HAL_PAL_LLD_H
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+#undef PAL_MODE_RESET
+#undef PAL_MODE_UNCONNECTED
+#undef PAL_MODE_INPUT
+#undef PAL_MODE_INPUT_PULLUP
+#undef PAL_MODE_INPUT_PULLDOWN
+#undef PAL_MODE_INPUT_ANALOG
+#undef PAL_MODE_OUTPUT_PUSHPULL
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+/**
+ * @name STM32-specific I/O mode flags
+ * @{
+ */
+#define PAL_STM32_MODE_MASK (3U << 0U)
+#define PAL_STM32_MODE_INPUT (0U << 0U)
+#define PAL_STM32_MODE_OUTPUT (1U << 0U)
+#define PAL_STM32_MODE_ALTERNATE (2U << 0U)
+#define PAL_STM32_MODE_ANALOG (3U << 0U)
+
+#define PAL_STM32_OTYPE_MASK (1U << 2U)
+#define PAL_STM32_OTYPE_PUSHPULL (0U << 2U)
+#define PAL_STM32_OTYPE_OPENDRAIN (1U << 2U)
+
+#define PAL_STM32_OSPEED_MASK (3U << 3U)
+#define PAL_STM32_OSPEED_LOW (0U << 3U)
+#define PAL_STM32_OSPEED_MEDIUM (1U << 3U)
+#define PAL_STM32_OSPEED_FAST (2U << 3U)
+#define PAL_STM32_OSPEED_HIGH (3U << 3U)
+
+#define PAL_STM32_PUPDR_MASK (3U << 5U)
+#define PAL_STM32_PUPDR_FLOATING (0U << 5U)
+#define PAL_STM32_PUPDR_PULLUP (1U << 5U)
+#define PAL_STM32_PUPDR_PULLDOWN (2U << 5U)
+
+#define PAL_STM32_ALTERNATE_MASK (15U << 7U)
+#define PAL_STM32_ALTERNATE(n) ((n) << 7U)
+
+#define PAL_STM32_ASCR_MASK (1U << 11U)
+#define PAL_STM32_ASCR_OFF (0U << 11U)
+#define PAL_STM32_ASCR_ON (1U << 11U)
+
+#define PAL_STM32_LOCKR_MASK (1U << 12U)
+#define PAL_STM32_LOCKR_OFF (0U << 12U)
+#define PAL_STM32_LOCKR_ON (1U << 12U)
+
+/**
+ * @brief Alternate function.
+ *
+ * @param[in] n alternate function selector
+ */
+#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \
+ PAL_STM32_ALTERNATE(n))
+/** @} */
+
+/**
+ * @name Standard I/O mode flags
+ * @{
+ */
+/**
+ * @brief Implemented as input.
+ */
+#define PAL_MODE_RESET PAL_STM32_MODE_INPUT
+
+/**
+ * @brief Implemented as analog with analog switch disabled and lock.
+ */
+#define PAL_MODE_UNCONNECTED (PAL_STM32_MODE_ANALOG | \
+ PAL_STM32_ASCR_OFF | \
+ PAL_STM32_LOCKR_ON)
+
+/**
+ * @brief Regular input high-Z pad.
+ */
+#define PAL_MODE_INPUT PAL_STM32_MODE_INPUT
+
+/**
+ * @brief Input pad with weak pull up resistor.
+ */
+#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \
+ PAL_STM32_PUPDR_PULLUP)
+
+/**
+ * @brief Input pad with weak pull down resistor.
+ */
+#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \
+ PAL_STM32_PUPDR_PULLDOWN)
+
+/**
+ * @brief Analog input mode.
+ */
+#define PAL_MODE_INPUT_ANALOG (PAL_STM32_MODE_ANALOG | \
+ PAL_STM32_ASCR_ON)
+
+/**
+ * @brief Push-pull output pad.
+ */
+#define PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | \
+ PAL_STM32_OTYPE_PUSHPULL)
+
+/**
+ * @brief Open-drain output pad.
+ */
+#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \
+ PAL_STM32_OTYPE_OPENDRAIN)
+/** @} */
+
+/* Discarded definitions from the ST headers, the PAL driver uses its own
+ definitions in order to have an unified handling for all devices.
+ Unfortunately the ST headers have no uniform definitions for the same
+ objects across the various sub-families.*/
+#undef GPIOA
+#undef GPIOB
+#undef GPIOC
+#undef GPIOD
+#undef GPIOE
+#undef GPIOF
+#undef GPIOG
+#undef GPIOH
+#undef GPIOI
+#undef GPIOJ
+#undef GPIOK
+
+/**
+ * @name GPIO ports definitions
+ * @{
+ */
+#define GPIOA ((stm32_gpio_t *)GPIOA_BASE)
+#define GPIOB ((stm32_gpio_t *)GPIOB_BASE)
+#define GPIOC ((stm32_gpio_t *)GPIOC_BASE)
+#define GPIOD ((stm32_gpio_t *)GPIOD_BASE)
+#define GPIOE ((stm32_gpio_t *)GPIOE_BASE)
+#define GPIOF ((stm32_gpio_t *)GPIOF_BASE)
+#define GPIOG ((stm32_gpio_t *)GPIOG_BASE)
+#define GPIOH ((stm32_gpio_t *)GPIOH_BASE)
+#define GPIOI ((stm32_gpio_t *)GPIOI_BASE)
+#define GPIOJ ((stm32_gpio_t *)GPIOJ_BASE)
+#define GPIOK ((stm32_gpio_t *)GPIOK_BASE)
+/** @} */
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+/**
+ * @name Port related definitions
+ * @{
+ */
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 16
+
+/**
+ * @brief Whole port mask.
+ * @details This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
+/** @} */
+
+/**
+ * @name Line handling macros
+ * @{
+ */
+/**
+ * @brief Forms a line identifier.
+ * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
+ * of this type is platform-dependent.
+ * @note In this driver the pad number is encoded in the lower 4 bits of
+ * the GPIO address which are guaranteed to be zero.
+ */
+#define PAL_LINE(port, pad) \
+ ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
+
+/**
+ * @brief Decodes a port identifier from a line identifier.
+ */
+#define PAL_PORT(line) \
+ ((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U))
+
+/**
+ * @brief Decodes a pad identifier from a line identifier.
+ */
+#define PAL_PAD(line) \
+ ((uint32_t)((uint32_t)(line) & 0x0000000FU))
+
+/**
+ * @brief Value identifying an invalid line.
+ */
+#define PAL_NOLINE 0U
+/** @} */
+
+/**
+ * @brief STM32 GPIO registers block.
+ */
+typedef struct {
+
+ volatile uint32_t MODER;
+ volatile uint32_t OTYPER;
+ volatile uint32_t OSPEEDR;
+ volatile uint32_t PUPDR;
+ volatile uint32_t IDR;
+ volatile uint32_t ODR;
+ volatile union {
+ uint32_t W;
+ struct {
+ uint16_t set;
+ uint16_t clear;
+ } H;
+ } BSRR;
+ volatile uint32_t LOCKR;
+ volatile uint32_t AFRL;
+ volatile uint32_t AFRH;
+ volatile uint32_t BRR;
+ volatile uint32_t ASCR;
+} stm32_gpio_t;
+
+/**
+ * @brief GPIO port setup info.
+ */
+typedef struct {
+ /** Initial value for MODER register.*/
+ uint32_t moder;
+ /** Initial value for OTYPER register.*/
+ uint32_t otyper;
+ /** Initial value for OSPEEDR register.*/
+ uint32_t ospeedr;
+ /** Initial value for PUPDR register.*/
+ uint32_t pupdr;
+ /** Initial value for ODR register.*/
+ uint32_t odr;
+ /** Initial value for AFRL register.*/
+ uint32_t afrl;
+ /** Initial value for AFRH register.*/
+ uint32_t afrh;
+ /** Initial value for ASCR register.*/
+ uint32_t ascr;
+ /** Initial value for LOCKR register.*/
+ uint32_t lockr;
+} stm32_gpio_setup_t;
+
+/**
+ * @brief STM32 GPIO static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialize the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ /** @brief Port A setup data.*/
+ stm32_gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ /** @brief Port B setup data.*/
+ stm32_gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ /** @brief Port C setup data.*/
+ stm32_gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ /** @brief Port D setup data.*/
+ stm32_gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ /** @brief Port E setup data.*/
+ stm32_gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ /** @brief Port F setup data.*/
+ stm32_gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ /** @brief Port G setup data.*/
+ stm32_gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ /** @brief Port H setup data.*/
+ stm32_gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ /** @brief Port I setup data.*/
+ stm32_gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ /** @brief Port I setup data.*/
+ stm32_gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ /** @brief Port I setup data.*/
+ stm32_gpio_setup_t PKData;
+#endif
+} PALConfig;
+
+/**
+ * @brief Type of digital I/O port sized unsigned integer.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief Type of digital I/O modes.
+ */
+typedef uint32_t iomode_t;
+
+/**
+ * @brief Type of an I/O line.
+ */
+typedef uint32_t ioline_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef stm32_gpio_t * ioportid_t;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/* The low level driver wraps the definitions already present in the STM32 */
+/* firmware library. */
+/*===========================================================================*/
+
+/**
+ * @brief GPIO port A identifier.
+ */
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+#define IOPORT1 GPIOA
+#endif
+
+/**
+ * @brief GPIO port B identifier.
+ */
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+#define IOPORT2 GPIOB
+#endif
+
+/**
+ * @brief GPIO port C identifier.
+ */
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+#define IOPORT3 GPIOC
+#endif
+
+/**
+ * @brief GPIO port D identifier.
+ */
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+#define IOPORT4 GPIOD
+#endif
+
+/**
+ * @brief GPIO port E identifier.
+ */
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+#define IOPORT5 GPIOE
+#endif
+
+/**
+ * @brief GPIO port F identifier.
+ */
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+#define IOPORT6 GPIOF
+#endif
+
+/**
+ * @brief GPIO port G identifier.
+ */
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+#define IOPORT7 GPIOG
+#endif
+
+/**
+ * @brief GPIO port H identifier.
+ */
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+#define IOPORT8 GPIOH
+#endif
+
+/**
+ * @brief GPIO port I identifier.
+ */
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+#define IOPORT9 GPIOI
+#endif
+
+/**
+ * @brief GPIO port J identifier.
+ */
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+#define IOPORT10 GPIOJ
+#endif
+
+/**
+ * @brief GPIO port K identifier.
+ */
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+#define IOPORT11 GPIOK
+#endif
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief GPIO ports subsystem initialization.
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief Reads an I/O port.
+ * @details This function is implemented by reading the GPIO IDR register, the
+ * implementation has no side effects.
+ * @note This function is not meant to be invoked directly by the application
+ * code.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) ((port)->IDR)
+
+/**
+ * @brief Reads the output latch.
+ * @details This function is implemented by reading the GPIO ODR register, the
+ * implementation has no side effects.
+ * @note This function is not meant to be invoked directly by the application
+ * code.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) ((port)->ODR)
+
+/**
+ * @brief Writes on a I/O port.
+ * @details This function is implemented by writing the GPIO ODR register, the
+ * implementation has no side effects.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
+
+/**
+ * @brief Sets a bits mask on a I/O port.
+ * @details This function is implemented by writing the GPIO BSRR register, the
+ * implementation has no side effects.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits))
+
+/**
+ * @brief Clears a bits mask on a I/O port.
+ * @details This function is implemented by writing the GPIO BSRR register, the
+ * implementation has no side effects.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits))
+
+/**
+ * @brief Writes a group of bits.
+ * @details This function is implemented by writing the GPIO BSRR register, the
+ * implementation has no side effects.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset the group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group
+ * width are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits) \
+ ((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \
+ (((bits) & (mask)) << (offset)))
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] mode group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode) \
+ _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief Writes a logical state on an output pad.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
+
+extern const PALConfig pal_default_config;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* HAL_PAL_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/driver.mk
new file mode 100644
index 0000000000..f8cca018e9
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/driver.mk
@@ -0,0 +1,21 @@
+ifeq ($(USE_HAL_I2C_FALLBACK),yes)
+ # Fallback SW driver.
+ ifeq ($(USE_SMART_BUILD),yes)
+ ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+ PLATFORMSRC += $(CHIBIOS)/os/hal/lib/fallback/I2C/hal_i2c_lld.c
+ endif
+ else
+ PLATFORMSRC += $(CHIBIOS)/os/hal/lib/fallback/I2C/hal_i2c_lld.c
+ endif
+ PLATFORMINC += $(CHIBIOS)/os/hal/lib/fallback/I2C
+else
+ # Default HW driver.
+ ifeq ($(USE_SMART_BUILD),yes)
+ ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
+ endif
+ else
+ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
+ endif
+ PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1
+endif
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv1/i2c_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
similarity index 73%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
index 1ecfaa1154..479c6aa97f 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,14 +19,13 @@
*/
/**
- * @file STM32/I2Cv1/i2c_lld.c
+ * @file I2Cv1/hal_i2c_lld.c
* @brief STM32 I2C subsystem low level driver source.
*
* @addtogroup I2C
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_I2C || defined(__DOXYGEN__)
@@ -113,25 +112,6 @@ I2CDriver I2CD3;
/* Driver local functions. */
/*===========================================================================*/
-/**
- * @brief Wakes up the waiting thread.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] msg wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) { \
- chSysLockFromIsr(); \
- if ((i2cp)->thread != NULL) { \
- Thread *tp = (i2cp)->thread; \
- (i2cp)->thread = NULL; \
- tp->p_u.rdymsg = (msg); \
- chSchReadyI(tp); \
- } \
- chSysUnlockFromIsr(); \
-}
-
/**
* @brief Aborts an I2C transaction.
*
@@ -153,27 +133,6 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) {
dmaStreamDisable(i2cp->dmarx);
}
-/**
- * @brief Handling of stalled I2C transactions.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_safety_timeout(void *p) {
- I2CDriver *i2cp = (I2CDriver *)p;
-
- chSysLockFromIsr();
- if (i2cp->thread) {
- Thread *tp = i2cp->thread;
- i2c_lld_abort_operation(i2cp);
- i2cp->thread = NULL;
- tp->p_u.rdymsg = RDY_TIMEOUT;
- chSchReadyI(tp);
- }
- chSysUnlockFromIsr();
-}
-
/**
* @brief Set clock speed.
*
@@ -187,8 +146,9 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
int32_t clock_speed = i2cp->config->clock_speed;
i2cdutycycle_t duty = i2cp->config->duty_cycle;
- chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000),
- "i2c_lld_set_clock");
+ osalDbgCheck((i2cp != NULL) &&
+ (clock_speed > 0) &&
+ (clock_speed <= 4000000));
/* CR2 Configuration.*/
dp->CR2 &= (uint16_t)~I2C_CR2_FREQ;
@@ -200,19 +160,15 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
if (clock_speed <= 100000) {
/* Configure clock_div in standard mode.*/
- chDbgAssert(duty == STD_DUTY_CYCLE,
- "i2c_lld_set_clock(), #1",
- "Invalid standard mode duty cycle");
+ osalDbgAssert(duty == STD_DUTY_CYCLE, "invalid standard mode duty cycle");
/* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/
- chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0,
- "i2c_lld_set_clock(), #2",
- "PCLK1 must be divided without remainder");
+ osalDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0,
+ "PCLK1 must be divisible without remainder");
clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
- chDbgAssert(clock_div >= 0x04,
- "i2c_lld_set_clock(), #3",
- "Clock divider less then 0x04 not allowed");
+ osalDbgAssert(clock_div >= 0x04,
+ "clock divider less then 0x04 not allowed");
regCCR |= (clock_div & I2C_CCR_CCR);
/* Sets the Maximum Rise Time for standard mode.*/
@@ -220,37 +176,33 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
}
else if (clock_speed <= 400000) {
/* Configure clock_div in fast mode.*/
- chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9),
- "i2c_lld_set_clock(), #4",
- "Invalid fast mode duty cycle");
+ osalDbgAssert((duty == FAST_DUTY_CYCLE_2) ||
+ (duty == FAST_DUTY_CYCLE_16_9),
+ "invalid fast mode duty cycle");
if (duty == FAST_DUTY_CYCLE_2) {
/* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/
- chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0,
- "i2c_lld_set_clock(), #5",
- "PCLK1 must be divided without remainder");
+ osalDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0,
+ "PCLK1 must be divided without remainder");
clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
}
else if (duty == FAST_DUTY_CYCLE_16_9) {
/* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/
- chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0,
- "i2c_lld_set_clock(), #6",
- "PCLK1 must be divided without remainder");
+ osalDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0,
+ "PCLK1 must be divided without remainder");
clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
regCCR |= I2C_CCR_DUTY;
}
- chDbgAssert(clock_div >= 0x01,
- "i2c_lld_set_clock(), #7",
- "Clock divider less then 0x04 not allowed");
+ osalDbgAssert(clock_div >= 0x01,
+ "clock divider less then 0x04 not allowed");
regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR));
/* Sets the Maximum Rise Time for fast mode.*/
dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1;
}
- chDbgAssert((clock_div <= I2C_CCR_CCR),
- "i2c_lld_set_clock(), #8", "the selected clock is too low");
+ osalDbgAssert((clock_div <= I2C_CCR_CCR), "the selected clock is too low");
dp->CCR = regCCR;
}
@@ -332,7 +284,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
}
dp->CR2 &= ~I2C_CR2_ITEVTEN;
dp->CR1 |= I2C_CR1_STOP;
- wakeup_isr(i2cp, RDY_OK);
+ _i2c_wakeup_isr(i2cp);
break;
default:
break;
@@ -367,7 +319,7 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
dp->CR2 &= ~I2C_CR2_LAST;
dp->CR1 &= ~I2C_CR1_ACK;
dp->CR1 |= I2C_CR1_STOP;
- wakeup_isr(i2cp, RDY_OK);
+ _i2c_wakeup_isr(i2cp);
}
/**
@@ -410,35 +362,35 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) {
dmaStreamDisable(i2cp->dmatx);
dmaStreamDisable(i2cp->dmarx);
- i2cp->errors = I2CD_NO_ERROR;
+ i2cp->errors = I2C_NO_ERROR;
if (sr & I2C_SR1_BERR) /* Bus error. */
- i2cp->errors |= I2CD_BUS_ERROR;
+ i2cp->errors |= I2C_BUS_ERROR;
if (sr & I2C_SR1_ARLO) /* Arbitration lost. */
- i2cp->errors |= I2CD_ARBITRATION_LOST;
+ i2cp->errors |= I2C_ARBITRATION_LOST;
if (sr & I2C_SR1_AF) { /* Acknowledge fail. */
i2cp->i2c->CR2 &= ~I2C_CR2_ITEVTEN;
i2cp->i2c->CR1 |= I2C_CR1_STOP; /* Setting stop bit. */
- i2cp->errors |= I2CD_ACK_FAILURE;
+ i2cp->errors |= I2C_ACK_FAILURE;
}
if (sr & I2C_SR1_OVR) /* Overrun. */
- i2cp->errors |= I2CD_OVERRUN;
+ i2cp->errors |= I2C_OVERRUN;
if (sr & I2C_SR1_TIMEOUT) /* SMBus Timeout. */
- i2cp->errors |= I2CD_TIMEOUT;
+ i2cp->errors |= I2C_TIMEOUT;
if (sr & I2C_SR1_PECERR) /* PEC error. */
- i2cp->errors |= I2CD_PEC_ERROR;
+ i2cp->errors |= I2C_PEC_ERROR;
if (sr & I2C_SR1_SMBALERT) /* SMBus alert. */
- i2cp->errors |= I2CD_SMB_ALERT;
+ i2cp->errors |= I2C_SMB_ALERT;
/* If some error has been identified then sends wakes the waiting thread.*/
- if (i2cp->errors != I2CD_NO_ERROR)
- wakeup_isr(i2cp, RDY_RESET);
+ if (i2cp->errors != I2C_NO_ERROR)
+ _i2c_wakeup_error_isr(i2cp);
}
/*===========================================================================*/
@@ -451,27 +403,27 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) {
*
* @notapi
*/
-CH_IRQ_HANDLER(I2C1_EV_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
i2c_lld_serve_event_interrupt(&I2CD1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
* @brief I2C1 error interrupt handler.
*/
-CH_IRQ_HANDLER(I2C1_ER_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) {
uint16_t sr = I2CD1.i2c->SR1;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
I2CD1.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
i2c_lld_serve_error_interrupt(&I2CD1, sr);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_I2C_USE_I2C1 */
@@ -481,13 +433,13 @@ CH_IRQ_HANDLER(I2C1_ER_IRQHandler) {
*
* @notapi
*/
-CH_IRQ_HANDLER(I2C2_EV_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
i2c_lld_serve_event_interrupt(&I2CD2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -495,15 +447,15 @@ CH_IRQ_HANDLER(I2C2_EV_IRQHandler) {
*
* @notapi
*/
-CH_IRQ_HANDLER(I2C2_ER_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) {
uint16_t sr = I2CD2.i2c->SR1;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
I2CD2.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
i2c_lld_serve_error_interrupt(&I2CD2, sr);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_I2C_USE_I2C2 */
@@ -513,13 +465,13 @@ CH_IRQ_HANDLER(I2C2_ER_IRQHandler) {
*
* @notapi
*/
-CH_IRQ_HANDLER(I2C3_EV_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_I2C3_EVENT_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
i2c_lld_serve_event_interrupt(&I2CD3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -527,15 +479,15 @@ CH_IRQ_HANDLER(I2C3_EV_IRQHandler) {
*
* @notapi
*/
-CH_IRQ_HANDLER(I2C3_ER_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_I2C3_ERROR_HANDLER) {
uint16_t sr = I2CD3.i2c->SR1;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
I2CD3.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
i2c_lld_serve_error_interrupt(&I2CD3, sr);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_I2C_USE_I2C3 */
@@ -585,38 +537,36 @@ void i2c_lld_init(void) {
void i2c_lld_start(I2CDriver *i2cp) {
I2C_TypeDef *dp = i2cp->i2c;
- i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
- STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
- STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DIR_M2P;
- i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
- STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
- STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DIR_P2M;
-
/* If in stopped state then enables the I2C and DMA clocks.*/
if (i2cp->state == I2C_STOP) {
+ i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DIR_M2P;
+ i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DIR_P2M;
+
#if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) {
- bool_t b;
+ bool b;
rccResetI2C1();
b = dmaStreamAllocate(i2cp->dmarx,
STM32_I2C_I2C1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
STM32_I2C_I2C1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableI2C1(FALSE);
- nvicEnableVector(I2C1_EV_IRQn,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
- nvicEnableVector(I2C1_ER_IRQn,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
+ nvicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
+ nvicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
@@ -627,24 +577,22 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) {
- bool_t b;
+ bool b;
rccResetI2C2();
b = dmaStreamAllocate(i2cp->dmarx,
STM32_I2C_I2C2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
STM32_I2C_I2C2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableI2C2(FALSE);
- nvicEnableVector(I2C2_EV_IRQn,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
- nvicEnableVector(I2C2_ER_IRQn,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
+ nvicEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
+ nvicEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
@@ -655,24 +603,22 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_I2C3
if (&I2CD3 == i2cp) {
- bool_t b;
+ bool b;
rccResetI2C3();
b = dmaStreamAllocate(i2cp->dmarx,
STM32_I2C_I2C3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #5", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
STM32_I2C_I2C3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
- chDbgAssert(!b, "i2c_lld_start(), #6", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableI2C3(FALSE);
- nvicEnableVector(I2C3_EV_IRQn,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY));
- nvicEnableVector(I2C3_ER_IRQn,
- CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY));
+ nvicEnableVector(I2C3_EV_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY);
+ nvicEnableVector(I2C3_ER_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY);
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
@@ -756,10 +702,10 @@ void i2c_lld_stop(I2CDriver *i2cp) {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a
* timeout the driver must be stopped and restarted
* because the bus is in an uncertain state.
*
@@ -769,56 +715,54 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
uint8_t *rxbuf, size_t rxbytes,
systime_t timeout) {
I2C_TypeDef *dp = i2cp->i2c;
- VirtualTimer vt;
+ systime_t start, end;
#if defined(STM32F1XX_I2C)
- chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout");
+ osalDbgCheck(rxbytes > 1);
#endif
- /* Global timeout for the whole operation.*/
- if (timeout != TIME_INFINITE)
- chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
- /* Releases the lock from high level driver.*/
- chSysUnlock();
+ /* Resetting error flags for this transfer.*/
+ i2cp->errors = I2C_NO_ERROR;
/* Initializes driver fields, LSB = 1 -> receive.*/
i2cp->addr = (addr << 1) | 0x01;
- i2cp->errors = 0;
+
+ /* Releases the lock from high level driver.*/
+ osalSysUnlock();
/* RX DMA setup.*/
dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
- /* Waits until BUSY flag is reset and the STOP from the previous operation
- is completed, alternatively for a timeout condition.*/
- while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) {
- chSysLock();
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
- chSysUnlock();
- }
+ /* Calculating the time window for the timeout on the busy bus condition.*/
+ start = osalOsGetSystemTimeX();
+ end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT);
+
+ /* Waits until BUSY flag is reset or, alternatively, for a timeout
+ condition.*/
+ while (true) {
+ osalSysLock();
+
+ /* If the bus is not busy then the operation can continue, note, the
+ loop is exited in the locked state.*/
+ if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP))
+ break;
- /* This lock will be released in high level driver.*/
- chSysLock();
+ /* If the system time went outside the allowed window then a timeout
+ condition is returned.*/
+ if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+ return MSG_TIMEOUT;
- /* Atomic check on the timer in order to make sure that a timeout didn't
- happen outside the critical zone.*/
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
+ osalSysUnlock();
+ }
/* Starts the operation.*/
dp->CR2 |= I2C_CR2_ITEVTEN;
dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
/* Waits for the operation completion or a timeout.*/
- i2cp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
- chVTResetI(&vt);
-
- return chThdSelf()->p_u.rdymsg;
+ return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
}
/**
@@ -837,10 +781,10 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a
* timeout the driver must be stopped and restarted
* because the bus is in an uncertain state.
*
@@ -851,23 +795,20 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
uint8_t *rxbuf, size_t rxbytes,
systime_t timeout) {
I2C_TypeDef *dp = i2cp->i2c;
- VirtualTimer vt;
+ systime_t start, end;
#if defined(STM32F1XX_I2C)
- chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))),
- "i2c_lld_master_transmit_timeout");
+ osalDbgCheck((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL)));
#endif
- /* Global timeout for the whole operation.*/
- if (timeout != TIME_INFINITE)
- chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
+ /* Resetting error flags for this transfer.*/
+ i2cp->errors = I2C_NO_ERROR;
- /* Releases the lock from high level driver.*/
- chSysUnlock();
+ /* Initializes driver fields, LSB = 0 -> transmit.*/
+ i2cp->addr = (addr << 1);
- /* Initializes driver fields, LSB = 0 -> write.*/
- i2cp->addr = addr << 1;
- i2cp->errors = 0;
+ /* Releases the lock from high level driver.*/
+ osalSysUnlock();
/* TX DMA setup.*/
dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
@@ -879,34 +820,34 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
- /* Waits until BUSY flag is reset and the STOP from the previous operation
- is completed, alternatively for a timeout condition.*/
- while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) {
- chSysLock();
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
- chSysUnlock();
- }
+ /* Calculating the time window for the timeout on the busy bus condition.*/
+ start = osalOsGetSystemTimeX();
+ end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT);
- /* This lock will be released in high level driver.*/
- chSysLock();
+ /* Waits until BUSY flag is reset or, alternatively, for a timeout
+ condition.*/
+ while (true) {
+ osalSysLock();
- /* Atomic check on the timer in order to make sure that a timeout didn't
- happen outside the critical zone.*/
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
+ /* If the bus is not busy then the operation can continue, note, the
+ loop is exited in the locked state.*/
+ if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP))
+ break;
+
+ /* If the system time went outside the allowed window then a timeout
+ condition is returned.*/
+ if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+ return MSG_TIMEOUT;
+
+ osalSysUnlock();
+ }
/* Starts the operation.*/
dp->CR2 |= I2C_CR2_ITEVTEN;
dp->CR1 |= I2C_CR1_START;
/* Waits for the operation completion or a timeout.*/
- i2cp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
- chVTResetI(&vt);
-
- return chThdSelf()->p_u.rdymsg;
+ return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
}
#endif /* HAL_USE_I2C */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv1/i2c_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.h
similarity index 77%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv1/i2c_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.h
index 5844841fae..a0ed7a80b6 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv1/i2c_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,15 +19,15 @@
*/
/**
- * @file STM32/I2Cv1/i2c_lld.h
+ * @file I2Cv1/hal_i2c_lld.h
* @brief STM32 I2C subsystem low level driver header.
*
* @addtogroup I2C
* @{
*/
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
+#ifndef HAL_I2C_LLD_H
+#define HAL_I2C_LLD_H
#if HAL_USE_I2C || defined(__DOXYGEN__)
@@ -54,7 +54,7 @@
* @note The default is @p FALSE.
*/
#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C1 FALSE
#endif
/**
@@ -63,7 +63,7 @@
* @note The default is @p FALSE.
*/
#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
-#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
#endif
/**
@@ -72,28 +72,35 @@
* @note The default is @p FALSE.
*/
#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__)
-#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#endif
+
+/**
+ * @brief I2C timeout on busy condition in milliseconds.
+ */
+#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
+#define STM32_I2C_BUSY_TIMEOUT 50
#endif
/**
* @brief I2C1 interrupt priority level setting.
*/
#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_IRQ_PRIORITY 10
+#define STM32_I2C_I2C1_IRQ_PRIORITY 10
#endif
/**
* @brief I2C2 interrupt priority level setting.
*/
#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_IRQ_PRIORITY 10
+#define STM32_I2C_I2C2_IRQ_PRIORITY 10
#endif
/**
* @brief I2C3 interrupt priority level setting.
*/
#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C3_IRQ_PRIORITY 10
+#define STM32_I2C_I2C3_IRQ_PRIORITY 10
#endif
/**
@@ -132,7 +139,7 @@
* error can only happen because programming errors.
*/
#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt()
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
#endif
#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
@@ -142,7 +149,7 @@
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#endif
/**
@@ -150,7 +157,7 @@
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#endif
/**
@@ -158,7 +165,7 @@
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#endif
/**
@@ -166,7 +173,7 @@
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#endif
/**
@@ -174,7 +181,7 @@
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#endif
/**
@@ -182,25 +189,25 @@
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#endif
#else /* !STM32_ADVANCED_DMA */
/* Fixed streams for platforms using the old DMA peripheral, the values are
valid for both STM32F1xx and STM32L1xx.*/
-#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
-#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#endif /* !STM32_ADVANCED_DMA*/
/* Flag for the whole STM32F1XX family. */
#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_LD) || defined(STM32F10X_MD) || \
- defined(STM32F10X_HD) || defined(STM32F10X_XL) || \
- defined(STM32F10X_CL)
+ defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \
+ defined(STM32F10X_MD) || defined(STM32F10X_HD) || \
+ defined(STM32F10X_XL) || defined(STM32F10X_CL)
#define STM32F1XX_I2C
#endif
/** @} */
@@ -227,6 +234,51 @@
#error "I2C driver activated but no I2C peripheral assigned"
#endif
+#if STM32_I2C_USE_I2C1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C1"
+#endif
+
+#if STM32_I2C_USE_I2C2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C2"
+#endif
+
+#if STM32_I2C_USE_I2C3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C3"
+#endif
+
+#if STM32_I2C_USE_I2C1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C1"
+#endif
+
+#if STM32_I2C_USE_I2C2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C2"
+#endif
+
+#if STM32_I2C_USE_I2C3 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C3"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) || \
+ !defined(STM32_I2C_I2C1_TX_DMA_STREAM))
+#error "I2C1 DMA streams not defined"
+#endif
+
+#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) || \
+ !defined(STM32_I2C_I2C2_TX_DMA_STREAM))
+#error "I2C2 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
#if STM32_I2C_USE_I2C1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \
STM32_I2C1_RX_DMA_MSK)
@@ -262,6 +314,7 @@
STM32_I2C3_TX_DMA_MSK)
#error "invalid DMA stream associated to I2C3 TX"
#endif
+#endif /* STM32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
@@ -304,12 +357,12 @@
/*===========================================================================*/
/**
- * @brief Type representing I2C address.
+ * @brief Type representing an I2C address.
*/
typedef uint16_t i2caddr_t;
/**
- * @brief I2C Driver condition flags type.
+ * @brief Type of I2C driver condition flags.
*/
typedef uint32_t i2cflags_t;
@@ -332,9 +385,10 @@ typedef enum {
} i2cdutycycle_t;
/**
- * @brief Driver configuration structure.
+ * @brief Type of I2C driver configuration structure.
*/
typedef struct {
+ /* End of the mandatory fields.*/
i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */
uint32_t clock_speed; /**< @brief Specifies the clock frequency.
@note Must be set to a value lower
@@ -349,7 +403,7 @@ typedef struct {
typedef struct I2CDriver I2CDriver;
/**
- * @brief Structure representing an I2C driver.
+ * @brief Structure representing an I2C driver.
*/
struct I2CDriver {
/**
@@ -365,14 +419,10 @@ struct I2CDriver {
*/
i2cflags_t errors;
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
+ mutex_t mutex;
#endif /* I2C_USE_MUTUAL_EXCLUSION */
#if defined(I2C_DRIVER_EXT_FIELDS)
I2C_DRIVER_EXT_FIELDS
@@ -381,7 +431,7 @@ struct I2CDriver {
/**
* @brief Thread waiting for I/O completion.
*/
- Thread *thread;
+ thread_reference_t thread;
/**
* @brief Current slave address without R/W bit.
*/
@@ -458,6 +508,6 @@ extern "C" {
#endif /* HAL_USE_I2C */
-#endif /* _I2C_LLD_H_ */
+#endif /* HAL_I2C_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
new file mode 100644
index 0000000000..06fb82ff8f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
@@ -0,0 +1,21 @@
+ifeq ($(USE_HAL_I2C_FALLBACK),yes)
+ # Fallback SW driver.
+ ifeq ($(USE_SMART_BUILD),yes)
+ ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+ PLATFORMSRC += $(CHIBIOS)/os/hal/lib/fallback/I2C/hal_i2c_lld.c
+ endif
+ else
+ PLATFORMSRC += $(CHIBIOS)/os/hal/lib/fallback/I2C/hal_i2c_lld.c
+ endif
+ PLATFORMINC += $(CHIBIOS)/os/hal/lib/fallback/I2C
+else
+ # Default HW driver.
+ ifeq ($(USE_SMART_BUILD),yes)
+ ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c
+ endif
+ else
+ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c
+ endif
+ PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2
+endif
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c
new file mode 100644
index 0000000000..ee85cf6eef
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c
@@ -0,0 +1,1152 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file I2Cv2/hal_i2c_lld.c
+ * @brief STM32 I2C subsystem low level driver source.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if STM32_I2C_USE_DMA == TRUE
+#define DMAMODE_COMMON \
+ (STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | \
+ STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | \
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE)
+
+#define I2C1_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \
+ STM32_I2C1_RX_DMA_CHN)
+
+#define I2C1_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \
+ STM32_I2C1_TX_DMA_CHN)
+
+#define I2C2_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \
+ STM32_I2C2_RX_DMA_CHN)
+
+#define I2C2_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \
+ STM32_I2C2_TX_DMA_CHN)
+
+#define I2C3_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \
+ STM32_I2C3_RX_DMA_CHN)
+
+#define I2C3_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \
+ STM32_I2C3_TX_DMA_CHN)
+
+#define I2C4_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2C_I2C4_RX_DMA_STREAM, \
+ STM32_I2C4_RX_DMA_CHN)
+
+#define I2C4_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2C_I2C4_TX_DMA_STREAM, \
+ STM32_I2C4_TX_DMA_CHN)
+#endif /* STM32_I2C_USE_DMA == TRUE */
+
+#if STM32_I2C_USE_DMA == TRUE
+#define i2c_lld_get_rxbytes(i2cp) dmaStreamGetTransactionSize((i2cp)->dmarx)
+#define i2c_lld_get_txbytes(i2cp) dmaStreamGetTransactionSize((i2cp)->dmatx)
+#else
+#define i2c_lld_get_rxbytes(i2cp) (i2cp)->rxbytes
+#define i2c_lld_get_txbytes(i2cp) (i2cp)->txbytes
+#endif
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define I2C_ERROR_MASK \
+ ((uint32_t)(I2C_ISR_BERR | I2C_ISR_ARLO | I2C_ISR_OVR | I2C_ISR_PECERR | \
+ I2C_ISR_TIMEOUT | I2C_ISR_ALERT))
+
+#define I2C_INT_MASK \
+ ((uint32_t)(I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF | I2C_ISR_NACKF | \
+ I2C_ISR_ADDR | I2C_ISR_RXNE | I2C_ISR_TXIS))
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief I2C1 driver identifier.*/
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/** @brief I2C2 driver identifier.*/
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/** @brief I2C3 driver identifier.*/
+#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__)
+I2CDriver I2CD3;
+#endif
+
+/** @brief I2C4 driver identifier.*/
+#if STM32_I2C_USE_I2C4 || defined(__DOXYGEN__)
+I2CDriver I2CD4;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Slave address setup.
+ * @note The RW bit is set to zero internally.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ *
+ * @notapi
+ */
+static void i2c_lld_set_address(I2CDriver *i2cp, i2caddr_t addr) {
+ I2C_TypeDef *dp = i2cp->i2c;
+
+ /* Address alignment depends on the addressing mode selected.*/
+ if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0U)
+ dp->CR2 = (uint32_t)addr << 1U;
+ else
+ dp->CR2 = (uint32_t)addr;
+}
+
+/**
+ * @brief I2C RX transfer setup.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_setup_rx_transfer(I2CDriver *i2cp) {
+ I2C_TypeDef *dp = i2cp->i2c;
+ uint32_t reload;
+ size_t n;
+
+ /* The unit can transfer 255 bytes maximum in a single operation.*/
+ n = i2c_lld_get_rxbytes(i2cp);
+ if (n > 255U) {
+ n = 255U;
+ reload = I2C_CR2_RELOAD;
+ }
+ else {
+ reload = 0U;
+ }
+
+ /* Configures the CR2 registers with both the calculated and static
+ settings.*/
+ dp->CR2 = (dp->CR2 & ~(I2C_CR2_NBYTES | I2C_CR2_RELOAD)) | i2cp->config->cr2 |
+ I2C_CR2_RD_WRN | (n << 16U) | reload;
+}
+
+/**
+ * @brief I2C TX transfer setup.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_setup_tx_transfer(I2CDriver *i2cp) {
+ I2C_TypeDef *dp = i2cp->i2c;
+ uint32_t reload;
+ size_t n;
+
+ /* The unit can transfer 255 bytes maximum in a single operation.*/
+ n = i2c_lld_get_txbytes(i2cp);
+ if (n > 255U) {
+ n = 255U;
+ reload = I2C_CR2_RELOAD;
+ }
+ else {
+ reload = 0U;
+ }
+
+ /* Configures the CR2 registers with both the calculated and static
+ settings.*/
+ dp->CR2 = (dp->CR2 & ~(I2C_CR2_NBYTES | I2C_CR2_RELOAD)) | i2cp->config->cr2 |
+ (n << 16U) | reload;
+}
+
+/**
+ * @brief Aborts an I2C transaction.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_abort_operation(I2CDriver *i2cp) {
+ I2C_TypeDef *dp = i2cp->i2c;
+
+ if (dp->CR1 & I2C_CR1_PE) {
+ /* Stops the I2C peripheral.*/
+ dp->CR1 &= ~I2C_CR1_PE;
+ while (dp->CR1 & I2C_CR1_PE)
+ dp->CR1 &= ~I2C_CR1_PE;
+ dp->CR1 |= I2C_CR1_PE;
+ }
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* Stops the associated DMA streams.*/
+ dmaStreamDisable(i2cp->dmatx);
+ dmaStreamDisable(i2cp->dmarx);
+#else
+ dp->CR1 &= ~(I2C_CR1_TXIE | I2C_CR1_RXIE);
+#endif
+}
+
+/**
+ * @brief I2C shared ISR code.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] isr content of the ISR register to be decoded
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t isr) {
+ I2C_TypeDef *dp = i2cp->i2c;
+
+ /* Special case of a received NACK, the transfer is aborted.*/
+ if ((isr & I2C_ISR_NACKF) != 0U) {
+#if STM32_I2C_USE_DMA == TRUE
+ /* Stops the associated DMA streams.*/
+ dmaStreamDisable(i2cp->dmatx);
+ dmaStreamDisable(i2cp->dmarx);
+#endif
+
+ /* Error flag.*/
+ i2cp->errors |= I2C_ACK_FAILURE;
+
+ /* Transaction finished sending the STOP.*/
+ dp->CR2 |= I2C_CR2_STOP;
+
+ /* Make sure no more interrupts.*/
+ dp->CR1 &= ~(I2C_CR1_TCIE | I2C_CR1_TXIE | I2C_CR1_RXIE);
+
+ /* Errors are signaled to the upper layer.*/
+ _i2c_wakeup_error_isr(i2cp);
+
+ return;
+ }
+
+#if STM32_I2C_USE_DMA == FALSE
+ /* Handling of data transfer if the DMA mode is disabled.*/
+ {
+ uint32_t cr1 = dp->CR1;
+
+ if (i2cp->state == I2C_ACTIVE_TX) {
+ /* Transmission phase.*/
+ if (((cr1 &I2C_CR1_TXIE) != 0U) && ((isr & I2C_ISR_TXIS) != 0U)) {
+ dp->TXDR = (uint32_t)*i2cp->txptr;
+ i2cp->txptr++;
+ i2cp->txbytes--;
+ if (i2cp->txbytes == 0U) {
+ dp->CR1 &= ~I2C_CR1_TXIE;
+ }
+ }
+ }
+ else {
+ /* Receive phase.*/
+ if (((cr1 & I2C_CR1_RXIE) != 0U) && ((isr & I2C_ISR_RXNE) != 0U)) {
+ *i2cp->rxptr = (uint8_t)dp->RXDR;
+ i2cp->rxptr++;
+ i2cp->rxbytes--;
+ if (i2cp->rxbytes == 0U) {
+ dp->CR1 &= ~I2C_CR1_RXIE;
+ }
+ }
+ }
+ }
+#endif
+
+ /* Partial transfer handling, restarting the transfer and returning.*/
+ if ((isr & I2C_ISR_TCR) != 0U) {
+ if (i2cp->state == I2C_ACTIVE_TX) {
+ i2c_lld_setup_tx_transfer(i2cp);
+ }
+ else {
+ i2c_lld_setup_rx_transfer(i2cp);
+ }
+ return;
+ }
+
+ /* The following condition is true if a transfer phase has been completed.*/
+ if ((isr & I2C_ISR_TC) != 0U) {
+ if (i2cp->state == I2C_ACTIVE_TX) {
+ /* End of the transmit phase.*/
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* Disabling TX DMA channel.*/
+ dmaStreamDisable(i2cp->dmatx);
+#endif
+
+ /* Starting receive phase if necessary.*/
+ if (i2c_lld_get_rxbytes(i2cp) > 0U) {
+ /* Setting up the peripheral.*/
+ i2c_lld_setup_rx_transfer(i2cp);
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* Enabling RX DMA.*/
+ dmaStreamEnable(i2cp->dmarx);
+#else
+ /* RX interrupt enabled.*/
+ dp->CR1 |= I2C_CR1_RXIE;
+#endif
+
+ /* Starts the read operation.*/
+ dp->CR2 |= I2C_CR2_START;
+
+ /* State change.*/
+ i2cp->state = I2C_ACTIVE_RX;
+
+ /* Note, returning because the transaction is not over yet.*/
+ return;
+ }
+ }
+ else {
+ /* End of the receive phase.*/
+#if STM32_I2C_USE_DMA == TRUE
+ /* Disabling RX DMA channel.*/
+ dmaStreamDisable(i2cp->dmarx);
+#endif
+ }
+
+ /* Transaction finished sending the STOP.*/
+ dp->CR2 |= I2C_CR2_STOP;
+
+ /* Make sure no more 'Transfer Complete' interrupts.*/
+ dp->CR1 &= ~I2C_CR1_TCIE;
+
+ /* Normal transaction end.*/
+ _i2c_wakeup_isr(i2cp);
+ }
+}
+
+/**
+ * @brief I2C error handler.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] isr content of the ISR register to be decoded
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t isr) {
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* Clears DMA interrupt flags just to be safe.*/
+ dmaStreamDisable(i2cp->dmatx);
+ dmaStreamDisable(i2cp->dmarx);
+#else
+ /* Disabling RX and TX interrupts.*/
+ i2cp->i2c->CR1 &= ~(I2C_CR1_TXIE | I2C_CR1_RXIE);
+#endif
+
+ if (isr & I2C_ISR_BERR)
+ i2cp->errors |= I2C_BUS_ERROR;
+
+ if (isr & I2C_ISR_ARLO)
+ i2cp->errors |= I2C_ARBITRATION_LOST;
+
+ if (isr & I2C_ISR_OVR)
+ i2cp->errors |= I2C_OVERRUN;
+
+ if (isr & I2C_ISR_TIMEOUT)
+ i2cp->errors |= I2C_TIMEOUT;
+
+ /* If some error has been identified then sends wakes the waiting thread.*/
+ if (i2cp->errors != I2C_NO_ERROR)
+ _i2c_wakeup_error_isr(i2cp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+#if defined(STM32_I2C1_GLOBAL_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief I2C1 event interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(STM32_I2C1_GLOBAL_HANDLER) {
+ uint32_t isr = I2CD1.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD1.i2c->ICR = isr;
+
+ if (isr & I2C_ERROR_MASK)
+ i2c_lld_serve_error_interrupt(&I2CD1, isr);
+ else if (isr & I2C_INT_MASK)
+ i2c_lld_serve_interrupt(&I2CD1, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#elif defined(STM32_I2C1_EVENT_HANDLER) && defined(STM32_I2C1_ERROR_HANDLER)
+OSAL_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) {
+ uint32_t isr = I2CD1.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD1.i2c->ICR = isr & I2C_INT_MASK;
+
+ i2c_lld_serve_interrupt(&I2CD1, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+OSAL_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) {
+ uint32_t isr = I2CD1.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD1.i2c->ICR = isr & I2C_ERROR_MASK;
+
+ i2c_lld_serve_error_interrupt(&I2CD1, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#else
+#error "I2C1 interrupt handlers not defined"
+#endif
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+#if defined(STM32_I2C2_GLOBAL_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief I2C2 event interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(STM32_I2C2_GLOBAL_HANDLER) {
+ uint32_t isr = I2CD2.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD2.i2c->ICR = isr;
+
+ if (isr & I2C_ERROR_MASK)
+ i2c_lld_serve_error_interrupt(&I2CD2, isr);
+ else if (isr & I2C_INT_MASK)
+ i2c_lld_serve_interrupt(&I2CD2, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#elif defined(STM32_I2C2_EVENT_HANDLER) && defined(STM32_I2C2_ERROR_HANDLER)
+OSAL_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) {
+ uint32_t isr = I2CD2.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD2.i2c->ICR = isr & I2C_INT_MASK;
+
+ i2c_lld_serve_interrupt(&I2CD2, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+OSAL_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) {
+ uint32_t isr = I2CD2.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD2.i2c->ICR = isr & I2C_ERROR_MASK;
+
+ i2c_lld_serve_error_interrupt(&I2CD2, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#else
+#error "I2C2 interrupt handlers not defined"
+#endif
+#endif /* STM32_I2C_USE_I2C2 */
+
+#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__)
+#if defined(STM32_I2C3_GLOBAL_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief I2C3 event interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(STM32_I2C3_GLOBAL_HANDLER) {
+ uint32_t isr = I2CD3.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD3.i2c->ICR = isr;
+
+ if (isr & I2C_ERROR_MASK)
+ i2c_lld_serve_error_interrupt(&I2CD3, isr);
+ else if (isr & I2C_INT_MASK)
+ i2c_lld_serve_interrupt(&I2CD3, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#elif defined(STM32_I2C3_EVENT_HANDLER) && defined(STM32_I2C3_ERROR_HANDLER)
+OSAL_IRQ_HANDLER(STM32_I2C3_EVENT_HANDLER) {
+ uint32_t isr = I2CD3.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD3.i2c->ICR = isr & I2C_INT_MASK;
+
+ i2c_lld_serve_interrupt(&I2CD3, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+OSAL_IRQ_HANDLER(STM32_I2C3_ERROR_HANDLER) {
+ uint32_t isr = I2CD3.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD3.i2c->ICR = isr & I2C_ERROR_MASK;
+
+ i2c_lld_serve_error_interrupt(&I2CD3, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#else
+#error "I2C3 interrupt handlers not defined"
+#endif
+#endif /* STM32_I2C_USE_I2C3 */
+
+#if STM32_I2C_USE_I2C4 || defined(__DOXYGEN__)
+#if defined(STM32_I2C4_GLOBAL_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief I2C4 event interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(STM32_I2C4_GLOBAL_HANDLER) {
+ uint32_t isr = I2CD4.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD4.i2c->ICR = isr;
+
+ if (isr & I2C_ERROR_MASK)
+ i2c_lld_serve_error_interrupt(&I2CD4, isr);
+ else if (isr & I2C_INT_MASK)
+ i2c_lld_serve_interrupt(&I2CD4, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#elif defined(STM32_I2C4_EVENT_HANDLER) && defined(STM32_I2C4_ERROR_HANDLER)
+OSAL_IRQ_HANDLER(STM32_I2C4_EVENT_HANDLER) {
+ uint32_t isr = I2CD4.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD4.i2c->ICR = isr & I2C_INT_MASK;
+
+ i2c_lld_serve_interrupt(&I2CD4, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+OSAL_IRQ_HANDLER(STM32_I2C4_ERROR_HANDLER) {
+ uint32_t isr = I2CD4.i2c->ISR;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clearing IRQ bits.*/
+ I2CD4.i2c->ICR = isr & I2C_ERROR_MASK;
+
+ i2c_lld_serve_error_interrupt(&I2CD4, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#else
+#error "I2C4 interrupt handlers not defined"
+#endif
+#endif /* STM32_I2C_USE_I2C4 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2C driver initialization.
+ *
+ * @notapi
+ */
+void i2c_lld_init(void) {
+
+#if STM32_I2C_USE_I2C1
+ i2cObjectInit(&I2CD1);
+ I2CD1.thread = NULL;
+ I2CD1.i2c = I2C1;
+#if STM32_I2C_USE_DMA == TRUE
+ I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
+ I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
+#endif
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2
+ i2cObjectInit(&I2CD2);
+ I2CD2.thread = NULL;
+ I2CD2.i2c = I2C2;
+#if STM32_I2C_USE_DMA == TRUE
+ I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
+ I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
+#endif
+#endif /* STM32_I2C_USE_I2C2 */
+
+#if STM32_I2C_USE_I2C3
+ i2cObjectInit(&I2CD3);
+ I2CD3.thread = NULL;
+ I2CD3.i2c = I2C3;
+#if STM32_I2C_USE_DMA == TRUE
+ I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM);
+ I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM);
+#endif
+#endif /* STM32_I2C_USE_I2C3 */
+
+#if STM32_I2C_USE_I2C4
+ i2cObjectInit(&I2CD4);
+ I2CD4.thread = NULL;
+ I2CD4.i2c = I2C4;
+#if STM32_I2C_USE_DMA == TRUE
+ I2CD4.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C4_RX_DMA_STREAM);
+ I2CD4.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C4_TX_DMA_STREAM);
+#endif
+#endif /* STM32_I2C_USE_I2C4 */
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+ I2C_TypeDef *dp = i2cp->i2c;
+
+ /* Make sure I2C peripheral is disabled */
+ dp->CR1 &= ~I2C_CR1_PE;
+
+ /* If in stopped state then enables the I2C and DMA clocks.*/
+ if (i2cp->state == I2C_STOP) {
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* Common DMA modes.*/
+ i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P;
+ i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M;
+#endif
+
+#if STM32_I2C_USE_I2C1
+ if (&I2CD1 == i2cp) {
+
+ rccResetI2C1();
+ rccEnableI2C1(FALSE);
+#if STM32_I2C_USE_DMA == TRUE
+ {
+ bool b;
+
+ b = dmaStreamAllocate(i2cp->dmarx,
+ STM32_I2C_I2C1_IRQ_PRIORITY,
+ NULL,
+ (void *)i2cp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(i2cp->dmatx,
+ STM32_I2C_I2C1_IRQ_PRIORITY,
+ NULL,
+ (void *)i2cp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
+ i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
+ }
+#endif /* STM32_I2C_USE_DMA == TRUE */
+
+#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+ nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY);
+#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER)
+ nvicEnableVector(STM32_I2C1_EVENT_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_I2C1_ERROR_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY);
+#else
+#error "I2C1 interrupt numbers not defined"
+#endif
+ }
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2
+ if (&I2CD2 == i2cp) {
+
+ rccResetI2C2();
+ rccEnableI2C2(FALSE);
+#if STM32_I2C_USE_DMA == TRUE
+ {
+ bool b;
+
+ b = dmaStreamAllocate(i2cp->dmarx,
+ STM32_I2C_I2C2_IRQ_PRIORITY,
+ NULL,
+ (void *)i2cp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(i2cp->dmatx,
+ STM32_I2C_I2C2_IRQ_PRIORITY,
+ NULL,
+ (void *)i2cp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
+ i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
+ }
+#endif /*STM32_I2C_USE_DMA == TRUE */
+
+#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+ nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY);
+#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER)
+ nvicEnableVector(STM32_I2C2_EVENT_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY);
+ nvicEnableVector(STM32_I2C2_ERROR_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY);
+#else
+#error "I2C2 interrupt numbers not defined"
+#endif
+ }
+#endif /* STM32_I2C_USE_I2C2 */
+
+#if STM32_I2C_USE_I2C3
+ if (&I2CD3 == i2cp) {
+
+ rccResetI2C3();
+ rccEnableI2C3(FALSE);
+#if STM32_I2C_USE_DMA == TRUE
+ {
+ bool b;
+
+ b = dmaStreamAllocate(i2cp->dmarx,
+ STM32_I2C_I2C3_IRQ_PRIORITY,
+ NULL,
+ (void *)i2cp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(i2cp->dmatx,
+ STM32_I2C_I2C3_IRQ_PRIORITY,
+ NULL,
+ (void *)i2cp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
+ i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
+ }
+#endif /*STM32_I2C_USE_DMA == TRUE */
+
+#if defined(STM32_I2C3_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+ nvicEnableVector(STM32_I2C3_GLOBAL_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY);
+#elif defined(STM32_I2C3_EVENT_NUMBER) && defined(STM32_I2C3_ERROR_NUMBER)
+ nvicEnableVector(STM32_I2C3_EVENT_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY);
+ nvicEnableVector(STM32_I2C3_ERROR_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY);
+#else
+#error "I2C3 interrupt numbers not defined"
+#endif
+ }
+#endif /* STM32_I2C_USE_I2C3 */
+
+#if STM32_I2C_USE_I2C4
+ if (&I2CD4 == i2cp) {
+
+ rccResetI2C4();
+ rccEnableI2C4(FALSE);
+#if STM32_I2C_USE_DMA == TRUE
+ {
+ bool b;
+
+ b = dmaStreamAllocate(i2cp->dmarx,
+ STM32_I2C_I2C4_IRQ_PRIORITY,
+ NULL,
+ (void *)i2cp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(i2cp->dmatx,
+ STM32_I2C_I2C4_IRQ_PRIORITY,
+ NULL,
+ (void *)i2cp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C4_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
+ i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C4_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
+ }
+#endif /*STM32_I2C_USE_DMA == TRUE */
+
+#if defined(STM32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+ nvicEnableVector(STM32_I2C4_GLOBAL_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY);
+#elif defined(STM32_I2C4_EVENT_NUMBER) && defined(STM32_I2C4_ERROR_NUMBER)
+ nvicEnableVector(STM32_I2C4_EVENT_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY);
+ nvicEnableVector(STM32_I2C4_ERROR_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY);
+#else
+#error "I2C4 interrupt numbers not defined"
+#endif
+ }
+#endif /* STM32_I2C_USE_I2C4 */
+ }
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* I2C registers pointed by the DMA.*/
+ dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR);
+ dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR);
+#endif
+
+ /* Reset i2c peripheral, the TCIE bit will be handled separately.*/
+ dp->CR1 = i2cp->config->cr1 |
+#if STM32_I2C_USE_DMA == TRUE
+ I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN | /* Enable only if using DMA */
+#endif
+ I2C_CR1_ERRIE | I2C_CR1_NACKIE;
+
+ /* Setup I2C parameters.*/
+ dp->TIMINGR = i2cp->config->timingr;
+
+ /* Ready to go.*/
+ dp->CR1 |= I2C_CR1_PE;
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+
+ /* If not in stopped state then disables the I2C clock.*/
+ if (i2cp->state != I2C_STOP) {
+
+ /* I2C disable.*/
+ i2c_lld_abort_operation(i2cp);
+#if STM32_I2C_USE_DMA == TRUE
+ dmaStreamRelease(i2cp->dmatx);
+ dmaStreamRelease(i2cp->dmarx);
+#endif
+
+#if STM32_I2C_USE_I2C1
+ if (&I2CD1 == i2cp) {
+#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+ nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER);
+#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER)
+ nvicDisableVector(STM32_I2C1_EVENT_NUMBER);
+ nvicDisableVector(STM32_I2C1_ERROR_NUMBER);
+#else
+#error "I2C1 interrupt numbers not defined"
+#endif
+
+ rccDisableI2C1(FALSE);
+ }
+#endif
+
+#if STM32_I2C_USE_I2C2
+ if (&I2CD2 == i2cp) {
+#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+ nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER);
+#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER)
+ nvicDisableVector(STM32_I2C2_EVENT_NUMBER);
+ nvicDisableVector(STM32_I2C2_ERROR_NUMBER);
+#else
+#error "I2C2 interrupt numbers not defined"
+#endif
+
+ rccDisableI2C2(FALSE);
+ }
+#endif
+
+#if STM32_I2C_USE_I2C3
+ if (&I2CD3 == i2cp) {
+#if defined(STM32_I2C3_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+ nvicDisableVector(STM32_I2C3_GLOBAL_NUMBER);
+#elif defined(STM32_I2C3_EVENT_NUMBER) && defined(STM32_I2C3_ERROR_NUMBER)
+ nvicDisableVector(STM32_I2C3_EVENT_NUMBER);
+ nvicDisableVector(STM32_I2C3_ERROR_NUMBER);
+#else
+#error "I2C3 interrupt numbers not defined"
+#endif
+
+ rccDisableI2C3(FALSE);
+ }
+#endif
+
+#if STM32_I2C_USE_I2C4
+ if (&I2CD4 == i2cp) {
+#if defined(STM32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+ nvicDisableVector(STM32_I2C4_GLOBAL_NUMBER);
+#elif defined(STM32_I2C4_EVENT_NUMBER) && defined(STM32_I2C4_ERROR_NUMBER)
+ nvicDisableVector(STM32_I2C4_EVENT_NUMBER);
+ nvicDisableVector(STM32_I2C4_ERROR_NUMBER);
+#else
+#error "I2C4 interrupt numbers not defined"
+#endif
+
+ rccDisableI2C4(FALSE);
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Receives data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+ msg_t msg;
+ I2C_TypeDef *dp = i2cp->i2c;
+ systime_t start, end;
+
+ /* Resetting error flags for this transfer.*/
+ i2cp->errors = I2C_NO_ERROR;
+
+ /* Releases the lock from high level driver.*/
+ osalSysUnlock();
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* RX DMA setup.*/
+ dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
+ dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
+ dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
+#else
+ i2cp->rxptr = rxbuf;
+ i2cp->rxbytes = rxbytes;
+#endif
+
+ /* Calculating the time window for the timeout on the busy bus condition.*/
+ start = osalOsGetSystemTimeX();
+ end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT);
+
+ /* Waits until BUSY flag is reset or, alternatively, for a timeout
+ condition.*/
+ while (true) {
+ osalSysLock();
+
+ /* If the bus is not busy then the operation can continue, note, the
+ loop is exited in the locked state.*/
+ if ((dp->ISR & I2C_ISR_BUSY) == 0)
+ break;
+
+ /* If the system time went outside the allowed window then a timeout
+ condition is returned.*/
+ if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) {
+ return MSG_TIMEOUT;
+ }
+
+ osalSysUnlock();
+ }
+
+ /* Setting up the slave address.*/
+ i2c_lld_set_address(i2cp, addr);
+
+ /* Setting up the peripheral.*/
+ i2c_lld_setup_rx_transfer(i2cp);
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* Enabling RX DMA.*/
+ dmaStreamEnable(i2cp->dmarx);
+
+ /* Transfer complete interrupt enabled.*/
+ dp->CR1 |= I2C_CR1_TCIE;
+#else
+
+ /* Transfer complete and RX interrupts enabled.*/
+ dp->CR1 |= I2C_CR1_TCIE | I2C_CR1_RXIE;
+#endif
+
+ /* Starts the operation.*/
+ dp->CR2 |= I2C_CR2_START;
+
+ /* Waits for the operation completion or a timeout.*/
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+
+ /* In case of a software timeout a STOP is sent as an extreme attempt
+ to release the bus.*/
+ if (msg == MSG_TIMEOUT) {
+ dp->CR2 |= I2C_CR2_STOP;
+ }
+
+ return msg;
+}
+
+/**
+ * @brief Transmits data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[in] txbuf pointer to the transmit buffer
+ * @param[in] txbytes number of bytes to be transmitted
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+ msg_t msg;
+ I2C_TypeDef *dp = i2cp->i2c;
+ systime_t start, end;
+
+ /* Resetting error flags for this transfer.*/
+ i2cp->errors = I2C_NO_ERROR;
+
+ /* Releases the lock from high level driver.*/
+ osalSysUnlock();
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* TX DMA setup.*/
+ dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
+ dmaStreamSetMemory0(i2cp->dmatx, txbuf);
+ dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
+
+ /* RX DMA setup, note, rxbytes can be zero but we write the value anyway.*/
+ dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
+ dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
+ dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
+#else
+ i2cp->txptr = txbuf;
+ i2cp->txbytes = txbytes;
+ i2cp->rxptr = rxbuf;
+ i2cp->rxbytes = rxbytes;
+#endif
+
+ /* Calculating the time window for the timeout on the busy bus condition.*/
+ start = osalOsGetSystemTimeX();
+ end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT);
+
+ /* Waits until BUSY flag is reset or, alternatively, for a timeout
+ condition.*/
+ while (true) {
+ osalSysLock();
+
+ /* If the bus is not busy then the operation can continue, note, the
+ loop is exited in the locked state.*/
+ if ((dp->ISR & I2C_ISR_BUSY) == 0)
+ break;
+
+ /* If the system time went outside the allowed window then a timeout
+ condition is returned.*/
+ if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) {
+ return MSG_TIMEOUT;
+ }
+
+ osalSysUnlock();
+ }
+
+ /* Setting up the slave address.*/
+ i2c_lld_set_address(i2cp, addr);
+
+ /* Preparing the transfer.*/
+ i2c_lld_setup_tx_transfer(i2cp);
+
+#if STM32_I2C_USE_DMA == TRUE
+ /* Enabling TX DMA.*/
+ dmaStreamEnable(i2cp->dmatx);
+
+ /* Transfer complete interrupt enabled.*/
+ dp->CR1 |= I2C_CR1_TCIE;
+#else
+ /* Transfer complete and TX interrupts enabled.*/
+ dp->CR1 |= I2C_CR1_TCIE | I2C_CR1_TXIE;
+#endif
+
+ /* Starts the operation.*/
+ dp->CR2 |= I2C_CR2_START;
+
+ /* Waits for the operation completion or a timeout.*/
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+
+ /* In case of a software timeout a STOP is sent as an extreme attempt
+ to release the bus.*/
+ if (msg == MSG_TIMEOUT) {
+ dp->CR2 |= I2C_CR2_STOP;
+ }
+
+ return msg;
+}
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv2/i2c_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.h
similarity index 55%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv2/i2c_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.h
index 1450b7ab07..3a96a92e97 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/I2Cv2/i2c_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,15 +19,15 @@
*/
/**
- * @file STM32/I2Cv2/i2c_lld.h
+ * @file I2Cv2/hal_i2c_lld.h
* @brief STM32 I2C subsystem low level driver header.
*
* @addtogroup I2C
* @{
*/
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
+#ifndef HAL_I2C_LLD_H
+#define HAL_I2C_LLD_H
#if HAL_USE_I2C || defined(__DOXYGEN__)
@@ -77,6 +77,31 @@
#define STM32_I2C_USE_I2C2 FALSE
#endif
+/**
+ * @brief I2C3 driver enable switch.
+ * @details If set to @p TRUE the support for I2C3 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C3 FALSE
+#endif
+
+/**
+ * @brief I2C4 driver enable switch.
+ * @details If set to @p TRUE the support for I2C4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_I2C_USE_I2C4) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C4 FALSE
+#endif
+
+/**
+ * @brief I2C timeout on busy condition in milliseconds.
+ */
+#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
+#define STM32_I2C_BUSY_TIMEOUT 50
+#endif
+
/**
* @brief I2C1 interrupt priority level setting.
*/
@@ -91,6 +116,27 @@
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
#endif
+/**
+ * @brief I2C3 interrupt priority level setting.
+ */
+#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C3_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2C4 interrupt priority level setting.
+ */
+#if !defined(STM32_I2C_I2C4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C4_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief DMA use switch.
+ */
+#if !defined(STM32_I2C_USE_DMA) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_DMA TRUE
+#endif
+
/**
* @brief I2C1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
@@ -111,13 +157,33 @@
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#endif
+/**
+ * @brief I2C3 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA streams but
+ * because of the streams ordering the RX stream has always priority
+ * over the TX stream.
+ */
+#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C3_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2C4 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA streams but
+ * because of the streams ordering the RX stream has always priority
+ * over the TX stream.
+ */
+#if !defined(STM32_I2C_I2C4_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C4_DMA_PRIORITY 1
+#endif
+
/**
* @brief I2C DMA error hook.
* @note The default action for DMA errors is a system halt because DMA
* error can only happen because programming errors.
*/
#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt()
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
#endif
/** @} */
@@ -125,23 +191,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-/* Streams for the DMA peripheral.*/
-#if defined(STM32F0XX)
-#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-
-#elif defined(STM32F30X) || defined(STM32F37X)
-#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
-#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-
-#else
-#error "device unsupported by I2Cv2 driver"
-#endif
-
/** @brief error checks */
#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
#error "I2C1 not present in the selected device"
@@ -151,10 +200,85 @@
#error "I2C2 not present in the selected device"
#endif
-#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2
+#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3
+#error "I2C3 not present in the selected device"
+#endif
+
+#if STM32_I2C_USE_I2C4 && !STM32_HAS_I2C4
+#error "I2C4 not present in the selected device"
+#endif
+
+#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && !STM32_I2C_USE_I2C3 && \
+ !STM32_I2C_USE_I2C4
#error "I2C driver activated but no I2C peripheral assigned"
#endif
+#if STM32_I2C_USE_I2C1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C1"
+#endif
+
+#if STM32_I2C_USE_I2C2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C2"
+#endif
+
+#if STM32_I2C_USE_I2C3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C3"
+#endif
+
+#if STM32_I2C_USE_I2C4 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C4"
+#endif
+
+#if STM32_I2C_USE_DMA == TRUE
+#if STM32_I2C_USE_I2C1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C1"
+#endif
+
+#if STM32_I2C_USE_I2C2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C2"
+#endif
+
+#if STM32_I2C_USE_I2C3 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C3"
+#endif
+
+#if STM32_I2C_USE_I2C4 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C4_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C4"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) || \
+ !defined(STM32_I2C_I2C1_TX_DMA_STREAM))
+#error "I2C1 DMA streams not defined"
+#endif
+
+#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) || \
+ !defined(STM32_I2C_I2C2_TX_DMA_STREAM))
+#error "I2C2 DMA streams not defined"
+#endif
+
+#if STM32_I2C_USE_I2C3 && (!defined(STM32_I2C_I2C3_RX_DMA_STREAM) || \
+ !defined(STM32_I2C_I2C3_TX_DMA_STREAM))
+#error "I2C3 DMA streams not defined"
+#endif
+
+#if STM32_I2C_USE_I2C4 && (!defined(STM32_I2C_I2C4_RX_DMA_STREAM) || \
+ !defined(STM32_I2C_I2C4_TX_DMA_STREAM))
+#error "I2C4 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
#if STM32_I2C_USE_I2C1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \
STM32_I2C1_RX_DMA_MSK)
@@ -179,28 +303,52 @@
#error "invalid DMA stream associated to I2C2 TX"
#endif
+#if STM32_I2C_USE_I2C3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \
+ STM32_I2C3_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2C3 RX"
+#endif
+
+#if STM32_I2C_USE_I2C3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \
+ STM32_I2C3_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2C3 TX"
+#endif
+
+#if STM32_I2C_USE_I2C4 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C4_RX_DMA_STREAM, \
+ STM32_I2C4_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2C4 RX"
+#endif
+
+#if STM32_I2C_USE_I2C4 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C4_TX_DMA_STREAM, \
+ STM32_I2C4_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2C4 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
-
-/* Check clock range. */
+#endif /* STM32_I2C_USE_DMA == TRUE */
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
- * @brief Type representing I2C address.
+ * @brief Type representing an I2C address.
*/
typedef uint16_t i2caddr_t;
/**
- * @brief I2C Driver condition flags type.
+ * @brief Type of I2C driver condition flags.
*/
typedef uint32_t i2cflags_t;
/**
- * @brief Driver configuration structure.
+ * @brief Type of I2C driver configuration structure.
*/
typedef struct {
/**
@@ -227,9 +375,9 @@ typedef struct {
typedef struct I2CDriver I2CDriver;
/**
- * @brief Structure representing an I2C driver.
+ * @brief Structure representing an I2C driver.
*/
-struct I2CDriver{
+struct I2CDriver {
/**
* @brief Driver state.
*/
@@ -243,14 +391,7 @@ struct I2CDriver{
*/
i2cflags_t errors;
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
+ mutex_t mutex;
#endif /* I2C_USE_MUTUAL_EXCLUSION */
#if defined(I2C_DRIVER_EXT_FIELDS)
I2C_DRIVER_EXT_FIELDS
@@ -259,11 +400,8 @@ struct I2CDriver{
/**
* @brief Thread waiting for I/O completion.
*/
- Thread *thread;
- /**
- * @brief Current slave address without R/W bit.
- */
- i2caddr_t addr;
+ thread_reference_t thread;
+#if (STM32_I2C_USE_DMA == TRUE) || defined(__DOXYGEN__)
/**
* @brief RX DMA mode bit mask.
*/
@@ -280,6 +418,24 @@ struct I2CDriver{
* @brief Transmit DMA channel.
*/
const stm32_dma_stream_t *dmatx;
+#else /* STM32_I2C_USE_DMA == FALSE */
+ /**
+ * @brief Pointer to the next TX buffer location.
+ */
+ const uint8_t *txptr;
+ /**
+ * @brief Number of bytes in TX phase.
+ */
+ size_t txbytes;
+ /**
+ * @brief Pointer to the next RX buffer location.
+ */
+ uint8_t *rxptr;
+ /**
+ * @brief Number of bytes in RX phase.
+ */
+ size_t rxbytes;
+#endif /* STM32_I2C_USE_DMA == FALSE */
/**
* @brief Pointer to the I2Cx registers block.
*/
@@ -312,6 +468,14 @@ extern I2CDriver I2CD1;
extern I2CDriver I2CD2;
#endif
+#if STM32_I2C_USE_I2C3
+extern I2CDriver I2CD3;
+#endif
+
+#if STM32_I2C_USE_I2C4
+extern I2CDriver I2CD4;
+#endif
+
#endif /* !defined(__DOXYGEN__) */
#ifdef __cplusplus
@@ -333,6 +497,6 @@ extern "C" {
#endif /* HAL_USE_I2C */
-#endif /* _I2C_LLD_H_ */
+#endif /* HAL_I2C_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/driver.mk
new file mode 100644
index 0000000000..f0a8938e47
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/mac_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c
similarity index 83%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/mac_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c
index a237ca3f0c..6d460f5828 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/mac_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
*/
/**
- * @file STM32/mac_lld.c
+ * @file MACv1/hal_mac_lld.c
* @brief STM32 low level MAC driver code.
*
* @addtogroup MAC
@@ -24,18 +24,35 @@
#include
-#include "ch.h"
#include "hal.h"
-#include "mii.h"
#if HAL_USE_MAC || defined(__DOXYGEN__)
+#include "hal_mii.h"
+
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define BUFFER_SIZE ((((STM32_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
+/* Fixing inconsistencies in ST headers.*/
+#if !defined(ETH_MACMIIAR_CR_Div102) && defined(ETH_MACMIIAR_CR_DIV102)
+#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_DIV102
+#endif
+#if !defined(ETH_MACMIIAR_CR_Div62) && defined(ETH_MACMIIAR_CR_DIV62)
+#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_DIV62
+#endif
+#if !defined(ETH_MACMIIAR_CR_Div42) && defined(ETH_MACMIIAR_CR_DIV42)
+#define ETH_MACMIIAR_CR_Div42 ETH_MACMIIAR_CR_DIV42
+#endif
+#if !defined(ETH_MACMIIAR_CR_Div26) && defined(ETH_MACMIIAR_CR_DIV26)
+#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_DIV26
+#endif
+#if !defined(ETH_MACMIIAR_CR_Div16) && defined(ETH_MACMIIAR_CR_DIV16)
+#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_DIV16
+#endif
+
/* MII divider optimal value.*/
#if (STM32_HCLK >= 150000000)
#define MACMIIDR_CR ETH_MACMIIAR_CR_Div102
@@ -67,11 +84,11 @@ MACDriver ETHD1;
static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
0x37, 0x01, 0x10};
-static stm32_eth_rx_descriptor_t rd[STM32_MAC_RECEIVE_BUFFERS];
-static stm32_eth_tx_descriptor_t td[STM32_MAC_TRANSMIT_BUFFERS];
+static stm32_eth_rx_descriptor_t __eth_rd[STM32_MAC_RECEIVE_BUFFERS];
+static stm32_eth_tx_descriptor_t __eth_td[STM32_MAC_TRANSMIT_BUFFERS];
-static uint32_t rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
-static uint32_t tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
+static uint32_t __eth_rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
+static uint32_t __eth_tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
/*===========================================================================*/
/* Driver local functions. */
@@ -123,23 +140,23 @@ static void mii_find_phy(MACDriver *macp) {
uint32_t i;
#if STM32_MAC_PHY_TIMEOUT > 0
- halrtcnt_t start = halGetCounterValue();
- halrtcnt_t timeout = start + MS2RTT(STM32_MAC_PHY_TIMEOUT);
- while (halIsCounterWithin(start, timeout)) {
+ unsigned n = STM32_MAC_PHY_TIMEOUT;
+ do {
#endif
- for (i = 0; i < 31; i++) {
- macp->phyaddr = i << 11;
- ETH->MACMIIDR = (i << 6) | MACMIIDR_CR;
- if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
- ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
+ for (i = 0U; i < 31U; i++) {
+ macp->phyaddr = i << 11U;
+ ETH->MACMIIDR = (i << 6U) | MACMIIDR_CR;
+ if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16U)) &&
+ ((mii_read(macp, MII_PHYSID2) & 0xFFF0U) == (BOARD_PHY_ID & 0xFFF0U))) {
return;
}
}
#if STM32_MAC_PHY_TIMEOUT > 0
- }
+ n--;
+ } while (n > 0U);
#endif
/* Wrong or defective board.*/
- chSysHalt();
+ osalSysHalt("MAC failure");
}
#endif
@@ -173,32 +190,32 @@ static void mac_lld_set_address(const uint8_t *p) {
/* Driver interrupt handlers. */
/*===========================================================================*/
-CH_IRQ_HANDLER(ETH_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_ETH_HANDLER) {
uint32_t dmasr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
dmasr = ETH->DMASR;
ETH->DMASR = dmasr; /* Clear status bits.*/
if (dmasr & ETH_DMASR_RS) {
/* Data Received.*/
- chSysLockFromIsr();
- chSemResetI(ÐD1.rdsem, 0);
+ osalSysLockFromISR();
+ osalThreadDequeueAllI(ÐD1.rdqueue, MSG_RESET);
#if MAC_USE_EVENTS
- chEvtBroadcastI(ÐD1.rdevent);
+ osalEventBroadcastFlagsI(ÐD1.rdevent, 0);
#endif
- chSysUnlockFromIsr();
+ osalSysUnlockFromISR();
}
if (dmasr & ETH_DMASR_TS) {
/* Data Transmitted.*/
- chSysLockFromIsr();
- chSemResetI(ÐD1.tdsem, 0);
- chSysUnlockFromIsr();
+ osalSysLockFromISR();
+ osalThreadDequeueAllI(ÐD1.tdqueue, MSG_RESET);
+ osalSysUnlockFromISR();
}
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
@@ -214,19 +231,19 @@ void mac_lld_init(void) {
unsigned i;
macObjectInit(ÐD1);
- ETHD1.link_up = FALSE;
+ ETHD1.link_up = false;
/* Descriptor tables are initialized in chained mode, note that the first
word is not initialized here but in mac_lld_start().*/
for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) {
- rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE;
- rd[i].rdes2 = (uint32_t)rb[i];
- rd[i].rdes3 = (uint32_t)&rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS];
+ __eth_rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE;
+ __eth_rd[i].rdes2 = (uint32_t)__eth_rb[i];
+ __eth_rd[i].rdes3 = (uint32_t)&__eth_rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS];
}
for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) {
- td[i].tdes1 = 0;
- td[i].tdes2 = (uint32_t)tb[i];
- td[i].tdes3 = (uint32_t)&td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS];
+ __eth_td[i].tdes1 = 0;
+ __eth_td[i].tdes2 = (uint32_t)__eth_tb[i];
+ __eth_td[i].tdes3 = (uint32_t)&__eth_td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS];
}
/* Selection of the RMII or MII mode based on info exported by board.h.*/
@@ -236,7 +253,7 @@ void mac_lld_init(void) {
#else
AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL;
#endif
-#elif defined(STM32F2XX) || defined(STM32F4XX)
+#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)
#if defined(BOARD_PHY_RMII)
SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
#else
@@ -250,7 +267,7 @@ void mac_lld_init(void) {
rccResetETH();
/* MAC clocks temporary activation.*/
- rccEnableETH(FALSE);
+ rccEnableETH(false);
/* PHY address setup.*/
#if defined(BOARD_PHY_ADDRESS)
@@ -266,7 +283,7 @@ void mac_lld_init(void) {
/* PHY soft reset procedure.*/
mii_write(ÐD1, MII_BMCR, BMCR_RESET);
#if defined(BOARD_PHY_RESET_DELAY)
- halPolledDelay(BOARD_PHY_RESET_DELAY);
+ osalSysPolledDelayX(BOARD_PHY_RESET_DELAY);
#endif
while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET)
;
@@ -278,7 +295,7 @@ void mac_lld_init(void) {
#endif
/* MAC clocks stopped again.*/
- rccDisableETH(FALSE);
+ rccDisableETH(false);
}
/**
@@ -293,14 +310,14 @@ void mac_lld_start(MACDriver *macp) {
/* Resets the state of all descriptors.*/
for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++)
- rd[i].rdes0 = STM32_RDES0_OWN;
- macp->rxptr = (stm32_eth_rx_descriptor_t *)rd;
+ __eth_rd[i].rdes0 = STM32_RDES0_OWN;
+ macp->rxptr = (stm32_eth_rx_descriptor_t *)__eth_rd;
for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++)
- td[i].tdes0 = STM32_TDES0_TCH;
- macp->txptr = (stm32_eth_tx_descriptor_t *)td;
+ __eth_td[i].tdes0 = STM32_TDES0_TCH;
+ macp->txptr = (stm32_eth_tx_descriptor_t *)__eth_td;
/* MAC clocks activation and commanded reset procedure.*/
- rccEnableETH(FALSE);
+ rccEnableETH(false);
#if defined(STM32_MAC_DMABMR_SR)
ETH->DMABMR |= ETH_DMABMR_SR;
while(ETH->DMABMR & ETH_DMABMR_SR)
@@ -308,8 +325,7 @@ void mac_lld_start(MACDriver *macp) {
#endif
/* ISR vector enabled.*/
- nvicEnableVector(ETH_IRQn,
- CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY));
+ nvicEnableVector(STM32_ETH_NUMBER, STM32_MAC_ETH1_IRQ_PRIORITY);
#if STM32_MAC_ETH1_CHANGE_PHY_STATE
/* PHY in power up mode.*/
@@ -338,8 +354,8 @@ void mac_lld_start(MACDriver *macp) {
/* DMA configuration:
Descriptor chains pointers.*/
- ETH->DMARDLAR = (uint32_t)rd;
- ETH->DMATDLAR = (uint32_t)td;
+ ETH->DMARDLAR = (uint32_t)__eth_rd;
+ ETH->DMATDLAR = (uint32_t)__eth_td;
/* Enabling required interrupt sources.*/
ETH->DMASR = ETH->DMASR;
@@ -380,10 +396,10 @@ void mac_lld_stop(MACDriver *macp) {
ETH->DMASR = ETH->DMASR;
/* MAC clocks stopped.*/
- rccDisableETH(FALSE);
+ rccDisableETH(false);
/* ISR vector disabled.*/
- nvicDisableVector(ETH_IRQn);
+ nvicDisableVector(STM32_ETH_NUMBER);
}
}
@@ -395,8 +411,8 @@ void mac_lld_stop(MACDriver *macp) {
* @param[in] macp pointer to the @p MACDriver object
* @param[out] tdp pointer to a @p MACTransmitDescriptor structure
* @return The operation status.
- * @retval RDY_OK the descriptor has been obtained.
- * @retval RDY_TIMEOUT descriptor not available.
+ * @retval MSG_OK the descriptor has been obtained.
+ * @retval MSG_TIMEOUT descriptor not available.
*
* @notapi
*/
@@ -405,9 +421,9 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
stm32_eth_tx_descriptor_t *tdes;
if (!macp->link_up)
- return RDY_TIMEOUT;
+ return MSG_TIMEOUT;
- chSysLock();
+ osalSysLock();
/* Get Current TX descriptor.*/
tdes = macp->txptr;
@@ -415,8 +431,8 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
/* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
another thread.*/
if (tdes->tdes0 & (STM32_TDES0_OWN | STM32_TDES0_LOCKED)) {
- chSysUnlock();
- return RDY_TIMEOUT;
+ osalSysUnlock();
+ return MSG_TIMEOUT;
}
/* Marks the current descriptor as locked using a reserved bit.*/
@@ -425,14 +441,14 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
/* Next TX descriptor to use.*/
macp->txptr = (stm32_eth_tx_descriptor_t *)tdes->tdes3;
- chSysUnlock();
+ osalSysUnlock();
/* Set the buffer size and configuration.*/
tdp->offset = 0;
tdp->size = STM32_MAC_BUFFERS_SIZE;
tdp->physdesc = tdes;
- return RDY_OK;
+ return MSG_OK;
}
/**
@@ -445,11 +461,10 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
*/
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
- chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
- "mac_lld_release_transmit_descriptor(), #1",
+ osalDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
"attempt to release descriptor already owned by DMA");
- chSysLock();
+ osalSysLock();
/* Unlocks the descriptor and returns it to the DMA engine.*/
tdp->physdesc->tdes1 = tdp->offset;
@@ -457,13 +472,16 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
STM32_TDES0_TCH | STM32_TDES0_OWN;
+ /* Wait for the write to tdes0 to go through before resuming the DMA.*/
+ __DSB();
+
/* If the DMA engine is stalled then a restart request is issued.*/
if ((ETH->DMASR & ETH_DMASR_TPS) == ETH_DMASR_TPS_Suspended) {
ETH->DMASR = ETH_DMASR_TBUS;
ETH->DMATPDR = ETH_DMASR_TBUS; /* Any value is OK.*/
}
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -472,8 +490,8 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
* @param[in] macp pointer to the @p MACDriver object
* @param[out] rdp pointer to a @p MACReceiveDescriptor structure
* @return The operation status.
- * @retval RDY_OK the descriptor has been obtained.
- * @retval RDY_TIMEOUT descriptor not available.
+ * @retval MSG_OK the descriptor has been obtained.
+ * @retval MSG_TIMEOUT descriptor not available.
*
* @notapi
*/
@@ -481,7 +499,7 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp) {
stm32_eth_rx_descriptor_t *rdes;
- chSysLock();
+ osalSysLock();
/* Get Current RX descriptor.*/
rdes = macp->rxptr;
@@ -501,8 +519,8 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
rdp->physdesc = rdes;
macp->rxptr = (stm32_eth_rx_descriptor_t *)rdes->rdes3;
- chSysUnlock();
- return RDY_OK;
+ osalSysUnlock();
+ return MSG_OK;
}
/* Invalid frame found, purging.*/
rdes->rdes0 = STM32_RDES0_OWN;
@@ -512,8 +530,8 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
/* Next descriptor to check.*/
macp->rxptr = rdes;
- chSysUnlock();
- return RDY_TIMEOUT;
+ osalSysUnlock();
+ return MSG_TIMEOUT;
}
/**
@@ -527,22 +545,24 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
*/
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
- chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
- "mac_lld_release_receive_descriptor(), #1",
+ osalDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
"attempt to release descriptor already owned by DMA");
- chSysLock();
+ osalSysLock();
/* Give buffer back to the Ethernet DMA.*/
rdp->physdesc->rdes0 = STM32_RDES0_OWN;
+ /* Wait for the write to rdes0 to go through before resuming the DMA.*/
+ __DSB();
+
/* If the DMA engine is stalled then a restart request is issued.*/
if ((ETH->DMASR & ETH_DMASR_RPS) == ETH_DMASR_RPS_Suspended) {
ETH->DMASR = ETH_DMASR_RBUS;
ETH->DMARPDR = ETH_DMASR_RBUS; /* Any value is OK.*/
}
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -550,12 +570,12 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
*
* @param[in] macp pointer to the @p MACDriver object
* @return The link status.
- * @retval TRUE if the link is active.
- * @retval FALSE if the link is down.
+ * @retval true if the link is active.
+ * @retval false if the link is down.
*
* @notapi
*/
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
+bool mac_lld_poll_link_status(MACDriver *macp) {
uint32_t maccr, bmsr, bmcr;
maccr = ETH->MACCR;
@@ -572,7 +592,7 @@ bool_t mac_lld_poll_link_status(MACDriver *macp) {
/* Auto-negotiation must be finished without faults and link established.*/
if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
(BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
- return macp->link_up = FALSE;
+ return macp->link_up = false;
/* Auto-negotiation enabled, checks the LPA register.*/
lpa = mii_read(macp, MII_LPA);
@@ -592,7 +612,7 @@ bool_t mac_lld_poll_link_status(MACDriver *macp) {
else {
/* Link must be established.*/
if (!(bmsr & BMSR_LSTATUS))
- return macp->link_up = FALSE;
+ return macp->link_up = false;
/* Check on link speed.*/
if (bmcr & BMCR_SPEED100)
@@ -611,7 +631,7 @@ bool_t mac_lld_poll_link_status(MACDriver *macp) {
ETH->MACCR = maccr;
/* Returns the link status.*/
- return macp->link_up = TRUE;
+ return macp->link_up = true;
}
/**
@@ -632,8 +652,7 @@ size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size) {
- chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
- "mac_lld_write_transmit_descriptor(), #1",
+ osalDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
"attempt to write descriptor already owned by DMA");
if (size > tdp->size - tdp->offset)
@@ -663,8 +682,7 @@ size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
uint8_t *buf,
size_t size) {
- chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
- "mac_lld_read_receive_descriptor(), #1",
+ osalDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
"attempt to read descriptor already owned by DMA");
if (size > rdp->size - rdp->offset)
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/mac_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.h
similarity index 92%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/mac_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.h
index 1d2c50b00c..b411a4049d 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/mac_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/mac_lld.h
+ * @file MACv1/hal_mac_lld.h
* @brief STM32 low level MAC driver header.
*
* @addtogroup MAC
* @{
*/
-#ifndef _MAC_LLD_H_
-#define _MAC_LLD_H_
+#ifndef HAL_MAC_LLD_H
+#define HAL_MAC_LLD_H
#if HAL_USE_MAC || defined(__DOXYGEN__)
@@ -144,12 +144,11 @@
/**
* @brief PHY detection timeout.
- * @details Timeout, in milliseconds, for PHY address detection, if a PHY
- * is not detected within the timeout then the driver halts during
- * initialization. This setting applies only if the PHY address is
- * not explicitly set in the board header file using
- * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
- * single search path is performed.
+ * @details Timeout for PHY address detection, the scan for a PHY is performed
+ * the specified number of times before invoking the failure handler.
+ * This setting applies only if the PHY address is not explicitly
+ * set in the board header file using @p BOARD_PHY_ADDRESS. A zero
+ * value disables the timeout and a single search is performed.
*/
#if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
#define STM32_MAC_PHY_TIMEOUT 100
@@ -191,10 +190,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if (STM32_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
-#error "STM32_MAC_PHY_TIMEOUT requires the realtime counter service"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -245,22 +240,22 @@ struct MACDriver {
/**
* @brief Transmit semaphore.
*/
- Semaphore tdsem;
+ threads_queue_t tdqueue;
/**
* @brief Receive semaphore.
*/
- Semaphore rdsem;
+ threads_queue_t rdqueue;
#if MAC_USE_EVENTS || defined(__DOXYGEN__)
/**
* @brief Receive event.
*/
- EventSource rdevent;
+ event_source_t rdevent;
#endif
/* End of the mandatory fields.*/
/**
* @brief Link status flag.
*/
- bool_t link_up;
+ bool link_up;
/**
* @brief PHY address (pre shifted).
*/
@@ -339,7 +334,7 @@ extern "C" {
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp);
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
- bool_t mac_lld_poll_link_status(MACDriver *macp);
+ bool mac_lld_poll_link_status(MACDriver *macp);
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size);
@@ -359,6 +354,6 @@ extern "C" {
#endif /* HAL_USE_MAC */
-#endif /* _MAC_LLD_H_ */
+#endif /* HAL_MAC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/driver.mk
new file mode 100644
index 0000000000..16250123ba
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/usb_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
similarity index 65%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/usb_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
index e6dfa8f88c..9a7bcc0d7d 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/usb_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
*/
/**
- * @file STM32/OTGv1/usb_lld.c
+ * @file OTGv1/hal_usb_lld.c
* @brief STM32 USB subsystem low level driver source.
*
* @addtogroup USB
@@ -24,7 +24,6 @@
#include
-#include "ch.h"
#include "hal.h"
#if HAL_USE_USB || defined(__DOXYGEN__)
@@ -33,11 +32,30 @@
/* Driver local definitions. */
/*===========================================================================*/
-#define TRDT_VALUE 5
+#define TRDT_VALUE_FS 5
+#define TRDT_VALUE_HS 9
#define EP0_MAX_INSIZE 64
#define EP0_MAX_OUTSIZE 64
+#if STM32_OTG_STEPPING == 1
+#if defined(BOARD_OTG_NOVBUSSENS)
+#define GCCFG_INIT_VALUE (GCCFG_NOVBUSSENS | GCCFG_VBUSASEN | \
+ GCCFG_VBUSBSEN | GCCFG_PWRDWN)
+#else
+#define GCCFG_INIT_VALUE (GCCFG_VBUSASEN | GCCFG_VBUSBSEN | \
+ GCCFG_PWRDWN)
+#endif
+
+#elif STM32_OTG_STEPPING == 2
+#if defined(BOARD_OTG_NOVBUSSENS)
+#define GCCFG_INIT_VALUE GCCFG_PWRDWN
+#else
+#define GCCFG_INIT_VALUE (GCCFG_VBDEN | GCCFG_PWRDWN)
+#endif
+
+#endif
+
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -97,7 +115,7 @@ static const USBEndpointConfig ep0config = {
static const stm32_otg_params_t fsparams = {
STM32_USB_OTG1_RX_FIFO_SIZE / 4,
STM32_OTG1_FIFO_MEM_SIZE,
- STM32_OTG1_ENDOPOINTS_NUMBER
+ STM32_OTG1_ENDPOINTS
};
#endif
@@ -105,7 +123,7 @@ static const stm32_otg_params_t fsparams = {
static const stm32_otg_params_t hsparams = {
STM32_USB_OTG2_RX_FIFO_SIZE / 4,
STM32_OTG2_FIFO_MEM_SIZE,
- STM32_OTG2_ENDOPOINTS_NUMBER
+ STM32_OTG2_ENDPOINTS
};
#endif
@@ -113,32 +131,17 @@ static const stm32_otg_params_t hsparams = {
/* Driver local functions. */
/*===========================================================================*/
-/**
- * @brief Wakes up the pump thread.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void usb_lld_wakeup_pump(USBDriver *usbp) {
-
- if (usbp->thd_wait != NULL) {
- chThdResumeI(usbp->thd_wait);
- usbp->thd_wait = NULL;
- }
-}
-
static void otg_core_reset(USBDriver *usbp) {
stm32_otg_t *otgp = usbp->otg;
- halPolledDelay(32);
+ osalSysPolledDelayX(32);
/* Core reset and delay of at least 3 PHY cycles.*/
otgp->GRSTCTL = GRSTCTL_CSRST;
while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
;
- halPolledDelay(12);
+ osalSysPolledDelayX(18);
/* Wait AHB idle condition.*/
while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)
@@ -150,32 +153,11 @@ static void otg_disable_ep(USBDriver *usbp) {
unsigned i;
for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
- /* Disable only if enabled because this sentence in the manual:
- "The application must set this bit only if Endpoint Enable is
- already set for this endpoint".*/
- if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0) {
- otgp->ie[i].DIEPCTL = DIEPCTL_EPDIS;
- /* Wait for endpoint disable.*/
- while (!(otgp->ie[i].DIEPINT & DIEPINT_EPDISD))
- ;
- }
- else
- otgp->ie[i].DIEPCTL = 0;
+ otgp->ie[i].DIEPCTL = 0;
otgp->ie[i].DIEPTSIZ = 0;
otgp->ie[i].DIEPINT = 0xFFFFFFFF;
- /* Disable only if enabled because this sentence in the manual:
- "The application must set this bit only if Endpoint Enable is
- already set for this endpoint".
- Note that the attempt to disable the OUT EP0 is ignored by the
- hardware but the code is simpler this way.*/
- if ((otgp->oe[i].DOEPCTL & DOEPCTL_EPENA) != 0) {
- otgp->oe[i].DOEPCTL = DOEPCTL_EPDIS;
- /* Wait for endpoint disable.*/
- while (!(otgp->oe[i].DOEPINT & DOEPINT_OTEPDIS))
- ;
- }
- else
- otgp->oe[i].DOEPCTL = 0;
+
+ otgp->oe[i].DOEPCTL = 0;
otgp->oe[i].DOEPTSIZ = 0;
otgp->oe[i].DOEPINT = 0xFFFFFFFF;
}
@@ -189,7 +171,7 @@ static void otg_rxfifo_flush(USBDriver *usbp) {
while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0)
;
/* Wait for 3 PHY Clocks.*/
- halPolledDelay(12);
+ osalSysPolledDelayX(18);
}
static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) {
@@ -199,7 +181,7 @@ static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) {
while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
;
/* Wait for 3 PHY Clocks.*/
- halPolledDelay(12);
+ osalSysPolledDelayX(18);
}
/**
@@ -227,35 +209,11 @@ static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) {
next = usbp->pmnext;
usbp->pmnext += size;
- chDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size,
- "otg_fifo_alloc(), #1", "OTG FIFO memory overflow");
+ osalDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size,
+ "OTG FIFO memory overflow");
return next;
}
-/**
- * @brief Pushes a series of words into a FIFO.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] buf pointer to the words buffer, not necessarily word
- * aligned
- * @param[in] n number of words to push
- *
- * @return A pointer after the last word pushed.
- *
- * @notapi
- */
-static uint8_t *otg_do_push(volatile uint32_t *fifop, uint8_t *buf, size_t n) {
-
- while (n > 0) {
- /* Note, this line relies on the Cortex-M3/M4 ability to perform
- unaligned word accesses and on the LSB-first memory organization.*/
- *fifop = *((PACKED_VAR uint32_t *)buf);
- buf += 4;
- n--;
- }
- return buf;
-}
-
/**
* @brief Writes to a TX FIFO.
*
@@ -269,90 +227,16 @@ static void otg_fifo_write_from_buffer(volatile uint32_t *fifop,
const uint8_t *buf,
size_t n) {
- otg_do_push(fifop, (uint8_t *)buf, (n + 3) / 4);
-}
+ osalDbgAssert(n > 0, "is zero");
-/**
- * @brief Writes to a TX FIFO fetching data from a queue.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] oqp pointer to an @p OutputQueue object
- * @param[in] n maximum number of bytes to copy
- *
- * @notapi
- */
-static void otg_fifo_write_from_queue(volatile uint32_t *fifop,
- OutputQueue *oqp,
- size_t n) {
- size_t ntogo;
-
- ntogo = n;
- while (ntogo > 0) {
- uint32_t w, i;
- size_t nw = ntogo / 4;
-
- if (nw > 0) {
- size_t streak;
- uint32_t nw2end = (oqp->q_top - oqp->q_rdptr) / 4;
-
- ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4;
- oqp->q_rdptr = otg_do_push(fifop, oqp->q_rdptr, streak);
- if (oqp->q_rdptr >= oqp->q_top) {
- oqp->q_rdptr = oqp->q_buffer;
- continue;
- }
- }
-
- /* If this condition is not satisfied then there is a word lying across
- queue circular buffer boundary or there are some remaining bytes.*/
- if (ntogo <= 0)
+ while (true) {
+ *fifop = *((uint32_t *)buf);
+ if (n <= 4) {
break;
-
- /* One byte at time.*/
- w = 0;
- i = 0;
- while ((ntogo > 0) && (i < 4)) {
- w |= (uint32_t)*oqp->q_rdptr++ << (i * 8);
- if (oqp->q_rdptr >= oqp->q_top)
- oqp->q_rdptr = oqp->q_buffer;
- ntogo--;
- i++;
}
- *fifop = w;
- }
-
- /* Updating queue.*/
- chSysLock();
- oqp->q_counter += n;
- while (notempty(&oqp->q_waiting))
- chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
- chSchRescheduleS();
- chSysUnlock();
-}
-
-/**
- * @brief Pops a series of words from a FIFO.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] buf pointer to the words buffer, not necessarily word
- * aligned
- * @param[in] n number of words to push
- *
- * @return A pointer after the last word pushed.
- *
- * @notapi
- */
-static uint8_t *otg_do_pop(volatile uint32_t *fifop, uint8_t *buf, size_t n) {
-
- while (n > 0) {
- uint32_t w = *fifop;
- /* Note, this line relies on the Cortex-M3/M4 ability to perform
- unaligned word accesses and on the LSB-first memory organization.*/
- *((PACKED_VAR uint32_t *)buf) = w;
+ n -= 4;
buf += 4;
- n--;
}
- return buf;
}
/**
@@ -369,77 +253,19 @@ static void otg_fifo_read_to_buffer(volatile uint32_t *fifop,
uint8_t *buf,
size_t n,
size_t max) {
+ uint32_t w = 0;
+ size_t i = 0;
- n = (n + 3) / 4;
- max = (max + 3) / 4;
- while (n) {
- uint32_t w = *fifop;
- if (max) {
- /* Note, this line relies on the Cortex-M3/M4 ability to perform
- unaligned word accesses and on the LSB-first memory organization.*/
- *((PACKED_VAR uint32_t *)buf) = w;
- buf += 4;
- max--;
+ while (i < n) {
+ if ((i & 3) == 0){
+ w = *fifop;
}
- n--;
- }
-}
-
-/**
- * @brief Reads a packet from the RXFIFO.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] iqp pointer to an @p InputQueue object
- * @param[in] n number of bytes to pull from the FIFO
- *
- * @notapi
- */
-static void otg_fifo_read_to_queue(volatile uint32_t *fifop,
- InputQueue *iqp,
- size_t n) {
- size_t ntogo;
-
- ntogo = n;
- while (ntogo > 0) {
- uint32_t w, i;
- size_t nw = ntogo / 4;
-
- if (nw > 0) {
- size_t streak;
- uint32_t nw2end = (iqp->q_wrptr - iqp->q_wrptr) / 4;
-
- ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4;
- iqp->q_wrptr = otg_do_pop(fifop, iqp->q_wrptr, streak);
- if (iqp->q_wrptr >= iqp->q_top) {
- iqp->q_wrptr = iqp->q_buffer;
- continue;
- }
- }
-
- /* If this condition is not satisfied then there is a word lying across
- queue circular buffer boundary or there are some remaining bytes.*/
- if (ntogo <= 0)
- break;
-
- /* One byte at time.*/
- w = *fifop;
- i = 0;
- while ((ntogo > 0) && (i < 4)) {
- *iqp->q_wrptr++ = (uint8_t)(w >> (i * 8));
- if (iqp->q_wrptr >= iqp->q_top)
- iqp->q_wrptr = iqp->q_buffer;
- ntogo--;
- i++;
+ if (i < max) {
+ *buf++ = (uint8_t)w;
+ w >>= 8;
}
+ i++;
}
-
- /* Updating queue.*/
- chSysLock();
- iqp->q_counter += n;
- while (notempty(&iqp->q_waiting))
- chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
- chSchRescheduleS();
- chSysUnlock();
}
/**
@@ -452,39 +278,35 @@ static void otg_fifo_read_to_queue(volatile uint32_t *fifop,
static void otg_rxfifo_handler(USBDriver *usbp) {
uint32_t sts, cnt, ep;
+ /* Popping the event word out of the RX FIFO.*/
sts = usbp->otg->GRXSTSP;
+
+ /* Event details.*/
+ cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
+ ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
+
switch (sts & GRXSTSP_PKTSTS_MASK) {
- case GRXSTSP_SETUP_COMP:
- break;
case GRXSTSP_SETUP_DATA:
- cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
- ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf,
cnt, 8);
break;
+ case GRXSTSP_SETUP_COMP:
+ break;
case GRXSTSP_OUT_DATA:
- cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
- ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
- if (usbp->epc[ep]->out_state->rxqueued) {
- /* Queue associated.*/
- otg_fifo_read_to_queue(usbp->otg->FIFO[0],
- usbp->epc[ep]->out_state->mode.queue.rxqueue,
- cnt);
- }
- else {
- otg_fifo_read_to_buffer(usbp->otg->FIFO[0],
- usbp->epc[ep]->out_state->mode.linear.rxbuf,
- cnt,
- usbp->epc[ep]->out_state->rxsize -
- usbp->epc[ep]->out_state->rxcnt);
- usbp->epc[ep]->out_state->mode.linear.rxbuf += cnt;
- }
+ otg_fifo_read_to_buffer(usbp->otg->FIFO[0],
+ usbp->epc[ep]->out_state->rxbuf,
+ cnt,
+ usbp->epc[ep]->out_state->rxsize -
+ usbp->epc[ep]->out_state->rxcnt);
+ usbp->epc[ep]->out_state->rxbuf += cnt;
usbp->epc[ep]->out_state->rxcnt += cnt;
break;
- case GRXSTSP_OUT_GLOBAL_NAK:
case GRXSTSP_OUT_COMP:
+ break;
+ case GRXSTSP_OUT_GLOBAL_NAK:
+ break;
default:
- ;
+ break;
}
}
@@ -496,15 +318,15 @@ static void otg_rxfifo_handler(USBDriver *usbp) {
*
* @notapi
*/
-static bool_t otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
+static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
/* The TXFIFO is filled until there is space and data to be transmitted.*/
- while (TRUE) {
+ while (true) {
uint32_t n;
/* Transaction end condition.*/
if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize)
- return TRUE;
+ return true;
/* Number of bytes remaining in current transaction.*/
n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt;
@@ -514,30 +336,20 @@ static bool_t otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
/* Checks if in the TXFIFO there is enough space to accommodate the
next packet.*/
if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n)
- return FALSE;
+ return false;
#if STM32_USB_OTGFIFO_FILL_BASEPRI
- __set_BASEPRI(CORTEX_PRIORITY_MASK(STM32_USB_OTGFIFO_FILL_BASEPRI));
+ __set_BASEPRI(CORTEX_PRIO_MASK(STM32_USB_OTGFIFO_FILL_BASEPRI));
#endif
- /* Handles the two cases: linear buffer or queue.*/
- if (usbp->epc[ep]->in_state->txqueued) {
- /* Queue associated.*/
- otg_fifo_write_from_queue(usbp->otg->FIFO[ep],
- usbp->epc[ep]->in_state->mode.queue.txqueue,
- n);
- }
- else {
- /* Linear buffer associated.*/
- otg_fifo_write_from_buffer(usbp->otg->FIFO[ep],
- usbp->epc[ep]->in_state->mode.linear.txbuf,
- n);
- usbp->epc[ep]->in_state->mode.linear.txbuf += n;
- }
- usbp->epc[ep]->in_state->txcnt += n;
- }
+ otg_fifo_write_from_buffer(usbp->otg->FIFO[ep],
+ usbp->epc[ep]->in_state->txbuf,
+ n);
+ usbp->epc[ep]->in_state->txbuf += n;
#if STM32_USB_OTGFIFO_FILL_BASEPRI
__set_BASEPRI(0);
#endif
+ usbp->epc[ep]->in_state->txcnt += n;
+ }
}
/**
@@ -567,10 +379,9 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
cover the remaining.*/
isp->txsize = isp->totsize - isp->txsize;
isp->txcnt = 0;
- usb_lld_prepare_transmit(usbp, ep);
- chSysLockFromIsr();
+ osalSysLockFromISR();
usb_lld_start_in(usbp, ep);
- chSysUnlockFromIsr();
+ osalSysUnlockFromISR();
}
else {
/* End on IN transfer.*/
@@ -580,11 +391,11 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
if ((epint & DIEPINT_TXFE) &&
(otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) {
/* The thread is made ready, it will be scheduled on ISR exit.*/
- chSysLockFromIsr();
+ osalSysLockFromISR();
usbp->txpending |= (1 << ep);
otgp->DIEPEMPMSK &= ~(1 << ep);
- usb_lld_wakeup_pump(usbp);
- chSysUnlockFromIsr();
+ osalThreadResumeI(&usbp->wait, MSG_OK);
+ osalSysUnlockFromISR();
}
}
@@ -607,25 +418,102 @@ static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
/* Setup packets handling, setup packets are handled using a
specific callback.*/
_usb_isr_invoke_setup_cb(usbp, ep);
-
}
+
if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) {
- /* Receive transfer complete.*/
- USBOutEndpointState *osp = usbp->epc[ep]->out_state;
+ USBOutEndpointState *osp;
+
+ /* OUT state structure pointer for this endpoint.*/
+ osp = usbp->epc[ep]->out_state;
+
+ /* EP0 requires special handling.*/
+ if (ep == 0) {
+
+#if defined(STM32_OTG_SEQUENCE_WORKAROUND)
+ /* If an OUT transaction end interrupt is processed while the state
+ machine is not in an OUT state then it is ignored, this is caused
+ on some devices (L4) apparently injecting spurious data complete
+ words in the RX FIFO.*/
+ if ((usbp->ep0state & USB_OUT_STATE) == 0)
+ return;
+#endif
- if (osp->rxsize < osp->totsize) {
/* In case the transaction covered only part of the total transfer
then another transaction is immediately started in order to
cover the remaining.*/
- osp->rxsize = osp->totsize - osp->rxsize;
- osp->rxcnt = 0;
- usb_lld_prepare_receive(usbp, ep);
- chSysLockFromIsr();
- usb_lld_start_out(usbp, ep);
- chSysUnlockFromIsr();
+ if (((osp->rxcnt % usbp->epc[ep]->out_maxsize) == 0) &&
+ (osp->rxsize < osp->totsize)) {
+ osp->rxsize = osp->totsize - osp->rxsize;
+ osp->rxcnt = 0;
+ osalSysLockFromISR();
+ usb_lld_start_out(usbp, ep);
+ osalSysUnlockFromISR();
+ return;
+ }
}
- else {
- /* End on OUT transfer.*/
+
+ /* End on OUT transfer.*/
+ _usb_isr_invoke_out_cb(usbp, ep);
+ }
+}
+
+/**
+ * @brief Isochronous IN transfer failed handler.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+static void otg_isoc_in_failed_handler(USBDriver *usbp) {
+ usbep_t ep;
+ stm32_otg_t *otgp = usbp->otg;
+
+ for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
+ if (((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTYP_MASK) == DIEPCTL_EPTYP_ISO) &&
+ ((otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA) != 0)) {
+ /* Endpoint enabled -> ISOC IN transfer failed */
+ /* Disable endpoint */
+ otgp->ie[ep].DIEPCTL |= (DIEPCTL_EPDIS | DIEPCTL_SNAK);
+ while (otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA)
+ ;
+
+ /* Flush FIFO */
+ otg_txfifo_flush(usbp, ep);
+
+ /* Prepare data for next frame */
+ _usb_isr_invoke_in_cb(usbp, ep);
+
+ /* Pump out data for next frame */
+ osalSysLockFromISR();
+ otgp->DIEPEMPMSK &= ~(1 << ep);
+ usbp->txpending |= (1 << ep);
+ osalThreadResumeI(&usbp->wait, MSG_OK);
+ osalSysUnlockFromISR();
+ }
+ }
+}
+
+/**
+ * @brief Isochronous OUT transfer failed handler.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+static void otg_isoc_out_failed_handler(USBDriver *usbp) {
+ usbep_t ep;
+ stm32_otg_t *otgp = usbp->otg;
+
+ for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
+ if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) &&
+ ((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) {
+ /* Endpoint enabled -> ISOC OUT transfer failed */
+ /* Disable endpoint */
+ /* FIXME: Core stucks here */
+ /*otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK);
+ while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA)
+ ;*/
+ /* Prepare transfer for next frame */
_usb_isr_invoke_out_cb(usbp, ep);
}
}
@@ -642,18 +530,59 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
stm32_otg_t *otgp = usbp->otg;
uint32_t sts, src;
- sts = otgp->GINTSTS & otgp->GINTMSK;
+ sts = otgp->GINTSTS;
+ sts &= otgp->GINTMSK;
otgp->GINTSTS = sts;
/* Reset interrupt handling.*/
if (sts & GINTSTS_USBRST) {
+
+ /* Resetting pending operations.*/
+ usbp->txpending = 0;
+
+ /* Default reset action.*/
_usb_reset(usbp);
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
+
+ /* Preventing execution of more handlers, the core has been reset.*/
+ return;
+ }
+
+ /* Wake-up handling.*/
+ if (sts & GINTSTS_WKUPINT) {
+ /* If clocks are gated off, turn them back on (may be the case if
+ coming out of suspend mode).*/
+ if (otgp->PCGCCTL & (PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK)) {
+ /* Set to zero to un-gate the USB core clocks.*/
+ otgp->PCGCCTL &= ~(PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK);
+ }
+
+ /* Clear the Remote Wake-up Signaling.*/
+ otgp->DCTL &= ~DCTL_RWUSIG;
+
+ _usb_wakeup(usbp);
+ }
+
+ /* Suspend handling.*/
+ if (sts & GINTSTS_USBSUSP) {
+
+ /* Resetting pending operations.*/
+ usbp->txpending = 0;
+
+ /* Default suspend action.*/
+ _usb_suspend(usbp);
}
/* Enumeration done.*/
if (sts & GINTSTS_ENUMDNE) {
- (void)otgp->DSTS;
+ /* Full or High speed timing selection.*/
+ if ((otgp->DSTS & DSTS_ENUMSPD_MASK) == DSTS_ENUMSPD_HS_480) {
+ otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) |
+ GUSBCFG_TRDT(TRDT_VALUE_HS);
+ }
+ else {
+ otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) |
+ GUSBCFG_TRDT(TRDT_VALUE_FS);
+ }
}
/* SOF interrupt handling.*/
@@ -661,18 +590,58 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
_usb_isr_invoke_sof_cb(usbp);
}
+ /* Isochronous IN failed handling */
+ if (sts & GINTSTS_IISOIXFR) {
+ otg_isoc_in_failed_handler(usbp);
+ }
+
+ /* Isochronous OUT failed handling */
+ if (sts & GINTSTS_IISOOXFR) {
+ otg_isoc_out_failed_handler(usbp);
+ }
+
/* RX FIFO not empty handling.*/
if (sts & GINTSTS_RXFLVL) {
/* The interrupt is masked while the thread has control or it would
be triggered again.*/
- chSysLockFromIsr();
+ osalSysLockFromISR();
otgp->GINTMSK &= ~GINTMSK_RXFLVLM;
- usb_lld_wakeup_pump(usbp);
- chSysUnlockFromIsr();
+ osalThreadResumeI(&usbp->wait, MSG_OK);
+ osalSysUnlockFromISR();
}
/* IN/OUT endpoints event handling.*/
src = otgp->DAINT;
+ if (sts & GINTSTS_OEPINT) {
+ if (src & (1 << 16))
+ otg_epout_handler(usbp, 0);
+ if (src & (1 << 17))
+ otg_epout_handler(usbp, 1);
+ if (src & (1 << 18))
+ otg_epout_handler(usbp, 2);
+ if (src & (1 << 19))
+ otg_epout_handler(usbp, 3);
+#if USB_MAX_ENDPOINTS >= 4
+ if (src & (1 << 20))
+ otg_epout_handler(usbp, 4);
+#endif
+#if USB_MAX_ENDPOINTS >= 5
+ if (src & (1 << 21))
+ otg_epout_handler(usbp, 5);
+#endif
+#if USB_MAX_ENDPOINTS >= 6
+ if (src & (1 << 22))
+ otg_epout_handler(usbp, 6);
+#endif
+#if USB_MAX_ENDPOINTS >= 7
+ if (src & (1 << 23))
+ otg_epout_handler(usbp, 7);
+#endif
+#if USB_MAX_ENDPOINTS >= 8
+ if (src & (1 << 24))
+ otg_epout_handler(usbp, 8);
+#endif
+ }
if (sts & GINTSTS_IEPINT) {
if (src & (1 << 0))
otg_epin_handler(usbp, 0);
@@ -682,128 +651,62 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
otg_epin_handler(usbp, 2);
if (src & (1 << 3))
otg_epin_handler(usbp, 3);
-#if STM32_USB_USE_OTG2
+#if USB_MAX_ENDPOINTS >= 4
if (src & (1 << 4))
otg_epin_handler(usbp, 4);
+#endif
+#if USB_MAX_ENDPOINTS >= 5
if (src & (1 << 5))
otg_epin_handler(usbp, 5);
#endif
- }
- if (sts & GINTSTS_OEPINT) {
- if (src & (1 << 16))
- otg_epout_handler(usbp, 0);
- if (src & (1 << 17))
- otg_epout_handler(usbp, 1);
- if (src & (1 << 18))
- otg_epout_handler(usbp, 2);
- if (src & (1 << 19))
- otg_epout_handler(usbp, 3);
-#if STM32_USB_USE_OTG2
- if (src & (1 << 20))
- otg_epout_handler(usbp, 4);
- if (src & (1 << 21))
- otg_epout_handler(usbp, 5);
+#if USB_MAX_ENDPOINTS >= 6
+ if (src & (1 << 6))
+ otg_epin_handler(usbp, 6);
+#endif
+#if USB_MAX_ENDPOINTS >= 7
+ if (src & (1 << 7))
+ otg_epin_handler(usbp, 7);
+#endif
+#if USB_MAX_ENDPOINTS >= 8
+ if (src & (1 << 8))
+ otg_epin_handler(usbp, 8);
#endif
}
}
/*===========================================================================*/
-/* Driver interrupt handlers and threads. */
+/* Driver interrupt handlers. */
/*===========================================================================*/
-static msg_t usb_lld_pump(void *p) {
- USBDriver *usbp = (USBDriver *)p;
- stm32_otg_t *otgp = usbp->otg;
-
- chRegSetThreadName("usb_lld_pump");
- chSysLock();
- while (TRUE) {
- usbep_t ep;
- uint32_t epmask;
-
- /* Nothing to do, going to sleep.*/
- if ((usbp->state == USB_STOP) ||
- ((usbp->txpending == 0) && !(otgp->GINTSTS & GINTSTS_RXFLVL))) {
- otgp->GINTMSK |= GINTMSK_RXFLVLM;
- usbp->thd_wait = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- }
- chSysUnlock();
-
- /* Checks if there are TXFIFOs to be filled.*/
- for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
-
- /* Empties the RX FIFO.*/
- while (otgp->GINTSTS & GINTSTS_RXFLVL) {
- otg_rxfifo_handler(usbp);
- }
-
- epmask = (1 << ep);
- if (usbp->txpending & epmask) {
- bool_t done;
-
- chSysLock();
- /* USB interrupts are globally *suspended* because the peripheral
- does not allow any interference during the TX FIFO filling
- operation.
- Synopsys document: DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
- "The application has to finish writing one complete packet before
- switching to a different channel/endpoint FIFO. Violating this
- rule results in an error.".*/
- otgp->GAHBCFG &= ~GAHBCFG_GINTMSK;
- usbp->txpending &= ~epmask;
- chSysUnlock();
-
- done = otg_txfifo_handler(usbp, ep);
-
- chSysLock();
- otgp->GAHBCFG |= GAHBCFG_GINTMSK;
- if (!done)
- otgp->DIEPEMPMSK |= epmask;
- chSysUnlock();
- }
- }
- chSysLock();
- }
- chSysUnlock();
- return 0;
-}
-
#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
-#if !defined(STM32_OTG1_HANDLER)
-#error "STM32_OTG1_HANDLER not defined"
-#endif
/**
* @brief OTG1 interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_OTG1_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_OTG1_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
usb_lld_serve_interrupt(&USBD1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
-#if !defined(STM32_OTG2_HANDLER)
-#error "STM32_OTG2_HANDLER not defined"
-#endif
/**
* @brief OTG2 interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_OTG2_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_OTG2_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
usb_lld_serve_interrupt(&USBD2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -821,46 +724,44 @@ void usb_lld_init(void) {
/* Driver initialization.*/
#if STM32_USB_USE_OTG1
usbObjectInit(&USBD1);
- USBD1.thd_ptr = NULL;
- USBD1.thd_wait = NULL;
+ USBD1.wait = NULL;
USBD1.otg = OTG_FS;
USBD1.otgparams = &fsparams;
+#if defined(_CHIBIOS_RT_)
+ USBD1.tr = NULL;
/* Filling the thread working area here because the function
@p chThdCreateI() does not do it.*/
#if CH_DBG_FILL_THREADS
{
void *wsp = USBD1.wa_pump;
_thread_memfill((uint8_t *)wsp,
- (uint8_t *)wsp + sizeof(Thread),
- CH_THREAD_FILL_VALUE);
- _thread_memfill((uint8_t *)wsp + sizeof(Thread),
- (uint8_t *)wsp + sizeof(USBD1.wa_pump) - sizeof(Thread),
- CH_STACK_FILL_VALUE);
+ (uint8_t *)wsp + sizeof (USBD1.wa_pump),
+ CH_DBG_STACK_FILL_VALUE);
}
-#endif
+#endif /* CH_DBG_FILL_THREADS */
+#endif /* defined(_CHIBIOS_RT_) */
#endif
#if STM32_USB_USE_OTG2
usbObjectInit(&USBD2);
- USBD2.thd_ptr = NULL;
- USBD2.thd_wait = NULL;
+ USBD2.wait = NULL;
USBD2.otg = OTG_HS;
USBD2.otgparams = &hsparams;
+#if defined(_CHIBIOS_RT_)
+ USBD2.tr = NULL;
/* Filling the thread working area here because the function
@p chThdCreateI() does not do it.*/
#if CH_DBG_FILL_THREADS
{
void *wsp = USBD2.wa_pump;
_thread_memfill((uint8_t *)wsp,
- (uint8_t *)wsp + sizeof(Thread),
- CH_THREAD_FILL_VALUE);
- _thread_memfill((uint8_t *)wsp + sizeof(Thread),
- (uint8_t *)wsp + sizeof(USBD2.wa_pump) - sizeof(Thread),
- CH_STACK_FILL_VALUE);
+ (uint8_t *)wsp + sizeof (USBD2.wa_pump),
+ CH_DBG_STACK_FILL_VALUE);
}
-#endif
+#endif /* CH_DBG_FILL_THREADS */
+#endif /* defined(_CHIBIOS_RT_) */
#endif
}
@@ -879,60 +780,95 @@ void usb_lld_start(USBDriver *usbp) {
if (usbp->state == USB_STOP) {
/* Clock activation.*/
+
#if STM32_USB_USE_OTG1
if (&USBD1 == usbp) {
/* OTG FS clock enable and reset.*/
- rccEnableOTG_FS(FALSE);
+ rccEnableOTG_FS(false);
rccResetOTG_FS();
/* Enables IRQ vector.*/
- nvicEnableVector(STM32_OTG1_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_USB_OTG1_IRQ_PRIORITY));
+ nvicEnableVector(STM32_OTG1_NUMBER, STM32_USB_OTG1_IRQ_PRIORITY);
+
+ /* - Forced device mode.
+ - USB turn-around time = TRDT_VALUE_FS.
+ - Full Speed 1.1 PHY.*/
+ otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) |
+ GUSBCFG_PHYSEL;
+
+ /* 48MHz 1.1 PHY.*/
+ otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11;
}
#endif
+
#if STM32_USB_USE_OTG2
if (&USBD2 == usbp) {
/* OTG HS clock enable and reset.*/
- rccEnableOTG_HS(FALSE);
+ rccEnableOTG_HS(false);
rccResetOTG_HS();
+ /* ULPI clock is managed depending on the presence of an external
+ PHY.*/
+#if defined(BOARD_OTG2_USES_ULPI)
+ rccEnableOTG_HSULPI(true);
+#else
/* Workaround for the problem described here:
- http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798 */
- rccDisableOTG_HSULPI(TRUE);
+ http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798.*/
+ rccDisableOTG_HSULPI(true);
+#endif
/* Enables IRQ vector.*/
- nvicEnableVector(STM32_OTG2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_USB_OTG2_IRQ_PRIORITY));
+ nvicEnableVector(STM32_OTG2_NUMBER, STM32_USB_OTG2_IRQ_PRIORITY);
+
+ /* - Forced device mode.
+ - USB turn-around time = TRDT_VALUE_HS or TRDT_VALUE_FS.*/
+#if defined(BOARD_OTG2_USES_ULPI)
+ /* High speed ULPI PHY.*/
+ otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_HS) |
+ GUSBCFG_SRPCAP | GUSBCFG_HNPCAP;
+#else
+ otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) |
+ GUSBCFG_PHYSEL;
+#endif
+
+#if defined(BOARD_OTG2_USES_ULPI)
+#if STM32_USE_USB_OTG2_HS
+ /* USB 2.0 High Speed PHY in HS mode.*/
+ otgp->DCFG = 0x02200000 | DCFG_DSPD_HS;
+#else
+ /* USB 2.0 High Speed PHY in FS mode.*/
+ otgp->DCFG = 0x02200000 | DCFG_DSPD_HS_FS;
+#endif
+#else
+ /* 48MHz 1.1 PHY.*/
+ otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11;
+#endif
}
#endif
- /* Creates the data pump threads in a suspended state. Note, it is
- created only once, the first time @p usbStart() is invoked.*/
+ /* Clearing mask of TXFIFOs to be filled.*/
usbp->txpending = 0;
- if (usbp->thd_ptr == NULL)
- usbp->thd_ptr = usbp->thd_wait = chThdCreateI(usbp->wa_pump,
- sizeof usbp->wa_pump,
- STM32_USB_OTG_THREAD_PRIO,
- usb_lld_pump,
- usbp);
-
- /* - Forced device mode.
- - USB turn-around time = TRDT_VALUE.
- - Full Speed 1.1 PHY.*/
- otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE) | GUSBCFG_PHYSEL;
-
- /* 48MHz 1.1 PHY.*/
- otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11;
/* PHY enabled.*/
otgp->PCGCCTL = 0;
- /* Internal FS PHY activation.*/
-#if defined(BOARD_OTG_NOVBUSSENS)
- otgp->GCCFG = GCCFG_NOVBUSSENS | GCCFG_VBUSASEN | GCCFG_VBUSBSEN |
- GCCFG_PWRDWN;
+ /* VBUS sensing and transceiver enabled.*/
+ otgp->GOTGCTL = GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
+
+#if defined(BOARD_OTG2_USES_ULPI)
+#if STM32_USB_USE_OTG1
+ if (&USBD1 == usbp) {
+ otgp->GCCFG = GCCFG_INIT_VALUE;
+ }
+#endif
+
+#if STM32_USB_USE_OTG2
+ if (&USBD2 == usbp) {
+ otgp->GCCFG = 0;
+ }
+#endif
#else
- otgp->GCCFG = GCCFG_VBUSASEN | GCCFG_VBUSBSEN | GCCFG_PWRDWN;
+ otgp->GCCFG = GCCFG_INIT_VALUE;
#endif
/* Soft core reset.*/
@@ -950,12 +886,34 @@ void usb_lld_start(USBDriver *usbp) {
otgp->DOEPMSK = 0;
otgp->DAINTMSK = 0;
if (usbp->config->sof_cb == NULL)
- otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM |
- GINTMSK_ESUSPM |*/;
+ otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM |
+ GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM |
+ GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM;
else
- otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM |
- GINTMSK_ESUSPM */ | GINTMSK_SOFM;
- otgp->GINTSTS = 0xFFFFFFFF; /* Clears all pending IRQs, if any. */
+ otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM |
+ GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM |
+ GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM |
+ GINTMSK_SOFM;
+
+ /* Clears all pending IRQs, if any. */
+ otgp->GINTSTS = 0xFFFFFFFF;
+
+#if defined(_CHIBIOS_RT_)
+ /* Creates the data pump thread. Note, it is created only once.*/
+ if (usbp->tr == NULL) {
+ thread_descriptor_t usbpump_descriptor = {
+ "usb_pump",
+ THD_WORKING_AREA_BASE(usbp->wa_pump),
+ THD_WORKING_AREA_END(usbp->wa_pump),
+ STM32_USB_OTG_THREAD_PRIO,
+ usb_lld_pump,
+ (void *)usbp
+ };
+
+ usbp->tr = chThdCreateI(&usbpump_descriptor);
+ chSchRescheduleS();
+ }
+#endif
/* Global interrupts enable.*/
otgp->GAHBCFG |= GAHBCFG_GINTMSK;
@@ -985,17 +943,20 @@ void usb_lld_stop(USBDriver *usbp) {
otgp->GAHBCFG = 0;
otgp->GCCFG = 0;
-#if STM32_USB_USE_USB1
+#if STM32_USB_USE_OTG1
if (&USBD1 == usbp) {
nvicDisableVector(STM32_OTG1_NUMBER);
- rccDisableOTG1(FALSE);
+ rccDisableOTG_FS(false);
}
#endif
-#if STM32_USB_USE_USB2
+#if STM32_USB_USE_OTG2
if (&USBD2 == usbp) {
nvicDisableVector(STM32_OTG2_NUMBER);
- rccDisableOTG2(FALSE);
+ rccDisableOTG_HS(false);
+#if defined(BOARD_OTG2_USES_ULPI)
+ rccDisableOTG_HSULPI(true)
+#endif
}
#endif
}
@@ -1015,18 +976,18 @@ void usb_lld_reset(USBDriver *usbp) {
/* Flush the Tx FIFO.*/
otg_txfifo_flush(usbp, 0);
+ /* Endpoint interrupts all disabled and cleared.*/
+ otgp->DIEPEMPMSK = 0;
+ otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
+
/* All endpoints in NAK mode, interrupts cleared.*/
for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
otgp->ie[i].DIEPCTL = DIEPCTL_SNAK;
otgp->oe[i].DOEPCTL = DOEPCTL_SNAK;
- otgp->ie[i].DIEPINT = 0xFF;
- otgp->oe[i].DOEPINT = 0xFF;
+ otgp->ie[i].DIEPINT = 0xFFFFFFFF;
+ otgp->oe[i].DOEPINT = 0xFFFFFFFF;
}
- /* Endpoint interrupts all disabled and cleared.*/
- otgp->DAINT = 0xFFFFFFFF;
- otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
-
/* Resets the FIFO memory allocator.*/
otg_ram_reset(usbp);
@@ -1044,7 +1005,7 @@ void usb_lld_reset(USBDriver *usbp) {
/* EP0 initialization, it is a special case.*/
usbp->epc[0] = &ep0config;
- otgp->oe[0].DOEPTSIZ = 0;
+ otgp->oe[0].DOEPTSIZ = DOEPTSIZ_STUPCNT(3);
otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL |
DOEPCTL_MPSIZ(ep0config.out_maxsize);
otgp->ie[0].DIEPTSIZ = 0;
@@ -1100,7 +1061,7 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
/* OUT endpoint activation or deactivation.*/
otgp->oe[ep].DOEPTSIZ = 0;
- if (usbp->epc[ep]->out_cb != NULL) {
+ if (usbp->epc[ep]->out_state != NULL) {
otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize);
otgp->DAINTMSK |= DAINTMSK_OEPM(ep);
}
@@ -1111,7 +1072,7 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
/* IN endpoint activation or deactivation.*/
otgp->ie[ep].DIEPTSIZ = 0;
- if (usbp->epc[ep]->in_cb != NULL) {
+ if (usbp->epc[ep]->in_state != NULL) {
/* FIFO allocation for the IN endpoint.*/
fsize = usbp->epc[ep]->in_maxsize / 4;
if (usbp->epc[ep]->in_multiplier > 1)
@@ -1219,38 +1180,57 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
}
/**
- * @brief Prepares for a receive operation.
+ * @brief Starts a receive operation on an OUT endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
-void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
- uint32_t pcnt;
+void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
+ uint32_t pcnt, rxsize;
USBOutEndpointState *osp = usbp->epc[ep]->out_state;
/* Transfer initialization.*/
osp->totsize = osp->rxsize;
- if ((ep == 0) && (osp->rxsize > EP0_MAX_OUTSIZE))
+ if ((ep == 0) && (osp->rxsize > EP0_MAX_OUTSIZE))
osp->rxsize = EP0_MAX_OUTSIZE;
- pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
- usbp->epc[ep]->out_maxsize;
+ /* Transaction size is rounded to a multiple of packet size because the
+ following requirement in the RM:
+ "For OUT transfers, the transfer size field in the endpoint's transfer
+ size register must be a multiple of the maximum packet size of the
+ endpoint, adjusted to the Word boundary".*/
+ pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1U) /
+ usbp->epc[ep]->out_maxsize;
+ rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU;
+
+ /*Setting up transaction parameters in DOEPTSIZ.*/
usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) |
- DOEPTSIZ_XFRSIZ(osp->rxsize);
+ DOEPTSIZ_XFRSIZ(rxsize);
+
+ /* Special case of isochronous endpoint.*/
+ if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) {
+ /* Odd/even bit toggling for isochronous endpoint.*/
+ if (usbp->otg->DSTS & DSTS_FNSOF_ODD)
+ usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SEVNFRM;
+ else
+ usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SODDFRM;
+ }
+ /* Starting operation.*/
+ usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK;
}
/**
- * @brief Prepares for a transmit operation.
+ * @brief Starts a transmit operation on an IN endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
-void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
+void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
USBInEndpointState *isp = usbp->epc[ep]->in_state;
/* Transfer initialization.*/
@@ -1260,40 +1240,27 @@ void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0);
}
else {
- if ((ep == 0) && (isp->txsize > EP0_MAX_INSIZE))
+ if ((ep == 0) && (isp->txsize > EP0_MAX_INSIZE))
isp->txsize = EP0_MAX_INSIZE;
/* Normal case.*/
uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) /
usbp->epc[ep]->in_maxsize;
- usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(pcnt) |
+ /* TODO: Support more than one packet per frame for isochronous transfers.*/
+ usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_MCNT(1) | DIEPTSIZ_PKTCNT(pcnt) |
DIEPTSIZ_XFRSIZ(isp->txsize);
}
-}
-/**
- * @brief Starts a receive operation on an OUT endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
-
- usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_CNAK;
-}
-
-/**
- * @brief Starts a transmit operation on an IN endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
+ /* Special case of isochronous endpoint.*/
+ if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) {
+ /* Odd/even bit toggling.*/
+ if (usbp->otg->DSTS & DSTS_FNSOF_ODD)
+ usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SEVNFRM;
+ else
+ usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SODDFRM;
+ }
+ /* Starting operation.*/
usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep);
}
@@ -1350,6 +1317,71 @@ void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
usbp->otg->ie[ep].DIEPCTL &= ~DIEPCTL_STALL;
}
+/**
+ * @brief USB data transfer loop.
+ * @details This function must be executed by a system thread in order to
+ * make the USB driver work.
+ * @note The data copy part of the driver is implemented in this thread
+ * in order to not perform heavy tasks within interrupt handlers.
+ *
+ * @param[in] p pointer to the @p USBDriver object
+ *
+ * @special
+ */
+void usb_lld_pump(void *p) {
+ USBDriver *usbp = (USBDriver *)p;
+ stm32_otg_t *otgp = usbp->otg;
+
+ osalSysLock();
+ while (true) {
+ usbep_t ep;
+ uint32_t epmask;
+
+ /* Nothing to do, going to sleep.*/
+ if ((usbp->state == USB_STOP) ||
+ ((usbp->txpending == 0) && !(otgp->GINTSTS & GINTSTS_RXFLVL))) {
+ otgp->GINTMSK |= GINTMSK_RXFLVLM;
+ osalThreadSuspendS(&usbp->wait);
+ }
+ osalSysUnlock();
+
+ /* Checks if there are TXFIFOs to be filled.*/
+ for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
+
+ /* Empties the RX FIFO.*/
+ while (otgp->GINTSTS & GINTSTS_RXFLVL) {
+ otg_rxfifo_handler(usbp);
+ }
+
+ epmask = (1 << ep);
+ if (usbp->txpending & epmask) {
+ bool done;
+
+ osalSysLock();
+ /* USB interrupts are globally *suspended* because the peripheral
+ does not allow any interference during the TX FIFO filling
+ operation.
+ Synopsys document: DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
+ "The application has to finish writing one complete packet before
+ switching to a different channel/endpoint FIFO. Violating this
+ rule results in an error.".*/
+ otgp->GAHBCFG &= ~GAHBCFG_GINTMSK;
+ usbp->txpending &= ~epmask;
+ osalSysUnlock();
+
+ done = otg_txfifo_handler(usbp, ep);
+
+ osalSysLock();
+ otgp->GAHBCFG |= GAHBCFG_GINTMSK;
+ if (!done)
+ otgp->DIEPEMPMSK |= epmask;
+ osalSysUnlock();
+ }
+ }
+ osalSysLock();
+ }
+}
+
#endif /* HAL_USE_USB */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/usb_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
similarity index 76%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/usb_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
index e8ff68fb0f..70db7e8cd6 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/usb_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/OTGv1/usb_lld.h
+ * @file OTGv1/hal_usb_lld.h
* @brief STM32 USB subsystem low level driver header.
*
* @addtogroup USB
* @{
*/
-#ifndef _USB_LLD_H_
-#define _USB_LLD_H_
+#ifndef HAL_USB_LLD_H
+#define HAL_USB_LLD_H
#if HAL_USE_USB || defined(__DOXYGEN__)
@@ -33,15 +33,6 @@
/* Driver constants. */
/*===========================================================================*/
-/**
- * @brief Maximum endpoint address.
- */
-#if !STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
-#define USB_MAX_ENDPOINTS 3
-#else
-#define USB_MAX_ENDPOINTS 5
-#endif
-
/**
* @brief Status stage handling method.
*/
@@ -52,6 +43,11 @@
*/
#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS
+/**
+ * @brief Method for set address acknowledge.
+ */
+#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -59,7 +55,7 @@
/**
* @brief OTG1 driver enable switch.
* @details If set to @p TRUE the support for OTG_FS is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE
*/
#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__)
#define STM32_USB_USE_OTG1 FALSE
@@ -68,7 +64,7 @@
/**
* @brief OTG2 driver enable switch.
* @details If set to @p TRUE the support for OTG_HS is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_USB_USE_OTG2) || defined(__DOXYGEN__)
#define STM32_USB_USE_OTG2 FALSE
@@ -104,6 +100,15 @@
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#endif
+/**
+ * @brief Enables HS mode on OTG2 else FS mode.
+ * @note The default is @p TRUE.
+ * @note Has effect only if @p BOARD_OTG2_USES_ULPI is defined.
+ */
+#if !defined(STM32_USE_USB_OTG2_HS) || defined(__DOXYGEN__)
+#define STM32_USE_USB_OTG2_HS TRUE
+#endif
+
/**
* @brief Dedicated data pump threads priority.
*/
@@ -137,10 +142,69 @@
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
#endif
+/**
+ * @brief Host wake-up procedure duration.
+ */
+#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
+#define USB_HOST_WAKEUP_DURATION 2
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+/* Registry checks.*/
+#if !defined(STM32_OTG_STEPPING)
+#error "STM32_OTG_STEPPING not defined in registry"
+#endif
+
+#if (STM32_OTG_STEPPING < 1) || (STM32_OTG_STEPPING > 2)
+#error "unsupported STM32_OTG_STEPPING"
+#endif
+
+#if !defined(STM32_HAS_OTG1) || !defined(STM32_HAS_OTG2)
+#error "STM32_HAS_OTGx not defined in registry"
+#endif
+
+#if STM32_HAS_OTG1 && !defined(STM32_OTG1_ENDPOINTS)
+#error "STM32_OTG1_ENDPOINTS not defined in registry"
+#endif
+
+#if STM32_HAS_OTG2 && !defined(STM32_OTG2_ENDPOINTS)
+#error "STM32_OTG2_ENDPOINTS not defined in registry"
+#endif
+
+#if STM32_HAS_OTG1 && !defined(STM32_OTG1_FIFO_MEM_SIZE)
+#error "STM32_OTG1_FIFO_MEM_SIZE not defined in registry"
+#endif
+
+#if STM32_HAS_OTG2 && !defined(STM32_OTG2_FIFO_MEM_SIZE)
+#error "STM32_OTG2_FIFO_MEM_SIZE not defined in registry"
+#endif
+
+#if (STM32_USB_USE_OTG1 && !defined(STM32_OTG1_HANDLER)) || \
+ (STM32_USB_USE_OTG2 && !defined(STM32_OTG2_HANDLER))
+#error "STM32_OTGx_HANDLER not defined in registry"
+#endif
+
+#if (STM32_USB_USE_OTG1 && !defined(STM32_OTG1_NUMBER)) || \
+ (STM32_USB_USE_OTG2 && !defined(STM32_OTG2_NUMBER))
+#error "STM32_OTGx_NUMBER not defined in registry"
+#endif
+
+/**
+ * @brief Maximum endpoint address.
+ */
+#if (STM32_HAS_OTG2 && STM32_USB_USE_OTG2) || defined(__DOXYGEN__)
+#if (STM32_OTG1_ENDPOINTS < STM32_OTG2_ENDPOINTS) || defined(__DOXYGEN__)
+#define USB_MAX_ENDPOINTS STM32_OTG2_ENDPOINTS
+#else
+#define USB_MAX_ENDPOINTS STM32_OTG1_ENDPOINTS
+#endif
+#else
+#define USB_MAX_ENDPOINTS STM32_OTG1_ENDPOINTS
+#endif
+
#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1
#error "OTG1 not present in the selected device"
#endif
@@ -154,12 +218,12 @@
#endif
#if STM32_USB_USE_OTG1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OTG1"
#endif
#if STM32_USB_USE_OTG2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OTG2"
#endif
@@ -171,10 +235,12 @@
#error "OTG2 RX FIFO size must be a multiple of 4"
#endif
-#if defined(STM32F4XX) || defined(STM32F2XX)
+#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)
#define STM32_USBCLK STM32_PLL48CLK
#elif defined(STM32F10X_CL)
#define STM32_USBCLK STM32_OTGFSCLK
+#elif defined(STM32L4XX)
+#define STM32_USBCLK STM32_48CLK
#else
#error "unsupported STM32 platform for OTG functionality"
#endif
@@ -183,6 +249,10 @@
#error "the USB OTG driver requires a 48MHz clock"
#endif
+#if (USB_HOST_WAKEUP_DURATION < 2) || (USB_HOST_WAKEUP_DURATION > 15)
+#error "invalid USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -200,10 +270,6 @@ typedef struct {
* @brief Type of an IN endpoint state structure.
*/
typedef struct {
- /**
- * @brief Buffer mode, queue or linear.
- */
- bool_t txqueued;
/**
* @brief Requested transmit transfer size.
*/
@@ -212,20 +278,17 @@ typedef struct {
* @brief Transmitted bytes so far.
*/
size_t txcnt;
- union {
- struct {
- /**
- * @brief Pointer to the transmission linear buffer.
- */
- const uint8_t *txbuf;
- } linear;
- struct {
- /**
- * @brief Pointer to the output queue.
- */
- OutputQueue *txqueue;
- } queue;
- } mode;
+ /**
+ * @brief Pointer to the transmission linear buffer.
+ */
+ const uint8_t *txbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
/**
* @brief Total transmit transfer size.
*/
@@ -236,10 +299,6 @@ typedef struct {
* @brief Type of an OUT endpoint state structure.
*/
typedef struct {
- /**
- * @brief Buffer mode, queue or linear.
- */
- bool_t rxqueued;
/**
* @brief Requested receive transfer size.
*/
@@ -248,22 +307,19 @@ typedef struct {
* @brief Received bytes so far.
*/
size_t rxcnt;
- union {
- struct {
- /**
- * @brief Pointer to the receive linear buffer.
- */
- uint8_t *rxbuf;
- } linear;
- struct {
- /**
- * @brief Pointer to the input queue.
- */
- InputQueue *rxqueue;
- } queue;
- } mode;
/**
- * @brief Total transmit transfer size.
+ * @brief Pointer to the receive linear buffer.
+ */
+ uint8_t *rxbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Total receive transfer size.
*/
size_t totsize;
} USBOutEndpointState;
@@ -290,36 +346,34 @@ typedef struct {
usbepcallback_t setup_cb;
/**
* @brief IN endpoint notification callback.
- * @details This field must be set to @p NULL if the IN endpoint is not
- * used.
+ * @details This field must be set to @p NULL if callback is not required.
*/
usbepcallback_t in_cb;
/**
* @brief OUT endpoint notification callback.
- * @details This field must be set to @p NULL if the OUT endpoint is not
- * used.
+ * @details This field must be set to @p NULL if callback is not required.
*/
usbepcallback_t out_cb;
/**
* @brief IN endpoint maximum packet size.
- * @details This field must be set to zero if the IN endpoint is not
- * used.
+ * @details This field must be set to zero if the IN endpoint is not used.
*/
uint16_t in_maxsize;
/**
* @brief OUT endpoint maximum packet size.
- * @details This field must be set to zero if the OUT endpoint is not
- * used.
+ * @details This field must be set to zero if the OUT endpoint is not used.
*/
uint16_t out_maxsize;
/**
* @brief @p USBEndpointState associated to the IN endpoint.
- * @details This structure maintains the state of the IN endpoint.
+ * @details This field must be set to @p NULL if the IN endpoint is not
+ * used.
*/
USBInEndpointState *in_state;
/**
* @brief @p USBEndpointState associated to the OUT endpoint.
- * @details This structure maintains the state of the OUT endpoint.
+ * @details This field must be set to @p NULL if the OUT endpoint is not
+ * used.
*/
USBOutEndpointState *out_state;
/* End of the mandatory fields.*/
@@ -434,6 +488,10 @@ struct USBDriver {
* @brief Current USB device configuration.
*/
uint8_t configuration;
+ /**
+ * @brief State of the driver when a suspend happened.
+ */
+ usbstate_t saved_state;
#if defined(USB_DRIVER_EXT_FIELDS)
USB_DRIVER_EXT_FIELDS
#endif
@@ -455,17 +513,19 @@ struct USBDriver {
*/
uint32_t txpending;
/**
- * @brief Pointer to the thread.
+ * @brief Pointer to the thread when it is sleeping or @p NULL.
*/
- Thread *thd_ptr;
+ thread_reference_t wait;
+#if defined(_CHIBIOS_RT_)
/**
- * @brief Pointer to the thread when it is sleeping or @p NULL.
+ * @brief Pointer to the thread.
*/
- Thread *thd_wait;
+ thread_reference_t tr;
/**
* @brief Working area for the dedicated data pump thread;
*/
- WORKING_AREA(wa_pump, STM32_USB_OTG_THREAD_STACK_SIZE);
+ THD_WORKING_AREA(wa_pump, STM32_USB_OTG_THREAD_STACK_SIZE);
+#endif
};
/*===========================================================================*/
@@ -492,16 +552,36 @@ struct USBDriver {
/**
* @brief Connects the USB device.
*
- * @api
+ * @notapi
*/
+#if (STM32_OTG_STEPPING == 1) || defined(__DOXYGEN__)
#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN)
+#else
+#define usb_lld_connect_bus(usbp) ((usbp)->otg->DCTL &= ~DCTL_SDIS)
+#endif
/**
* @brief Disconnect the USB device.
*
- * @api
+ * @notapi
*/
+#if (STM32_OTG_STEPPING == 1) || defined(__DOXYGEN__)
#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN)
+#else
+#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->DCTL |= DCTL_SDIS)
+#endif
+
+/**
+ * @brief Start of host wake-up procedure.
+ *
+ * @notapi
+ */
+#define usb_lld_wakeup_host(usbp) \
+ do{ \
+ (usbp)->otg->DCTL |= DCTL_RWUSIG; \
+ osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION); \
+ (usbp)->otg->DCTL &= ~DCTL_RWUSIG; \
+ } while (false)
/*===========================================================================*/
/* External declarations. */
@@ -528,20 +608,19 @@ extern "C" {
usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
- void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
- void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_pump(void *p);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_USB */
-#endif /* _USB_LLD_H_ */
+#endif /* HAL_USB_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/stm32_otg.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
similarity index 97%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/stm32_otg.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
index 7b1c183ff9..5f12e629a6 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/OTGv1/stm32_otg.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,27 +15,15 @@
*/
/**
- * @file stm32_otg.h
+ * @file OTGv1/stm32_otg.h
* @brief STM32 OTG registers layout header.
*
* @addtogroup USB
* @{
*/
-#ifndef _STM32_OTG_H_
-#define _STM32_OTG_H_
-
-/**
- * @brief Number of the implemented endpoints in OTG_FS.
- * @details This value does not include the endpoint 0 that is always present.
- */
-#define STM32_OTG1_ENDOPOINTS_NUMBER 3
-
-/**
- * @brief Number of the implemented endpoints in OTG_HS.
- * @details This value does not include the endpoint 0 that is always present.
- */
-#define STM32_OTG2_ENDOPOINTS_NUMBER 5
+#ifndef STM32_OTG_H
+#define STM32_OTG_H
/**
* @brief OTG_FS FIFO memory size in words.
@@ -189,10 +177,17 @@ typedef struct {
#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */
#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */
#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */
+#define GOTGCTL_EHEN (1U<<12)
#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */
#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */
#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */
#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */
+#define GOTGCTL_BVALOVAL (1U<<7)
+#define GOTGCTL_BVALOEN (1U<<6)
+#define GOTGCTL_AVALOVAL (1U<<5)
+#define GOTGCTL_AVALOEN (1U<<4)
+#define GOTGCTL_VBVALOVAL (1U<<3)
+#define GOTGCTL_VBVALOEN (1U<<2)
#define GOTGCTL_SRQ (1U<<1) /**< Session request. */
#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */
/** @} */
@@ -422,12 +417,16 @@ typedef struct {
* @name GCCFG register bit definitions
* @{
*/
+/* Definitions for stepping 1.*/
#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */
#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */
#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B"
device. */
#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A"
device. */
+
+/* Definitions for stepping 2.*/
+#define GCCFG_VBDEN (1U<<21) /**< VBUS sensing enable. */
#define GCCFG_PWRDWN (1U<<16) /**< Power down. */
/** @} */
@@ -563,8 +562,8 @@ typedef struct {
#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */
#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */
#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */
-#define HCCHAR_MPS_MASK (11U<<0) /**< Maximum packet size mask. */
-#define HCCHAR_MPS(n) (11U<<0) /**< Maximum packet size value. */
+#define HCCHAR_MPS_MASK (0x7FFU<<0) /**< Maximum packet size mask. */
+#define HCCHAR_MPS(n) ((n)<<0) /**< Maximum packet size value. */
/** @} */
/**
@@ -582,6 +581,7 @@ typedef struct {
interrupt. */
#define HCINT_STALL (1U<<3) /**< STALL response received
interrupt. */
+#define HCINT_AHBERR (1U<<2) /**< AHB error interrupt. */
#define HCINT_CHH (1U<<1) /**< Channel halted. */
#define HCINT_XFRC (1U<<0) /**< Transfer completed. */
/** @} */
@@ -603,6 +603,7 @@ typedef struct {
interrupt mask. */
#define HCINTMSK_STALLM (1U<<3) /**< STALL response received
interrupt mask. */
+#define HCINTMSK_AHBERRM (1U<<2) /**< AHB error interrupt mask. */
#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */
#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */
/** @} */
@@ -616,6 +617,7 @@ typedef struct {
#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */
#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */
#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */
+#define HCTSIZ_DPID_SETUP (3U<<29) /**< SETUP. */
#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */
@@ -671,10 +673,13 @@ typedef struct {
SOF mask. */
#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received
SOF value. */
+#define DSTS_FNSOF_ODD (1U<<8) /**< Frame parity of the received
+ SOF value. */
#define DSTS_EERR (1U<<3) /**< Erratic error. */
#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */
#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is
running at 48 MHz). */
+#define DSTS_ENUMSPD_HS_480 (0U<<1) /**< High speed. */
#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */
/** @} */
@@ -857,6 +862,7 @@ typedef struct {
* @name DOEPINT register bit definitions
* @{
*/
+#define DOEPINT_SETUP_RCVD (1U<<15) /**< SETUP packet received. */
#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets
received. */
#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when
@@ -911,6 +917,6 @@ typedef struct {
*/
#define OTG_HS ((stm32_otg_t *)OTG_HS_ADDR)
-#endif /* _STM32_OTG_H_ */
+#endif /* STM32_OTG_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
new file mode 100644
index 0000000000..802f8eaf6e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_QSPI TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
new file mode 100644
index 0000000000..b2e97dfca8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
@@ -0,0 +1,349 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file QUADSPIv1/hal_qspi_lld.c
+ * @brief STM32 QSPI subsystem low level driver source.
+ *
+ * @addtogroup QSPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_QSPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define QUADSPI1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_QSPI_QUADSPI1_DMA_STREAM, \
+ STM32_QUADSPI1_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief QUADSPI1 driver identifier.*/
+#if STM32_QSPI_USE_QUADSPI1 || defined(__DOXYGEN__)
+QSPIDriver QSPID1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Shared service routine.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void qspi_lld_serve_dma_interrupt(QSPIDriver *qspip, uint32_t flags) {
+
+ (void)qspip;
+ (void)flags;
+
+ /* DMA errors handling.*/
+#if defined(STM32_QSPI_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_QSPI_DMA_ERROR_HOOK(qspip);
+ }
+#endif
+}
+
+/**
+ * @brief Shared service routine.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ */
+static void qspi_lld_serve_interrupt(QSPIDriver *qspip) {
+
+ /* Stop everything.*/
+ dmaStreamDisable(qspip->dma);
+
+ /* Portable QSPI ISR code defined in the high level driver, note, it is
+ a macro.*/
+ _qspi_isr_code(qspip);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_QSPI_USE_QUADSPI1 || defined(__DOXYGEN__)
+#if !defined(STM32_QUADSPI1_SUPPRESS_ISR)
+#if !defined(STM32_QUADSPI1_HANDLER)
+#error "STM32_QUADSPI1_HANDLER not defined"
+#endif
+/**
+ * @brief STM32_QUADSPI1_HANDLER interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_QUADSPI1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ QUADSPI->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
+ QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
+
+ qspi_lld_serve_interrupt(&QSPID1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* !defined(STM32_QUADSPI1_SUPPRESS_ISR) */
+#endif /* STM32_QSPI_USE_QUADSPI1 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level QSPI driver initialization.
+ *
+ * @notapi
+ */
+void qspi_lld_init(void) {
+
+#if STM32_QSPI_USE_QUADSPI1
+ qspiObjectInit(&QSPID1);
+ QSPID1.qspi = QUADSPI;
+ QSPID1.dma = STM32_DMA_STREAM(STM32_QSPI_QUADSPI1_DMA_STREAM);
+ QSPID1.dmamode = STM32_DMA_CR_CHSEL(QUADSPI1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_QSPI_QUADSPI1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_BYTE |
+ STM32_DMA_CR_MSIZE_BYTE |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+ nvicEnableVector(STM32_QUADSPI1_NUMBER, STM32_QSPI_QUADSPI1_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Configures and activates the QSPI peripheral.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @notapi
+ */
+void qspi_lld_start(QSPIDriver *qspip) {
+
+ /* If in stopped state then full initialization.*/
+ if (qspip->state == QSPI_STOP) {
+#if STM32_QSPI_USE_QUADSPI1
+ if (&QSPID1 == qspip) {
+ bool b = dmaStreamAllocate(qspip->dma,
+ STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)qspi_lld_serve_dma_interrupt,
+ (void *)qspip);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableQUADSPI1(false);
+ }
+#endif
+
+ /* Common initializations.*/
+ dmaStreamSetPeripheral(qspip->dma, &qspip->qspi->DR);
+ }
+
+ /* QSPI setup and enable.*/
+ qspip->qspi->DCR = qspip->config->dcr;
+ qspip->qspi->CR = ((STM32_QSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |
+ QUADSPI_CR_TCIE | QUADSPI_CR_DMAEN | QUADSPI_CR_EN;
+ qspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
+ QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
+}
+
+/**
+ * @brief Deactivates the QSPI peripheral.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @notapi
+ */
+void qspi_lld_stop(QSPIDriver *qspip) {
+
+ /* If in ready state then disables the QUADSPI clock.*/
+ if (qspip->state == QSPI_READY) {
+
+ /* QSPI disable.*/
+ qspip->qspi->CR = 0U;
+
+ /* Releasing the DMA.*/
+ dmaStreamRelease(qspip->dma);
+
+ /* Stopping involved clocks.*/
+#if STM32_QSPI_USE_QUADSPI1
+ if (&QSPID1 == qspip) {
+ rccDisableQUADSPI1(FALSE);
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Sends a command without data phase.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmd pointer to the command descriptor
+ *
+ * @notapi
+ */
+void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp) {
+
+#if STM32_USE_STM32_D1_WORKAROUND == TRUE
+ /* If it is a command without address and alternate phases then the command
+ is sent as an alternate byte, the command phase is suppressed.*/
+ if ((cmdp->cfg & (QSPI_CFG_ADDR_MODE_MASK | QSPI_CFG_ALT_MODE_MASK)) == 0U) {
+ uint32_t cfg;
+
+ /* The command mode field is copied in the alternate mode field. All
+ other fields are not used in this scenario.*/
+ cfg = (cmdp->cfg & QSPI_CFG_CMD_MODE_MASK) << 6U;
+
+ qspip->qspi->DLR = 0U;
+ qspip->qspi->ABR = cmdp->cfg & QSPI_CFG_CMD_MASK;
+ qspip->qspi->CCR = cfg;
+ return;
+ }
+#endif
+ qspip->qspi->DLR = 0U;
+ qspip->qspi->ABR = cmdp->alt;
+ qspip->qspi->CCR = cmdp->cfg;
+ if ((cmdp->cfg & QSPI_CFG_ADDR_MODE_MASK) != QSPI_CFG_ADDR_MODE_NONE) {
+ qspip->qspi->AR = cmdp->addr;
+ }
+}
+
+/**
+ * @brief Sends a command with data over the QSPI bus.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmd pointer to the command descriptor
+ * @param[in] n number of bytes to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, const uint8_t *txbuf) {
+
+ dmaStreamSetMemory0(qspip->dma, txbuf);
+ dmaStreamSetTransactionSize(qspip->dma, n);
+ dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_M2P);
+
+ qspip->qspi->DLR = n - 1;
+ qspip->qspi->ABR = cmdp->alt;
+ qspip->qspi->CCR = cmdp->cfg;
+ if ((cmdp->cfg & QSPI_CFG_ADDR_MODE_MASK) != QSPI_CFG_ADDR_MODE_NONE) {
+ qspip->qspi->AR = cmdp->addr;
+ }
+
+ dmaStreamEnable(qspip->dma);
+}
+
+/**
+ * @brief Sends a command then receives data over the QSPI bus.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmd pointer to the command descriptor
+ * @param[in] n number of bytes to send
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, uint8_t *rxbuf) {
+
+ dmaStreamSetMemory0(qspip->dma, rxbuf);
+ dmaStreamSetTransactionSize(qspip->dma, n);
+ dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_P2M);
+
+ qspip->qspi->DLR = n - 1;
+ qspip->qspi->ABR = cmdp->alt;
+ qspip->qspi->CCR = cmdp->cfg | QUADSPI_CCR_FMODE_0;
+ if ((cmdp->cfg & QSPI_CFG_ADDR_MODE_MASK) != QSPI_CFG_ADDR_MODE_NONE) {
+ qspip->qspi->AR = cmdp->addr;
+ }
+
+ dmaStreamEnable(qspip->dma);
+}
+
+#if (QSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Maps in memory space a QSPI flash device.
+ * @pre The memory flash device must be initialized appropriately
+ * before mapping it in memory space.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[out] addrp pointer to the memory start address of the mapped
+ * flash or @p NULL
+ *
+ * @notapi
+ */
+void qspi_lld_map_flash(QSPIDriver *qspip,
+ const qspi_command_t *cmdp,
+ uint8_t **addrp) {
+
+ /* Disabling the DMA request while in memory mapped mode.*/
+ qspip->qspi->CR &= ~QUADSPI_CR_DMAEN;
+
+ /* Starting memory mapped mode using the passed parameters.*/
+ qspip->qspi->DLR = 0;
+ qspip->qspi->ABR = 0;
+ qspip->qspi->AR = 0;
+ qspip->qspi->CCR = cmdp->cfg | QUADSPI_CCR_FMODE_1 | QUADSPI_CCR_FMODE_0;
+
+ /* Mapped flash absolute base address.*/
+ if (addrp != NULL) {
+ *addrp = (uint8_t *)0x90000000;
+ }
+}
+
+/**
+ * @brief Maps in memory space a QSPI flash device.
+ * @post The memory flash device must be re-initialized for normal
+ * commands exchange.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @notapi
+ */
+void qspi_lld_unmap_flash(QSPIDriver *qspip) {
+
+ /* Aborting memory mapped mode.*/
+ qspip->qspi->CR |= QUADSPI_CR_ABORT;
+ while ((qspip->qspi->CR & QUADSPI_CR_ABORT) != 0U) {
+ }
+
+ /* Re-enabling DMA request, we are going back to indirect mode.*/
+ qspip->qspi->CR |= QUADSPI_CR_DMAEN;
+}
+#endif /* QSPI_SUPPORTS_MEMMAP == TRUE */
+
+#endif /* HAL_USE_QSPI */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h
new file mode 100644
index 0000000000..5dcd0c6e1b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h
@@ -0,0 +1,281 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file QUADSPIv1/hal_qspi_lld.h
+ * @brief STM32 QSPI subsystem low level driver header.
+ *
+ * @addtogroup QSPI
+ * @{
+ */
+
+#ifndef HAL_QSPI_LLD_H
+#define HAL_QSPI_LLD_H
+
+#if (HAL_USE_QSPI == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name QSPI capabilities
+ * @{
+ */
+#define QSPI_SUPPORTS_MEMMAP TRUE
+/** @} */
+
+/**
+ * @name DCR register options
+ * @{
+ */
+#define STM32_DCR_CK_MODE (1U << 0U)
+#define STM32_DCR_CSHT_MASK (7U << 8U)
+#define STM32_DCR_CSHT(n) ((n) << 8U)
+#define STM32_DCR_FSIZE_MASK (31U << 16U)
+#define STM32_DCR_FSIZE(n) ((n) << 16U)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief QUADSPI1 driver enable switch.
+ * @details If set to @p TRUE the support for QUADSPI1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_QSPI_USE_QUADSPI1) || defined(__DOXYGEN__)
+#define STM32_QSPI_USE_QUADSPI1 FALSE
+#endif
+
+/**
+ * @brief QUADSPI1 prescaler setting.
+ * @note This is the prescaler divider value 1..256. The maximum frequency
+ * varies depending on the STM32 model and operating conditions,
+ * find the details in the data sheet.
+ */
+#if !defined(STM32_QSPI_QUADSPI1_PRESCALER_VALUE) || defined(__DOXYGEN__)
+#define STM32_QSPI_QUADSPI1_PRESCALER_VALUE 1
+#endif
+
+/**
+ * @brief QUADSPI1 interrupt priority level setting.
+ */
+#if !defined(STM32_QSPI_QUADSPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QSPI_QUADSPI1_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief QUADSPI1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_QSPI_QUADSPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QSPI_QUADSPI1_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief QUADSPI1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief QUADSPI DMA error hook.
+ */
+#if !defined(STM32_QSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_QSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
+#endif
+
+/**
+ * @brief Enables a workaround for a STM32L476 QUADSPI errata.
+ * @details The document DM00111498 states: "QUADSPI_BK1_IO1 is always an
+ * input when the command is sent in dual or quad SPI mode".
+ * This workaround makes commands without address or data phases
+ * to be sent as alternate bytes.
+ */
+#if !defined(STM32_USE_STM32_D1_WORKAROUND) || defined(__DOXYGEN__)
+#define STM32_USE_STM32_D1_WORKAROUND TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_QSPI_USE_QUADSPI1 && !STM32_HAS_QUADSPI1
+#error "QUADSPI1 not present in the selected device"
+#endif
+
+#if !STM32_QSPI_USE_QUADSPI1
+#error "QSPI driver activated but no QUADSPI peripheral assigned"
+#endif
+
+#if STM32_QSPI_USE_QUADSPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to QUADSPI1"
+#endif
+
+#if STM32_QSPI_USE_QUADSPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to QUADSPI1 DMA"
+#endif
+
+#if STM32_QSPI_USE_QUADSPI1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to QUADSPI1"
+#endif
+
+#if (STM32_QSPI_QUADSPI1_PRESCALER_VALUE < 1) || \
+ (STM32_QSPI_QUADSPI1_PRESCALER_VALUE > 256)
+#error "STM32_QSPI_QUADSPI1_PRESCALER_VALUE not within 1..256"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_QSPI_USE_QUADSPI1 && !defined(STM32_QSPI_QUADSPI1_DMA_STREAM)
+#error "QUADSPI1 DMA stream not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_QSPI_USE_QUADSPI1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_QSPI_QUADSPI1_DMA_STREAM, STM32_QUADSPI1_DMA_MSK)
+#error "invalid DMA stream associated to QUADSPI1"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an QSPI driver.
+ */
+typedef struct QSPIDriver QSPIDriver;
+
+/**
+ * @brief Type of a QSPI notification callback.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object triggering the
+ * callback
+ */
+typedef void (*qspicallback_t)(QSPIDriver *qspip);
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Operation complete callback or @p NULL.
+ */
+ qspicallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief DCR register initialization data.
+ */
+ uint32_t dcr;
+} QSPIConfig;
+
+/**
+ * @brief Structure representing an QSPI driver.
+ */
+struct QSPIDriver {
+ /**
+ * @brief Driver state.
+ */
+ qspistate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const QSPIConfig *config;
+#if (QSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif /* QSPI_USE_WAIT */
+#if (QSPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* QSPI_USE_MUTUAL_EXCLUSION */
+#if defined(QSPI_DRIVER_EXT_FIELDS)
+ QSPI_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the QUADSPIx registers block.
+ */
+ QUADSPI_TypeDef *qspi;
+ /**
+ * @brief QUADSPI DMA stream.
+ */
+ const stm32_dma_stream_t *dma;
+ /**
+ * @brief QUADSPI DMA mode bit mask.
+ */
+ uint32_t dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (STM32_QSPI_USE_QUADSPI1 == TRUE) && !defined(__DOXYGEN__)
+extern QSPIDriver QSPID1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void qspi_lld_init(void);
+ void qspi_lld_start(QSPIDriver *qspip);
+ void qspi_lld_stop(QSPIDriver *qspip);
+ void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp);
+ void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, const uint8_t *txbuf);
+ void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, uint8_t *rxbuf);
+#if QSPI_SUPPORTS_MEMMAP == TRUE
+ void qspi_lld_map_flash(QSPIDriver *qspip,
+ const qspi_command_t *cmdp,
+ uint8_t **addrp);
+ void qspi_lld_unmap_flash(QSPIDriver *qspip);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_QSPI */
+
+#endif /* HAL_QSPI_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/driver.mk
new file mode 100644
index 0000000000..1dbb3b7733
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c
similarity index 51%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv1/rtc_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c
index 6980dbd6b2..33fbdb0568 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,14 +19,13 @@
*/
/**
- * @file STM32/RTCv1/rtc_lld.c
+ * @file RTCv1/hal_rtc_lld.c
* @brief STM32 RTC subsystem low level driver header.
*
* @addtogroup RTC
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_RTC || defined(__DOXYGEN__)
@@ -60,7 +59,11 @@ RTCDriver RTCD1;
*
* @notapi
*/
-#define rtc_lld_apb1_sync() {while ((RTC->CRL & RTC_CRL_RSF) == 0);}
+static void rtc_apb1_sync(void) {
+
+ while ((RTC->CRL & RTC_CRL_RSF) == 0)
+ ;
+}
/**
* @brief Wait for for previous write operation complete.
@@ -68,7 +71,11 @@ RTCDriver RTCD1;
*
* @notapi
*/
-#define rtc_lld_wait_write() {while ((RTC->CRL & RTC_CRL_RTOFF) == 0);}
+static void rtc_wait_write_completed(void) {
+
+ while ((RTC->CRL & RTC_CRL_RTOFF) == 0)
+ ;
+}
/**
* @brief Acquires write access to RTC registers.
@@ -78,14 +85,64 @@ RTCDriver RTCD1;
*
* @notapi
*/
-#define rtc_lld_acquire() {rtc_lld_wait_write(); RTC->CRL |= RTC_CRL_CNF;}
+static void rtc_acquire_access(void) {
+
+ rtc_wait_write_completed();
+ RTC->CRL |= RTC_CRL_CNF;
+}
/**
* @brief Releases write access to RTC registers.
*
* @notapi
*/
-#define rtc_lld_release() {RTC->CRL &= ~RTC_CRL_CNF;}
+static void rtc_release_access(void) {
+
+ RTC->CRL &= ~RTC_CRL_CNF;
+}
+
+/**
+ * @brief Converts time from timespec to seconds counter.
+ *
+ * @param[in] timespec pointer to a @p RTCDateTime structure
+ * @return the TR register encoding.
+ *
+ * @notapi
+ */
+static time_t rtc_encode(const RTCDateTime *timespec) {
+ struct tm tim;
+
+ rtcConvertDateTimeToStructTm(timespec, &tim, NULL);
+ return mktime(&tim);
+}
+
+/**
+ * @brief Converts time from seconds/milliseconds to timespec.
+ *
+ * @param[in] tv_sec seconds value
+ * @param[in] tv_msec milliseconds value
+ * @param[out] timespec pointer to a @p RTCDateTime structure
+ *
+ * @notapi
+ */
+static void rtc_decode(uint32_t tv_sec,
+ uint32_t tv_msec,
+ RTCDateTime *timespec) {
+ struct tm tim;
+ struct tm *t;
+
+ /* If the conversion is successful the function returns a pointer
+ to the object the result was written into.*/
+#if defined(__GNUC__) || defined(__CC_ARM)
+ t = localtime_r((time_t *)&(tv_sec), &tim);
+ osalDbgAssert(t != NULL, "conversion failed");
+#else
+ t = localtime(&tv_sec);
+ memcpy(&tim, t, sizeof(struct tm));
+#endif
+
+ rtcConvertStructTmToDateTime(&tim, tv_msec, timespec);
+}
/*===========================================================================*/
/* Driver interrupt handlers. */
@@ -96,18 +153,18 @@ RTCDriver RTCD1;
*
* @isr
*/
-CH_IRQ_HANDLER(RTC_IRQHandler) {
+OSAL_IRQ_HANDLER(STM32_RTC1_HANDLER) {
uint16_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- /* This wait works only when AHB1 bus was previously powered off by any
- reason (standby, reset, etc). In other cases it does nothing.*/
- rtc_lld_apb1_sync();
+ /* Code hits this wait only when AHB1 bus was previously powered off by any
+ reason (standby, reset, etc). In other cases there is no waiting.*/
+ rtc_apb1_sync();
/* Mask of all enabled and pending sources.*/
- flags = RTC->CRH & RTC->CRL;
- RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
+ flags = RTCD1.rtc->CRH & RTCD1.rtc->CRL;
+ RTCD1.rtc->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
if (flags & RTC_CRL_SECF)
RTCD1.callback(&RTCD1, RTC_EVENT_SECOND);
@@ -118,7 +175,7 @@ CH_IRQ_HANDLER(RTC_IRQHandler) {
if (flags & RTC_CRL_OWF)
RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
@@ -135,11 +192,19 @@ CH_IRQ_HANDLER(RTC_IRQHandler) {
*
* @notapi
*/
-void rtc_lld_set_prescaler(void){
- rtc_lld_acquire();
+void rtc_lld_set_prescaler(void) {
+ syssts_t sts;
+
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
+
+ rtc_acquire_access();
RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F;
RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF);
- rtc_lld_release();
+ rtc_release_access();
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
}
/**
@@ -147,76 +212,70 @@ void rtc_lld_set_prescaler(void){
*
* @notapi
*/
-void rtc_lld_init(void){
+void rtc_lld_init(void) {
+
+ /* RTC object initialization.*/
+ rtcObjectInit(&RTCD1);
+
+ /* RTC pointer initialization.*/
+ RTCD1.rtc = RTC;
/* RSF bit must be cleared by software after an APB1 reset or an APB1 clock
stop. Otherwise its value will not be actual. */
- RTC->CRL &= ~RTC_CRL_RSF;
+ RTCD1.rtc->CRL &= ~RTC_CRL_RSF;
/* Required because access to PRL.*/
- rtc_lld_apb1_sync();
+ rtc_apb1_sync();
/* All interrupts initially disabled.*/
- rtc_lld_wait_write();
- RTC->CRH = 0;
+ rtc_wait_write_completed();
+ RTCD1.rtc->CRH = 0;
/* Callback initially disabled.*/
RTCD1.callback = NULL;
/* IRQ vector permanently assigned to this driver.*/
- nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY));
+ nvicEnableVector(STM32_RTC1_NUMBER, STM32_RTC_IRQ_PRIORITY);
}
/**
* @brief Set current time.
* @note Fractional part will be silently ignored. There is no possibility
* to change it on STM32F1xx platform.
+ * @note The function can be called from any context.
*
* @param[in] rtcp pointer to RTC driver structure
- * @param[in] timespec pointer to a @p RTCTime structure
+ * @param[in] timespec pointer to a @p RTCDateTime structure
*
* @notapi
*/
-void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
+void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) {
+ time_t tv_sec = rtc_encode(timespec);
- (void)rtcp;
-
- rtc_lld_acquire();
- RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16);
- RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF);
- rtc_lld_release();
+ rtcSTM32SetSec(rtcp, tv_sec);
}
/**
* @brief Get current time.
+ * @note The function can be called from any context.
*
* @param[in] rtcp pointer to RTC driver structure
- * @param[in] timespec pointer to a @p RTCTime structure
+ * @param[in] timespec pointer to a @p RTCDateTime structure
*
* @notapi
*/
-void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
- (void)rtcp;
-
- uint32_t time_frac;
+void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) {
+ uint32_t tv_sec, tv_msec;
- /* Required because access to CNT and DIV.*/
- rtc_lld_apb1_sync();
-
- /* Loops until two consecutive read returning the same value.*/
- do {
- timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL;
- time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL;
- } while ((timespec->tv_sec) != (((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL));
-
- timespec->tv_msec = (uint16_t)(((STM32_RTCCLK - 1 - time_frac) * 1000) /
- STM32_RTCCLK);
+ rtcSTM32GetSecMsec(rtcp, &tv_sec, &tv_msec);
+ rtc_decode(tv_sec, tv_msec, timespec);
}
/**
* @brief Set alarm time.
*
- * @note Default value after BKP domain reset is 0xFFFFFFFF
+ * @note Default value after BKP domain reset is 0xFFFFFFFF
+ * @note The function can be called from any context.
*
* @param[in] rtcp pointer to RTC driver structure
* @param[in] alarm alarm identifier
@@ -225,29 +284,34 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
* @notapi
*/
void rtc_lld_set_alarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
+ rtcalarm_t alarm_number,
const RTCAlarm *alarmspec) {
+ syssts_t sts;
+ (void)alarm_number;
- (void)rtcp;
- (void)alarm;
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
- rtc_lld_acquire();
+ rtc_acquire_access();
if (alarmspec != NULL) {
- RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16);
- RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF);
+ rtcp->rtc->ALRH = (uint16_t)(alarmspec->tv_sec >> 16);
+ rtcp->rtc->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF);
}
else {
- RTC->ALRH = 0;
- RTC->ALRL = 0;
+ rtcp->rtc->ALRH = 0;
+ rtcp->rtc->ALRL = 0;
}
- rtc_lld_release();
+ rtc_release_access();
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
}
/**
* @brief Get current alarm.
* @note If an alarm has not been set then the returned alarm specification
* is not meaningful.
- *
+ * @note The function can be called from any context.
* @note Default value after BKP domain reset is 0xFFFFFFFF.
*
* @param[in] rtcp pointer to RTC driver structure
@@ -257,22 +321,28 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
* @notapi
*/
void rtc_lld_get_alarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
+ rtcalarm_t alarm_number,
RTCAlarm *alarmspec) {
+ syssts_t sts;
+ (void)alarm_number;
- (void)rtcp;
- (void)alarm;
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
/* Required because access to ALR.*/
- rtc_lld_apb1_sync();
+ rtc_apb1_sync();
+
+ alarmspec->tv_sec = ((rtcp->rtc->ALRH << 16) + rtcp->rtc->ALRL);
- alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL);
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
}
/**
* @brief Enables or disables RTC callbacks.
* @details This function enables or disables callbacks, use a @p NULL pointer
* in order to disable a callback.
+ * @note The function can be called from any context.
*
* @param[in] rtcp pointer to RTC driver structure
* @param[in] callback callback function pointer or @p NULL
@@ -280,50 +350,97 @@ void rtc_lld_get_alarm(RTCDriver *rtcp,
* @notapi
*/
void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
+ syssts_t sts;
+
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
if (callback != NULL) {
/* IRQ sources enabled only after setting up the callback.*/
rtcp->callback = callback;
- rtc_lld_wait_write();
- RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
- RTC->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;
+ rtc_wait_write_completed();
+ rtcp->rtc->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
+ rtcp->rtc->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;
}
else {
- rtc_lld_wait_write();
- RTC->CRH = 0;
+ rtc_wait_write_completed();
+ rtcp->rtc->CRH = 0;
/* Callback set to NULL only after disabling the IRQ sources.*/
rtcp->callback = NULL;
}
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
}
-#include "chrtclib.h"
+/**
+ * @brief Get seconds and (optionally) milliseconds from RTC.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[out] tv_sec pointer to seconds value
+ * @param[out] tv_msec pointer to milliseconds value, set it
+ * to @p NULL if not needed
+ *
+ * @api
+ */
+void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec) {
+ uint32_t time_frac;
+ syssts_t sts;
+
+ osalDbgCheck((NULL != tv_sec) && (NULL != rtcp));
+
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
+
+ /* Required because access to CNT and DIV.*/
+ rtc_apb1_sync();
+
+ /* wait for previous write accesses to complete.*/
+ rtc_wait_write_completed();
+
+ /* Loops until two consecutive read returning the same value.*/
+ do {
+ *tv_sec = ((uint32_t)(rtcp->rtc->CNTH) << 16) + rtcp->rtc->CNTL;
+ time_frac = (((uint32_t)rtcp->rtc->DIVH) << 16) + (uint32_t)rtcp->rtc->DIVL;
+ } while ((*tv_sec) != (((uint32_t)(rtcp->rtc->CNTH) << 16) + rtcp->rtc->CNTL));
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
+
+ if (NULL != tv_msec)
+ *tv_msec = (((uint32_t)STM32_RTCCLK - 1 - time_frac) * 1000) / STM32_RTCCLK;
+}
/**
- * @brief Get current time in format suitable for usage in FatFS.
+ * @brief Set seconds in RTC.
+ * @note The function can be called from any context.
*
* @param[in] rtcp pointer to RTC driver structure
- * @return FAT time value.
+ * @param[in] tv_sec seconds value
*
* @api
*/
-uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
- uint32_t fattime;
- struct tm timp;
+void rtcSTM32SetSec(RTCDriver *rtcp, uint32_t tv_sec) {
+ syssts_t sts;
+
+ osalDbgCheck(NULL != rtcp);
- rtcGetTimeTm(rtcp, &timp);
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
- fattime = (timp.tm_sec) >> 1;
- fattime |= (timp.tm_min) << 5;
- fattime |= (timp.tm_hour) << 11;
- fattime |= (timp.tm_mday) << 16;
- fattime |= (timp.tm_mon + 1) << 21;
- fattime |= (timp.tm_year - 80) << 25;
+ rtc_acquire_access();
+ rtcp->rtc->CNTH = (uint16_t)(tv_sec >> 16);
+ rtcp->rtc->CNTL = (uint16_t)(tv_sec & 0xFFFF);
+ rtc_release_access();
- return fattime;
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
}
+
#endif /* HAL_USE_RTC */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.h
similarity index 75%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv1/rtc_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.h
index 69508d60a4..f7d0d2ad23 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/RTCv1/rtc_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,15 +19,15 @@
*/
/**
- * @file STM32/RTCv1/rtc_lld.h
- * @brief STM32F1xx RTC subsystem low level driver header.
+ * @file RTCv1/hal_rtc_lld.h
+ * @brief STM32 RTC subsystem low level driver header.
*
* @addtogroup RTC
* @{
*/
-#ifndef _RTC_LLD_H_
-#define _RTC_LLD_H_
+#ifndef HAL_RTC_LLD_H
+#define HAL_RTC_LLD_H
#if HAL_USE_RTC || defined(__DOXYGEN__)
@@ -35,6 +35,9 @@
/* Driver constants. */
/*===========================================================================*/
+/**
+ * @name Implementation capabilities
+ */
/**
* @brief This RTC implementation supports callbacks.
*/
@@ -45,6 +48,12 @@
*/
#define RTC_ALARMS 1
+/**
+ * @brief Presence of a local persistent storage.
+ */
+#define RTC_HAS_STORAGE FALSE
+/** @} */
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -76,14 +85,15 @@
/*===========================================================================*/
/**
- * @brief Type of a structure representing an RTC alarm time stamp.
+ * @brief FileStream specific methods.
*/
-typedef struct RTCAlarm RTCAlarm;
+#define _rtc_driver_methods \
+ _file_stream_methods
/**
- * @brief Type of a structure representing an RTC callbacks config.
+ * @brief Type of a structure representing an RTC alarm time stamp.
*/
-typedef struct RTCCallbackConfig RTCCallbackConfig;
+typedef struct RTCAlarm RTCAlarm;
/**
* @brief Type of an RTC alarm.
@@ -106,45 +116,42 @@ typedef enum {
typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event);
/**
- * @brief Structure representing an RTC callbacks config.
- */
-struct RTCCallbackConfig{
- /**
- * @brief Generic RTC callback pointer.
- */
- rtccb_t callback;
-};
-
-/**
- * @brief Structure representing an RTC time stamp.
+ * @brief Structure representing an RTC alarm time stamp.
*/
-struct RTCTime {
+struct RTCAlarm {
/**
* @brief Seconds since UNIX epoch.
*/
- uint32_t tv_sec;
- /**
- * @brief Fractional part.
- */
- uint32_t tv_msec;
+ uint32_t tv_sec;
};
+#if RTC_HAS_STORAGE || defined(__DOXYGEN__)
/**
- * @brief Structure representing an RTC alarm time stamp.
+ * @extends FileStream
+ *
+ * @brief @p RTCDriver virtual methods table.
*/
-struct RTCAlarm {
- /**
- * @brief Seconds since UNIX epoch.
- */
- uint32_t tv_sec;
+struct RTCDriverVMT {
+ _rtc_driver_methods
};
+#endif
/**
* @brief Structure representing an RTC driver.
*/
struct RTCDriver{
+#if RTC_HAS_STORAGE || defined(__DOXYGEN__)
/**
- * @brief Callback pointer.
+ * @brief Virtual Methods Table.
+ */
+ const struct RTCDriverVMT *vmt;
+#endif
+ /**
+ * @brief Pointer to the RTC registers block.
+ */
+ RTC_TypeDef *rtc;
+ /**
+ * @brief Callback pointer.
*/
rtccb_t callback;
};
@@ -159,6 +166,9 @@ struct RTCDriver{
#if !defined(__DOXYGEN__)
extern RTCDriver RTCD1;
+#if RTC_HAS_STORAGE
+extern struct RTCDriverVMT _rtc_lld_vmt;
+#endif
#endif
#ifdef __cplusplus
@@ -166,22 +176,23 @@ extern "C" {
#endif
void rtc_lld_set_prescaler(void);
void rtc_lld_init(void);
- void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec);
- void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec);
+ void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec);
+ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec);
void rtc_lld_set_alarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
+ rtcalarm_t alarm_number,
const RTCAlarm *alarmspec);
void rtc_lld_get_alarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
+ rtcalarm_t alarm_number,
RTCAlarm *alarmspec);
void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback);
- uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp);
+ void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec);
+ void rtcSTM32SetSec(RTCDriver *rtcp, uint32_t tv_sec);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_RTC */
-#endif /* _RTC_LLD_H_ */
+#endif /* HAL_RTC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/driver.mk
new file mode 100644
index 0000000000..720f4d331e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c
new file mode 100644
index 0000000000..21f50cf404
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c
@@ -0,0 +1,558 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file RTCv2/hal_rtc_lld.c
+ * @brief STM32 RTC low level driver.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_RTC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define RTC_TR_PM_OFFSET 22
+#define RTC_TR_HT_OFFSET 20
+#define RTC_TR_HU_OFFSET 16
+#define RTC_TR_MNT_OFFSET 12
+#define RTC_TR_MNU_OFFSET 8
+#define RTC_TR_ST_OFFSET 4
+#define RTC_TR_SU_OFFSET 0
+
+#define RTC_DR_YT_OFFSET 20
+#define RTC_DR_YU_OFFSET 16
+#define RTC_DR_WDU_OFFSET 13
+#define RTC_DR_MT_OFFSET 12
+#define RTC_DR_MU_OFFSET 8
+#define RTC_DR_DT_OFFSET 4
+#define RTC_DR_DU_OFFSET 0
+
+#define RTC_CR_BKP_OFFSET 18
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief RTC driver identifier.
+ */
+RTCDriver RTCD1;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Beginning of configuration procedure.
+ *
+ * @notapi
+ */
+static void rtc_enter_init(void) {
+
+ RTCD1.rtc->ISR |= RTC_ISR_INIT;
+ while ((RTCD1.rtc->ISR & RTC_ISR_INITF) == 0)
+ ;
+}
+
+/**
+ * @brief Finalizing of configuration procedure.
+ *
+ * @notapi
+ */
+static inline void rtc_exit_init(void) {
+
+ RTCD1.rtc->ISR &= ~RTC_ISR_INIT;
+}
+
+/**
+ * @brief Converts time from TR register encoding to timespec.
+ *
+ * @param[in] tr TR register value
+ * @param[out] timespec pointer to a @p RTCDateTime structure
+ *
+ * @notapi
+ */
+static void rtc_decode_time(uint32_t tr, RTCDateTime *timespec) {
+ uint32_t n;
+
+ n = ((tr >> RTC_TR_HT_OFFSET) & 3) * 36000000;
+ n += ((tr >> RTC_TR_HU_OFFSET) & 15) * 3600000;
+ n += ((tr >> RTC_TR_MNT_OFFSET) & 7) * 600000;
+ n += ((tr >> RTC_TR_MNU_OFFSET) & 15) * 60000;
+ n += ((tr >> RTC_TR_ST_OFFSET) & 7) * 10000;
+ n += ((tr >> RTC_TR_SU_OFFSET) & 15) * 1000;
+ timespec->millisecond = n;
+}
+
+/**
+ * @brief Converts date from DR register encoding to timespec.
+ *
+ * @param[in] dr DR register value
+ * @param[out] timespec pointer to a @p RTCDateTime structure
+ *
+ * @notapi
+ */
+static void rtc_decode_date(uint32_t dr, RTCDateTime *timespec) {
+
+ timespec->year = (((dr >> RTC_DR_YT_OFFSET) & 15) * 10) +
+ ((dr >> RTC_DR_YU_OFFSET) & 15);
+ timespec->month = (((dr >> RTC_TR_MNT_OFFSET) & 1) * 10) +
+ ((dr >> RTC_TR_MNU_OFFSET) & 15);
+ timespec->day = (((dr >> RTC_DR_DT_OFFSET) & 3) * 10) +
+ ((dr >> RTC_DR_DU_OFFSET) & 15);
+ timespec->dayofweek = (dr >> RTC_DR_WDU_OFFSET) & 7;
+}
+
+/**
+ * @brief Converts time from timespec to TR register encoding.
+ *
+ * @param[in] timespec pointer to a @p RTCDateTime structure
+ * @return the TR register encoding.
+ *
+ * @notapi
+ */
+static uint32_t rtc_encode_time(const RTCDateTime *timespec) {
+ uint32_t n, tr = 0;
+
+ /* Subseconds cannot be set.*/
+ n = timespec->millisecond / 1000;
+
+ /* Seconds conversion.*/
+ tr = tr | ((n % 10) << RTC_TR_SU_OFFSET);
+ n /= 10;
+ tr = tr | ((n % 6) << RTC_TR_ST_OFFSET);
+ n /= 6;
+
+ /* Minutes conversion.*/
+ tr = tr | ((n % 10) << RTC_TR_MNU_OFFSET);
+ n /= 10;
+ tr = tr | ((n % 6) << RTC_TR_MNT_OFFSET);
+ n /= 6;
+
+ /* Hours conversion.*/
+ tr = tr | ((n % 10) << RTC_TR_HU_OFFSET);
+ n /= 10;
+ tr = tr | (n << RTC_TR_HT_OFFSET);
+
+ return tr;
+}
+
+/**
+ * @brief Converts a date from timespec to DR register encoding.
+ *
+ * @param[in] timespec pointer to a @p RTCDateTime structure
+ * @return the DR register encoding.
+ *
+ * @notapi
+ */
+static uint32_t rtc_encode_date(const RTCDateTime *timespec) {
+ uint32_t n, dr = 0;
+
+ /* Year conversion. Note, only years last two digits are considered.*/
+ n = timespec->year;
+ dr = dr | ((n % 10) << RTC_DR_YU_OFFSET);
+ n /= 10;
+ dr = dr | ((n % 10) << RTC_DR_YT_OFFSET);
+
+ /* Months conversion.*/
+ n = timespec->month;
+ dr = dr | ((n % 10) << RTC_DR_MU_OFFSET);
+ n /= 10;
+ dr = dr | ((n % 10) << RTC_DR_MT_OFFSET);
+
+ /* Days conversion.*/
+ n = timespec->day;
+ dr = dr | ((n % 10) << RTC_DR_DU_OFFSET);
+ n /= 10;
+ dr = dr | ((n % 10) << RTC_DR_DT_OFFSET);
+
+ /* Days of week conversion.*/
+ dr = dr | (timespec->dayofweek << RTC_DR_WDU_OFFSET);
+
+ return dr;
+}
+
+#if RTC_HAS_STORAGE
+/* TODO: Map on the backup SRAM on devices that have it.*/
+static size_t _write(void *instance, const uint8_t *bp, size_t n) {
+
+ (void)instance;
+ (void)bp;
+ (void)n;
+
+ return 0;
+}
+
+static size_t _read(void *instance, uint8_t *bp, size_t n) {
+
+ (void)instance;
+ (void)bp;
+ (void)n;
+
+ return 0;
+}
+
+static msg_t _put(void *instance, uint8_t b) {
+
+ (void)instance;
+ (void)b;
+
+ return FILE_OK;
+}
+
+static msg_t _get(void *instance) {
+
+ (void)instance;
+
+ return FILE_OK;
+}
+
+static msg_t _close(void *instance) {
+
+ /* Close is not supported.*/
+ (void)instance;
+
+ return FILE_OK;
+}
+
+static msg_t _geterror(void *instance) {
+
+ (void)instance;
+
+ return (msg_t)0;
+}
+
+static msg_t _getsize(void *instance) {
+
+ (void)instance;
+
+ return 0;
+}
+
+static msg_t _getposition(void *instance) {
+
+ (void)instance;
+
+ return 0;
+}
+
+static msg_t _lseek(void *instance, fileoffset_t offset) {
+
+ (void)instance;
+ (void)offset;
+
+ return FILE_OK;
+}
+
+/**
+ * @brief VMT for the RTC storage file interface.
+ */
+struct RTCDriverVMT _rtc_lld_vmt = {
+ _write, _read, _put, _get,
+ _close, _geterror, _getsize, _getposition, _lseek
+};
+#endif /* RTC_HAS_STORAGE */
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enable access to registers.
+ *
+ * @notapi
+ */
+void rtc_lld_init(void) {
+
+ /* RTC object initialization.*/
+ rtcObjectInit(&RTCD1);
+
+ /* RTC pointer initialization.*/
+ RTCD1.rtc = RTC;
+
+ /* Disable write protection. */
+ RTCD1.rtc->WPR = 0xCA;
+ RTCD1.rtc->WPR = 0x53;
+
+ /* If calendar has not been initialized yet then proceed with the
+ initial setup.*/
+ if (!(RTCD1.rtc->ISR & RTC_ISR_INITS)) {
+
+ rtc_enter_init();
+
+ RTCD1.rtc->CR = 0;
+ RTCD1.rtc->ISR = RTC_ISR_INIT; /* Clearing all but RTC_ISR_INIT. */
+ RTCD1.rtc->PRER = STM32_RTC_PRER_BITS;
+ RTCD1.rtc->PRER = STM32_RTC_PRER_BITS;
+
+ rtc_exit_init();
+ }
+ else
+ RTCD1.rtc->ISR &= ~RTC_ISR_RSF;
+}
+
+/**
+ * @brief Set current time.
+ * @note Fractional part will be silently ignored. There is no possibility
+ * to set it on STM32 platform.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] timespec pointer to a @p RTCDateTime structure
+ *
+ * @notapi
+ */
+void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) {
+ uint32_t dr, tr;
+ syssts_t sts;
+
+ tr = rtc_encode_time(timespec);
+ dr = rtc_encode_date(timespec);
+
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
+
+ /* Writing the registers.*/
+ rtc_enter_init();
+ rtcp->rtc->TR = tr;
+ rtcp->rtc->DR = dr;
+ rtcp->rtc->CR = (rtcp->rtc->CR & ~(1U << RTC_CR_BKP_OFFSET)) |
+ (timespec->dstflag << RTC_CR_BKP_OFFSET);
+ rtc_exit_init();
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
+}
+
+/**
+ * @brief Get current time.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[out] timespec pointer to a @p RTCDateTime structure
+ *
+ * @notapi
+ */
+void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) {
+ uint32_t dr, tr, cr;
+ uint32_t subs;
+#if STM32_RTC_HAS_SUBSECONDS
+ uint32_t ssr;
+#endif /* STM32_RTC_HAS_SUBSECONDS */
+ syssts_t sts;
+
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
+
+ /* Synchronization with the RTC and reading the registers, note
+ DR must be read last.*/
+ while ((rtcp->rtc->ISR & RTC_ISR_RSF) == 0)
+ ;
+#if STM32_RTC_HAS_SUBSECONDS
+ ssr = rtcp->rtc->SSR;
+#endif /* STM32_RTC_HAS_SUBSECONDS */
+ tr = rtcp->rtc->TR;
+ dr = rtcp->rtc->DR;
+ cr = rtcp->rtc->CR;
+ rtcp->rtc->ISR &= ~RTC_ISR_RSF;
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
+
+ /* Decoding day time, this starts the atomic read sequence, see "Reading
+ the calendar" in the RTC documentation.*/
+ rtc_decode_time(tr, timespec);
+
+ /* If the RTC is capable of sub-second counting then the value is
+ normalized in milliseconds and added to the time.*/
+#if STM32_RTC_HAS_SUBSECONDS
+ subs = (((STM32_RTC_PRESS_VALUE - 1U) - ssr) * 1000U) / STM32_RTC_PRESS_VALUE;
+#else
+ subs = 0;
+#endif /* STM32_RTC_HAS_SUBSECONDS */
+ timespec->millisecond += subs;
+
+ /* Decoding date, this concludes the atomic read sequence.*/
+ rtc_decode_date(dr, timespec);
+
+ /* Retrieving the DST bit.*/
+ timespec->dstflag = (cr >> RTC_CR_BKP_OFFSET) & 1;
+}
+
+#if (RTC_ALARMS > 0) || defined(__DOXYGEN__)
+/**
+ * @brief Set alarm time.
+ * @note Default value after BKP domain reset for both comparators is 0.
+ * @note Function does not performs any checks of alarm time validity.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure.
+ * @param[in] alarm alarm identifier. Can be 1 or 2.
+ * @param[in] alarmspec pointer to a @p RTCAlarm structure.
+ *
+ * @notapi
+ */
+void rtc_lld_set_alarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ const RTCAlarm *alarmspec) {
+ syssts_t sts;
+
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
+
+ if (alarm == 0) {
+ if (alarmspec != NULL) {
+ rtcp->rtc->CR &= ~RTC_CR_ALRAE;
+ while (!(rtcp->rtc->ISR & RTC_ISR_ALRAWF))
+ ;
+ rtcp->rtc->ALRMAR = alarmspec->alrmr;
+ rtcp->rtc->CR |= RTC_CR_ALRAE;
+ rtcp->rtc->CR |= RTC_CR_ALRAIE;
+ }
+ else {
+ rtcp->rtc->CR &= ~RTC_CR_ALRAIE;
+ rtcp->rtc->CR &= ~RTC_CR_ALRAE;
+ }
+ }
+#if RTC_ALARMS > 1
+ else {
+ if (alarmspec != NULL) {
+ rtcp->rtc->CR &= ~RTC_CR_ALRBE;
+ while (!(rtcp->rtc->ISR & RTC_ISR_ALRBWF))
+ ;
+ rtcp->rtc->ALRMBR = alarmspec->alrmr;
+ rtcp->rtc->CR |= RTC_CR_ALRBE;
+ rtcp->rtc->CR |= RTC_CR_ALRBIE;
+ }
+ else {
+ rtcp->rtc->CR &= ~RTC_CR_ALRBIE;
+ rtcp->rtc->CR &= ~RTC_CR_ALRBE;
+ }
+ }
+#endif /* RTC_ALARMS > 1 */
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
+}
+
+/**
+ * @brief Get alarm time.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] alarm alarm identifier
+ * @param[out] alarmspec pointer to a @p RTCAlarm structure
+ *
+ * @notapi
+ */
+void rtc_lld_get_alarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ RTCAlarm *alarmspec) {
+
+ if (alarm == 0)
+ alarmspec->alrmr = rtcp->rtc->ALRMAR;
+#if RTC_ALARMS > 1
+ else
+ alarmspec->alrmr = rtcp->rtc->ALRMBR;
+#endif /* RTC_ALARMS > 1 */
+}
+#endif /* RTC_ALARMS > 0 */
+
+#if STM32_RTC_HAS_PERIODIC_WAKEUPS || defined(__DOXYGEN__)
+/**
+ * @brief Sets time of periodic wakeup.
+ * @note Default value after BKP domain reset is 0x0000FFFF
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] wakeupspec pointer to a @p RTCWakeup structure
+ *
+ * @api
+ */
+void rtcSTM32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec) {
+ syssts_t sts;
+
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
+
+ if (wakeupspec != NULL) {
+ osalDbgCheck(wakeupspec->wutr != 0x30000);
+
+ rtcp->rtc->CR &= ~RTC_CR_WUTE;
+ rtcp->rtc->CR &= ~RTC_CR_WUTIE;
+ while (!(rtcp->rtc->ISR & RTC_ISR_WUTWF))
+ ;
+ rtcp->rtc->WUTR = wakeupspec->wutr & 0xFFFF;
+ rtcp->rtc->CR &= ~RTC_CR_WUCKSEL;
+ rtcp->rtc->CR |= (wakeupspec->wutr >> 16) & RTC_CR_WUCKSEL;
+ rtcp->rtc->CR |= RTC_CR_WUTIE;
+ rtcp->rtc->CR |= RTC_CR_WUTE;
+ }
+ else {
+ rtcp->rtc->CR &= ~RTC_CR_WUTE;
+ rtcp->rtc->CR &= ~RTC_CR_WUTIE;
+ }
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
+}
+
+/**
+ * @brief Gets time of periodic wakeup.
+ * @note Default value after BKP domain reset is 0x0000FFFF
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[out] wakeupspec pointer to a @p RTCWakeup structure
+ *
+ * @api
+ */
+void rtcSTM32GetPeriodicWakeup(RTCDriver *rtcp, RTCWakeup *wakeupspec) {
+ syssts_t sts;
+
+ /* Entering a reentrant critical zone.*/
+ sts = osalSysGetStatusAndLockX();
+
+ wakeupspec->wutr = 0;
+ wakeupspec->wutr |= rtcp->rtc->WUTR;
+ wakeupspec->wutr |= (((uint32_t)rtcp->rtc->CR) & 0x7) << 16;
+
+ /* Leaving a reentrant critical zone.*/
+ osalSysRestoreStatusX(sts);
+}
+#endif /* STM32_RTC_HAS_PERIODIC_WAKEUPS */
+
+#endif /* HAL_USE_RTC */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.h
new file mode 100644
index 0000000000..818597c480
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.h
@@ -0,0 +1,238 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file RTCv2/hal_rtc_lld.h
+ * @brief STM32 RTC low level driver header.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#ifndef HAL_RTC_LLD_H
+#define HAL_RTC_LLD_H
+
+#if HAL_USE_RTC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Implementation capabilities
+ */
+/**
+ * @brief Callback support int the driver.
+ */
+#define RTC_SUPPORTS_CALLBACKS STM32_RTC_HAS_INTERRUPTS
+
+/**
+ * @brief Number of alarms available.
+ */
+#define RTC_ALARMS STM32_RTC_NUM_ALARMS
+
+/**
+ * @brief Presence of a local persistent storage.
+ */
+#define RTC_HAS_STORAGE FALSE
+/** @} */
+
+/**
+ * @brief RTC PRER register initializer.
+ */
+#define RTC_PRER(a, s) ((((a) - 1) << 16) | ((s) - 1))
+
+/**
+ * @name Alarm helper macros
+ * @{
+ */
+#define RTC_ALRM_MSK4 (1U << 31)
+#define RTC_ALRM_WDSEL (1U << 30)
+#define RTC_ALRM_DT(n) ((n) << 28)
+#define RTC_ALRM_DU(n) ((n) << 24)
+#define RTC_ALRM_MSK3 (1U << 23)
+#define RTC_ALRM_HT(n) ((n) << 20)
+#define RTC_ALRM_HU(n) ((n) << 16)
+#define RTC_ALRM_MSK2 (1U << 15)
+#define RTC_ALRM_MNT(n) ((n) << 12)
+#define RTC_ALRM_MNU(n) ((n) << 8)
+#define RTC_ALRM_MSK1 (1U << 7)
+#define RTC_ALRM_ST(n) ((n) << 4)
+#define RTC_ALRM_SU(n) ((n) << 0)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief RTC PRES register initialization.
+ * @note The default is calculated for a 32768Hz clock.
+ */
+#if !defined(STM32_RTC_PRESA_VALUE) || defined(__DOXYGEN__)
+#define STM32_RTC_PRESA_VALUE 32
+#endif
+
+/**
+ * @brief RTC PRESS divider initialization.
+ * @note The default is calculated for a 32768Hz clock.
+ */
+#if !defined(STM32_RTC_PRESS_VALUE) || defined(__DOXYGEN__)
+#define STM32_RTC_PRESS_VALUE 1024
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if HAL_USE_RTC && !STM32_HAS_RTC
+#error "RTC not present in the selected device"
+#endif
+
+#if !(STM32_RTCSEL == STM32_RTCSEL_LSE) && \
+ !(STM32_RTCSEL == STM32_RTCSEL_LSI) && \
+ !(STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
+#error "invalid source selected for RTC clock"
+#endif
+
+#if STM32_PCLK1 < (STM32_RTCCLK * 7)
+#error "STM32_PCLK1 frequency is too low"
+#endif
+
+/**
+ * @brief Initialization for the RTC_PRER register.
+ */
+#define STM32_RTC_PRER_BITS RTC_PRER(STM32_RTC_PRESA_VALUE, \
+ STM32_RTC_PRESS_VALUE)
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief FileStream specific methods.
+ */
+#define _rtc_driver_methods \
+ _file_stream_methods
+
+/**
+ * @brief Type of an RTC alarm number.
+ */
+typedef uint32_t rtcalarm_t;
+
+/**
+ * @brief Type of a structure representing an RTC alarm time stamp.
+ */
+typedef struct {
+ /**
+ * @brief Type of an alarm as encoded in RTC ALRMxR registers.
+ */
+ uint32_t alrmr;
+} RTCAlarm;
+
+#if STM32_RTC_HAS_PERIODIC_WAKEUPS
+/**
+ * @brief Type of a wakeup as encoded in RTC WUTR register.
+ */
+typedef struct {
+ /**
+ * @brief Wakeup as encoded in RTC WUTR register.
+ * @note ((WUTR == 0) || (WUCKSEL == 3)) are a forbidden combination.
+ * @note Bits 16..18 are copied in the CR bits 0..2 (WUCKSEL).
+ */
+ uint32_t wutr;
+} RTCWakeup;
+#endif
+
+#if RTC_HAS_STORAGE || defined(__DOXYGEN__)
+/**
+ * @extends FileStream
+ *
+ * @brief @p RTCDriver virtual methods table.
+ */
+struct RTCDriverVMT {
+ _rtc_driver_methods
+};
+#endif
+
+/**
+ * @brief Structure representing an RTC driver.
+ */
+struct RTCDriver {
+#if RTC_HAS_STORAGE || defined(__DOXYGEN__)
+ /**
+ * @brief Virtual Methods Table.
+ */
+ const struct RTCDriverVMT *vmt;
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the RTC registers block.
+ */
+ RTC_TypeDef *rtc;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern RTCDriver RTCD1;
+#if RTC_HAS_STORAGE
+extern struct RTCDriverVMT _rtc_lld_vmt;
+#endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void rtc_lld_init(void);
+ void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec);
+ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec);
+#if RTC_ALARMS > 0
+ void rtc_lld_set_alarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ const RTCAlarm *alarmspec);
+ void rtc_lld_get_alarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ RTCAlarm *alarmspec);
+#endif
+#if STM32_RTC_HAS_PERIODIC_WAKEUPS
+ void rtcSTM32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec);
+ void rtcSTM32GetPeriodicWakeup(RTCDriver *rtcp, RTCWakeup *wakeupspec);
+#endif /* STM32_RTC_HAS_PERIODIC_WAKEUPS */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_RTC */
+
+#endif /* HAL_RTC_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/driver.mk
new file mode 100644
index 0000000000..1a1a4bde73
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/sdc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
similarity index 55%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/sdc_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
index 483d277ff6..6088e0c1a4 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/sdc_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,20 +15,15 @@
*/
/**
- * @file STM32/sdc_lld.c
+ * @file SDIOv1/hal_sdc_lld.c
* @brief STM32 SDC subsystem low level driver source.
*
* @addtogroup SDC
* @{
*/
-/*
- TODO: Try preerase blocks before writing (ACMD23).
- */
-
#include
-#include "ch.h"
#include "hal.h"
#if HAL_USE_SDC || defined(__DOXYGEN__)
@@ -62,10 +57,66 @@ static union {
} u;
#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+/**
+ * @brief SDIO default configuration.
+ */
+static const SDCConfig sdc_default_cfg = {
+ NULL,
+ SDC_MODE_4BIT
+};
+
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
+/**
+ * @brief Prepares to handle read transaction.
+ * @details Designed for read special registers from card.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[out] buf pointer to the read buffer
+ * @param[in] bytes number of bytes to read
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_lld_prepare_read_bytes(SDCDriver *sdcp,
+ uint8_t *buf, uint32_t bytes) {
+ osalDbgCheck(bytes < 0x1000000);
+
+ sdcp->sdio->DTIMER = STM32_SDC_READ_TIMEOUT;
+
+ /* Checks for errors and waits for the card to be ready for reading.*/
+ if (_sdc_wait_for_transfer_state(sdcp))
+ return HAL_FAILED;
+
+ /* Prepares the DMA channel for writing.*/
+ dmaStreamSetMemory0(sdcp->dma, buf);
+ dmaStreamSetTransactionSize(sdcp->dma, bytes / sizeof (uint32_t));
+ dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M);
+ dmaStreamEnable(sdcp->dma);
+
+ /* Setting up data transfer.*/
+ sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS;
+ sdcp->sdio->MASK = SDIO_MASK_DCRCFAILIE |
+ SDIO_MASK_DTIMEOUTIE |
+ SDIO_MASK_STBITERRIE |
+ SDIO_MASK_RXOVERRIE |
+ SDIO_MASK_DATAENDIE;
+ sdcp->sdio->DLEN = bytes;
+
+ /* Transaction starts just after DTEN bit setting.*/
+ sdcp->sdio->DCTRL = SDIO_DCTRL_DTDIR |
+ SDIO_DCTRL_DTMODE | /* multibyte data transfer */
+ SDIO_DCTRL_DMAEN |
+ SDIO_DCTRL_DTEN;
+
+ return HAL_SUCCESS;
+}
+
/**
* @brief Prepares card to handle read transaction.
*
@@ -75,13 +126,13 @@ static union {
* @param[in] resp pointer to the response buffer
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
- uint32_t n, uint32_t *resp) {
+static bool sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
+ uint32_t n, uint32_t *resp) {
/* Driver handles data in 512 bytes blocks (just like HC cards). But if we
have not HC card than we must convert address from blocks to bytes.*/
@@ -92,16 +143,16 @@ static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
/* Send read multiple blocks command to card.*/
if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK,
startblk, resp) || MMCSD_R1_ERROR(resp[0]))
- return CH_FAILED;
+ return HAL_FAILED;
}
- else{
+ else {
/* Send read single block command.*/
if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK,
startblk, resp) || MMCSD_R1_ERROR(resp[0]))
- return CH_FAILED;
+ return HAL_FAILED;
}
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -113,13 +164,13 @@ static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
* @param[in] resp pointer to the response buffer
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
- uint32_t n, uint32_t *resp) {
+static bool sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
+ uint32_t n, uint32_t *resp) {
/* Driver handles data in 512 bytes blocks (just like HC cards). But if we
have not HC card than we must convert address from blocks to bytes.*/
@@ -130,16 +181,16 @@ static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
/* Write multiple blocks command.*/
if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK,
startblk, resp) || MMCSD_R1_ERROR(resp[0]))
- return CH_FAILED;
+ return HAL_FAILED;
}
- else{
+ else {
/* Write single block command.*/
if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK,
startblk, resp) || MMCSD_R1_ERROR(resp[0]))
- return CH_FAILED;
+ return HAL_FAILED;
}
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -150,26 +201,20 @@ static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
* @param[in] resp pointer to the response buffer
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*/
-static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
- uint32_t *resp) {
+static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
+ uint32_t *resp) {
/* Note the mask is checked before going to sleep because the interrupt
may have occurred before reaching the critical zone.*/
- chSysLock();
- if (SDIO->MASK != 0) {
- chDbgAssert(sdcp->thread == NULL,
- "sdc_lld_start_data_transaction(), #1", "not NULL");
- sdcp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- chDbgAssert(sdcp->thread == NULL,
- "sdc_lld_start_data_transaction(), #2", "not NULL");
- }
- if ((SDIO->STA & SDIO_STA_DATAEND) == 0) {
- chSysUnlock();
- return CH_FAILED;
+ osalSysLock();
+ if (sdcp->sdio->MASK != 0)
+ osalThreadSuspendS(&sdcp->thread);
+ if ((sdcp->sdio->STA & SDIO_STA_DATAEND) == 0) {
+ osalSysUnlock();
+ return HAL_FAILED;
}
#if (defined(STM32F4XX) || defined(STM32F2XX))
@@ -180,28 +225,28 @@ static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
/* DMA event flags must be manually cleared.*/
dmaStreamClearInterrupt(sdcp->dma);
- SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
- SDIO->DCTRL = 0;
- chSysUnlock();
+ sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS;
+ sdcp->sdio->DCTRL = 0;
+ osalSysUnlock();
/* Wait until interrupt flags to be cleared.*/
/*while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF)
dmaStreamClearInterrupt(sdcp->dma);*/
#else
- /* Waits for transfer completion at DMA level, the the stream is
+ /* Waits for transfer completion at DMA level, then the stream is
disabled and cleared.*/
dmaWaitCompletion(sdcp->dma);
- SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
- SDIO->DCTRL = 0;
- chSysUnlock();
+ sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS;
+ sdcp->sdio->DCTRL = 0;
+ osalSysUnlock();
#endif
/* Finalize transaction.*/
if (n > 1)
return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -245,13 +290,13 @@ static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) {
static void sdc_lld_error_cleanup(SDCDriver *sdcp,
uint32_t n,
uint32_t *resp) {
- uint32_t sta = SDIO->STA;
+ uint32_t sta = sdcp->sdio->STA;
dmaStreamClearInterrupt(sdcp->dma);
dmaStreamDisable(sdcp->dma);
- SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
- SDIO->MASK = 0;
- SDIO->DCTRL = 0;
+ sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS;
+ sdcp->sdio->MASK = 0;
+ sdcp->sdio->DCTRL = 0;
sdc_lld_collect_errors(sdcp, sta);
if (n > 1)
sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
@@ -271,24 +316,21 @@ static void sdc_lld_error_cleanup(SDCDriver *sdcp,
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_SDIO_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_SDIO_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- chSysLockFromIsr()
+ osalSysLockFromISR();
/* Disables the source but the status flags are not reset because the
read/write functions needs to check them.*/
SDIO->MASK = 0;
- if (SDCD1.thread != NULL) {
- chSchReadyI(SDCD1.thread);
- SDCD1.thread = NULL;
- }
+ osalThreadResumeI(&SDCD1.thread, MSG_OK);
- chSysUnlockFromIsr();
+ osalSysUnlockFromISR();
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
@@ -305,9 +347,7 @@ void sdc_lld_init(void) {
sdcObjectInit(&SDCD1);
SDCD1.thread = NULL;
SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM);
-#if CH_DBG_ENABLE_ASSERTS
SDCD1.sdio = SDIO;
-#endif
}
/**
@@ -319,6 +359,11 @@ void sdc_lld_init(void) {
*/
void sdc_lld_start(SDCDriver *sdcp) {
+ /* Checking configuration, using a default if NULL has been passed.*/
+ if (sdcp->config == NULL) {
+ sdcp->config = &sdc_default_cfg;
+ }
+
sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_WORD |
@@ -333,23 +378,22 @@ void sdc_lld_start(SDCDriver *sdcp) {
if (sdcp->state == BLK_STOP) {
/* Note, the DMA must be enabled before the IRQs.*/
- bool_t b;
+ bool b;
b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL);
- chDbgAssert(!b, "sdc_lld_start(), #1", "stream already allocated");
- dmaStreamSetPeripheral(sdcp->dma, &SDIO->FIFO);
+ osalDbgAssert(!b, "stream already allocated");
+ dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdio->FIFO);
#if (defined(STM32F4XX) || defined(STM32F2XX))
dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL);
#endif
- nvicEnableVector(STM32_SDIO_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY));
+ nvicEnableVector(STM32_SDIO_NUMBER, STM32_SDC_SDIO_IRQ_PRIORITY);
rccEnableSDIO(FALSE);
}
/* Configuration, card clock is initially stopped.*/
- SDIO->POWER = 0;
- SDIO->CLKCR = 0;
- SDIO->DCTRL = 0;
- SDIO->DTIMER = 0;
+ sdcp->sdio->POWER = 0;
+ sdcp->sdio->CLKCR = 0;
+ sdcp->sdio->DCTRL = 0;
+ sdcp->sdio->DTIMER = 0;
}
/**
@@ -364,10 +408,10 @@ void sdc_lld_stop(SDCDriver *sdcp) {
if (sdcp->state != BLK_STOP) {
/* SDIO deactivation.*/
- SDIO->POWER = 0;
- SDIO->CLKCR = 0;
- SDIO->DCTRL = 0;
- SDIO->DTIMER = 0;
+ sdcp->sdio->POWER = 0;
+ sdcp->sdio->CLKCR = 0;
+ sdcp->sdio->DCTRL = 0;
+ sdcp->sdio->DTIMER = 0;
/* Clock deactivation.*/
nvicDisableVector(STM32_SDIO_NUMBER);
@@ -385,29 +429,36 @@ void sdc_lld_stop(SDCDriver *sdcp) {
*/
void sdc_lld_start_clk(SDCDriver *sdcp) {
- (void)sdcp;
-
/* Initial clock setting: 400kHz, 1bit mode.*/
- SDIO->CLKCR = STM32_SDIO_DIV_LS;
- SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;
- SDIO->CLKCR |= SDIO_CLKCR_CLKEN;
+ sdcp->sdio->CLKCR = STM32_SDIO_DIV_LS;
+ sdcp->sdio->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;
+ sdcp->sdio->CLKCR |= SDIO_CLKCR_CLKEN;
/* Clock activation delay.*/
- chThdSleepMilliseconds(STM32_SDC_CLOCK_ACTIVATION_DELAY);
+ osalThreadSleep(OSAL_MS2ST(STM32_SDC_CLOCK_ACTIVATION_DELAY));
}
/**
* @brief Sets the SDIO clock to data mode (25MHz or less).
*
* @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] clk the clock mode
*
* @notapi
*/
-void sdc_lld_set_data_clk(SDCDriver *sdcp) {
-
- (void)sdcp;
+void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
+#if 0
+ if (SDC_CLK_50MHz == clk) {
+ sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS
+ | SDIO_CLKCR_BYPASS;
+ }
+ else
+ sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS;
+#else
+ (void)clk;
- SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS;
+ sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS;
+#endif
}
/**
@@ -419,10 +470,8 @@ void sdc_lld_set_data_clk(SDCDriver *sdcp) {
*/
void sdc_lld_stop_clk(SDCDriver *sdcp) {
- (void)sdcp;
-
- SDIO->CLKCR = 0;
- SDIO->POWER = 0;
+ sdcp->sdio->CLKCR = 0;
+ sdcp->sdio->POWER = 0;
}
/**
@@ -434,19 +483,17 @@ void sdc_lld_stop_clk(SDCDriver *sdcp) {
* @notapi
*/
void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
- uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS;
-
- (void)sdcp;
+ uint32_t clk = sdcp->sdio->CLKCR & ~SDIO_CLKCR_WIDBUS;
switch (mode) {
case SDC_MODE_1BIT:
- SDIO->CLKCR = clk;
+ sdcp->sdio->CLKCR = clk;
break;
case SDC_MODE_4BIT:
- SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0;
+ sdcp->sdio->CLKCR = clk | SDIO_CLKCR_WIDBUS_0;
break;
case SDC_MODE_8BIT:
- SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1;
+ sdcp->sdio->CLKCR = clk | SDIO_CLKCR_WIDBUS_1;
break;
}
}
@@ -462,13 +509,11 @@ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
*/
void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
- (void)sdcp;
-
- SDIO->ARG = arg;
- SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN;
- while ((SDIO->STA & SDIO_STA_CMDSENT) == 0)
+ sdcp->sdio->ARG = arg;
+ sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN;
+ while ((sdcp->sdio->STA & SDIO_STA_CMDSENT) == 0)
;
- SDIO->ICR = SDIO_ICR_CMDSENTC;
+ sdcp->sdio->ICR = SDIO_ICR_CMDSENTC;
}
/**
@@ -481,29 +526,28 @@ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
* @param[out] resp pointer to the response buffer (one word)
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp) {
+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
uint32_t sta;
- (void)sdcp;
-
- SDIO->ARG = arg;
- SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN;
- while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
- SDIO_STA_CCRCFAIL)) == 0)
+ sdcp->sdio->ARG = arg;
+ sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN;
+ while (((sta = sdcp->sdio->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
+ SDIO_STA_CCRCFAIL)) == 0)
;
- SDIO->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL);
+ sdcp->sdio->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
+ SDIO_STA_CCRCFAIL);
if ((sta & (SDIO_STA_CTIMEOUT)) != 0) {
sdc_lld_collect_errors(sdcp, sta);
- return CH_FAILED;
+ return HAL_FAILED;
}
- *resp = SDIO->RESP1;
- return CH_SUCCESS;
+ *resp = sdcp->sdio->RESP1;
+ return HAL_SUCCESS;
}
/**
@@ -515,29 +559,27 @@ bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
* @param[out] resp pointer to the response buffer (one word)
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp) {
+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
uint32_t sta;
- (void)sdcp;
-
- SDIO->ARG = arg;
- SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN;
- while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
- SDIO_STA_CCRCFAIL)) == 0)
+ sdcp->sdio->ARG = arg;
+ sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN;
+ while (((sta = sdcp->sdio->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
+ SDIO_STA_CCRCFAIL)) == 0)
;
- SDIO->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL);
+ sdcp->sdio->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL);
if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) {
sdc_lld_collect_errors(sdcp, sta);
- return CH_FAILED;
+ return HAL_FAILED;
}
- *resp = SDIO->RESP1;
- return CH_SUCCESS;
+ *resp = sdcp->sdio->RESP1;
+ return HAL_SUCCESS;
}
/**
@@ -549,34 +591,72 @@ bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
* @param[out] resp pointer to the response buffer (four words)
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp) {
+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
uint32_t sta;
(void)sdcp;
- SDIO->ARG = arg;
- SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 |
- SDIO_CMD_CPSMEN;
- while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
- SDIO_STA_CCRCFAIL)) == 0)
+ sdcp->sdio->ARG = arg;
+ sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 |
+ SDIO_CMD_CPSMEN;
+ while (((sta = sdcp->sdio->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
+ SDIO_STA_CCRCFAIL)) == 0)
;
- SDIO->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL);
+ sdcp->sdio->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
+ SDIO_STA_CCRCFAIL);
if ((sta & (STM32_SDIO_STA_ERROR_MASK)) != 0) {
sdc_lld_collect_errors(sdcp, sta);
- return CH_FAILED;
+ return HAL_FAILED;
}
/* Save bytes in reverse order because MSB in response comes first.*/
- *resp++ = SDIO->RESP4;
- *resp++ = SDIO->RESP3;
- *resp++ = SDIO->RESP2;
- *resp = SDIO->RESP1;
- return CH_SUCCESS;
+ *resp++ = sdcp->sdio->RESP4;
+ *resp++ = sdcp->sdio->RESP3;
+ *resp++ = sdcp->sdio->RESP2;
+ *resp = sdcp->sdio->RESP1;
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Reads special registers using data bus.
+ * @details Needs only during card detection procedure.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[out] buf pointer to the read buffer
+ * @param[in] bytes number of bytes to read
+ * @param[in] cmd card command
+ * @param[in] arg argument for command
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t arg) {
+ uint32_t resp[1];
+
+ if(sdc_lld_prepare_read_bytes(sdcp, buf, bytes))
+ goto error;
+
+ if (sdc_lld_send_cmd_short_crc(sdcp, cmd, arg, resp)
+ || MMCSD_R1_ERROR(resp[0]))
+ goto error;
+
+ if (sdc_lld_wait_transaction_end(sdcp, 1, resp))
+ goto error;
+
+ return HAL_SUCCESS;
+
+error:
+ sdc_lld_error_cleanup(sdcp, 1, resp);
+ return HAL_FAILED;
}
/**
@@ -585,60 +665,60 @@ bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
* @param[in] sdcp pointer to the @p SDCDriver object
* @param[in] startblk first block to read
* @param[out] buf pointer to the read buffer
- * @param[in] n number of blocks to read
+ * @param[in] blocks number of blocks to read
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
- uint8_t *buf, uint32_t n) {
+bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t blocks) {
uint32_t resp[1];
- chDbgCheck((n < (0x1000000 / MMCSD_BLOCK_SIZE)), "max transaction size");
+ osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE);
- SDIO->DTIMER = STM32_SDC_READ_TIMEOUT;
+ sdcp->sdio->DTIMER = STM32_SDC_READ_TIMEOUT;
/* Checks for errors and waits for the card to be ready for reading.*/
if (_sdc_wait_for_transfer_state(sdcp))
- return CH_FAILED;
+ return HAL_FAILED;
/* Prepares the DMA channel for writing.*/
dmaStreamSetMemory0(sdcp->dma, buf);
dmaStreamSetTransactionSize(sdcp->dma,
- (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
+ (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M);
dmaStreamEnable(sdcp->dma);
/* Setting up data transfer.*/
- SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
- SDIO->MASK = SDIO_MASK_DCRCFAILIE |
- SDIO_MASK_DTIMEOUTIE |
- SDIO_MASK_STBITERRIE |
- SDIO_MASK_RXOVERRIE |
- SDIO_MASK_DATAENDIE;
- SDIO->DLEN = n * MMCSD_BLOCK_SIZE;
+ sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS;
+ sdcp->sdio->MASK = SDIO_MASK_DCRCFAILIE |
+ SDIO_MASK_DTIMEOUTIE |
+ SDIO_MASK_STBITERRIE |
+ SDIO_MASK_RXOVERRIE |
+ SDIO_MASK_DATAENDIE;
+ sdcp->sdio->DLEN = blocks * MMCSD_BLOCK_SIZE;
/* Transaction starts just after DTEN bit setting.*/
- SDIO->DCTRL = SDIO_DCTRL_DTDIR |
- SDIO_DCTRL_DBLOCKSIZE_3 |
- SDIO_DCTRL_DBLOCKSIZE_0 |
- SDIO_DCTRL_DMAEN |
- SDIO_DCTRL_DTEN;
+ sdcp->sdio->DCTRL = SDIO_DCTRL_DTDIR |
+ SDIO_DCTRL_DBLOCKSIZE_3 |
+ SDIO_DCTRL_DBLOCKSIZE_0 |
+ SDIO_DCTRL_DMAEN |
+ SDIO_DCTRL_DTEN;
- /* Talk to card what we want from it.*/
- if (sdc_lld_prepare_read(sdcp, startblk, n, resp) == TRUE)
+ if (sdc_lld_prepare_read(sdcp, startblk, blocks, resp) == TRUE)
goto error;
- if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE)
+
+ if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == TRUE)
goto error;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
error:
- sdc_lld_error_cleanup(sdcp, n, resp);
- return CH_FAILED;
+ sdc_lld_error_cleanup(sdcp, blocks, resp);
+ return HAL_FAILED;
}
/**
@@ -650,56 +730,57 @@ bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
* @param[in] n number of blocks to write
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
- const uint8_t *buf, uint32_t n) {
+bool sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t blocks) {
uint32_t resp[1];
- chDbgCheck((n < (0x1000000 / MMCSD_BLOCK_SIZE)), "max transaction size");
+ osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE);
- SDIO->DTIMER = STM32_SDC_WRITE_TIMEOUT;
+ sdcp->sdio->DTIMER = STM32_SDC_WRITE_TIMEOUT;
/* Checks for errors and waits for the card to be ready for writing.*/
if (_sdc_wait_for_transfer_state(sdcp))
- return CH_FAILED;
+ return HAL_FAILED;
/* Prepares the DMA channel for writing.*/
dmaStreamSetMemory0(sdcp->dma, buf);
dmaStreamSetTransactionSize(sdcp->dma,
- (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
+ (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P);
dmaStreamEnable(sdcp->dma);
/* Setting up data transfer.*/
- SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
- SDIO->MASK = SDIO_MASK_DCRCFAILIE |
- SDIO_MASK_DTIMEOUTIE |
- SDIO_MASK_STBITERRIE |
- SDIO_MASK_TXUNDERRIE |
- SDIO_MASK_DATAENDIE;
- SDIO->DLEN = n * MMCSD_BLOCK_SIZE;
+ sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS;
+ sdcp->sdio->MASK = SDIO_MASK_DCRCFAILIE |
+ SDIO_MASK_DTIMEOUTIE |
+ SDIO_MASK_STBITERRIE |
+ SDIO_MASK_TXUNDERRIE |
+ SDIO_MASK_DATAENDIE;
+ sdcp->sdio->DLEN = blocks * MMCSD_BLOCK_SIZE;
/* Talk to card what we want from it.*/
- if (sdc_lld_prepare_write(sdcp, startblk, n, resp) == TRUE)
+ if (sdc_lld_prepare_write(sdcp, startblk, blocks, resp) == TRUE)
goto error;
/* Transaction starts just after DTEN bit setting.*/
- SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 |
- SDIO_DCTRL_DBLOCKSIZE_0 |
- SDIO_DCTRL_DMAEN |
- SDIO_DCTRL_DTEN;
- if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE)
+ sdcp->sdio->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 |
+ SDIO_DCTRL_DBLOCKSIZE_0 |
+ SDIO_DCTRL_DMAEN |
+ SDIO_DCTRL_DTEN;
+
+ if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == TRUE)
goto error;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
error:
- sdc_lld_error_cleanup(sdcp, n, resp);
- return CH_FAILED;
+ sdc_lld_error_cleanup(sdcp, blocks, resp);
+ return HAL_FAILED;
}
/**
@@ -708,31 +789,33 @@ bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
* @param[in] sdcp pointer to the @p SDCDriver object
* @param[in] startblk first block to read
* @param[out] buf pointer to the read buffer
- * @param[in] n number of blocks to read
+ * @param[in] blocks number of blocks to read
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
- uint8_t *buf, uint32_t n) {
+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t blocks) {
#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
if (((unsigned)buf & 3) != 0) {
uint32_t i;
- for (i = 0; i < n; i++) {
+ for (i = 0; i < blocks; i++) {
if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1))
- return CH_FAILED;
+ return HAL_FAILED;
memcpy(buf, u.buf, MMCSD_BLOCK_SIZE);
buf += MMCSD_BLOCK_SIZE;
startblk++;
}
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
-#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
- return sdc_lld_read_aligned(sdcp, startblk, buf, n);
+#else /* !STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+ osalDbgAssert((((unsigned)buf & 3) == 0), "unaligned buffer");
+#endif /* !STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+ return sdc_lld_read_aligned(sdcp, startblk, buf, blocks);
}
/**
@@ -741,31 +824,33 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
* @param[in] sdcp pointer to the @p SDCDriver object
* @param[in] startblk first block to write
* @param[out] buf pointer to the write buffer
- * @param[in] n number of blocks to write
+ * @param[in] blocks number of blocks to write
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
- const uint8_t *buf, uint32_t n) {
+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t blocks) {
#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
if (((unsigned)buf & 3) != 0) {
uint32_t i;
- for (i = 0; i < n; i++) {
+ for (i = 0; i < blocks; i++) {
memcpy(u.buf, buf, MMCSD_BLOCK_SIZE);
buf += MMCSD_BLOCK_SIZE;
if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1))
- return CH_FAILED;
+ return HAL_FAILED;
startblk++;
}
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
-#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
- return sdc_lld_write_aligned(sdcp, startblk, buf, n);
+#else /* !STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+ osalDbgAssert((((unsigned)buf & 3) == 0), "unaligned buffer");
+#endif /* !STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+ return sdc_lld_write_aligned(sdcp, startblk, buf, blocks);
}
/**
@@ -774,16 +859,16 @@ bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
* @param[in] sdcp pointer to the @p SDCDriver object
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t sdc_lld_sync(SDCDriver *sdcp) {
+bool sdc_lld_sync(SDCDriver *sdcp) {
/* TODO: Implement.*/
(void)sdcp;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
#endif /* HAL_USE_SDC */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/sdc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h
similarity index 67%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/sdc_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h
index 9af4804a33..82e2a3da54 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/sdc_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/sdc_lld.h
+ * @file SDIOv1/hal_sdc_lld.h
* @brief STM32 SDC subsystem low level driver header.
*
* @addtogroup SDC
* @{
*/
-#ifndef _SDC_LLD_H_
-#define _SDC_LLD_H_
+#ifndef HAL_SDC_LLD_H
+#define HAL_SDC_LLD_H
#if HAL_USE_SDC || defined(__DOXYGEN__)
@@ -31,6 +31,26 @@
/* Driver constants. */
/*===========================================================================*/
+/*
+ * The following definitions are missing from some implementations, fixing
+ * as zeroed masks.
+ */
+#if !defined(SDIO_STA_STBITERR)
+#define SDIO_STA_STBITERR 0
+#endif
+
+#if !defined(SDIO_ICR_STBITERRC)
+#define SDIO_ICR_STBITERRC 0
+#endif
+
+#if !defined(SDIO_ICR_CEATAENDC)
+#define SDIO_ICR_CEATAENDC 0
+#endif
+
+#if !defined(SDIO_MASK_STBITERRIE)
+#define SDIO_MASK_STBITERRIE 0
+#endif
+
/**
* @brief Value to clear all interrupts flag at once.
*/
@@ -74,15 +94,15 @@
/**
* @brief Write timeout in milliseconds.
*/
-#if !defined(SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__)
-#define SDC_WRITE_TIMEOUT_MS 250
+#if !defined(STM32_SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__)
+#define STM32_SDC_WRITE_TIMEOUT_MS 1000
#endif
/**
* @brief Read timeout in milliseconds.
*/
-#if !defined(SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__)
-#define SDC_READ_TIMEOUT_MS 25
+#if !defined(STM32_SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__)
+#define STM32_SDC_READ_TIMEOUT_MS 1000
#endif
/**
@@ -99,21 +119,6 @@
#if !defined(STM32_SDC_SDIO_UNALIGNED_SUPPORT) || defined(__DOXYGEN__)
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief DMA stream used for SDC operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SDC_SDIO_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
-#endif
-
-#else /* !STM32_ADVANCED_DMA*/
-#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
-
-#endif /* !STM32_ADVANCED_DMA*/
/** @} */
/*===========================================================================*/
@@ -124,7 +129,7 @@
#error "SDIO not present in the selected device"
#endif
-#if !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SDC_SDIO_IRQ_PRIORITY)
+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SDC_SDIO_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SDIO"
#endif
@@ -132,6 +137,20 @@
#error "Invalid DMA priority assigned to SDIO"
#endif
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if !defined(STM32_SDC_SDIO_DMA_STREAM)
+#error "SDIO DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if !STM32_DMA_IS_VALID_ID(STM32_SDC_SDIO_DMA_STREAM, STM32_SDC_SDIO_DMA_MSK)
+#error "invalid DMA stream associated to SDIO"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
@@ -160,31 +179,32 @@
#error "SDIO requires STM32_CLOCK48_REQUIRED to be enabled"
#endif
+#if STM32_PLL48CLK != 48000000
+#error "invalid STM32_PLL48CLK clock value"
+#endif
+
#define STM32_SDC_WRITE_TIMEOUT \
- (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS)
+ (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * \
+ STM32_SDC_WRITE_TIMEOUT_MS)
#define STM32_SDC_READ_TIMEOUT \
- (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS)
+ (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * \
+ STM32_SDC_READ_TIMEOUT_MS)
+
+#else /* !(defined(STM32F4XX) || defined(STM32F2XX)) */
-#else
#define STM32_SDC_WRITE_TIMEOUT \
- (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS)
+ (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * \
+ STM32_SDC_WRITE_TIMEOUT_MS)
#define STM32_SDC_READ_TIMEOUT \
- (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS)
-#endif
+ (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * \
+ STM32_SDC_READ_TIMEOUT_MS)
+
+#endif /* !(defined(STM32F4XX) || defined(STM32F2XX)) */
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type of SDIO bus mode.
- */
-typedef enum {
- SDC_MODE_1BIT = 0,
- SDC_MODE_4BIT,
- SDC_MODE_8BIT
-} sdcbusmode_t;
-
/**
* @brief Type of card flags.
*/
@@ -205,7 +225,20 @@ typedef struct SDCDriver SDCDriver;
* @note It could be empty on some architectures.
*/
typedef struct {
- uint32_t dummy;
+ /**
+ * @brief Working area for memory consuming operations.
+ * @note Buffer must be word aligned and big enough to store 512 bytes.
+ * @note It is mandatory for detecting MMC cards bigger than 2GB else it
+ * can be @p NULL. SD cards do NOT need it.
+ * @note Memory pointed by this buffer is only used by @p sdcConnect(),
+ * afterward it can be reused for other purposes.
+ */
+ uint8_t *scratchpad;
+ /**
+ * @brief Bus width.
+ */
+ sdcbusmode_t bus_width;
+ /* End of the mandatory fields.*/
} SDCConfig;
/**
@@ -252,7 +285,7 @@ struct SDCDriver {
/**
* @brief Thread waiting for I/O completion IRQ.
*/
- Thread *thread;
+ thread_reference_t thread;
/**
* @brief DMA mode bit mask.
*/
@@ -263,11 +296,9 @@ struct SDCDriver {
const stm32_dma_stream_t *dma;
/**
* @brief Pointer to the SDIO registers block.
- * @note Used only for dubugging purpose.
+ * @note Needed for debugging aid.
*/
-#if CH_DBG_ENABLE_ASSERTS
SDIO_TypeDef *sdio;
-#endif
};
/*===========================================================================*/
@@ -289,29 +320,31 @@ extern "C" {
void sdc_lld_start(SDCDriver *sdcp);
void sdc_lld_stop(SDCDriver *sdcp);
void sdc_lld_start_clk(SDCDriver *sdcp);
- void sdc_lld_set_data_clk(SDCDriver *sdcp);
+ void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk);
void sdc_lld_stop_clk(SDCDriver *sdcp);
void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
- bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp);
- bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp);
- bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp);
- bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
- uint8_t *buf, uint32_t n);
- bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
- const uint8_t *buf, uint32_t n);
- bool_t sdc_lld_sync(SDCDriver *sdcp);
- bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp);
- bool_t sdc_lld_is_write_protected(SDCDriver *sdcp);
+ bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument);
+ bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t blocks);
+ bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t blocks);
+ bool sdc_lld_sync(SDCDriver *sdcp);
+ bool sdc_lld_is_card_inserted(SDCDriver *sdcp);
+ bool sdc_lld_is_write_protected(SDCDriver *sdcp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_SDC */
-#endif /* _SDC_LLD_H_ */
+#endif /* HAL_SDC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
new file mode 100644
index 0000000000..7f0658c698
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
new file mode 100644
index 0000000000..71d62cdfc0
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
@@ -0,0 +1,983 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SDMMCv1/hal_sdc_lld.c
+ * @brief STM32 SDC subsystem low level driver source.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#include
+
+#include "hal.h"
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+
+#if !defined(STM32_SDMMCCLK)
+#error "STM32_SDMMCCLK not defined"
+#endif
+
+#if STM32_SDMMCCLK > 48000000
+#error "STM32_SDMMCCLK exceeding 48MHz"
+#endif
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define SDMMC_ICR_ALL_FLAGS \
+ (SDMMC_ICR_CCRCFAILC | SDMMC_ICR_DCRCFAILC | \
+ SDMMC_ICR_CTIMEOUTC | SDMMC_ICR_DTIMEOUTC | \
+ SDMMC_ICR_TXUNDERRC | SDMMC_ICR_RXOVERRC | \
+ SDMMC_ICR_CMDRENDC | SDMMC_ICR_CMDSENTC | \
+ SDMMC_ICR_DATAENDC | SDMMC_ICR_DBCKENDC | \
+ SDMMC_ICR_SDIOITC)
+
+#define SDMMC_STA_ERROR_MASK \
+ (SDMMC_STA_CCRCFAIL | SDMMC_STA_DCRCFAIL | \
+ SDMMC_STA_CTIMEOUT | SDMMC_STA_DTIMEOUT | \
+ SDMMC_STA_TXUNDERR | SDMMC_STA_RXOVERR)
+
+#define SDMMC_CLKDIV_HS (2 - 2)
+#define SDMMC_CLKDIV_LS (120 - 2)
+
+#define SDMMC_WRITE_TIMEOUT \
+ (((STM32_SDMMCCLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \
+ STM32_SDC_SDMMC_WRITE_TIMEOUT)
+#define SDMMC_READ_TIMEOUT \
+ (((STM32_SDMMCCLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \
+ STM32_SDC_SDMMC_READ_TIMEOUT)
+
+#define SDMMC1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_SDC_SDMMC1_DMA_STREAM, \
+ STM32_SDC_SDMMC1_DMA_CHN)
+
+#define SDMMC2_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_SDC_SDMMC2_DMA_STREAM, \
+ STM32_SDC_SDMMC2_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief SDCD1 driver identifier.*/
+#if STM32_SDC_USE_SDMMC1 || defined(__DOXYGEN__)
+SDCDriver SDCD1;
+#endif
+
+/** @brief SDCD2 driver identifier.*/
+#if STM32_SDC_USE_SDMMC2 || defined(__DOXYGEN__)
+SDCDriver SDCD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#if STM32_SDC_SDMMC_UNALIGNED_SUPPORT
+/**
+ * @brief Buffer for temporary storage during unaligned transfers.
+ */
+static union {
+ uint32_t alignment;
+ uint8_t buf[MMCSD_BLOCK_SIZE];
+} u;
+#endif /* STM32_SDC_SDMMC_UNALIGNED_SUPPORT */
+
+/**
+ * @brief SDIO default configuration.
+ */
+static const SDCConfig sdc_default_cfg = {
+ NULL,
+ SDC_MODE_4BIT
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Prepares to handle read transaction.
+ * @details Designed for read special registers from card.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[out] buf pointer to the read buffer
+ * @param[in] bytes number of bytes to read
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_lld_prepare_read_bytes(SDCDriver *sdcp,
+ uint8_t *buf, uint32_t bytes) {
+ osalDbgCheck(bytes < 0x1000000);
+
+ sdcp->sdmmc->DTIMER = SDMMC_READ_TIMEOUT;
+
+ /* Checks for errors and waits for the card to be ready for reading.*/
+ if (_sdc_wait_for_transfer_state(sdcp))
+ return HAL_FAILED;
+
+ /* Prepares the DMA channel for writing.*/
+ dmaStreamSetMemory0(sdcp->dma, buf);
+ dmaStreamSetTransactionSize(sdcp->dma, bytes / sizeof (uint32_t));
+ dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M);
+ dmaStreamEnable(sdcp->dma);
+
+ /* Setting up data transfer.*/
+ sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS;
+ sdcp->sdmmc->MASK = SDMMC_MASK_DCRCFAILIE |
+ SDMMC_MASK_DTIMEOUTIE |
+ SDMMC_MASK_RXOVERRIE |
+ SDMMC_MASK_DATAENDIE;
+ sdcp->sdmmc->DLEN = bytes;
+
+ /* Transaction starts just after DTEN bit setting.*/
+ sdcp->sdmmc->DCTRL = SDMMC_DCTRL_DTDIR |
+ SDMMC_DCTRL_DTMODE | /* multibyte data transfer */
+ SDMMC_DCTRL_DMAEN |
+ SDMMC_DCTRL_DTEN;
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Prepares card to handle read transaction.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to read
+ * @param[in] n number of blocks to read
+ * @param[in] resp pointer to the response buffer
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
+ uint32_t n, uint32_t *resp) {
+
+ /* Driver handles data in 512 bytes blocks (just like HC cards). But if we
+ have not HC card than we must convert address from blocks to bytes.*/
+ if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY))
+ startblk *= MMCSD_BLOCK_SIZE;
+
+ if (n > 1) {
+ /* Send read multiple blocks command to card.*/
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK,
+ startblk, resp) || MMCSD_R1_ERROR(resp[0]))
+ return HAL_FAILED;
+ }
+ else {
+ /* Send read single block command.*/
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK,
+ startblk, resp) || MMCSD_R1_ERROR(resp[0]))
+ return HAL_FAILED;
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Prepares card to handle write transaction.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to read
+ * @param[in] n number of blocks to write
+ * @param[in] resp pointer to the response buffer
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
+ uint32_t n, uint32_t *resp) {
+
+ /* Driver handles data in 512 bytes blocks (just like HC cards). But if we
+ have not HC card than we must convert address from blocks to bytes.*/
+ if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY))
+ startblk *= MMCSD_BLOCK_SIZE;
+
+ if (n > 1) {
+ /* Write multiple blocks command.*/
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK,
+ startblk, resp) || MMCSD_R1_ERROR(resp[0]))
+ return HAL_FAILED;
+ }
+ else {
+ /* Write single block command.*/
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK,
+ startblk, resp) || MMCSD_R1_ERROR(resp[0]))
+ return HAL_FAILED;
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Wait end of data transaction and performs finalizations.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] n number of blocks in transaction
+ * @param[in] resp pointer to the response buffer
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ */
+static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
+ uint32_t *resp) {
+
+ /* Note the mask is checked before going to sleep because the interrupt
+ may have occurred before reaching the critical zone.*/
+ osalSysLock();
+ if (sdcp->sdmmc->MASK != 0)
+ osalThreadSuspendS(&sdcp->thread);
+ if ((sdcp->sdmmc->STA & SDMMC_STA_DATAEND) == 0) {
+ osalSysUnlock();
+ return HAL_FAILED;
+ }
+
+ /* Waits for transfer completion at DMA level, then the stream is
+ disabled and cleared.*/
+ dmaWaitCompletion(sdcp->dma);
+
+ sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS;
+ sdcp->sdmmc->DCTRL = 0;
+ osalSysUnlock();
+
+ /* Finalize transaction.*/
+ if (n > 1)
+ return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Gets SDC errors.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] sta value of the STA register
+ *
+ * @notapi
+ */
+static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) {
+ uint32_t errors = SDC_NO_ERROR;
+
+ if (sta & SDMMC_STA_CCRCFAIL)
+ errors |= SDC_CMD_CRC_ERROR;
+ if (sta & SDMMC_STA_DCRCFAIL)
+ errors |= SDC_DATA_CRC_ERROR;
+ if (sta & SDMMC_STA_CTIMEOUT)
+ errors |= SDC_COMMAND_TIMEOUT;
+ if (sta & SDMMC_STA_DTIMEOUT)
+ errors |= SDC_DATA_TIMEOUT;
+ if (sta & SDMMC_STA_TXUNDERR)
+ errors |= SDC_TX_UNDERRUN;
+ if (sta & SDMMC_STA_RXOVERR)
+ errors |= SDC_RX_OVERRUN;
+/* if (sta & SDMMC_STA_STBITERR)
+ errors |= SDC_STARTBIT_ERROR;*/
+
+ sdcp->errors |= errors;
+}
+
+/**
+ * @brief Performs clean transaction stopping in case of errors.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] n number of blocks in transaction
+ * @param[in] resp pointer to the response buffer
+ *
+ * @notapi
+ */
+static void sdc_lld_error_cleanup(SDCDriver *sdcp,
+ uint32_t n,
+ uint32_t *resp) {
+ uint32_t sta = sdcp->sdmmc->STA;
+
+ dmaStreamDisable(sdcp->dma);
+ sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS;
+ sdcp->sdmmc->MASK = 0;
+ sdcp->sdmmc->DCTRL = 0;
+ sdc_lld_collect_errors(sdcp, sta);
+
+ if (n > 1)
+ sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief SDMMC1 IRQ handler.
+ * @details It just wakes transaction thread, errors handling is performed in
+ * there.
+ *
+ * @isr
+ */
+#if STM32_SDC_USE_SDMMC1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(STM32_SDMMC1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+
+ /* Disables the source but the status flags are not reset because the
+ read/write functions needs to check them.*/
+ SDMMC1->MASK = 0;
+
+ osalThreadResumeI(&SDCD1.thread, MSG_OK);
+
+ osalSysUnlockFromISR();
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief SDMMC2 IRQ handler.
+ * @details It just wakes transaction thread, errors handling is performed in
+ * there.
+ *
+ * @isr
+ */
+#if STM32_SDC_USE_SDMMC2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(STM32_SDMMC2_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+
+ /* Disables the source but the status flags are not reset because the
+ read/write functions needs to check them.*/
+ SDMMC2->MASK = 0;
+
+ osalThreadResumeI(&SDCD2.thread, MSG_OK);
+
+ osalSysUnlockFromISR();
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SDC driver initialization.
+ *
+ * @notapi
+ */
+void sdc_lld_init(void) {
+
+#if STM32_SDC_USE_SDMMC1
+ sdcObjectInit(&SDCD1);
+ SDCD1.thread = NULL;
+ SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC1_DMA_STREAM);
+ SDCD1.sdmmc = SDMMC1;
+ nvicEnableVector(STM32_SDMMC1_NUMBER, STM32_SDC_SDMMC1_IRQ_PRIORITY);
+#endif
+
+#if STM32_SDC_USE_SDMMC2
+ sdcObjectInit(&SDCD2);
+ SDCD2.thread = NULL;
+ SDCD2.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC2_DMA_STREAM);
+ SDCD2.sdmmc = SDMMC2;
+ nvicEnableVector(STM32_SDMMC2_NUMBER, STM32_SDC_SDMMC2_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Configures and activates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start(SDCDriver *sdcp) {
+
+ /* Checking configuration, using a default if NULL has been passed.*/
+ if (sdcp->config == NULL) {
+ sdcp->config = &sdc_default_cfg;
+ }
+
+ sdcp->dmamode = STM32_DMA_CR_CHSEL(SDMMC1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_SDC_SDMMC1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_WORD |
+ STM32_DMA_CR_MSIZE_WORD |
+ STM32_DMA_CR_MINC;
+
+#if STM32_DMA_ADVANCED
+ sdcp->dmamode |= STM32_DMA_CR_PFCTRL |
+ STM32_DMA_CR_PBURST_INCR4 |
+ STM32_DMA_CR_MBURST_INCR4;
+#endif
+
+ /* If in stopped state then clocks are enabled and DMA initialized.*/
+ if (sdcp->state == BLK_STOP) {
+#if STM32_SDC_USE_SDMMC1
+ if (&SDCD1 == sdcp) {
+ bool b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC1_IRQ_PRIORITY,
+ NULL, NULL);
+
+ osalDbgAssert(!b, "stream already allocated");
+
+ dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdmmc->FIFO);
+#if STM32_DMA_ADVANCED
+ dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS |
+ STM32_DMA_FCR_FTH_FULL);
+#endif
+ rccEnableSDMMC1(FALSE);
+ }
+#endif /* STM32_SDC_USE_SDMMC1 */
+
+#if STM32_SDC_USE_SDMMC2
+ if (&SDCD2 == sdcp) {
+ bool b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC2_IRQ_PRIORITY,
+ NULL, NULL);
+
+ osalDbgAssert(!b, "stream already allocated");
+
+ dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdmmc->FIFO);
+#if STM32_DMA_ADVANCED
+ dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS |
+ STM32_DMA_FCR_FTH_FULL);
+#endif
+ rccEnableSDMMC2(FALSE);
+ }
+#endif /* STM32_SDC_USE_SDMMC2 */
+ }
+
+ /* Configuration, card clock is initially stopped.*/
+ sdcp->sdmmc->POWER = 0;
+ sdcp->sdmmc->CLKCR = 0;
+ sdcp->sdmmc->DCTRL = 0;
+ sdcp->sdmmc->DTIMER = 0;
+}
+
+/**
+ * @brief Deactivates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop(SDCDriver *sdcp) {
+
+ if (sdcp->state != BLK_STOP) {
+
+ /* SDIO deactivation.*/
+ sdcp->sdmmc->POWER = 0;
+ sdcp->sdmmc->CLKCR = 0;
+ sdcp->sdmmc->DCTRL = 0;
+ sdcp->sdmmc->DTIMER = 0;
+
+ /* DMA stream released.*/
+ dmaStreamRelease(sdcp->dma);
+
+ /* Clock deactivation.*/
+#if STM32_SDC_USE_SDMMC1
+ if (&SDCD1 == sdcp) {
+ rccDisableSDMMC1(FALSE);
+ }
+#endif
+
+#if STM32_SDC_USE_SDMMC2
+ if (&SDCD2 == sdcp) {
+ rccDisableSDMMC2(FALSE);
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Starts the SDIO clock and sets it to init mode (400kHz or less).
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start_clk(SDCDriver *sdcp) {
+
+ /* Initial clock setting: 400kHz, 1bit mode.*/
+ sdcp->sdmmc->CLKCR = SDMMC_CLKDIV_LS;
+ sdcp->sdmmc->POWER |= SDMMC_POWER_PWRCTRL_0 | SDMMC_POWER_PWRCTRL_1;
+ sdcp->sdmmc->CLKCR |= SDMMC_CLKCR_CLKEN;
+
+ /* Clock activation delay.*/
+ osalThreadSleep(OSAL_MS2ST(STM32_SDC_SDMMC_CLOCK_DELAY));
+}
+
+/**
+ * @brief Sets the SDIO clock to data mode (25MHz or less).
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] clk the clock mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
+#if 0
+ if (SDC_CLK_50MHz == clk) {
+ sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) |
+#if STM32_SDC_SDMMC_PWRSAV
+ SDMMC_CLKDIV_HS | SDMMC_CLKCR_BYPASS |
+ SDMMC_CLKCR_PWRSAV;
+#else
+ SDMMC_CLKDIV_HS | SDMMC_CLKCR_BYPASS;
+#endif
+ }
+ else {
+#if STM32_SDC_SDMMC_PWRSAV
+ sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | SDMMC_CLKDIV_HS |
+ SDMMC_CLKCR_PWRSAV;
+#else
+ sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | SDMMC_CLKDIV_HS;
+#endif
+ }
+#else
+ (void)clk;
+
+#if STM32_SDC_SDMMC_PWRSAV
+ sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | SDMMC_CLKDIV_HS |
+ SDMMC_CLKCR_PWRSAV;
+#else
+ sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | SDMMC_CLKDIV_HS;
+#endif
+#endif
+}
+
+/**
+ * @brief Stops the SDIO clock.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop_clk(SDCDriver *sdcp) {
+
+ sdcp->sdmmc->CLKCR = 0;
+ sdcp->sdmmc->POWER = 0;
+}
+
+/**
+ * @brief Switches the bus to 1, 4 or 8 bits mode.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] mode bus mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
+ uint32_t clk = sdcp->sdmmc->CLKCR & ~SDMMC_CLKCR_WIDBUS;
+
+ switch (mode) {
+ case SDC_MODE_1BIT:
+ sdcp->sdmmc->CLKCR = clk;
+ break;
+ case SDC_MODE_4BIT:
+ sdcp->sdmmc->CLKCR = clk | SDMMC_CLKCR_WIDBUS_0;
+ break;
+ case SDC_MODE_8BIT:
+ sdcp->sdmmc->CLKCR = clk | SDMMC_CLKCR_WIDBUS_1;
+ break;
+ }
+}
+
+/**
+ * @brief Sends an SDIO command with no response expected.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ *
+ * @notapi
+ */
+void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
+
+ sdcp->sdmmc->ARG = arg;
+ sdcp->sdmmc->CMD = (uint32_t)cmd | SDMMC_CMD_CPSMEN;
+ while ((sdcp->sdmmc->STA & SDMMC_STA_CMDSENT) == 0)
+ ;
+ sdcp->sdmmc->ICR = SDMMC_ICR_CMDSENTC;
+}
+
+/**
+ * @brief Sends an SDIO command with a short response expected.
+ * @note The CRC is not verified.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (one word)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ uint32_t sta;
+
+ sdcp->sdmmc->ARG = arg;
+ sdcp->sdmmc->CMD = (uint32_t)cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN;
+ while (((sta = sdcp->sdmmc->STA) & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT |
+ SDMMC_STA_CCRCFAIL)) == 0)
+ ;
+ sdcp->sdmmc->ICR = sta & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT |
+ SDMMC_STA_CCRCFAIL);
+ if ((sta & (SDMMC_STA_CTIMEOUT)) != 0) {
+ sdc_lld_collect_errors(sdcp, sta);
+ return HAL_FAILED;
+ }
+ *resp = sdcp->sdmmc->RESP1;
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Sends an SDIO command with a short response expected and CRC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (one word)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ uint32_t sta;
+
+ sdcp->sdmmc->ARG = arg;
+ sdcp->sdmmc->CMD = (uint32_t)cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN;
+ while (((sta = sdcp->sdmmc->STA) & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT |
+ SDMMC_STA_CCRCFAIL)) == 0)
+ ;
+ sdcp->sdmmc->ICR = sta & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT | SDMMC_STA_CCRCFAIL);
+ if ((sta & (SDMMC_STA_CTIMEOUT | SDMMC_STA_CCRCFAIL)) != 0) {
+ sdc_lld_collect_errors(sdcp, sta);
+ return HAL_FAILED;
+ }
+ *resp = sdcp->sdmmc->RESP1;
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Sends an SDIO command with a long response expected and CRC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (four words)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ uint32_t sta;
+
+ (void)sdcp;
+
+ sdcp->sdmmc->ARG = arg;
+ sdcp->sdmmc->CMD = (uint32_t)cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_WAITRESP_1 |
+ SDMMC_CMD_CPSMEN;
+ while (((sta = sdcp->sdmmc->STA) & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT |
+ SDMMC_STA_CCRCFAIL)) == 0)
+ ;
+ sdcp->sdmmc->ICR = sta & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT |
+ SDMMC_STA_CCRCFAIL);
+ if ((sta & (SDMMC_STA_ERROR_MASK)) != 0) {
+ sdc_lld_collect_errors(sdcp, sta);
+ return HAL_FAILED;
+ }
+ /* Save bytes in reverse order because MSB in response comes first.*/
+ *resp++ = sdcp->sdmmc->RESP4;
+ *resp++ = sdcp->sdmmc->RESP3;
+ *resp++ = sdcp->sdmmc->RESP2;
+ *resp = sdcp->sdmmc->RESP1;
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Reads special registers using data bus.
+ * @details Needs only during card detection procedure.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[out] buf pointer to the read buffer
+ * @param[in] bytes number of bytes to read
+ * @param[in] cmd card command
+ * @param[in] arg argument for command
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t arg) {
+ uint32_t resp[1];
+
+ if (sdc_lld_prepare_read_bytes(sdcp, buf, bytes))
+ goto error;
+
+ if (sdc_lld_send_cmd_short_crc(sdcp, cmd, arg, resp)
+ || MMCSD_R1_ERROR(resp[0]))
+ goto error;
+
+ if (sdc_lld_wait_transaction_end(sdcp, 1, resp))
+ goto error;
+
+ return HAL_SUCCESS;
+
+error:
+ sdc_lld_error_cleanup(sdcp, 1, resp);
+ return HAL_FAILED;
+}
+
+/**
+ * @brief Reads one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to read
+ * @param[out] buf pointer to the read buffer
+ * @param[in] blocks number of blocks to read
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t blocks) {
+ uint32_t resp[1];
+
+ osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE);
+
+ sdcp->sdmmc->DTIMER = SDMMC_READ_TIMEOUT;
+
+ /* Checks for errors and waits for the card to be ready for reading.*/
+ if (_sdc_wait_for_transfer_state(sdcp))
+ return HAL_FAILED;
+
+ /* Prepares the DMA channel for writing.*/
+ dmaStreamSetMemory0(sdcp->dma, buf);
+ dmaStreamSetTransactionSize(sdcp->dma,
+ (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
+ dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M);
+ dmaStreamEnable(sdcp->dma);
+
+ /* Setting up data transfer.*/
+ sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS;
+ sdcp->sdmmc->MASK = SDMMC_MASK_DCRCFAILIE |
+ SDMMC_MASK_DTIMEOUTIE |
+ SDMMC_MASK_RXOVERRIE |
+ SDMMC_MASK_DATAENDIE;
+ sdcp->sdmmc->DLEN = blocks * MMCSD_BLOCK_SIZE;
+
+ /* Transaction starts just after DTEN bit setting.*/
+ sdcp->sdmmc->DCTRL = SDMMC_DCTRL_DTDIR |
+ SDMMC_DCTRL_DBLOCKSIZE_3 |
+ SDMMC_DCTRL_DBLOCKSIZE_0 |
+ SDMMC_DCTRL_DMAEN |
+ SDMMC_DCTRL_DTEN;
+
+ if (sdc_lld_prepare_read(sdcp, startblk, blocks, resp) == TRUE)
+ goto error;
+
+ if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == TRUE)
+ goto error;
+
+ return HAL_SUCCESS;
+
+error:
+ sdc_lld_error_cleanup(sdcp, blocks, resp);
+ return HAL_FAILED;
+}
+
+/**
+ * @brief Writes one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to write
+ * @param[out] buf pointer to the write buffer
+ * @param[in] n number of blocks to write
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t blocks) {
+ uint32_t resp[1];
+
+ osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE);
+
+ sdcp->sdmmc->DTIMER = SDMMC_WRITE_TIMEOUT;
+
+ /* Checks for errors and waits for the card to be ready for writing.*/
+ if (_sdc_wait_for_transfer_state(sdcp))
+ return HAL_FAILED;
+
+ /* Prepares the DMA channel for writing.*/
+ dmaStreamSetMemory0(sdcp->dma, buf);
+ dmaStreamSetTransactionSize(sdcp->dma,
+ (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
+ dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P);
+ dmaStreamEnable(sdcp->dma);
+
+ /* Setting up data transfer.*/
+ sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS;
+ sdcp->sdmmc->MASK = SDMMC_MASK_DCRCFAILIE |
+ SDMMC_MASK_DTIMEOUTIE |
+ SDMMC_MASK_TXUNDERRIE |
+ SDMMC_MASK_DATAENDIE;
+ sdcp->sdmmc->DLEN = blocks * MMCSD_BLOCK_SIZE;
+
+ /* Talk to card what we want from it.*/
+ if (sdc_lld_prepare_write(sdcp, startblk, blocks, resp) == TRUE)
+ goto error;
+
+ /* Transaction starts just after DTEN bit setting.*/
+ sdcp->sdmmc->DCTRL = SDMMC_DCTRL_DBLOCKSIZE_3 |
+ SDMMC_DCTRL_DBLOCKSIZE_0 |
+ SDMMC_DCTRL_DMAEN |
+ SDMMC_DCTRL_DTEN;
+
+ if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == TRUE)
+ goto error;
+
+ return HAL_SUCCESS;
+
+error:
+ sdc_lld_error_cleanup(sdcp, blocks, resp);
+ return HAL_FAILED;
+}
+
+/**
+ * @brief Reads one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to read
+ * @param[out] buf pointer to the read buffer
+ * @param[in] blocks number of blocks to read
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t blocks) {
+
+#if STM32_SDC_SDMMC_UNALIGNED_SUPPORT
+ if (((unsigned)buf & 3) != 0) {
+ uint32_t i;
+ for (i = 0; i < blocks; i++) {
+ if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1))
+ return HAL_FAILED;
+ memcpy(buf, u.buf, MMCSD_BLOCK_SIZE);
+ buf += MMCSD_BLOCK_SIZE;
+ startblk++;
+ }
+ return HAL_SUCCESS;
+ }
+#else /* !STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+ osalDbgAssert((((unsigned)buf & 3) == 0), "unaligned buffer");
+#endif /* !STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+ return sdc_lld_read_aligned(sdcp, startblk, buf, blocks);
+}
+
+/**
+ * @brief Writes one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to write
+ * @param[out] buf pointer to the write buffer
+ * @param[in] blocks number of blocks to write
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t blocks) {
+
+#if STM32_SDC_SDMMC_UNALIGNED_SUPPORT
+ if (((unsigned)buf & 3) != 0) {
+ uint32_t i;
+ for (i = 0; i < blocks; i++) {
+ memcpy(u.buf, buf, MMCSD_BLOCK_SIZE);
+ buf += MMCSD_BLOCK_SIZE;
+ if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1))
+ return HAL_FAILED;
+ startblk++;
+ }
+ return HAL_SUCCESS;
+ }
+#else /* !STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+ osalDbgAssert((((unsigned)buf & 3) == 0), "unaligned buffer");
+#endif /* !STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+ return sdc_lld_write_aligned(sdcp, startblk, buf, blocks);
+}
+
+/**
+ * @brief Waits for card idle condition.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
+ *
+ * @api
+ */
+bool sdc_lld_sync(SDCDriver *sdcp) {
+
+ /* TODO: Implement.*/
+ (void)sdcp;
+ return HAL_SUCCESS;
+}
+
+#endif /* HAL_USE_SDC */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
new file mode 100644
index 0000000000..16009962c7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
@@ -0,0 +1,368 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SDMMCv1/hal_sdc_lld.h
+ * @brief STM32 SDC subsystem low level driver header.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#ifndef HAL_SDC_LLD_H
+#define HAL_SDC_LLD_H
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SDMMC1 driver enable switch.
+ * @details If set to @p TRUE the support for SDMMC1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SDC_USE_SDMMC1) || defined(__DOXYGEN__)
+#define STM32_SDC_USE_SDMMC1 FALSE
+#endif
+
+/**
+ * @brief SDMMC2 driver enable switch.
+ * @details If set to @p TRUE the support for SDMMC2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SDC_USE_SDMMC2) || defined(__DOXYGEN__)
+#define STM32_SDC_USE_SDMMC2 FALSE
+#endif
+
+/**
+ * @brief Support for unaligned transfers.
+ * @note Unaligned transfers are much slower.
+ */
+#if !defined(STM32_SDC_SDMMC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
+#endif
+
+/**
+ * @brief Write timeout in milliseconds.
+ */
+#if !defined(STM32_SDC_SDMMC_WRITE_TIMEOUT) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
+#endif
+
+/**
+ * @brief Read timeout in milliseconds.
+ */
+#if !defined(STM32_SDC_SDMMC_READ_TIMEOUT) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
+#endif
+
+/**
+ * @brief Card clock activation delay in milliseconds.
+ */
+#if !defined(STM32_SDC_SDMMC_CLOCK_DELAY) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC_CLOCK_DELAY 10
+#endif
+
+/**
+ * @brief Card clock power saving enable.
+ */
+#if !defined(STM32_SDC_SDMMC_PWRSAV) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC_PWRSAV TRUE
+#endif
+
+/**
+ * @brief SDMMC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_SDC_SDMMC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
+#endif
+
+/**
+ * @brief SDMMC2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_SDC_SDMMC2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC2_DMA_PRIORITY 3
+#endif
+
+/**
+ * @brief SDMMC1 interrupt priority level setting.
+ */
+#if !defined(STM32_SDC_SDMMC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
+#endif
+
+/**
+ * @brief SDMMC2 interrupt priority level setting.
+ */
+#if !defined(STM32_SDC_SDMMC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC2_IRQ_PRIORITY 9
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/* Registry checks.*/
+#if (STM32_SDC_USE_SDMMC1 && !defined(STM32_SDMMC1_HANDLER)) || \
+ (STM32_SDC_USE_SDMMC2 && !defined(STM32_SDMMC2_HANDLER))
+#error "STM32_SDMMCx_HANDLER not defined in registry"
+#endif
+
+#if (STM32_SDC_USE_SDMMC1 && !defined(STM32_SDMMC1_NUMBER)) || \
+ (STM32_SDC_USE_SDMMC2 && !defined(STM32_SDMMC2_NUMBER))
+#error "STM32_ADCx_NUMBER not defined in registry"
+#endif
+
+#if (STM32_SDC_USE_SDMMC1 && !defined(STM32_SDC_SDMMC1_DMA_MSK)) || \
+ (STM32_SDC_USE_SDMMC2 && !defined(STM32_SDC_SDMMC2_DMA_MSK))
+#error "STM32_SDC_SDMMCx_DMA_MSK not defined in registry"
+#endif
+
+#if (STM32_SDC_USE_SDMMC1 && !defined(STM32_SDC_SDMMC1_DMA_CHN)) || \
+ (STM32_SDC_USE_SDMMC2 && !defined(STM32_SDC_SDMMC2_DMA_CHN))
+#error "STM32_SDC_SDMMCx_DMA_CHN not defined in registry"
+#endif
+
+/* Units checks.*/
+#if STM32_SDC_USE_SDMMC1 && !STM32_HAS_SDMMC1
+#error "SDMMC1 not present in the selected device"
+#endif
+
+#if STM32_SDC_USE_SDMMC2 && !STM32_HAS_SDMMC2
+#error "SDMMC2 not present in the selected device"
+#endif
+
+#if !STM32_SDC_USE_SDMMC1 && !STM32_SDC_USE_SDMMC2
+#error "SDC driver activated but no SDMMC peripheral assigned"
+#endif
+
+/* Clock related tests.*/
+#if !defined(STM32_SDMMCCLK)
+#error "STM32_SDMMCCLK not defined"
+#endif
+
+#if !defined(STM32_HCLK)
+#error "STM32_HCLK not defined"
+#endif
+
+#if STM32_SDMMCCLK * 10 > STM32_HCLK * 7
+#error "STM32_SDC_USE_SDMMC1 must not exceed STM32_HCLK * 0.7"
+#endif
+
+/* SDMMC IRQ priority tests.*/
+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SDC_SDMMC1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDMMC1"
+#endif
+
+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SDC_SDMMC2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDMMC2"
+#endif
+
+/* DMA priority tests.*/
+#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDMMC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDMMC1"
+#endif
+
+#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDMMC2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDMMC2"
+#endif
+
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_SDC_USE_SDMMC1 && !defined(STM32_SDC_SDMMC1_DMA_STREAM)
+#error "SDMMC1 DMA streams not defined"
+#endif
+
+#if STM32_SDC_USE_SDMMC2 && !defined(STM32_SDC_SDMMC2_DMA_STREAM)
+#error "SDMMC2 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_SDC_USE_SDMMC1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_SDC_SDMMC1_DMA_STREAM, STM32_SDC_SDMMC1_DMA_MSK)
+#error "invalid DMA stream associated to SDMMC1"
+#endif
+
+#if STM32_SDC_USE_SDMMC2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_SDC_SDMMC2_DMA_STREAM, STM32_SDC_SDMMC2_DMA_MSK)
+#error "invalid DMA stream associated to SDMMC2"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of card flags.
+ */
+typedef uint32_t sdcmode_t;
+
+/**
+ * @brief SDC Driver condition flags type.
+ */
+typedef uint32_t sdcflags_t;
+
+/**
+ * @brief Type of a structure representing an SDC driver.
+ */
+typedef struct SDCDriver SDCDriver;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Working area for memory consuming operations.
+ * @note Buffer must be word aligned and big enough to store 512 bytes.
+ * @note It is mandatory for detecting MMC cards bigger than 2GB else it
+ * can be @p NULL. SD cards do NOT need it.
+ * @note Memory pointed by this buffer is only used by @p sdcConnect(),
+ * afterward it can be reused for other purposes.
+ */
+ uint8_t *scratchpad;
+ /**
+ * @brief Bus width.
+ */
+ sdcbusmode_t bus_width;
+ /* End of the mandatory fields.*/
+} SDCConfig;
+
+/**
+ * @brief @p SDCDriver specific methods.
+ */
+#define _sdc_driver_methods \
+ _mmcsd_block_device_methods
+
+/**
+ * @extends MMCSDBlockDeviceVMT
+ *
+ * @brief @p SDCDriver virtual methods table.
+ */
+struct SDCDriverVMT {
+ _sdc_driver_methods
+};
+
+/**
+ * @brief Structure representing an SDC driver.
+ */
+struct SDCDriver {
+ /**
+ * @brief Virtual Methods Table.
+ */
+ const struct SDCDriverVMT *vmt;
+ _mmcsd_block_device_data
+ /**
+ * @brief Current configuration data.
+ */
+ const SDCConfig *config;
+ /**
+ * @brief Various flags regarding the mounted card.
+ */
+ sdcmode_t cardmode;
+ /**
+ * @brief Errors flags.
+ */
+ sdcflags_t errors;
+ /**
+ * @brief Card RCA.
+ */
+ uint32_t rca;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Thread waiting for I/O completion IRQ.
+ */
+ thread_reference_t thread;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+ /**
+ * @brief Transmit DMA channel.
+ */
+ const stm32_dma_stream_t *dma;
+ /**
+ * @brief Pointer to the SDMMC registers block.
+ * @note Needed for debugging aid.
+ */
+ SDMMC_TypeDef *sdmmc;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_SDC_USE_SDMMC1 && !defined(__DOXYGEN__)
+extern SDCDriver SDCD1;
+#endif
+
+#if STM32_SDC_USE_SDMMC2 && !defined(__DOXYGEN__)
+extern SDCDriver SDCD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sdc_lld_init(void);
+ void sdc_lld_start(SDCDriver *sdcp);
+ void sdc_lld_stop(SDCDriver *sdcp);
+ void sdc_lld_start_clk(SDCDriver *sdcp);
+ void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk);
+ void sdc_lld_stop_clk(SDCDriver *sdcp);
+ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
+ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
+ bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument);
+ bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t blocks);
+ bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t blocks);
+ bool sdc_lld_sync(SDCDriver *sdcp);
+ bool sdc_lld_is_card_inserted(SDCDriver *sdcp);
+ bool sdc_lld_is_write_protected(SDCDriver *sdcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SDC */
+
+#endif /* HAL_SDC_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/driver.mk
new file mode 100644
index 0000000000..619ff93196
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/driver.mk
@@ -0,0 +1,13 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c
+endif
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c
new file mode 100644
index 0000000000..60a6487beb
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c
@@ -0,0 +1,577 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPIv1/hal_i2s_lld.c
+ * @brief STM32 I2S subsystem low level driver source.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define I2S1_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \
+ STM32_SPI1_RX_DMA_CHN)
+
+#define I2S1_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \
+ STM32_SPI1_TX_DMA_CHN)
+
+#define I2S2_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \
+ STM32_SPI2_RX_DMA_CHN)
+
+#define I2S2_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \
+ STM32_SPI2_TX_DMA_CHN)
+
+#define I2S3_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM, \
+ STM32_SPI3_RX_DMA_CHN)
+
+#define I2S3_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \
+ STM32_SPI3_TX_DMA_CHN)
+
+/*
+ * Static I2S settings for I2S1.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
+ SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
+
+/*
+ * Static I2S settings for I2S2.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
+ SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
+
+/*
+ * Static I2S settings for I2S3.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
+ SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief I2S1 driver identifier.*/
+#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__)
+I2SDriver I2SD1;
+#endif
+
+/** @brief I2S2 driver identifier.*/
+#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__)
+I2SDriver I2SD2;
+#endif
+
+/** @brief I2S3 driver identifier.*/
+#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__)
+I2SDriver I2SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \
+ STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \
+ STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared end-of-rx service routine.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
+
+ (void)i2sp;
+
+ /* DMA errors handling.*/
+#if defined(STM32_I2S_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_I2S_DMA_ERROR_HOOK(i2sp);
+ }
+#endif
+
+ /* Callbacks handling, note it is portable code defined in the high
+ level driver.*/
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _i2s_isr_full_code(i2sp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _i2s_isr_half_code(i2sp);
+ }
+}
+#endif
+
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared end-of-tx service routine.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
+
+ (void)i2sp;
+
+ /* DMA errors handling.*/
+#if defined(STM32_I2S_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_I2S_DMA_ERROR_HOOK(i2sp);
+ }
+#endif
+
+ /* Callbacks handling, note it is portable code defined in the high
+ level driver.*/
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _i2s_isr_full_code(i2sp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _i2s_isr_half_code(i2sp);
+ }
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2S driver initialization.
+ *
+ * @notapi
+ */
+void i2s_lld_init(void) {
+
+#if STM32_I2S_USE_SPI1
+ i2sObjectInit(&I2SD1);
+ I2SD1.spi = SPI1;
+ I2SD1.cfg = STM32_I2S1_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+ I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM);
+ I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD1.dmarx = NULL;
+ I2SD1.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+ I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM);
+ I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD1.dmatx = NULL;
+ I2SD1.txdmamode = 0;
+#endif
+#endif
+
+#if STM32_I2S_USE_SPI2
+ i2sObjectInit(&I2SD2);
+ I2SD2.spi = SPI2;
+ I2SD2.cfg = STM32_I2S2_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+ I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
+ I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD2.dmarx = NULL;
+ I2SD2.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+ I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
+ I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD2.dmatx = NULL;
+ I2SD2.txdmamode = 0;
+#endif
+#endif
+
+#if STM32_I2S_USE_SPI3
+ i2sObjectInit(&I2SD3);
+ I2SD3.spi = SPI3;
+ I2SD3.cfg = STM32_I2S3_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+ I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
+ I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD3.dmarx = NULL;
+ I2SD3.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+ I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
+ I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD3.dmatx = NULL;
+ I2SD3.txdmamode = 0;
+#endif
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start(I2SDriver *i2sp) {
+
+ /* If in stopped state then enables the SPI and DMA clocks.*/
+ if (i2sp->state == I2S_STOP) {
+
+#if STM32_I2S_USE_SPI1
+ if (&I2SD1 == i2sp) {
+ bool b;
+
+ /* Enabling I2S unit clock.*/
+ rccEnableSPI1(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+ b = dmaStreamAllocate(i2sp->dmarx,
+ STM32_I2S_SPI1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+ b = dmaStreamAllocate(i2sp->dmatx,
+ STM32_I2S_SPI1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+ }
+#endif
+
+#if STM32_I2S_USE_SPI2
+ if (&I2SD2 == i2sp) {
+ bool b;
+
+ /* Enabling I2S unit clock.*/
+ rccEnableSPI2(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+ b = dmaStreamAllocate(i2sp->dmarx,
+ STM32_I2S_SPI2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+ b = dmaStreamAllocate(i2sp->dmatx,
+ STM32_I2S_SPI2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+ }
+#endif
+
+#if STM32_I2S_USE_SPI3
+ if (&I2SD3 == i2sp) {
+ bool b;
+
+ /* Enabling I2S unit clock.*/
+ rccEnableSPI3(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+ b = dmaStreamAllocate(i2sp->dmarx,
+ STM32_I2S_SPI3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+ b = dmaStreamAllocate(i2sp->dmatx,
+ STM32_I2S_SPI3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+ }
+#endif
+ }
+
+ /* I2S (re)configuration.*/
+ i2sp->spi->I2SPR = i2sp->config->i2spr;
+ i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD;
+}
+
+/**
+ * @brief Deactivates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop(I2SDriver *i2sp) {
+
+ /* If in ready state then disables the SPI clock.*/
+ if (i2sp->state == I2S_READY) {
+
+ /* SPI disable.*/
+ i2sp->spi->CR2 = 0;
+ if (NULL != i2sp->dmarx)
+ dmaStreamRelease(i2sp->dmarx);
+ if (NULL != i2sp->dmatx)
+ dmaStreamRelease(i2sp->dmatx);
+
+#if STM32_I2S_USE_SPI1
+ if (&I2SD1 == i2sp)
+ rccDisableSPI1(FALSE);
+#endif
+
+#if STM32_I2S_USE_SPI2
+ if (&I2SD2 == i2sp)
+ rccDisableSPI2(FALSE);
+#endif
+
+#if STM32_I2S_USE_SPI3
+ if (&I2SD3 == i2sp)
+ rccDisableSPI3(FALSE);
+#endif
+ }
+}
+
+/**
+ * @brief Starts a I2S data exchange.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start_exchange(I2SDriver *i2sp) {
+ size_t size = i2sp->config->size;
+
+ /* In 32 bit modes the DMA has to perform double operations because fetches
+ are always performed using 16 bit accesses.
+ DATLEN CHLEN SIZE
+ 00 (16) 0 (16) 16
+ 00 (16) 1 (32) 16
+ 01 (24) X 32
+ 10 (32) X 32
+ 11 (NA) X NA
+ */
+ if ((i2sp->config->i2scfgr & SPI_I2SCFGR_DATLEN) != 0)
+ size *= 2;
+
+ /* RX DMA setup.*/
+ if (NULL != i2sp->dmarx) {
+ dmaStreamSetMode(i2sp->dmarx, i2sp->rxdmamode);
+ dmaStreamSetPeripheral(i2sp->dmarx, &i2sp->spi->DR);
+ dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer);
+ dmaStreamSetTransactionSize(i2sp->dmarx, size);
+ dmaStreamEnable(i2sp->dmarx);
+ }
+
+ /* TX DMA setup.*/
+ if (NULL != i2sp->dmatx) {
+ dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode);
+ dmaStreamSetPeripheral(i2sp->dmatx, &i2sp->spi->DR);
+ dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer);
+ dmaStreamSetTransactionSize(i2sp->dmatx, size);
+ dmaStreamEnable(i2sp->dmatx);
+ }
+
+ /* Starting transfer.*/
+ i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE;
+}
+
+/**
+ * @brief Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ * was not active the function does nothing.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop_exchange(I2SDriver *i2sp) {
+
+ /* Stop TX DMA, if enabled.*/
+ if (NULL != i2sp->dmatx) {
+ dmaStreamDisable(i2sp->dmatx);
+
+ /* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory
+ to wait for TXE = 1 and BSY = 0.*/
+ while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE)
+ ;
+ }
+
+ /* Stop SPI/I2S peripheral.*/
+ i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
+
+ /* Stop RX DMA, if enabled.*/
+ if (NULL != i2sp->dmarx)
+ dmaStreamDisable(i2sp->dmarx);
+}
+
+#endif /* HAL_USE_I2S */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.h
new file mode 100644
index 0000000000..8dbcf19593
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.h
@@ -0,0 +1,432 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPIv1/hal_i2s_lld.h
+ * @brief STM32 I2S subsystem low level driver header.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#ifndef HAL_I2S_LLD_H
+#define HAL_I2S_LLD_H
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Static I2S modes
+ * @{
+ */
+#define STM32_I2S_MODE_SLAVE 0
+#define STM32_I2S_MODE_MASTER 1
+#define STM32_I2S_MODE_RX 2
+#define STM32_I2S_MODE_TX 4
+#define STM32_I2S_MODE_RXTX (STM32_I2S_MODE_RX | \
+ STM32_I2S_MODE_TX)
+/** @} */
+
+/**
+ * @name Mode checks
+ * @{
+ */
+#define STM32_I2S_IS_MASTER(mode) ((mode) & STM32_I2S_MODE_MASTER)
+#define STM32_I2S_RX_ENABLED(mode) ((mode) & STM32_I2S_MODE_RX)
+#define STM32_I2S_TX_ENABLED(mode) ((mode) & STM32_I2S_MODE_TX)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief I2S1 driver enable switch.
+ * @details If set to @p TRUE the support for I2S1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI1) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI1 FALSE
+#endif
+
+/**
+ * @brief I2S2 driver enable switch.
+ * @details If set to @p TRUE the support for I2S2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI2) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI2 FALSE
+#endif
+
+/**
+ * @brief I2S3 driver enable switch.
+ * @details If set to @p TRUE the support for I2S3 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI3) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI3 FALSE
+#endif
+
+/**
+ * @brief I2S1 mode.
+ */
+#if !defined(STM32_I2S_SPI1_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief I2S2 mode.
+ */
+#if !defined(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief I2S3 mode.
+ */
+#if !defined(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief I2S1 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2S2 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2S3 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2S1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S DMA error hook.
+ */
+#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_I2S_USE_SPI1 && !STM32_SPI1_SUPPORTS_I2S
+#error "SPI1 does not support I2S mode"
+#endif
+
+#if STM32_I2S_USE_SPI2 && !STM32_SPI2_SUPPORTS_I2S
+#error "SPI2 does not support I2S mode"
+#endif
+
+#if STM32_I2S_USE_SPI3 && !STM32_SPI3_SUPPORTS_I2S
+#error "SPI3 does not support I2S mode"
+#endif
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#error "I2S1 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#error "I2S2 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) && \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#error "I2S3 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2
+#error "SPI2 not present in the selected device"
+#endif
+
+#if STM32_I2S_USE_SPI3 && !STM32_HAS_SPI3
+#error "SPI3 not present in the selected device"
+#endif
+
+#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3
+#error "I2S driver activated but no SPI peripheral assigned"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI2"
+#endif
+
+#if STM32_I2S_USE_SPI3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI3"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI1"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI2"
+#endif
+
+#if STM32_I2S_USE_SPI3 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI3"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_I2S_USE_SPI1 && (!defined(STM32_I2S_SPI1_RX_DMA_STREAM) || \
+ !defined(STM32_I2S_SPI1_TX_DMA_STREAM))
+#error "SPI1 DMA streams not defined"
+#endif
+
+#if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) || \
+ !defined(STM32_I2S_SPI2_TX_DMA_STREAM))
+#error "SPI2 DMA streams not defined"
+#endif
+
+#if STM32_I2S_USE_SPI3 && (!defined(STM32_I2S_SPI3_RX_DMA_STREAM) || \
+ !defined(STM32_I2S_SPI3_TX_DMA_STREAM))
+#error "SPI3 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 RX"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 TX"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 RX"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 TX"
+#endif
+
+#if STM32_I2S_USE_SPI3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 RX"
+#endif
+
+#if STM32_I2S_USE_SPI3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an I2S driver.
+ */
+typedef struct I2SDriver I2SDriver;
+
+/**
+ * @brief I2S notification callback type.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] offset offset in buffers of the data to read/write
+ * @param[in] n number of samples to read/write
+ */
+typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n);
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Transmission buffer pointer.
+ * @note Can be @p NULL if TX is not required.
+ */
+ const void *tx_buffer;
+ /**
+ * @brief Receive buffer pointer.
+ * @note Can be @p NULL if RX is not required.
+ */
+ void *rx_buffer;
+ /**
+ * @brief TX and RX buffers size as number of samples.
+ */
+ size_t size;
+ /**
+ * @brief Callback function called during streaming.
+ */
+ i2scallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Configuration of the I2SCFGR register.
+ * @details See the STM32 reference manual, this register is used for
+ * the I2S configuration, the following bits must not be
+ * specified because handled directly by the driver:
+ * - I2SMOD
+ * - I2SE
+ * - I2SCFG
+ * .
+ */
+ int16_t i2scfgr;
+ /**
+ * @brief Configuration of the I2SPR register.
+ * @details See the STM32 reference manual, this register is used for
+ * the I2S clock setup.
+ */
+ int16_t i2spr;
+} I2SConfig;
+
+/**
+ * @brief Structure representing an I2S driver.
+ */
+struct I2SDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2sstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2SConfig *config;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the SPIx registers block.
+ */
+ SPI_TypeDef *spi;
+ /**
+ * @brief Calculated part of the I2SCFGR register.
+ */
+ uint16_t cfg;
+ /**
+ * @brief Receive DMA stream or @p NULL.
+ */
+ const stm32_dma_stream_t *dmarx;
+ /**
+ * @brief Transmit DMA stream or @p NULL.
+ */
+ const stm32_dma_stream_t *dmatx;
+ /**
+ * @brief RX DMA mode bit mask.
+ */
+ uint32_t rxdmamode;
+ /**
+ * @brief TX DMA mode bit mask.
+ */
+ uint32_t txdmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_I2S_USE_SPI1 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD1;
+#endif
+
+#if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD2;
+#endif
+
+#if STM32_I2S_USE_SPI3 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2s_lld_init(void);
+ void i2s_lld_start(I2SDriver *i2sp);
+ void i2s_lld_stop(I2SDriver *i2sp);
+ void i2s_lld_start_exchange(I2SDriver *i2sp);
+ void i2s_lld_stop_exchange(I2SDriver *i2sp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2S */
+
+#endif /* HAL_I2S_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv1/spi_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c
similarity index 94%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv1/spi_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c
index 7c0a5e58a6..d17ab0b268 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv1/spi_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/SPIv1/spi_lld.c
+ * @file SPIv1/hal_spi_lld.c
* @brief STM32 SPI subsystem low level driver source.
*
* @addtogroup SPI
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_SPI || defined(__DOXYGEN__)
@@ -117,7 +116,7 @@ SPIDriver SPID6;
/* Driver local variables and types. */
/*===========================================================================*/
-static uint16_t dummytx;
+static const uint16_t dummytx = 0xFFFFU;
static uint16_t dummyrx;
/*===========================================================================*/
@@ -185,8 +184,6 @@ static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
*/
void spi_lld_init(void) {
- dummytx = 0xFFFF;
-
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
@@ -309,97 +306,97 @@ void spi_lld_start(SPIDriver *spip) {
if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI1(FALSE);
}
#endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI2(FALSE);
}
#endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI3(FALSE);
}
#endif
#if STM32_SPI_USE_SPI4
if (&SPID4 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #7", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #8", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI4(FALSE);
}
#endif
#if STM32_SPI_USE_SPI5
if (&SPID5 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #9", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #10", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI5(FALSE);
}
#endif
#if STM32_SPI_USE_SPI6
if (&SPID6 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #11", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #12", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI6(FALSE);
}
#endif
@@ -425,10 +422,11 @@ void spi_lld_start(SPIDriver *spip) {
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
}
/* SPI setup and enable.*/
- spip->spi->CR1 = 0;
+ spip->spi->CR1 &= ~SPI_CR1_SPE;
spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
SPI_CR1_SSI;
- spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
+ spip->spi->CR2 = spip->config->cr2 | SPI_CR2_SSOE | SPI_CR2_RXDMAEN |
+ SPI_CR2_TXDMAEN;
spip->spi->CR1 |= SPI_CR1_SPE;
}
@@ -445,8 +443,9 @@ void spi_lld_stop(SPIDriver *spip) {
if (spip->state == SPI_READY) {
/* SPI disable.*/
- spip->spi->CR1 = 0;
- spip->spi->CR2 = 0;
+ spip->spi->CR1 &= ~SPI_CR1_SPE;
+ spip->spi->CR1 = 0;
+ spip->spi->CR2 = 0;
dmaStreamRelease(spip->dmarx);
dmaStreamRelease(spip->dmatx);
@@ -515,6 +514,8 @@ void spi_lld_unselect(SPIDriver *spip) {
*/
void spi_lld_ignore(SPIDriver *spip, size_t n) {
+ osalDbgAssert(n < 65536, "unsupported DMA transfer size");
+
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
@@ -545,6 +546,8 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
void spi_lld_exchange(SPIDriver *spip, size_t n,
const void *txbuf, void *rxbuf) {
+ osalDbgAssert(n < 65536, "unsupported DMA transfer size");
+
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
@@ -572,6 +575,8 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
*/
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+ osalDbgAssert(n < 65536, "unsupported DMA transfer size");
+
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
@@ -599,6 +604,8 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
*/
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+ osalDbgAssert(n < 65536, "unsupported DMA transfer size");
+
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv1/spi_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.h
similarity index 74%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv1/spi_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.h
index c7a417907c..9970e5b751 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv1/spi_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/SPIv1/spi_lld.h
+ * @file SPIv1/hal_spi_lld.h
* @brief STM32 SPI subsystem low level driver header.
*
* @addtogroup SPI
* @{
*/
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
+#ifndef HAL_SPI_LLD_H
+#define HAL_SPI_LLD_H
#if HAL_USE_SPI || defined(__DOXYGEN__)
@@ -199,125 +199,8 @@
* @brief SPI DMA error hook.
*/
#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief DMA stream used for SPI1 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
-#endif
-
-/**
- * @brief DMA stream used for SPI1 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
-#endif
-
-/**
- * @brief DMA stream used for SPI2 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#endif
-
-/**
- * @brief DMA stream used for SPI2 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#endif
-
-/**
- * @brief DMA stream used for SPI3 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
-#endif
-
-/**
- * @brief DMA stream used for SPI3 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#endif
-
-/**
- * @brief DMA stream used for SPI4 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI4_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
-#endif
-
-/**
- * @brief DMA stream used for SPI4 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI4_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#endif
-
-/**
- * @brief DMA stream used for SPI5 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI5_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
-#endif
-
-/**
- * @brief DMA stream used for SPI5 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI5_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
-#endif
-
-/**
- * @brief DMA stream used for SPI6 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI6_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
-#endif
-
-/**
- * @brief DMA stream used for SPI6 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI6_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
-#endif
-
-#else /* !STM32_ADVANCED_DMA */
-
-/* Fixed streams for platforms using the old DMA peripheral, the values are
- valid for both STM32F1xx and STM32L1xx.*/
-#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
-#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
-#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
-#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
-#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
-#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
-
-#endif /* !STM32_ADVANCED_DMA*/
/** @} */
/*===========================================================================*/
@@ -354,32 +237,32 @@
#endif
#if STM32_SPI_USE_SPI1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI1"
#endif
#if STM32_SPI_USE_SPI2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI2"
#endif
#if STM32_SPI_USE_SPI3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI3"
#endif
#if STM32_SPI_USE_SPI4 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI4"
#endif
#if STM32_SPI_USE_SPI5 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI5"
#endif
#if STM32_SPI_USE_SPI6 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI6"
#endif
@@ -413,6 +296,41 @@
#error "Invalid DMA priority assigned to SPI6"
#endif
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI1_TX_DMA_STREAM))
+#error "SPI1 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI2_TX_DMA_STREAM))
+#error "SPI2 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI3_TX_DMA_STREAM))
+#error "SPI3 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI4_TX_DMA_STREAM))
+#error "SPI4 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI5_TX_DMA_STREAM))
+#error "SPI5 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI6_TX_DMA_STREAM))
+#error "SPI6 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 RX"
@@ -472,6 +390,7 @@
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI6 TX"
#endif
+#endif /* STM32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
@@ -512,13 +431,17 @@ typedef struct {
*/
uint16_t sspad;
/**
- * @brief SPI initialization data.
+ * @brief SPI CR1 register initialization data.
*/
uint16_t cr1;
+ /**
+ * @brief SPI CR2 register initialization data.
+ */
+ uint16_t cr2;
} SPIConfig;
/**
- * @brief Structure representing a SPI driver.
+ * @brief Structure representing an SPI driver.
*/
struct SPIDriver {
/**
@@ -533,17 +456,13 @@ struct SPIDriver {
/**
* @brief Waiting thread.
*/
- Thread *thread;
+ thread_reference_t thread;
#endif /* SPI_USE_WAIT */
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
+ mutex_t mutex;
#endif /* SPI_USE_MUTUAL_EXCLUSION */
#if defined(SPI_DRIVER_EXT_FIELDS)
SPI_DRIVER_EXT_FIELDS
@@ -623,6 +542,6 @@ extern "C" {
#endif /* HAL_USE_SPI */
-#endif /* _SPI_LLD_H_ */
+#endif /* HAL_SPI_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/driver.mk
new file mode 100644
index 0000000000..d18ea35c00
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/driver.mk
@@ -0,0 +1,13 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c
+endif
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c
new file mode 100644
index 0000000000..7c456204d6
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c
@@ -0,0 +1,577 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPIv2/hal_i2s_lld.c
+ * @brief STM32 I2S subsystem low level driver source.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define I2S1_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \
+ STM32_SPI1_RX_DMA_CHN)
+
+#define I2S1_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \
+ STM32_SPI1_TX_DMA_CHN)
+
+#define I2S2_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \
+ STM32_SPI2_RX_DMA_CHN)
+
+#define I2S2_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \
+ STM32_SPI2_TX_DMA_CHN)
+
+#define I2S3_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM, \
+ STM32_SPI3_RX_DMA_CHN)
+
+#define I2S3_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \
+ STM32_SPI3_TX_DMA_CHN)
+
+/*
+ * Static I2S settings for I2S1.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
+ SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
+
+/*
+ * Static I2S settings for I2S2.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
+ SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
+
+/*
+ * Static I2S settings for I2S3.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
+ SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief I2S1 driver identifier.*/
+#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__)
+I2SDriver I2SD1;
+#endif
+
+/** @brief I2S2 driver identifier.*/
+#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__)
+I2SDriver I2SD2;
+#endif
+
+/** @brief I2S3 driver identifier.*/
+#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__)
+I2SDriver I2SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \
+ STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \
+ STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared end-of-rx service routine.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
+
+ (void)i2sp;
+
+ /* DMA errors handling.*/
+#if defined(STM32_I2S_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_I2S_DMA_ERROR_HOOK(i2sp);
+ }
+#endif
+
+ /* Callbacks handling, note it is portable code defined in the high
+ level driver.*/
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _i2s_isr_full_code(i2sp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _i2s_isr_half_code(i2sp);
+ }
+}
+#endif
+
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared end-of-tx service routine.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
+
+ (void)i2sp;
+
+ /* DMA errors handling.*/
+#if defined(STM32_I2S_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_I2S_DMA_ERROR_HOOK(i2sp);
+ }
+#endif
+
+ /* Callbacks handling, note it is portable code defined in the high
+ level driver.*/
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _i2s_isr_full_code(i2sp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _i2s_isr_half_code(i2sp);
+ }
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2S driver initialization.
+ *
+ * @notapi
+ */
+void i2s_lld_init(void) {
+
+#if STM32_I2S_USE_SPI1
+ i2sObjectInit(&I2SD1);
+ I2SD1.spi = SPI1;
+ I2SD1.cfg = STM32_I2S1_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+ I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM);
+ I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD1.dmarx = NULL;
+ I2SD1.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+ I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM);
+ I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD1.dmatx = NULL;
+ I2SD1.txdmamode = 0;
+#endif
+#endif
+
+#if STM32_I2S_USE_SPI2
+ i2sObjectInit(&I2SD2);
+ I2SD2.spi = SPI2;
+ I2SD2.cfg = STM32_I2S2_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+ I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
+ I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD2.dmarx = NULL;
+ I2SD2.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+ I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
+ I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD2.dmatx = NULL;
+ I2SD2.txdmamode = 0;
+#endif
+#endif
+
+#if STM32_I2S_USE_SPI3
+ i2sObjectInit(&I2SD3);
+ I2SD3.spi = SPI3;
+ I2SD3.cfg = STM32_I2S3_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+ I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
+ I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD3.dmarx = NULL;
+ I2SD3.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+ I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
+ I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD3.dmatx = NULL;
+ I2SD3.txdmamode = 0;
+#endif
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start(I2SDriver *i2sp) {
+
+ /* If in stopped state then enables the SPI and DMA clocks.*/
+ if (i2sp->state == I2S_STOP) {
+
+#if STM32_I2S_USE_SPI1
+ if (&I2SD1 == i2sp) {
+ bool b;
+
+ /* Enabling I2S unit clock.*/
+ rccEnableSPI1(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+ b = dmaStreamAllocate(i2sp->dmarx,
+ STM32_I2S_SPI1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+ b = dmaStreamAllocate(i2sp->dmatx,
+ STM32_I2S_SPI1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+ }
+#endif
+
+#if STM32_I2S_USE_SPI2
+ if (&I2SD2 == i2sp) {
+ bool b;
+
+ /* Enabling I2S unit clock.*/
+ rccEnableSPI2(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+ b = dmaStreamAllocate(i2sp->dmarx,
+ STM32_I2S_SPI2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+ b = dmaStreamAllocate(i2sp->dmatx,
+ STM32_I2S_SPI2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+ }
+#endif
+
+#if STM32_I2S_USE_SPI3
+ if (&I2SD3 == i2sp) {
+ bool b;
+
+ /* Enabling I2S unit clock.*/
+ rccEnableSPI3(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+ b = dmaStreamAllocate(i2sp->dmarx,
+ STM32_I2S_SPI3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+ b = dmaStreamAllocate(i2sp->dmatx,
+ STM32_I2S_SPI3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+ }
+#endif
+ }
+
+ /* I2S (re)configuration.*/
+ i2sp->spi->I2SPR = i2sp->config->i2spr;
+ i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD;
+}
+
+/**
+ * @brief Deactivates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop(I2SDriver *i2sp) {
+
+ /* If in ready state then disables the SPI clock.*/
+ if (i2sp->state == I2S_READY) {
+
+ /* SPI disable.*/
+ i2sp->spi->CR2 = 0;
+ if (NULL != i2sp->dmarx)
+ dmaStreamRelease(i2sp->dmarx);
+ if (NULL != i2sp->dmatx)
+ dmaStreamRelease(i2sp->dmatx);
+
+#if STM32_I2S_USE_SPI1
+ if (&I2SD1 == i2sp)
+ rccDisableSPI1(FALSE);
+#endif
+
+#if STM32_I2S_USE_SPI2
+ if (&I2SD2 == i2sp)
+ rccDisableSPI2(FALSE);
+#endif
+
+#if STM32_I2S_USE_SPI3
+ if (&I2SD3 == i2sp)
+ rccDisableSPI3(FALSE);
+#endif
+ }
+}
+
+/**
+ * @brief Starts a I2S data exchange.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start_exchange(I2SDriver *i2sp) {
+ size_t size = i2sp->config->size;
+
+ /* In 32 bit modes the DMA has to perform double operations because fetches
+ are always performed using 16 bit accesses.
+ DATLEN CHLEN SIZE
+ 00 (16) 0 (16) 16
+ 00 (16) 1 (32) 16
+ 01 (24) X 32
+ 10 (32) X 32
+ 11 (NA) X NA
+ */
+ if ((i2sp->config->i2scfgr & SPI_I2SCFGR_DATLEN) != 0)
+ size *= 2;
+
+ /* RX DMA setup.*/
+ if (NULL != i2sp->dmarx) {
+ dmaStreamSetMode(i2sp->dmarx, i2sp->rxdmamode);
+ dmaStreamSetPeripheral(i2sp->dmarx, &i2sp->spi->DR);
+ dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer);
+ dmaStreamSetTransactionSize(i2sp->dmarx, size);
+ dmaStreamEnable(i2sp->dmarx);
+ }
+
+ /* TX DMA setup.*/
+ if (NULL != i2sp->dmatx) {
+ dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode);
+ dmaStreamSetPeripheral(i2sp->dmatx, &i2sp->spi->DR);
+ dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer);
+ dmaStreamSetTransactionSize(i2sp->dmatx, size);
+ dmaStreamEnable(i2sp->dmatx);
+ }
+
+ /* Starting transfer.*/
+ i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE;
+}
+
+/**
+ * @brief Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ * was not active the function does nothing.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop_exchange(I2SDriver *i2sp) {
+
+ /* Stop TX DMA, if enabled.*/
+ if (NULL != i2sp->dmatx) {
+ dmaStreamDisable(i2sp->dmatx);
+
+ /* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory
+ to wait for TXE = 1 and BSY = 0.*/
+ while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE)
+ ;
+ }
+
+ /* Stop SPI/I2S peripheral.*/
+ i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
+
+ /* Stop RX DMA, if enabled.*/
+ if (NULL != i2sp->dmarx)
+ dmaStreamDisable(i2sp->dmarx);
+}
+
+#endif /* HAL_USE_I2S */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h
new file mode 100644
index 0000000000..9f46529c6c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h
@@ -0,0 +1,432 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPIv2/hal_i2s_lld.h
+ * @brief STM32 I2S subsystem low level driver header.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#ifndef HAL_I2S_LLD_H
+#define HAL_I2S_LLD_H
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Static I2S modes
+ * @{
+ */
+#define STM32_I2S_MODE_SLAVE 0
+#define STM32_I2S_MODE_MASTER 1
+#define STM32_I2S_MODE_RX 2
+#define STM32_I2S_MODE_TX 4
+#define STM32_I2S_MODE_RXTX (STM32_I2S_MODE_RX | \
+ STM32_I2S_MODE_TX)
+/** @} */
+
+/**
+ * @name Mode checks
+ * @{
+ */
+#define STM32_I2S_IS_MASTER(mode) ((mode) & STM32_I2S_MODE_MASTER)
+#define STM32_I2S_RX_ENABLED(mode) ((mode) & STM32_I2S_MODE_RX)
+#define STM32_I2S_TX_ENABLED(mode) ((mode) & STM32_I2S_MODE_TX)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief I2S1 driver enable switch.
+ * @details If set to @p TRUE the support for I2S1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI1) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI1 FALSE
+#endif
+
+/**
+ * @brief I2S2 driver enable switch.
+ * @details If set to @p TRUE the support for I2S2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI2) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI2 FALSE
+#endif
+
+/**
+ * @brief I2S3 driver enable switch.
+ * @details If set to @p TRUE the support for I2S3 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI3) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI3 FALSE
+#endif
+
+/**
+ * @brief I2S1 mode.
+ */
+#if !defined(STM32_I2S_SPI1_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief I2S2 mode.
+ */
+#if !defined(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief I2S3 mode.
+ */
+#if !defined(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief I2S1 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2S2 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2S3 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2S1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S DMA error hook.
+ */
+#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_I2S_USE_SPI1 && !STM32_SPI1_SUPPORTS_I2S
+#error "SPI1 does not support I2S mode"
+#endif
+
+#if STM32_I2S_USE_SPI2 && !STM32_SPI2_SUPPORTS_I2S
+#error "SPI2 does not support I2S mode"
+#endif
+
+#if STM32_I2S_USE_SPI3 && !STM32_SPI3_SUPPORTS_I2S
+#error "SPI3 does not support I2S mode"
+#endif
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#error "I2S1 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#error "I2S2 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) && \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#error "I2S3 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2
+#error "SPI2 not present in the selected device"
+#endif
+
+#if STM32_I2S_USE_SPI3 && !STM32_HAS_SPI3
+#error "SPI3 not present in the selected device"
+#endif
+
+#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3
+#error "I2S driver activated but no SPI peripheral assigned"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI2"
+#endif
+
+#if STM32_I2S_USE_SPI3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI3"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI1"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI2"
+#endif
+
+#if STM32_I2S_USE_SPI3 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI3"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_I2S_USE_SPI1 && (!defined(STM32_I2S_SPI1_RX_DMA_STREAM) || \
+ !defined(STM32_I2S_SPI1_TX_DMA_STREAM))
+#error "SPI1 DMA streams not defined"
+#endif
+
+#if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) || \
+ !defined(STM32_I2S_SPI2_TX_DMA_STREAM))
+#error "SPI2 DMA streams not defined"
+#endif
+
+#if STM32_I2S_USE_SPI3 && (!defined(STM32_I2S_SPI3_RX_DMA_STREAM) || \
+ !defined(STM32_I2S_SPI3_TX_DMA_STREAM))
+#error "SPI3 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 RX"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 TX"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 RX"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 TX"
+#endif
+
+#if STM32_I2S_USE_SPI3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 RX"
+#endif
+
+#if STM32_I2S_USE_SPI3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an I2S driver.
+ */
+typedef struct I2SDriver I2SDriver;
+
+/**
+ * @brief I2S notification callback type.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] offset offset in buffers of the data to read/write
+ * @param[in] n number of samples to read/write
+ */
+typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n);
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Transmission buffer pointer.
+ * @note Can be @p NULL if TX is not required.
+ */
+ const void *tx_buffer;
+ /**
+ * @brief Receive buffer pointer.
+ * @note Can be @p NULL if RX is not required.
+ */
+ void *rx_buffer;
+ /**
+ * @brief TX and RX buffers size as number of samples.
+ */
+ size_t size;
+ /**
+ * @brief Callback function called during streaming.
+ */
+ i2scallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Configuration of the I2SCFGR register.
+ * @details See the STM32 reference manual, this register is used for
+ * the I2S configuration, the following bits must not be
+ * specified because handled directly by the driver:
+ * - I2SMOD
+ * - I2SE
+ * - I2SCFG
+ * .
+ */
+ int16_t i2scfgr;
+ /**
+ * @brief Configuration of the I2SPR register.
+ * @details See the STM32 reference manual, this register is used for
+ * the I2S clock setup.
+ */
+ int16_t i2spr;
+} I2SConfig;
+
+/**
+ * @brief Structure representing an I2S driver.
+ */
+struct I2SDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2sstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2SConfig *config;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the SPIx registers block.
+ */
+ SPI_TypeDef *spi;
+ /**
+ * @brief Calculated part of the I2SCFGR register.
+ */
+ uint16_t cfg;
+ /**
+ * @brief Receive DMA stream or @p NULL.
+ */
+ const stm32_dma_stream_t *dmarx;
+ /**
+ * @brief Transmit DMA stream or @p NULL.
+ */
+ const stm32_dma_stream_t *dmatx;
+ /**
+ * @brief RX DMA mode bit mask.
+ */
+ uint32_t rxdmamode;
+ /**
+ * @brief TX DMA mode bit mask.
+ */
+ uint32_t txdmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_I2S_USE_SPI1 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD1;
+#endif
+
+#if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD2;
+#endif
+
+#if STM32_I2S_USE_SPI3 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2s_lld_init(void);
+ void i2s_lld_start(I2SDriver *i2sp);
+ void i2s_lld_stop(I2SDriver *i2sp);
+ void i2s_lld_start_exchange(I2SDriver *i2sp);
+ void i2s_lld_stop_exchange(I2SDriver *i2sp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2S */
+
+#endif /* HAL_I2S_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv2/spi_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c
similarity index 70%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv2/spi_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c
index 300ea68ce6..370502e91a 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv2/spi_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/SPIv2/spi_lld.c
+ * @file SPIv2/hal_spi_lld.c
* @brief STM32 SPI subsystem low level driver source.
*
* @addtogroup SPI
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_SPI || defined(__DOXYGEN__)
@@ -55,6 +54,30 @@
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \
STM32_SPI3_TX_DMA_CHN)
+#define SPI4_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM, \
+ STM32_SPI4_RX_DMA_CHN)
+
+#define SPI4_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM, \
+ STM32_SPI4_TX_DMA_CHN)
+
+#define SPI5_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM, \
+ STM32_SPI5_RX_DMA_CHN)
+
+#define SPI5_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM, \
+ STM32_SPI5_TX_DMA_CHN)
+
+#define SPI6_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM, \
+ STM32_SPI6_RX_DMA_CHN)
+
+#define SPI6_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM, \
+ STM32_SPI6_TX_DMA_CHN)
+
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -74,11 +97,26 @@ SPIDriver SPID2;
SPIDriver SPID3;
#endif
+/** @brief SPI4 driver identifier.*/
+#if STM32_SPI_USE_SPI4 || defined(__DOXYGEN__)
+SPIDriver SPID4;
+#endif
+
+/** @brief SPI5 driver identifier.*/
+#if STM32_SPI_USE_SPI5 || defined(__DOXYGEN__)
+SPIDriver SPID5;
+#endif
+
+/** @brief SPI6 driver identifier.*/
+#if STM32_SPI_USE_SPI6 || defined(__DOXYGEN__)
+SPIDriver SPID6;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
-static uint16_t dummytx;
+static const uint16_t dummytx = 0xFFFFU;
static uint16_t dummyrx;
/*===========================================================================*/
@@ -146,8 +184,6 @@ static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
*/
void spi_lld_init(void) {
- dummytx = 0xFFFF;
-
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
@@ -201,6 +237,60 @@ void spi_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
+
+#if STM32_SPI_USE_SPI4
+ spiObjectInit(&SPID4);
+ SPID4.spi = SPI4;
+ SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);
+ SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);
+ SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+ SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI5
+ spiObjectInit(&SPID5);
+ SPID5.spi = SPI5;
+ SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);
+ SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);
+ SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+ SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI6
+ spiObjectInit(&SPID6);
+ SPID6.spi = SPI6;
+ SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);
+ SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);
+ SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+ SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#endif
}
/**
@@ -217,52 +307,100 @@ void spi_lld_start(SPIDriver *spip) {
if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI1(FALSE);
}
#endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI2(FALSE);
}
#endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI3(FALSE);
}
#endif
+#if STM32_SPI_USE_SPI4
+ if (&SPID4 == spip) {
+ bool b;
+ b = dmaStreamAllocate(spip->dmarx,
+ STM32_SPI_SPI4_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(spip->dmatx,
+ STM32_SPI_SPI4_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableSPI4(FALSE);
+ }
+#endif
+#if STM32_SPI_USE_SPI5
+ if (&SPID5 == spip) {
+ bool b;
+ b = dmaStreamAllocate(spip->dmarx,
+ STM32_SPI_SPI5_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(spip->dmatx,
+ STM32_SPI_SPI5_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableSPI5(FALSE);
+ }
+#endif
+#if STM32_SPI_USE_SPI6
+ if (&SPID6 == spip) {
+ bool b;
+ b = dmaStreamAllocate(spip->dmarx,
+ STM32_SPI_SPI6_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(spip->dmatx,
+ STM32_SPI_SPI6_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableSPI6(FALSE);
+ }
+#endif
/* DMA setup.*/
dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR);
@@ -285,10 +423,10 @@ void spi_lld_start(SPIDriver *spip) {
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
}
+
/* SPI setup and enable.*/
- spip->spi->CR1 = 0;
- spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
- SPI_CR1_SSI;
+ spip->spi->CR1 &= ~SPI_CR1_SPE;
+ spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR;
spip->spi->CR2 = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |
SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
spip->spi->CR1 |= SPI_CR1_SPE;
@@ -307,8 +445,9 @@ void spi_lld_stop(SPIDriver *spip) {
if (spip->state == SPI_READY) {
/* SPI disable.*/
- spip->spi->CR1 = 0;
- spip->spi->CR2 = 0;
+ spip->spi->CR1 &= ~SPI_CR1_SPE;
+ spip->spi->CR1 = 0;
+ spip->spi->CR2 = 0;
dmaStreamRelease(spip->dmarx);
dmaStreamRelease(spip->dmatx);
@@ -323,6 +462,18 @@ void spi_lld_stop(SPIDriver *spip) {
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip)
rccDisableSPI3(FALSE);
+#endif
+#if STM32_SPI_USE_SPI4
+ if (&SPID4 == spip)
+ rccDisableSPI4(FALSE);
+#endif
+#if STM32_SPI_USE_SPI5
+ if (&SPID5 == spip)
+ rccDisableSPI5(FALSE);
+#endif
+#if STM32_SPI_USE_SPI6
+ if (&SPID6 == spip)
+ rccDisableSPI6(FALSE);
#endif
}
}
@@ -365,6 +516,8 @@ void spi_lld_unselect(SPIDriver *spip) {
*/
void spi_lld_ignore(SPIDriver *spip, size_t n) {
+ osalDbgAssert(n < 65536, "unsupported DMA transfer size");
+
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
@@ -395,9 +548,11 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
void spi_lld_exchange(SPIDriver *spip, size_t n,
const void *txbuf, void *rxbuf) {
+ osalDbgAssert(n < 65536, "unsupported DMA transfer size");
+
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
- dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
+ dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
@@ -422,6 +577,8 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
*/
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+ osalDbgAssert(n < 65536, "unsupported DMA transfer size");
+
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
@@ -449,6 +606,8 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
*/
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+ osalDbgAssert(n < 65536, "unsupported DMA transfer size");
+
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv2/spi_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.h
similarity index 57%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv2/spi_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.h
index 9dfe2f2424..cc5e74d57e 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/SPIv2/spi_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/SPIv2/spi_lld.h
+ * @file SPIv2/hal_spi_lld.h
* @brief STM32 SPI subsystem low level driver header.
*
* @addtogroup SPI
* @{
*/
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
+#ifndef HAL_SPI_LLD_H
+#define HAL_SPI_LLD_H
#if HAL_USE_SPI || defined(__DOXYGEN__)
@@ -66,6 +66,33 @@
#define STM32_SPI_USE_SPI3 FALSE
#endif
+/**
+ * @brief SPI4 driver enable switch.
+ * @details If set to @p TRUE the support for SPI4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI4 FALSE
+#endif
+
+/**
+ * @brief SPI5 driver enable switch.
+ * @details If set to @p TRUE the support for SPI5 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI5 FALSE
+#endif
+
+/**
+ * @brief SPI6 driver enable switch.
+ * @details If set to @p TRUE the support for SPI6 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI6 FALSE
+#endif
+
/**
* @brief SPI1 interrupt priority level setting.
*/
@@ -87,6 +114,27 @@
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#endif
+/**
+ * @brief SPI4 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief SPI5 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief SPI6 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10
+#endif
+
/**
* @brief SPI1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
@@ -118,83 +166,41 @@
#endif
/**
- * @brief SPI DMA error hook.
- */
-#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief DMA stream used for SPI1 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
-#endif
-
-/**
- * @brief DMA stream used for SPI1 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
+ * @brief SPI4 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA streams but
+ * because of the streams ordering the RX stream has always priority
+ * over the TX stream.
*/
-#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
#endif
/**
- * @brief DMA stream used for SPI2 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
+ * @brief SPI5 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA streams but
+ * because of the streams ordering the RX stream has always priority
+ * over the TX stream.
*/
-#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
#endif
/**
- * @brief DMA stream used for SPI2 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
+ * @brief SPI6 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA streams but
+ * because of the streams ordering the RX stream has always priority
+ * over the TX stream.
*/
-#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI6_DMA_PRIORITY 1
#endif
/**
- * @brief DMA stream used for SPI3 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
+ * @brief SPI DMA error hook.
*/
-#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
#endif
-
-/**
- * @brief DMA stream used for SPI3 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#endif
-
-#else /* !STM32_ADVANCED_DMA */
-
-#if defined(STM32F0XX)
-/* Fixed values for STM32F0xx devices.*/
-#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#endif /* defined(STM32F0XX) */
-
-#if defined(STM32F30X) || defined(STM32F37X)
-/* Fixed values for STM32F3xx devices.*/
-#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
-#endif /* defined(STM32F30X) */
-
-#endif /* !STM32_ADVANCED_DMA*/
/** @} */
/*===========================================================================*/
@@ -213,25 +219,53 @@
#error "SPI3 not present in the selected device"
#endif
-#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3
+#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4
+#error "SPI4 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5
+#error "SPI5 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6
+#error "SPI6 not present in the selected device"
+#endif
+
+#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \
+ !STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6
#error "SPI driver activated but no SPI peripheral assigned"
#endif
#if STM32_SPI_USE_SPI1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI1"
#endif
#if STM32_SPI_USE_SPI2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI2"
#endif
#if STM32_SPI_USE_SPI3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI3"
#endif
+#if STM32_SPI_USE_SPI4 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI4"
+#endif
+
+#if STM32_SPI_USE_SPI5 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI5"
+#endif
+
+#if STM32_SPI_USE_SPI6 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI6"
+#endif
+
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI1"
@@ -247,6 +281,56 @@
#error "Invalid DMA priority assigned to SPI3"
#endif
+#if STM32_SPI_USE_SPI4 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI4"
+#endif
+
+#if STM32_SPI_USE_SPI5 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI5"
+#endif
+
+#if STM32_SPI_USE_SPI6 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI6"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI1_TX_DMA_STREAM))
+#error "SPI1 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI2_TX_DMA_STREAM))
+#error "SPI2 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI3_TX_DMA_STREAM))
+#error "SPI3 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI4_TX_DMA_STREAM))
+#error "SPI4 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI5_TX_DMA_STREAM))
+#error "SPI5 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) || \
+ !defined(STM32_SPI_SPI6_TX_DMA_STREAM))
+#error "SPI6 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 RX"
@@ -277,6 +361,37 @@
#error "invalid DMA stream associated to SPI3 TX"
#endif
+#if STM32_SPI_USE_SPI4 && \
+ !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI4 RX"
+#endif
+
+#if STM32_SPI_USE_SPI4 && \
+ !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI4 TX"
+#endif
+
+#if STM32_SPI_USE_SPI5 && \
+ !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI5 RX"
+#endif
+
+#if STM32_SPI_USE_SPI5 && \
+ !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI5 TX"
+#endif
+
+#if STM32_SPI_USE_SPI6 && \
+ !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI6 RX"
+#endif
+
+#if STM32_SPI_USE_SPI6 && \
+ !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI6 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
@@ -326,7 +441,7 @@ typedef struct {
} SPIConfig;
/**
- * @brief Structure representing a SPI driver.
+ * @brief Structure representing an SPI driver.
*/
struct SPIDriver {
/**
@@ -339,19 +454,15 @@ struct SPIDriver {
const SPIConfig *config;
#if SPI_USE_WAIT || defined(__DOXYGEN__)
/**
- * @brief Waiting thread.
+ * @brief Waiting thread.
*/
- Thread *thread;
+ thread_reference_t thread;
#endif /* SPI_USE_WAIT */
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
- * @brief Mutex protecting the bus.
+ * @brief Mutex protecting the peripheral.
*/
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
+ mutex_t mutex;
#endif /* SPI_USE_MUTUAL_EXCLUSION */
#if defined(SPI_DRIVER_EXT_FIELDS)
SPI_DRIVER_EXT_FIELDS
@@ -362,19 +473,19 @@ struct SPIDriver {
*/
SPI_TypeDef *spi;
/**
- * @brief Receive DMA stream.
+ * @brief Receive DMA stream.
*/
const stm32_dma_stream_t *dmarx;
/**
- * @brief Transmit DMA stream.
+ * @brief Transmit DMA stream.
*/
const stm32_dma_stream_t *dmatx;
/**
- * @brief RX DMA mode bit mask.
+ * @brief RX DMA mode bit mask.
*/
uint32_t rxdmamode;
/**
- * @brief TX DMA mode bit mask.
+ * @brief TX DMA mode bit mask.
*/
uint32_t txdmamode;
};
@@ -399,6 +510,18 @@ extern SPIDriver SPID2;
extern SPIDriver SPID3;
#endif
+#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
+extern SPIDriver SPID4;
+#endif
+
+#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
+extern SPIDriver SPID5;
+#endif
+
+#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
+extern SPIDriver SPID6;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -419,6 +542,6 @@ extern "C" {
#endif /* HAL_USE_SPI */
-#endif /* _SPI_LLD_H_ */
+#endif /* HAL_SPI_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/driver.mk
new file mode 100644
index 0000000000..2fcf8995b3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/driver.mk
@@ -0,0 +1,19 @@
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
+
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
+endif
+ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c
+endif
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/gpt_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
similarity index 67%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/gpt_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
index 60ad0299b8..6b3cc85b20 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/gpt_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/gpt_lld.c
+ * @file TIMv1/hal_gpt_lld.c
* @brief STM32 GPT subsystem low level driver source.
*
* @addtogroup GPT
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_GPT || defined(__DOXYGEN__)
@@ -139,26 +138,12 @@ GPTDriver GPTD14;
/* Driver local functions. */
/*===========================================================================*/
-/**
- * @brief Shared IRQ handler.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
- gptp->tim->SR = 0;
- if (gptp->state == GPT_ONESHOT) {
- gptp->state = GPT_READY; /* Back in GPT_READY state. */
- gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */
- }
- gptp->config->callback(gptp);
-}
-
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
-#if STM32_GPT_USE_TIM1
+#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
#if !defined(STM32_TIM1_UP_HANDLER)
#error "STM32_TIM1_UP_HANDLER not defined"
#endif
@@ -167,17 +152,19 @@ static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM1 */
-#if STM32_GPT_USE_TIM2
+#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
#if !defined(STM32_TIM2_HANDLER)
#error "STM32_TIM2_HANDLER not defined"
#endif
@@ -186,17 +173,19 @@ CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM2 */
-#if STM32_GPT_USE_TIM3
+#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
#if !defined(STM32_TIM3_HANDLER)
#error "STM32_TIM3_HANDLER not defined"
#endif
@@ -205,17 +194,19 @@ CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM3 */
-#if STM32_GPT_USE_TIM4
+#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
#if !defined(STM32_TIM4_HANDLER)
#error "STM32_TIM4_HANDLER not defined"
#endif
@@ -224,17 +215,19 @@ CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM4 */
-#if STM32_GPT_USE_TIM5
+#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
#if !defined(STM32_TIM5_HANDLER)
#error "STM32_TIM5_HANDLER not defined"
#endif
@@ -243,17 +236,19 @@ CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD5);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM5 */
-#if STM32_GPT_USE_TIM6
+#if STM32_GPT_USE_TIM6 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM6_SUPPRESS_ISR)
#if !defined(STM32_TIM6_HANDLER)
#error "STM32_TIM6_HANDLER not defined"
#endif
@@ -262,17 +257,19 @@ CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM6_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM6_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD6);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM6_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM6 */
-#if STM32_GPT_USE_TIM7
+#if STM32_GPT_USE_TIM7 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM7_SUPPRESS_ISR)
#if !defined(STM32_TIM7_HANDLER)
#error "STM32_TIM7_HANDLER not defined"
#endif
@@ -281,17 +278,19 @@ CH_IRQ_HANDLER(STM32_TIM6_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM7_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM7_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD7);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM7_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM7 */
-#if STM32_GPT_USE_TIM8
+#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
#if !defined(STM32_TIM8_UP_HANDLER)
#error "STM32_TIM8_UP_HANDLER not defined"
#endif
@@ -300,17 +299,19 @@ CH_IRQ_HANDLER(STM32_TIM7_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD8);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM8 */
-#if STM32_GPT_USE_TIM9
+#if STM32_GPT_USE_TIM9 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
#if !defined(STM32_TIM9_HANDLER)
#error "STM32_TIM9_HANDLER not defined"
#endif
@@ -319,17 +320,19 @@ CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD9);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM9 */
-#if STM32_GPT_USE_TIM11
+#if STM32_GPT_USE_TIM11 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM11_SUPPRESS_ISR)
#if !defined(STM32_TIM11_HANDLER)
#error "STM32_TIM11_HANDLER not defined"
#endif
@@ -338,17 +341,19 @@ CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM11_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM11_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD11);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM11_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM11 */
-#if STM32_GPT_USE_TIM12
+#if STM32_GPT_USE_TIM12 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM12_SUPPRESS_ISR)
#if !defined(STM32_TIM12_HANDLER)
#error "STM32_TIM12_HANDLER not defined"
#endif
@@ -357,17 +362,19 @@ CH_IRQ_HANDLER(STM32_TIM11_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM12_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD12);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM12_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM12 */
-#if STM32_GPT_USE_TIM14
+#if STM32_GPT_USE_TIM14 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM14_SUPPRESS_ISR)
#if !defined(STM32_TIM14_HANDLER)
#error "STM32_TIM14_HANDLER not defined"
#endif
@@ -376,14 +383,15 @@ CH_IRQ_HANDLER(STM32_TIM12_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM14_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD14);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM14_SUPPRESS_ISR) */
#endif /* STM32_GPT_USE_TIM14 */
/*===========================================================================*/
@@ -486,8 +494,9 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD1 == gptp) {
rccEnableTIM1(FALSE);
rccResetTIM1();
- nvicEnableVector(STM32_TIM1_UP_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY);
+#endif
#if defined(STM32_TIM1CLK)
gptp->clock = STM32_TIM1CLK;
#else
@@ -495,31 +504,49 @@ void gpt_lld_start(GPTDriver *gptp) {
#endif
}
#endif
+
#if STM32_GPT_USE_TIM2
if (&GPTD2 == gptp) {
rccEnableTIM2(FALSE);
rccResetTIM2();
- nvicEnableVector(STM32_TIM2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY));
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM2CLK)
+ gptp->clock = STM32_TIM2CLK;
+#else
gptp->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_GPT_USE_TIM3
if (&GPTD3 == gptp) {
rccEnableTIM3(FALSE);
rccResetTIM3();
- nvicEnableVector(STM32_TIM3_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY));
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM3CLK)
+ gptp->clock = STM32_TIM3CLK;
+#else
gptp->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_GPT_USE_TIM4
if (&GPTD4 == gptp) {
rccEnableTIM4(FALSE);
rccResetTIM4();
- nvicEnableVector(STM32_TIM4_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY));
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM4CLK)
+ gptp->clock = STM32_TIM4CLK;
+#else
gptp->clock = STM32_TIMCLK1;
+#endif
}
#endif
@@ -527,9 +554,14 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD5 == gptp) {
rccEnableTIM5(FALSE);
rccResetTIM5();
- nvicEnableVector(STM32_TIM5_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY));
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM5CLK)
+ gptp->clock = STM32_TIM5CLK;
+#else
gptp->clock = STM32_TIMCLK1;
+#endif
}
#endif
@@ -537,9 +569,14 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD6 == gptp) {
rccEnableTIM6(FALSE);
rccResetTIM6();
- nvicEnableVector(STM32_TIM6_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM6_IRQ_PRIORITY));
+#if !defined(STM32_TIM6_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM6CLK)
+ gptp->clock = STM32_TIM6CLK;
+#else
gptp->clock = STM32_TIMCLK1;
+#endif
}
#endif
@@ -547,9 +584,14 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD7 == gptp) {
rccEnableTIM7(FALSE);
rccResetTIM7();
- nvicEnableVector(STM32_TIM7_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM7_IRQ_PRIORITY));
+#if !defined(STM32_TIM7_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM7CLK)
+ gptp->clock = STM32_TIM7CLK;
+#else
gptp->clock = STM32_TIMCLK1;
+#endif
}
#endif
@@ -557,8 +599,9 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD8 == gptp) {
rccEnableTIM8(FALSE);
rccResetTIM8();
- nvicEnableVector(STM32_TIM8_UP_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY));
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY);
+#endif
#if defined(STM32_TIM8CLK)
gptp->clock = STM32_TIM8CLK;
#else
@@ -571,9 +614,14 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD9 == gptp) {
rccEnableTIM9(FALSE);
rccResetTIM9();
- nvicEnableVector(STM32_TIM9_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM9_IRQ_PRIORITY));
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM9CLK)
+ gptp->clock = STM32_TIM9CLK;
+#else
gptp->clock = STM32_TIMCLK2;
+#endif
}
#endif
@@ -581,9 +629,14 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD11 == gptp) {
rccEnableTIM11(FALSE);
rccResetTIM11();
- nvicEnableVector(STM32_TIM11_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM11_IRQ_PRIORITY));
+#if !defined(STM32_TIM11_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM11CLK)
+ gptp->clock = STM32_TIM11CLK;
+#else
gptp->clock = STM32_TIMCLK2;
+#endif
}
#endif
@@ -591,9 +644,14 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD12 == gptp) {
rccEnableTIM12(FALSE);
rccResetTIM12();
- nvicEnableVector(STM32_TIM12_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM12_IRQ_PRIORITY));
+#if !defined(STM32_TIM12_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM12CLK)
+ gptp->clock = STM32_TIM12CLK;
+#else
gptp->clock = STM32_TIMCLK1;
+#endif
}
#endif
@@ -601,25 +659,30 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD14 == gptp) {
rccEnableTIM14(FALSE);
rccResetTIM14();
- nvicEnableVector(STM32_TIM14_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_GPT_TIM14_IRQ_PRIORITY));
+#if !defined(STM32_TIM14_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM14CLK)
+ gptp->clock = STM32_TIM14CLK;
+#else
gptp->clock = STM32_TIMCLK1;
+#endif
}
#endif
}
/* Prescaler value calculation.*/
psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
- chDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
- "gpt_lld_start(), #1", "invalid frequency");
+ osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
+ "invalid frequency");
/* Timer configuration.*/
- gptp->tim->CR1 = 0; /* Initially stopped. */
- gptp->tim->CR2 = STM32_TIM_CR2_CCDS; /* DMA on UE (if any). */
- gptp->tim->PSC = psc; /* Prescaler value. */
+ gptp->tim->CR1 = 0; /* Initially stopped. */
+ gptp->tim->CR2 = gptp->config->cr2;
+ gptp->tim->PSC = psc; /* Prescaler value. */
+ gptp->tim->SR = 0; /* Clear pending IRQs. */
gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
- STM32_TIM_DIER_IRQ_MASK;
- gptp->tim->SR = 0; /* Clear pending IRQs. */
+ ~STM32_TIM_DIER_IRQ_MASK;
}
/**
@@ -632,79 +695,114 @@ void gpt_lld_start(GPTDriver *gptp) {
void gpt_lld_stop(GPTDriver *gptp) {
if (gptp->state == GPT_READY) {
- gptp->tim->CR1 = 0; /* Timer disabled. */
+ gptp->tim->CR1 = 0; /* Timer disabled. */
gptp->tim->DIER = 0; /* All IRQs disabled. */
- gptp->tim->SR = 0; /* Clear pending IRQs. */
+ gptp->tim->SR = 0; /* Clear pending IRQs. */
#if STM32_GPT_USE_TIM1
if (&GPTD1 == gptp) {
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM1_UP_NUMBER);
+#endif
rccDisableTIM1(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM2
if (&GPTD2 == gptp) {
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM2_NUMBER);
+#endif
rccDisableTIM2(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM3
if (&GPTD3 == gptp) {
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM3_NUMBER);
+#endif
rccDisableTIM3(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM4
if (&GPTD4 == gptp) {
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM4_NUMBER);
+#endif
rccDisableTIM4(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM5
if (&GPTD5 == gptp) {
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM5_NUMBER);
+#endif
rccDisableTIM5(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM6
if (&GPTD6 == gptp) {
+#if !defined(STM32_TIM6_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM6_NUMBER);
+#endif
rccDisableTIM6(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM7
if (&GPTD7 == gptp) {
+#if !defined(STM32_TIM7_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM7_NUMBER);
+#endif
rccDisableTIM7(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM8
if (&GPTD8 == gptp) {
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM8_UP_NUMBER);
+#endif
rccDisableTIM8(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM9
if (&GPTD9 == gptp) {
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM9_NUMBER);
+#endif
rccDisableTIM9(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM11
if (&GPTD11 == gptp) {
+#if !defined(STM32_TIM11_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM11_NUMBER);
+#endif
rccDisableTIM11(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM12
if (&GPTD12 == gptp) {
+#if !defined(STM32_TIM12_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM12_NUMBER);
+#endif
rccDisableTIM12(FALSE);
}
#endif
+
#if STM32_GPT_USE_TIM14
if (&GPTD14 == gptp) {
+#if !defined(STM32_TIM14_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM14_NUMBER);
+#endif
rccDisableTIM14(FALSE);
}
#endif
@@ -721,16 +819,17 @@ void gpt_lld_stop(GPTDriver *gptp) {
*/
void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
- gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */
- gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
- gptp->tim->CNT = 0; /* Reset counter. */
+ gptp->tim->ARR = (uint32_t)(interval); /* Time constant. */
+ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
+ gptp->tim->CNT = 0; /* Reset counter. */
/* NOTE: After generating the UG event it takes several clock cycles before
- SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
+ SR bit 0 goes to 1. This is why the clearing of CNT has been inserted
before the clearing of SR, to give it some time.*/
- gptp->tim->SR = 0; /* Clear pending IRQs. */
- gptp->tim->DIER |= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
- gptp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
+ gptp->tim->SR = 0; /* Clear pending IRQs. */
+ if (NULL != gptp->config->callback)
+ gptp->tim->DIER |= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
+ gptp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
}
/**
@@ -742,8 +841,8 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
*/
void gpt_lld_stop_timer(GPTDriver *gptp) {
- gptp->tim->CR1 = 0; /* Initially stopped. */
- gptp->tim->SR = 0; /* Clear pending IRQs. */
+ gptp->tim->CR1 = 0; /* Initially stopped. */
+ gptp->tim->SR = 0; /* Clear pending IRQs. */
/* All interrupts disabled.*/
gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
@@ -762,12 +861,30 @@ void gpt_lld_stop_timer(GPTDriver *gptp) {
*/
void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
- gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */
- gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
- gptp->tim->SR = 0; /* Clear pending IRQs. */
- gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
+ gptp->tim->ARR = (uint32_t)(interval); /* Time constant. */
+ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
+ gptp->tim->SR = 0; /* Clear pending IRQs. */
+ gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
;
+ gptp->tim->SR = 0; /* Clear pending IRQs. */
+}
+
+/**
+ * @brief Shared IRQ handler.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_serve_interrupt(GPTDriver *gptp) {
+
+ gptp->tim->SR = 0;
+ if (gptp->state == GPT_ONESHOT) {
+ gptp->state = GPT_READY; /* Back in GPT_READY state. */
+ gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */
+ }
+ gptp->config->callback(gptp);
}
#endif /* HAL_USE_GPT */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/gpt_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.h
similarity index 73%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/gpt_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.h
index f303a1bd18..951a7281b8 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/gpt_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/gpt_lld.h
+ * @file TIMv1/hal_gpt_lld.h
* @brief STM32 GPT subsystem low level driver header.
*
* @addtogroup GPT
* @{
*/
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
+#ifndef HAL_GPT_LLD_H
+#define HAL_GPT_LLD_H
#include "stm32_tim.h"
@@ -295,63 +295,161 @@
#error "GPT driver activated but no TIM peripheral assigned"
#endif
-#if STM32_GPT_USE_TIM1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY)
+/* Checks on allocation of TIMx units.*/
+#if STM32_GPT_USE_TIM1
+#if defined(STM32_TIM1_IS_USED)
+#error "GPTD1 requires TIM1 but the timer is already used"
+#else
+#define STM32_TIM1_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM2
+#if defined(STM32_TIM2_IS_USED)
+#error "GPTD2 requires TIM2 but the timer is already used"
+#else
+#define STM32_TIM2_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM3
+#if defined(STM32_TIM3_IS_USED)
+#error "GPTD3 requires TIM3 but the timer is already used"
+#else
+#define STM32_TIM3_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM4
+#if defined(STM32_TIM4_IS_USED)
+#error "GPTD4 requires TIM4 but the timer is already used"
+#else
+#define STM32_TIM4_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM5
+#if defined(STM32_TIM5_IS_USED)
+#error "GPTD5 requires TIM5 but the timer is already used"
+#else
+#define STM32_TIM5_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM6
+#if defined(STM32_TIM6_IS_USED)
+#error "GPTD6 requires TIM6 but the timer is already used"
+#else
+#define STM32_TIM6_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM7
+#if defined(STM32_TIM7_IS_USED)
+#error "GPTD7 requires TIM7 but the timer is already used"
+#else
+#define STM32_TIM7_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM8
+#if defined(STM32_TIM8_IS_USED)
+#error "GPTD8 requires TIM8 but the timer is already used"
+#else
+#define STM32_TIM8_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM9
+#if defined(STM32_TIM9_IS_USED)
+#error "GPTD9 requires TIM9 but the timer is already used"
+#else
+#define STM32_TIM9_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM11
+#if defined(STM32_TIM11_IS_USED)
+#error "GPTD11 requires TIM11 but the timer is already used"
+#else
+#define STM32_TIM11_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM12
+#if defined(STM32_TIM12_IS_USED)
+#error "GPTD12 requires TIM12 but the timer is already used"
+#else
+#define STM32_TIM12_IS_USED
+#endif
+#endif
+
+#if STM32_GPT_USE_TIM14
+#if defined(STM32_TIM14_IS_USED)
+#error "GPTD14 requires TIM14 but the timer is already used"
+#else
+#define STM32_TIM14_IS_USED
+#endif
+#endif
+
+/* IRQ priority checks.*/
+#if STM32_GPT_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM1"
#endif
-#if STM32_GPT_USE_TIM2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM2"
#endif
-#if STM32_GPT_USE_TIM3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM3"
#endif
-#if STM32_GPT_USE_TIM4 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM4 && !defined(STM32_TIM_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM4"
#endif
-#if STM32_GPT_USE_TIM5 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM5"
#endif
-#if STM32_GPT_USE_TIM6 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM6 && !defined(STM32_TIM6_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM6"
#endif
-#if STM32_GPT_USE_TIM7 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM7 && !defined(STM32_TIM7_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM7"
#endif
-#if STM32_GPT_USE_TIM8 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM8"
#endif
-#if STM32_GPT_USE_TIM9 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM9"
#endif
-#if STM32_GPT_USE_TIM11 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM11 && !defined(STM32_TIM11_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM11"
#endif
-#if STM32_GPT_USE_TIM12 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM12 && !defined(STM32_TIM12_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM12"
#endif
-#if STM32_GPT_USE_TIM14 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY)
+#if STM32_GPT_USE_TIM14 && !defined(STM32_TIM14_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM14"
#endif
@@ -383,9 +481,16 @@ typedef struct {
/**
* @brief Timer callback pointer.
* @note This callback is invoked on GPT counter events.
+ * @note This callback can be set to @p NULL but in that case the
+ * one-shot mode cannot be used.
*/
gptcallback_t callback;
/* End of the mandatory fields.*/
+ /**
+ * @brief TIM CR2 register initialization data.
+ * @note The value of this field should normally be equal to zero.
+ */
+ uint32_t cr2;
/**
* @brief TIM DIER register initialization data.
* @note The value of this field should normally be equal to zero.
@@ -427,19 +532,42 @@ struct GPTDriver {
/**
* @brief Changes the interval of GPT peripheral.
* @details This function changes the interval of a running GPT unit.
- * @pre The GPT unit must have been activated using @p gptStart().
- * @pre The GPT unit must have been running in continuous mode using
- * @p gptStartContinuous().
+ * @pre The GPT unit must be running in continuous mode.
* @post The GPT unit interval is changed to the new value.
* @note The function has effect at the next cycle start.
*
* @param[in] gptp pointer to a @p GPTDriver object
* @param[in] interval new cycle time in timer ticks
+ *
* @notapi
*/
#define gpt_lld_change_interval(gptp, interval) \
((gptp)->tim->ARR = (uint32_t)((interval) - 1))
+/**
+ * @brief Returns the interval of GPT peripheral.
+ * @pre The GPT unit must be running in continuous mode.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @return The current interval.
+ *
+ * @notapi
+ */
+#define gpt_lld_get_interval(gptp) ((gptcnt_t)(gptp)->tim->ARR + 1)
+
+/**
+ * @brief Returns the counter value of GPT peripheral.
+ * @pre The GPT unit must be running in continuous mode.
+ * @note The nature of the counter is not defined, it may count upward
+ * or downward, it could be continuously running or not.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @return The current counter value.
+ *
+ * @notapi
+ */
+#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->tim->CNT)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
@@ -501,12 +629,13 @@ extern "C" {
void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
void gpt_lld_stop_timer(GPTDriver *gptp);
void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
+ void gpt_lld_serve_interrupt(GPTDriver *gptp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_GPT */
-#endif /* _GPT_LLD_H_ */
+#endif /* HAL_GPT_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/icu_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c
similarity index 62%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/icu_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c
index 2ceeaca363..e0e5d9dad4 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/icu_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,14 +19,13 @@
*/
/**
- * @file STM32/icu_lld.c
+ * @file TIMv1/hal_icu_lld.c
* @brief STM32 ICU subsystem low level driver header.
*
* @addtogroup ICU
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_ICU || defined(__DOXYGEN__)
@@ -103,55 +102,63 @@ ICUDriver ICUD9;
/* Driver local functions. */
/*===========================================================================*/
-/**
- * @brief Shared IRQ handler.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
- uint16_t sr;
+static bool icu_lld_wait_edge(ICUDriver *icup) {
+ uint32_t sr;
+ bool result;
- sr = icup->tim->SR;
- sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
- icup->tim->SR = ~sr;
+ /* Polled mode so re-enabling the interrupts while the operation is
+ performed.*/
+ osalSysUnlock();
+
+ /* Polling the right bit depending on the input channel.*/
if (icup->config->channel == ICU_CHANNEL_1) {
- if ((sr & STM32_TIM_SR_CC1IF) != 0)
- _icu_isr_invoke_period_cb(icup);
- if ((sr & STM32_TIM_SR_CC2IF) != 0)
- _icu_isr_invoke_width_cb(icup);
- } else {
- if ((sr & STM32_TIM_SR_CC1IF) != 0)
- _icu_isr_invoke_width_cb(icup);
- if ((sr & STM32_TIM_SR_CC2IF) != 0)
- _icu_isr_invoke_period_cb(icup);
+ /* Waiting for an edge.*/
+ while (((sr = icup->tim->SR) &
+ (STM32_TIM_SR_CC1IF | STM32_TIM_SR_UIF)) == 0)
+ ;
}
- if ((sr & STM32_TIM_SR_UIF) != 0)
- _icu_isr_invoke_overflow_cb(icup);
+ else {
+ /* Waiting for an edge.*/
+ while (((sr = icup->tim->SR) &
+ (STM32_TIM_SR_CC2IF | STM32_TIM_SR_UIF)) == 0)
+ ;
+ }
+
+ /* Edge or overflow?*/
+ result = (sr & STM32_TIM_SR_UIF) != 0 ? true : false;
+
+ /* Done, disabling interrupts again.*/
+ osalSysLock();
+
+ /* Resetting all flags.*/
+ icup->tim->SR &= ~(STM32_TIM_SR_CC1IF |
+ STM32_TIM_SR_CC2IF |
+ STM32_TIM_SR_UIF);
+
+ return result;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
-#if STM32_ICU_USE_TIM1
+#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
#if !defined(STM32_TIM1_UP_HANDLER)
#error "STM32_TIM1_UP_HANDLER not defined"
#endif
/**
* @brief TIM1 compare interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#if !defined(STM32_TIM1_CC_HANDLER)
@@ -159,129 +166,121 @@ CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
#endif
/**
* @brief TIM1 compare interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
#endif /* STM32_ICU_USE_TIM1 */
-#if STM32_ICU_USE_TIM2
+#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
#if !defined(STM32_TIM2_HANDLER)
#error "STM32_TIM2_HANDLER not defined"
#endif
/**
* @brief TIM2 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
#endif /* STM32_ICU_USE_TIM2 */
-#if STM32_ICU_USE_TIM3
+#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
#if !defined(STM32_TIM3_HANDLER)
#error "STM32_TIM3_HANDLER not defined"
#endif
/**
* @brief TIM3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
#endif /* STM32_ICU_USE_TIM3 */
-#if STM32_ICU_USE_TIM4
+#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
#if !defined(STM32_TIM4_HANDLER)
#error "STM32_TIM4_HANDLER not defined"
#endif
/**
* @brief TIM4 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
#endif /* STM32_ICU_USE_TIM4 */
-#if STM32_ICU_USE_TIM5
+#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
#if !defined(STM32_TIM5_HANDLER)
#error "STM32_TIM5_HANDLER not defined"
#endif
/**
* @brief TIM5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD5);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
#endif /* STM32_ICU_USE_TIM5 */
-#if STM32_ICU_USE_TIM8
+#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
#if !defined(STM32_TIM8_UP_HANDLER)
#error "STM32_TIM8_UP_HANDLER not defined"
#endif
/**
* @brief TIM8 compare interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD8);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#if !defined(STM32_TIM8_CC_HANDLER)
@@ -289,42 +288,39 @@ CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
#endif
/**
* @brief TIM8 compare interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD8);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
#endif /* STM32_ICU_USE_TIM8 */
-#if STM32_ICU_USE_TIM9
+#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
#if !defined(STM32_TIM9_HANDLER)
#error "STM32_TIM9_HANDLER not defined"
#endif
/**
* @brief TIM9 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD9);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
#endif /* STM32_ICU_USE_TIM9 */
/*===========================================================================*/
@@ -391,9 +387,9 @@ void icu_lld_init(void) {
void icu_lld_start(ICUDriver *icup) {
uint32_t psc;
- chDbgAssert((icup->config->channel == ICU_CHANNEL_1) ||
- (icup->config->channel == ICU_CHANNEL_2),
- "icu_lld_start(), #1", "invalid input");
+ osalDbgAssert((icup->config->channel == ICU_CHANNEL_1) ||
+ (icup->config->channel == ICU_CHANNEL_2),
+ "invalid input");
if (icup->state == ICU_STOP) {
/* Clock activation and timer reset.*/
@@ -401,10 +397,10 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD1 == icup) {
rccEnableTIM1(FALSE);
rccResetTIM1();
- nvicEnableVector(STM32_TIM1_UP_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
- nvicEnableVector(STM32_TIM1_CC_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY);
+#endif
#if defined(STM32_TIM1CLK)
icup->clock = STM32_TIM1CLK;
#else
@@ -412,50 +408,75 @@ void icu_lld_start(ICUDriver *icup) {
#endif
}
#endif
+
#if STM32_ICU_USE_TIM2
if (&ICUD2 == icup) {
rccEnableTIM2(FALSE);
rccResetTIM2();
- nvicEnableVector(STM32_TIM2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY));
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM2_NUMBER, STM32_ICU_TIM2_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM2CLK)
+ icup->clock = STM32_TIM2CLK;
+#else
icup->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_ICU_USE_TIM3
if (&ICUD3 == icup) {
rccEnableTIM3(FALSE);
rccResetTIM3();
- nvicEnableVector(STM32_TIM3_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY));
- icup->clock = STM32_TIMCLK1;
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM3_NUMBER, STM32_ICU_TIM3_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM3CLK)
+ icup->clock = STM32_TIM3CLK;
+#else
+ icup->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_ICU_USE_TIM4
if (&ICUD4 == icup) {
rccEnableTIM4(FALSE);
rccResetTIM4();
- nvicEnableVector(STM32_TIM4_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY));
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM4_NUMBER, STM32_ICU_TIM4_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM4CLK)
+ icup->clock = STM32_TIM4CLK;
+#else
icup->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_ICU_USE_TIM5
if (&ICUD5 == icup) {
rccEnableTIM5(FALSE);
rccResetTIM5();
- nvicEnableVector(STM32_TIM5_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY));
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM5_NUMBER, STM32_ICU_TIM5_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM5CLK)
+ icup->clock = STM32_TIM5CLK;
+#else
icup->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_ICU_USE_TIM8
if (&ICUD8 == icup) {
rccEnableTIM8(FALSE);
rccResetTIM8();
- nvicEnableVector(STM32_TIM8_UP_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
- nvicEnableVector(STM32_TIM8_CC_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY);
+ nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY);
+#endif
#if defined(STM32_TIM8CLK)
icup->clock = STM32_TIM8CLK;
#else
@@ -463,13 +484,19 @@ void icu_lld_start(ICUDriver *icup) {
#endif
}
#endif
+
#if STM32_ICU_USE_TIM9
if (&ICUD9 == icup) {
rccEnableTIM9(FALSE);
rccResetTIM9();
- nvicEnableVector(STM32_TIM9_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_ICU_TIM9_IRQ_PRIORITY));
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM9_NUMBER, STM32_ICU_TIM9_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM9CLK)
+ icup->clock = STM32_TIM9CLK;
+#else
icup->clock = STM32_TIMCLK2;
+#endif
}
#endif
}
@@ -482,14 +509,14 @@ void icu_lld_start(ICUDriver *icup) {
}
/* Timer configuration.*/
- icup->tim->SR = 0; /* Clear eventual pending IRQs. */
- icup->tim->DIER = icup->config->dier & /* DMA-related DIER settings. */
- ~STM32_TIM_DIER_IRQ_MASK;
+ icup->tim->SR = 0; /* Clear eventual pending IRQs. */
+ icup->tim->DIER = icup->config->dier & /* DMA-related DIER settings. */
+ ~STM32_TIM_DIER_IRQ_MASK;
psc = (icup->clock / icup->config->frequency) - 1;
- chDbgAssert((psc <= 0xFFFF) &&
- ((psc + 1) * icup->config->frequency) == icup->clock,
- "icu_lld_start(), #1", "invalid frequency");
- icup->tim->PSC = (uint16_t)psc;
+ osalDbgAssert((psc <= 0xFFFF) &&
+ ((psc + 1) * icup->config->frequency) == icup->clock,
+ "invalid frequency");
+ icup->tim->PSC = psc;
icup->tim->ARR = 0xFFFF;
if (icup->config->channel == ICU_CHANNEL_1) {
@@ -516,7 +543,8 @@ void icu_lld_start(ICUDriver *icup) {
data faster from within callbacks.*/
icup->wccrp = &icup->tim->CCR[1];
icup->pccrp = &icup->tim->CCR[0];
- } else {
+ }
+ else {
/* Selected input 2.
CCMR1_CC1S = 10 = CH1 Input on TI2.
CCMR1_CC2S = 01 = CH2 Input on TI2.*/
@@ -560,45 +588,65 @@ void icu_lld_stop(ICUDriver *icup) {
#if STM32_ICU_USE_TIM1
if (&ICUD1 == icup) {
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM1_UP_NUMBER);
nvicDisableVector(STM32_TIM1_CC_NUMBER);
+#endif
rccDisableTIM1(FALSE);
}
#endif
+
#if STM32_ICU_USE_TIM2
if (&ICUD2 == icup) {
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM2_NUMBER);
+#endif
rccDisableTIM2(FALSE);
}
#endif
+
#if STM32_ICU_USE_TIM3
if (&ICUD3 == icup) {
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM3_NUMBER);
+#endif
rccDisableTIM3(FALSE);
}
#endif
+
#if STM32_ICU_USE_TIM4
if (&ICUD4 == icup) {
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM4_NUMBER);
+#endif
rccDisableTIM4(FALSE);
}
#endif
+
#if STM32_ICU_USE_TIM5
if (&ICUD5 == icup) {
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM5_NUMBER);
+#endif
rccDisableTIM5(FALSE);
}
#endif
+
#if STM32_ICU_USE_TIM8
if (&ICUD8 == icup) {
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM8_UP_NUMBER);
nvicDisableVector(STM32_TIM8_CC_NUMBER);
+#endif
rccDisableTIM8(FALSE);
}
#endif
+
#if STM32_ICU_USE_TIM9
if (&ICUD9 == icup) {
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM9_NUMBER);
+#endif
rccDisableTIM9(FALSE);
}
#endif
@@ -606,48 +654,152 @@ void icu_lld_stop(ICUDriver *icup) {
}
/**
- * @brief Enables the input capture.
+ * @brief Starts the input capture.
*
* @param[in] icup pointer to the @p ICUDriver object
*
* @notapi
*/
-void icu_lld_enable(ICUDriver *icup) {
+void icu_lld_start_capture(ICUDriver *icup) {
+ /* Triggering an UG and clearing the IRQ status.*/
icup->tim->EGR |= STM32_TIM_EGR_UG;
- icup->tim->SR = 0; /* Clear pending IRQs (if any). */
- if (icup->config->channel == ICU_CHANNEL_1) {
- if (icup->config->period_cb != NULL)
- icup->tim->DIER |= STM32_TIM_DIER_CC1IE;
- if (icup->config->width_cb != NULL)
- icup->tim->DIER |= STM32_TIM_DIER_CC2IE;
- } else {
- if (icup->config->width_cb != NULL)
- icup->tim->DIER |= STM32_TIM_DIER_CC1IE;
- if (icup->config->period_cb != NULL)
- icup->tim->DIER |= STM32_TIM_DIER_CC2IE;
- }
- if (icup->config->overflow_cb != NULL)
- icup->tim->DIER |= STM32_TIM_DIER_UIE;
+ icup->tim->SR = 0;
+
+ /* Timer is started.*/
icup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
}
/**
- * @brief Disables the input capture.
+ * @brief Waits for a completed capture.
+ * @note The operation is performed in polled mode.
+ * @note In order to use this function notifications must be disabled.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The capture status.
+ * @retval false if the capture is successful.
+ * @retval true if a timer overflow occurred.
+ *
+ * @notapi
+ */
+bool icu_lld_wait_capture(ICUDriver *icup) {
+
+ /* If the driver is still in the ICU_WAITING state then we need to wait
+ for the first activation edge.*/
+ if (icup->state == ICU_WAITING)
+ if (icu_lld_wait_edge(icup))
+ return true;
+
+ /* This edge marks the availability of a capture result.*/
+ return icu_lld_wait_edge(icup);
+}
+
+/**
+ * @brief Stops the input capture.
*
* @param[in] icup pointer to the @p ICUDriver object
*
* @notapi
*/
-void icu_lld_disable(ICUDriver *icup) {
+void icu_lld_stop_capture(ICUDriver *icup) {
- icup->tim->CR1 = 0; /* Initially stopped. */
- icup->tim->SR = 0; /* Clear pending IRQs (if any). */
+ /* Timer stopped.*/
+ icup->tim->CR1 = 0;
/* All interrupts disabled.*/
icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
}
+/**
+ * @brief Enables notifications.
+ * @pre The ICU unit must have been activated using @p icuStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_enable_notifications(ICUDriver *icup) {
+ uint32_t dier = icup->tim->DIER;
+
+ /* If interrupts were already enabled then the operation is skipped.
+ This is done in order to avoid clearing the SR and risk losing
+ pending interrupts.*/
+ if ((dier & STM32_TIM_DIER_IRQ_MASK) == 0) {
+ /* Previously triggered IRQs are ignored, status cleared.*/
+ icup->tim->SR = 0;
+
+ if (icup->config->channel == ICU_CHANNEL_1) {
+ /* Enabling periodic callback on CC1.*/
+ dier |= STM32_TIM_DIER_CC1IE;
+
+ /* Optionally enabling width callback on CC2.*/
+ if (icup->config->width_cb != NULL)
+ dier |= STM32_TIM_DIER_CC2IE;
+ }
+ else {
+ /* Enabling periodic callback on CC2.*/
+ dier |= STM32_TIM_DIER_CC2IE;
+
+ /* Optionally enabling width callback on CC1.*/
+ if (icup->config->width_cb != NULL)
+ dier |= STM32_TIM_DIER_CC1IE;
+ }
+
+ /* If an overflow callback is defined then also the overflow callback
+ is enabled.*/
+ if (icup->config->overflow_cb != NULL)
+ dier |= STM32_TIM_DIER_UIE;
+
+ /* One single atomic write.*/
+ icup->tim->DIER = dier;
+ }
+}
+
+/**
+ * @brief Disables notifications.
+ * @pre The ICU unit must have been activated using @p icuStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_disable_notifications(ICUDriver *icup) {
+
+ /* All interrupts disabled.*/
+ icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
+}
+
+/**
+ * @brief Shared IRQ handler.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_serve_interrupt(ICUDriver *icup) {
+ uint32_t sr;
+
+ sr = icup->tim->SR;
+ sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
+ icup->tim->SR = ~sr;
+ if (icup->config->channel == ICU_CHANNEL_1) {
+ if ((sr & STM32_TIM_SR_CC2IF) != 0)
+ _icu_isr_invoke_width_cb(icup);
+ if ((sr & STM32_TIM_SR_CC1IF) != 0)
+ _icu_isr_invoke_period_cb(icup);
+ }
+ else {
+ if ((sr & STM32_TIM_SR_CC1IF) != 0)
+ _icu_isr_invoke_width_cb(icup);
+ if ((sr & STM32_TIM_SR_CC2IF) != 0)
+ _icu_isr_invoke_period_cb(icup);
+ }
+ if ((sr & STM32_TIM_SR_UIF) != 0)
+ _icu_isr_invoke_overflow_cb(icup);
+}
+
#endif /* HAL_USE_ICU */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/icu_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.h
similarity index 78%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/icu_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.h
index 6c48831541..61d278caf3 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/icu_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,20 +15,20 @@
*/
/**
- * @file STM32/icu_lld.h
+ * @file TIMv1/hal_icu_lld.h
* @brief STM32 ICU subsystem low level driver header.
*
* @addtogroup ICU
* @{
*/
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#include "stm32_tim.h"
+#ifndef HAL_ICU_LLD_H
+#define HAL_ICU_LLD_H
#if HAL_USE_ICU || defined(__DOXYGEN__)
+#include "stm32_tim.h"
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@@ -193,38 +193,96 @@
#error "ICU driver activated but no TIM peripheral assigned"
#endif
-#if STM32_ICU_USE_TIM1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY)
+/* Checks on allocation of TIMx units.*/
+#if STM32_ICU_USE_TIM1
+#if defined(STM32_TIM1_IS_USED)
+#error "ICUD1 requires TIM1 but the timer is already used"
+#else
+#define STM32_TIM1_IS_USED
+#endif
+#endif
+
+#if STM32_ICU_USE_TIM2
+#if defined(STM32_TIM2_IS_USED)
+#error "ICUD2 requires TIM2 but the timer is already used"
+#else
+#define STM32_TIM2_IS_USED
+#endif
+#endif
+
+#if STM32_ICU_USE_TIM3
+#if defined(STM32_TIM3_IS_USED)
+#error "ICUD3 requires TIM3 but the timer is already used"
+#else
+#define STM32_TIM3_IS_USED
+#endif
+#endif
+
+#if STM32_ICU_USE_TIM4
+#if defined(STM32_TIM4_IS_USED)
+#error "ICUD4 requires TIM4 but the timer is already used"
+#else
+#define STM32_TIM4_IS_USED
+#endif
+#endif
+
+#if STM32_ICU_USE_TIM5
+#if defined(STM32_TIM5_IS_USED)
+#error "ICUD5 requires TIM5 but the timer is already used"
+#else
+#define STM32_TIM5_IS_USED
+#endif
+#endif
+
+#if STM32_ICU_USE_TIM8
+#if defined(STM32_TIM8_IS_USED)
+#error "ICUD8 requires TIM8 but the timer is already used"
+#else
+#define STM32_TIM8_IS_USED
+#endif
+#endif
+
+#if STM32_ICU_USE_TIM9
+#if defined(STM32_TIM9_IS_USED)
+#error "ICUD9 requires TIM9 but the timer is already used"
+#else
+#define STM32_TIM9_IS_USED
+#endif
+#endif
+
+/* IRQ priority checks.*/
+#if STM32_ICU_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM1"
#endif
-#if STM32_ICU_USE_TIM2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY)
+#if STM32_ICU_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM2"
#endif
-#if STM32_ICU_USE_TIM3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY)
+#if STM32_ICU_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM3"
#endif
-#if STM32_ICU_USE_TIM4 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY)
+#if STM32_ICU_USE_TIM4 && !defined(STM32_TIM4_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM4"
#endif
-#if STM32_ICU_USE_TIM5 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY)
+#if STM32_ICU_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM5"
#endif
-#if STM32_ICU_USE_TIM8 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY)
+#if STM32_ICU_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM8"
#endif
-#if STM32_ICU_USE_TIM9 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY)
+#if STM32_ICU_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM9"
#endif
@@ -256,7 +314,7 @@ typedef enum {
/**
* @brief ICU counter type.
*/
-typedef uint16_t icucnt_t;
+typedef uint32_t icucnt_t;
/**
* @brief Driver configuration structure.
@@ -361,6 +419,19 @@ struct ICUDriver {
*/
#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
+/**
+ * @brief Check on notifications status.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The notifications status.
+ * @retval false if notifications are not enabled.
+ * @retval true if notifications are enabled.
+ *
+ * @notapi
+ */
+#define icu_lld_are_notifications_enabled(icup) \
+ (bool)(((icup)->tim->DIER & STM32_TIM_DIER_IRQ_MASK) != 0)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
@@ -399,14 +470,18 @@ extern "C" {
void icu_lld_init(void);
void icu_lld_start(ICUDriver *icup);
void icu_lld_stop(ICUDriver *icup);
- void icu_lld_enable(ICUDriver *icup);
- void icu_lld_disable(ICUDriver *icup);
+ void icu_lld_start_capture(ICUDriver *icup);
+ bool icu_lld_wait_capture(ICUDriver *icup);
+ void icu_lld_stop_capture(ICUDriver *icup);
+ void icu_lld_enable_notifications(ICUDriver *icup);
+ void icu_lld_disable_notifications(ICUDriver *icup);
+ void icu_lld_serve_interrupt(ICUDriver *icup);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_ICU */
-#endif /* _ICU_LLD_H_ */
+#endif /* HAL_ICU_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/pwm_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c
similarity index 64%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/pwm_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c
index 78f7957ebe..1db0b766e4 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/pwm_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/pwm_lld.c
+ * @file TIMv1/hal_pwm_lld.c
* @brief STM32 PWM subsystem low level driver header.
*
* @addtogroup PWM
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_PWM || defined(__DOXYGEN__)
@@ -99,40 +98,12 @@ PWMDriver PWMD9;
/* Driver local functions. */
/*===========================================================================*/
-#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 || \
- STM32_PWM_USE_TIM5 || STM32_PWM_USE_TIM9 || defined(__DOXYGEN__)
-/**
- * @brief Common TIM2...TIM5,TIM9 IRQ handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- uint16_t sr;
-
- sr = pwmp->tim->SR;
- sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
- pwmp->tim->SR = ~sr;
- if ((sr & STM32_TIM_SR_CC1IF) != 0)
- pwmp->config->channels[0].callback(pwmp);
- if ((sr & STM32_TIM_SR_CC2IF) != 0)
- pwmp->config->channels[1].callback(pwmp);
- if ((sr & STM32_TIM_SR_CC3IF) != 0)
- pwmp->config->channels[2].callback(pwmp);
- if ((sr & STM32_TIM_SR_CC4IF) != 0)
- pwmp->config->channels[3].callback(pwmp);
- if ((sr & STM32_TIM_SR_UIF) != 0)
- pwmp->config->callback(pwmp);
-}
-#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */
-
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
-#if STM32_PWM_USE_TIM1
+#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
#if !defined(STM32_TIM1_UP_HANDLER)
#error "STM32_TIM1_UP_HANDLER not defined"
#endif
@@ -144,14 +115,13 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- STM32_TIM1->SR = ~STM32_TIM_SR_UIF;
- PWMD1.config->callback(&PWMD1);
+ pwm_lld_serve_interrupt(&PWMD1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#if !defined(STM32_TIM1_CC_HANDLER)
@@ -165,27 +135,19 @@ CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
- uint16_t sr;
-
- CH_IRQ_PROLOGUE();
-
- sr = STM32_TIM1->SR & STM32_TIM1->DIER & STM32_TIM_DIER_IRQ_MASK;
- STM32_TIM1->SR = ~sr;
- if ((sr & STM32_TIM_SR_CC1IF) != 0)
- PWMD1.config->channels[0].callback(&PWMD1);
- if ((sr & STM32_TIM_SR_CC2IF) != 0)
- PWMD1.config->channels[1].callback(&PWMD1);
- if ((sr & STM32_TIM_SR_CC3IF) != 0)
- PWMD1.config->channels[2].callback(&PWMD1);
- if ((sr & STM32_TIM_SR_CC4IF) != 0)
- PWMD1.config->channels[3].callback(&PWMD1);
-
- CH_IRQ_EPILOGUE();
+OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD1);
+
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
#endif /* STM32_PWM_USE_TIM1 */
-#if STM32_PWM_USE_TIM2
+#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
#if !defined(STM32_TIM2_HANDLER)
#error "STM32_TIM2_HANDLER not defined"
#endif
@@ -194,17 +156,19 @@ CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
#endif /* STM32_PWM_USE_TIM2 */
-#if STM32_PWM_USE_TIM3
+#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
#if !defined(STM32_TIM3_HANDLER)
#error "STM32_TIM3_HANDLER not defined"
#endif
@@ -213,17 +177,19 @@ CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
#endif /* STM32_PWM_USE_TIM3 */
-#if STM32_PWM_USE_TIM4
+#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
#if !defined(STM32_TIM4_HANDLER)
#error "STM32_TIM4_HANDLER not defined"
#endif
@@ -232,17 +198,19 @@ CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
#endif /* STM32_PWM_USE_TIM4 */
-#if STM32_PWM_USE_TIM5
+#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
#if !defined(STM32_TIM5_HANDLER)
#error "STM32_TIM5_HANDLER not defined"
#endif
@@ -251,17 +219,19 @@ CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD5);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
#endif /* STM32_PWM_USE_TIM5 */
-#if STM32_PWM_USE_TIM8
+#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
#if !defined(STM32_TIM8_UP_HANDLER)
#error "STM32_TIM8_UP_HANDLER not defined"
#endif
@@ -273,14 +243,13 @@ CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- STM32_TIM8->SR = ~TIM_SR_UIF;
- PWMD8.config->callback(&PWMD8);
+ pwm_lld_serve_interrupt(&PWMD8);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#if !defined(STM32_TIM8_CC_HANDLER)
@@ -294,27 +263,19 @@ CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
- uint16_t sr;
-
- CH_IRQ_PROLOGUE();
-
- sr = STM32_TIM8->SR & STM32_TIM8->DIER & STM32_TIM_DIER_IRQ_MASK;
- STM32_TIM8->SR = ~sr;
- if ((sr & STM32_TIM_SR_CC1IF) != 0)
- PWMD8.config->channels[0].callback(&PWMD8);
- if ((sr & STM32_TIM_SR_CC2IF) != 0)
- PWMD8.config->channels[1].callback(&PWMD8);
- if ((sr & STM32_TIM_SR_CC3IF) != 0)
- PWMD8.config->channels[2].callback(&PWMD8);
- if ((sr & STM32_TIM_SR_CC4IF) != 0)
- PWMD8.config->channels[3].callback(&PWMD8);
-
- CH_IRQ_EPILOGUE();
+OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD8);
+
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
#endif /* STM32_PWM_USE_TIM8 */
-#if STM32_PWM_USE_TIM9
+#if STM32_PWM_USE_TIM9 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
#if !defined(STM32_TIM9_HANDLER)
#error "STM32_TIM9_HANDLER not defined"
#endif
@@ -323,14 +284,15 @@ CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD9);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
#endif /* STM32_PWM_USE_TIM9 */
/*===========================================================================*/
@@ -347,42 +309,49 @@ void pwm_lld_init(void) {
#if STM32_PWM_USE_TIM1
/* Driver initialization.*/
pwmObjectInit(&PWMD1);
+ PWMD1.channels = STM32_TIM1_CHANNELS;
PWMD1.tim = STM32_TIM1;
#endif
#if STM32_PWM_USE_TIM2
/* Driver initialization.*/
pwmObjectInit(&PWMD2);
+ PWMD2.channels = STM32_TIM2_CHANNELS;
PWMD2.tim = STM32_TIM2;
#endif
#if STM32_PWM_USE_TIM3
/* Driver initialization.*/
pwmObjectInit(&PWMD3);
+ PWMD3.channels = STM32_TIM3_CHANNELS;
PWMD3.tim = STM32_TIM3;
#endif
#if STM32_PWM_USE_TIM4
/* Driver initialization.*/
pwmObjectInit(&PWMD4);
+ PWMD4.channels = STM32_TIM4_CHANNELS;
PWMD4.tim = STM32_TIM4;
#endif
#if STM32_PWM_USE_TIM5
/* Driver initialization.*/
pwmObjectInit(&PWMD5);
+ PWMD5.channels = STM32_TIM5_CHANNELS;
PWMD5.tim = STM32_TIM5;
#endif
#if STM32_PWM_USE_TIM8
/* Driver initialization.*/
pwmObjectInit(&PWMD8);
+ PWMD8.channels = STM32_TIM8_CHANNELS;
PWMD8.tim = STM32_TIM8;
#endif
#if STM32_PWM_USE_TIM9
/* Driver initialization.*/
pwmObjectInit(&PWMD9);
+ PWMD9.channels = STM32_TIM9_CHANNELS;
PWMD9.tim = STM32_TIM9;
#endif
}
@@ -399,7 +368,6 @@ void pwm_lld_init(void) {
void pwm_lld_start(PWMDriver *pwmp) {
uint32_t psc;
uint32_t ccer;
- uint32_t dier;
if (pwmp->state == PWM_STOP) {
/* Clock activation and timer reset.*/
@@ -407,10 +375,10 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD1 == pwmp) {
rccEnableTIM1(FALSE);
rccResetTIM1();
- nvicEnableVector(STM32_TIM1_UP_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
- nvicEnableVector(STM32_TIM1_CC_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY);
+#endif
#if defined(STM32_TIM1CLK)
pwmp->clock = STM32_TIM1CLK;
#else
@@ -418,31 +386,49 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif
}
#endif
+
#if STM32_PWM_USE_TIM2
if (&PWMD2 == pwmp) {
rccEnableTIM2(FALSE);
rccResetTIM2();
- nvicEnableVector(STM32_TIM2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM2_NUMBER, STM32_PWM_TIM2_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM2CLK)
+ pwmp->clock = STM32_TIM2CLK;
+#else
pwmp->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_PWM_USE_TIM3
if (&PWMD3 == pwmp) {
rccEnableTIM3(FALSE);
rccResetTIM3();
- nvicEnableVector(STM32_TIM3_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM3_NUMBER, STM32_PWM_TIM3_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM3CLK)
+ pwmp->clock = STM32_TIM3CLK;
+#else
pwmp->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_PWM_USE_TIM4
if (&PWMD4 == pwmp) {
rccEnableTIM4(FALSE);
rccResetTIM4();
- nvicEnableVector(STM32_TIM4_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM4_NUMBER, STM32_PWM_TIM4_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM4CLK)
+ pwmp->clock = STM32_TIM4CLK;
+#else
pwmp->clock = STM32_TIMCLK1;
+#endif
}
#endif
@@ -450,19 +436,25 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD5 == pwmp) {
rccEnableTIM5(FALSE);
rccResetTIM5();
- nvicEnableVector(STM32_TIM5_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM5_NUMBER, STM32_PWM_TIM5_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM5CLK)
+ pwmp->clock = STM32_TIM5CLK;
+#else
pwmp->clock = STM32_TIMCLK1;
+#endif
}
#endif
+
#if STM32_PWM_USE_TIM8
if (&PWMD8 == pwmp) {
rccEnableTIM8(FALSE);
rccResetTIM8();
- nvicEnableVector(STM32_TIM8_UP_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
- nvicEnableVector(STM32_TIM8_CC_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY);
+ nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY);
+#endif
#if defined(STM32_TIM8CLK)
pwmp->clock = STM32_TIM8CLK;
#else
@@ -470,13 +462,19 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif
}
#endif
+
#if STM32_PWM_USE_TIM9
if (&PWMD9 == pwmp) {
rccEnableTIM9(FALSE);
rccResetTIM9();
- nvicEnableVector(STM32_TIM9_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_PWM_TIM9_IRQ_PRIORITY));
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
+ nvicEnableVector(STM32_TIM9_NUMBER, STM32_PWM_TIM9_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM9CLK)
+ pwmp->clock = STM32_TIM9CLK;
+#else
pwmp->clock = STM32_TIMCLK2;
+#endif
}
#endif
@@ -486,6 +484,10 @@ void pwm_lld_start(PWMDriver *pwmp) {
STM32_TIM_CCMR1_OC2M(6) | STM32_TIM_CCMR1_OC2PE;
pwmp->tim->CCMR2 = STM32_TIM_CCMR2_OC3M(6) | STM32_TIM_CCMR2_OC3PE |
STM32_TIM_CCMR2_OC4M(6) | STM32_TIM_CCMR2_OC4PE;
+#if STM32_TIM_MAX_CHANNELS > 4
+ pwmp->tim->CCMR3 = STM32_TIM_CCMR3_OC5M(6) | STM32_TIM_CCMR3_OC5PE |
+ STM32_TIM_CCMR3_OC6M(6) | STM32_TIM_CCMR3_OC6PE;
+#endif
}
else {
/* Driver re-configuration scenario, it must be stopped first.*/
@@ -494,16 +496,22 @@ void pwm_lld_start(PWMDriver *pwmp) {
pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */
pwmp->tim->CCR[2] = 0; /* Comparator 3 disabled. */
pwmp->tim->CCR[3] = 0; /* Comparator 4 disabled. */
+#if STM32_TIM_MAX_CHANNELS > 4
+ if (pwmp->channels > 4) {
+ pwmp->tim->CCXR[0] = 0; /* Comparator 5 disabled. */
+ pwmp->tim->CCXR[1] = 0; /* Comparator 6 disabled. */
+ }
+#endif
pwmp->tim->CNT = 0; /* Counter reset to zero. */
}
/* Timer configuration.*/
psc = (pwmp->clock / pwmp->config->frequency) - 1;
- chDbgAssert((psc <= 0xFFFF) &&
- ((psc + 1) * pwmp->config->frequency) == pwmp->clock,
- "pwm_lld_start(), #1", "invalid frequency");
- pwmp->tim->PSC = (uint16_t)psc;
- pwmp->tim->ARR = (uint16_t)(pwmp->period - 1);
+ osalDbgAssert((psc <= 0xFFFF) &&
+ ((psc + 1) * pwmp->config->frequency) == pwmp->clock,
+ "invalid frequency");
+ pwmp->tim->PSC = psc;
+ pwmp->tim->ARR = pwmp->period - 1;
pwmp->tim->CR2 = pwmp->config->cr2;
/* Output enables and polarities setup.*/
@@ -580,8 +588,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
pwmp->tim->CCER = ccer;
pwmp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
pwmp->tim->SR = 0; /* Clear pending IRQs. */
- pwmp->tim->DIER = (pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE) |
- (pwmp->config->dier & ~STM32_TIM_DIER_IRQ_MASK);
+ pwmp->tim->DIER = pwmp->config->dier & /* DMA-related DIER settings. */
+ ~STM32_TIM_DIER_IRQ_MASK;
#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
#if STM32_PWM_USE_ADVANCED
pwmp->tim->BDTR = pwmp->config->bdtr | STM32_TIM_BDTR_MOE;
@@ -614,45 +622,65 @@ void pwm_lld_stop(PWMDriver *pwmp) {
#if STM32_PWM_USE_TIM1
if (&PWMD1 == pwmp) {
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM1_UP_NUMBER);
nvicDisableVector(STM32_TIM1_CC_NUMBER);
+#endif
rccDisableTIM1(FALSE);
}
#endif
+
#if STM32_PWM_USE_TIM2
if (&PWMD2 == pwmp) {
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM2_NUMBER);
+#endif
rccDisableTIM2(FALSE);
}
#endif
+
#if STM32_PWM_USE_TIM3
if (&PWMD3 == pwmp) {
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM3_NUMBER);
+#endif
rccDisableTIM3(FALSE);
}
#endif
+
#if STM32_PWM_USE_TIM4
if (&PWMD4 == pwmp) {
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM4_NUMBER);
+#endif
rccDisableTIM4(FALSE);
}
#endif
+
#if STM32_PWM_USE_TIM5
if (&PWMD5 == pwmp) {
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM5_NUMBER);
+#endif
rccDisableTIM5(FALSE);
}
#endif
+
#if STM32_PWM_USE_TIM8
if (&PWMD8 == pwmp) {
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM8_UP_NUMBER);
nvicDisableVector(STM32_TIM8_CC_NUMBER);
+#endif
rccDisableTIM8(FALSE);
}
#endif
+
#if STM32_PWM_USE_TIM9
if (&PWMD9 == pwmp) {
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
nvicDisableVector(STM32_TIM9_NUMBER);
+#endif
rccDisableTIM9(FALSE);
}
#endif
@@ -664,9 +692,10 @@ void pwm_lld_stop(PWMDriver *pwmp) {
* @pre The PWM unit must have been activated using @p pwmStart().
* @post The channel is active using the specified configuration.
* @note The function has effect at the next cycle start.
+ * @note Channel notification is not enabled.
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] channel PWM channel identifier (0...channels-1)
* @param[in] width PWM pulse width as clock pulses number
*
* @notapi
@@ -675,36 +704,153 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
- pwmp->tim->CCR[channel] = width; /* New duty cycle. */
- /* If there is a callback defined for the channel then the associated
- interrupt must be enabled.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- uint32_t dier = pwmp->tim->DIER;
- /* If the IRQ is not already enabled care must be taken to clear it,
- it is probably already pending because the timer is running.*/
- if ((dier & (2 << channel)) == 0) {
- pwmp->tim->DIER = dier | (2 << channel);
- pwmp->tim->SR = ~(2 << channel);
- }
- }
+ /* Changing channel duty cycle on the fly.*/
+#if STM32_TIM_MAX_CHANNELS <= 4
+ pwmp->tim->CCR[channel] = width;
+#else
+ if (channel < 4)
+ pwmp->tim->CCR[channel] = width;
+ else
+ pwmp->tim->CCXR[channel - 4] = width;
+#endif
}
/**
- * @brief Disables a PWM channel.
+ * @brief Disables a PWM channel and its notification.
* @pre The PWM unit must have been activated using @p pwmStart().
* @post The channel is disabled and its output line returned to the
* idle state.
* @note The function has effect at the next cycle start.
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] channel PWM channel identifier (0...channels-1)
*
* @notapi
*/
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+#if STM32_TIM_MAX_CHANNELS <= 4
pwmp->tim->CCR[channel] = 0;
pwmp->tim->DIER &= ~(2 << channel);
+#else
+ if (channel < 4) {
+ pwmp->tim->CCR[channel] = 0;
+ pwmp->tim->DIER &= ~(2 << channel);
+ }
+ else
+ pwmp->tim->CCXR[channel - 4] = 0;
+#endif
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+ uint32_t dier = pwmp->tim->DIER;
+
+ /* If the IRQ is not already enabled care must be taken to clear it,
+ it is probably already pending because the timer is running.*/
+ if ((dier & STM32_TIM_DIER_UIE) == 0) {
+ pwmp->tim->DIER = dier | STM32_TIM_DIER_UIE;
+ pwmp->tim->SR &= STM32_TIM_SR_UIF;
+ }
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+
+ pwmp->tim->DIER &= ~STM32_TIM_DIER_UIE;
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ uint32_t dier = pwmp->tim->DIER;
+
+#if STM32_TIM_MAX_CHANNELS > 4
+ /* Channels 4 and 5 do not support callbacks.*/
+ osalDbgAssert(channel < 4, "callback not supported");
+#endif
+
+ /* If the IRQ is not already enabled care must be taken to clear it,
+ it is probably already pending because the timer is running.*/
+ if ((dier & (2 << channel)) == 0) {
+ pwmp->tim->DIER = dier | (2 << channel);
+ pwmp->tim->SR = ~(2 << channel);
+ }
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+
+ pwmp->tim->DIER &= ~(2 << channel);
+}
+
+/**
+ * @brief Common TIM2...TIM5,TIM9 IRQ handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+ uint32_t sr;
+
+ sr = pwmp->tim->SR;
+ sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
+ pwmp->tim->SR = ~sr;
+ if (((sr & STM32_TIM_SR_CC1IF) != 0) &&
+ (pwmp->config->channels[0].callback != NULL))
+ pwmp->config->channels[0].callback(pwmp);
+ if (((sr & STM32_TIM_SR_CC2IF) != 0) &&
+ (pwmp->config->channels[1].callback != NULL))
+ pwmp->config->channels[1].callback(pwmp);
+ if (((sr & STM32_TIM_SR_CC3IF) != 0) &&
+ (pwmp->config->channels[2].callback != NULL))
+ pwmp->config->channels[2].callback(pwmp);
+ if (((sr & STM32_TIM_SR_CC4IF) != 0) &&
+ (pwmp->config->channels[3].callback != NULL))
+ pwmp->config->channels[3].callback(pwmp);
+ if (((sr & STM32_TIM_SR_UIF) != 0) && (pwmp->config->callback != NULL))
+ pwmp->config->callback(pwmp);
}
#endif /* HAL_USE_PWM */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/pwm_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.h
similarity index 78%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/pwm_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.h
index 4f3b459517..deeaf9324c 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/pwm_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,20 +15,20 @@
*/
/**
- * @file STM32/pwm_lld.h
+ * @file TIMv1/hal_pwm_lld.h
* @brief STM32 PWM subsystem low level driver header.
*
* @addtogroup PWM
* @{
*/
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#include "stm32_tim.h"
+#ifndef HAL_PWM_LLD_H
+#define HAL_PWM_LLD_H
#if HAL_USE_PWM || defined(__DOXYGEN__)
+#include "stm32_tim.h"
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@@ -36,8 +36,12 @@
/**
* @brief Number of PWM channels per PWM driver.
*/
-#define PWM_CHANNELS 4
+#define PWM_CHANNELS STM32_TIM_MAX_CHANNELS
+/**
+ * @name STM32-specific PWM complementary output mode macros
+ * @{
+ */
/**
* @brief Complementary output modes mask.
* @note This is an STM32-specific setting.
@@ -67,6 +71,7 @@
* timers TIM1 and TIM8.
*/
#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20
+/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
@@ -243,38 +248,96 @@
#error "advanced mode selected but no advanced timer assigned"
#endif
-#if STM32_PWM_USE_TIM1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM1_IRQ_PRIORITY)
+/* Checks on allocation of TIMx units.*/
+#if STM32_PWM_USE_TIM1
+#if defined(STM32_TIM1_IS_USED)
+#error "PWMD1 requires TIM1 but the timer is already used"
+#else
+#define STM32_TIM1_IS_USED
+#endif
+#endif
+
+#if STM32_PWM_USE_TIM2
+#if defined(STM32_TIM2_IS_USED)
+#error "PWMD2 requires TIM2 but the timer is already used"
+#else
+#define STM32_TIM2_IS_USED
+#endif
+#endif
+
+#if STM32_PWM_USE_TIM3
+#if defined(STM32_TIM3_IS_USED)
+#error "PWMD3 requires TIM3 but the timer is already used"
+#else
+#define STM32_TIM3_IS_USED
+#endif
+#endif
+
+#if STM32_PWM_USE_TIM4
+#if defined(STM32_TIM4_IS_USED)
+#error "PWMD4 requires TIM4 but the timer is already used"
+#else
+#define STM32_TIM4_IS_USED
+#endif
+#endif
+
+#if STM32_PWM_USE_TIM5
+#if defined(STM32_TIM5_IS_USED)
+#error "PWMD5 requires TIM5 but the timer is already used"
+#else
+#define STM32_TIM5_IS_USED
+#endif
+#endif
+
+#if STM32_PWM_USE_TIM8
+#if defined(STM32_TIM8_IS_USED)
+#error "PWMD8 requires TIM8 but the timer is already used"
+#else
+#define STM32_TIM8_IS_USED
+#endif
+#endif
+
+#if STM32_PWM_USE_TIM9
+#if defined(STM32_TIM9_IS_USED)
+#error "PWMD9 requires TIM9 but the timer is already used"
+#else
+#define STM32_TIM9_IS_USED
+#endif
+#endif
+
+/* IRQ priority checks.*/
+#if STM32_PWM_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM1"
#endif
-#if STM32_PWM_USE_TIM2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM2_IRQ_PRIORITY)
+#if STM32_PWM_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM2"
#endif
-#if STM32_PWM_USE_TIM3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM3_IRQ_PRIORITY)
+#if STM32_PWM_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM3"
#endif
-#if STM32_PWM_USE_TIM4 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM4_IRQ_PRIORITY)
+#if STM32_PWM_USE_TIM4 && !defined(STM32_TIM4_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM4"
#endif
-#if STM32_PWM_USE_TIM5 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM5_IRQ_PRIORITY)
+#if STM32_PWM_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM5"
#endif
-#if STM32_PWM_USE_TIM8 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM8_IRQ_PRIORITY)
+#if STM32_PWM_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM8"
#endif
-#if STM32_PWM_USE_TIM9 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM9_IRQ_PRIORITY)
+#if STM32_PWM_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM9_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM9"
#endif
@@ -283,22 +346,27 @@
/*===========================================================================*/
/**
- * @brief PWM mode type.
+ * @brief Type of a PWM mode.
*/
typedef uint32_t pwmmode_t;
/**
- * @brief PWM channel type.
+ * @brief Type of a PWM channel.
*/
typedef uint8_t pwmchannel_t;
/**
- * @brief PWM counter type.
+ * @brief Type of a channels mask.
*/
-typedef uint16_t pwmcnt_t;
+typedef uint32_t pwmchnmsk_t;
/**
- * @brief PWM driver channel configuration structure.
+ * @brief Type of a PWM counter.
+ */
+typedef uint32_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
*/
typedef struct {
/**
@@ -315,7 +383,7 @@ typedef struct {
} PWMChannelConfig;
/**
- * @brief PWM driver configuration structure.
+ * @brief Type of a PWM driver configuration structure.
*/
typedef struct {
/**
@@ -377,6 +445,14 @@ struct PWMDriver {
* @brief Current PWM period in ticks.
*/
pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
#if defined(PWM_DRIVER_EXT_FIELDS)
PWM_DRIVER_EXT_FIELDS
#endif
@@ -412,20 +488,7 @@ struct PWMDriver {
* @notapi
*/
#define pwm_lld_change_period(pwmp, period) \
- ((pwmp)->tim->ARR = (uint16_t)((period) - 1))
-
-/**
- * @brief Returns a PWM channel status.
- * @pre The PWM unit must have been activated using @p pwmStart().
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-#define pwm_lld_is_channel_enabled(pwmp, channel) \
- (((pwmp)->tim->CCR[channel] != 0) || \
- (((pwmp)->tim->DIER & (2 << channel)) != 0))
+ ((pwmp)->tim->ARR = ((period) - 1))
/*===========================================================================*/
/* External declarations. */
@@ -469,12 +532,19 @@ extern "C" {
pwmchannel_t channel,
pwmcnt_t width);
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_serve_interrupt(PWMDriver *pwmp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_PWM */
-#endif /* _PWM_LLD_H_ */
+#endif /* HAL_PWM_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
new file mode 100644
index 0000000000..ce010b481f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
@@ -0,0 +1,308 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TIMv1/hal_st_lld.c
+ * @brief ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+
+#if (OSAL_ST_RESOLUTION == 32)
+#define ST_ARR_INIT 0xFFFFFFFF
+#else
+#define ST_ARR_INIT 0x0000FFFF
+#endif
+
+#if STM32_ST_USE_TIMER == 2
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM2_IS_32BITS
+#error "TIM2 is not a 32bits timer"
+#endif
+
+#if defined(STM32_TIM2_IS_USED)
+#error "ST requires TIM2 but the timer is already used"
+#else
+#define STM32_TIM2_IS_USED
+#endif
+
+#define ST_HANDLER STM32_TIM2_HANDLER
+#define ST_NUMBER STM32_TIM2_NUMBER
+#define ST_CLOCK_SRC STM32_TIMCLK1
+#define ST_ENABLE_CLOCK() rccEnableTIM2(FALSE)
+#if defined(STM32F1XX)
+#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP
+#elif defined(STM32L4XX)
+#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP
+#else
+#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP
+#endif
+
+#elif STM32_ST_USE_TIMER == 3
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM3_IS_32BITS
+#error "TIM3 is not a 32bits timer"
+#endif
+
+#if defined(STM32_TIM3_IS_USED)
+#error "ST requires TIM3 but the timer is already used"
+#else
+#define STM32_TIM3_IS_USED
+#endif
+
+#define ST_HANDLER STM32_TIM3_HANDLER
+#define ST_NUMBER STM32_TIM3_NUMBER
+#define ST_CLOCK_SRC STM32_TIMCLK1
+#define ST_ENABLE_CLOCK() rccEnableTIM3(FALSE)
+#if defined(STM32F1XX)
+#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP
+#elif defined(STM32L4XX)
+#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP
+#else
+#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM3_STOP
+#endif
+
+#elif STM32_ST_USE_TIMER == 4
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM4_IS_32BITS
+#error "TIM4 is not a 32bits timer"
+#endif
+
+#if defined(STM32_TIM4_IS_USED)
+#error "ST requires TIM4 but the timer is already used"
+#else
+#define STM32_TIM4_IS_USED
+#endif
+
+#define ST_HANDLER STM32_TIM4_HANDLER
+#define ST_NUMBER STM32_TIM4_NUMBER
+#define ST_CLOCK_SRC STM32_TIMCLK1
+#define ST_ENABLE_CLOCK() rccEnableTIM4(FALSE)
+#if defined(STM32F1XX)
+#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP
+#elif defined(STM32L4XX)
+#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM4_STOP
+#else
+#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM4_STOP
+#endif
+
+#elif STM32_ST_USE_TIMER == 5
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM5_IS_32BITS
+#error "TIM5 is not a 32bits timer"
+#endif
+
+#if defined(STM32_TIM5_IS_USED)
+#error "ST requires TIM5 but the timer is already used"
+#else
+#define STM32_TIM5_IS_USED
+#endif
+
+#define ST_HANDLER STM32_TIM5_HANDLER
+#define ST_NUMBER STM32_TIM5_NUMBER
+#define ST_CLOCK_SRC STM32_TIMCLK1
+#define ST_ENABLE_CLOCK() rccEnableTIM5(FALSE)
+#if defined(STM32F1XX)
+#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM5_STOP
+#elif defined(STM32L4XX)
+#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP
+#else
+#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM5_STOP
+#endif
+
+#elif STM32_ST_USE_TIMER == 21
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM21_IS_32BITS
+#error "TIM21 is not a 32bits timer"
+#endif
+
+#if defined(STM32_TIM21_IS_USED)
+#error "ST requires TIM21 but the timer is already used"
+#else
+#define STM32_TIM21_IS_USED
+#endif
+
+#define ST_HANDLER STM32_TIM21_HANDLER
+#define ST_NUMBER STM32_TIM21_NUMBER
+#define ST_CLOCK_SRC STM32_TIMCLK2
+#define ST_ENABLE_CLOCK() rccEnableTIM21(FALSE)
+#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP
+
+#elif STM32_ST_USE_TIMER == 22
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM22_IS_32BITS
+#error "TIM21 is not a 32bits timer"
+#endif
+
+#if defined(STM32_TIM22_IS_USED)
+#error "ST requires TIM22 but the timer is already used"
+#else
+#define STM32_TIM22_IS_USED
+#endif
+
+#define ST_HANDLER STM32_TIM22_HANDLER
+#define ST_NUMBER STM32_TIM22_NUMBER
+#define ST_CLOCK_SRC STM32_TIMCLK2
+#define ST_ENABLE_CLOCK() rccEnableTIM22(FALSE)
+#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP
+
+#else
+#error "STM32_ST_USE_TIMER specifies an unsupported timer"
+#endif
+
+#if ST_CLOCK_SRC % OSAL_ST_FREQUENCY != 0
+#error "the selected ST frequency is not obtainable because integer rounding"
+#endif
+
+#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF
+#error "the selected ST frequency is not obtainable because TIM timer prescaler limits"
+#endif
+
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+
+#if STM32_HCLK % OSAL_ST_FREQUENCY != 0
+#error "the selected ST frequency is not obtainable because integer rounding"
+#endif
+
+#if (STM32_HCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF
+#error "the selected ST frequency is not obtainable because SysTick timer counter limits"
+#endif
+
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
+/**
+ * @brief System Timer vector.
+ * @details This interrupt is used for system tick in periodic mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SysTick_Handler) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
+/**
+ * @brief TIM2 interrupt handler.
+ * @details This interrupt is used for system tick in free running mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(ST_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Note, under rare circumstances an interrupt can remain latched even if
+ the timer SR register has been cleared, in those cases the interrupt
+ is simply ignored.*/
+ if ((STM32_ST_TIM->SR & TIM_SR_CC1IF) != 0U) {
+ STM32_ST_TIM->SR = 0U;
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+ /* Free running counter mode.*/
+
+ /* Enabling timer clock.*/
+ ST_ENABLE_CLOCK();
+
+ /* Enabling the stop mode during debug for this timer.*/
+ ST_ENABLE_STOP();
+
+ /* Initializing the counter in free running mode.*/
+ STM32_ST_TIM->PSC = (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1;
+ STM32_ST_TIM->ARR = ST_ARR_INIT;
+ STM32_ST_TIM->CCMR1 = 0;
+ STM32_ST_TIM->CCR[0] = 0;
+ STM32_ST_TIM->DIER = 0;
+ STM32_ST_TIM->CR2 = 0;
+ STM32_ST_TIM->EGR = TIM_EGR_UG;
+ STM32_ST_TIM->CR1 = TIM_CR1_CEN;
+
+ /* IRQ enabled.*/
+ nvicEnableVector(ST_NUMBER, STM32_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+ /* Periodic systick mode, the Cortex-Mx internal systick timer is used
+ in this mode.*/
+ SysTick->LOAD = (STM32_HCLK / OSAL_ST_FREQUENCY) - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk |
+ SysTick_CTRL_TICKINT_Msk;
+
+ /* IRQ enabled.*/
+ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, STM32_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.h
new file mode 100644
index 0000000000..3b595de0e4
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.h
@@ -0,0 +1,210 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TIMv1/hal_st_lld.h
+ * @brief ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef HAL_ST_LLD_H
+#define HAL_ST_LLD_H
+
+#include "mcuconf.h"
+#include "stm32_registry.h"
+#include "stm32_tim.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SysTick timer IRQ priority.
+ */
+#if !defined(STM32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ST_IRQ_PRIORITY 8
+#endif
+
+/**
+ * @brief TIMx unit (by number) to be used for free running operations.
+ * @note You must select a 32 bits timer if a 32 bits @p systick_t type
+ * is required.
+ * @note Timers 2, 3, 4 and 5 are supported.
+ */
+#if !defined(STM32_ST_USE_TIMER) || defined(__DOXYGEN__)
+#define STM32_ST_USE_TIMER 2
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_ST_USE_TIMER == 2
+#if !STM32_HAS_TIM2
+#error "TIM2 not present"
+#endif
+#define STM32_ST_TIM STM32_TIM2
+
+#elif STM32_ST_USE_TIMER == 3
+#if !STM32_HAS_TIM3
+#error "TIM3 not present"
+#endif
+#define STM32_ST_TIM STM32_TIM3
+
+#elif STM32_ST_USE_TIMER == 4
+#if !STM32_HAS_TIM4
+#error "TIM4 not present"
+#endif
+#define STM32_ST_TIM STM32_TIM4
+
+#elif STM32_ST_USE_TIMER == 5
+#if !STM32_HAS_TIM5
+#error "TIM5 not present"
+#endif
+#define STM32_ST_TIM STM32_TIM5
+
+#elif STM32_ST_USE_TIMER == 21
+#if !STM32_HAS_TIM21
+#error "TIM21 not present"
+#endif
+#define STM32_ST_TIM STM32_TIM21
+
+#elif STM32_ST_USE_TIMER == 22
+#if !STM32_HAS_TIM22
+#error "TIM22 not present"
+#endif
+#define STM32_ST_TIM STM32_TIM22
+
+#else
+#error "STM32_ST_USE_TIMER specifies an unsupported timer"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the time counter value.
+ *
+ * @return The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+ return (systime_t)STM32_ST_TIM->CNT;
+}
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time) {
+
+ STM32_ST_TIM->CCR[0] = (uint32_t)time;
+ STM32_ST_TIM->SR = 0;
+ STM32_ST_TIM->DIER = STM32_TIM_DIER_CC1IE;
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+ STM32_ST_TIM->DIER = 0;
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time) {
+
+ STM32_ST_TIM->CCR[0] = (uint32_t)time;
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+ return (systime_t)STM32_ST_TIM->CCR[0];
+}
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+ return (bool)((STM32_ST_TIM->DIER & STM32_TIM_DIER_CC1IE) != 0);
+}
+
+#endif /* HAL_ST_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/stm32_tim.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
similarity index 97%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/stm32_tim.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
index 5d48170f58..7c65aae1d9 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/TIMv1/stm32_tim.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,16 +15,16 @@
*/
/**
- * @file stm32_tim.h
- * @brief STM32 TIM registers layout header.
+ * @file TIMv1/stm32_tim.h
+ * @brief STM32 TIM units common header.
* @note This file requires definitions from the ST STM32 header file.
*
* @addtogroup STM32_TIMv1
* @{
*/
-#ifndef _STM32_TIM_H_
-#define _STM32_TIM_H_
+#ifndef STM32_TIM_H
+#define STM32_TIM_H
/*===========================================================================*/
/* Driver constants. */
@@ -327,7 +327,7 @@
#define STM32_TIM_DCR_DBA(n) ((n) << 0)
#define STM32_TIM_DCR_DBL_MASK (31U << 8)
-#define STM32_TIM_DCR_DBL(b) ((n) << 8)
+#define STM32_TIM_DCR_DBL(n) ((n) << 8)
/** @} */
/**
@@ -392,6 +392,9 @@
#define STM32_TIM17 ((stm32_tim_t *)TIM17_BASE)
#define STM32_TIM18 ((stm32_tim_t *)TIM18_BASE)
#define STM32_TIM19 ((stm32_tim_t *)TIM19_BASE)
+#define STM32_TIM20 ((stm32_tim_t *)TIM20_BASE)
+#define STM32_TIM21 ((stm32_tim_t *)TIM21_BASE)
+#define STM32_TIM22 ((stm32_tim_t *)TIM22_BASE)
/** @} */
/*===========================================================================*/
@@ -431,8 +434,7 @@ typedef struct {
volatile uint32_t DMAR;
volatile uint32_t OR;
volatile uint32_t CCMR3;
- volatile uint32_t CCR5;
- volatile uint32_t CCR6;
+ volatile uint32_t CCXR[2];
} stm32_tim_t;
/*===========================================================================*/
@@ -443,6 +445,6 @@ typedef struct {
/* External declarations. */
/*===========================================================================*/
-#endif /* _STM32_TIM_H_ */
+#endif /* STM32_TIM_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt
new file mode 100644
index 0000000000..9c980c51e9
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt
@@ -0,0 +1,14 @@
+TIM units IRQ collisions mapping.
+
+ 1B 1UP 1TC 1CC 2 3 4 5 6 7 8B 8UP 8TC 8CC 9 10 11 12 13 14 15 16 17 18 19 20 21 22 LP1 LP2
+F0xx 1---1 2---2 * * * * * * * *
+F030 1---1 2---2 * * * * *
+F1xx 1 2 3 * * * * * * * 1 2 3
+F100 1 2 3 * * * * * * * 1 2 3
+F3xx 1 2 3 * * * * * * * * * * 1 2 3
+F37x * * * * * * * * * * * * * *
+F4xx 1 2 3 * * * * * * * 4 5 6 * 1 2 3 4 5 6
+F7xx 1 2 3 * * * * * * * 4 5 6 * 1 2 3 4 5 6 *
+L0xx * * * * *
+L1xx * * * * * * * * *
+L4xx 1 2 3 * * * * * * * * * * * 1 2 3 * *
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/driver.mk
new file mode 100644
index 0000000000..4f46aebd5c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/driver.mk
@@ -0,0 +1,13 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c
+endif
+ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/serial_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c
similarity index 72%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/serial_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c
index 5a14e455c7..42227ba8a5 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/serial_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/USARTv1/serial_lld.c
+ * @file USARTv1/hal_serial_lld.c
* @brief STM32 low level serial driver code.
*
* @addtogroup SERIAL
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
@@ -65,6 +64,16 @@ SerialDriver SD5;
SerialDriver SD6;
#endif
+/** @brief UART7 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+SerialDriver SD7;
+#endif
+
+/** @brief UART8 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+SerialDriver SD8;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -74,7 +83,7 @@ static const SerialConfig default_config =
{
SERIAL_DEFAULT_BITRATE,
0,
- USART_CR2_STOP1_BITS | USART_CR2_LINEN,
+ USART_CR2_STOP1_BITS,
0
};
@@ -111,6 +120,15 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
u->SR = 0;
(void)u->SR; /* SR reset step 1.*/
(void)u->DR; /* SR reset step 2.*/
+
+ /* Deciding mask to be applied on the data register on receive, this is
+ required in order to mask out the parity bit.*/
+ if ((config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_PCE) {
+ sdp->rxmask = 0x7F;
+ }
+ else {
+ sdp->rxmask = 0xFF;
+ }
}
/**
@@ -133,7 +151,7 @@ static void usart_deinit(USART_TypeDef *u) {
* @param[in] sr USART SR register value
*/
static void set_error(SerialDriver *sdp, uint16_t sr) {
- flagsmask_t sts = 0;
+ eventflags_t sts = 0;
if (sr & USART_SR_ORE)
sts |= SD_OVERRUN_ERROR;
@@ -158,50 +176,55 @@ static void serve_interrupt(SerialDriver *sdp) {
/* Special case, LIN break detection.*/
if (sr & USART_SR_LBD) {
- chSysLockFromIsr();
+ osalSysLockFromISR();
chnAddFlagsI(sdp, SD_BREAK_DETECTED);
- chSysUnlockFromIsr();
u->SR = ~USART_SR_LBD;
+ osalSysUnlockFromISR();
}
/* Data available.*/
- chSysLockFromIsr();
- while (sr & USART_SR_RXNE) {
+ osalSysLockFromISR();
+ while (sr & (USART_SR_RXNE | USART_SR_ORE | USART_SR_NE | USART_SR_FE |
+ USART_SR_PE)) {
+ uint8_t b;
+
/* Error condition detection.*/
if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE))
set_error(sdp, sr);
- sdIncomingDataI(sdp, u->DR);
+ b = (uint8_t)u->DR & sdp->rxmask;
+ if (sr & USART_SR_RXNE)
+ sdIncomingDataI(sdp, b);
sr = u->SR;
}
- chSysUnlockFromIsr();
+ osalSysUnlockFromISR();
/* Transmission buffer empty.*/
if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) {
msg_t b;
- chSysLockFromIsr();
- b = chOQGetI(&sdp->oqueue);
- if (b < Q_OK) {
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ if (b < MSG_OK) {
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
}
else
u->DR = b;
- chSysUnlockFromIsr();
+ osalSysUnlockFromISR();
}
/* Physical transmission end.*/
if (sr & USART_SR_TC) {
- chSysLockFromIsr();
- if (chOQIsEmptyI(&sdp->oqueue))
+ osalSysLockFromISR();
+ if (oqIsEmptyI(&sdp->oqueue))
chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
u->CR1 = cr1 & ~USART_CR1_TCIE;
u->SR = ~USART_SR_TC;
- chSysUnlockFromIsr();
+ osalSysUnlockFromISR();
}
}
#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
+static void notify1(io_queue_t *qp) {
(void)qp;
USART1->CR1 |= USART_CR1_TXEIE;
@@ -209,7 +232,7 @@ static void notify1(GenericQueue *qp) {
#endif
#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
+static void notify2(io_queue_t *qp) {
(void)qp;
USART2->CR1 |= USART_CR1_TXEIE;
@@ -217,7 +240,7 @@ static void notify2(GenericQueue *qp) {
#endif
#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
+static void notify3(io_queue_t *qp) {
(void)qp;
USART3->CR1 |= USART_CR1_TXEIE;
@@ -225,7 +248,7 @@ static void notify3(GenericQueue *qp) {
#endif
#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-static void notify4(GenericQueue *qp) {
+static void notify4(io_queue_t *qp) {
(void)qp;
UART4->CR1 |= USART_CR1_TXEIE;
@@ -233,7 +256,7 @@ static void notify4(GenericQueue *qp) {
#endif
#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-static void notify5(GenericQueue *qp) {
+static void notify5(io_queue_t *qp) {
(void)qp;
UART5->CR1 |= USART_CR1_TXEIE;
@@ -241,13 +264,29 @@ static void notify5(GenericQueue *qp) {
#endif
#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-static void notify6(GenericQueue *qp) {
+static void notify6(io_queue_t *qp) {
(void)qp;
USART6->CR1 |= USART_CR1_TXEIE;
}
#endif
+#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+static void notify7(io_queue_t *qp) {
+
+ (void)qp;
+ UART7->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+static void notify8(io_queue_t *qp) {
+
+ (void)qp;
+ UART8->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@@ -261,13 +300,13 @@ static void notify6(GenericQueue *qp) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -280,13 +319,13 @@ CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -299,13 +338,13 @@ CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -318,13 +357,13 @@ CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -337,13 +376,13 @@ CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD5);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -352,17 +391,55 @@ CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
#error "STM32_USART6_HANDLER not defined"
#endif
/**
- * @brief USART1 interrupt handler.
+ * @brief USART6 interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD6);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+#if !defined(STM32_UART7_HANDLER)
+#error "STM32_UART7_HANDLER not defined"
+#endif
+/**
+ * @brief UART7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+#if !defined(STM32_UART8_HANDLER)
+#error "STM32_UART8_HANDLER not defined"
+#endif
+/**
+ * @brief UART8 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD8);
+
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -406,6 +483,16 @@ void sd_lld_init(void) {
sdObjectInit(&SD6, NULL, notify6);
SD6.usart = USART6;
#endif
+
+#if STM32_SERIAL_USE_UART7
+ sdObjectInit(&SD7, NULL, notify7);
+ SD7.usart = UART7;
+#endif
+
+#if STM32_SERIAL_USE_UART8
+ sdObjectInit(&SD8, NULL, notify8);
+ SD8.usart = UART8;
+#endif
}
/**
@@ -427,43 +514,49 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
#if STM32_SERIAL_USE_USART1
if (&SD1 == sdp) {
rccEnableUSART1(FALSE);
- nvicEnableVector(STM32_USART1_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
+ nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART2
if (&SD2 == sdp) {
rccEnableUSART2(FALSE);
- nvicEnableVector(STM32_USART2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
+ nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART3
if (&SD3 == sdp) {
rccEnableUSART3(FALSE);
- nvicEnableVector(STM32_USART3_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
+ nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_UART4
if (&SD4 == sdp) {
rccEnableUART4(FALSE);
- nvicEnableVector(STM32_UART4_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
+ nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_UART5
if (&SD5 == sdp) {
rccEnableUART5(FALSE);
- nvicEnableVector(STM32_UART5_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
+ nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART6
if (&SD6 == sdp) {
rccEnableUSART6(FALSE);
- nvicEnableVector(STM32_USART6_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY));
+ nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
+ }
+#endif
+#if STM32_SERIAL_USE_UART7
+ if (&SD7 == sdp) {
+ rccEnableUART7(FALSE);
+ nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY);
+ }
+#endif
+#if STM32_SERIAL_USE_UART8
+ if (&SD8 == sdp) {
+ rccEnableUART8(FALSE);
+ nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY);
}
#endif
}
@@ -524,6 +617,20 @@ void sd_lld_stop(SerialDriver *sdp) {
nvicDisableVector(STM32_USART6_NUMBER);
return;
}
+#endif
+#if STM32_SERIAL_USE_UART7
+ if (&SD7 == sdp) {
+ rccDisableUART7(FALSE);
+ nvicDisableVector(STM32_UART7_NUMBER);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_UART8
+ if (&SD8 == sdp) {
+ rccDisableUART8(FALSE);
+ nvicDisableVector(STM32_UART8_NUMBER);
+ return;
+ }
#endif
}
}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/serial_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.h
similarity index 76%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/serial_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.h
index c1a9e2f9b5..0546c15c54 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/serial_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/USARTv1/serial_lld.h
+ * @file USARTv1/hal_serial_lld.h
* @brief STM32 low level serial driver header.
*
* @addtogroup SERIAL
* @{
*/
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
+#ifndef HAL_SERIAL_LLD_H
+#define HAL_SERIAL_LLD_H
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
@@ -42,7 +42,7 @@
/**
* @brief USART1 driver enable switch.
* @details If set to @p TRUE the support for USART1 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART1 FALSE
@@ -51,7 +51,7 @@
/**
* @brief USART2 driver enable switch.
* @details If set to @p TRUE the support for USART2 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART2 FALSE
@@ -60,7 +60,7 @@
/**
* @brief USART3 driver enable switch.
* @details If set to @p TRUE the support for USART3 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART3 FALSE
@@ -69,7 +69,7 @@
/**
* @brief UART4 driver enable switch.
* @details If set to @p TRUE the support for UART4 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_UART4 FALSE
@@ -78,7 +78,7 @@
/**
* @brief UART5 driver enable switch.
* @details If set to @p TRUE the support for UART5 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_UART5 FALSE
@@ -87,12 +87,30 @@
/**
* @brief USART6 driver enable switch.
* @details If set to @p TRUE the support for USART6 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART6 FALSE
#endif
+/**
+ * @brief UART7 driver enable switch.
+ * @details If set to @p TRUE the support for UART7 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SERIAL_USE_UART7) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART7 FALSE
+#endif
+
+/**
+ * @brief UART8 driver enable switch.
+ * @details If set to @p TRUE the support for UART8 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SERIAL_USE_UART8) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART8 FALSE
+#endif
+
/**
* @brief USART1 interrupt priority level setting.
*/
@@ -134,6 +152,20 @@
#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_USART6_PRIORITY 12
#endif
+
+/**
+ * @brief UART7 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART7_PRIORITY 12
+#endif
+
+/**
+ * @brief UART8 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART8_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART8_PRIORITY 12
+#endif
/** @} */
/*===========================================================================*/
@@ -164,42 +196,61 @@
#error "USART6 not present in the selected device"
#endif
+#if STM32_SERIAL_USE_UART7 && !STM32_HAS_UART7
+#error "UART7 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_UART8 && !STM32_HAS_UART8
+#error "UART8 not present in the selected device"
+#endif
+
#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \
!STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \
- !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6
+ !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 && \
+ !STM32_SERIAL_USE_UART7 && !STM32_SERIAL_USE_UART8
#error "SERIAL driver activated but no USART/UART peripheral assigned"
#endif
#if STM32_SERIAL_USE_USART1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
#error "Invalid IRQ priority assigned to USART1"
#endif
#if STM32_SERIAL_USE_USART2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
#error "Invalid IRQ priority assigned to USART2"
#endif
#if STM32_SERIAL_USE_USART3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
#error "Invalid IRQ priority assigned to USART3"
#endif
#if STM32_SERIAL_USE_UART4 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
#error "Invalid IRQ priority assigned to UART4"
#endif
#if STM32_SERIAL_USE_UART5 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
#error "Invalid IRQ priority assigned to UART5"
#endif
#if STM32_SERIAL_USE_USART6 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
#error "Invalid IRQ priority assigned to USART6"
#endif
+#if STM32_SERIAL_USE_UART7 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART7_PRIORITY)
+#error "Invalid IRQ priority assigned to UART7"
+#endif
+
+#if STM32_SERIAL_USE_UART8 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART8_PRIORITY)
+#error "Invalid IRQ priority assigned to UART8"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -240,16 +291,18 @@ typedef struct {
/* Driver state.*/ \
sdstate_t state; \
/* Input queue.*/ \
- InputQueue iqueue; \
+ input_queue_t iqueue; \
/* Output queue.*/ \
- OutputQueue oqueue; \
+ output_queue_t oqueue; \
/* Input circular buffer.*/ \
uint8_t ib[SERIAL_BUFFERS_SIZE]; \
/* Output circular buffer.*/ \
uint8_t ob[SERIAL_BUFFERS_SIZE]; \
/* End of the mandatory fields.*/ \
/* Pointer to the USART registers block.*/ \
- USART_TypeDef *usart;
+ USART_TypeDef *usart; \
+ /* Mask to be applied on received frames.*/ \
+ uint8_t rxmask;
/*===========================================================================*/
/* Driver macros. */
@@ -285,6 +338,12 @@ extern SerialDriver SD5;
#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
extern SerialDriver SD6;
#endif
+#if STM32_SERIAL_USE_UART7 && !defined(__DOXYGEN__)
+extern SerialDriver SD7;
+#endif
+#if STM32_SERIAL_USE_UART8 && !defined(__DOXYGEN__)
+extern SerialDriver SD8;
+#endif
#ifdef __cplusplus
extern "C" {
@@ -298,6 +357,6 @@ extern "C" {
#endif /* HAL_USE_SERIAL */
-#endif /* _SERIAL_LLD_H_ */
+#endif /* HAL_SERIAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/uart_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
similarity index 83%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/uart_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
index 81dfa8bc3e..57042893a9 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/uart_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32/USARTv1/uart_lld.c
+ * @file USARTv1/hal_uart_lld.c
* @brief STM32 low level UART driver code.
*
* @addtogroup UART
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_UART || defined(__DOXYGEN__)
@@ -157,7 +156,7 @@ static uartflags_t translate_errors(uint16_t sr) {
*
* @param[in] uartp pointer to the @p UARTDriver object
*/
-static void set_rx_idle_loop(UARTDriver *uartp) {
+static void uart_enter_rx_idle_loop(UARTDriver *uartp) {
uint32_t mode;
/* RX DMA channel preparation, if the char callback is defined then the
@@ -223,15 +222,14 @@ static void usart_start(UARTDriver *uartp) {
u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
USART_CR3_EIE;
- if (uartp->config->txend2_cb == NULL)
- cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
- else
- cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
- USART_CR1_TCIE;
+
+ /* Mustn't ever set TCIE here - if done, it causes an immediate
+ interrupt.*/
+ cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
u->CR1 = uartp->config->cr1 | cr1;
/* Starting the receiver idle loop.*/
- set_rx_idle_loop(uartp);
+ uart_enter_rx_idle_loop(uartp);
}
/**
@@ -254,23 +252,13 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
if (uartp->rxstate == UART_RX_IDLE) {
/* Receiver in idle state, a callback is generated, if enabled, for each
received character and then the driver stays in the same state.*/
- if (uartp->config->rxchar_cb != NULL)
- uartp->config->rxchar_cb(uartp, uartp->rxbuf);
+ _uart_rx_idle_code(uartp);
}
else {
/* Receiver in active state, a callback is generated, if enabled, after
a completed transfer.*/
dmaStreamDisable(uartp->dmarx);
- uartp->rxstate = UART_RX_COMPLETE;
- if (uartp->config->rxend_cb != NULL)
- uartp->config->rxend_cb(uartp);
-
- /* If the callback didn't explicitly change state then the receiver
- automatically returns to the idle state.*/
- if (uartp->rxstate == UART_RX_COMPLETE) {
- uartp->rxstate = UART_RX_IDLE;
- set_rx_idle_loop(uartp);
- }
+ _uart_rx_complete_isr_code(uartp);
}
}
@@ -294,14 +282,7 @@ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
dmaStreamDisable(uartp->dmatx);
/* A callback is generated, if enabled, after a completed transfer.*/
- uartp->txstate = UART_TX_COMPLETE;
- if (uartp->config->txend1_cb != NULL)
- uartp->config->txend1_cb(uartp);
-
- /* If the callback didn't explicitly change state then the transmitter
- automatically returns to the idle state.*/
- if (uartp->txstate == UART_TX_COMPLETE)
- uartp->txstate = UART_TX_IDLE;
+ _uart_tx1_isr_code(uartp);
}
/**
@@ -312,21 +293,24 @@ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
static void serve_usart_irq(UARTDriver *uartp) {
uint16_t sr;
USART_TypeDef *u = uartp->usart;
-
+ uint32_t cr1 = u->CR1;
+
sr = u->SR; /* SR reset step 1.*/
(void)u->DR; /* SR reset step 2.*/
+
if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE |
USART_SR_FE | USART_SR_PE)) {
u->SR = ~USART_SR_LBD;
- if (uartp->config->rxerr_cb != NULL)
- uartp->config->rxerr_cb(uartp, translate_errors(sr));
+ _uart_rx_error_isr_code(uartp, translate_errors(sr));
}
- if (sr & USART_SR_TC) {
+
+ if ((sr & USART_SR_TC) && (cr1 & USART_CR1_TCIE)) {
+ /* TC interrupt cleared and disabled.*/
u->SR = ~USART_SR_TC;
+ u->CR1 = cr1 & ~USART_CR1_TCIE;
/* End of transmission, a callback is generated.*/
- if (uartp->config->txend2_cb != NULL)
- uartp->config->txend2_cb(uartp);
+ _uart_tx2_isr_code(uartp);
}
}
@@ -343,13 +327,13 @@ static void serve_usart_irq(UARTDriver *uartp) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_USART1 */
@@ -362,13 +346,13 @@ CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_USART2 */
@@ -381,13 +365,13 @@ CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_USART3 */
@@ -400,13 +384,13 @@ CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_UART4 */
@@ -419,13 +403,13 @@ CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD5);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_UART5 */
@@ -438,13 +422,13 @@ CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD6);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_USART6 */
@@ -519,20 +503,19 @@ void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableUSART1(FALSE);
- nvicEnableVector(STM32_USART1_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
+ nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
}
@@ -540,20 +523,19 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART2
if (&UARTD2 == uartp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableUSART2(FALSE);
- nvicEnableVector(STM32_USART2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
+ nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
}
@@ -561,20 +543,19 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART3
if (&UARTD3 == uartp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableUSART3(FALSE);
- nvicEnableVector(STM32_USART3_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
+ nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
}
@@ -582,28 +563,25 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART4
if (&UARTD4 == uartp) {
- bool_t b;
+ bool b;
- chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
- "uart_lld_start(), #7",
- "specified invalid bits in UART4 CR2 register settings");
- chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
- "uart_lld_start(), #8",
- "specified invalid bits in UART4 CR3 register settings");
+ osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
+ "specified invalid bits in UART4 CR2 register settings");
+ osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
+ "specified invalid bits in UART4 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #9", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #10", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableUART4(FALSE);
- nvicEnableVector(STM32_UART4_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_UART4_IRQ_PRIORITY));
+ nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
}
@@ -611,28 +589,25 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART5
if (&UARTD5 == uartp) {
- bool_t b;
+ bool b;
- chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
- "uart_lld_start(), #11",
- "specified invalid bits in UART5 CR2 register settings");
- chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
- "uart_lld_start(), #12",
- "specified invalid bits in UART5 CR3 register settings");
+ osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
+ "specified invalid bits in UART5 CR2 register settings");
+ osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
+ "specified invalid bits in UART5 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #13", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #14", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableUART5(FALSE);
- nvicEnableVector(STM32_UART5_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_UART5_IRQ_PRIORITY));
+ nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
}
@@ -640,20 +615,19 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART6
if (&UARTD6 == uartp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #15", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
- chDbgAssert(!b, "uart_lld_start(), #16", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableUSART6(FALSE);
- nvicEnableVector(STM32_USART6_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY));
+ nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
}
@@ -750,11 +724,21 @@ void uart_lld_stop(UARTDriver *uartp) {
*/
void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
- /* TX DMA channel preparation and start.*/
+ /* TX DMA channel preparation.*/
dmaStreamSetMemory0(uartp->dmatx, txbuf);
dmaStreamSetTransactionSize(uartp->dmatx, n);
dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
+
+ /* Only enable TC interrupt if there's a callback attached to it or
+ if called from uartSendFullTimeout(). Also we need to clear TC flag
+ which could be set before.*/
+ if ((uartp->config->txend2_cb != NULL) || (uartp->early == false)) {
+ uartp->usart->SR = ~USART_SR_TC;
+ uartp->usart->CR1 |= USART_CR1_TCIE;
+ }
+
+ /* Starting transfer.*/
dmaStreamEnable(uartp->dmatx);
}
@@ -772,6 +756,7 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
size_t uart_lld_stop_send(UARTDriver *uartp) {
dmaStreamDisable(uartp->dmatx);
+
return dmaStreamGetTransactionSize(uartp->dmatx);
}
@@ -791,11 +776,13 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
/* Stopping previous activity (idle state).*/
dmaStreamDisable(uartp->dmarx);
- /* RX DMA channel preparation and start.*/
+ /* RX DMA channel preparation.*/
dmaStreamSetMemory0(uartp->dmarx, rxbuf);
dmaStreamSetTransactionSize(uartp->dmarx, n);
dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
+
+ /* Starting transfer.*/
dmaStreamEnable(uartp->dmarx);
}
@@ -815,7 +802,8 @@ size_t uart_lld_stop_receive(UARTDriver *uartp) {
dmaStreamDisable(uartp->dmarx);
n = dmaStreamGetTransactionSize(uartp->dmarx);
- set_rx_idle_loop(uartp);
+ uart_enter_rx_idle_loop(uartp);
+
return n;
}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/uart_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h
similarity index 78%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/uart_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h
index e70acd6dc0..d93e9a397f 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv1/uart_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/USARTv1/uart_lld.h
+ * @file USARTv1/hal_uart_lld.h
* @brief STM32 low level UART driver header.
*
* @addtogroup UART
* @{
*/
-#ifndef _UART_LLD_H_
-#define _UART_LLD_H_
+#ifndef HAL_UART_LLD_H
+#define HAL_UART_LLD_H
#if HAL_USE_UART || defined(__DOXYGEN__)
@@ -201,121 +201,8 @@
* error can only happen because programming errors.
*/
#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief DMA stream used for USART1 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
-#endif
-
-/**
- * @brief DMA stream used for USART1 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
-#endif
-
-/**
- * @brief DMA stream used for USART2 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#endif
-
-/**
- * @brief DMA stream used for USART2 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
-#endif
-
-/**
- * @brief DMA stream used for USART3 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
-#endif
-
-/**
- * @brief DMA stream used for USART3 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#endif
-
-/**
- * @brief DMA stream used for UART4 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_UART4_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#endif
-
-/**
- * @brief DMA stream used for UART4 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_UART4_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#endif
-
-/**
- * @brief DMA stream used for UART5 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_UART5_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
-#endif
-
-/**
- * @brief DMA stream used for UART5 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_UART5_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#endif
-
-/**
- * @brief DMA stream used for USART6 RX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART6_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
-#endif
-
-/**
- * @brief DMA stream used for USART6 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART6_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
-#endif
-
-#else /* !STM32_ADVANCED_DMA */
-
-/* Fixed streams for platforms using the old DMA peripheral, the values are
- valid for both STM32F1xx and STM32L1xx.*/
-#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
-#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
-
-#endif /* !STM32_ADVANCED_DMA*/
/** @} */
/*===========================================================================*/
@@ -339,7 +226,8 @@
#error "UART4 not present in the selected device"
#endif
-#if !defined(STM32F2XX) && !defined(STM32F4XX)
+#if !defined(STM32F2XX) && !defined(STM32F4XX) && !defined(STM32L151xE) && \
+ !defined(STM32L152xE) && !defined(STM32L162xE)
#error "UART4 DMA access not supported in this platform"
#endif
#endif /* STM32_UART_USE_UART4 */
@@ -349,7 +237,8 @@
#error "UART5 not present in the selected device"
#endif
-#if !defined(STM32F2XX) && !defined(STM32F4XX)
+#if !defined(STM32F2XX) && !defined(STM32F4XX) && !defined(STM32L151xE) && \
+ !defined(STM32L152xE) && !defined(STM32L162xE)
#error "UART5 DMA access not supported in this platform"
#endif
#endif /* STM32_UART_USE_UART5 */
@@ -365,32 +254,32 @@
#endif
#if STM32_UART_USE_USART1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART1"
#endif
#if STM32_UART_USE_USART2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART2"
#endif
#if STM32_UART_USE_USART3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART3"
#endif
#if STM32_UART_USE_UART4 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to UART4"
#endif
#if STM32_UART_USE_UART5 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to UART5"
#endif
#if STM32_UART_USE_USART6 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART6"
#endif
@@ -424,6 +313,41 @@
#error "Invalid DMA priority assigned to USART6"
#endif
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) || \
+ !defined(STM32_UART_USART1_TX_DMA_STREAM))
+#error "USART1 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_STREAM) || \
+ !defined(STM32_UART_USART2_TX_DMA_STREAM))
+#error "USART2 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_STREAM) || \
+ !defined(STM32_UART_USART3_TX_DMA_STREAM))
+#error "USART3 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_STREAM) || \
+ !defined(STM32_UART_UART4_TX_DMA_STREAM))
+#error "UART4 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_STREAM) || \
+ !defined(STM32_UART_UART5_TX_DMA_STREAM))
+#error "UART5 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_STREAM) || \
+ !defined(STM32_UART_USART6_TX_DMA_STREAM))
+#error "USART6 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
STM32_USART1_RX_DMA_MSK)
@@ -495,6 +419,7 @@
STM32_USART6_TX_DMA_MSK)
#error "invalid DMA stream associated to USART6 TX"
#endif
+#endif /* STM32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
@@ -601,6 +526,26 @@ struct UARTDriver {
* @brief Current configuration data.
*/
const UARTConfig *config;
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Synchronization flag for transmit operations.
+ */
+ bool early;
+ /**
+ * @brief Waiting thread on RX.
+ */
+ thread_reference_t threadrx;
+ /**
+ * @brief Waiting thread on TX.
+ */
+ thread_reference_t threadtx;
+#endif /* UART_USE_WAIT */
+#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* UART_USE_MUTUAL_EXCLUSION */
#if defined(UART_DRIVER_EXT_FIELDS)
UART_DRIVER_EXT_FIELDS
#endif
@@ -675,6 +620,6 @@ extern "C" {
#endif /* HAL_USE_UART */
-#endif /* _UART_LLD_H_ */
+#endif /* HAL_UART_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/driver.mk
new file mode 100644
index 0000000000..6b614601d3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/driver.mk
@@ -0,0 +1,13 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
+endif
+ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
new file mode 100644
index 0000000000..12bd424223
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
@@ -0,0 +1,891 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file USARTv2/hal_serial_lld.c
+ * @brief STM32 low level serial driver code.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/* For compatibility for those devices without LIN support in the USARTs.*/
+#if !defined(USART_ISR_LBDF)
+#define USART_ISR_LBDF 0
+#endif
+
+#if !defined(USART_CR2_LBDIE)
+#define USART_CR2_LBDIE 0
+#endif
+
+/* STM32L0xx/STM32F7xx ST headers difference.*/
+#if !defined(USART_ISR_LBDF)
+#define USART_ISR_LBDF USART_ISR_LBD
+#endif
+
+/* Handling differences in frame size bits.*/
+#if !defined(USART_CR1_M_0)
+#define USART_CR1_M_0 (1 << 12)
+#endif
+
+#if !defined(USART_CR1_M_1)
+#define USART_CR1_M_1 (1 << 28)
+#endif
+
+/* Workarounds for those devices where UARTs are USARTs.*/
+#if defined(USART4)
+#define UART4 USART4
+#endif
+#if defined(USART5)
+#define UART5 USART5
+#endif
+#if defined(USART7)
+#define UART7 USART7
+#endif
+#if defined(USART8)
+#define UART8 USART8
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief USART1 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/** @brief USART2 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/** @brief USART3 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/** @brief UART4 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+/** @brief UART5 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+/** @brief USART6 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
+/** @brief UART7 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+SerialDriver SD7;
+#endif
+
+/** @brief UART8 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+SerialDriver SD8;
+#endif
+
+/** @brief LPUART1 serial driver identifier.*/
+#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
+SerialDriver LPSD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/** @brief Driver default configuration.*/
+static const SerialConfig default_config =
+{
+ SERIAL_DEFAULT_BITRATE,
+ 0,
+ USART_CR2_STOP1_BITS,
+ 0
+};
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD1.*/
+static uint8_t sd_in_buf1[STM32_SERIAL_USART1_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD1.*/
+static uint8_t sd_out_buf1[STM32_SERIAL_USART1_OUT_BUF_SIZE];
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD2.*/
+static uint8_t sd_in_buf2[STM32_SERIAL_USART2_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD2.*/
+static uint8_t sd_out_buf2[STM32_SERIAL_USART2_OUT_BUF_SIZE];
+#endif
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD3.*/
+static uint8_t sd_in_buf3[STM32_SERIAL_USART3_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD3.*/
+static uint8_t sd_out_buf3[STM32_SERIAL_USART3_OUT_BUF_SIZE];
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD4.*/
+static uint8_t sd_in_buf4[STM32_SERIAL_UART4_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD4.*/
+static uint8_t sd_out_buf4[STM32_SERIAL_UART4_OUT_BUF_SIZE];
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD5.*/
+static uint8_t sd_in_buf5[STM32_SERIAL_UART5_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD5.*/
+static uint8_t sd_out_buf5[STM32_SERIAL_UART5_OUT_BUF_SIZE];
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD6.*/
+static uint8_t sd_in_buf6[STM32_SERIAL_USART6_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD6.*/
+static uint8_t sd_out_buf6[STM32_SERIAL_USART6_OUT_BUF_SIZE];
+#endif
+
+#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD7.*/
+static uint8_t sd_in_buf7[STM32_SERIAL_UART7_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD7.*/
+static uint8_t sd_out_buf7[STM32_SERIAL_UART7_OUT_BUF_SIZE];
+#endif
+
+#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD8.*/
+static uint8_t sd_in_buf8[STM32_SERIAL_UART8_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD8.*/
+static uint8_t sd_out_buf8[STM32_SERIAL_UART8_OUT_BUF_SIZE];
+#endif
+
+#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
+/** @brief Input buffer for LPSD1.*/
+static uint8_t sd_in_buflp1[STM32_SERIAL_LPUART1_IN_BUF_SIZE];
+
+/** @brief Output buffer for LPSD1.*/
+static uint8_t sd_out_buflp1[STM32_SERIAL_LPUART1_OUT_BUF_SIZE];
+#endif
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief USART initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration
+ */
+static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
+ USART_TypeDef *u = sdp->usart;
+
+ /* Baud rate setting.*/
+#if STM32_SERIAL_USE_LPUART1
+ if ( sdp == &LPSD1 )
+ {
+ u->BRR = (uint32_t)( ( (uint64_t)sdp->clock * 256 ) / config->speed);
+ }
+ else
+#endif
+ u->BRR = (uint32_t)(sdp->clock / config->speed);
+
+ /* Note that some bits are enforced.*/
+ u->CR2 = config->cr2 | USART_CR2_LBDIE;
+ u->CR3 = config->cr3 | USART_CR3_EIE;
+ u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
+ USART_CR1_RXNEIE | USART_CR1_TE |
+ USART_CR1_RE;
+ u->ICR = 0xFFFFFFFFU;
+
+ /* Deciding mask to be applied on the data register on receive, this is
+ required in order to mask out the parity bit.*/
+ if ((config->cr1 & USART_CR1_PCE) != 0U) {
+ switch (config->cr1 & (USART_CR1_M_1 | USART_CR1_M_0)) {
+ case 0:
+ sdp->rxmask = 0x7F;
+ break;
+ case USART_CR1_M_1:
+ sdp->rxmask = 0x3F;
+ break;
+ default:
+ sdp->rxmask = 0xFF;
+ }
+ }
+ else {
+ sdp->rxmask = 0xFF;
+ }
+}
+
+/**
+ * @brief USART de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] u pointer to an USART I/O block
+ */
+static void usart_deinit(USART_TypeDef *u) {
+
+ u->CR1 = 0;
+ u->CR2 = 0;
+ u->CR3 = 0;
+}
+
+/**
+ * @brief Error handling routine.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] isr USART ISR register value
+ */
+static void set_error(SerialDriver *sdp, uint32_t isr) {
+ eventflags_t sts = 0;
+
+ if (isr & USART_ISR_ORE)
+ sts |= SD_OVERRUN_ERROR;
+ if (isr & USART_ISR_PE)
+ sts |= SD_PARITY_ERROR;
+ if (isr & USART_ISR_FE)
+ sts |= SD_FRAMING_ERROR;
+ if (isr & USART_ISR_NE)
+ sts |= SD_NOISE_ERROR;
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, sts);
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Common IRQ handler.
+ *
+ * @param[in] sdp communication channel associated to the USART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ USART_TypeDef *u = sdp->usart;
+ uint32_t cr1 = u->CR1;
+ uint32_t isr;
+
+ /* Reading and clearing status.*/
+ isr = u->ISR;
+ u->ICR = isr;
+
+ /* Error condition detection.*/
+ if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE))
+ set_error(sdp, isr);
+
+ /* Special case, LIN break detection.*/
+ if (isr & USART_ISR_LBDF) {
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, SD_BREAK_DETECTED);
+ osalSysUnlockFromISR();
+ }
+
+ /* Data available.*/
+ if (isr & USART_ISR_RXNE) {
+ osalSysLockFromISR();
+ sdIncomingDataI(sdp, (uint8_t)u->RDR & sdp->rxmask);
+ osalSysUnlockFromISR();
+ }
+
+ /* Transmission buffer empty.*/
+ if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
+ msg_t b;
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ if (b < MSG_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
+ }
+ else
+ u->TDR = b;
+ osalSysUnlockFromISR();
+ }
+
+ /* Physical transmission end.*/
+ if (isr & USART_ISR_TC) {
+ osalSysLockFromISR();
+ if (oqIsEmptyI(&sdp->oqueue))
+ chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
+ u->CR1 = cr1 & ~USART_CR1_TCIE;
+ osalSysUnlockFromISR();
+ }
+}
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp) {
+
+ (void)qp;
+ USART1->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp) {
+
+ (void)qp;
+ USART2->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp) {
+
+ (void)qp;
+ USART3->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+static void notify4(io_queue_t *qp) {
+
+ (void)qp;
+ UART4->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+static void notify5(io_queue_t *qp) {
+
+ (void)qp;
+ UART5->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+static void notify6(io_queue_t *qp) {
+
+ (void)qp;
+ USART6->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+static void notify7(io_queue_t *qp) {
+
+ (void)qp;
+ UART7->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+static void notify8(io_queue_t *qp) {
+
+ (void)qp;
+ UART8->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
+static void notifylp1(io_queue_t *qp) {
+
+ (void)qp;
+ LPUART1->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+#if !defined(STM32_USART1_HANDLER)
+#error "STM32_USART1_HANDLER not defined"
+#endif
+/**
+ * @brief USART1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+#if !defined(STM32_USART2_HANDLER)
+#error "STM32_USART2_HANDLER not defined"
+#endif
+/**
+ * @brief USART2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_USART3_8_HANDLER)
+#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
+ STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \
+ STM32_SERIAL_USE_UART7 || STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+/**
+ * @brief USART3..8 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART3_8_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+#if STM32_SERIAL_USE_USART3
+ serve_interrupt(&SD3);
+#endif
+#if STM32_SERIAL_USE_UART4
+ serve_interrupt(&SD4);
+#endif
+#if STM32_SERIAL_USE_UART5
+ serve_interrupt(&SD5);
+#endif
+#if STM32_SERIAL_USE_USART6
+ serve_interrupt(&SD6);
+#endif
+#if STM32_SERIAL_USE_UART7
+ serve_interrupt(&SD7);
+#endif
+#if STM32_SERIAL_USE_UART8
+ serve_interrupt(&SD8);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#else /* !defined(STM32_USART3_8_HANDLER) */
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+#if !defined(STM32_USART3_HANDLER)
+#error "STM32_USART3_HANDLER not defined"
+#endif
+/**
+ * @brief USART3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(STM32_UART4_HANDLER)
+#error "STM32_UART4_HANDLER not defined"
+#endif
+/**
+ * @brief UART4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(STM32_UART5_HANDLER)
+#error "STM32_UART5_HANDLER not defined"
+#endif
+/**
+ * @brief UART5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+#if !defined(STM32_USART6_HANDLER)
+#error "STM32_USART6_HANDLER not defined"
+#endif
+/**
+ * @brief USART6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+#if !defined(STM32_UART7_HANDLER)
+#error "STM32_UART7_HANDLER not defined"
+#endif
+/**
+ * @brief UART7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+#if !defined(STM32_UART8_HANDLER)
+#error "STM32_UART8_HANDLER not defined"
+#endif
+/**
+ * @brief UART8 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#endif /* !defined(STM32_USART3_8_HANDLER) */
+
+#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
+#if !defined(STM32_LPUART1_HANDLER)
+#error "STM32_LPUART1_HANDLER not defined"
+#endif
+/**
+ * @brief LPUART1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_LPUART1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&LPSD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if STM32_SERIAL_USE_USART1
+ sdObjectInit(&SD1);
+ iqObjectInit(&SD1.iqueue, sd_in_buf1, sizeof sd_in_buf1, NULL, &SD1);
+ oqObjectInit(&SD1.oqueue, sd_out_buf1, sizeof sd_out_buf1, notify1, &SD1);
+ SD1.usart = USART1;
+ SD1.clock = STM32_USART1CLK;
+#if defined(STM32_USART1_NUMBER)
+ nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_USART2
+ sdObjectInit(&SD2);
+ iqObjectInit(&SD2.iqueue, sd_in_buf2, sizeof sd_in_buf2, NULL, &SD2);
+ oqObjectInit(&SD2.oqueue, sd_out_buf2, sizeof sd_out_buf2, notify2, &SD2);
+ SD2.usart = USART2;
+ SD2.clock = STM32_USART2CLK;
+#if defined(STM32_USART2_NUMBER)
+ nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_USART3
+ sdObjectInit(&SD3);
+ iqObjectInit(&SD3.iqueue, sd_in_buf3, sizeof sd_in_buf3, NULL, &SD3);
+ oqObjectInit(&SD3.oqueue, sd_out_buf3, sizeof sd_out_buf3, notify3, &SD3);
+ SD3.usart = USART3;
+ SD3.clock = STM32_USART3CLK;
+#if defined(STM32_USART3_NUMBER)
+ nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_UART4
+ sdObjectInit(&SD4);
+ iqObjectInit(&SD4.iqueue, sd_in_buf4, sizeof sd_in_buf4, NULL, &SD4);
+ oqObjectInit(&SD4.oqueue, sd_out_buf4, sizeof sd_out_buf4, notify4, &SD4);
+ SD4.usart = UART4;
+ SD4.clock = STM32_UART4CLK;
+#if defined(STM32_UART4_NUMBER)
+ nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_UART5
+ sdObjectInit(&SD5);
+ iqObjectInit(&SD5.iqueue, sd_in_buf5, sizeof sd_in_buf5, NULL, &SD5);
+ oqObjectInit(&SD5.oqueue, sd_out_buf5, sizeof sd_out_buf5, notify5, &SD5);
+ SD5.usart = UART5;
+ SD5.clock = STM32_UART5CLK;
+#if defined(STM32_UART5_NUMBER)
+ nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_USART6
+ sdObjectInit(&SD6);
+ iqObjectInit(&SD6.iqueue, sd_in_buf6, sizeof sd_in_buf6, NULL, &SD6);
+ oqObjectInit(&SD6.oqueue, sd_out_buf6, sizeof sd_out_buf6, notify6, &SD6);
+ SD6.usart = USART6;
+ SD6.clock = STM32_USART6CLK;
+#if defined(STM32_USART6_NUMBER)
+ nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_UART7
+ sdObjectInit(&SD7);
+ iqObjectInit(&SD7.iqueue, sd_in_buf7, sizeof sd_in_buf7, NULL, &SD7);
+ oqObjectInit(&SD7.oqueue, sd_out_buf7, sizeof sd_out_buf7, notify7, &SD7);
+ SD7.usart = UART7;
+ SD7.clock = STM32_UART7CLK;
+#if defined(STM32_UART7_NUMBER)
+ nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_UART8
+ sdObjectInit(&SD8);
+ iqObjectInit(&SD8.iqueue, sd_in_buf8, sizeof sd_in_buf8, NULL, &SD8);
+ oqObjectInit(&SD8.oqueue, sd_out_buf8, sizeof sd_out_buf8, notify8, &SD8);
+ SD8.usart = UART8;
+ SD8.clock = STM32_UART8CLK;
+#if defined(STM32_UART8_NUMBER)
+ nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_LPUART1
+ sdObjectInit(&LPSD1);
+ iqObjectInit(&LPSD1.iqueue, sd_in_buflp1, sizeof sd_in_buflp1, NULL, &LPSD1);
+ oqObjectInit(&LPSD1.oqueue, sd_out_buflp1, sizeof sd_out_buflp1, notifylp1, &LPSD1);
+ LPSD1.usart = LPUART1;
+ LPSD1.clock = STM32_LPUART1CLK;
+#if defined(STM32_LPUART1_NUMBER)
+ nvicEnableVector(STM32_LPUART1_NUMBER, STM32_SERIAL_LPUART1_PRIORITY);
+#endif
+#endif
+
+#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
+ STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \
+ STM32_SERIAL_USE_UART7 || STM32_SERIAL_USE_UART8
+#if defined(STM32_USART3_8_HANDLER)
+ nvicEnableVector(STM32_USART3_8_NUMBER, STM32_SERIAL_USART3_8_PRIORITY);
+#endif
+#endif
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+#if STM32_SERIAL_USE_USART1
+ if (&SD1 == sdp) {
+ rccEnableUSART1(FALSE);
+ }
+#endif
+#if STM32_SERIAL_USE_USART2
+ if (&SD2 == sdp) {
+ rccEnableUSART2(FALSE);
+ }
+#endif
+#if STM32_SERIAL_USE_USART3
+ if (&SD3 == sdp) {
+ rccEnableUSART3(FALSE);
+ }
+#endif
+#if STM32_SERIAL_USE_UART4
+ if (&SD4 == sdp) {
+ rccEnableUART4(FALSE);
+ }
+#endif
+#if STM32_SERIAL_USE_UART5
+ if (&SD5 == sdp) {
+ rccEnableUART5(FALSE);
+ }
+#endif
+#if STM32_SERIAL_USE_USART6
+ if (&SD6 == sdp) {
+ rccEnableUSART6(FALSE);
+ }
+#endif
+#if STM32_SERIAL_USE_UART7
+ if (&SD7 == sdp) {
+ rccEnableUART7(FALSE);
+ }
+#endif
+#if STM32_SERIAL_USE_UART8
+ if (&SD8 == sdp) {
+ rccEnableUART8(FALSE);
+ }
+#endif
+#if STM32_SERIAL_USE_LPUART1
+ if (&LPSD1 == sdp) {
+ rccEnableLPUART1(FALSE);
+ }
+#endif
+ }
+ usart_init(sdp, config);
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ /* UART is de-initialized then clocks are disabled.*/
+ usart_deinit(sdp->usart);
+
+#if STM32_SERIAL_USE_USART1
+ if (&SD1 == sdp) {
+ rccDisableUSART1(FALSE);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_USART2
+ if (&SD2 == sdp) {
+ rccDisableUSART2(FALSE);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_USART3
+ if (&SD3 == sdp) {
+ rccDisableUSART3(FALSE);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_UART4
+ if (&SD4 == sdp) {
+ rccDisableUART4(FALSE);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_UART5
+ if (&SD5 == sdp) {
+ rccDisableUART5(FALSE);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_USART6
+ if (&SD6 == sdp) {
+ rccDisableUSART6(FALSE);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_UART7
+ if (&SD7 == sdp) {
+ rccDisableUART7(FALSE);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_UART8
+ if (&SD8 == sdp) {
+ rccDisableUART8(FALSE);
+ return;
+ }
+#endif
+#if STM32_SERIAL_USE_LPUART1
+ if (&LPSD1 == sdp) {
+ rccDisableLPUART1(FALSE);
+ return;
+ }
+#endif
+ }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/serial_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h
similarity index 52%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/serial_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h
index 003e200b61..37d9c05115 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USARTv2/serial_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/USARTv2/serial_lld.h
+ * @file USARTv2/hal_serial_lld.h
* @brief STM32 low level serial driver header.
*
* @addtogroup SERIAL
* @{
*/
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
+#ifndef HAL_SERIAL_LLD_H
+#define HAL_SERIAL_LLD_H
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
@@ -31,6 +31,15 @@
/* Driver constants. */
/*===========================================================================*/
+/**
+ * @brief Advanced buffering support switch.
+ * @details This constants enables the advanced buffering support in the
+ * low level driver, the queue buffer is no more part of the
+ * @p SerialDriver structure, each driver can have a different
+ * queue size.
+ */
+#define SERIAL_ADVANCED_BUFFERING_SUPPORT TRUE
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -42,7 +51,7 @@
/**
* @brief USART1 driver enable switch.
* @details If set to @p TRUE the support for USART1 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART1 FALSE
@@ -51,7 +60,7 @@
/**
* @brief USART2 driver enable switch.
* @details If set to @p TRUE the support for USART2 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART2 FALSE
@@ -60,7 +69,7 @@
/**
* @brief USART3 driver enable switch.
* @details If set to @p TRUE the support for USART3 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART3 FALSE
@@ -69,7 +78,7 @@
/**
* @brief UART4 driver enable switch.
* @details If set to @p TRUE the support for UART4 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_UART4 FALSE
@@ -78,7 +87,7 @@
/**
* @brief UART5 driver enable switch.
* @details If set to @p TRUE the support for UART5 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_UART5 FALSE
@@ -87,12 +96,39 @@
/**
* @brief USART6 driver enable switch.
* @details If set to @p TRUE the support for USART6 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART6 FALSE
#endif
+/**
+ * @brief UART7 driver enable switch.
+ * @details If set to @p TRUE the support for UART7 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SERIAL_USE_UART7) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART7 FALSE
+#endif
+
+/**
+ * @brief UART8 driver enable switch.
+ * @details If set to @p TRUE the support for UART8 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SERIAL_USE_UART8) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART8 FALSE
+#endif
+
+/**
+ * @brief LPUART1 driver enable switch.
+ * @details If set to @p TRUE the support for LPUART is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_SERIAL_USE_LPUART1) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_LPUART1 FALSE
+#endif
+
/**
* @brief USART1 interrupt priority level setting.
*/
@@ -114,6 +150,14 @@
#define STM32_SERIAL_USART3_PRIORITY 12
#endif
+/**
+ * @brief USART3..8 interrupt priority level setting.
+ * @note Only valid on those devices with a shared IRQ.
+ */
+#if !defined(STM32_SERIAL_USART3_8_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART3_8_PRIORITY 12
+#endif
+
/**
* @brief UART4 interrupt priority level setting.
*/
@@ -134,6 +178,153 @@
#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_USART6_PRIORITY 12
#endif
+
+/**
+ * @brief UART7 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART7_PRIORITY 12
+#endif
+
+/**
+ * @brief UART8 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART8_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART8_PRIORITY 12
+#endif
+
+/**
+ * @brief LPUART1 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_LPUART1_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_LPUART1_PRIORITY 12
+#endif
+
+/**
+ * @brief Input buffer size for USART1.
+ */
+#if !defined(STM32_SERIAL_USART1_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for USART1.
+ */
+#if !defined(STM32_SERIAL_USART1_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Input buffer size for USART2.
+ */
+#if !defined(STM32_SERIAL_USART2_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART2_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for USART2.
+ */
+#if !defined(STM32_SERIAL_USART2_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART2_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Input buffer size for USART3.
+ */
+#if !defined(STM32_SERIAL_USART3_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART3_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for USART3.
+ */
+#if !defined(STM32_SERIAL_USART3_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART3_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Input buffer size for UART4.
+ */
+#if !defined(STM32_SERIAL_UART4_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART4_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for UART4.
+ */
+#if !defined(STM32_SERIAL_UART4_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART4_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Input buffer size for UART5.
+ */
+#if !defined(STM32_SERIAL_UART5_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART5_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for UART5.
+ */
+#if !defined(STM32_SERIAL_UART5_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART5_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Input buffer size for USART6.
+ */
+#if !defined(STM32_SERIAL_USART6_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART6_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for USART6.
+ */
+#if !defined(STM32_SERIAL_USART6_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART6_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Input buffer size for UART7.
+ */
+#if !defined(STM32_SERIAL_UART7_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART7_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for UART7.
+ */
+#if !defined(STM32_SERIAL_UART7_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART7_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Input buffer size for UART8.
+ */
+#if !defined(STM32_SERIAL_UART8_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART8_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for UART8.
+ */
+#if !defined(STM32_SERIAL_UART8_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART8_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Input buffer size for LPUART1.
+ */
+#if !defined(STM32_SERIAL_LPUART1_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_LPUART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief Output buffer size for LPUART1.
+ */
+#if !defined(STM32_SERIAL_LPUART1_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define STM32_SERIAL_LPUART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
+#endif
/** @} */
/*===========================================================================*/
@@ -164,42 +355,84 @@
#error "USART6 not present in the selected device"
#endif
+#if STM32_SERIAL_USE_UART7 && !STM32_HAS_UART7
+#error "UART7 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_UART8 && !STM32_HAS_UART8
+#error "UART8 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_LPUART1 && !STM32_HAS_LPUART1
+#error "LPUART1 not present in the selected device"
+#endif
+
#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \
!STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \
- !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6
+ !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 && \
+ !STM32_SERIAL_USE_UART7 && !STM32_SERIAL_USE_UART8 && \
+ !STM32_SERIAL_USE_LPUART1
#error "SERIAL driver activated but no USART/UART peripheral assigned"
#endif
#if STM32_SERIAL_USE_USART1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
#error "Invalid IRQ priority assigned to USART1"
#endif
#if STM32_SERIAL_USE_USART2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
#error "Invalid IRQ priority assigned to USART2"
#endif
+#if defined(STM32_USART3_8_HANDLER)
+
+#if (STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
+ STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \
+ STM32_SERIAL_USE_UART7 || STM32_SERIAL_USE_UART8) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART3_8_PRIORITY)
+#error "Invalid IRQ priority assigned to USART3..8"
+#endif
+
+#else /* !defined(STM32_USART3_8_HANDLER) */
+
#if STM32_SERIAL_USE_USART3 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
#error "Invalid IRQ priority assigned to USART3"
#endif
#if STM32_SERIAL_USE_UART4 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
#error "Invalid IRQ priority assigned to UART4"
#endif
#if STM32_SERIAL_USE_UART5 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
#error "Invalid IRQ priority assigned to UART5"
#endif
#if STM32_SERIAL_USE_USART6 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
#error "Invalid IRQ priority assigned to USART6"
#endif
+#if STM32_SERIAL_USE_UART7 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART7_PRIORITY)
+#error "Invalid IRQ priority assigned to UART7"
+#endif
+
+#if STM32_SERIAL_USE_UART8 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART8_PRIORITY)
+#error "Invalid IRQ priority assigned to UART8"
+#endif
+
+#endif /* !defined(STM32_USART3_8_HANDLER) */
+
+#if STM32_SERIAL_USE_LPUART1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_LPUART1_PRIORITY)
+#error "Invalid IRQ priority assigned to LPUART1"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -240,18 +473,16 @@ typedef struct {
/* Driver state.*/ \
sdstate_t state; \
/* Input queue.*/ \
- InputQueue iqueue; \
+ input_queue_t iqueue; \
/* Output queue.*/ \
- OutputQueue oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ output_queue_t oqueue; \
/* End of the mandatory fields.*/ \
/* Pointer to the USART registers block.*/ \
USART_TypeDef *usart; \
/* Clock frequency for the associated USART/UART.*/ \
- uint32_t clock;
+ uint32_t clock; \
+ /* Mask to be applied on received frames.*/ \
+ uint8_t rxmask;
/*===========================================================================*/
/* Driver macros. */
@@ -287,6 +518,15 @@ extern SerialDriver SD5;
#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
extern SerialDriver SD6;
#endif
+#if STM32_SERIAL_USE_UART7 && !defined(__DOXYGEN__)
+extern SerialDriver SD7;
+#endif
+#if STM32_SERIAL_USE_UART8 && !defined(__DOXYGEN__)
+extern SerialDriver SD8;
+#endif
+#if STM32_SERIAL_USE_LPUART1 && !defined(__DOXYGEN__)
+extern SerialDriver LPSD1;
+#endif
#ifdef __cplusplus
extern "C" {
@@ -300,6 +540,6 @@ extern "C" {
#endif /* HAL_USE_SERIAL */
-#endif /* _SERIAL_LLD_H_ */
+#endif /* HAL_SERIAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
new file mode 100644
index 0000000000..b0f7d08d89
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
@@ -0,0 +1,1035 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file USARTv2/hal_uart_lld.c
+ * @brief STM32 low level UART driver code.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/* For compatibility for those devices without LIN support in the USARTs.*/
+#if !defined(USART_ISR_LBDF)
+#define USART_ISR_LBDF 0
+#endif
+
+#if !defined(USART_CR2_LBDIE)
+#define USART_CR2_LBDIE 0
+#endif
+
+/* STM32L0xx/STM32F7xx ST headers difference.*/
+#if !defined(USART_ISR_LBDF)
+#define USART_ISR_LBDF USART_ISR_LBD
+#endif
+
+/* STM32L0xx/STM32F7xx ST headers difference.*/
+#if !defined(USART_ISR_LBDF)
+#define USART_ISR_LBDF USART_ISR_LBD
+#endif
+
+#define USART1_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \
+ STM32_USART1_RX_DMA_CHN)
+
+#define USART1_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \
+ STM32_USART1_TX_DMA_CHN)
+
+#define USART2_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \
+ STM32_USART2_RX_DMA_CHN)
+
+#define USART2_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \
+ STM32_USART2_TX_DMA_CHN)
+
+#define USART3_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \
+ STM32_USART3_RX_DMA_CHN)
+
+#define USART3_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
+ STM32_USART3_TX_DMA_CHN)
+
+#define UART4_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \
+ STM32_UART4_RX_DMA_CHN)
+
+#define UART4_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM, \
+ STM32_UART4_TX_DMA_CHN)
+
+#define UART5_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \
+ STM32_UART5_RX_DMA_CHN)
+
+#define UART5_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM, \
+ STM32_UART5_TX_DMA_CHN)
+
+#define USART6_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \
+ STM32_USART6_RX_DMA_CHN)
+
+#define USART6_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \
+ STM32_USART6_TX_DMA_CHN)
+
+#define UART7_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_UART7_RX_DMA_STREAM, \
+ STM32_UART7_RX_DMA_CHN)
+
+#define UART7_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_UART7_TX_DMA_STREAM, \
+ STM32_UART7_TX_DMA_CHN)
+
+#define UART8_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_UART8_RX_DMA_STREAM, \
+ STM32_UART8_RX_DMA_CHN)
+
+#define UART8_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_UART_UART8_TX_DMA_STREAM, \
+ STM32_UART8_TX_DMA_CHN)
+
+/* Workarounds for those devices where UARTs are USARTs.*/
+#if defined(USART4)
+#define UART4 USART4
+#endif
+#if defined(USART5)
+#define UART5 USART5
+#endif
+#if defined(USART7)
+#define UART7 USART7
+#endif
+#if defined(USART8)
+#define UART8 USART8
+#endif
+
+/* Workaround for more differences in headers.*/
+#if !defined(USART_CR1_M0)
+#define USART_CR1_M0 USART_CR1_M
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief USART1 UART driver identifier.*/
+#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
+UARTDriver UARTD1;
+#endif
+
+/** @brief USART2 UART driver identifier.*/
+#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
+UARTDriver UARTD2;
+#endif
+
+/** @brief USART3 UART driver identifier.*/
+#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
+UARTDriver UARTD3;
+#endif
+
+/** @brief UART4 UART driver identifier.*/
+#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
+UARTDriver UARTD4;
+#endif
+
+/** @brief UART5 UART driver identifier.*/
+#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
+UARTDriver UARTD5;
+#endif
+
+/** @brief USART6 UART driver identifier.*/
+#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
+UARTDriver UARTD6;
+#endif
+
+/** @brief UART7 UART driver identifier.*/
+#if STM32_UART_USE_UART7 || defined(__DOXYGEN__)
+UARTDriver UARTD7;
+#endif
+
+/** @brief UART8 UART driver identifier.*/
+#if STM32_UART_USE_UART8 || defined(__DOXYGEN__)
+UARTDriver UARTD8;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Status bits translation.
+ *
+ * @param[in] isr USART SR register value
+ *
+ * @return The error flags.
+ */
+static uartflags_t translate_errors(uint32_t isr) {
+ uartflags_t sts = 0;
+
+ if (isr & USART_ISR_ORE)
+ sts |= UART_OVERRUN_ERROR;
+ if (isr & USART_ISR_PE)
+ sts |= UART_PARITY_ERROR;
+ if (isr & USART_ISR_FE)
+ sts |= UART_FRAMING_ERROR;
+ if (isr & USART_ISR_NE)
+ sts |= UART_NOISE_ERROR;
+ if (isr & USART_ISR_LBDF)
+ sts |= UART_BREAK_DETECTED;
+ return sts;
+}
+
+/**
+ * @brief Puts the receiver in the UART_RX_IDLE state.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ */
+static void uart_enter_rx_idle_loop(UARTDriver *uartp) {
+ uint32_t mode;
+
+ /* RX DMA channel preparation, if the char callback is defined then the
+ TCIE interrupt is enabled too.*/
+ if (uartp->config->rxchar_cb == NULL)
+ mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
+ else
+ mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
+ dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
+ dmaStreamSetTransactionSize(uartp->dmarx, 1);
+ dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
+ dmaStreamEnable(uartp->dmarx);
+}
+
+/**
+ * @brief USART de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ */
+static void usart_stop(UARTDriver *uartp) {
+
+ /* Stops RX and TX DMA channels.*/
+ dmaStreamDisable(uartp->dmarx);
+ dmaStreamDisable(uartp->dmatx);
+
+ /* Stops USART operations.*/
+ uartp->usart->CR1 = 0;
+ uartp->usart->CR2 = 0;
+ uartp->usart->CR3 = 0;
+}
+
+/**
+ * @brief USART initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ */
+static void usart_start(UARTDriver *uartp) {
+ uint32_t cr1;
+ const uint32_t tmo = uartp->config->timeout;
+ USART_TypeDef *u = uartp->usart;
+
+ /* Defensive programming, starting from a clean state.*/
+ usart_stop(uartp);
+
+ /* Baud rate setting.*/
+ u->BRR = (uint32_t)(uartp->clock / uartp->config->speed);
+
+ /* Resetting eventual pending status flags.*/
+ u->ICR = 0xFFFFFFFFU;
+
+ /* Note that some bits are enforced because required for correct driver
+ operations.*/
+ u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
+ u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
+ USART_CR3_EIE;
+
+ /* Mustn't ever set TCIE here - if done, it causes an immediate
+ interrupt.*/
+ cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
+ u->CR1 = uartp->config->cr1 | cr1;
+
+ /* Set receive timeout and checks if it is really applied.*/
+ if (tmo > 0) {
+ osalDbgAssert(tmo <= USART_RTOR_RTO, "Timeout overflow");
+ u->RTOR = tmo;
+ osalDbgAssert(tmo == u->RTOR, "Timeout feature unsupported in this UART");
+ }
+
+ /* Starting the receiver idle loop.*/
+ uart_enter_rx_idle_loop(uartp);
+}
+
+/**
+ * @brief RX DMA common service routine.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
+
+ /* DMA errors handling.*/
+#if defined(STM32_UART_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_UART_DMA_ERROR_HOOK(uartp);
+ }
+#else
+ (void)flags;
+#endif
+
+ if (uartp->rxstate == UART_RX_IDLE) {
+ /* Receiver in idle state, a callback is generated, if enabled, for each
+ received character and then the driver stays in the same state.*/
+ _uart_rx_idle_code(uartp);
+ }
+ else {
+ /* Receiver in active state, a callback is generated, if enabled, after
+ a completed transfer.*/
+ dmaStreamDisable(uartp->dmarx);
+ _uart_rx_complete_isr_code(uartp);
+ }
+}
+
+/**
+ * @brief TX DMA common service routine.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
+
+ /* DMA errors handling.*/
+#if defined(STM32_UART_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_UART_DMA_ERROR_HOOK(uartp);
+ }
+#else
+ (void)flags;
+#endif
+
+ dmaStreamDisable(uartp->dmatx);
+
+ /* A callback is generated, if enabled, after a completed transfer.*/
+ _uart_tx1_isr_code(uartp);
+}
+
+/**
+ * @brief USART common service routine.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ */
+static void serve_usart_irq(UARTDriver *uartp) {
+ uint32_t isr;
+ USART_TypeDef *u = uartp->usart;
+ uint32_t cr1 = u->CR1;
+
+ /* Reading and clearing status.*/
+ isr = u->ISR;
+ u->ICR = isr;
+
+ if (isr & (USART_ISR_LBDF | USART_ISR_ORE | USART_ISR_NE |
+ USART_ISR_FE | USART_ISR_PE)) {
+ _uart_rx_error_isr_code(uartp, translate_errors(isr));
+ }
+
+ if ((isr & USART_ISR_TC) && (cr1 & USART_CR1_TCIE)) {
+ /* TC interrupt disabled.*/
+ u->CR1 = cr1 & ~USART_CR1_TCIE;
+
+ /* End of transmission, a callback is generated.*/
+ _uart_tx2_isr_code(uartp);
+ }
+
+ /* Timeout interrupt sources are only checked if enabled in CR1.*/
+ if (((cr1 & USART_CR1_IDLEIE) && (isr & USART_ISR_IDLE)) ||
+ ((cr1 & USART_CR1_RTOIE) && (isr & USART_ISR_RTOF))) {
+ _uart_timeout_isr_code(uartp);
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
+#if !defined(STM32_USART1_HANDLER)
+#error "STM32_USART1_HANDLER not defined"
+#endif
+/**
+ * @brief USART1 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_usart_irq(&UARTD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART1 */
+
+#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
+#if !defined(STM32_USART2_HANDLER)
+#error "STM32_USART2_HANDLER not defined"
+#endif
+/**
+ * @brief USART2 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_usart_irq(&UARTD2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART2 */
+
+#if defined(STM32_USART3_8_HANDLER)
+#if STM32_UART_USE_USART3 || STM32_UART_USE_UART4 || \
+ STM32_UART_USE_UART5 || STM32_UART_USE_USART6 || \
+ STM32_UART_USE_UART7 || STM32_UART_USE_UART8 || defined(__DOXYGEN__)
+/**
+ * @brief USART3-8 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART3_8_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+#if STM32_UART_USE_USART3
+ serve_usart_irq(&UARTD3);
+#endif
+#if STM32_UART_USE_UART4
+ serve_usart_irq(&UARTD4);
+#endif
+#if STM32_UART_USE_UART5
+ serve_usart_irq(&UARTD5);
+#endif
+#if STM32_UART_USE_USART6
+ serve_usart_irq(&UARTD6);
+#endif
+#if STM32_UART_USE_UART7
+ serve_usart_irq(&UARTD7);
+#endif
+#if STM32_UART_USE_UART8
+ serve_usart_irq(&UARTD8);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#else /* !defined(STM32_USART3_8_HANDLER) */
+
+#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
+#if !defined(STM32_USART3_HANDLER)
+#error "STM32_USART3_HANDLER not defined"
+#endif
+/**
+ * @brief USART3 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_usart_irq(&UARTD3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART3 */
+
+#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(STM32_UART4_HANDLER)
+#error "STM32_UART4_HANDLER not defined"
+#endif
+/**
+ * @brief UART4 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_usart_irq(&UARTD4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_UART4 */
+
+#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(STM32_UART5_HANDLER)
+#error "STM32_UART5_HANDLER not defined"
+#endif
+/**
+ * @brief UART5 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_usart_irq(&UARTD5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_UART5 */
+
+#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
+#if !defined(STM32_USART6_HANDLER)
+#error "STM32_USART6_HANDLER not defined"
+#endif
+/**
+ * @brief USART6 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_usart_irq(&UARTD6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART6 */
+
+#if STM32_UART_USE_UART7 || defined(__DOXYGEN__)
+#if !defined(STM32_UART7_HANDLER)
+#error "STM32_UART7_HANDLER not defined"
+#endif
+/**
+ * @brief UART7 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_usart_irq(&UARTD7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_UART7 */
+
+#if STM32_UART_USE_UART8 || defined(__DOXYGEN__)
+#if !defined(STM32_UART8_HANDLER)
+#error "STM32_UART8_HANDLER not defined"
+#endif
+/**
+ * @brief UART8 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_usart_irq(&UARTD8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_UART8 */
+
+#endif /* !defined(STM32_USART3_8_HANDLER) */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level UART driver initialization.
+ *
+ * @notapi
+ */
+void uart_lld_init(void) {
+
+#if STM32_UART_USE_USART1
+ uartObjectInit(&UARTD1);
+ UARTD1.usart = USART1;
+ UARTD1.clock = STM32_USART1CLK;
+ UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
+ UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
+#if defined(STM32_USART1_NUMBER)
+ nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_UART_USE_USART2
+ uartObjectInit(&UARTD2);
+ UARTD2.usart = USART2;
+ UARTD2.clock = STM32_USART2CLK;
+ UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
+ UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
+#if defined(STM32_USART2_NUMBER)
+ nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_UART_USE_USART3
+ uartObjectInit(&UARTD3);
+ UARTD3.usart = USART3;
+ UARTD3.clock = STM32_USART3CLK;
+ UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
+ UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
+#if defined(STM32_USART3_NUMBER)
+ nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_UART_USE_UART4
+ uartObjectInit(&UARTD4);
+ UARTD4.usart = UART4;
+ UARTD4.clock = STM32_UART4CLK;
+ UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);
+ UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);
+#if defined(STM32_UART4_NUMBER)
+ nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_UART_USE_UART5
+ uartObjectInit(&UARTD5);
+ UARTD5.usart = UART5;
+ UARTD5.clock = STM32_UART5CLK;
+ UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);
+ UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);
+#if defined(STM32_UART5_NUMBER)
+ nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_UART_USE_USART6
+ uartObjectInit(&UARTD6);
+ UARTD6.usart = USART6;
+ UARTD6.clock = STM32_USART6CLK;
+ UARTD6.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
+ UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
+#if defined(STM32_USART6_NUMBER)
+ nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_UART_USE_UART7
+ uartObjectInit(&UARTD7);
+ UARTD7.usart = UART7;
+ UARTD7.clock = STM32_UART7CLK;
+ UARTD7.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ UARTD7.dmarx = STM32_DMA_STREAM(STM32_UART_UART7_RX_DMA_STREAM);
+ UARTD7.dmatx = STM32_DMA_STREAM(STM32_UART_UART7_TX_DMA_STREAM);
+#if defined(STM32_UART7_NUMBER)
+ nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_UART_USE_UART8
+ uartObjectInit(&UARTD8);
+ UARTD8.usart = UART8;
+ UARTD8.clock = STM32_UART8CLK;
+ UARTD8.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ UARTD8.dmarx = STM32_DMA_STREAM(STM32_UART_UART8_RX_DMA_STREAM);
+ UARTD8.dmatx = STM32_DMA_STREAM(STM32_UART_UART8_TX_DMA_STREAM);
+#if defined(STM32_UART8_NUMBER)
+ nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_UART_USE_USART3 || STM32_UART_USE_UART4 || \
+ STM32_UART_USE_UART5 || STM32_UART_USE_USART6 || \
+ STM32_UART_USE_UART7 || STM32_UART_USE_UART8
+#if defined(STM32_USART3_8_HANDLER)
+ nvicEnableVector(STM32_USART3_8_NUMBER, STM32_UART_USART3_8_IRQ_PRIORITY);
+#endif
+#endif
+}
+
+/**
+ * @brief Configures and activates the UART peripheral.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_start(UARTDriver *uartp) {
+
+ if (uartp->state == UART_STOP) {
+#if STM32_UART_USE_USART1
+ if (&UARTD1 == uartp) {
+ bool b;
+ b = dmaStreamAllocate(uartp->dmarx,
+ STM32_UART_USART1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(uartp->dmatx,
+ STM32_UART_USART1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableUSART1(FALSE);
+ uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
+ }
+#endif
+
+#if STM32_UART_USE_USART2
+ if (&UARTD2 == uartp) {
+ bool b;
+ b = dmaStreamAllocate(uartp->dmarx,
+ STM32_UART_USART2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(uartp->dmatx,
+ STM32_UART_USART2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableUSART2(FALSE);
+ uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
+ }
+#endif
+
+#if STM32_UART_USE_USART3
+ if (&UARTD3 == uartp) {
+ bool b;
+ b = dmaStreamAllocate(uartp->dmarx,
+ STM32_UART_USART3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(uartp->dmatx,
+ STM32_UART_USART3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableUSART3(FALSE);
+ uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
+ }
+#endif
+
+#if STM32_UART_USE_UART4
+ if (&UARTD4 == uartp) {
+ bool b;
+ b = dmaStreamAllocate(uartp->dmarx,
+ STM32_UART_UART4_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(uartp->dmatx,
+ STM32_UART_UART4_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableUART4(FALSE);
+ uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
+ }
+#endif
+
+#if STM32_UART_USE_UART5
+ if (&UARTD5 == uartp) {
+ bool b;
+ b = dmaStreamAllocate(uartp->dmarx,
+ STM32_UART_UART5_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(uartp->dmatx,
+ STM32_UART_UART5_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableUART5(FALSE);
+ uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
+ }
+#endif
+
+#if STM32_UART_USE_USART6
+ if (&UARTD6 == uartp) {
+ bool b;
+ b = dmaStreamAllocate(uartp->dmarx,
+ STM32_UART_USART6_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(uartp->dmatx,
+ STM32_UART_USART6_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableUSART6(FALSE);
+ uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
+ }
+#endif
+
+#if STM32_UART_USE_UART7
+ if (&UARTD7 == uartp) {
+ bool b;
+ b = dmaStreamAllocate(uartp->dmarx,
+ STM32_UART_UART7_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(uartp->dmatx,
+ STM32_UART_UART7_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableUART7(FALSE);
+ uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY);
+ }
+#endif
+
+#if STM32_UART_USE_UART8
+ if (&UARTD8 == uartp) {
+ bool b;
+ b = dmaStreamAllocate(uartp->dmarx,
+ STM32_UART_UART8_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ b = dmaStreamAllocate(uartp->dmatx,
+ STM32_UART_UART8_IRQ_PRIORITY,
+ (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+ (void *)uartp);
+ osalDbgAssert(!b, "stream already allocated");
+ rccEnableUART8(FALSE);
+ uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY);
+ }
+#endif
+
+ /* Static DMA setup, the transfer size depends on the USART settings,
+ it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
+ if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M0)
+ uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+ dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
+ dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
+ uartp->rxbuf = 0;
+ }
+
+ uartp->rxstate = UART_RX_IDLE;
+ uartp->txstate = UART_TX_IDLE;
+ usart_start(uartp);
+}
+
+/**
+ * @brief Deactivates the UART peripheral.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_stop(UARTDriver *uartp) {
+
+ if (uartp->state == UART_READY) {
+ usart_stop(uartp);
+ dmaStreamRelease(uartp->dmarx);
+ dmaStreamRelease(uartp->dmatx);
+
+#if STM32_UART_USE_USART1
+ if (&UARTD1 == uartp) {
+ rccDisableUSART1(FALSE);
+ return;
+ }
+#endif
+
+#if STM32_UART_USE_USART2
+ if (&UARTD2 == uartp) {
+ rccDisableUSART2(FALSE);
+ return;
+ }
+#endif
+
+#if STM32_UART_USE_USART3
+ if (&UARTD3 == uartp) {
+ rccDisableUSART3(FALSE);
+ return;
+ }
+#endif
+
+#if STM32_UART_USE_UART4
+ if (&UARTD4 == uartp) {
+ rccDisableUART4(FALSE);
+ return;
+ }
+#endif
+
+#if STM32_UART_USE_UART5
+ if (&UARTD5 == uartp) {
+ rccDisableUART5(FALSE);
+ return;
+ }
+#endif
+
+#if STM32_UART_USE_USART6
+ if (&UARTD6 == uartp) {
+ rccDisableUSART6(FALSE);
+ return;
+ }
+#endif
+
+#if STM32_UART_USE_UART7
+ if (&UARTD7 == uartp) {
+ rccDisableUART7(FALSE);
+ return;
+ }
+#endif
+
+#if STM32_UART_USE_UART8
+ if (&UARTD8 == uartp) {
+ rccDisableUART8(FALSE);
+ return;
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Starts a transmission on the UART peripheral.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] n number of data frames to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
+
+ /* TX DMA channel preparation.*/
+ dmaStreamSetMemory0(uartp->dmatx, txbuf);
+ dmaStreamSetTransactionSize(uartp->dmatx, n);
+ dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
+
+ /* Only enable TC interrupt if there's a callback attached to it or
+ if called from uartSendFullTimeout(). Also we need to clear TC flag
+ which could be set before.*/
+ if ((uartp->config->txend2_cb != NULL) || (uartp->early == false)) {
+ uartp->usart->ICR = USART_ICR_TCCF;
+ uartp->usart->CR1 |= USART_CR1_TCIE;
+ }
+
+ /* Starting transfer.*/
+ dmaStreamEnable(uartp->dmatx);
+}
+
+/**
+ * @brief Stops any ongoing transmission.
+ * @note Stopping a transmission also suppresses the transmission callbacks.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @return The number of data frames not transmitted by the
+ * stopped transmit operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_send(UARTDriver *uartp) {
+
+ dmaStreamDisable(uartp->dmatx);
+
+ return dmaStreamGetTransactionSize(uartp->dmatx);
+}
+
+/**
+ * @brief Starts a receive operation on the UART peripheral.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] n number of data frames to send
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
+
+ /* Stopping previous activity (idle state).*/
+ dmaStreamDisable(uartp->dmarx);
+
+ /* RX DMA channel preparation.*/
+ dmaStreamSetMemory0(uartp->dmarx, rxbuf);
+ dmaStreamSetTransactionSize(uartp->dmarx, n);
+ dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
+
+ /* Starting transfer.*/
+ dmaStreamEnable(uartp->dmarx);
+}
+
+/**
+ * @brief Stops any ongoing receive operation.
+ * @note Stopping a receive operation also suppresses the receive callbacks.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @return The number of data frames not received by the
+ * stopped receive operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_receive(UARTDriver *uartp) {
+ size_t n;
+
+ dmaStreamDisable(uartp->dmarx);
+ n = dmaStreamGetTransactionSize(uartp->dmarx);
+ uart_enter_rx_idle_loop(uartp);
+
+ return n;
+}
+
+#endif /* HAL_USE_UART */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
new file mode 100644
index 0000000000..e4f88f38b0
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
@@ -0,0 +1,767 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file USARTv2/hal_uart_lld.h
+ * @brief STM32 low level UART driver header.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#ifndef HAL_UART_LLD_H
+#define HAL_UART_LLD_H
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief UART driver on USART1 enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART1 FALSE
+#endif
+
+/**
+ * @brief UART driver on USART2 enable switch.
+ * @details If set to @p TRUE the support for USART2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART2 FALSE
+#endif
+
+/**
+ * @brief UART driver on USART3 enable switch.
+ * @details If set to @p TRUE the support for USART3 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART3 FALSE
+#endif
+
+/**
+ * @brief UART driver on UART4 enable switch.
+ * @details If set to @p TRUE the support for UART4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__)
+#define STM32_UART_USE_UART4 FALSE
+#endif
+
+/**
+ * @brief UART driver on UART5 enable switch.
+ * @details If set to @p TRUE the support for UART5 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__)
+#define STM32_UART_USE_UART5 FALSE
+#endif
+
+/**
+ * @brief UART driver on USART6 enable switch.
+ * @details If set to @p TRUE the support for USART6 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART6 FALSE
+#endif
+
+/**
+ * @brief UART driver on UART7 enable switch.
+ * @details If set to @p TRUE the support for UART7 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_UART7) || defined(__DOXYGEN__)
+#define STM32_UART_USE_UART7 FALSE
+#endif
+
+/**
+ * @brief UART driver on UART8 enable switch.
+ * @details If set to @p TRUE the support for UART8 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_UART8) || defined(__DOXYGEN__)
+#define STM32_UART_USE_UART8 FALSE
+#endif
+
+/**
+ * @brief USART1 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief USART2 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief USART3 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief USART3..8 interrupt priority level setting.
+ * @note Only valid on those devices with a shared IRQ.
+ */
+#if !defined(STM32_UART_USART3_8_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART3_8_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief UART4 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief UART5 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief USART6 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief UART7 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART7_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief UART8 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_UART8_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART8_IRQ_PRIORITY 12
+#endif
+
+/**
+ * @brief USART1 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA channels but
+ * because of the channels ordering the RX channel has always priority
+ * over the TX channel.
+ */
+#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief USART2 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA channels but
+ * because of the channels ordering the RX channel has always priority
+ * over the TX channel.
+ */
+#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief USART3 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA channels but
+ * because of the channels ordering the RX channel has always priority
+ * over the TX channel.
+ */
+#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief UART4 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA channels but
+ * because of the channels ordering the RX channel has always priority
+ * over the TX channel.
+ */
+#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief UART5 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA channels but
+ * because of the channels ordering the RX channel has always priority
+ * over the TX channel.
+ */
+#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief USART6 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA channels but
+ * because of the channels ordering the RX channel has always priority
+ * over the TX channel.
+ */
+#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief UART7 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA channels but
+ * because of the channels ordering the RX channel has always priority
+ * over the TX channel.
+ */
+#if !defined(STM32_UART_UART7_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART7_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief UART8 DMA priority (0..3|lowest..highest).
+ * @note The priority level is used for both the TX and RX DMA channels but
+ * because of the channels ordering the RX channel has always priority
+ * over the TX channel.
+ */
+#if !defined(STM32_UART_UART8_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART8_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief UART DMA error hook.
+ * @note The default action for DMA errors is a system halt because DMA
+ * error can only happen because programming errors.
+ */
+#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
+#error "USART1 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
+#error "USART2 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
+#error "USART3 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_UART4 && !STM32_HAS_UART4
+#error "UART4 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_UART5 && !STM32_HAS_UART5
+#error "UART5 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_UART7 && !STM32_HAS_UART7
+#error "UART7 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_UART8 && !STM32_HAS_UART8
+#error "UART8 not present in the selected device"
+#endif
+
+#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
+ !STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 && \
+ !STM32_UART_USE_UART5 && !STM32_UART_USE_USART6 && \
+ !STM32_UART_USE_UART7 && !STM32_UART_USE_UART8
+#error "UART driver activated but no USART/UART peripheral assigned"
+#endif
+
+#if STM32_UART_USE_USART1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART1"
+#endif
+
+#if STM32_UART_USE_USART2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART2"
+#endif
+
+#if defined(STM32_USART3_8_HANDLER)
+
+#if (STM32_UART_USE_USART3 || STM32_UART_USE_UART4 || \
+ STM32_UART_USE_UART5 || STM32_UART_USE_USART6 || \
+ STM32_UART_USE_UART7 || STM32_UART_USE_UART8) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART3_8_PRIORITY)
+#error "Invalid IRQ priority assigned to USART3..8"
+#endif
+
+#else /* !defined(STM32_USART3_8_HANDLER) */
+
+#if STM32_UART_USE_USART3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART3"
+#endif
+
+#if STM32_UART_USE_UART4 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART4"
+#endif
+
+#if STM32_UART_USE_UART5 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART5"
+#endif
+
+#if STM32_UART_USE_USART6 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART6"
+#endif
+
+#if STM32_UART_USE_UART7 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART7"
+#endif
+
+#if STM32_UART_USE_UART8 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART8_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART8"
+#endif
+
+#if STM32_UART_USE_USART1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART1"
+#endif
+
+#if STM32_UART_USE_USART2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART2"
+#endif
+
+#if STM32_UART_USE_USART3 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART3"
+#endif
+
+#if STM32_UART_USE_UART4 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to UART4"
+#endif
+
+#if STM32_UART_USE_UART5 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to UART5"
+#endif
+
+#if STM32_UART_USE_USART6 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART6"
+#endif
+
+#if STM32_UART_USE_UART7 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART7_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to UART7"
+#endif
+
+#endif /* !defined(STM32_USART3_8_HANDLER) */
+
+#if STM32_UART_USE_UART8 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART8_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to UART8"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) || \
+ !defined(STM32_UART_USART1_TX_DMA_STREAM))
+#error "USART1 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_STREAM) || \
+ !defined(STM32_UART_USART2_TX_DMA_STREAM))
+#error "USART2 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_STREAM) || \
+ !defined(STM32_UART_USART3_TX_DMA_STREAM))
+#error "USART3 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_STREAM) || \
+ !defined(STM32_UART_UART4_TX_DMA_STREAM))
+#error "UART4 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_STREAM) || \
+ !defined(STM32_UART_UART5_TX_DMA_STREAM))
+#error "UART5 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_STREAM) || \
+ !defined(STM32_UART_USART6_TX_DMA_STREAM))
+#error "USART6 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_UART7 && (!defined(STM32_UART_UART7_RX_DMA_STREAM) || \
+ !defined(STM32_UART_UART7_TX_DMA_STREAM))
+#error "UART7 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_UART8 && (!defined(STM32_UART_UART8_RX_DMA_STREAM) || \
+ !defined(STM32_UART_UART8_TX_DMA_STREAM))
+#error "UART8 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_UART_USE_USART1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
+ STM32_USART1_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART1 RX"
+#endif
+
+#if STM32_UART_USE_USART1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \
+ STM32_USART1_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART1 TX"
+#endif
+
+#if STM32_UART_USE_USART2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \
+ STM32_USART2_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART2 RX"
+#endif
+
+#if STM32_UART_USE_USART2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \
+ STM32_USART2_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART2 TX"
+#endif
+
+#if STM32_UART_USE_USART3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \
+ STM32_USART3_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART3 RX"
+#endif
+
+#if STM32_UART_USE_USART3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \
+ STM32_USART3_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART3 TX"
+#endif
+
+#if STM32_UART_USE_UART4 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM, \
+ STM32_UART4_RX_DMA_MSK)
+#error "invalid DMA stream associated to UART4 RX"
+#endif
+
+#if STM32_UART_USE_UART4 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM, \
+ STM32_UART4_TX_DMA_MSK)
+#error "invalid DMA stream associated to UART4 TX"
+#endif
+
+#if STM32_UART_USE_UART5 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM, \
+ STM32_UART5_RX_DMA_MSK)
+#error "invalid DMA stream associated to UART5 RX"
+#endif
+
+#if STM32_UART_USE_UART5 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM, \
+ STM32_UART5_TX_DMA_MSK)
+#error "invalid DMA stream associated to UART5 TX"
+#endif
+
+#if STM32_UART_USE_USART6 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \
+ STM32_USART6_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART6 RX"
+#endif
+
+#if STM32_UART_USE_USART6 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM, \
+ STM32_USART6_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART6 TX"
+#endif
+
+#if STM32_UART_USE_UART7 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_UART7_RX_DMA_STREAM, \
+ STM32_UART7_RX_DMA_MSK)
+#error "invalid DMA stream associated to UART7 RX"
+#endif
+
+#if STM32_UART_USE_UART7 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_UART7_TX_DMA_STREAM, \
+ STM32_UART7_TX_DMA_MSK)
+#error "invalid DMA stream associated to UART7 TX"
+#endif
+
+#if STM32_UART_USE_UART8 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_UART8_RX_DMA_STREAM, \
+ STM32_UART8_RX_DMA_MSK)
+#error "invalid DMA stream associated to UART8 RX"
+#endif
+
+#if STM32_UART_USE_UART8 && \
+ !STM32_DMA_IS_VALID_ID(STM32_UART_UART8_TX_DMA_STREAM, \
+ STM32_UART8_TX_DMA_MSK)
+#error "invalid DMA stream associated to UART8 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief UART driver condition flags type.
+ */
+typedef uint32_t uartflags_t;
+
+/**
+ * @brief Structure representing an UART driver.
+ */
+typedef struct UARTDriver UARTDriver;
+
+/**
+ * @brief Generic UART notification callback type.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ */
+typedef void (*uartcb_t)(UARTDriver *uartp);
+
+/**
+ * @brief Character received UART notification callback type.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] c received character
+ */
+typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
+
+/**
+ * @brief Receive error UART notification callback type.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] e receive error mask
+ */
+typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief End of transmission buffer callback.
+ */
+ uartcb_t txend1_cb;
+ /**
+ * @brief Physical end of transmission callback.
+ */
+ uartcb_t txend2_cb;
+ /**
+ * @brief Receive buffer filled callback.
+ */
+ uartcb_t rxend_cb;
+ /**
+ * @brief Character received while out if the @p UART_RECEIVE state.
+ */
+ uartccb_t rxchar_cb;
+ /**
+ * @brief Receive error callback.
+ */
+ uartecb_t rxerr_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Receiver timeout callback.
+ * @details Handles both idle and timeout interrupts depending on configured
+ * flags in CR registers and supported hardware features.
+ */
+ uartcb_t timeout_cb;
+ /**
+ * @brief Receiver timeout value in terms of number of bit duration.
+ * @details Set it to 0 when you want to handle idle interrupt instead of
+ * hardware timeout.
+ */
+ uint32_t timeout;
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t speed;
+ /**
+ * @brief Initialization value for the CR1 register.
+ */
+ uint32_t cr1;
+ /**
+ * @brief Initialization value for the CR2 register.
+ */
+ uint32_t cr2;
+ /**
+ * @brief Initialization value for the CR3 register.
+ */
+ uint32_t cr3;
+} UARTConfig;
+
+/**
+ * @brief Structure representing an UART driver.
+ */
+struct UARTDriver {
+ /**
+ * @brief Driver state.
+ */
+ uartstate_t state;
+ /**
+ * @brief Transmitter state.
+ */
+ uarttxstate_t txstate;
+ /**
+ * @brief Receiver state.
+ */
+ uartrxstate_t rxstate;
+ /**
+ * @brief Current configuration data.
+ */
+ const UARTConfig *config;
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Synchronization flag for transmit operations.
+ */
+ bool early;
+ /**
+ * @brief Waiting thread on RX.
+ */
+ thread_reference_t threadrx;
+ /**
+ * @brief Waiting thread on TX.
+ */
+ thread_reference_t threadtx;
+#endif /* UART_USE_WAIT */
+#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* UART_USE_MUTUAL_EXCLUSION */
+#if defined(UART_DRIVER_EXT_FIELDS)
+ UART_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the USART registers block.
+ */
+ USART_TypeDef *usart;
+ /**
+ * @brief Clock frequency for the associated USART/UART.
+ */
+ uint32_t clock;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+ /**
+ * @brief Receive DMA channel.
+ */
+ const stm32_dma_stream_t *dmarx;
+ /**
+ * @brief Transmit DMA channel.
+ */
+ const stm32_dma_stream_t *dmatx;
+ /**
+ * @brief Default receive buffer while into @p UART_RX_IDLE state.
+ */
+ volatile uint16_t rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD1;
+#endif
+
+#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD2;
+#endif
+
+#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD3;
+#endif
+
+#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD4;
+#endif
+
+#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD5;
+#endif
+
+#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD6;
+#endif
+
+#if STM32_UART_USE_UART7 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD7;
+#endif
+
+#if STM32_UART_USE_UART8 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD8;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void uart_lld_init(void);
+ void uart_lld_start(UARTDriver *uartp);
+ void uart_lld_stop(UARTDriver *uartp);
+ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
+ size_t uart_lld_stop_send(UARTDriver *uartp);
+ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
+ size_t uart_lld_stop_receive(UARTDriver *uartp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_UART */
+
+#endif /* HAL_UART_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/driver.mk
new file mode 100644
index 0000000000..5d7811155f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/usb_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
similarity index 61%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/usb_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
index a3b4ea73f8..6789e5845e 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/usb_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
*/
/**
- * @file STM32/USBv1/usb_lld.c
+ * @file USBv1/hal_usb_lld.c
* @brief STM32 USB subsystem low level driver source.
*
* @addtogroup USB
@@ -24,7 +24,6 @@
#include
-#include "ch.h"
#include "hal.h"
#if HAL_USE_USB || defined(__DOXYGEN__)
@@ -35,6 +34,8 @@
#define BTABLE_ADDR 0x0000
+#define EPR_EP_TYPE_IS_ISO(bits) ((bits & EPR_EP_TYPE_MASK) == EPR_EP_TYPE_ISO)
+
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -106,158 +107,251 @@ static void usb_pm_reset(USBDriver *usbp) {
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] size size of the packet buffer to allocate
+ * @return The packet buffer address.
*/
static uint32_t usb_pm_alloc(USBDriver *usbp, size_t size) {
uint32_t next;
next = usbp->pmnext;
- usbp->pmnext += size;
- chDbgAssert(usbp->pmnext <= USB_PMA_SIZE, "usb_pm_alloc(), #1", "PMA overflow");
+ usbp->pmnext += (size + 1) & ~1;
+ osalDbgAssert(usbp->pmnext <= STM32_USB_PMA_SIZE, "PMA overflow");
return next;
}
/**
* @brief Reads from a dedicated packet buffer.
*
- * @param[in] udp pointer to a @p stm32_usb_descriptor_t
+ * @param[in] ep endpoint number
* @param[out] buf buffer where to copy the packet data
- * @param[in] n maximum number of bytes to copy. This value must
- * not exceed the maximum packet size for this endpoint.
+ * @return The size of the receivee packet.
*
* @notapi
*/
-static void usb_packet_read_to_buffer(stm32_usb_descriptor_t *udp,
- uint8_t *buf, size_t n) {
- uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0);
-
- n = (n + 1) / 2;
- while (n > 0) {
- /* Note, this line relies on the Cortex-M3/M4 ability to perform
- unaligned word accesses.*/
- *(uint16_t *)buf = (uint16_t)*pmap++;
- buf += 2;
- n--;
- }
-}
+static size_t usb_packet_read_to_buffer(usbep_t ep, uint8_t *buf) {
+ size_t i, n;
+ stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep);
+ stm32_usb_pma_t *pmap = USB_ADDR2PTR(udp->RXADDR0);
+#if STM32_USB_USE_ISOCHRONOUS
+ uint32_t epr = STM32_USB->EPR[ep];
+
+ /* Double buffering is always enabled for isochronous endpoints, and
+ although we overlap the two buffers for simplicity, we still need
+ to read from the right counter. The DTOG_RX bit indicates the buffer
+ that is currently in use by the USB peripheral, that is, the buffer
+ in which the next received packet will be stored, so we need to
+ read the counter of the OTHER buffer, which is where the last
+ received packet was stored.*/
+ if (EPR_EP_TYPE_IS_ISO(epr) && !(epr & EPR_DTOG_RX))
+ n = (size_t)udp->RXCOUNT1 & RXCOUNT_COUNT_MASK;
+ else
+ n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK;
+#else
+ n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK;
+#endif
-/**
- * @brief Reads from a dedicated packet buffer.
- *
- * @param[in] udp pointer to a @p stm32_usb_descriptor_t
- * @param[in] iqp pointer to an @p InputQueue object
- * @param[in] n maximum number of bytes to copy. This value must
- * not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_read_to_queue(stm32_usb_descriptor_t *udp,
- InputQueue *iqp, size_t n) {
- size_t nhw;
- uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0);
+ i = n;
- nhw = n / 2;
- while (nhw > 0) {
+#if STM32_USB_USE_FAST_COPY
+ while (i >= 16) {
uint32_t w;
- w = *pmap++;
- *iqp->q_wrptr++ = (uint8_t)w;
- if (iqp->q_wrptr >= iqp->q_top)
- iqp->q_wrptr = iqp->q_buffer;
- *iqp->q_wrptr++ = (uint8_t)(w >> 8);
- if (iqp->q_wrptr >= iqp->q_top)
- iqp->q_wrptr = iqp->q_buffer;
- nhw--;
+ w = *(pmap + 0);
+ *(buf + 0) = (uint8_t)w;
+ *(buf + 1) = (uint8_t)(w >> 8);
+ w = *(pmap + 1);
+ *(buf + 2) = (uint8_t)w;
+ *(buf + 3) = (uint8_t)(w >> 8);
+ w = *(pmap + 2);
+ *(buf + 4) = (uint8_t)w;
+ *(buf + 5) = (uint8_t)(w >> 8);
+ w = *(pmap + 3);
+ *(buf + 6) = (uint8_t)w;
+ *(buf + 7) = (uint8_t)(w >> 8);
+ w = *(pmap + 4);
+ *(buf + 8) = (uint8_t)w;
+ *(buf + 9) = (uint8_t)(w >> 8);
+ w = *(pmap + 5);
+ *(buf + 10) = (uint8_t)w;
+ *(buf + 11) = (uint8_t)(w >> 8);
+ w = *(pmap + 6);
+ *(buf + 12) = (uint8_t)w;
+ *(buf + 13) = (uint8_t)(w >> 8);
+ w = *(pmap + 7);
+ *(buf + 14) = (uint8_t)w;
+ *(buf + 15) = (uint8_t)(w >> 8);
+
+ i -= 16;
+ buf += 16;
+ pmap += 8;
}
- /* Last byte for odd numbers.*/
- if ((n & 1) != 0) {
- *iqp->q_wrptr++ = (uint8_t)*pmap;
- if (iqp->q_wrptr >= iqp->q_top)
- iqp->q_wrptr = iqp->q_buffer;
+#endif /* STM32_USB_USE_FAST_COPY */
+
+ while (i >= 2) {
+ uint32_t w = *pmap++;
+ *buf++ = (uint8_t)w;
+ *buf++ = (uint8_t)(w >> 8);
+ i -= 2;
}
- /* Updating queue.*/
- chSysLockFromIsr();
- iqp->q_counter += n;
- while (notempty(&iqp->q_waiting))
- chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
- chSysUnlockFromIsr();
+ if (i >= 1) {
+ *buf = (uint8_t)*pmap;
+ }
+
+ return n;
}
/**
* @brief Writes to a dedicated packet buffer.
*
- * @param[in] udp pointer to a @p stm32_usb_descriptor_t
+ * @param[in] ep endpoint number
* @param[in] buf buffer where to fetch the packet data
* @param[in] n maximum number of bytes to copy. This value must
* not exceed the maximum packet size for this endpoint.
*
* @notapi
*/
-static void usb_packet_write_from_buffer(stm32_usb_descriptor_t *udp,
+static void usb_packet_write_from_buffer(usbep_t ep,
const uint8_t *buf,
size_t n) {
- uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0);
-
- udp->TXCOUNT0 = (uint16_t)n;
- n = (n + 1) / 2;
- while (n > 0) {
- /* Note, this line relies on the Cortex-M3/M4 ability to perform
- unaligned word accesses.*/
- *pmap++ = *(uint16_t *)buf;
- buf += 2;
- n--;
+ stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep);
+ stm32_usb_pma_t *pmap = USB_ADDR2PTR(udp->TXADDR0);
+ int i = (int)n;
+
+#if STM32_USB_USE_ISOCHRONOUS
+ uint32_t epr = STM32_USB->EPR[ep];
+
+ /* Double buffering is always enabled for isochronous endpoints, and
+ although we overlap the two buffers for simplicity, we still need
+ to write to the right counter. The DTOG_TX bit indicates the buffer
+ that is currently in use by the USB peripheral, that is, the buffer
+ from which the next packet will be sent, so we need to write the
+ counter of that buffer.*/
+ if (EPR_EP_TYPE_IS_ISO(epr) && (epr & EPR_DTOG_TX))
+ udp->TXCOUNT1 = (stm32_usb_pma_t)n;
+ else
+ udp->TXCOUNT0 = (stm32_usb_pma_t)n;
+#else
+ udp->TXCOUNT0 = (stm32_usb_pma_t)n;
+#endif
+
+#if STM32_USB_USE_FAST_COPY
+ while (i >= 16) {
+ uint32_t w;
+
+ w = *(buf + 0);
+ w |= *(buf + 1) << 8;
+ *(pmap + 0) = (stm32_usb_pma_t)w;
+ w = *(buf + 2);
+ w |= *(buf + 3) << 8;
+ *(pmap + 1) = (stm32_usb_pma_t)w;
+ w = *(buf + 4);
+ w |= *(buf + 5) << 8;
+ *(pmap + 2) = (stm32_usb_pma_t)w;
+ w = *(buf + 6);
+ w |= *(buf + 7) << 8;
+ *(pmap + 3) = (stm32_usb_pma_t)w;
+ w = *(buf + 8);
+ w |= *(buf + 9) << 8;
+ *(pmap + 4) = (stm32_usb_pma_t)w;
+ w = *(buf + 10);
+ w |= *(buf + 11) << 8;
+ *(pmap + 5) = (stm32_usb_pma_t)w;
+ w = *(buf + 12);
+ w |= *(buf + 13) << 8;
+ *(pmap + 6) = (stm32_usb_pma_t)w;
+ w = *(buf + 14);
+ w |= *(buf + 15) << 8;
+ *(pmap + 7) = (stm32_usb_pma_t)w;
+
+ i -= 16;
+ buf += 16;
+ pmap += 8;
+ }
+#endif /* STM32_USB_USE_FAST_COPY */
+
+ while (i > 0) {
+ uint32_t w;
+
+ w = *buf++;
+ w |= *buf++ << 8;
+ *pmap++ = (stm32_usb_pma_t)w;
+ i -= 2;
}
}
/**
- * @brief Writes to a dedicated packet buffer.
+ * @brief Common ISR code, serves the EP-related interrupts.
*
- * @param[in] udp pointer to a @p stm32_usb_descriptor_t
- * @param[in] buf buffer where to fetch the packet data
- * @param[in] n maximum number of bytes to copy. This value must
- * not exceed the maximum packet size for this endpoint.
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
*
* @notapi
*/
-static void usb_packet_write_from_queue(stm32_usb_descriptor_t *udp,
- OutputQueue *oqp, size_t n) {
- size_t nhw;
- uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0);
-
- udp->TXCOUNT0 = (uint16_t)n;
- nhw = n / 2;
- while (nhw > 0) {
- uint32_t w;
+static void usb_serve_endpoints(USBDriver *usbp, uint32_t ep) {
+ size_t n;
+ uint32_t epr = STM32_USB->EPR[ep];
+ const USBEndpointConfig *epcp = usbp->epc[ep];
- w = (uint32_t)*oqp->q_rdptr++;
- if (oqp->q_rdptr >= oqp->q_top)
- oqp->q_rdptr = oqp->q_buffer;
- w |= (uint32_t)*oqp->q_rdptr++ << 8;
- if (oqp->q_rdptr >= oqp->q_top)
- oqp->q_rdptr = oqp->q_buffer;
- *pmap++ = w;
- nhw--;
- }
+ if (epr & EPR_CTR_TX) {
+ /* IN endpoint, transmission.*/
+ USBInEndpointState *isp = epcp->in_state;
- /* Last byte for odd numbers.*/
- if ((n & 1) != 0) {
- *pmap = (uint32_t)*oqp->q_rdptr++;
- if (oqp->q_rdptr >= oqp->q_top)
- oqp->q_rdptr = oqp->q_buffer;
- }
+ EPR_CLEAR_CTR_TX(ep);
- /* Updating queue. Note, the lock is done in this unusual way because this
- function can be called from both ISR and thread context so the kind
- of lock function to be invoked cannot be decided beforehand.*/
- port_lock();
- dbg_enter_lock();
+ isp->txcnt += isp->txlast;
+ n = isp->txsize - isp->txcnt;
+ if (n > 0) {
+ /* Transfer not completed, there are more packets to send.*/
+ if (n > epcp->in_maxsize)
+ n = epcp->in_maxsize;
- oqp->q_counter += n;
- while (notempty(&oqp->q_waiting))
- chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
+ /* Writes the packet from the defined buffer.*/
+ isp->txbuf += isp->txlast;
+ isp->txlast = n;
+ usb_packet_write_from_buffer(ep, isp->txbuf, n);
- dbg_leave_lock();
- port_unlock();
+ /* Starting IN operation.*/
+ EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID);
+ }
+ else {
+ /* Transfer completed, invokes the callback.*/
+ _usb_isr_invoke_in_cb(usbp, ep);
+ }
+ }
+ if (epr & EPR_CTR_RX) {
+ /* OUT endpoint, receive.*/
+
+ EPR_CLEAR_CTR_RX(ep);
+
+ if (epr & EPR_SETUP) {
+ /* Setup packets handling, setup packets are handled using a
+ specific callback.*/
+ _usb_isr_invoke_setup_cb(usbp, ep);
+ }
+ else {
+ USBOutEndpointState *osp = epcp->out_state;
+
+ /* Reads the packet into the defined buffer.*/
+ n = usb_packet_read_to_buffer(ep, osp->rxbuf);
+ osp->rxbuf += n;
+
+ /* Transaction data updated.*/
+ osp->rxcnt += n;
+ osp->rxsize -= n;
+ osp->rxpkts -= 1;
+
+ /* The transaction is completed if the specified number of packets
+ has been received or the current packet is a short packet.*/
+ if ((n < epcp->out_maxsize) || (osp->rxpkts == 0)) {
+ /* Transfer complete, invokes the callback.*/
+ _usb_isr_invoke_out_cb(usbp, ep);
+ }
+ else {
+ /* Transfer not complete, there are more packets to receive.*/
+ EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID);
+ }
+ }
+ }
}
/*===========================================================================*/
@@ -265,52 +359,60 @@ static void usb_packet_write_from_queue(stm32_usb_descriptor_t *udp,
/*===========================================================================*/
#if STM32_USB_USE_USB1 || defined(__DOXYGEN__)
-#if !defined(STM32_USB1_HP_HANDLER)
-#error "STM32_USB1_HP_HANDLER not defined"
-#endif
+#if STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER
+#if STM32_USB_USE_ISOCHRONOUS
/**
* @brief USB high priority interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USB1_HP_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USB1_HP_HANDLER) {
+ uint32_t istr;
+ USBDriver *usbp = &USBD1;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- CH_IRQ_EPILOGUE();
+ /* Endpoint events handling.*/
+ istr = STM32_USB->ISTR;
+ while (istr & ISTR_CTR) {
+ usb_serve_endpoints(usbp, istr & ISTR_EP_ID_MASK);
+ istr = STM32_USB->ISTR;
+ }
+
+ OSAL_IRQ_EPILOGUE();
}
+#endif /* STM32_USB_USE_ISOCHRONOUS */
+#endif /* STM32_USB1_LP_NUMBER != STM32_USB1_HP_NUMBER */
-#if !defined(STM32_USB1_LP_HANDLER)
-#error "STM32_USB1_LP_HANDLER not defined"
-#endif
/**
* @brief USB low priority interrupt handler.
*
* @isr
*/
-CH_IRQ_HANDLER(STM32_USB1_LP_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USB1_LP_HANDLER) {
uint32_t istr;
USBDriver *usbp = &USBD1;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
istr = STM32_USB->ISTR;
/* USB bus reset condition handling.*/
if (istr & ISTR_RESET) {
- _usb_reset(usbp);
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
STM32_USB->ISTR = ~ISTR_RESET;
+
+ _usb_reset(usbp);
}
/* USB bus SUSPEND condition handling.*/
if (istr & ISTR_SUSP) {
STM32_USB->CNTR |= CNTR_FSUSP;
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND);
#if STM32_USB_LOW_POWER_ON_SUSPEND
STM32_USB->CNTR |= CNTR_LP_MODE;
#endif
STM32_USB->ISTR = ~ISTR_SUSP;
+
+ _usb_suspend(usbp);
}
/* USB bus WAKEUP condition handling.*/
@@ -318,7 +420,8 @@ CH_IRQ_HANDLER(STM32_USB1_LP_HANDLER) {
uint32_t fnr = STM32_USB->FNR;
if (!(fnr & FNR_RXDP)) {
STM32_USB->CNTR &= ~CNTR_FSUSP;
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP);
+
+ _usb_wakeup(usbp);
}
#if STM32_USB_LOW_POWER_ON_SUSPEND
else {
@@ -338,89 +441,13 @@ CH_IRQ_HANDLER(STM32_USB1_LP_HANDLER) {
/* Endpoint events handling.*/
while (istr & ISTR_CTR) {
- size_t n;
- uint32_t ep;
- uint32_t epr = STM32_USB->EPR[ep = istr & ISTR_EP_ID_MASK];
- const USBEndpointConfig *epcp = usbp->epc[ep];
-
- if (epr & EPR_CTR_TX) {
- size_t transmitted;
- /* IN endpoint, transmission.*/
- EPR_CLEAR_CTR_TX(ep);
-
- transmitted = (size_t)USB_GET_DESCRIPTOR(ep)->TXCOUNT0;
- epcp->in_state->txcnt += transmitted;
- n = epcp->in_state->txsize - epcp->in_state->txcnt;
- if (n > 0) {
- /* Transfer not completed, there are more packets to send.*/
- if (n > epcp->in_maxsize)
- n = epcp->in_maxsize;
-
- if (epcp->in_state->txqueued)
- usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep),
- epcp->in_state->mode.queue.txqueue,
- n);
- else {
- epcp->in_state->mode.linear.txbuf += transmitted;
- usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep),
- epcp->in_state->mode.linear.txbuf,
- n);
- }
- chSysLockFromIsr();
- usb_lld_start_in(usbp, ep);
- chSysUnlockFromIsr();
- }
- else {
- /* Transfer completed, invokes the callback.*/
- _usb_isr_invoke_in_cb(usbp, ep);
- }
- }
- if (epr & EPR_CTR_RX) {
- EPR_CLEAR_CTR_RX(ep);
- /* OUT endpoint, receive.*/
- if (epr & EPR_SETUP) {
- /* Setup packets handling, setup packets are handled using a
- specific callback.*/
- _usb_isr_invoke_setup_cb(usbp, ep);
- }
- else {
- stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep);
- n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK;
-
- /* Reads the packet into the defined buffer.*/
- if (epcp->out_state->rxqueued)
- usb_packet_read_to_queue(udp,
- epcp->out_state->mode.queue.rxqueue,
- n);
- else {
- usb_packet_read_to_buffer(udp,
- epcp->out_state->mode.linear.rxbuf,
- n);
- epcp->out_state->mode.linear.rxbuf += n;
- }
- /* Transaction data updated.*/
- epcp->out_state->rxcnt += n;
- epcp->out_state->rxsize -= n;
- epcp->out_state->rxpkts -= 1;
-
- /* The transaction is completed if the specified number of packets
- has been received or the current packet is a short packet.*/
- if ((n < epcp->out_maxsize) || (epcp->out_state->rxpkts == 0)) {
- /* Transfer complete, invokes the callback.*/
- _usb_isr_invoke_out_cb(usbp, ep);
- }
- else {
- /* Transfer not complete, there are more packets to receive.*/
- EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID);
- }
- }
- }
+ usb_serve_endpoints(usbp, istr & ISTR_EP_ID_MASK);
istr = STM32_USB->ISTR;
}
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
-#endif
+#endif /* STM32_USB_USE_USB1 */
/*===========================================================================*/
/* Driver exported functions. */
@@ -456,18 +483,17 @@ void usb_lld_start(USBDriver *usbp) {
STM32_USB->CNTR = CNTR_FRES;
/* Enabling the USB IRQ vectors, this also gives enough time to allow
the transceiver power up (1uS).*/
- nvicEnableVector(STM32_USB1_HP_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_USB_USB1_HP_IRQ_PRIORITY));
- nvicEnableVector(STM32_USB1_LP_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_USB_USB1_LP_IRQ_PRIORITY));
+#if STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER
+ nvicEnableVector(STM32_USB1_HP_NUMBER, STM32_USB_USB1_HP_IRQ_PRIORITY);
+#endif
+ nvicEnableVector(STM32_USB1_LP_NUMBER, STM32_USB_USB1_LP_IRQ_PRIORITY);
/* Releases the USB reset.*/
STM32_USB->CNTR = 0;
}
#endif
/* Reset procedure enforced on driver start.*/
- _usb_reset(usbp);
+ usb_lld_reset(usbp);
}
- /* Configuration.*/
}
/**
@@ -483,7 +509,9 @@ void usb_lld_stop(USBDriver *usbp) {
if (usbp->state == USB_STOP) {
#if STM32_USB_USE_USB1
if (&USBD1 == usbp) {
+#if STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER
nvicDisableVector(STM32_USB1_HP_NUMBER);
+#endif
nvicDisableVector(STM32_USB1_LP_NUMBER);
STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES;
rccDisableUSB(FALSE);
@@ -503,7 +531,7 @@ void usb_lld_reset(USBDriver *usbp) {
uint32_t cntr;
/* Post reset initialization.*/
- STM32_USB->BTABLE = 0;
+ STM32_USB->BTABLE = BTABLE_ADDR;
STM32_USB->ISTR = 0;
STM32_USB->DADDR = DADDR_EF;
cntr = /*CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM |
@@ -543,15 +571,23 @@ void usb_lld_set_address(USBDriver *usbp) {
* @notapi
*/
void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
- uint16_t nblocks, epr;
+ uint16_t epr;
stm32_usb_descriptor_t *dp;
const USBEndpointConfig *epcp = usbp->epc[ep];
- /* Setting the endpoint type.*/
+ /* Setting the endpoint type. Note that isochronous endpoints cannot be
+ bidirectional because it uses double buffering and both transmit and
+ receive descriptor fields are used for either direction.*/
switch (epcp->ep_mode & USB_EP_MODE_TYPE) {
case USB_EP_MODE_TYPE_ISOC:
+#if STM32_USB_USE_ISOCHRONOUS
+ osalDbgAssert((epcp->in_state == NULL) || (epcp->out_state == NULL),
+ "isochronous EP cannot be IN and OUT");
epr = EPR_EP_TYPE_ISO;
break;
+#else
+ osalDbgAssert(false, "isochronous support disabled");
+#endif
case USB_EP_MODE_TYPE_BULK:
epr = EPR_EP_TYPE_BULK;
break;
@@ -562,29 +598,57 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
epr = EPR_EP_TYPE_CONTROL;
}
- /* IN endpoint initially in NAK mode.*/
- if (epcp->in_cb != NULL)
+ dp = USB_GET_DESCRIPTOR(ep);
+
+ /* IN endpoint handling.*/
+ if (epcp->in_state != NULL) {
+ dp->TXCOUNT0 = 0;
+ dp->TXADDR0 = usb_pm_alloc(usbp, epcp->in_maxsize);
+
+#if STM32_USB_USE_ISOCHRONOUS
+ if (epr == EPR_EP_TYPE_ISO) {
+ epr |= EPR_STAT_TX_VALID;
+ dp->TXCOUNT1 = dp->TXCOUNT0;
+ dp->TXADDR1 = dp->TXADDR0; /* Both buffers overlapped.*/
+ }
+ else {
+ epr |= EPR_STAT_TX_NAK;
+ }
+#else
epr |= EPR_STAT_TX_NAK;
+#endif
+ }
- /* OUT endpoint initially in NAK mode.*/
- if (epcp->out_cb != NULL)
+ /* OUT endpoint handling.*/
+ if (epcp->out_state != NULL) {
+ uint16_t nblocks;
+
+ /* Endpoint size and address initialization.*/
+ if (epcp->out_maxsize > 62)
+ nblocks = (((((epcp->out_maxsize - 1) | 0x1f) + 1) / 32) << 10) |
+ 0x8000;
+ else
+ nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10;
+ dp->RXCOUNT0 = nblocks;
+ dp->RXADDR0 = usb_pm_alloc(usbp, epcp->out_maxsize);
+
+#if STM32_USB_USE_ISOCHRONOUS
+ if (epr == EPR_EP_TYPE_ISO) {
+ epr |= EPR_STAT_RX_VALID;
+ dp->RXCOUNT1 = dp->RXCOUNT0;
+ dp->RXADDR1 = dp->RXADDR0; /* Both buffers overlapped.*/
+ }
+ else {
+ epr |= EPR_STAT_RX_NAK;
+ }
+#else
epr |= EPR_STAT_RX_NAK;
+#endif
+ }
/* EPxR register setup.*/
EPR_SET(ep, epr | ep);
EPR_TOGGLE(ep, epr);
-
- /* Endpoint size and address initialization.*/
- if (epcp->out_maxsize > 62)
- nblocks = (((((epcp->out_maxsize - 1) | 0x1f) + 1) / 32) << 10) |
- 0x8000;
- else
- nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10;
- dp = USB_GET_DESCRIPTOR(ep);
- dp->TXCOUNT0 = 0;
- dp->RXCOUNT0 = nblocks;
- dp->TXADDR0 = usb_pm_alloc(usbp, epcp->in_maxsize);
- dp->RXADDR0 = usb_pm_alloc(usbp, epcp->out_maxsize);
}
/**
@@ -672,7 +736,7 @@ usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
* @notapi
*/
void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
- uint32_t *pmap;
+ stm32_usb_pma_t *pmap;
stm32_usb_descriptor_t *udp;
uint32_t n;
@@ -686,14 +750,14 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
}
/**
- * @brief Prepares for a receive operation.
+ * @brief Starts a receive operation on an OUT endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
-void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
+void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
USBOutEndpointState *osp = usbp->epc[ep]->out_state;
/* Transfer initialization.*/
@@ -702,17 +766,19 @@ void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
else
osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
usbp->epc[ep]->out_maxsize);
+
+ EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID);
}
/**
- * @brief Prepares for a transmit operation.
+ * @brief Starts a transmit operation on an IN endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
-void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
+void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
size_t n;
USBInEndpointState *isp = usbp->epc[ep]->in_state;
@@ -721,40 +787,8 @@ void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
if (n > (size_t)usbp->epc[ep]->in_maxsize)
n = (size_t)usbp->epc[ep]->in_maxsize;
- if (isp->txqueued)
- usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep),
- isp->mode.queue.txqueue, n);
- else
- usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep),
- isp->mode.linear.txbuf, n);
-}
-
-/**
- * @brief Starts a receive operation on an OUT endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
-
- (void)usbp;
-
- EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID);
-}
-
-/**
- * @brief Starts a transmit operation on an IN endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
-
- (void)usbp;
+ isp->txlast = n;
+ usb_packet_write_from_buffer(ep, isp->txbuf, n);
EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID);
}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/usb_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.h
similarity index 75%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/usb_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.h
index aa1905380c..f477fbda0e 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/usb_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32/USBv1/usb_lld.h
+ * @file USBv1/hal_usb_lld.h
* @brief STM32 USB subsystem low level driver header.
*
* @addtogroup USB
* @{
*/
-#ifndef _USB_LLD_H_
-#define _USB_LLD_H_
+#ifndef HAL_USB_LLD_H
+#define HAL_USB_LLD_H
#if HAL_USE_USB || defined(__DOXYGEN__)
@@ -48,6 +48,11 @@
*/
#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS
+/**
+ * @brief Method for set address acknowledge.
+ */
+#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -71,7 +76,8 @@
/**
* @brief USB1 interrupt priority level setting.
*/
-#if !defined(STM32_USB_USB1_HP_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#if (!defined(STM32_USB_USB1_HP_IRQ_PRIORITY) && \
+ (STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER)) || defined(__DOXYGEN__)
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#endif
@@ -82,6 +88,30 @@
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
#endif
+/**
+ * @brief Enables isochronous support.
+ * @note Isochronous support requires special handling and this makes the
+ * code size increase significantly.
+ */
+#if !defined(STM32_USB_USE_ISOCHRONOUS) || defined(__DOXYGEN__)
+#define STM32_USB_USE_ISOCHRONOUS FALSE
+#endif
+
+/**
+ * @brief Use faster copy for packets.
+ * @note Makes the driver larger.
+ */
+#if !defined(STM32_USB_USE_FAST_COPY) || defined(__DOXYGEN__)
+#define STM32_USB_USE_FAST_COPY FALSE
+#endif
+
+/**
+ * @brief Host wake-up procedure duration.
+ */
+#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
+#define USB_HOST_WAKEUP_DURATION 2
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -94,13 +124,14 @@
#error "USB driver activated but no USB peripheral assigned"
#endif
-#if STM32_USB_USE_USB1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_HP_IRQ_PRIORITY)
+#if STM32_USB_USE_USB1 && \
+ (STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER) && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_USB1_HP_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USB HP"
#endif
-#if STM32_USB_USE_USB1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_LP_IRQ_PRIORITY)
+#if STM32_USB_USE_USB1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_USB1_LP_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USB LP"
#endif
@@ -108,6 +139,26 @@
#error "the USB driver requires a 48MHz clock"
#endif
+#if !defined(STM32_USB1_HP_HANDLER)
+#error "STM32_USB1_HP_HANDLER not defined"
+#endif
+
+#if !defined(STM32_USB1_HP_NUMBER)
+#error "STM32_USB1_HP_NUMBER not defined"
+#endif
+
+#if !defined(STM32_USB1_LP_HANDLER)
+#error "STM32_USB1_LP_HANDLER not defined"
+#endif
+
+#if !defined(STM32_USB1_LP_NUMBER)
+#error "STM32_USB1_LP_NUMBER not defined"
+#endif
+
+#if (USB_HOST_WAKEUP_DURATION < 2) || (USB_HOST_WAKEUP_DURATION > 15)
+#error "invalid USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -116,10 +167,6 @@
* @brief Type of an IN endpoint state structure.
*/
typedef struct {
- /**
- * @brief Buffer mode, queue or linear.
- */
- bool_t txqueued;
/**
* @brief Requested transmit transfer size.
*/
@@ -128,31 +175,27 @@ typedef struct {
* @brief Transmitted bytes so far.
*/
size_t txcnt;
- union {
- struct {
- /**
- * @brief Pointer to the transmission linear buffer.
- */
- const uint8_t *txbuf;
- } linear;
- struct {
- /**
- * @brief Pointer to the output queue.
- */
- OutputQueue *txqueue;
- } queue;
- /* End of the mandatory fields.*/
- } mode;
+ /**
+ * @brief Pointer to the transmission linear buffer.
+ */
+ const uint8_t *txbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Size of the last transmitted packet.
+ */
+ size_t txlast;
} USBInEndpointState;
/**
* @brief Type of an OUT endpoint state structure.
*/
typedef struct {
- /**
- * @brief Buffer mode, queue or linear.
- */
- bool_t rxqueued;
/**
* @brief Requested receive transfer size.
*/
@@ -161,20 +204,16 @@ typedef struct {
* @brief Received bytes so far.
*/
size_t rxcnt;
- union {
- struct {
- /**
- * @brief Pointer to the receive linear buffer.
- */
- uint8_t *rxbuf;
- } linear;
- struct {
- /**
- * @brief Pointer to the input queue.
- */
- InputQueue *rxqueue;
- } queue;
- } mode;
+ /**
+ * @brief Pointer to the receive linear buffer.
+ */
+ uint8_t *rxbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
/* End of the mandatory fields.*/
/**
* @brief Number of packets to receive.
@@ -204,36 +243,34 @@ typedef struct {
usbepcallback_t setup_cb;
/**
* @brief IN endpoint notification callback.
- * @details This field must be set to @p NULL if the IN endpoint is not
- * used.
+ * @details This field must be set to @p NULL if callback is not required.
*/
usbepcallback_t in_cb;
/**
* @brief OUT endpoint notification callback.
- * @details This field must be set to @p NULL if the OUT endpoint is not
- * used.
+ * @details This field must be set to @p NULL if callback is not required.
*/
usbepcallback_t out_cb;
/**
* @brief IN endpoint maximum packet size.
- * @details This field must be set to zero if the IN endpoint is not
- * used.
+ * @details This field must be set to zero if the IN endpoint is not used.
*/
uint16_t in_maxsize;
/**
* @brief OUT endpoint maximum packet size.
- * @details This field must be set to zero if the OUT endpoint is not
- * used.
+ * @details This field must be set to zero if the OUT endpoint is not used.
*/
uint16_t out_maxsize;
/**
* @brief @p USBEndpointState associated to the IN endpoint.
- * @details This structure maintains the state of the IN endpoint.
+ * @details This field must be set to @p NULL if the IN endpoint is not
+ * used.
*/
USBInEndpointState *in_state;
/**
* @brief @p USBEndpointState associated to the OUT endpoint.
- * @details This structure maintains the state of the OUT endpoint.
+ * @details This field must be set to @p NULL if the OUT endpoint is not
+ * used.
*/
USBOutEndpointState *out_state;
/* End of the mandatory fields.*/
@@ -347,6 +384,10 @@ struct USBDriver {
* @brief Current USB device configuration.
*/
uint8_t configuration;
+ /**
+ * @brief State of the driver when a suspend happened.
+ */
+ usbstate_t saved_state;
#if defined(USB_DRIVER_EXT_FIELDS)
USB_DRIVER_EXT_FIELDS
#endif
@@ -388,19 +429,47 @@ struct USBDriver {
#define usb_lld_get_transaction_size(usbp, ep) \
((usbp)->epc[ep]->out_state->rxcnt)
+#if STM32_USB_HAS_BCDR || defined(__DOXYGEN__)
/**
- * @brief Returns the exact size of a received packet.
- * @pre The OUT endpoint must have been configured in packet mode
- * in order to use this function.
+ * @brief Connects the USB device.
*
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @return Received data size.
+ * @notapi
+ */
+#if !defined(usb_lld_connect_bus)
+#define usb_lld_connect_bus(usbp) (STM32_USB->BCDR |= USB_BCDR_DPPU)
+#endif
+
+/**
+ * @brief Disconnect the USB device.
+ *
+ * @notapi
+ */
+#if !defined(usb_lld_disconnect_bus)
+#define usb_lld_disconnect_bus(usbp) (STM32_USB->BCDR &= ~USB_BCDR_DPPU)
+#endif
+#endif /* STM32_USB_HAS_BCDR */
+
+#if defined(STM32L1XX)
+#if !defined(usb_lld_connect_bus)
+#define usb_lld_connect_bus(usbp) (SYSCFG->PMC |= SYSCFG_PMC_USB_PU)
+#endif
+
+#if !defined(usb_lld_disconnect_bus)
+#define usb_lld_disconnect_bus(usbp) (SYSCFG->PMC &= ~SYSCFG_PMC_USB_PU)
+#endif
+#endif /* STM32L1XX */
+
+/**
+ * @brief Start of host wake-up procedure.
*
* @notapi
*/
-#define usb_lld_get_packet_size(usbp, ep) \
- ((size_t)USB_GET_DESCRIPTOR(ep)->RXCOUNT & RXCOUNT_COUNT_MASK)
+#define usb_lld_wakeup_host(usbp) \
+ do{ \
+ STM32_USB->CNTR |= USB_CNTR_RESUME; \
+ osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION); \
+ STM32_USB->CNTR &= ~USB_CNTR_RESUME; \
+ } while (false)
/*===========================================================================*/
/* External declarations. */
@@ -423,8 +492,6 @@ extern "C" {
usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
- void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
- void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
@@ -437,6 +504,6 @@ extern "C" {
#endif /* HAL_USE_USB */
-#endif /* _USB_LLD_H_ */
+#endif /* HAL_USB_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/stm32_usb.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
similarity index 72%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/stm32_usb.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
index a6715856b7..f92a2f1fc1 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/USBv1/stm32_usb.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
*/
/**
- * @file stm32_usb.h
+ * @file USBv1/stm32_usb.h
* @brief STM32 USB registers layout header.
* @note This file requires definitions from the ST STM32 header files
* stm32f10x.h or stm32l1xx.h.
@@ -24,8 +24,8 @@
* @{
*/
-#ifndef _STM32_USB_H_
-#define _STM32_USB_H_
+#ifndef STM32_USB_H
+#define STM32_USB_H
/**
* @brief Number of the available endpoints.
@@ -33,6 +33,15 @@
*/
#define USB_ENDOPOINTS_NUMBER 7
+/**
+ * @brief Width of USB packet memory accesses.
+ */
+#if STM32_USB_ACCESS_SCHEME_2x16
+typedef uint16_t stm32_usb_pma_t;
+#else
+typedef uint32_t stm32_usb_pma_t;
+#endif
+
/**
* @brief USB registers block.
*/
@@ -40,31 +49,41 @@ typedef struct {
/**
* @brief Endpoint registers.
*/
- volatile uint32_t EPR[USB_ENDOPOINTS_NUMBER + 1];
+ volatile uint32_t EPR[USB_ENDOPOINTS_NUMBER + 1];
/*
* @brief Reserved space.
*/
- volatile uint32_t _r20[8];
+ volatile uint32_t _r20[8];
/*
* @brief Control Register.
*/
- volatile uint32_t CNTR;
+ volatile uint32_t CNTR;
/*
* @brief Interrupt Status Register.
*/
- volatile uint32_t ISTR;
+ volatile uint32_t ISTR;
/*
* @brief Frame Number Register.
*/
- volatile uint32_t FNR;
+ volatile uint32_t FNR;
/*
* @brief Device Address Register.
*/
- volatile uint32_t DADDR;
+ volatile uint32_t DADDR;
/*
* @brief Buffer Table Address.
*/
- volatile uint32_t BTABLE;
+ volatile uint32_t BTABLE;
+ /*
+ * @brief LPM Control and Status Register.
+ */
+ volatile uint32_t LPMCSR;
+#if STM32_USB_HAS_BCDR
+ /*
+ * @brief Battery Charging Detector
+ */
+ volatile uint32_t BCDR;
+#endif
} stm32_usb_t;
/**
@@ -74,46 +93,48 @@ typedef struct {
/**
* @brief TX buffer offset register.
*/
- volatile uint32_t TXADDR0;
+ volatile stm32_usb_pma_t TXADDR0;
/**
* @brief TX counter register 0.
*/
- volatile uint16_t TXCOUNT0;
- /**
- * @brief TX counter register 1.
- */
- volatile uint16_t TXCOUNT1;
+ volatile stm32_usb_pma_t TXCOUNT0;
/**
* @brief RX buffer offset register.
*/
- volatile uint32_t RXADDR0;
+ volatile stm32_usb_pma_t RXADDR0;
/**
* @brief RX counter register 0.
*/
- volatile uint16_t RXCOUNT0;
- /**
- * @brief RX counter register 1.
- */
- volatile uint16_t RXCOUNT1;
+ volatile stm32_usb_pma_t RXCOUNT0;
} stm32_usb_descriptor_t;
/**
* @name Register aliases
* @{
*/
-#define RXADDR1 TXADDR0
-#define TXADDR1 RXADDR0
+#define RXCOUNT1 TXCOUNT0
+#define TXCOUNT1 RXCOUNT0
+#define RXADDR1 TXADDR0
+#define TXADDR1 RXADDR0
/** @} */
/**
* @brief USB registers block numeric address.
*/
+#if defined(USB_BASE) || defined(__DOXYGEN__)
+#define STM32_USB_BASE USB_BASE
+#else
#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00)
+#endif
/**
* @brief USB RAM numeric address.
*/
+#if defined(USB_PMAADDR) || defined(__DOXYGEN__)
+#define STM32_USBRAM_BASE USB_PMAADDR
+#else
#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000)
+#endif
/**
* @brief Pointer to the USB registers block.
@@ -123,12 +144,7 @@ typedef struct {
/**
* @brief Pointer to the USB RAM.
*/
-#define STM32_USBRAM ((uint32_t *)STM32_USBRAM_BASE)
-
-/**
- * @brief Size of the dedicated packet memory.
- */
-#define USB_PMA_SIZE 512
+#define STM32_USBRAM ((stm32_usb_pma_t *)STM32_USBRAM_BASE)
/**
* @brief Mask of all the toggling bits in the EPR register.
@@ -201,34 +217,39 @@ typedef struct {
#define RXCOUNT_COUNT_MASK 0x03FF
#define TXCOUNT_COUNT_MASK 0x03FF
+#define EPR_CTR_MASK (EPR_CTR_TX | EPR_CTR_RX)
+
#define EPR_SET(ep, epr) \
- STM32_USB->EPR[ep] = (epr) & ~EPR_TOGGLE_MASK
+ STM32_USB->EPR[ep] = ((epr) & ~EPR_TOGGLE_MASK) | EPR_CTR_MASK
#define EPR_TOGGLE(ep, epr) \
- STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] ^ ((epr) & EPR_TOGGLE_MASK))
+ STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] ^ ((epr) & EPR_TOGGLE_MASK)) \
+ | EPR_CTR_MASK
#define EPR_SET_STAT_RX(ep, epr) \
- STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & \
+ STM32_USB->EPR[ep] = ((STM32_USB->EPR[ep] & \
~(EPR_TOGGLE_MASK & ~EPR_STAT_RX_MASK)) ^ \
- (epr)
+ (epr)) | EPR_CTR_MASK
#define EPR_SET_STAT_TX(ep, epr) \
- STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & \
+ STM32_USB->EPR[ep] = ((STM32_USB->EPR[ep] & \
~(EPR_TOGGLE_MASK & ~EPR_STAT_TX_MASK)) ^ \
- (epr)
+ (epr)) | EPR_CTR_MASK
#define EPR_CLEAR_CTR_RX(ep) \
- STM32_USB->EPR[ep] &= ~EPR_CTR_RX & ~EPR_TOGGLE_MASK
+ STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & ~EPR_CTR_RX & ~EPR_TOGGLE_MASK)\
+ | EPR_CTR_TX
#define EPR_CLEAR_CTR_TX(ep) \
- STM32_USB->EPR[ep] &= ~EPR_CTR_TX & ~EPR_TOGGLE_MASK
+ STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & ~EPR_CTR_TX & ~EPR_TOGGLE_MASK)\
+ | EPR_CTR_RX
/**
* @brief Returns an endpoint descriptor pointer.
*/
#define USB_GET_DESCRIPTOR(ep) \
((stm32_usb_descriptor_t *)((uint32_t)STM32_USBRAM_BASE + \
- (uint32_t)STM32_USB->BTABLE * 2 + \
+ (uint32_t)STM32_USB->BTABLE + \
(uint32_t)(ep) * \
sizeof(stm32_usb_descriptor_t)))
@@ -236,8 +257,10 @@ typedef struct {
* @brief Converts from a PMA address to a physical address.
*/
#define USB_ADDR2PTR(addr) \
- ((uint32_t *)((addr) * 2 + STM32_USBRAM_BASE))
+ ((stm32_usb_pma_t *)((addr) * \
+ (sizeof(stm32_usb_pma_t) / 2) + \
+ STM32_USBRAM_BASE))
-#endif /* _STM32_USB_H_ */
+#endif /* STM32_USB_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/driver.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
new file mode 100644
index 0000000000..e6314fdff2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
new file mode 100644
index 0000000000..739aa3a01f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
@@ -0,0 +1,140 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file xWDGv1/hal_wdg_lld.c
+ * @brief WDG Driver subsystem low level driver source.
+ *
+ * @addtogroup WDG
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define KR_KEY_RELOAD 0xAAAAU
+#define KR_KEY_ENABLE 0xCCCCU
+#define KR_KEY_WRITE 0x5555U
+#define KR_KEY_PROTECT 0x0000U
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+#if STM32_WDG_USE_IWDG || defined(__DOXYGEN__)
+WDGDriver WDGD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level WDG driver initialization.
+ *
+ * @notapi
+ */
+void wdg_lld_init(void) {
+
+#if STM32_WDG_USE_IWDG
+ WDGD1.state = WDG_STOP;
+ WDGD1.wdg = IWDG;
+#endif
+}
+
+/**
+ * @brief Configures and activates the WDG peripheral.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @notapi
+ */
+void wdg_lld_start(WDGDriver *wdgp) {
+
+#if STM32_IWDG_IS_WINDOWED
+ /* Enable IWDG and unlock for write.*/
+ wdgp->wdg->KR = KR_KEY_ENABLE;
+ wdgp->wdg->KR = KR_KEY_WRITE;
+
+ /* Write configuration.*/
+ wdgp->wdg->PR = wdgp->config->pr;
+ wdgp->wdg->RLR = wdgp->config->rlr;
+ while (wdgp->wdg->SR != 0)
+ ;
+
+ /* This also triggers a refresh.*/
+ wdgp->wdg->WINR = wdgp->config->winr;
+#else
+ /* Unlock IWDG.*/
+ wdgp->wdg->KR = KR_KEY_WRITE;
+
+ /* Write configuration.*/
+ while (wdgp->wdg->SR != 0)
+ ;
+ wdgp->wdg->PR = wdgp->config->pr;
+ wdgp->wdg->RLR = wdgp->config->rlr;
+
+ /* Start operations.*/
+ wdgp->wdg->KR = KR_KEY_RELOAD;
+ wdgp->wdg->KR = KR_KEY_ENABLE;
+#endif
+}
+
+/**
+ * @brief Deactivates the WDG peripheral.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @api
+ */
+void wdg_lld_stop(WDGDriver *wdgp) {
+
+ osalDbgAssert(wdgp->state == WDG_STOP,
+ "IWDG cannot be stopped once activated");
+}
+
+/**
+ * @brief Reloads WDG's counter.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @notapi
+ */
+void wdg_lld_reset(WDGDriver * wdgp) {
+
+ wdgp->wdg->KR = KR_KEY_RELOAD;
+}
+
+#endif /* HAL_USE_WDG == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.h
new file mode 100644
index 0000000000..a5ff059ef5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.h
@@ -0,0 +1,183 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file xWDGv1/hal_wdg_lld.h
+ * @brief WDG Driver subsystem low level driver header.
+ *
+ * @addtogroup WDG
+ * @{
+ */
+
+#ifndef HAL_WDG_LLD_H
+#define HAL_WDG_LLD_H
+
+#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name RLR register definitions
+ * @{
+ */
+#define STM32_IWDG_RL_MASK (0x00000FFF << 0)
+#define STM32_IWDG_RL(n) ((n) << 0)
+/** @} */
+
+/**
+ * @name PR register definitions
+ * @{
+ */
+#define STM32_IWDG_PR_MASK (7 << 0)
+#define STM32_IWDG_PR_4 0U
+#define STM32_IWDG_PR_8 1U
+#define STM32_IWDG_PR_16 2U
+#define STM32_IWDG_PR_32 3U
+#define STM32_IWDG_PR_64 4U
+#define STM32_IWDG_PR_128 5U
+#define STM32_IWDG_PR_256 6U
+/** @} */
+
+/**
+ * @name WINR register definitions
+ * @{
+ */
+#define STM32_IWDG_WIN_MASK (0x00000FFF << 0)
+#define STM32_IWDG_WIN(n) ((n) << 0)
+#define STM32_IWDG_WIN_DISABLED STM32_IWDG_WIN(0x00000FFF)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief IWDG driver enable switch.
+ * @details If set to @p TRUE the support for IWDG is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_WDG_USE_IWDG) || defined(__DOXYGEN__)
+#define STM32_WDG_USE_IWDG FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_WDG_USE_IWDG && !STM32_HAS_IWDG
+#error "IWDG not present in the selected device"
+#endif
+
+#if !STM32_WDG_USE_IWDG
+#error "WDG driver activated but no xWDG peripheral assigned"
+#endif
+
+#if !defined(STM32_LSI_ENABLED)
+#error "STM32_LSI_ENABLED not defined"
+#endif
+
+#if (STM32_WDG_USE_IWDG == TRUE) && (STM32_LSI_ENABLED == FALSE)
+#error "IWDG requires LSI clock"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an WDG driver.
+ */
+typedef struct WDGDriver WDGDriver;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Configuration of the IWDG_PR register.
+ * @details See the STM32 reference manual for details.
+ */
+ uint32_t pr;
+ /**
+ * @brief Configuration of the IWDG_RLR register.
+ * @details See the STM32 reference manual for details.
+ */
+ uint32_t rlr;
+#if STM32_IWDG_IS_WINDOWED || defined(__DOXYGEN__)
+ /**
+ * @brief Configuration of the IWDG_WINR register.
+ * @details See the STM32 reference manual for details.
+ * @note This field is not present in F1, F2, F4, L1 sub-families.
+ */
+ uint32_t winr;
+#endif
+} WDGConfig;
+
+/**
+ * @brief Structure representing an WDG driver.
+ */
+struct WDGDriver {
+ /**
+ * @brief Driver state.
+ */
+ wdgstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const WDGConfig *config;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the IWDG registers block.
+ */
+ IWDG_TypeDef *wdg;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_WDG_USE_IWDG && !defined(__DOXYGEN__)
+extern WDGDriver WDGD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void wdg_lld_init(void);
+ void wdg_lld_start(WDGDriver *wdgp);
+ void wdg_lld_stop(WDGDriver *wdgp);
+ void wdg_lld_reset(WDGDriver *wdgp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_WDG == TRUE */
+
+#endif /* HAL_WDG_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_ext_lld_isr.c
new file mode 100644
index 0000000000..eb59738bf2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_ext_lld_isr.c
@@ -0,0 +1,262 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F0xx/hal_ext_lld_isr.c
+ * @brief STM32F0xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "hal_ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTI[0]...EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector54) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= ((1U << 0) | (1U << 1));
+ EXTI->PR = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[2]...EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= ((1U << 2) | (1U << 3));
+ EXTI->PR = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[4]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= ((1U << 4) | (1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9) | (1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
+ EXTI->PR = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+ if (pr & (1U << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1U << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1U << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1U << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1U << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+ if (pr & (1U << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1U << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1U << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1U << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1U << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1U << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32F030) || defined(__DOXYGEN__)
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 16);
+ EXTI->PR = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI171920_HANDLER)
+/**
+ * @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 17) | (1U << 19) | (1U << 20));
+ EXTI->PR = pr;
+ if (pr & (1U << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+ if (pr & (1U << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+#endif /* HAL_USE_EXT */
+
+#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__)
+#if !defined(STM32F030) || defined(__DOXYGEN__)
+#if !defined(STM32_DISABLE_EXTI2122_HANDLER)
+/**
+ * @brief EXTI[21],EXTI[22] interrupt handler (ADC, COMP).
+ * @note This handler is shared with the ADC so it is handled
+ * a bit differently.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+
+ OSAL_IRQ_PROLOGUE();
+
+#if HAL_USE_EXT
+ {
+ uint32_t pr;
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 21) | (1U << 22));
+ EXTI->PR = pr;
+ if (pr & (1U << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1U << 22))
+ EXTD1.config->channels[21].cb(&EXTD1, 22);
+ }
+#endif
+#if HAL_USE_ADC
+ adc_lld_serve_interrupt(&ADCD1);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+#endif /* !defined(STM32F030) */
+#endif /* HAL_USE_EXT || HAL_USE_ADC */
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(EXTI0_1_IRQn, STM32_EXT_EXTI0_1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_3_IRQn, STM32_EXT_EXTI2_3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_15_IRQn, STM32_EXT_EXTI4_15_IRQ_PRIORITY);
+#if !defined(STM32F030) && !defined(STM32F070)
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(ADC1_COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+#endif
+ nvicEnableVector(RTC_IRQn, STM32_EXT_EXTI17_20_IRQ_PRIORITY);
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(EXTI0_1_IRQn);
+ nvicDisableVector(EXTI2_3_IRQn);
+ nvicDisableVector(EXTI4_15_IRQn);
+#if !defined(STM32F030) && !defined(STM32F070)
+ nvicDisableVector(PVD_IRQn);
+ nvicDisableVector(ADC1_COMP_IRQn);
+#endif
+ nvicDisableVector(RTC_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_ext_lld_isr.h
new file mode 100644
index 0000000000..76c54609a7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_ext_lld_isr.h
@@ -0,0 +1,114 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F0xx/hal_ext_lld_isr.h
+ * @brief STM32F0xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0..1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI2..3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI4..15 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI16 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI17,19,20 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI21,22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_exti_irq_enable(void);
+ void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_lld.c
new file mode 100644
index 0000000000..dfc89a572d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_lld.c
@@ -0,0 +1,348 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F0xx/hal_lld.c
+ * @brief STM32F0xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define STM32_PLLXTPRE_OFFSET 17 /**< PLLXTPRE offset */
+#define STM32_PLLXTPRE_MASK 0x01 /**< PLLXTPRE mask */
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32f0xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ * @note WARNING! Changing clock source impossible without resetting
+ * of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+ /* Backup domain reset.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+ }
+
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->BDCR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->BDCR |= RCC_BDCR_RTCEN;
+ }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+#if defined(STM32_DMA1_CH23_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM2);
+
+ /* Check on channel 3.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH23_HANDLER) */
+
+#if defined(STM32_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM4);
+
+ /* Check on channel 5.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM5);
+
+#if STM32_DMA1_NUM_CHANNELS > 5
+ /* Check on channel 6.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM6);
+#endif
+
+#if STM32_DMA1_NUM_CHANNELS > 6
+ /* Check on channel 7.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM7);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH4567_HANDLER) */
+
+#if defined(STM32_DMA12_CH23_CH12_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3, DMA2 streams 1 and 1 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA12_CH23_CH12_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2 of DMA1.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM2);
+
+ /* Check on channel 3 of DMA1.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM3);
+
+ /* Check on channel 1 of DMA2.*/
+ dmaServeInterrupt(STM32_DMA2_STREAM1);
+
+ /* Check on channel 2 of DMA2.*/
+ dmaServeInterrupt(STM32_DMA2_STREAM2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA12_CH23_CH12_HANDLER) */
+
+#if defined(STM32_DMA12_CH4567_CH345_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7, DMA2 streams 3, 4 and 5 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA12_CH4567_CH345_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4 of DMA1.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM4);
+
+ /* Check on channel 5 of DMA1.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM5);
+
+ /* Check on channel 6 of DMA1.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM6);
+
+ /* Check on channel 7 of DMA1.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM7);
+
+ /* Check on channel 3 of DMA2.*/
+ dmaServeInterrupt(STM32_DMA2_STREAM3);
+
+ /* Check on channel 4 of DMA2.*/
+ dmaServeInterrupt(STM32_DMA2_STREAM4);
+
+ /* Check on channel 5 of DMA2.*/
+ dmaServeInterrupt(STM32_DMA2_STREAM5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA12_CH4567_CH345_HANDLER) */
+#endif /* defined(STM32_DMA_REQUIRED) */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Reset of all peripherals.*/
+ rccResetAHB(0xFFFFFFFF);
+ rccResetAPB1(0xFFFFFFFF);
+ rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
+
+ /* PWR clock enabled.*/
+ rccEnablePWRInterface(FALSE);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+ /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+ PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief STM32 clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+ /* HSI setup, it enforces the reset situation in order to handle possible
+ problems with JTAG probes and re-initializations.*/
+ RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
+ while (!(RCC->CR & RCC_CR_HSIRDY))
+ ; /* Wait until HSI is stable. */
+
+ /* HSI is selected as new source without touching the other fields in
+ CFGR. Clearing the register has to be postponed after HSI is the
+ new source.*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
+ RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ ; /* Wait until HSI is selected. */
+
+ /* Registers finally cleared to reset values.*/
+ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+ RCC->CFGR = 0; /* CFGR reset value. */
+
+#if STM32_HSE_ENABLED
+ /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+ /* No HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON;
+#endif
+ while (!(RCC->CR & RCC_CR_HSERDY))
+ ; /* Waits until HSE is stable. */
+#endif
+
+#if STM32_HSI14_ENABLED
+ /* HSI14 activation.*/
+ RCC->CR2 |= RCC_CR2_HSI14ON;
+ while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
+ ; /* Waits until HSI14 is stable. */
+#endif
+
+#if STM32_HSI48_ENABLED
+ /* HSI48 activation.*/
+ RCC->CR2 |= RCC_CR2_HSI48ON;
+ while (!(RCC->CR2 & RCC_CR2_HSI48RDY))
+ ; /* Waits until HSI48 is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Waits until LSI is stable. */
+#endif
+
+ /* Clock settings.*/
+ /* CFGR2 must be configured first since CFGR value could change CFGR2 */
+ RCC->CFGR2 = STM32_PREDIV;
+ RCC->CFGR = STM32_PLLNODIV | STM32_MCOPRE | STM32_MCOSEL | STM32_PLLMUL |
+ STM32_PLLSRC | STM32_PPRE | STM32_HPRE |
+ ((STM32_PREDIV & STM32_PLLXTPRE_MASK) << STM32_PLLXTPRE_OFFSET);
+#if STM32_CECSW == STM32_CECSW_OFF
+ RCC->CFGR3 = STM32_USBSW | STM32_I2C1SW | STM32_USART1SW;
+#else
+ RCC->CFGR3 = STM32_USBSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW;
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ; /* Waits until PLL is stable. */
+#endif
+
+ /* Flash setup and final clock selection. */
+ FLASH->ACR = STM32_FLASHBITS;
+
+ /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+ /* Switches clock source.*/
+ RCC->CFGR |= STM32_SW;
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ; /* Waits selection complete. */
+#endif
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+#endif /* !STM32_NO_INIT */
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_lld.h
new file mode 100644
index 0000000000..6027380ac1
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/hal_lld.h
@@ -0,0 +1,990 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F0xx/hal_lld.h
+ * @brief STM32F0xx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_LSEDRV.
+ * - STM32_LSE_BYPASS (optionally).
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6,
+ * STM32F070xB for Value Line devices.
+ * - STM32F031x6, STM32F051x8, STM32F071xB, STM32F091xC
+ * for Access Line devices.
+ * - STM32F042x6, STM32F072xB for USB Line devices.
+ * - STM32F038xx, STM32F048xx, STM32F058xx, STM32F078xx,
+ * STM32F098xx for Low Voltage Line devices.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+/*
+ * Registry definitions.
+ */
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification macros
+ * @{
+ */
+#if defined(STM32F030x6) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32F030x6 Entry Level Value Line devices"
+
+#elif defined(STM32F030x8)
+#define PLATFORM_NAME "STM32F030x8 Entry Level Value Line devices"
+
+#elif defined(STM32F030xC)
+#define PLATFORM_NAME "STM32F030xC Entry Level Value Line devices"
+
+#elif defined(STM32F070x6)
+#define PLATFORM_NAME "STM32F070x6 Entry Level Value Line devices"
+
+#elif defined(STM32F070xB)
+#define PLATFORM_NAME "STM32F070xB Entry Level Value Line devices"
+
+#elif defined(STM32F031x6)
+#define PLATFORM_NAME "STM32F031x6 Entry Level Access Line devices"
+
+#elif defined(STM32F051x8)
+#define PLATFORM_NAME "STM32F051x8 Entry Level Access Line devices"
+
+#elif defined(STM32F071xB)
+#define PLATFORM_NAME "STM32F071xB Entry Level Access Line devices"
+
+#elif defined(STM32F091xC)
+#define PLATFORM_NAME "STM32F091xC Entry Level Access Line devices"
+
+#elif defined(STM32F042x6)
+#define PLATFORM_NAME "STM32F042x6 Entry Level USB Line devices"
+
+#elif defined(STM32F072xB)
+#define PLATFORM_NAME "STM32F072xB Entry Level USB Line devices"
+
+#elif defined(STM32F038xx)
+#define PLATFORM_NAME "STM32F038xx Entry Level Low Voltage Line devices"
+
+#elif defined(STM32F048xx)
+#define PLATFORM_NAME "STM32F048xx Entry Level Low Voltage Line devices"
+
+#elif defined(STM32F058xx)
+#define PLATFORM_NAME "STM32F058xx Entry Level Low Voltage Line devices"
+
+#elif defined(STM32F078xx)
+#define PLATFORM_NAME "STM32F078xx Entry Level Low Voltage Line devices"
+
+#elif defined(STM32F098xx)
+#define PLATFORM_NAME "STM32F098xx Entry Level Low Voltage Line devices"
+
+#else
+#error "STM32F0xx device unsupported or not specified"
+#endif
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX 48000000
+
+/**
+ * @brief Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX 32000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN 1000000
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX 1000000
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN 32768
+
+/**
+ * @brief Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX 25000000
+
+/**
+ * @brief Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN 1000000
+
+/**
+ * @brief Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX 48000000
+
+/**
+ * @brief Minimum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN 16000000
+
+/**
+ * @brief Maximum APB clock frequency.
+ */
+#define STM32_PCLK_MAX 48000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK 8000000 /**< High speed internal clock. */
+#define STM32_HSI14CLK 14000000 /**< 14MHz speed internal clock.*/
+#define STM32_HSI48CLK 48000000 /**< 48MHz speed internal clock.*/
+#define STM32_LSICLK 40000 /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
+#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
+#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
+#define STM32_SW_HSI48 (3 << 0) /**< SYSCLK source is HSI48. */
+
+#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE_DIV1 (0 << 8) /**< HCLK divided by 1. */
+#define STM32_PPRE_DIV2 (4 << 8) /**< HCLK divided by 2. */
+#define STM32_PPRE_DIV4 (5 << 8) /**< HCLK divided by 4. */
+#define STM32_PPRE_DIV8 (6 << 8) /**< HCLK divided by 8. */
+#define STM32_PPRE_DIV16 (7 << 8) /**< HCLK divided by 16. */
+
+#define STM32_PLLSRC_HSI_DIV2 (0 << 15) /**< PLL clock source is HSI/2. */
+#define STM32_PLLSRC_HSI (1 << 15) /**< PLL clock source is HSI */
+#define STM32_PLLSRC_HSE (2 << 15) /**< PLL clock source is HSE. */
+#define STM32_PLLSRC_HSI48 (3 << 15) /**< PLL clock source is HSI48. */
+
+#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_HSI14 (1 << 24) /**< HSI14 clock on MCO pin. */
+#define STM32_MCOSEL_LSI (2 << 24) /**< LSI clock on MCO pin. */
+#define STM32_MCOSEL_LSE (3 << 24) /**< LSE clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
+#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
+#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
+
+#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
+#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
+#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
+#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
+#define STM32_MCOPRE_DIV32 (5 << 28) /**< MCO divided by 32. */
+#define STM32_MCOPRE_DIV64 (6 << 28) /**< MCO divided by 64. */
+#define STM32_MCOPRE_DIV128 (7 << 28) /**< MCO divided by 128. */
+
+#define STM32_PLLNODIV_MASK (1 << 31) /**< MCO PLL divider mask. */
+#define STM32_PLLNODIV_DIV2 (0 << 31) /**< MCO PLL is divided by two. */
+#define STM32_PLLNODIV_DIV1 (1 << 31) /**< MCO PLL is divided by one. */
+/** @} */
+
+/**
+ * @name RCC_CFGR2 register bits definitions
+ * @{
+ */
+#define STM32_PRE_DIV1 (0 << 0) /**< PLLSRC divided by 1. */
+#define STM32_PRE_DIV2 (1 << 0) /**< SYSCLK divided by 2. */
+#define STM32_PRE_DIV3 (2 << 0) /**< SYSCLK divided by 3. */
+#define STM32_PRE_DIV4 (3 << 0) /**< PLLSRC divided by 4. */
+#define STM32_PRE_DIV5 (4 << 0) /**< SYSCLK divided by 5. */
+#define STM32_PRE_DIV6 (5 << 0) /**< SYSCLK divided by 6. */
+#define STM32_PRE_DIV7 (6 << 0) /**< PLLSRC divided by 7. */
+#define STM32_PRE_DIV8 (7 << 0) /**< SYSCLK divided by 8. */
+#define STM32_PRE_DIV9 (8 << 0) /**< SYSCLK divided by 9. */
+#define STM32_PRE_DIV10 (9 << 0) /**< PLLSRC divided by 10. */
+#define STM32_PRE_DIV11 (10 << 0) /**< SYSCLK divided by 11. */
+#define STM32_PRE_DIV12 (11 << 0) /**< SYSCLK divided by 12. */
+#define STM32_PRE_DIV13 (12 << 0) /**< PLLSRC divided by 13. */
+#define STM32_PRE_DIV14 (13 << 0) /**< SYSCLK divided by 14. */
+#define STM32_PRE_DIV15 (14 << 0) /**< SYSCLK divided by 15. */
+#define STM32_PRE_DIV16 (15 << 0) /**< PLLSRC divided by 16. */
+/** @} */
+
+/**
+ * @name RCC_CFGR3 register bits definitions
+ * @{
+ */
+#define STM32_USART1SW_MASK (3 << 0) /**< USART1 clock source mask. */
+#define STM32_USART1SW_PCLK (0 << 0) /**< USART1 clock is PCLK. */
+#define STM32_USART1SW_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */
+#define STM32_USART1SW_LSE (2 << 0) /**< USART1 clock is LSE. */
+#define STM32_USART1SW_HSI (3 << 0) /**< USART1 clock is HSI. */
+#define STM32_I2C1SW_MASK (1 << 4) /**< I2C clock source mask. */
+#define STM32_I2C1SW_HSI (0 << 4) /**< I2C clock is HSI. */
+#define STM32_I2C1SW_SYSCLK (1 << 4) /**< I2C clock is SYSCLK. */
+#define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */
+#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */
+#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */
+#define STM32_CECSW_OFF 0xFFFFFFFF /**< CEC clock is not required. */
+#define STM32_USBSW_MASK (1 << 7) /**< USB clock source mask. */
+#define STM32_USBSW_HSI48 (0 << 7) /**< USB clock is HSI48. */
+#define STM32_USBSW_PCLK (1 << 7) /**< USB clock is PCLK. */
+/** @} */
+
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
+#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
+#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
+#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
+#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 32 used as
+ RTC clock. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSI14 clock source.
+ */
+#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI14_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSI48 clock source.
+ */
+#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI48_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 48MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 48MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief Crystal PLL pre-divider.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV_VALUE 1
+#endif
+
+/**
+ * @brief PLL multiplier value.
+ * @note The allowed range is 2...16.
+ * @note The default value is calculated for a 48MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE 6
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 48MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
+#define STM32_PPRE STM32_PPRE_DIV1
+#endif
+
+/**
+ * @brief MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief MCO PLL divider setting.
+ */
+#if !defined(STM32_PLLNODIV) || defined(__DOXYGEN__)
+#define STM32_PLLNODIV STM32_PLLNODIV_DIV2
+#endif
+
+/**
+ * @brief USB Clock source.
+ */
+#if !defined(STM32_USBSW) || defined(__DOXYGEN__)
+#define STM32_USBSW STM32_USBSW_HSI48
+#endif
+
+/**
+ * @brief CEC clock source.
+ */
+#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
+#define STM32_CECSW STM32_CECSW_HSI
+#endif
+
+/**
+ * @brief I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
+#define STM32_I2C1SW STM32_I2C1SW_HSI
+#endif
+
+/**
+ * @brief USART1 clock source.
+ */
+#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
+#define STM32_USART1SW STM32_USART1SW_PCLK
+#endif
+
+/**
+ * @brief RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F0xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#if (STM32_SW == STM32_SW_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI) && !STM32_HAS_HSI_PREDIV
+#error "STM32_PLLSRC_HSI not available on this platform. Select STM32_PLLSRC_HSI_DIV2 instead."
+#endif
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if STM32_CECSW == STM32_CECSW_HSI
+#error "HSI not enabled, required by STM32_CECSW"
+#endif
+
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#error "HSI not enabled, required by STM32_I2C1SW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_HSI
+#error "HSI not enabled, required by STM32_USART1SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ ((STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSI14 related checks.
+ */
+#if STM32_HSI14_ENABLED
+#else /* !STM32_HSI14_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_HSI14
+#error "HSI14 not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI14_ENABLED */
+
+/*
+ * HSI48 related checks.
+ */
+#if STM32_HSI48_ENABLED
+#if !STM32_HAS_HSI48
+#error "HSI48 not available on this platform"
+#endif
+#else /* !STM32_HSI48_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI48
+#error "HSI48 not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI48) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ ((STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI48)))
+#error "HSI48 not enabled, required by STM32_MCOSEL"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI48)
+#error "HSI48 not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#endif /* !STM32_HSI48_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined"
+#endif
+
+#if (STM32_LSEDRV >> 3) > 3
+#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_CECSW == STM32_CECSW_LSE
+#error "LSE not enabled, required by STM32_CECSW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_LSE
+#error "LSE not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if (STM32_SW == STM32_SW_PLL) || \
+ (STM32_USBSW == STM32_USBSW_PCLK) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/* HSE, HSI prescaler setting check.*/
+#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
+#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0)
+#else
+#error "invalid STM32_PREDIV value specified"
+#endif
+
+/**
+ * @brief PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2
+#define STM32_PLLCLKIN (STM32_HSICLK / 2)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PREDIV_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI48
+#define STM32_PLLCLKIN (STM32_HSI48CLK / STM32_PREDIV_VALUE)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSI48)
+#define STM32_SYSCLK STM32_HSI48CLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB frequency.
+ */
+#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK (STM32_HCLK / 1)
+#elif STM32_PPRE == STM32_PPRE_DIV2
+#define STM32_PCLK (STM32_HCLK / 2)
+#elif STM32_PPRE == STM32_PPRE_DIV4
+#define STM32_PCLK (STM32_HCLK / 4)
+#elif STM32_PPRE == STM32_PPRE_DIV8
+#define STM32_PCLK (STM32_HCLK / 8)
+#elif STM32_PPRE == STM32_PPRE_DIV16
+#define STM32_PCLK (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE value specified"
+#endif
+
+/* APB frequency check.*/
+#if STM32_PCLK > STM32_PCLK_MAX
+#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
+#endif
+
+/* STM32_PLLNODIV check.*/
+#if (STM32_PLLNODIV != STM32_PLLNODIV_DIV2) && \
+ (STM32_PLLNODIV != STM32_PLLNODIV_DIV1)
+#error "invalid STM32_PLLNODIV value specified"
+#endif
+
+/**
+ * @brief MCO clock before divider.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_MCODIVCLK 0
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI14
+#define STM32_MCODIVCLK STM32_HSI14CLK
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+#define STM32_MCODIVCLK STM32_LSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+#define STM32_MCODIVCLK STM32_LSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
+#define STM32_MCODIVCLK STM32_SYSCLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI
+#define STM32_MCODIVCLK STM32_HSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+#define STM32_MCODIVCLK STM32_HSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_PLLDIV2
+#if STM32_PLLNODIV == STM32_PLLNODIV_DIV2
+#define STM32_MCODIVCLK (STM32_PLLCLKOUT / 2)
+#else
+#define STM32_MCODIVCLK (STM32_PLLCLKOUT / 1)
+#endif
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
+#define STM32_MCODIVCLK STM32_HSI48CLK
+#else
+#error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief MCO output pin clock.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCOCLK STM32_MCODIVCLK
+#elif (STM32_MCOPRE == STM32_MCOPRE_DIV2) && STM32_HAS_MCO_PREDIV
+#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
+#elif (STM32_MCOPRE == STM32_MCOPRE_DIV4) && STM32_HAS_MCO_PREDIV
+#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
+#elif (STM32_MCOPRE == STM32_MCOPRE_DIV8) && STM32_HAS_MCO_PREDIV
+#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
+#elif (STM32_MCOPRE == STM32_MCOPRE_DIV16) && STM32_HAS_MCO_PREDIV
+#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
+#elif !STM32_HAS_MCO_PREDIV
+#error "MCO_PREDIV not available on this platform. Select STM32_MCODIVCLK."
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
+/**
+ * @brief RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK (STM32_HSECLK / 32)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK 0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief USB frequency.
+ */
+#if (STM32_USBSW == STM32_USBSW_HSI48) || defined(__DOXYGEN__)
+#define STM32_USBCLK STM32_HSI48CLK
+#elif STM32_USBSW == STM32_USBSW_PCLK
+#define STM32_USBCLK STM32_PLLCLKOUT
+#else
+#error "invalid source selected for USB clock"
+#endif
+
+/**
+ * @brief CEC frequency.
+ */
+#if (STM32_CECSW == STM32_CECSW_HSI) || defined(__DOXYGEN__)
+#define STM32_CECCLK STM32_HSICLK
+#elif STM32_CECSW == STM32_CECSW_LSE
+#define STM32_CECCLK STM32_LSECLK
+#elif STM32_CECSW == STM32_CECSW_OFF
+#define STM32_CECCLK 0
+#else
+#error "invalid source selected for CEC clock"
+#endif
+
+/**
+ * @brief I2C1 frequency.
+ */
+#if (STM32_I2C1SW == STM32_I2C1SW_HSI) || defined(__DOXYGEN__)
+#define STM32_I2C1CLK STM32_HSICLK
+#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
+#define STM32_I2C1CLK STM32_SYSCLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief USART1 frequency.
+ */
+#if (STM32_USART1SW == STM32_USART1SW_PCLK) || defined(__DOXYGEN__)
+#define STM32_USART1CLK STM32_PCLK
+#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
+#define STM32_USART1CLK STM32_SYSCLK
+#elif STM32_USART1SW == STM32_USART1SW_LSE
+#define STM32_USART1CLK STM32_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_HSI
+#define STM32_USART1CLK STM32_HSICLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief USART2 frequency.
+ */
+#define STM32_USART2CLK STM32_PCLK
+
+/**
+ * @brief USART3 frequency.
+ */
+#define STM32_USART3CLK STM32_PCLK
+
+/**
+ * @brief USART4 frequency.
+ */
+#define STM32_UART4CLK STM32_PCLK
+
+/**
+ * @brief USART5 frequency.
+ */
+#define STM32_UART5CLK STM32_PCLK
+
+/**
+ * @brief USART6 frequency.
+ */
+#define STM32_USART6CLK STM32_PCLK
+
+/**
+ * @brief Timers clock.
+ */
+#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK * 1)
+#define STM32_TIMCLK2 (STM32_PCLK * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK * 2)
+#define STM32_TIMCLK2 (STM32_PCLK * 2)
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS 0x00000010
+#else
+#define STM32_FLASHBITS 0x00000011
+#endif
+
+/*
+ * For compatibility with driver assuming a specific PPRE clock.
+ */
+#define STM32_PCLK1 STM32_PCLK
+#define STM32_PCLK2 STM32_PCLK
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/platform.mk
new file mode 100644
index 0000000000..29b570b5a4
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/platform.mk
@@ -0,0 +1,33 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_ext_lld_isr.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
new file mode 100644
index 0000000000..3524a11412
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
@@ -0,0 +1,118 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F0xx/stm32_isr.h
+ * @brief ISR remapper driver header.
+ *
+ * @addtogroup STM32F0xx_ISR
+ * @{
+ */
+
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name ISR names and numbers remapping
+ * @{
+ */
+/*
+ * CAN units.
+ */
+#define STM32_CAN1_UNIFIED_HANDLER VectorB8
+#define STM32_CAN1_UNIFIED_NUMBER 30
+
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+
+/*
+ * TIM units.
+ */
+#define STM32_TIM1_UP_HANDLER Vector74
+#define STM32_TIM1_CC_HANDLER Vector78
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM3_HANDLER Vector80
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM7_HANDLER Vector88
+#define STM32_TIM14_HANDLER Vector8C
+#define STM32_TIM15_HANDLER Vector90
+#define STM32_TIM16_HANDLER Vector94
+#define STM32_TIM17_HANDLER Vector98
+
+#define STM32_TIM1_UP_NUMBER 13
+#define STM32_TIM1_CC_NUMBER 14
+#define STM32_TIM2_NUMBER 15
+#define STM32_TIM3_NUMBER 16
+#define STM32_TIM6_NUMBER 17
+#define STM32_TIM7_NUMBER 18
+#define STM32_TIM14_NUMBER 19
+#define STM32_TIM15_NUMBER 20
+#define STM32_TIM16_NUMBER 21
+#define STM32_TIM17_NUMBER 22
+
+/*
+ * USART units.
+ */
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART3_8_HANDLER VectorB4
+
+#define STM32_USART1_NUMBER 27
+#define STM32_USART2_NUMBER 28
+#define STM32_USART3_8_NUMBER 29
+
+/*
+ * USB units.
+ */
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#endif /* STM32_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
similarity index 81%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_rcc.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
index 786cec07b0..e64d453c85 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_rcc.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,12 +15,12 @@
*/
/**
- * @file STM32F1xx/stm32_rcc.h
+ * @file STM32F0xx/stm32_rcc.h
* @brief RCC helper driver header.
* @note This file requires definitions from the ST header file
- * @p stm32f10x.h.
+ * @p stm32f0xx.h.
*
- * @addtogroup STM32F1xx_RCC
+ * @addtogroup STM32F0xx_RCC
* @{
*/
@@ -199,106 +199,97 @@
/** @} */
/**
- * @name Backup domain interface specific RCC operations
+ * @name CAN peripherals specific RCC operations
* @{
*/
/**
- * @brief Enables the BKP interface clock.
+ * @brief Enables the CAN1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableBKPInterface(lp) rccEnableAPB1((RCC_APB1ENR_BKPEN), lp)
+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
/**
- * @brief Disables BKP interface clock.
+ * @brief Disables the CAN1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableBKPInterface(lp) rccDisableAPB1((RCC_APB1ENR_BKPEN), lp)
-
-/**
- * @brief Resets the Backup Domain interface.
- *
- * @api
- */
-#define rccResetBKPInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CANEN, lp)
/**
- * @brief Resets the entire Backup Domain.
+ * @brief Resets the CAN1 peripheral.
*
* @api
*/
-#define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST)
+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
/** @} */
/**
- * @name PWR interface specific RCC operations
+ * @name DAC peripheral specific RCC operations
* @{
*/
/**
- * @brief Enables the PWR interface clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
/**
- * @brief Disables PWR interface clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
/**
- * @brief Resets the PWR interface.
+ * @brief Resets the DAC1 peripheral.
*
* @api
*/
-#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
/** @} */
/**
- * @name CAN peripherals specific RCC operations
+ * @name PWR interface specific RCC operations
* @{
*/
/**
- * @brief Enables the CAN1 peripheral clock.
+ * @brief Enables the PWR interface clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
/**
- * @brief Disables the CAN1 peripheral clock.
+ * @brief Disables PWR interface clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
/**
- * @brief Resets the CAN1 peripheral.
+ * @brief Resets the PWR interface.
*
* @api
*/
-#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
/**
@@ -354,7 +345,7 @@
#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
/**
- * @brief Resets the DMA1 peripheral.
+ * @brief Resets the DMA2 peripheral.
* @note Not supported in this family, does nothing.
*
* @api
@@ -363,636 +354,628 @@
/** @} */
/**
- * @name ETH peripheral specific RCC operations
+ * @name I2C peripherals specific RCC operations
* @{
*/
/**
- * @brief Enables the ETH peripheral clock.
+ * @brief Enables the I2C1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableETH(lp) rccEnableAHB(RCC_AHBENR_ETHMACEN | \
- RCC_AHBENR_ETHMACTXEN | \
- RCC_AHBENR_ETHMACRXEN, lp)
+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
- * @brief Disables the ETH peripheral clock.
+ * @brief Disables the I2C1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableETH(lp) rccDisableAHB(RCC_AHBENR_ETHMACEN | \
- RCC_AHBENR_ETHMACTXEN | \
- RCC_AHBENR_ETHMACRXEN, lp)
+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
- * @brief Resets the ETH peripheral.
+ * @brief Resets the I2C1 peripheral.
*
* @api
*/
-#define rccResetETH() rccResetAHB(RCC_AHBRSTR_ETHMACRST)
-/** @} */
+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
/**
- * @name I2C peripherals specific RCC operations
- * @{
- */
-/**
- * @brief Enables the I2C1 peripheral clock.
+ * @brief Enables the I2C2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
/**
- * @brief Disables the I2C1 peripheral clock.
+ * @brief Disables the I2C2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
/**
- * @brief Resets the I2C1 peripheral.
+ * @brief Resets the I2C2 peripheral.
*
* @api
*/
-#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+/** @} */
/**
- * @brief Enables the I2C2 peripheral clock.
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
- * @brief Disables the I2C2 peripheral clock.
+ * @brief Disables the SPI1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
- * @brief Resets the I2C2 peripheral.
+ * @brief Resets the SPI1 peripheral.
*
* @api
*/
-#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
-/** @} */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
/**
- * @name OTG peripherals specific RCC operations
- * @{
- */
-/**
- * @brief Enables the OTG_FS peripheral clock.
+ * @brief Enables the SPI2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableOTG_FS(lp) rccEnableAHB(RCC_AHBENR_OTGFSEN, lp)
+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
/**
- * @brief Disables the OTG_FS peripheral clock.
+ * @brief Disables the SPI2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableOTG_FS(lp) rccDisableAHB(RCC_AHBENR_OTGFSEN, lp)
+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
/**
- * @brief Resets the OTG_FS peripheral.
+ * @brief Resets the SPI2 peripheral.
*
* @api
*/
-#define rccResetOTG_FS() rccResetAHB(RCC_AHBRSTR_OTGFSRST)
+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
/** @} */
/**
- * @name SDIO peripheral specific RCC operations
+ * @name TIM peripherals specific RCC operations
* @{
*/
/**
- * @brief Enables the SDIO peripheral clock.
+ * @brief Enables the TIM1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableSDIO(lp) rccEnableAHB(RCC_AHBENR_SDIOEN, lp)
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
/**
- * @brief Disables the SDIO peripheral clock.
+ * @brief Disables the TIM1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableSDIO(lp) rccDisableAHB(RCC_AHBENR_SDIOEN, lp)
+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
/**
- * @brief Resets the SDIO peripheral.
- * @note Not supported in this family, does nothing.
+ * @brief Resets the TIM1 peripheral.
*
* @api
*/
-#define rccResetSDIO()
-/** @} */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
/**
- * @name SPI peripherals specific RCC operations
- * @{
- */
-/**
- * @brief Enables the SPI1 peripheral clock.
+ * @brief Enables the TIM2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
- * @brief Disables the SPI1 peripheral clock.
+ * @brief Disables the TIM2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
- * @brief Resets the SPI1 peripheral.
+ * @brief Resets the TIM2 peripheral.
*
* @api
*/
-#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
/**
- * @brief Enables the SPI2 peripheral clock.
+ * @brief Enables the TIM3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
- * @brief Disables the SPI2 peripheral clock.
+ * @brief Disables the TIM3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
- * @brief Resets the SPI2 peripheral.
+ * @brief Resets the TIM3 peripheral.
*
* @api
*/
-#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
/**
- * @brief Enables the SPI3 peripheral clock.
+ * @brief Enables the TIM6 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
/**
- * @brief Disables the SPI3 peripheral clock.
+ * @brief Disables the TIM6 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
/**
- * @brief Resets the SPI3 peripheral.
+ * @brief Resets the TIM6 peripheral.
*
* @api
*/
-#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
-/** @} */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
/**
- * @name TIM peripherals specific RCC operations
- * @{
- */
-/**
- * @brief Enables the TIM1 peripheral clock.
+ * @brief Enables the TIM7 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
/**
- * @brief Disables the TIM1 peripheral clock.
+ * @brief Disables the TIM7 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
/**
- * @brief Resets the TIM1 peripheral.
+ * @brief Resets the TIM7 peripheral.
*
* @api
*/
-#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
/**
- * @brief Enables the TIM2 peripheral clock.
+ * @brief Enables the TIM14 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
/**
- * @brief Disables the TIM2 peripheral clock.
+ * @brief Disables the TIM14 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp)
/**
- * @brief Resets the TIM2 peripheral.
+ * @brief Resets the TIM14 peripheral.
*
* @api
*/
-#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
/**
- * @brief Enables the TIM3 peripheral clock.
+ * @brief Enables the TIM15 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
/**
- * @brief Disables the TIM3 peripheral clock.
+ * @brief Disables the TIM15 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp)
/**
- * @brief Resets the TIM3 peripheral.
+ * @brief Resets the TIM15 peripheral.
*
* @api
*/
-#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
/**
- * @brief Enables the TIM4 peripheral clock.
+ * @brief Enables the TIM16 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
/**
- * @brief Disables the TIM4 peripheral clock.
+ * @brief Disables the TIM16 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp)
/**
- * @brief Resets the TIM4 peripheral.
+ * @brief Resets the TIM16 peripheral.
*
* @api
*/
-#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
/**
- * @brief Enables the TIM5 peripheral clock.
+ * @brief Enables the TIM17 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
/**
- * @brief Disables the TIM5 peripheral clock.
+ * @brief Disables the TIM17 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)
+#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp)
/**
- * @brief Resets the TIM5 peripheral.
+ * @brief Resets the TIM17 peripheral.
*
* @api
*/
-#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+/** @} */
/**
- * @brief Enables the TIM6 peripheral clock.
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
- * @brief Disables the TIM6 peripheral clock.
+ * @brief Disables the USART1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
- * @brief Resets the TIM6 peripheral.
+ * @brief Resets the USART1 peripheral.
*
* @api
*/
-#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
/**
- * @brief Enables the TIM7 peripheral clock.
+ * @brief Enables the USART2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
/**
- * @brief Disables the TIM7 peripheral clock.
+ * @brief Disables the USART2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
/**
- * @brief Resets the TIM7 peripheral.
+ * @brief Resets the USART2 peripheral.
*
* @api
*/
-#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
/**
- * @brief Enables the TIM8 peripheral clock.
+ * @brief Enables the USART3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
/**
- * @brief Disables the TIM8 peripheral clock.
+ * @brief Disables the USART3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
/**
- * @brief Resets the TIM8 peripheral.
+ * @brief Resets the USART3 peripheral.
*
* @api
*/
-#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
-/** @} */
+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
/**
- * @name USART/UART peripherals specific RCC operations
- * @{
- */
-/**
- * @brief Enables the USART1 peripheral clock.
+ * @brief Enables the USART4 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_USART4EN, lp)
/**
- * @brief Disables the USART1 peripheral clock.
+ * @brief Disables the USART4 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_USART4EN, lp)
/**
- * @brief Resets the USART1 peripheral.
+ * @brief Resets the USART4 peripheral.
*
* @api
*/
-#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_USART4RST)
/**
- * @brief Enables the USART2 peripheral clock.
+ * @brief Enables the USART5 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_USART5EN, lp)
/**
- * @brief Disables the USART2 peripheral clock.
+ * @brief Disables the USART5 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_USART5EN, lp)
/**
- * @brief Resets the USART2 peripheral.
+ * @brief Resets the USART5 peripheral.
*
* @api
*/
-#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_USART5RST)
/**
- * @brief Enables the USART3 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Enables the USART6 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
+#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
/**
- * @brief Disables the USART3 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Disables the USART6 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)
/**
- * @brief Resets the USART3 peripheral.
+ * @brief Resets the USART6 peripheral.
*
* @api
*/
-#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
+/** @} */
/**
- * @brief Enables the UART4 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @name USB peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
+#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
/**
- * @brief Disables the UART4 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Disables the USB peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
+#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
/**
- * @brief Resets the UART4 peripheral.
+ * @brief Resets the USB peripheral.
*
* @api
*/
-#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
+#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+/** @} */
/**
- * @brief Enables the UART5 peripheral clock.
+ * @name CRC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRC peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
+#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
/**
- * @brief Disables the UART5 peripheral clock.
+ * @brief Disables the CRC peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
+#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN, lp)
/**
- * @brief Resets the UART5 peripheral.
+ * @brief Resets the CRC peripheral.
*
* @api
*/
-#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
+#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST)
/** @} */
/**
- * @name USB peripheral specific RCC operations
+ * @name WWDG peripherals specific RCC operations
* @{
*/
/**
- * @brief Enables the USB peripheral clock.
+ * @brief Enables the WWDG peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
+#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp)
/**
- * @brief Disables the USB peripheral clock.
+ * @brief Disables the WWDG peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
+#define rccDisableWWDG(lp) rccDisableAPB1(RCC_APB1ENR_WWDGEN, lp)
/**
- * @brief Resets the USB peripheral.
+ * @brief Resets the WWDG peripheral.
*
* @api
*/
-#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST)
/** @} */
/*===========================================================================*/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
new file mode 100644
index 0000000000..9696efc51e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
@@ -0,0 +1,2146 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F0xx/stm32_registry.h
+ * @brief STM32F0xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+#if !defined(STM32F0XX) || defined(__DOXYGEN__)
+#define STM32F0XX
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32F0xx capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* STM32F030x6, STM32F030x8, STM32F030xC. */
+/*===========================================================================*/
+#if defined(STM32F030x6) || defined(STM32F030x8) || \
+ defined(STM32F030xC) || defined(__DOXYGEN__)
+
+/* Common identifier of all STM32F030 devices.*/
+#define STM32F030
+
+/* RCC attributes. */
+#define STM32_HAS_HSI48 FALSE
+#if defined(STM32F030xC)
+#define STM32_HAS_HSI_PREDIV TRUE
+#else
+#define STM32_HAS_HSI_PREDIV FALSE
+#endif
+#define STM32_HAS_MCO_PREDIV TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI FALSE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000011
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#if defined(STM32F030xC) || defined(__DOXYGEN__)
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#else
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#endif
+#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 20
+#define STM32_EXTI_IMR_MASK 0xFFF50000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#if defined(STM32F030x8)
+#define STM32_HAS_GPIOD TRUE
+#else
+#define STM32_HAS_GPIOD FALSE
+#endif
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#if defined(STM32F030x8)
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+#else
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIOFEN)
+#endif
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_I2C1_RX_DMA_CHN 0x00000200
+#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C1_TX_DMA_CHN 0x00000020
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00020000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00002000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#if defined (STM32F030xC)
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#else
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#endif
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN 0x00000030
+#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN 0x00000300
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_RX_DMA_CHN 0x00003000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_SPI2_TX_DMA_CHN 0x00030000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#if defined(STM32F030x8) || defined(STM32F030xC)
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#else
+#define STM32_HAS_TIM6 FALSE
+#endif
+
+#if defined(STM32F030xC)
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+#else
+#define STM32_HAS_TIM7 FALSE
+#endif
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#if defined(STM32F030x8) || defined(STM32F030xC)
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+#else
+#define STM32_HAS_TIM15 FALSE
+#endif
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM2 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00080808
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00008080
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART2_RX_DMA_CHN 0x00090909
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART2_TX_DMA_CHN 0x00009090
+
+#if defined(STM32F030xC)
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART3_RX_DMA_CHN 0x000A0A0A
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN 0x0000A0A0
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_UART4_RX_DMA_CHN 0x000B0B0B
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_UART4_TX_DMA_CHN 0x0000B0B0
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_UART5_RX_DMA_CHN 0x000C0C0C
+#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_UART5_TX_DMA_CHN 0x0000C0C0
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART6_RX_DMA_CHN 0x000D0D0D
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART6_TX_DMA_CHN 0x0000D0D0
+
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+#else
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+#endif
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+/*===========================================================================*/
+/* STM32F031x6, STM32F038xx. */
+/*===========================================================================*/
+#elif defined(STM32F031x6) || defined(STM32F038xx)
+
+/* RCC attributes. */
+#define STM32_HAS_HSI48 FALSE
+#define STM32_HAS_HSI_PREDIV FALSE
+#define STM32_HAS_MCO_PREDIV TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x0FF40000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_I2C1_RX_DMA_CHN 0x00000000
+#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
+#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN 0x00000000
+#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART2 FALSE
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32F042x6. */
+/*===========================================================================*/
+#elif defined(STM32F042x6)
+
+/* RCC attributes. */
+#define STM32_HAS_HSI48 TRUE
+#define STM32_HAS_HSI_PREDIV TRUE
+#define STM32_HAS_MCO_PREDIV TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x7FF40000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_I2C1_RX_DMA_CHN 0x00000000
+#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
+#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN 0x00000000
+#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR TRUE
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32F048xx. */
+/*===========================================================================*/
+#elif defined(STM32F048xx)
+
+/* RCC attributes. */
+#define STM32_HAS_HSI48 TRUE
+#define STM32_HAS_HSI_PREDIV TRUE
+#define STM32_HAS_MCO_PREDIV TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x7FF40000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_I2C1_RX_DMA_CHN 0x00000000
+#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
+#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN 0x00000000
+#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR TRUE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32F051x8, STM32F058xx. */
+/*===========================================================================*/
+#elif defined(STM32F051x8) || defined(STM32F058xx)
+
+/* RCC attributes. */
+#define STM32_HAS_HSI48 FALSE
+#define STM32_HAS_HSI_PREDIV FALSE
+#define STM32_HAS_MCO_PREDIV FALSE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_DAC1_CH1_DMA_CHN 0x00000000
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x0F940000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_I2C1_RX_DMA_CHN 0x00000000
+#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00000000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
+#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN 0x00000000
+#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32F070x6, STM32F070xB. */
+/*===========================================================================*/
+#elif defined(STM32F070x6) || defined(STM32F070xB)
+
+/* Common identifier of all STM32F070 devices.*/
+#define STM32F070
+
+/* RCC attributes. */
+#define STM32_HAS_HSI48 FALSE
+#define STM32_HAS_HSI_PREDIV TRUE
+#define STM32_HAS_MCO_PREDIV TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x7F840000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_I2C1_RX_DMA_CHN 0x00000000
+#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00000000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#if defined (STM32F070xB)
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#else
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#endif
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN 0x00000000
+#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM2 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK 0
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK 0
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR TRUE
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+/*===========================================================================*/
+/* STM32F071xB, STM32F072xB, STM32F078xx. */
+/*===========================================================================*/
+#elif defined(STM32F071xB) || defined(STM32F072xB) || \
+ defined(STM32F078xx)
+
+/* RCC attributes. */
+#define STM32_HAS_HSI48 TRUE
+#define STM32_HAS_HSI_PREDIV TRUE
+#define STM32_HAS_MCO_PREDIV TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#if defined(STM32F072xB)
+#define STM32_HAS_CAN1 TRUE
+#define STM32_CAN_MAX_FILTERS 14
+#else
+#define STM32_HAS_CAN1 FALSE
+#endif
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_DAC1_CH1_DMA_CHN 0x00000000
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_DAC1_CH2_DMA_CHN 0x00000000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x7F840000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x00000000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00000000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
+#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN 0x00000000
+#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#if defined(STM32F072xB) || defined(STM32F078xx)
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR TRUE
+#else
+#define STM32_HAS_USB FALSE
+#endif
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32F091xC, STM32F098xx. */
+/*===========================================================================*/
+#elif defined(STM32F091xC) || defined(STM32F098xx)
+
+/* RCC attributes. */
+#define STM32_HAS_HSI48 TRUE
+#define STM32_HAS_HSI_PREDIV TRUE
+#define STM32_HAS_MCO_PREDIV TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC1_DMA_CHN 0x00100011
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000100
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH2_DMA_CHN 0x00001000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 5
+
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA12_CH23_CH12_HANDLER Vector68
+#define STM32_DMA12_CH4567_CH345_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA12_CH23_CH12_NUMBER 10
+#define STM32_DMA12_CH4567_CH345_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA2_CH1_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA2_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define DMA1_CH2_CMASK 0x00000186U
+#define DMA1_CH3_CMASK 0x00000186U
+#define DMA2_CH1_CMASK 0x00000186U
+#define DMA2_CH2_CMASK 0x00000186U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH3_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define DMA1_CH4_CMASK 0x00000E78U
+#define DMA1_CH5_CMASK 0x00000E78U
+#define DMA1_CH6_CMASK 0x00000E78U
+#define DMA1_CH7_CMASK 0x00000E78U
+#define DMA2_CH3_CMASK 0x00000E78U
+#define DMA2_CH4_CMASK 0x00000E78U
+#define DMA2_CH5_CMASK 0x00000E78U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x7F840000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x02000200
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00200020
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_I2C2_RX_DMA_CHN 0x00020020
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_I2C2_TX_DMA_CHN 0x00002002
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000330
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00003300
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00303000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x03030000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_USART1_RX_DMA_CHN 0x00880888
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_TX_DMA_CHN 0x08088088
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_USART2_RX_DMA_CHN 0x00990999
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART2_TX_DMA_CHN 0x09099099
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00AA0AAA
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART3_TX_DMA_CHN 0x0A0AA0AA
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_UART4_RX_DMA_CHN 0x00BB0BBB
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART4_TX_DMA_CHN 0x0B0BB0BB
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_UART5_RX_DMA_CHN 0x00CC0CCC
+#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART5_TX_DMA_CHN 0x0C0CC0CC
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_USART6_RX_DMA_CHN 0x00DD0DDD
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART6_TX_DMA_CHN 0x0D0DD0DD
+
+#define STM32_HAS_UART7 TRUE
+#define STM32_UART7_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_UART7_RX_DMA_CHN 0x00EE0EEE
+#define STM32_UART7_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART7_TX_DMA_CHN 0x0E0EE0EE
+
+#define STM32_HAS_UART8 TRUE
+#define STM32_UART8_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_UART8_RX_DMA_CHN 0x00FF0FFF
+#define STM32_UART8_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART8_TX_DMA_CHN 0x0F0FF0FF
+
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#else
+#error "STM32F0xx device not specified"
+#endif
+
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/adc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
similarity index 97%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/adc_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
index e4bc5b2afc..981fbf2a36 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/adc_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32F1xx/adc_lld.c
+ * @file STM32F1xx/hal_adc_lld.c
* @brief STM32F1xx ADC subsystem low level driver source.
*
* @addtogroup ADC
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_ADC || defined(__DOXYGEN__)
@@ -133,12 +132,12 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
- bool_t b;
+ bool b;
b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC1_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
- chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(FALSE);
}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/adc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.h
similarity index 97%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/adc_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.h
index 0c6b68919f..cb1af87e05 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/adc_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32F1xx/adc_lld.h
+ * @file STM32F1xx/hal_adc_lld.h
* @brief STM32F1xx ADC subsystem low level driver header.
*
* @addtogroup ADC
* @{
*/
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
#if HAL_USE_ADC || defined(__DOXYGEN__)
@@ -184,7 +184,7 @@ typedef struct {
/**
* @brief Enables the circular buffer mode for the group.
*/
- bool_t circular;
+ bool circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
@@ -276,17 +276,13 @@ struct ADCDriver {
/**
* @brief Waiting thread.
*/
- Thread *thread;
+ thread_reference_t thread;
#endif
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the peripheral.
*/
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
+ mutex_t mutex;
#endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS)
ADC_DRIVER_EXT_FIELDS
@@ -388,6 +384,6 @@ extern "C" {
#endif /* HAL_USE_ADC */
-#endif /* _ADC_LLD_H_ */
+#endif /* HAL_ADC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c
similarity index 53%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/ext_lld_isr.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c
index 8d9afb3cca..6d1b6ea660 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/ext_lld_isr.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,19 +15,18 @@
*/
/**
- * @file STM32F1xx/ext_lld_isr.c
+ * @file STM32F1xx/hal_ext_lld_isr.c
* @brief STM32F1xx EXT subsystem low level driver ISR code.
*
* @addtogroup EXT
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
-#include "ext_lld_isr.h"
+#include "hal_ext_lld_isr.h"
/*===========================================================================*/
/* Driver local definitions. */
@@ -54,14 +53,18 @@
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI0_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 0);
- EXTD1.config->channels[0].cb(&EXTD1, 0);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 0);
+ EXTI->PR = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -69,14 +72,18 @@ CH_IRQ_HANDLER(EXTI0_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI1_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 1);
- EXTD1.config->channels[1].cb(&EXTD1, 1);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 1);
+ EXTI->PR = pr;
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -84,14 +91,18 @@ CH_IRQ_HANDLER(EXTI1_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI2_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector60) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 2);
- EXTD1.config->channels[2].cb(&EXTD1, 2);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 2);
+ EXTI->PR = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -99,14 +110,18 @@ CH_IRQ_HANDLER(EXTI2_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI3_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector64) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 3);
- EXTD1.config->channels[3].cb(&EXTD1, 3);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 3);
+ EXTI->PR = pr;
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -114,14 +129,18 @@ CH_IRQ_HANDLER(EXTI3_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI4_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector68) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 4);
- EXTD1.config->channels[4].cb(&EXTD1, 4);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 4);
+ EXTI->PR = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -129,25 +148,26 @@ CH_IRQ_HANDLER(EXTI4_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector9C) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
+ pr = EXTI->PR;
+ pr &= ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9));
EXTI->PR = pr;
- if (pr & (1 << 5))
+ if (pr & (1U << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
- if (pr & (1 << 6))
+ if (pr & (1U << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
- if (pr & (1 << 7))
+ if (pr & (1U << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
- if (pr & (1 << 8))
+ if (pr & (1U << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
- if (pr & (1 << 9))
+ if (pr & (1U << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -155,28 +175,29 @@ CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
+OSAL_IRQ_HANDLER(VectorE0) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
- (1 << 15));
+ pr = EXTI->PR;
+ pr &= ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | (1U << 14) |
+ (1U << 15));
EXTI->PR = pr;
- if (pr & (1 << 10))
+ if (pr & (1U << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
- if (pr & (1 << 11))
+ if (pr & (1U << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
- if (pr & (1 << 12))
+ if (pr & (1U << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
- if (pr & (1 << 13))
+ if (pr & (1U << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
- if (pr & (1 << 14))
+ if (pr & (1U << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
- if (pr & (1 << 15))
+ if (pr & (1U << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -184,14 +205,18 @@ CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(PVD_IRQHandler) {
+OSAL_IRQ_HANDLER(Veector44) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 16);
- EXTD1.config->channels[16].cb(&EXTD1, 16);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 16);
+ EXTI->PR = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -199,14 +224,18 @@ CH_IRQ_HANDLER(PVD_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
+OSAL_IRQ_HANDLER(VectorE4) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 17);
- EXTD1.config->channels[17].cb(&EXTD1, 17);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 17);
+ EXTI->PR = pr;
+ if (pr & (1U << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#if defined(STM32F10X_CL)
@@ -215,14 +244,18 @@ CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(VectorE8) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 18);
- EXTD1.config->channels[18].cb(&EXTD1, 18);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 18);
+ EXTI->PR = pr;
+ if (pr & (1U << 18))
+ EXTD1.config->channels[18].cb(&EXTD1, 18);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -230,17 +263,20 @@ CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector138) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 19);
- EXTD1.config->channels[19].cb(&EXTD1, 19);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 19);
+ EXTI->PR = pr;
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL)
+#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL)
#else /* Other STM32F1xx devices.*/
/**
@@ -248,14 +284,18 @@ CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(VectorE8) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 18);
- EXTD1.config->channels[18].cb(&EXTD1, 18);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 18);
+ EXTI->PR = pr;
+ if (pr & (1U << 18))
+ EXTD1.config->channels[18].cb(&EXTD1, 18);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -270,37 +310,27 @@ CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
*/
void ext_lld_exti_irq_enable(void) {
- nvicEnableVector(EXTI0_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
- nvicEnableVector(EXTI1_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
- nvicEnableVector(EXTI2_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
- nvicEnableVector(EXTI3_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
- nvicEnableVector(EXTI4_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
- nvicEnableVector(EXTI9_5_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
- nvicEnableVector(EXTI15_10_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
- nvicEnableVector(PVD_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
- nvicEnableVector(RTC_Alarm_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
#if defined(STM32F10X_CL)
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/
- nvicEnableVector(OTG_FS_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
- nvicEnableVector(ETH_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL)
+ nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+#if defined(STM32F107xC)
+ /* EXTI vectors specific to STM32F107 Connectivity Line.*/
+ nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+#endif
+#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL)
/* EXTI vectors specific to STM32F1xx Value Line.*/
#else
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
- nvicEnableVector(USB_FS_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
+ nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
#endif
}
@@ -324,12 +354,11 @@ void ext_lld_exti_irq_disable(void) {
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/
nvicDisableVector(OTG_FS_WKUP_IRQn);
nvicDisableVector(ETH_WKUP_IRQn);
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL)
+#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL)
/* EXTI vectors specific to STM32F1xx Value Line.*/
#else
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
- nvicDisableVector(USB_FS_WKUP_IRQn);
+ nvicDisableVector(USBWakeUp_IRQn);
#endif
}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.h
similarity index 96%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/ext_lld_isr.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.h
index 9bc30d7c06..bdc8a302c9 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/ext_lld_isr.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32F1xx/ext_lld_isr.h
+ * @file STM32F1xx/hal_ext_lld_isr.h
* @brief STM32F1xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
-#ifndef _EXT_LLD_ISR_H_
-#define _EXT_LLD_ISR_H_
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
#if HAL_USE_EXT || defined(__DOXYGEN__)
@@ -144,6 +144,6 @@ extern "C" {
#endif /* HAL_USE_EXT */
-#endif /* _EXT_LLD_ISR_H_ */
+#endif /* HAL_EXT_LLD_ISR_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld.c
similarity index 86%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld.c
index a9a24467e7..2636b8716c 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,7 +22,6 @@
* @{
*/
-#include "ch.h"
#include "hal.h"
/*===========================================================================*/
@@ -33,6 +32,12 @@
/* Driver exported variables. */
/*===========================================================================*/
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32f10x.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -61,7 +66,13 @@ static void hal_lld_backup_domain_init(void) {
/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON;
+#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif /* STM32_LSE_ENABLED */
@@ -87,6 +98,28 @@ static void hal_lld_backup_domain_init(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+#if defined(STM32_DMA2_CH45_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 streams 4 and 5 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH45_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4 of DMA2.*/
+ dmaServeInterrupt(STM32_DMA2_STREAM4);
+
+ /* Check on channel 5 of DMA2.*/
+ dmaServeInterrupt(STM32_DMA2_STREAM5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA2_CH45_HANDLER) */
+#endif /* defined(STM32_DMA_REQUIRED) */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -102,17 +135,6 @@ void hal_lld_init(void) {
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
- /* SysTick initialization using the system clock.*/
- SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk |
- SysTick_CTRL_TICKINT_Msk;
-
- /* DWT cycle counter enable.*/
- SCS_DEMCR |= SCS_DEMCR_TRCENA;
- DWT_CTRL |= DWT_CTRL_CYCCNTENA;
-
/* PWR and BD clocks enabled.*/
rccEnablePWRInterface(FALSE);
rccEnableBKPInterface(FALSE);
@@ -160,7 +182,7 @@ void stm32_clock_init(void) {
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
- RCC->CR |= RCC_CR_HSEBYP;
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#endif
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
@@ -218,14 +240,23 @@ void stm32_clock_init(void) {
void stm32_clock_init(void) {
#if !STM32_NO_INIT
- /* HSI setup.*/
+ /* HSI setup, it enforces the reset situation in order to handle possible
+ problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
- RCC->CFGR = 0;
- RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+
+ /* HSI is selected as new source without touching the other fields in
+ CFGR. Clearing the register has to be postponed after HSI is the
+ new source.*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
+ RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
- ; /* Wait until HSI is the source.*/
+ ; /* Wait until HSI is selected. */
+
+ /* Registers finally cleared to reset values.*/
+ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+ RCC->CFGR = 0; /* CFGR reset value. */
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld.h
similarity index 67%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld.h
index 16b999a7ce..ce299761a2 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -20,36 +20,74 @@
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - STM32_LSECLK.
+ * - STM32_LSE_BYPASS (optionally).
* - STM32_HSECLK.
* - STM32_HSE_BYPASS (optionally).
* .
* One of the following macros must also be defined:
- * - STM32F10X_LD_VL for Value Line Low Density devices.
- * - STM32F10X_MD_VL for Value Line Medium Density devices.
- * - STM32F10X_LD for Performance Low Density devices.
- * - STM32F10X_MD for Performance Medium Density devices.
- * - STM32F10X_HD for Performance High Density devices.
- * - STM32F10X_XL for Performance eXtra Density devices.
- * - STM32F10X_CL for Connectivity Line devices.
+ * - STM32F100xB for Value Line Medium Density devices.
+ * - STM32F100xE for Value Line High Density devices.
+ * - STM32F101x6, STM32F102x6, STM32F103x6 for Performance
+ * Low Density devices.
+ * - STM32F101xB, STM32F102xB, STM32F103xB for Performance
+ * Medium Density devices.
+ * - STM32F101xE, STM32F103xE for Performance High Density devices.
+ * - STM32F101xG, STM32F103xG for Performance eXtra Density devices.
+ * - STM32F105xC, STM32F107xC for Connectivity Line devices.
* .
*
* @addtogroup HAL
* @{
*/
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
-#include "stm32.h"
+#include "stm32_registry.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
+ * @name Platform identification
+ * @{
*/
-#define HAL_IMPLEMENTS_COUNTERS TRUE
+#if defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32F1xx"
+
+#elif defined(STM32F10X_MD_VL)
+#define PLATFORM_NAME "STM32F100 Value Line Medium Density"
+
+#elif defined(STM32F10X_HD_VL)
+#define PLATFORM_NAME "STM32F100 Value Line High Density"
+
+#elif defined(STM32F10X_LD)
+#define PLATFORM_NAME "STM32F10x Performance Line Low Density"
+
+#elif defined(STM32F10X_MD)
+#define PLATFORM_NAME "STM32F10x Performance Line Medium Density"
+
+#elif defined(STM32F10X_HD)
+#define PLATFORM_NAME "STM32F10x Performance Line High Density"
+
+#elif defined(STM32F10X_XL)
+#define PLATFORM_NAME "STM32F10x Performance Line eXtra Density"
+
+#elif defined(STM32F10X_CL)
+#define PLATFORM_NAME "STM32F10x Connectivity Line"
+
+#else
+#error "unsupported or unrecognized STM32F1xx member"
+#endif
+
+/**
+ * @brief Sub-family identifier.
+ */
+#if !defined(STM32F1XX) || defined(__DOXYGEN__)
+#define STM32F1XX
+#endif
+/** @} */
/**
* @name Internal clock sources
@@ -78,16 +116,6 @@
/* Platform capabilities. */
/*===========================================================================*/
-/**
- * @name STM32F1xx capabilities
- * @{
- */
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_IS_CALENDAR FALSE
-/** @} */
-
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -150,16 +178,8 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if defined(__DOXYGEN__)
-/**
- * @name Platform identification
- * @{
- */
-#define PLATFORM_NAME "STM32"
-/** @} */
-
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL) || defined(__DOXYGEN__)
+#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) || \
+ defined(__DOXYGEN__)
#include "hal_lld_f100.h"
#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \
@@ -169,74 +189,22 @@
#elif defined(STM32F10X_CL) || defined(__DOXYGEN__)
#include "hal_lld_f105_f107.h"
-
-#else
-#error "unspecified, unsupported or invalid STM32 platform"
-#endif
-
-/* There are differences in vector names in the various sub-families,
- normalizing.*/
-#if defined(STM32F10X_XL)
-#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
-#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
-#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
-#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
-#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
-#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
-
-#elif defined(STM32F10X_LD_VL)|| defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL)
-#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
-#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() DWT_CYCCNT
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() STM32_HCLK
-
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-/* STM32 ISR, DMA and RCC helpers.*/
+/* Various helpers.*/
+#include "nvic.h"
#include "stm32_isr.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"
@@ -250,6 +218,6 @@ extern "C" {
}
#endif
-#endif /* _HAL_LLD_H_ */
+#endif /* HAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h
similarity index 55%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f100.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h
index 65be1dfd85..2f3b63c877 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -36,23 +36,6 @@
/* Driver constants. */
/*===========================================================================*/
-/**
- * @name Platform identification
- * @{
- */
-#if defined(__DOXYGEN__)
-#define PLATFORM_NAME "STM32F100 Value Line"
-
-#elif defined(STM32F10X_LD_VL)
-#define PLATFORM_NAME "STM32F100 Value Line Low Density"
-
-#elif defined(STM32F10X_MD_VL)
-#define PLATFORM_NAME "STM32F100 Value Line Medium Density"
-#else
-#error "unsupported STM32 Value Line member"
-#endif
-/** @} */
-
/**
* @name Absolute Maximum Ratings
* @{
@@ -88,7 +71,7 @@
#define STM32_PLLIN_MAX 24000000
/**
- * @brief Maximum PLLs input clock frequency.
+ * @brief Minimum PLLs input clock frequency.
*/
#define STM32_PLLIN_MIN 1000000
@@ -98,7 +81,7 @@
#define STM32_PLLOUT_MAX 24000000
/**
- * @brief Maximum PLL output clock frequency.
+ * @brief Minimum PLL output clock frequency.
*/
#define STM32_PLLOUT_MIN 16000000
@@ -178,365 +161,6 @@
RTC clock. */
/** @} */
-/*===========================================================================*/
-/* Platform capabilities. */
-/*===========================================================================*/
-
-#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-/**
- * @name STM32F100 LD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_HAS_ADC2 FALSE
-#define STM32_HAS_ADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 FALSE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_CAN_MAX_FILTERS 0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 18
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE FALSE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOH FALSE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 FALSE
-#define STM32_I2C2_RX_DMA_MSK 0
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK 0
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_SPI3_RX_DMA_MSK 0
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK 0
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 FALSE
-#define STM32_SPI2_RX_DMA_MSK 0
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK 0
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 FALSE
-#define STM32_SPI3_RX_DMA_MSK 0
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK 0
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 FALSE
-#define STM32_HAS_TIM5 FALSE
-#define STM32_HAS_TIM6 TRUE
-#define STM32_HAS_TIM7 TRUE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM9 FALSE
-#define STM32_HAS_TIM10 FALSE
-#define STM32_HAS_TIM11 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 TRUE
-#define STM32_HAS_TIM16 TRUE
-#define STM32_HAS_TIM17 TRUE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 FALSE
-#define STM32_USART3_RX_DMA_MSK 0
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK 0
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 FALSE
-#define STM32_UART4_RX_DMA_MSK 0
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK 0
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 FALSE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-#endif /* defined(STM32F10X_LD_VL) */
-
-#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
-/**
- * @name STM32F100 MD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_HAS_ADC2 FALSE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 FALSE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_CAN_MAX_FILTERS 0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOH FALSE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_I2C3_RX_DMA_MSK 0
-#define STM32_I2C3_RX_DMA_CHN 0x00000000
-#define STM32_I2C3_TX_DMA_MSK 0
-#define STM32_I2C3_TX_DMA_CHN 0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 FALSE
-#define STM32_HAS_SPI4 FALSE
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 TRUE
-#define STM32_HAS_TIM5 FALSE
-#define STM32_HAS_TIM6 TRUE
-#define STM32_HAS_TIM7 TRUE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM9 FALSE
-#define STM32_HAS_TIM10 FALSE
-#define STM32_HAS_TIM11 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 TRUE
-#define STM32_HAS_TIM16 TRUE
-#define STM32_HAS_TIM17 TRUE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 FALSE
-#define STM32_UART4_RX_DMA_MSK 0
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK 0
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 FALSE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-#endif /* defined(STM32F10X_MD_VL) */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names. */
-/*===========================================================================*/
-
-/**
- * @name IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
-#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
- detect. */
-#define TAMPER_IRQHandler Vector48 /**< Tamper. */
-#define RTC_IRQHandler Vector4C /**< RTC. */
-#define FLASH_IRQHandler Vector50 /**< Flash. */
-#define RCC_IRQHandler Vector54 /**< RCC. */
-#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
-#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
-#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
-#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
-#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
-#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */
-#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */
-#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */
-#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */
-#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */
-#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
-#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
-#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */
-#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
-#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */
-#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */
-#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and
- Commutation. */
-#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */
-#define TIM2_IRQHandler VectorB0 /**< TIM2. */
-#define TIM3_IRQHandler VectorB4 /**< TIM3. */
-#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-#define TIM4_IRQHandler VectorB8 /**< TIM4. */
-#endif
-#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
-#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
-#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
-#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */
-#endif
-#define SPI1_IRQHandler VectorCC /**< SPI1. */
-#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-#define SPI2_IRQHandler VectorD0 /**< SPI2. */
-#endif
-#define USART1_IRQHandler VectorD4 /**< USART1. */
-#define USART2_IRQHandler VectorD8 /**< USART2. */
-#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-#define USART3_IRQHandler VectorDC /**< USART3. */
-#endif
-#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
-#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */
-#define CEC_IRQHandler VectorE8 /**< CEC. */
-#define TIM12_IRQHandler VectorEC /**< TIM12. */
-#define TIM13_IRQHandler VectorF0 /**< TIM13. */
-#define TIM14_IRQHandler VectorF4 /**< TIM14. */
-/** @} */
-
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -687,8 +311,9 @@
#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
#endif
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
- ((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
#error "HSE not enabled, required by STM32_MCOSEL"
#endif
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h
new file mode 100644
index 0000000000..c2f1e42334
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h
@@ -0,0 +1,604 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @defgroup STM32F103_HAL STM32F103 HAL Support
+ * @details HAL support for STM32 Performance Line LD, MD and HD sub-families.
+ *
+ * @ingroup HAL
+ */
+
+/**
+ * @file STM32F1xx/hal_lld_f103.h
+ * @brief STM32F103 Performance Line HAL subsystem low level driver header.
+ *
+ * @addtogroup STM32F103_HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_F103_H_
+#define _HAL_LLD_F103_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX 72000000
+
+/**
+ * @brief Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX 25000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN 1000000
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX 1000000
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN 32768
+
+/**
+ * @brief Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX 25000000
+
+/**
+ * @brief Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN 1000000
+
+/**
+ * @brief Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX 72000000
+
+/**
+ * @brief Minimum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN 16000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX 36000000
+
+/**
+ * @brief Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX 72000000
+
+/**
+ * @brief Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX 14000000
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
+#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
+#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
+#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
+#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
+#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
+
+#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
+#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
+#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
+#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
+#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
+
+#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
+#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
+#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
+#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
+
+#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
+#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
+
+#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
+#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
+
+#define STM32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */
+#define STM32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */
+
+#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
+#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
+/** @} */
+
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
+#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
+#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
+#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
+#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
+ RTC clock. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief Crystal PLL pre-divider.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
+#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
+#endif
+
+/**
+ * @brief PLL multiplier value.
+ * @note The allowed range is 2...16.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE 9
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE STM32_ADCPRE_DIV4
+#endif
+
+/**
+ * @brief USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_REQUIRED TRUE
+#endif
+
+/**
+ * @brief USB prescaler initialization.
+ */
+#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
+#define STM32_USBPRE STM32_USBPRE_DIV1P5
+#endif
+
+/**
+ * @brief MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F103_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F103_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if STM32_USB_CLOCK_REQUIRED || \
+ (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
+ (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
+#error "invalid STM32_PLLXTPRE value specified"
+#endif
+
+/**
+ * @brief PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
+#define STM32_PLLCLKIN (STM32_HSECLK / 1)
+#else
+#define STM32_PLLCLKIN (STM32_HSECLK / 2)
+#endif
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK (STM32_HSECLK / 128)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK 0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief ADC frequency.
+ */
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK (STM32_PCLK2 / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK (STM32_PCLK2 / 4)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
+#define STM32_ADCCLK (STM32_PCLK2 / 6)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
+#define STM32_ADCCLK (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+
+/* ADC frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/**
+ * @brief USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+
+/**
+ * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Timers 1, 8, 9, 10, 11 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS 0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS 0x00000011
+#else
+#define STM32_FLASHBITS 0x00000012
+#endif
+
+#endif /* _HAL_LLD_F103_H_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h
similarity index 68%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h
index 10913c0271..a59e21c6c7 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -36,13 +36,6 @@
/* Driver constants. */
/*===========================================================================*/
-/**
- * @name Platform identification
- * @{
- */
-#define PLATFORM_NAME "STM32F10x Connectivity Line"
-/** @} */
-
/**
* @name Absolute Maximum Ratings
* @{
@@ -78,7 +71,7 @@
#define STM32_PLL1IN_MAX 12000000
/**
- * @brief Maximum PLL1 input clock frequency.
+ * @brief Minimum PLL1 input clock frequency.
*/
#define STM32_PLL1IN_MIN 3000000
@@ -88,7 +81,7 @@
#define STM32_PLL23IN_MAX 5000000
/**
- * @brief Maximum PLL2 and PLL3 input clock frequency.
+ * @brief Minimum PLL2 and PLL3 input clock frequency.
*/
#define STM32_PLL23IN_MIN 3000000
@@ -98,7 +91,7 @@
#define STM32_PLL1VCO_MAX 144000000
/**
- * @brief Maximum PLL1 VCO clock frequency.
+ * @brief Minimum PLL1 VCO clock frequency.
*/
#define STM32_PLL1VCO_MIN 36000000
@@ -108,7 +101,7 @@
#define STM32_PLL23VCO_MAX 148000000
/**
- * @brief Maximum PLL2 and PLL3 VCO clock frequency.
+ * @brief Minimum PLL2 and PLL3 VCO clock frequency.
*/
#define STM32_PLL23VCO_MIN 80000000
@@ -206,235 +199,6 @@
#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */
/** @} */
-/*===========================================================================*/
-/* Platform capabilities. */
-/*===========================================================================*/
-
-/**
- * @name STM32F105/F107 CL capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_HAS_ADC2 TRUE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH TRUE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 20
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOH FALSE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_I2C3_RX_DMA_MSK 0
-#define STM32_I2C3_RX_DMA_CHN 0x00000000
-#define STM32_I2C3_TX_DMA_MSK 0
-#define STM32_I2C3_TX_DMA_CHN 0x00000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 FALSE
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 TRUE
-#define STM32_HAS_TIM5 TRUE
-#define STM32_HAS_TIM6 TRUE
-#define STM32_HAS_TIM7 TRUE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM9 FALSE
-#define STM32_HAS_TIM10 FALSE
-#define STM32_HAS_TIM11 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 TRUE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names. */
-/*===========================================================================*/
-
-/**
- * @name IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
-#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
- detect. */
-#define TAMPER_IRQHandler Vector48 /**< Tamper. */
-#define RTC_IRQHandler Vector4C /**< RTC. */
-#define FLASH_IRQHandler Vector50 /**< Flash. */
-#define RCC_IRQHandler Vector54 /**< RCC. */
-#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
-#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
-#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
-#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
-#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
-#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */
-#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */
-#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */
-#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */
-#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */
-#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
-#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
-#define ADC1_2_IRQHandler Vector88 /**< ADC1 and ADC2. */
-#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */
-#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */
-#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */
-#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */
-#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
-#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */
-#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */
-#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and
- Commutation. */
-#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */
-#define TIM2_IRQHandler VectorB0 /**< TIM2. */
-#define TIM3_IRQHandler VectorB4 /**< TIM3. */
-#define TIM4_IRQHandler VectorB8 /**< TIM4. */
-#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
-#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
-#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
-#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */
-#define SPI1_IRQHandler VectorCC /**< SPI1. */
-#define SPI2_IRQHandler VectorD0 /**< SPI2. */
-#define USART1_IRQHandler VectorD4 /**< USART1. */
-#define USART2_IRQHandler VectorD8 /**< USART2. */
-#define USART3_IRQHandler VectorDC /**< USART3. */
-#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
-#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarm through EXTI
- line. */
-#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through
- EXTI line. */
-#define TIM5_IRQHandler Vector108 /**< TIM5. */
-#define SPI3_IRQHandler Vector10C /**< SPI3. */
-#define UART4_IRQHandler Vector110 /**< UART4. */
-#define UART5_IRQHandler Vector114 /**< UART5. */
-#define TIM6_IRQHandler Vector118 /**< TIM6. */
-#define TIM7_IRQHandler Vector11C /**< TIM7. */
-#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */
-#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */
-#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */
-#define DMA2_Ch4_IRQHandler Vector12C /**< DMA2 Channel4. */
-#define DMA2_Ch5_IRQHandler Vector130 /**< DMA2 Channel5. */
-#define ETH_IRQHandler Vector134 /**< Ethernet. */
-#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through
- EXTI line. */
-#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */
-#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */
-#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */
-#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */
-#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */
-/** @} */
-
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -639,10 +403,11 @@
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
- ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
- (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) || \
- (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) || \
+ (((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL2) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL3) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
(STM32_MCOSEL == STM32_MCOSEL_XT1)
#error "HSE not enabled, required by STM32_MCOSEL"
#endif
@@ -701,8 +466,7 @@
/* PLL2 activation conditions.*/
#if ((STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) && STM32_ACTIVATE_PLL1) || \
- (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) || \
- defined(__DOXYGEN__)
+ (STM32_MCOSEL == STM32_MCOSEL_PLL2) || defined(__DOXYGEN__)
/**
* @brief PLL2 activation flag.
*/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/platform.mk
new file mode 100644
index 0000000000..c6196c4a58
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/platform.mk
@@ -0,0 +1,37 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c
+endif
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk
new file mode 100644
index 0000000000..204ff2d784
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk
@@ -0,0 +1,37 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c
+endif
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_isr.h
similarity index 95%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_isr.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_isr.h
index c13c20c273..e42a96bbc5 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F1xx/stm32_isr.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_isr.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,8 +22,8 @@
* @{
*/
-#ifndef _STM32_ISR_H_
-#define _STM32_ISR_H_
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
@@ -129,6 +129,13 @@
#define STM32_USB1_HP_NUMBER 19
#define STM32_USB1_LP_NUMBER 20
+
+/*
+ * RTC unit
+ */
+#define STM32_RTC1_HANDLER Vector4C
+
+#define STM32_RTC1_NUMBER 3
/** @} */
/*===========================================================================*/
@@ -151,6 +158,6 @@
/* External declarations. */
/*===========================================================================*/
-#endif /* _STM32_ISR_H_ */
+#endif /* STM32_ISR_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h
new file mode 100644
index 0000000000..3f5ba19748
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h
@@ -0,0 +1,1336 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F1xx/stm32_rcc.h
+ * @brief RCC helper driver header.
+ * @note This file requires definitions from the ST header file
+ * @p stm32f10x.h.
+ *
+ * @addtogroup STM32F1xx_RCC
+ * @{
+ */
+
+#ifndef _STM32_RCC_
+#define _STM32_RCC_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1(mask, lp) { \
+ RCC->APB1ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1(mask, lp) { \
+ RCC->APB1ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1(mask) { \
+ RCC->APB1RSTR |= (mask); \
+ RCC->APB1RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB2 bus.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) { \
+ RCC->APB2ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB2 bus.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask, lp) { \
+ RCC->APB2ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) { \
+ RCC->APB2RSTR |= (mask); \
+ RCC->APB2RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB bus.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask AHB peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB(mask, lp) { \
+ RCC->AHBENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB bus.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask AHB peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB(mask, lp) { \
+ RCC->AHBENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB(mask) { \
+ RCC->AHBRSTR |= (mask); \
+ RCC->AHBRSTR = 0; \
+}
+/** @} */
+
+/**
+ * @name ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ADC1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief Disables the ADC1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief Resets the ADC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
+/** @} */
+
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
+/** @} */
+
+/**
+ * @name Backup domain interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the BKP interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableBKPInterface(lp) rccEnableAPB1((RCC_APB1ENR_BKPEN), lp)
+
+/**
+ * @brief Disables BKP interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableBKPInterface(lp) rccDisableAPB1((RCC_APB1ENR_BKPEN), lp)
+
+/**
+ * @brief Resets the Backup Domain interface.
+ *
+ * @api
+ */
+#define rccResetBKPInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
+
+/**
+ * @brief Resets the entire Backup Domain.
+ *
+ * @api
+ */
+#define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST)
+/** @} */
+
+/**
+ * @name PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
+/** @} */
+
+/**
+ * @name CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CAN1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
+
+/**
+ * @brief Disables the CAN1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
+
+/**
+ * @brief Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
+
+/**
+ * @brief Enables the CAN2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)
+
+/**
+ * @brief Disables the CAN2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)
+
+/**
+ * @brief Resets the CAN2 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)
+/** @} */
+
+/**
+ * @name DMA peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief Disables the DMA1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ * @note Not supported in this family, does nothing.
+ *
+ * @api
+ */
+#define rccResetDMA1()
+
+/**
+ * @brief Enables the DMA2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
+
+/**
+ * @brief Disables the DMA2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ * @note Not supported in this family, does nothing.
+ *
+ * @api
+ */
+#define rccResetDMA2()
+/** @} */
+
+/**
+ * @name ETH peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ETH peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableETH(lp) rccEnableAHB(RCC_AHBENR_ETHMACEN | \
+ RCC_AHBENR_ETHMACTXEN | \
+ RCC_AHBENR_ETHMACRXEN, lp)
+
+/**
+ * @brief Disables the ETH peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableETH(lp) rccDisableAHB(RCC_AHBENR_ETHMACEN | \
+ RCC_AHBENR_ETHMACTXEN | \
+ RCC_AHBENR_ETHMACRXEN, lp)
+
+/**
+ * @brief Resets the ETH peripheral.
+ *
+ * @api
+ */
+#define rccResetETH() rccResetAHB(RCC_AHBRSTR_ETHMACRST)
+/** @} */
+
+/**
+ * @name I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the I2C1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Disables the I2C1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
+
+/**
+ * @brief Enables the I2C2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Disables the I2C2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+/** @} */
+
+/**
+ * @name OTG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_FS(lp) rccEnableAHB(RCC_AHBENR_OTGFSEN, lp)
+
+/**
+ * @brief Disables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_FS(lp) rccDisableAHB(RCC_AHBENR_OTGFSEN, lp)
+
+/**
+ * @brief Resets the OTG_FS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_FS() rccResetAHB(RCC_AHBRSTR_OTGFSRST)
+/** @} */
+
+/**
+ * @name SDIO peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SDIO peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDIO(lp) rccEnableAHB(RCC_AHBENR_SDIOEN, lp)
+
+/**
+ * @brief Disables the SDIO peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSDIO(lp) rccDisableAHB(RCC_AHBENR_SDIOEN, lp)
+
+/**
+ * @brief Resets the SDIO peripheral.
+ * @note Not supported in this family, does nothing.
+ *
+ * @api
+ */
+#define rccResetSDIO()
+/** @} */
+
+/**
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Disables the SPI1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief Enables the SPI2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Disables the SPI2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+
+/**
+ * @brief Enables the SPI3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Disables the SPI3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
+/** @} */
+
+/**
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Disables the TIM1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
+/**
+ * @brief Enables the TIM2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Disables the TIM2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
+/**
+ * @brief Enables the TIM3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+
+/**
+ * @brief Enables the TIM4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief Disables the TIM4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+
+/**
+ * @brief Enables the TIM5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
+
+/**
+ * @brief Disables the TIM5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)
+
+/**
+ * @brief Resets the TIM5 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
+ * @brief Enables the TIM8 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Disables the TIM8 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
+
+/**
+
+ * @brief Enables the TIM9 peripheral clock.
+
+ * @note The @p lp parameter is ignored in this family.
+
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
+
+/**
+ * @brief Disables the TIM9 peripheral clock.
+
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)
+
+/**
+ * @brief Resets the TIM9 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
+
+/**
+ * @brief Enables the TIM10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
+
+/**
+ * @brief Disables the TIM10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
+
+/**
+ * @brief Resets the TIM10 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
+
+/**
+ * @brief Enables the TIM11 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)
+
+/**
+ * @brief Disables the TIM11 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp)
+
+/**
+ * @brief Resets the TIM11 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)
+
+/**
+ * @brief Enables the TIM12 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)
+
+/**
+ * @brief Disables the TIM12 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp)
+
+/**
+ * @brief Resets the TIM12 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
+
+/**
+ * @brief Enables the TIM13 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Disables the TIM13 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Resets the TIM13 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
+
+/**
+ * @brief Enables the TIM14 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
+
+/**
+ * @brief Disables the TIM14 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp)
+
+/**
+ * @brief Resets the TIM14 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
+
+/**
+ * @brief Enables the TIM15 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Disables the TIM15 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Resets the TIM15 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
+
+/**
+ * @brief Enables the TIM16 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Disables the TIM16 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Resets the TIM16 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
+
+/**
+ * @brief Enables the TIM17 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Disables the TIM17 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Resets the TIM17 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+/** @} */
+
+/**
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Disables the USART1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief Enables the USART2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Disables the USART2 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
+/** @} */
+
+/**
+ * @name USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Disables the USB peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+/** @} */
+
+/**
+ * @name FSMC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableFSMC(lp) rccEnableAHB(RCC_AHBENR_FSMCEN, lp)
+
+/**
+ * @brief Disables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableFSMC(lp) rccDisableAHB(RCC_AHBENR_FSMCEN, lp)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_RCC_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
new file mode 100644
index 0000000000..5ccbb6a5bb
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
@@ -0,0 +1,1354 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F1xx/stm32_registry.h
+ * @brief STM32F1xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+#if defined(STM32F100xB)
+#define STM32F10X_MD_VL
+
+#elif defined(STM32F100xE)
+#define STM32F10X_HD_VL
+
+#elif defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
+#define STM32F10X_LD
+
+#elif defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define STM32F10X_MD
+
+#elif defined(STM32F101xE) || defined(STM32F103xE)
+#define STM32F10X_HD
+
+#elif defined(STM32F101xG) || defined(STM32F103xG)
+#define STM32F10X_XL
+
+#elif defined(STM32F105xC) || defined(STM32F107xC)
+#define STM32F10X_CL
+
+#elif defined(STM32F10X_MD)
+/* Fix for dRonin */
+
+#else
+#error "unsupported or unrecognized STM32F1xx member"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F100 MD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 0
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 19
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+/** @} */
+#endif /* defined(STM32F10X_MD_VL) */
+
+#if defined(STM32F10X_LD) || defined(__DOXYGEN__)
+/**
+ * @name STM32F103 LD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 19
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+/** @} */
+#endif /* defined(STM32F10X_LD) */
+
+#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
+/**
+ * @name STM32F103 MD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 19
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+/** @} */
+#endif /* defined(STM32F10X_MD) */
+
+#if defined(STM32F10X_HD) || defined(__DOXYGEN__)
+/**
+ * @name STM32F103 HD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH45_HANDLER Vector12C
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH45_NUMBER 59
+
+#define STM32_DMA2_CH4_NUMBER STM32_DMA2_CH45_NUMBER
+#define STM32_DMA2_CH5_NUMBER STM32_DMA2_CH45_NUMBER
+#define DMA2_CH4_CMASK 0x00000C00U
+#define DMA2_CH5_CMASK 0x00000C00U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 19
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS FALSE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 4
+
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC FALSE
+#define STM32_FSMC_HANDLER Vector100
+#define STM32_FSMC_NUMBER 48
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+/** @} */
+#endif /* defined(STM32F10X_HD) */
+
+#if defined(STM32F10X_XL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F103 XL capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 19
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS FALSE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 4
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC FALSE
+#define STM32_FSMC_HANDLER Vector100
+#define STM32_FSMC_NUMBER 48
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+/** @} */
+#endif /* defined(STM32F10X_XL) */
+
+#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F105/F107 CL capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH TRUE
+#define STM32_ETH_HANDLER Vector134
+#define STM32_ETH_NUMBER 61
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 20
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS FALSE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 1
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 3
+
+#define STM32_HAS_OTG2 FALSE
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+/** @} */
+#endif /* defined(STM32F10X_CL) */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
new file mode 100644
index 0000000000..e85b1eeb1d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
@@ -0,0 +1,735 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/hal_adc_lld.c
+ * @brief STM32F37x ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define SDADC_FORBIDDEN_CR1_FLAGS (SDADC_CR1_INIT | SDADC_CR1_RDMAEN | \
+ SDADC_CR1_RSYNC | SDADC_CR1_JSYNC | \
+ SDADC_CR1_ROVRIE | SDADC_CR1_REOCIE | \
+ SDADC_CR1_JEOCIE | SDADC_CR1_EOCALIE)
+
+#define SDADC_ENFORCED_CR1_FLAGS (SDADC_CR1_JDMAEN | SDADC_CR1_JOVRIE)
+
+#define SDADC_FORBIDDEN_CR2_FLAGS (SDADC_CR2_RSWSTART | \
+ SDADC_CR2_RCONT | \
+ SDADC_CR2_RCH | \
+ SDADC_CR2_JCONT | \
+ SDADC_CR2_STARTCALIB | \
+ SDADC_CR2_CALIBCNT)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/** @brief SDADC1 driver identifier.*/
+#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
+ADCDriver SDADCD1;
+#endif
+
+/** @brief SDADC2 driver identifier.*/
+#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
+ADCDriver SDADCD2;
+#endif
+
+/** @brief SDADC3 driver identifier.*/
+#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
+ADCDriver SDADCD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+static const ADCConfig adc_lld_default_config = {
+#if STM32_ADC_USE_SDADC
+ 0,
+ {
+ 0,
+ 0,
+ 0
+ }
+#else /* !STM32_ADC_USE_SDADC */
+ 0
+#endif /* !STM32_ADC_USE_SDADC */
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Stops, reconfigures and restarts an ADC/SDADC.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ */
+static void adc_lld_reconfig(ADCDriver *adcp) {
+
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+ if (adcp->adc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC
+ {
+ /* ADC initial setup, starting the analog part here in order to reduce
+ the latency when starting a conversion.*/
+ uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
+ adcp->adc->CR2 = cr2;
+ adcp->adc->CR1 = 0;
+ adcp->adc->CR2 = cr2 | ADC_CR2_ADON;
+
+ }
+#endif /* STM32_ADC_USE_ADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+ else if (adcp->sdadc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_SDADC
+ {
+ /* SDADC initial setup, starting the analog part here in order to reduce
+ the latency when starting a conversion.*/
+ adcp->sdadc->CR2 = 0;
+ adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
+ ~SDADC_FORBIDDEN_CR1_FLAGS;
+ adcp->sdadc->CONF0R = (adcp->sdadc->CONF0R & SDADC_CONFR_OFFSET_MASK) |
+ adcp->config->confxr[0];
+ adcp->sdadc->CONF1R = (adcp->sdadc->CONF1R & SDADC_CONFR_OFFSET_MASK) |
+ adcp->config->confxr[1];
+ adcp->sdadc->CONF2R = (adcp->sdadc->CONF2R & SDADC_CONFR_OFFSET_MASK) |
+ adcp->config->confxr[2];
+ adcp->sdadc->CR2 = SDADC_CR2_ADON;
+ }
+#endif /* STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+else {
+ osalDbgAssert(FALSE, "invalid state");
+ }
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+}
+
+/**
+ * @brief ADC DMA ISR service routine.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ *
+ * @notapi
+ */
+static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+ /* DMA errors handling.*/
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ /* DMA, this could help only if the DMA tries to access an unmapped
+ address space or violates alignment rules.*/
+ _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+ }
+ else {
+ /* It is possible that the conversion group has already be reset by the
+ ADC error handler, in this case this interrupt is spurious.*/
+ if (adcp->grpp != NULL) {
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _adc_isr_full_code(adcp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _adc_isr_half_code(adcp);
+ }
+ }
+ }
+}
+
+#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
+/**
+ * @brief ADC ISR service routine.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ * @param[in] sr content of the ISR register
+ *
+ * @notapi
+ */
+static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sr) {
+
+ /* It could be a spurious interrupt caused by overflows after DMA disabling,
+ just ignore it in this case.*/
+ if (adcp->grpp != NULL) {
+ if (sr & ADC_SR_AWD) {
+ /* Analog watchdog error.*/
+ _adc_isr_error_code(adcp, ADC_ERR_AWD1);
+ }
+ }
+}
+#endif /* STM32_ADC_USE_ADC */
+
+#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
+/**
+ * @brief ADC ISR service routine.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ * @param[in] isr content of the ISR register
+ *
+ * @notapi
+ */
+static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
+
+ /* It could be a spurious interrupt caused by overflows after DMA disabling,
+ just ignore it in this case.*/
+ if (adcp->grpp != NULL) {
+ /* Note, an overflow may occur after the conversion ended before the driver
+ is able to stop the ADC, this is why the DMA channel is checked too.*/
+ if ((isr & SDADC_ISR_JOVRF) &&
+ (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
+ /* ADC overflow condition, this could happen only if the DMA is unable
+ to read data fast enough.*/
+ _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
+ }
+ }
+}
+#endif /* STM32_ADC_USE_SDADC */
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief ADC1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector88) {
+ uint32_t sr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ sr = ADC1->SR;
+ ADC1->SR = 0;
+ adc_lld_serve_interrupt(&ADCD1, sr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
+/**
+ * @brief SDADC1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector134) {
+ uint32_t isr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ isr = SDADC1->ISR;
+ SDADC1->CLRISR = isr;
+ sdadc_lld_serve_interrupt(&SDADCD1, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_SDADC1 */
+
+#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
+/**
+ * @brief SDADC2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector138) {
+ uint32_t isr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ isr = SDADC2->ISR;
+ SDADC2->CLRISR = isr;
+ sdadc_lld_serve_interrupt(&SDADCD2, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_SDADC2 */
+
+#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
+/**
+ * @brief SDADC3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector13C) {
+ uint32_t isr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ isr = SDADC3->ISR;
+ SDADC3->CLRISR = isr;
+ sdadc_lld_serve_interrupt(&SDADCD3, isr);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_SDADC3 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.adc = ADC1;
+#if STM32_ADC_USE_SDADC
+ ADCD1.sdadc = NULL;
+#endif
+ ADCD1.dmastp = STM32_DMA1_STREAM1;
+ ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ nvicEnableVector(ADC1_IRQn, STM32_ADC_ADC1_IRQ_PRIORITY);
+#endif
+
+#if STM32_ADC_USE_SDADC1
+ /* Driver initialization.*/
+ adcObjectInit(&SDADCD1);
+#if STM32_ADC_USE_ADC
+ SDADCD1.adc = NULL;
+#endif
+ SDADCD1.sdadc = SDADC1;
+ SDADCD1.dmastp = STM32_DMA2_STREAM3;
+ SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ nvicEnableVector(SDADC1_IRQn, STM32_ADC_SDADC1_IRQ_PRIORITY);
+#endif
+
+#if STM32_ADC_USE_SDADC2
+ /* Driver initialization.*/
+ adcObjectInit(&SDADCD2);
+#if STM32_ADC_USE_ADC
+ SDADCD2.adc = NULL;
+#endif
+ SDADCD2.sdadc = SDADC2;
+ SDADCD2.dmastp = STM32_DMA2_STREAM4;
+ SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ nvicEnableVector(SDADC2_IRQn, STM32_ADC_SDADC2_IRQ_PRIORITY);
+#endif
+
+#if STM32_ADC_USE_SDADC3
+ /* Driver initialization.*/
+ adcObjectInit(&SDADCD3);
+#if STM32_ADC_USE_ADC
+ SDADCD3.adc = NULL;
+#endif
+ SDADCD3.sdadc = SDADC3;
+ SDADCD3.dmastp = STM32_DMA2_STREAM5;
+ SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+ nvicEnableVector(SDADC3_IRQn, STM32_ADC_SDADC3_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+ if (adcp->config == NULL)
+ adcp->config = &adc_lld_default_config;
+
+ /* If in stopped state then enables the ADC and DMA clocks.*/
+ if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+ if (&ADCD1 == adcp) {
+ bool b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
+ dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+ rccEnableADC1(FALSE);
+ }
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_SDADC1
+ if (&SDADCD1 == adcp) {
+ bool b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_SDADC1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
+ dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR);
+ rccEnableSDADC1(FALSE);
+ PWR->CR |= PWR_CR_SDADC1EN;
+ adcp->sdadc->CR2 = 0;
+ adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
+ ~SDADC_FORBIDDEN_CR1_FLAGS;
+ adcp->sdadc->CR2 = SDADC_CR2_ADON;
+ }
+#endif /* STM32_ADC_USE_SDADC1 */
+
+#if STM32_ADC_USE_SDADC2
+ if (&SDADCD2 == adcp) {
+ bool b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_SDADC2_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
+ dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);
+ rccEnableSDADC2(FALSE);
+ PWR->CR |= PWR_CR_SDADC2EN;
+ adcp->sdadc->CR2 = 0;
+ adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
+ ~SDADC_FORBIDDEN_CR1_FLAGS;
+ adcp->sdadc->CR2 = SDADC_CR2_ADON;
+ }
+#endif /* STM32_ADC_USE_SDADC2 */
+
+#if STM32_ADC_USE_SDADC3
+ if (&SDADCD3 == adcp) {
+ bool b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_SDADC3_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
+ dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);
+ rccEnableSDADC3(FALSE);
+ PWR->CR |= PWR_CR_SDADC3EN;
+ adcp->sdadc->CR2 = 0;
+ adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
+ ~SDADC_FORBIDDEN_CR1_FLAGS;
+ adcp->sdadc->CR2 = SDADC_CR2_ADON;
+ }
+#endif /* STM32_ADC_USE_SDADC3 */
+ }
+
+ adc_lld_reconfig(adcp);
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+ /* If in ready state then disables the ADC clock.*/
+ if (adcp->state == ADC_READY) {
+ dmaStreamRelease(adcp->dmastp);
+
+#if STM32_ADC_USE_ADC1
+ if (&ADCD1 == adcp) {
+ adcp->adc->CR1 = 0;
+ adcp->adc->CR2 = 0;
+ rccDisableADC1(FALSE);
+ }
+#endif
+
+#if STM32_ADC_USE_SDADC1
+ if (&SDADCD1 == adcp) {
+ adcp->sdadc->CR1 = 0;
+ adcp->sdadc->CR2 = 0;
+ rccDisableSDADC1(FALSE);
+ PWR->CR &= ~PWR_CR_SDADC1EN;
+ }
+#endif
+
+#if STM32_ADC_USE_SDADC2
+ if (&SDADCD2 == adcp) {
+ adcp->sdadc->CR1 = 0;
+ adcp->sdadc->CR2 = 0;
+ rccDisableSDADC2(FALSE);
+ PWR->CR &= ~PWR_CR_SDADC2EN;
+ }
+#endif
+
+#if STM32_ADC_USE_SDADC3
+ if (&SDADCD3 == adcp) {
+ adcp->sdadc->CR1 = 0;
+ adcp->sdadc->CR2 = 0;
+ rccDisableSDADC3(FALSE);
+ PWR->CR &= ~PWR_CR_SDADC3EN;
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+ uint32_t mode;
+ const ADCConversionGroup* grpp = adcp->grpp;
+
+ /* DMA setup.*/
+ mode = adcp->dmamode;
+ if (grpp->circular) {
+ mode |= STM32_DMA_CR_CIRC;
+ if (adcp->depth > 1) {
+ /* If circular buffer depth > 1, then the half transfer interrupt
+ is enabled in order to allow streaming processing.*/
+ mode |= STM32_DMA_CR_HTIE;
+ }
+ }
+ dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+ dmaStreamSetTransactionSize(adcp->dmastp,
+ (uint32_t)grpp->num_channels *
+ (uint32_t)adcp->depth);
+ dmaStreamSetMode(adcp->dmastp, mode);
+ dmaStreamEnable(adcp->dmastp);
+
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+ if (adcp->adc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC
+ {
+ uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
+ cr2 |= grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
+ if ((cr2 & ADC_CR2_SWSTART) != 0)
+ cr2 |= ADC_CR2_CONT;
+ adcp->adc->CR2 = cr2;
+
+ /* ADC setup.*/
+ adcp->adc->SR = 0;
+ adcp->adc->LTR = grpp->u.adc.ltr;
+ adcp->adc->HTR = grpp->u.adc.htr;
+ adcp->adc->SMPR1 = grpp->u.adc.smpr[0];
+ adcp->adc->SMPR2 = grpp->u.adc.smpr[1];
+ adcp->adc->SQR1 = grpp->u.adc.sqr[0] |
+ ADC_SQR1_NUM_CH(grpp->num_channels);
+ adcp->adc->SQR2 = grpp->u.adc.sqr[1];
+ adcp->adc->SQR3 = grpp->u.adc.sqr[2];
+
+ /* ADC conversion start, the start is performed using the method
+ specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
+ adcp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_AWDIE | ADC_CR1_SCAN;
+ adcp->adc->CR2 = adcp->adc->CR2; /* Triggers the conversion start.*/
+ }
+#endif /* STM32_ADC_USE_ADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+ else if (adcp->sdadc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_SDADC
+ {
+ uint32_t cr2 = (grpp->u.sdadc.cr2 & ~SDADC_FORBIDDEN_CR2_FLAGS) |
+ SDADC_CR2_ADON;
+ if ((grpp->u.sdadc.cr2 & SDADC_CR2_JSWSTART) != 0)
+ cr2 |= SDADC_CR2_JCONT;
+
+ /* Entering initialization mode.*/
+ adcp->sdadc->CR1 |= SDADC_CR1_INIT;
+ while ((adcp->sdadc->ISR & SDADC_ISR_INITRDY) == 0)
+ ;
+
+ /* SDADC setup.*/
+ adcp->sdadc->JCHGR = grpp->u.sdadc.jchgr;
+ adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0];
+ adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1];
+
+ /* SDADC trigger modes, this write must be performed when
+ SDADC_CR1_INIT=1.*/
+ adcp->sdadc->CR2 = cr2;
+
+ /* Leaving initialization mode.*/
+ adcp->sdadc->CR1 &= ~SDADC_CR1_INIT;
+
+ /* Special case, if SDADC_CR2_JSWSTART is specified it has to be
+ written after SDADC_CR1_INIT has been set to zero. Just a write is
+ performed, any other bit is ingore if not in initialization mode.*/
+ adcp->sdadc->CR2 = cr2;
+ }
+#endif /* STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+ else {
+ osalDbgAssert(FALSE, "invalid state");
+ }
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+ /* Disabling the associated DMA stream.*/
+ dmaStreamDisable(adcp->dmastp);
+
+ /* Stopping and restarting the whole ADC, apparently the only way to stop
+ a conversion.*/
+ adc_lld_reconfig(adcp);
+}
+
+/**
+ * @brief Calibrates an ADC unit.
+ * @note The calibration must be performed after calling @p adcStart().
+ * @note For SDADC units it is assumed that the field SDADC_CR2_CALIBCNT
+ * has been
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @api
+ */
+void adcSTM32Calibrate(ADCDriver *adcp) {
+
+ osalDbgAssert((adcp->state == ADC_READY) ||
+ (adcp->state == ADC_COMPLETE) ||
+ (adcp->state == ADC_ERROR),
+ "not ready");
+
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+ if (adcp->adc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC
+ {
+ /* Resetting calibration just to be safe.*/
+ ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+ while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
+ ;
+
+ /* Calibration.*/
+ ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+ while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
+ ;
+ }
+#endif /* STM32_ADC_USE_ADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+ else if (adcp->sdadc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_SDADC
+ {
+ /* Selecting a full calibration in three steps.*/
+ adcp->sdadc->CR2 = (adcp->sdadc->CR2 & ~SDADC_CR2_CALIBCNT) |
+ SDADC_CR2_CALIBCNT_1;
+
+ /* Calibration.*/
+ adcp->sdadc->CR2 |= SDADC_CR2_STARTCALIB;
+ while ((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0)
+ ;
+
+ /* Clearing the EOCALF flag.*/
+ adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF;
+ }
+#endif /* STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+ else {
+ osalDbgAssert(FALSE, "invalid state");
+ }
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+}
+
+#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
+/**
+ * @brief Enables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ *
+ * @api
+ */
+void adcSTM32EnableTSVREFE(void) {
+
+ ADC1->CR2 |= ADC_CR2_TSVREFE;
+}
+
+/**
+ * @brief Disables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ *
+ * @api
+ */
+void adcSTM32DisableTSVREFE(void) {
+
+ ADC1->CR2 &= ~ADC_CR2_TSVREFE;
+}
+
+/**
+ * @brief Enables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ *
+ * @api
+ */
+void adcSTM32EnableVBATE(void) {
+
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT;
+}
+
+/**
+ * @brief Disables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ *
+ * @api
+ */
+void adcSTM32DisableVBATE(void) {
+
+ SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_VBAT;
+}
+#endif /* STM32_ADC_USE_ADC */
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h
new file mode 100644
index 0000000000..fa787fb319
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h
@@ -0,0 +1,706 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/hal_adc_lld.h
+ * @brief STM32F37x ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Triggers selection
+ * @{
+ */
+#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */
+/** @} */
+
+/**
+ * @name ADC clock divider settings
+ * @{
+ */
+#define ADC_CCR_ADCPRE_DIV2 0
+#define ADC_CCR_ADCPRE_DIV4 1
+#define ADC_CCR_ADCPRE_DIV6 2
+#define ADC_CCR_ADCPRE_DIV8 3
+/** @} */
+
+/**
+ * @name Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
+#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
+#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
+#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
+#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
+#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
+#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
+#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
+#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
+#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
+#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
+#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
+#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
+#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
+#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
+#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
+#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/
+#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */
+#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. */
+/** @} */
+
+/**
+ * @name Sampling rates
+ * @{
+ */
+#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */
+#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */
+#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */
+#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */
+#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */
+#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */
+#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */
+#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */
+/** @} */
+
+/**
+ * @name SDADC JCHGR bit definitions
+ * @{
+ */
+#define SDADC_JCHG_MASK (511U << 0)
+#define SDADC_JCHG(n) (1U << (n))
+/** @} */
+
+/**
+ * @name SDADC channels definitions
+ * @{
+ */
+#define SDADC_CHANNEL_0 SDADC_JCHG(0)
+#define SDADC_CHANNEL_1 SDADC_JCHG(1)
+#define SDADC_CHANNEL_2 SDADC_JCHG(2)
+#define SDADC_CHANNEL_3 SDADC_JCHG(3)
+#define SDADC_CHANNEL_4 SDADC_JCHG(4)
+#define SDADC_CHANNEL_5 SDADC_JCHG(5)
+#define SDADC_CHANNEL_6 SDADC_JCHG(6)
+#define SDADC_CHANNEL_7 SDADC_JCHG(7)
+#define SDADC_CHANNEL_8 SDADC_JCHG(8)
+#define SDADC_CHANNEL_9 SDADC_JCHG(9)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1 FALSE
+#endif
+
+/**
+ * @brief SDADC1 driver enable switch.
+ * @details If set to @p TRUE the support for SDADC1 is included.
+ */
+#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC1 FALSE
+#endif
+
+/**
+ * @brief SDADC2 driver enable switch.
+ * @details If set to @p TRUE the support for SDADC2 is included.
+ */
+#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC2 FALSE
+#endif
+
+/**
+ * @brief SDADC3 driver enable switch.
+ * @details If set to @p TRUE the support for SDADC3 is included.
+ */
+#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC3 FALSE
+#endif
+
+/**
+ * @brief ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief SDADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief SDADC2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief SDADC3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief ADC interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief ADC DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC1 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC2 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC3 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC2 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC3 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/**
+ * @brief At least an ADC unit is in use.
+ */
+#define STM32_ADC_USE_ADC STM32_ADC_USE_ADC1
+
+/**
+ * @brief At least an SDADC unit is in use.
+ */
+#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 || \
+ STM32_ADC_USE_SDADC2 || \
+ STM32_ADC_USE_SDADC3)
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1
+#error "SDADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2
+#error "SDADC2 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3
+#error "SDADC3 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC
+#error "ADC driver activated but no ADC/SDADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_SDADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC1"
+#endif
+
+#if STM32_ADC_USE_SDADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_SDADC1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDADC1"
+#endif
+
+#if STM32_ADC_USE_SDADC2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC2"
+#endif
+
+#if STM32_ADC_USE_SDADC2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC2 DMA"
+#endif
+
+#if STM32_ADC_USE_SDADC2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDADC2"
+#endif
+
+#if STM32_ADC_USE_SDADC3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC3"
+#endif
+
+#if STM32_ADC_USE_SDADC3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC3 DMA"
+#endif
+
+#if STM32_ADC_USE_SDADC3 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDADC3"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
+ ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ * @note The use of this configuration structure requires knowledge of
+ * STM32 ADC cell registers interface, please refer to the STM32
+ * reference manual for details.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+
+ /**
+ * @brief Union of ADC and SDADC config parms. The decision of which struct
+ * union to use is determined by the ADCDriver. If the ADCDriver adc parm
+ * is not NULL, then use the adc struct, otherwise if the ADCDriver sdadc parm
+ * is not NULL, then use the sdadc struct.
+ */
+ union {
+#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
+ struct {
+ /**
+ * @brief ADC CR1 register initialization data.
+ * @note All the required bits must be defined into this field except
+ * @p ADC_CR1_SCAN that is enforced inside the driver.
+ */
+ uint32_t cr1;
+ /**
+ * @brief ADC CR2 register initialization data.
+ * @note All the required bits must be defined into this field except
+ * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+ * enforced inside the driver.
+ */
+ uint32_t cr2;
+ /**
+ * @brief ADC LTR register initialization data.
+ */
+ uint32_t ltr;
+ /**
+ * @brief ADC HTR register initialization data.
+ */
+ uint32_t htr;
+ /**
+ * @brief ADC SMPRx registers initialization data.
+ */
+ uint32_t smpr[2];
+ /**
+ * @brief ADC SQRx register initialization data.
+ */
+ uint32_t sqr[3];
+ } adc;
+#endif /* STM32_ADC_USE_ADC */
+#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
+ struct {
+ /**
+ * @brief SDADC CR2 register initialization data.
+ * @note Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL
+ * and @p SDADC_CR2_JEXTEN can be specified in this field.
+ */
+ uint32_t cr2;
+ /**
+ * @brief SDADC JCHGR register initialization data.
+ */
+ uint32_t jchgr;
+ /**
+ * @brief SDADC CONFCHxR registers initialization data.
+ */
+ uint32_t confchr[2];
+ } sdadc;
+#endif /* STM32_ADC_USE_SDADC */
+ } u;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+#if STM32_ADC_USE_SDADC
+ /**
+ * @brief SDADC CR1 register initialization data.
+ */
+ uint32_t cr1;
+ /**
+ * @brief SDADC CONFxR registers initialization data.
+ */
+ uint32_t confxr[3];
+#else /* !STM32_ADC_USE_SDADC */
+ uint32_t dummy;
+#endif /* !STM32_ADC_USE_SDADC */
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig *config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t *samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
+ /**
+ * @brief Pointer to the ADCx registers block.
+ */
+ ADC_TypeDef *adc;
+#endif
+#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
+ /**
+ * @brief Pointer to the SDADCx registers block.
+ */
+ SDADC_TypeDef *sdadc;
+#endif
+ /**
+ * @brief Pointer to associated DMA channel.
+ */
+ const stm32_dma_stream_t *dmastp;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Sequences building helper macros for ADC
+ * @{
+ */
+/**
+ * @brief Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
+#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
+#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
+#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
+#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
+
+#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
+#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
+#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
+#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
+#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
+#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
+
+#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
+#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
+#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
+#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
+#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
+#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
+/** @} */
+
+/**
+ * @name Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
+#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
+#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
+#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
+#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
+#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
+#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
+#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
+#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
+#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
+
+#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
+#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
+#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
+#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
+#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
+ sampling time. */
+#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
+ sampling time. */
+#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
+/** @} */
+
+/**
+ * @name Sequences building helper macros for SDADC
+ * @{
+ */
+#define SDADC_JCHGR_CH(n) (1U << (n))
+/** @} */
+
+/**
+ * @name Channel configuration number helper macros for SDADC
+ * @{
+ */
+#define SDADC_CONFCHR1_CH0(n) ((n) << 0)
+#define SDADC_CONFCHR1_CH1(n) ((n) << 4)
+#define SDADC_CONFCHR1_CH2(n) ((n) << 8)
+#define SDADC_CONFCHR1_CH3(n) ((n) << 12)
+#define SDADC_CONFCHR1_CH4(n) ((n) << 16)
+#define SDADC_CONFCHR1_CH5(n) ((n) << 20)
+#define SDADC_CONFCHR1_CH6(n) ((n) << 24)
+#define SDADC_CONFCHR1_CH7(n) ((n) << 28)
+#define SDADC_CONFCHR2_CH8(n) ((n) << 0)
+/** @} */
+
+/**
+ * @name Configuration registers helper macros for SDADC
+ * @{
+ */
+#define SDADC_CONFR_OFFSET_MASK (0xFFFU << 0)
+#define SDADC_CONFR_OFFSET(n) ((n) << 0)
+#define SDADC_CONFR_GAIN_MASK (7U << 20)
+#define SDADC_CONFR_GAIN_1X (0U << 20)
+#define SDADC_CONFR_GAIN_2X (1U << 20)
+#define SDADC_CONFR_GAIN_4X (2U << 20)
+#define SDADC_CONFR_GAIN_8X (3U << 20)
+#define SDADC_CONFR_GAIN_16X (4U << 20)
+#define SDADC_CONFR_GAIN_32X (5U << 20)
+#define SDADC_CONFR_GAIN_0P5X (7U << 20)
+#define SDADC_CONFR_SE_MASK (3U << 26)
+#define SDADC_CONFR_SE_DIFF (0U << 26)
+#define SDADC_CONFR_SE_OFFSET (1U << 26)
+#define SDADC_CONFR_SE_ZERO_VOLT (3U << 26)
+#define SDADC_CONFR_COMMON_MASK (3U << 30)
+#define SDADC_CONFR_COMMON_VSSSD (0U << 30)
+#define SDADC_CONFR_COMMON_VDDSD2 (1U << 30)
+#define SDADC_CONFR_COMMON_VDDSD (2U << 30)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD1;
+#endif
+
+#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD2;
+#endif
+
+#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void adc_lld_init(void);
+ void adc_lld_start(ADCDriver *adcp);
+ void adc_lld_stop(ADCDriver *adcp);
+ void adc_lld_start_conversion(ADCDriver *adcp);
+ void adc_lld_stop_conversion(ADCDriver *adcp);
+ void adcSTM32Calibrate(ADCDriver *adcdp);
+#if STM32_ADC_USE_ADC
+ void adcSTM32EnableTSVREFE(void);
+ void adcSTM32DisableTSVREFE(void);
+ void adcSTM32EnableVBATE(void);
+ void adcSTM32DisableVBATE(void);
+#endif /* STM32_ADC_USE_ADC */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* HAL_ADC_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c
new file mode 100644
index 0000000000..8eca506eef
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c
@@ -0,0 +1,400 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/hal_ext_lld_isr.c
+ * @brief STM32F37x EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "hal_ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if !defined(STM32_DISABLE_EXTI0_HANDLER)
+/**
+ * @brief EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 0);
+ EXTI->PR = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI1_HANDLER)
+/**
+ * @brief EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 1);
+ EXTI->PR = pr;
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI2_HANDLER)
+/**
+ * @brief EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 2);
+ EXTI->PR = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI3_HANDLER)
+/**
+ * @brief EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 3);
+ EXTI->PR = pr;
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI4_HANDLER)
+/**
+ * @brief EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 4);
+ EXTI->PR = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
+/**
+ * @brief EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9));
+ EXTI->PR = pr;
+ if (pr & (1U << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1U << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1U << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1U << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1U << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
+/**
+ * @brief EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
+ EXTI->PR = pr;
+ if (pr & (1U << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1U << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1U << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1U << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1U << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1U << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI16_HANDLER)
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 16);
+ EXTI->PR = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI17_HANDLER)
+/**
+ * @brief EXTI[17] interrupt handler (RTC Alarm).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 17);
+ EXTI->PR = pr;
+ if (pr & (1U << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_HAS_USB && !defined(STM32_DISABLE_EXTI18_HANDLER)
+/**
+ * @brief EXTI[18] interrupt handler (USB Wakeup).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector170) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 18);
+ EXTI->PR = pr;
+ if (pr & (1U << 18))
+ EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI19_HANDLER)
+/**
+ * @brief EXTI[19] interrupt handler (Tamper TimeStamp).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 19);
+ EXTI->PR = pr;
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI20_HANDLER)
+/**
+ * @brief EXTI[20] interrupt handler (RTC Wakeup).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 20);
+ EXTI->PR = pr;
+ if (pr & (1U << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI21_22_HANDLER)
+/**
+ * @brief EXTI[21]..EXTI[22] interrupt handler (COMP1, COMP2).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector140) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 21) | (1U << 22));
+ EXTI->PR = pr;
+ if (pr & (1U << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1U << 22))
+ EXTD1.config->channels[22].cb(&EXTD1, 22);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+#if STM32_HAS_USB
+ nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+#endif
+ nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+ nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+ nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(EXTI0_IRQn);
+ nvicDisableVector(EXTI1_IRQn);
+ nvicDisableVector(EXTI2_TSC_IRQn);
+ nvicDisableVector(EXTI3_IRQn);
+ nvicDisableVector(EXTI4_IRQn);
+ nvicDisableVector(EXTI9_5_IRQn);
+ nvicDisableVector(EXTI15_10_IRQn);
+ nvicDisableVector(PVD_IRQn);
+ nvicDisableVector(RTC_Alarm_IRQn);
+#if STM32_HAS_USB
+ nvicDisableVector(USBWakeUp_IRQn);
+#endif
+ nvicDisableVector(TAMP_STAMP_IRQn);
+ nvicDisableVector(RTC_WKUP_IRQn);
+ nvicDisableVector(COMP_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.h
new file mode 100644
index 0000000000..a9e767c1b7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.h
@@ -0,0 +1,163 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/hal_ext_lld_isr.h
+ * @brief STM32F37x EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI2 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI4 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI5..9 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI10..15 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI16 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI17 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI18 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI19 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI20 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI21..22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_exti_irq_enable(void);
+ void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_lld.c
new file mode 100644
index 0000000000..1a167cf424
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_lld.c
@@ -0,0 +1,208 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/hal_lld.c
+ * @brief STM32F37x HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32f3xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ * @note WARNING! Changing clock source impossible without resetting
+ * of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+ /* Backup domain reset.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+ }
+
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->BDCR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->BDCR |= RCC_BDCR_RTCEN;
+ }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Reset of all peripherals.*/
+ rccResetAHB(0xFFFFFFFF);
+ rccResetAPB1(0xFFFFFFFF);
+ rccResetAPB2(0xFFFFFFFF);
+
+ /* PWR clock enabled.*/
+ rccEnablePWRInterface(FALSE);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+ /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+ PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+}
+
+/**
+ * @brief STM32 clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+ /* HSI setup, it enforces the reset situation in order to handle possible
+ problems with JTAG probes and re-initializations.*/
+ RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
+ while (!(RCC->CR & RCC_CR_HSIRDY))
+ ; /* Wait until HSI is stable. */
+
+ /* HSI is selected as new source without touching the other fields in
+ CFGR. Clearing the register has to be postponed after HSI is the
+ new source.*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
+ RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ ; /* Wait until HSI is selected. */
+
+ /* Registers finally cleared to reset values.*/
+ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+ RCC->CFGR = 0; /* CFGR reset value. */
+
+#if STM32_HSE_ENABLED
+ /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+ /* No HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON;
+#endif
+ while (!(RCC->CR & RCC_CR_HSERDY))
+ ; /* Waits until HSE is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Waits until LSI is stable. */
+#endif
+
+ /* Clock settings.*/
+ RCC->CFGR = STM32_SDPRE | STM32_MCOSEL | STM32_USBPRE |
+ STM32_PLLMUL | STM32_PLLSRC | STM32_ADCPRE |
+ STM32_PPRE1 | STM32_PPRE2 | STM32_HPRE;
+ RCC->CFGR2 = STM32_PREDIV;
+ RCC->CFGR3 = STM32_USART3SW | STM32_USART2SW | STM32_I2C2SW |
+ STM32_I2C1SW | STM32_USART1SW;
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ; /* Waits until PLL is stable. */
+#endif
+
+ /* Flash setup and final clock selection. */
+ FLASH->ACR = STM32_FLASHBITS;
+
+ /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+ /* Switches clock source.*/
+ RCC->CFGR |= STM32_SW;
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ; /* Waits selection complete. */
+#endif
+#endif /* !STM32_NO_INIT */
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_lld.h
new file mode 100644
index 0000000000..5749a96579
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/hal_lld.h
@@ -0,0 +1,1002 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/hal_lld.h
+ * @brief STM32F37x HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_LSEDRV.
+ * - STM32_LSE_BYPASS (optionally).
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32F373xC for Analog & DSP devices.
+ * - STM32F378xx for Analog & DSP devices.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification macros
+ * @{
+ */
+#if defined(STM32F373xC) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32F373xC Analog & DSP"
+
+#elif defined(STM32F378xx)
+#define PLATFORM_NAME "STM32F378xx Analog & DSP"
+
+#else
+#error "STM32F7x device not specified"
+#endif
+
+/**
+ * @brief Sub-family identifier.
+ */
+#if !defined(STM32F37X) || defined(__DOXYGEN__)
+#define STM32F37X
+#endif
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX 72000000
+
+/**
+ * @brief Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX 32000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN 1000000
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX 1000000
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN 32768
+
+/**
+ * @brief Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX 24000000
+
+/**
+ * @brief Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN 1000000
+
+/**
+ * @brief Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX 72000000
+
+/**
+ * @brief Minimum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN 16000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX 36000000
+
+/**
+ * @brief Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX 72000000
+
+/**
+ * @brief Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX 14000000
+
+/**
+ * @brief Minimum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MIN 6000000
+
+/**
+ * @brief Maximum SDADC clock frequency in fast mode.
+ */
+#define STM32_SDADCCLK_FAST_MAX 6000000
+
+/**
+ * @brief Maximum SDADC clock frequency in slow mode.
+ */
+#define STM32_SDADCCLK_SLOW_MAX 1500000
+
+/**
+ * @brief Minimum SDADC clock frequency.
+ */
+#define STM32_SDADCCLK_MIN 500000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK 8000000 /**< High speed internal clock. */
+#define STM32_LSICLK 40000 /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK (7U << 5) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0U << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1U << 5) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2U << 5) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3U << 5) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4U << 5) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5U << 5) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6U << 5) /**< PVD level 6. */
+#define STM32_PLS_LEV7 (7U << 5) /**< PVD level 7. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI (0U << 0) /**< SYSCLK source is HSI. */
+#define STM32_SW_HSE (1U << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (2U << 0) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_DIV1 (0U << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8u << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9U << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10U << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11U << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12U << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13U << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14U << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15U << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE1_DIV1 (0U << 8) /**< HCLK divided by 1. */
+#define STM32_PPRE1_DIV2 (4U << 8) /**< HCLK divided by 2. */
+#define STM32_PPRE1_DIV4 (5U << 8) /**< HCLK divided by 4. */
+#define STM32_PPRE1_DIV8 (6U << 8) /**< HCLK divided by 8. */
+#define STM32_PPRE1_DIV16 (7U << 8) /**< HCLK divided by 16. */
+
+#define STM32_PPRE2_DIV1 (0U << 11) /**< HCLK divided by 1. */
+#define STM32_PPRE2_DIV2 (4U << 11) /**< HCLK divided by 2. */
+#define STM32_PPRE2_DIV4 (5U << 11) /**< HCLK divided by 4. */
+#define STM32_PPRE2_DIV8 (6U << 11) /**< HCLK divided by 8. */
+#define STM32_PPRE2_DIV16 (7U << 11) /**< HCLK divided by 16. */
+
+#define STM32_ADCPRE_DIV2 (0U << 14) /**< PPRE2 divided by 2. */
+#define STM32_ADCPRE_DIV4 (1U << 14) /**< PPRE2 divided by 4. */
+#define STM32_ADCPRE_DIV6 (2U << 14) /**< PPRE2 divided by 6. */
+#define STM32_ADCPRE_DIV8 (3U << 14) /**< PPRE2 divided by 8. */
+
+#define STM32_PLLSRC_HSI (0U << 16) /**< PLL clock source is HSI/2. */
+#define STM32_PLLSRC_HSE (1U << 16) /**< PLL clock source is
+ HSE/PREDIV. */
+
+#define STM32_USBPRE_DIV1P5 (0U << 22) /**< USB clock is PLLCLK/1.5. */
+#define STM32_USBPRE_DIV1 (1U << 22) /**< USB clock is PLLCLK/1. */
+
+#define STM32_MCOSEL_NOCLOCK (0U << 24) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_LSI (2U << 24) /**< LSI clock on MCO pin. */
+#define STM32_MCOSEL_LSE (3U << 24) /**< LSE clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (4U << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_HSI (5U << 24) /**< HSI clock on MCO pin. */
+#define STM32_MCOSEL_HSE (6U << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLLDIV2 (7U << 24) /**< PLL/2 clock on MCO pin. */
+
+#define STM32_SDPRE_DIV2 (16U << 27) /**< SYSCLK divided by 2. */
+#define STM32_SDPRE_DIV4 (17U << 27) /**< SYSCLK divided by 4. */
+#define STM32_SDPRE_DIV6 (18U << 27) /**< SYSCLK divided by 6. */
+#define STM32_SDPRE_DIV8 (19U << 27) /**< SYSCLK divided by 8. */
+#define STM32_SDPRE_DIV10 (20U << 27) /**< SYSCLK divided by 10. */
+#define STM32_SDPRE_DIV12 (21U << 27) /**< SYSCLK divided by 12. */
+#define STM32_SDPRE_DIV14 (22U << 27) /**< SYSCLK divided by 14. */
+#define STM32_SDPRE_DIV16 (23U << 27) /**< SYSCLK divided by 16. */
+#define STM32_SDPRE_DIV20 (24U << 27) /**< SYSCLK divided by 20. */
+#define STM32_SDPRE_DIV24 (25U << 27) /**< SYSCLK divided by 24. */
+#define STM32_SDPRE_DIV28 (26U << 27) /**< SYSCLK divided by 28. */
+#define STM32_SDPRE_DIV32 (27U << 27) /**< SYSCLK divided by 32. */
+#define STM32_SDPRE_DIV36 (28U << 27) /**< SYSCLK divided by 36. */
+#define STM32_SDPRE_DIV40 (29U << 27) /**< SYSCLK divided by 40. */
+#define STM32_SDPRE_DIV44 (30U << 27) /**< SYSCLK divided by 44. */
+#define STM32_SDPRE_DIV48 (31U << 27) /**< SYSCLK divided by 48. */
+/** @} */
+
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3U << 8) /**< RTC clock source mask. */
+#define STM32_RTCSEL_NOCLOCK (0U << 8) /**< No clock. */
+#define STM32_RTCSEL_LSE (1U << 8) /**< LSE used as RTC clock. */
+#define STM32_RTCSEL_LSI (2U << 8) /**< LSI used as RTC clock. */
+#define STM32_RTCSEL_HSEDIV (3U << 8) /**< HSE divided by 32 used as
+ RTC clock. */
+/** @} */
+
+/**
+ * @name RCC_CFGR2 register bits definitions
+ * @{
+ */
+#define STM32_PREDIV_MASK (15U << 0) /**< PREDIV divisor mask. */
+/** @} */
+
+/**
+ * @name RCC_CFGR3 register bits definitions
+ * @{
+ */
+#define STM32_USART1SW_MASK (3U << 0) /**< USART1 clock source mask. */
+#define STM32_USART1SW_PCLK (0U << 0) /**< USART1 clock is PCLK. */
+#define STM32_USART1SW_SYSCLK (1U << 0) /**< USART1 clock is SYSCLK. */
+#define STM32_USART1SW_LSE (2U << 0) /**< USART1 clock is LSE. */
+#define STM32_USART1SW_HSI (3U << 0) /**< USART1 clock is HSI. */
+#define STM32_I2C1SW_MASK (1U << 4) /**< I2C1 clock source mask. */
+#define STM32_I2C1SW_HSI (0U << 4) /**< I2C1 clock is HSI. */
+#define STM32_I2C1SW_SYSCLK (1U << 4) /**< I2C1 clock is SYSCLK. */
+#define STM32_I2C2SW_MASK (1U << 5) /**< I2C2 clock source mask. */
+#define STM32_I2C2SW_HSI (0U << 5) /**< I2C2 clock is HSI. */
+#define STM32_I2C2SW_SYSCLK (1U << 5) /**< I2C2 clock is SYSCLK. */
+#define STM32_USART2SW_MASK (3U << 16) /**< USART2 clock source mask. */
+#define STM32_USART2SW_PCLK (0U << 16) /**< USART2 clock is PCLK. */
+#define STM32_USART2SW_SYSCLK (1U << 16) /**< USART2 clock is SYSCLK. */
+#define STM32_USART2SW_LSE (2U << 16) /**< USART2 clock is LSE. */
+#define STM32_USART2SW_HSI (3U << 16) /**< USART2 clock is HSI. */
+#define STM32_USART3SW_MASK (3U << 18) /**< USART3 clock source mask. */
+#define STM32_USART3SW_PCLK (0U << 18) /**< USART3 clock is PCLK. */
+#define STM32_USART3SW_SYSCLK (1U << 18) /**< USART3 clock is SYSCLK. */
+#define STM32_USART3SW_LSE (2U << 18) /**< USART3 clock is LSE. */
+#define STM32_USART3SW_HSI (3U << 18) /**< USART3 clock is HSI. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief Crystal PLL pre-divider.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV_VALUE 1
+#endif
+
+/**
+ * @brief PLL multiplier value.
+ * @note The allowed range is 2...16.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE 9
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 72MHz system clock from
+ * a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE STM32_ADCPRE_DIV4
+#endif
+
+/**
+ * @brief SDADC prescaler value.
+ */
+#if !defined(STM32_SDPRE) || defined(__DOXYGEN__)
+#define STM32_SDPRE STM32_SDPRE_DIV12
+#endif
+
+/**
+ * @brief USART1 clock source.
+ */
+#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
+#define STM32_USART1SW STM32_USART1SW_PCLK
+#endif
+
+/**
+ * @brief USART2 clock source.
+ */
+#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
+#define STM32_USART2SW STM32_USART2SW_PCLK
+#endif
+
+/**
+ * @brief USART3 clock source.
+ */
+#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
+#define STM32_USART3SW STM32_USART3SW_PCLK
+#endif
+
+/**
+ * @brief I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
+#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
+#endif
+
+/**
+ * @brief I2C2 clock source.
+ */
+#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
+#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
+#endif
+
+/**
+ * @brief RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#endif
+
+/**
+ * @brief USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_REQUIRED TRUE
+#endif
+
+/**
+ * @brief USB prescaler initialization.
+ */
+#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
+#define STM32_USBPRE STM32_USBPRE_DIV1P5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F37x_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F37x_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_HSI
+#error "HSI not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_USART2SW == STM32_USART2SW_HSI
+#error "HSI not enabled, required by STM32_USART2SW"
+#endif
+
+#if STM32_USART3SW == STM32_USART3SW_HSI
+#error "HSI not enabled, required by STM32_USART3SW"
+#endif
+
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#error "HSI not enabled, required by STM32_I2C1SW"
+#endif
+
+#if STM32_I2C2SW == STM32_I2C2SW_HSI
+#error "HSI not enabled, required by STM32_I2C2SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
+#error "STM32_LSECLK not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined"
+#endif
+
+#if (STM32_LSEDRV >> 3) > 3
+#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_LSE
+#error "LSE not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_USART2SW == STM32_USART2SW_LSE
+#error "LSE not enabled, required by STM32_USART2SW"
+#endif
+
+#if STM32_USART3SW == STM32_USART3SW_LSE
+#error "LSE not enabled, required by STM32_USART3SW"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
+ STM32_USB_CLOCK_REQUIRED || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
+#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0)
+#else
+#error "invalid STM32_PREDIV value specified"
+#endif
+
+/**
+ * @brief PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK (STM32_HSECLK / 32)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK 0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief ADC frequency.
+ */
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK (STM32_PCLK2 / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK (STM32_PCLK2 / 4)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
+#define STM32_ADCCLK (STM32_PCLK2 / 6)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
+#define STM32_ADCCLK (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+
+/* ADC maximum frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/* ADC minimum frequency check.*/
+#if STM32_ADCCLK < STM32_ADCCLK_MIN
+#error "STM32_ADCCLK exceeding minimum frequency (STM32_ADCCLK_MIN)"
+#endif
+
+/**
+ * @brief SDADC frequency.
+ */
+#if (STM32_SDPRE == STM32_SDPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 2)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV4) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 4)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV6) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 6)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV8) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 8)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV10) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 10)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV12) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 12)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV14) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 14)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV16) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 16)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV20) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 20)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV24) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 24)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV28) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 28)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV32) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 32)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV36) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 36)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV40) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 40)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV44) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 44)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV48) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK (STM32_SYSCLK / 48)
+#else
+#error "invalid STM32_SDPRE value specified"
+#endif
+
+/* SDADC maximum frequency check.*/
+#if STM32_SDADCCLK > STM32_SDADCCLK_FAST_MAX
+#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_FAST_MAX)"
+#endif
+
+/* SDADC minimum frequency check.*/
+#if STM32_SDADCCLK < STM32_SDADCCLK_MIN
+#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_MIN)"
+#endif
+
+/**
+ * @brief I2C1 frequency.
+ */
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#define STM32_I2C1CLK STM32_HSICLK
+#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
+#define STM32_I2C1CLK STM32_SYSCLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief I2C2 frequency.
+ */
+#if STM32_I2C2SW == STM32_I2C2SW_HSI
+#define STM32_I2C2CLK STM32_HSICLK
+#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
+#define STM32_I2C2CLK STM32_SYSCLK
+#else
+#error "invalid source selected for I2C2 clock"
+#endif
+
+/**
+ * @brief USART1 frequency.
+ */
+#if STM32_USART1SW == STM32_USART1SW_PCLK
+#define STM32_USART1CLK STM32_PCLK2
+#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
+#define STM32_USART1CLK STM32_SYSCLK
+#elif STM32_USART1SW == STM32_USART1SW_LSE
+#define STM32_USART1CLK STM32_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_HSI
+#define STM32_USART1CLK STM32_HSICLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief USART2 frequency.
+ */
+#if STM32_USART2SW == STM32_USART2SW_PCLK
+#define STM32_USART2CLK STM32_PCLK1
+#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
+#define STM32_USART2CLK STM32_SYSCLK
+#elif STM32_USART2SW == STM32_USART2SW_LSE
+#define STM32_USART2CLK STM32_LSECLK
+#elif STM32_USART2SW == STM32_USART2SW_HSI
+#define STM32_USART2CLK STM32_HSICLK
+#else
+#error "invalid source selected for USART2 clock"
+#endif
+
+/**
+ * @brief USART3 frequency.
+ */
+#if STM32_USART3SW == STM32_USART3SW_PCLK
+#define STM32_USART3CLK STM32_PCLK1
+#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
+#define STM32_USART3CLK STM32_SYSCLK
+#elif STM32_USART3SW == STM32_USART3SW_LSE
+#define STM32_USART3CLK STM32_LSECLK
+#elif STM32_USART3SW == STM32_USART3SW_HSI
+#define STM32_USART3CLK STM32_HSICLK
+#else
+#error "invalid source selected for USART3 clock"
+#endif
+
+/**
+ * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14, 18 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Timers 15, 16, 17, 19 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS 0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS 0x00000011
+#else
+#define STM32_FLASHBITS 0x00000012
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_registry.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/platform.mk
new file mode 100644
index 0000000000..fd6083c02b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/platform.mk
@@ -0,0 +1,36 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
+endif
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_isr.h
new file mode 100644
index 0000000000..889590aec2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_isr.h
@@ -0,0 +1,126 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/stm32_isr.h
+ * @brief ISR remapper driver header.
+ *
+ * @addtogroup STM32F37x_ISR
+ * @{
+ */
+
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name ISR names and numbers remapping
+ * @{
+ */
+/*
+ * CAN units.
+ */
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_NUMBER 32
+
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_NUMBER 34
+
+/*
+ * TIM units.
+ */
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM12_HANDLER VectorEC
+#define STM32_TIM14_HANDLER VectorF4
+
+#define STM32_TIM2_NUMBER 28
+#define STM32_TIM3_NUMBER 29
+#define STM32_TIM4_NUMBER 30
+#define STM32_TIM5_NUMBER 50
+#define STM32_TIM6_NUMBER 54
+#define STM32_TIM7_NUMBER 55
+#define STM32_TIM12_NUMBER 43
+#define STM32_TIM14_NUMBER 45
+
+/*
+ * USART units.
+ */
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART3_HANDLER VectorDC
+
+#define STM32_USART1_NUMBER 37
+#define STM32_USART2_NUMBER 38
+#define STM32_USART3_NUMBER 39
+
+/*
+ * USB units.
+ */
+#define STM32_USB1_HP_HANDLER Vector168
+#define STM32_USB1_LP_HANDLER Vector16C
+
+#define STM32_USB1_HP_NUMBER 74
+#define STM32_USB1_LP_NUMBER 75
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#endif /* STM32_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_rcc.h
new file mode 100644
index 0000000000..6d5340e2f5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_rcc.h
@@ -0,0 +1,1063 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/stm32_rcc.h
+ * @brief RCC helper driver header.
+ * @note This file requires definitions from the ST header file
+ * @p stm32f30x.h.
+ *
+ * @addtogroup STM32F37x_RCC
+ * @{
+ */
+
+#ifndef _STM32_RCC_
+#define _STM32_RCC_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1(mask, lp) { \
+ RCC->APB1ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1(mask, lp) { \
+ RCC->APB1ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1(mask) { \
+ RCC->APB1RSTR |= (mask); \
+ RCC->APB1RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) { \
+ RCC->APB2ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask, lp) { \
+ RCC->APB2ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) { \
+ RCC->APB2RSTR |= (mask); \
+ RCC->APB2RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB(mask, lp) { \
+ RCC->AHBENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB(mask, lp) { \
+ RCC->AHBENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB(mask) { \
+ RCC->AHBRSTR |= (mask); \
+ RCC->AHBRSTR = 0; \
+}
+/** @} */
+
+/**
+ * @name ADC1 peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ADC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief Disables the ADC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief Resets the ADC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
+/** @} */
+
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DAC1EN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DAC1EN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DAC1RST)
+
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC2(lp) rccEnableAPB1(RCC_APB1ENR_DAC2EN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC2(lp) rccDisableAPB1(RCC_APB1ENR_DAC2EN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC2() rccResetAPB1(RCC_APB1RSTR_DAC2RST)
+/** @} */
+
+/**
+ * @name CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CAN1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
+
+/**
+ * @brief Disables the CAN1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CANEN, lp)
+
+/**
+ * @brief Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
+/** @} */
+
+/**
+ * @name DMA peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief Disables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
+
+/**
+ * @brief Enables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
+
+/**
+ * @brief Disables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
+
+/**
+ * @brief Resets the DMA2 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
+/** @} */
+
+/**
+ * @name PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
+/** @} */
+
+/**
+ * @name I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Disables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
+
+/**
+ * @brief Enables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Disables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+/** @} */
+
+/**
+ * @name SDADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SDADC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDADC1(lp) rccEnableAPB2(RCC_APB2ENR_SDADC1EN, lp)
+
+/**
+ * @brief Disables the SDADC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSDADC1(lp) rccDisableAPB2(RCC_APB2ENR_SDADC1EN, lp)
+
+/**
+ * @brief Resets the SDADC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSDADC1() rccResetAPB2(RCC_APB2RSTR_SDADC1RST)
+
+/**
+ * @brief Enables the SDADC2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDADC2(lp) rccEnableAPB2(RCC_APB2ENR_SDADC2EN, lp)
+
+/**
+ * @brief Disables the SDADC2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSDADC2(lp) rccDisableAPB2(RCC_APB2ENR_SDADC2EN, lp)
+
+/**
+ * @brief Resets the SDADC2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSDADC2() rccResetAPB2(RCC_APB2RSTR_SDADC2RST)
+
+/**
+ * @brief Enables the SDADC3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDADC3(lp) rccEnableAPB2(RCC_APB2ENR_SDADC3EN, lp)
+
+/**
+ * @brief Disables the SDADC3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSDADC3(lp) rccDisableAPB2(RCC_APB2ENR_SDADC3EN, lp)
+
+/**
+ * @brief Resets the SDADC3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSDADC3() rccResetAPB2(RCC_APB2RSTR_SDADC3RST)
+/** @} */
+
+/**
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Disables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief Enables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Disables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+
+/**
+ * @brief Enables the SPI3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Disables the SPI3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
+/** @} */
+
+/**
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Disables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
+/**
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+
+/**
+ * @brief Enables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief Disables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+
+/**
+ * @brief Enables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
+
+/**
+ * @brief Disables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)
+
+/**
+ * @brief Resets the TIM5 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
+ * @brief Enables the TIM12 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)
+
+/**
+ * @brief Disables the TIM12 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp)
+
+/**
+ * @brief Resets the TIM12 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
+
+/**
+ * @brief Enables the TIM13 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Disables the TIM13 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Resets the TIM13 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
+
+
+/**
+ * @brief Enables the TIM14 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
+
+/**
+ * @brief Disables the TIM14 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp)
+
+/**
+ * @brief Resets the TIM14 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
+
+/**
+ * @brief Enables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Disables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Resets the TIM15 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
+
+/**
+ * @brief Enables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Disables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Resets the TIM16 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
+
+/**
+ * @brief Enables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Disables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Resets the TIM17 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+
+/**
+ * @brief Enables the TIM18 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM18(lp) rccEnableAPB1(RCC_APB1ENR_TIM18EN, lp)
+
+/**
+ * @brief Disables the TIM18 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM18(lp) rccDisableAPB1(RCC_APB1ENR_TIM18EN, lp)
+
+/**
+ * @brief Resets the TIM18 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM18() rccResetAPB1(RCC_APB1RSTR_TIM18RST)
+
+/**
+ * @brief Enables the TIM19 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM19(lp) rccEnableAPB2(RCC_APB2ENR_TIM19EN, lp)
+
+/**
+ * @brief Disables the TIM19 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM19(lp) rccDisableAPB2(RCC_APB2ENR_TIM19EN, lp)
+
+/**
+ * @brief Resets the TIM19 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM19() rccResetAPB2(RCC_APB2RSTR_TIM19RST)
+/** @} */
+
+/**
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Disables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief Enables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Disables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+/** @} */
+
+/**
+ * @name USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_RCC_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_registry.h
new file mode 100644
index 0000000000..90bc9f1452
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F37x/stm32_registry.h
@@ -0,0 +1,542 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F37x/stm32_registry.h
+ * @brief STM32F37x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32F37x capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* STM32F373xC. */
+/*===========================================================================*/
+#if defined(STM32F373xC) || defined(__DOXYGEN__)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 TRUE
+#define STM32_HAS_SDADC2 TRUE
+#define STM32_HAS_SDADC3 TRUE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 TRUE
+#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM18 TRUE
+#define STM32_TIM18_IS_32BITS FALSE
+#define STM32_TIM18_CHANNELS 0
+
+#define STM32_HAS_TIM19 TRUE
+#define STM32_TIM19_IS_32BITS FALSE
+#define STM32_TIM19_CHANNELS 4
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F373xC) */
+
+/*===========================================================================*/
+/* STM32F378xx. */
+/*===========================================================================*/
+#if defined(STM32F378xx) || defined(__DOXYGEN__)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 TRUE
+#define STM32_HAS_SDADC2 TRUE
+#define STM32_HAS_SDADC3 TRUE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 TRUE
+#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM18 TRUE
+#define STM32_TIM18_IS_32BITS FALSE
+#define STM32_TIM18_CHANNELS 0
+
+#define STM32_HAS_TIM19 TRUE
+#define STM32_TIM19_IS_32BITS FALSE
+#define STM32_TIM19_CHANNELS 4
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F378xx) */
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c
similarity index 52%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/ext_lld_isr.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c
index 30a8797af7..605fe82a1a 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/ext_lld_isr.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,19 +15,18 @@
*/
/**
- * @file STM32F30x/ext_lld_isr.c
- * @brief STM32F30x EXT subsystem low level driver ISR code.
+ * @file STM32F3xx/hal_ext_lld_isr.c
+ * @brief STM32F3xx EXT subsystem low level driver ISR code.
*
* @addtogroup EXT
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
-#include "ext_lld_isr.h"
+#include "hal_ext_lld_isr.h"
/*===========================================================================*/
/* Driver local definitions. */
@@ -55,14 +54,18 @@
*
* @isr
*/
-CH_IRQ_HANDLER(Vector58) {
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 0);
- EXTD1.config->channels[0].cb(&EXTD1, 0);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 0);
+ EXTI->PR = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -72,14 +75,18 @@ CH_IRQ_HANDLER(Vector58) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector5C) {
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 1);
- EXTD1.config->channels[1].cb(&EXTD1, 1);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 1);
+ EXTI->PR = pr;
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -89,14 +96,18 @@ CH_IRQ_HANDLER(Vector5C) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector60) {
+OSAL_IRQ_HANDLER(Vector60) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 2);
- EXTD1.config->channels[2].cb(&EXTD1, 2);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 2);
+ EXTI->PR = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -106,14 +117,18 @@ CH_IRQ_HANDLER(Vector60) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector64) {
+OSAL_IRQ_HANDLER(Vector64) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 3);
- EXTD1.config->channels[3].cb(&EXTD1, 3);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 3);
+ EXTI->PR = pr;
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -123,14 +138,18 @@ CH_IRQ_HANDLER(Vector64) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector68) {
+OSAL_IRQ_HANDLER(Vector68) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 4);
- EXTD1.config->channels[4].cb(&EXTD1, 4);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 4);
+ EXTI->PR = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -140,25 +159,27 @@ CH_IRQ_HANDLER(Vector68) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector9C) {
+OSAL_IRQ_HANDLER(Vector9C) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9));
EXTI->PR = pr;
- if (pr & (1 << 5))
+ if (pr & (1U << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
- if (pr & (1 << 6))
+ if (pr & (1U << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
- if (pr & (1 << 7))
+ if (pr & (1U << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
- if (pr & (1 << 8))
+ if (pr & (1U << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
- if (pr & (1 << 9))
+ if (pr & (1U << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -168,28 +189,29 @@ CH_IRQ_HANDLER(Vector9C) {
*
* @isr
*/
-CH_IRQ_HANDLER(VectorE0) {
+OSAL_IRQ_HANDLER(VectorE0) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
- (1 << 15));
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
EXTI->PR = pr;
- if (pr & (1 << 10))
+ if (pr & (1U << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
- if (pr & (1 << 11))
+ if (pr & (1U << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
- if (pr & (1 << 12))
+ if (pr & (1U << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
- if (pr & (1 << 13))
+ if (pr & (1U << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
- if (pr & (1 << 14))
+ if (pr & (1U << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
- if (pr & (1 << 15))
+ if (pr & (1U << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -199,14 +221,18 @@ CH_IRQ_HANDLER(VectorE0) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector44) {
+OSAL_IRQ_HANDLER(Vector44) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 16);
- EXTD1.config->channels[16].cb(&EXTD1, 16);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 16);
+ EXTI->PR = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -216,31 +242,39 @@ CH_IRQ_HANDLER(Vector44) {
*
* @isr
*/
-CH_IRQ_HANDLER(VectorE4) {
+OSAL_IRQ_HANDLER(VectorE4) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 17);
- EXTD1.config->channels[17].cb(&EXTD1, 17);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 17);
+ EXTI->PR = pr;
+ if (pr & (1U << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
-#if !defined(STM32_DISABLE_EXTI18_HANDLER)
+#if !defined(STM32_DISABLE_EXTI18_HANDLER) && STM32_HAS_USB
/**
* @brief EXTI[18] interrupt handler (USB Wakeup).
*
* @isr
*/
-CH_IRQ_HANDLER(VectorE8) {
+OSAL_IRQ_HANDLER(VectorE8) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 18);
- EXTD1.config->channels[18].cb(&EXTD1, 18);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 18);
+ EXTI->PR = pr;
+ if (pr & (1U << 18))
+ EXTD1.config->channels[18].cb(&EXTD1, 18);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -250,14 +284,18 @@ CH_IRQ_HANDLER(VectorE8) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector48) {
+OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 19);
- EXTD1.config->channels[19].cb(&EXTD1, 19);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 19);
+ EXTI->PR = pr;
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -267,14 +305,18 @@ CH_IRQ_HANDLER(Vector48) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector4C) {
+OSAL_IRQ_HANDLER(Vector4C) {
+ uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 20);
- EXTD1.config->channels[20].cb(&EXTD1, 20);
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 20);
+ EXTI->PR = pr;
+ if (pr & (1U << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -284,21 +326,22 @@ CH_IRQ_HANDLER(Vector4C) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector140) {
+OSAL_IRQ_HANDLER(Vector140) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR & ((1 << 21) | (1 << 22) | (1 << 29));
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 21) | (1U << 22) | (1U << 29));
EXTI->PR = pr;
- if (pr & (1 << 21))
+ if (pr & (1U << 21))
EXTD1.config->channels[21].cb(&EXTD1, 21);
- if (pr & (1 << 22))
+ if (pr & (1U << 22))
EXTD1.config->channels[22].cb(&EXTD1, 22);
- if (pr & (1 << 29))
+ if (pr & (1U << 29))
EXTD1.config->channels[29].cb(&EXTD1, 29);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -308,24 +351,25 @@ CH_IRQ_HANDLER(Vector140) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector144) {
+OSAL_IRQ_HANDLER(Vector144) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR & ((1 << 30) | (1 << 31));
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 30) | (1U << 31));
EXTI->PR = pr;
- if (pr & (1 << 30))
+ if (pr & (1U << 30))
EXTD1.config->channels[30].cb(&EXTD1, 30);
- if (pr & (1 << 31))
+ if (pr & (1U << 31))
EXTD1.config->channels[31].cb(&EXTD1, 31);
- pr = EXTI->PR2 & (1 << 0);
+ pr = EXTI->PR2 & EXTI->IMR2 & (1U << 0);
EXTI->PR2 = pr;
- if (pr & (1 << 0))
+ if (pr & (1U << 0))
EXTD1.config->channels[32].cb(&EXTD1, 32);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -335,14 +379,18 @@ CH_IRQ_HANDLER(Vector144) {
*
* @isr
*/
-CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector148) {
+ uint32_t pr2;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
- EXTI->PR2 = (1 << 1);
- EXTD1.config->channels[33].cb(&EXTD1, 33);
+ pr2 = EXTI->PR2;
+ pr2 = EXTI->IMR & (1U << 1);
+ EXTI->PR2 = pr2;
+ if (pr2 & (1U << 1))
+ EXTD1.config->channels[33].cb(&EXTD1, 33);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -357,36 +405,25 @@ CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
*/
void ext_lld_exti_irq_enable(void) {
- nvicEnableVector(EXTI0_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
- nvicEnableVector(EXTI1_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
- nvicEnableVector(EXTI2_TS_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
- nvicEnableVector(EXTI3_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
- nvicEnableVector(EXTI4_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
- nvicEnableVector(EXTI9_5_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
- nvicEnableVector(EXTI15_10_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
- nvicEnableVector(PVD_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
- nvicEnableVector(RTC_Alarm_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
- nvicEnableVector(USBWakeUp_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
- nvicEnableVector(TAMPER_STAMP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
- nvicEnableVector(RTC_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
- nvicEnableVector(COMP1_2_3_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY));
- nvicEnableVector(COMP4_5_6_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI30_32_IRQ_PRIORITY));
- nvicEnableVector(COMP7_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI33_IRQ_PRIORITY));
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+#if STM32_HAS_USB
+ nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+#endif
+ nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+ nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+ nvicEnableVector(COMP1_2_3_IRQn, STM32_EXT_EXTI21_22_29_IRQ_PRIORITY);
+ nvicEnableVector(COMP4_5_6_IRQn, STM32_EXT_EXTI30_32_IRQ_PRIORITY);
+#if STM32_EXTI_NUM_LINES >= 34
+ nvicEnableVector(COMP7_IRQn, STM32_EXT_EXTI33_IRQ_PRIORITY);
+#endif
}
/**
@@ -398,19 +435,23 @@ void ext_lld_exti_irq_disable(void) {
nvicDisableVector(EXTI0_IRQn);
nvicDisableVector(EXTI1_IRQn);
- nvicDisableVector(EXTI2_TS_IRQn);
+ nvicDisableVector(EXTI2_TSC_IRQn);
nvicDisableVector(EXTI3_IRQn);
nvicDisableVector(EXTI4_IRQn);
nvicDisableVector(EXTI9_5_IRQn);
nvicDisableVector(EXTI15_10_IRQn);
nvicDisableVector(PVD_IRQn);
nvicDisableVector(RTC_Alarm_IRQn);
+#if STM32_HAS_USB
nvicDisableVector(USBWakeUp_IRQn);
- nvicDisableVector(TAMPER_STAMP_IRQn);
+#endif
+ nvicDisableVector(TAMP_STAMP_IRQn);
nvicDisableVector(RTC_WKUP_IRQn);
nvicDisableVector(COMP1_2_3_IRQn);
nvicDisableVector(COMP4_5_6_IRQn);
+#if STM32_EXTI_NUM_LINES >= 34
nvicDisableVector(COMP7_IRQn);
+#endif
}
#endif /* HAL_USE_EXT */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h
similarity index 95%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/ext_lld_isr.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h
index 1c88230bb4..a511e7c46a 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/ext_lld_isr.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32F30x/ext_lld_isr.h
- * @brief STM32F30x EXT subsystem low level driver ISR header.
+ * @file STM32F3xx/hal_ext_lld_isr.h
+ * @brief STM32F3xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
-#ifndef _EXT_LLD_ISR_H_
-#define _EXT_LLD_ISR_H_
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
#if HAL_USE_EXT || defined(__DOXYGEN__)
@@ -172,6 +172,6 @@ extern "C" {
#endif /* HAL_USE_EXT */
-#endif /* _EXT_LLD_ISR_H_ */
+#endif /* HAL_EXT_LLD_ISR_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_lld.c
similarity index 88%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/hal_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_lld.c
index 833a1c7937..13b8609ff4 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/hal_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file STM32F30x/hal_lld.c
- * @brief STM32F30x HAL subsystem low level driver source.
+ * @file STM32F3xx/hal_lld.c
+ * @brief STM32F3xx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
-#include "ch.h"
#include "hal.h"
/*===========================================================================*/
@@ -33,6 +32,12 @@
/* Driver exported variables. */
/*===========================================================================*/
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32f3xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -104,17 +109,6 @@ void hal_lld_init(void) {
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
- /* SysTick initialization using the system clock.*/
- SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk |
- SysTick_CTRL_TICKINT_Msk;
-
- /* DWT cycle counter enable.*/
- SCS_DEMCR |= SCS_DEMCR_TRCENA;
- DWT_CTRL |= DWT_CTRL_CYCCNTENA;
-
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
@@ -133,6 +127,11 @@ void hal_lld_init(void) {
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+
+#if STM32_HAS_USB
+ /* USB IRQ relocated to not conflict with CAN.*/
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
+#endif
}
/**
@@ -150,10 +149,18 @@ void stm32_clock_init(void) {
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
+
+ /* HSI is selected as new source without touching the other fields in
+ CFGR. Clearing the register has to be postponed after HSI is the
+ new source.*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
+ RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ ; /* Wait until HSI is selected. */
+
+ /* Registers finally cleared to reset values.*/
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
- while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
- ; /* Waits until HSI is selected. */
#if STM32_HSE_ENABLED
/* HSE activation.*/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_lld.h
similarity index 92%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/hal_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_lld.h
index e367540a53..f2c94d1c57 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/hal_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/hal_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,8 +15,8 @@
*/
/**
- * @file STM32F30x/hal_lld.h
- * @brief STM32F30x HAL subsystem low level driver header.
+ * @file STM32F3xx/hal_lld.h
+ * @brief STM32F3xx HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - STM32_LSECLK.
@@ -26,17 +26,27 @@
* - STM32_HSE_BYPASS (optionally).
* .
* One of the following macros must also be defined:
- * - STM32F30X for Analog & DSP devices.
+ * - STM32F301x8 for Analog & DSP devices.
+ * - STM32F302x8 for Analog & DSP devices.
+ * - STM32F302xC for Analog & DSP devices.
+ * - STM32F302xE for Analog & DSP devices.
+ * - STM32F303x8 for Analog & DSP devices.
+ * - STM32F303xC for Analog & DSP devices.
+ * - STM32F303xE for Analog & DSP devices.
+ * - STM32F318xx for Analog & DSP devices.
+ * - STM32F328xx for Analog & DSP devices.
+ * - STM32F334x8 for Analog & DSP devices.
+ * - STM32F358xx for Analog & DSP devices.
+ * - STM32F398xx for Analog & DSP devices.
* .
*
* @addtogroup HAL
* @{
*/
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
-#include "stm32.h"
#include "stm32_registry.h"
/*===========================================================================*/
@@ -44,15 +54,48 @@
/*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name Platform identification
+ * @name Platform identification macros
* @{
*/
-#define PLATFORM_NAME "STM32F30x Analog & DSP"
+#if defined(STM32F301x8) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32F301x8 Analog & DSP"
+
+#elif defined(STM32F302x8)
+#define PLATFORM_NAME "STM32F302x8 Analog & DSP"
+
+#elif defined(STM32F302xC)
+#define PLATFORM_NAME "STM32F302xC Analog & DSP"
+
+#elif defined(STM32F302xE)
+#define PLATFORM_NAME "STM32F302xE Analog & DSP"
+
+#elif defined(STM32F303x8)
+#define PLATFORM_NAME "STM32F303x8 Analog & DSP"
+
+#elif defined(STM32F303xC)
+#define PLATFORM_NAME "STM32F303xC Analog & DSP"
+
+#elif defined(STM32F303xE)
+#define PLATFORM_NAME "STM32F303xE Analog & DSP"
+
+#elif defined(STM32F318xx)
+#define PLATFORM_NAME "STM32F318xx Analog & DSP"
+
+#elif defined(STM32F328xx)
+#define PLATFORM_NAME "STM32F328xx Analog & DSP"
+
+#elif defined(STM32F334x8)
+#define PLATFORM_NAME "STM32F334x8 Analog & DSP"
+
+#elif defined(STM32F358xx)
+#define PLATFORM_NAME "STM32F358xx Analog & DSP"
+
+#elif defined(STM32F398xx)
+#define PLATFORM_NAME "STM32F398xx Analog & DSP"
+
+#else
+#error "STM32F3xx device not specified"
+#endif
/** @} */
/**
@@ -100,7 +143,7 @@
#define STM32_PLLOUT_MAX 72000000
/**
- * @brief Maximum PLL output clock frequency.
+ * @brief Minimum PLL output clock frequency.
*/
#define STM32_PLLOUT_MIN 16000000
@@ -515,8 +558,8 @@
/*
* Configuration-related checks.
*/
-#if !defined(STM32F30x_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F30x_MCUCONF not defined"
+#if !defined(STM32F3xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F3xx_MCUCONF not defined"
#endif
/*
@@ -557,14 +600,6 @@
#error "HSI not enabled, required by STM32_I2C2SW"
#endif
-#if STM32_TIM1SW == STM32_TIM1SW_HSI
-#error "HSI not enabled, required by STM32_TIM1SW"
-#endif
-
-#if STM32_TIM8SW == STM32_TIM8SW_HSI
-#error "HSI not enabled, required by STM32_TIM8SW"
-#endif
-
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
#endif
@@ -874,7 +909,7 @@
/**
* @brief ADC34 frequency.
*/
-#if (STM32_ADC43PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__)
+#if (STM32_ADC34PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__)
#define STM32_ADC34CLK 0
#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV1
#define STM32_ADC34CLK (STM32_PLLCLKOUT / 1)
@@ -943,9 +978,9 @@
#define STM32_USART1CLK STM32_PCLK2
#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
#define STM32_USART1CLK STM32_SYSCLK
-#elif STM32_USART1SW == STM32_USART1SW_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_LSE
#define STM32_USART1CLK STM32_LSECLK
-#elif STM32_USART1SW == STM32_USART1SW_HSICLK
+#elif STM32_USART1SW == STM32_USART1SW_HSI
#define STM32_USART1CLK STM32_HSICLK
#else
#error "invalid source selected for USART1 clock"
@@ -958,9 +993,9 @@
#define STM32_USART2CLK STM32_PCLK1
#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
#define STM32_USART2CLK STM32_SYSCLK
-#elif STM32_USART2SW == STM32_USART2SW_LSECLK
+#elif STM32_USART2SW == STM32_USART2SW_LSE
#define STM32_USART2CLK STM32_LSECLK
-#elif STM32_USART2SW == STM32_USART2SW_HSICLK
+#elif STM32_USART2SW == STM32_USART2SW_HSI
#define STM32_USART2CLK STM32_HSICLK
#else
#error "invalid source selected for USART2 clock"
@@ -973,9 +1008,9 @@
#define STM32_USART3CLK STM32_PCLK1
#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
#define STM32_USART3CLK STM32_SYSCLK
-#elif STM32_USART3SW == STM32_USART3SW_LSECLK
+#elif STM32_USART3SW == STM32_USART3SW_LSE
#define STM32_USART3CLK STM32_LSECLK
-#elif STM32_USART3SW == STM32_USART3SW_HSICLK
+#elif STM32_USART3SW == STM32_USART3SW_HSI
#define STM32_USART3CLK STM32_HSICLK
#else
#error "invalid source selected for USART3 clock"
@@ -988,9 +1023,9 @@
#define STM32_UART4CLK STM32_PCLK1
#elif STM32_UART4SW == STM32_UART4SW_SYSCLK
#define STM32_UART4CLK STM32_SYSCLK
-#elif STM32_UART4SW == STM32_UART4SW_LSECLK
+#elif STM32_UART4SW == STM32_UART4SW_LSE
#define STM32_UART4CLK STM32_LSECLK
-#elif STM32_UART4SW == STM32_UART4SW_HSICLK
+#elif STM32_UART4SW == STM32_UART4SW_HSI
#define STM32_UART4CLK STM32_HSICLK
#else
#error "invalid source selected for UART4 clock"
@@ -1003,9 +1038,9 @@
#define STM32_UART5CLK STM32_PCLK1
#elif STM32_UART5SW == STM32_UART5SW_SYSCLK
#define STM32_UART5CLK STM32_SYSCLK
-#elif STM32_UART5SW == STM32_UART5SW_LSECLK
+#elif STM32_UART5SW == STM32_UART5SW_LSE
#define STM32_UART5CLK STM32_LSECLK
-#elif STM32_UART5SW == STM32_UART5SW_HSICLK
+#elif STM32_UART5SW == STM32_UART5SW_HSI
#define STM32_UART5CLK STM32_HSICLK
#else
#error "invalid source selected for UART5 clock"
@@ -1015,7 +1050,11 @@
* @brief TIM1 frequency.
*/
#if STM32_TIM1SW == STM32_TIM1SW_PCLK2
+#if STM32_PPRE2 == STM32_PPRE2_DIV1
#define STM32_TIM1CLK STM32_PCLK2
+#else
+#define STM32_TIM1CLK (STM32_PCLK2 * 2)
+#endif
#elif STM32_TIM1SW == STM32_TIM1SW_PLLX2
#if (STM32_SW != STM32_SW_PLL) || \
@@ -1033,7 +1072,11 @@
* @brief TIM8 frequency.
*/
#if STM32_TIM8SW == STM32_TIM8SW_PCLK2
+#if STM32_PPRE2 == STM32_PPRE2_DIV1
#define STM32_TIM8CLK STM32_PCLK2
+#else
+#define STM32_TIM8CLK (STM32_PCLK2 * 2)
+#endif
#elif STM32_TIM8SW == STM32_TIM8SW_PLLX2
#if (STM32_SW != STM32_SW_PLL) || \
@@ -1091,48 +1134,16 @@
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() DWT_CYCCNT
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() STM32_HCLK
-
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-/* STM32 ISR, DMA and RCC helpers.*/
+/* Various helpers.*/
+#include "nvic.h"
#include "stm32_isr.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"
@@ -1146,6 +1157,6 @@ extern "C" {
}
#endif
-#endif /* _HAL_LLD_H_ */
+#endif /* HAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/platform.mk
new file mode 100644
index 0000000000..c4ff9849ae
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/platform.mk
@@ -0,0 +1,33 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
similarity index 92%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_isr.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
index 7306a3f8ae..d4b20482db 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_isr.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32F30x/stm32_isr.h
+ * @file STM32F3xx/stm32_isr.h
* @brief ISR remapper driver header.
*
- * @addtogroup STM32F30x_ISR
+ * @addtogroup STM32F3xx_ISR
* @{
*/
-#ifndef _STM32_ISR_H_
-#define _STM32_ISR_H_
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
@@ -59,6 +59,11 @@
#define STM32_I2C2_EVENT_NUMBER 33
#define STM32_I2C2_ERROR_NUMBER 34
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_NUMBER 73
+
/*
* TIM units.
*/
@@ -127,6 +132,6 @@
/* External declarations. */
/*===========================================================================*/
-#endif /* _STM32_ISR_H_ */
+#endif /* STM32_ISR_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
new file mode 100644
index 0000000000..d3c5bc24a2
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
@@ -0,0 +1,1037 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F3xx/stm32_rcc.h
+ * @brief RCC helper driver header.
+ * @note This file requires definitions from the ST header file
+ * @p stm32f30x.h.
+ *
+ * @addtogroup STM32F3xx_RCC
+ * @{
+ */
+
+#ifndef _STM32_RCC_
+#define _STM32_RCC_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1(mask, lp) { \
+ RCC->APB1ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1(mask, lp) { \
+ RCC->APB1ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1(mask) { \
+ RCC->APB1RSTR |= (mask); \
+ RCC->APB1RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) { \
+ RCC->APB2ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask, lp) { \
+ RCC->APB2ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) { \
+ RCC->APB2RSTR |= (mask); \
+ RCC->APB2RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB(mask, lp) { \
+ RCC->AHBENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB(mask, lp) { \
+ RCC->AHBENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB(mask) { \
+ RCC->AHBRSTR |= (mask); \
+ RCC->AHBRSTR = 0; \
+}
+/** @} */
+
+/**
+ * @name ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ADC1/ADC2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#if defined(RCC_AHBENR_ADC12EN) || defined(__DOXYGEN__)
+#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
+#else
+#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC1EN, lp)
+#endif
+
+/**
+ * @brief Disables the ADC1/ADC2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#if defined(RCC_AHBENR_ADC12EN) || defined(__DOXYGEN__)
+#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
+#else
+#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC1EN, lp)
+#endif
+
+/**
+ * @brief Resets the ADC1/ADC2 peripheral.
+ *
+ * @api
+ */
+#if defined(RCC_AHBRSTR_ADC12RST) || defined(__DOXYGEN__)
+#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
+#else
+#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC1RST)
+#endif
+
+/**
+ * @brief Enables the ADC3/ADC4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#if defined(RCC_AHBENR_ADC34EN) || defined(__DOXYGEN__)
+#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
+#else
+#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC3EN, lp)
+#endif
+
+/**
+ * @brief Disables the ADC3/ADC4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#if defined(RCC_AHBENR_ADC34EN) || defined(__DOXYGEN__)
+#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
+#else
+#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC3EN, lp)
+#endif
+
+/**
+ * @brief Resets the ADC3/ADC4 peripheral.
+ *
+ * @api
+ */
+#if defined(RCC_AHBRSTR_ADC34RST) || defined(__DOXYGEN__)
+#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
+#else
+#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC3RST)
+#endif
+/** @} */
+
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DAC1EN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DAC1EN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DAC1RST)
+
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC2(lp) rccEnableAPB1(RCC_APB1ENR_DAC2EN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC2(lp) rccDisableAPB1(RCC_APB1ENR_DAC2EN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC2() rccResetAPB1(RCC_APB1RSTR_DAC2RST)
+/** @} */
+
+/**
+ * @name CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CAN1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
+
+/**
+ * @brief Disables the CAN1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CANEN, lp)
+
+/**
+ * @brief Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
+/** @} */
+
+/**
+ * @name DMA peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief Disables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
+
+/**
+ * @brief Enables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
+
+/**
+ * @brief Disables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
+
+/**
+ * @brief Resets the DMA2 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
+/** @} */
+
+/**
+ * @name PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
+/** @} */
+
+/**
+ * @name I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Disables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
+
+/**
+ * @brief Enables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Disables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+/** @} */
+
+/**
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Disables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief Enables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Disables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+
+/**
+ * @brief Enables the SPI3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Disables the SPI3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
+/** @} */
+
+/**
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Disables the TIM1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
+/**
+ * @brief Enables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Disables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
+/**
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+
+/**
+ * @brief Enables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief Disables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
+ * @brief Enables the TIM8 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Disables the TIM8 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
+
+/**
+ * @brief Enables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Disables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Resets the TIM15 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
+
+/**
+ * @brief Enables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Disables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Resets the TIM16 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
+
+/**
+ * @brief Enables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Disables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Resets the TIM17 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+
+/**
+ * @brief Enables the TIM20 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM20(lp) rccEnableAPB2(RCC_APB2ENR_TIM20EN, lp)
+
+/**
+ * @brief Disables the TIM20 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM20(lp) rccDisableAPB2(RCC_APB2ENR_TIM20EN, lp)
+
+/**
+ * @brief Resets the TIM20 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM20() rccResetAPB2(RCC_APB2RSTR_TIM20RST)
+/** @} */
+
+/**
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Disables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief Enables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Disables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
+/** @} */
+
+/**
+ * @name USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+/** @} */
+
+/**
+ * @name FSMC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the FMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableFSMC(lp) rccEnableAHB(RCC_AHBENR_FMCEN, lp)
+
+/**
+ * @brief Disables the FMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableFSMC(lp) rccDisableAHB(RCC_AHBENR_FMCEN, lp)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_RCC_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
new file mode 100644
index 0000000000..653e4556da
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
@@ -0,0 +1,2907 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F3xx/stm32_registry.h
+ * @brief STM32F3xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+/**
+ * @brief Sub-family identifier.
+ */
+#if !defined(STM32F3XX) || defined(__DOXYGEN__)
+#define STM32F3XX
+#endif
+
+/*===========================================================================*/
+/* Common features. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32F3xx capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* STM32F303xC. */
+/*===========================================================================*/
+#if defined(STM32F303xC) || defined(__DOXYGEN__)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC4 TRUE
+#define STM32_ADC4_HANDLER Vector134
+#define STM32_ADC4_NUMBER 61
+#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC4_DMA_CHN 0x00000000
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN)
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F303xC) */
+
+/*===========================================================================*/
+/* STM32F303xE. */
+/*===========================================================================*/
+#if defined(STM32F303xE)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC4 TRUE
+#define STM32_ADC4_HANDLER Vector134
+#define STM32_ADC4_NUMBER 61
+#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC4_DMA_CHN 0x00000000
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM20 TRUE
+#define STM32_TIM20_IS_32BITS FALSE
+#define STM32_TIM20_CHANNELS 6
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F303xE) */
+
+/*===========================================================================*/
+/* STM32F303x8. */
+/*===========================================================================*/
+#if defined(STM32F303x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_DAC2_CH1 TRUE
+#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 33
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F303x8) */
+
+/*===========================================================================*/
+/* STM32F301x8. */
+/*===========================================================================*/
+#if defined(STM32F301x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 33
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI1 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F301x8) */
+
+/*===========================================================================*/
+/* STM32F302x8. */
+/*===========================================================================*/
+#if defined(STM32F302x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 33
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI1 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F302x8) */
+
+/*===========================================================================*/
+/* STM32F302xC. */
+/*===========================================================================*/
+#if defined(STM32F302xC)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F302xC) */
+
+/*===========================================================================*/
+/* STM32F302xE. */
+/*===========================================================================*/
+#if defined(STM32F302xE)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F302xE) */
+
+/*===========================================================================*/
+/* STM32F318x8. */
+/*===========================================================================*/
+#if defined(STM32F318x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 33
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI1 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F318x8) */
+
+/*===========================================================================*/
+/* STM32F328x8. */
+/*===========================================================================*/
+#if defined(STM32F328x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_DAC2_CH1 TRUE
+#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 33
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F328x8) */
+
+/*===========================================================================*/
+/* STM32F358xC. */
+/*===========================================================================*/
+#if defined(STM32F358xC)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F358xC) */
+
+/*===========================================================================*/
+/* STM32F334x8. */
+/*===========================================================================*/
+#if defined(STM32F334x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_DAC2_CH1 TRUE
+#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 0
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 33
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F334x8) */
+
+/*===========================================================================*/
+/* STM32F398xx. */
+/*===========================================================================*/
+#if defined(STM32F398xx)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC4 TRUE
+#define STM32_ADC4_HANDLER Vector134
+#define STM32_ADC4_NUMBER 61
+#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC4_DMA_CHN 0x00000000
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM20 TRUE
+#define STM32_TIM20_IS_32BITS FALSE
+#define STM32_TIM20_CHANNELS 6
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F398xx) */
+
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c
new file mode 100644
index 0000000000..26daa88a54
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c
@@ -0,0 +1,411 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F4xx/hal_ext_lld_isr.c
+ * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "hal_ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 0);
+ EXTI->PR = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 1);
+ EXTI->PR = pr;
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 2);
+ EXTI->PR = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 3);
+ EXTI->PR = pr;
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 4);
+ EXTI->PR = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9));
+ EXTI->PR = pr;
+ if (pr & (1U << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1U << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1U << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1U << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1U << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
+ EXTI->PR = pr;
+ if (pr & (1U << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1U << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1U << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1U << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1U << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1U << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 16);
+ EXTI->PR = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[17] interrupt handler (RTC_ALARM).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 17);
+ EXTI->PR = pr;
+ if (pr & (1U << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE8) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 18);
+ EXTI->PR = pr;
+ if (pr & (1U << 18))
+ EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if STM32_HAS_ETH || defined(__DOXYGEN__)
+/**
+ * @brief EXTI[19] interrupt handler (ETH_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector138) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 19);
+ EXTI->PR = pr;
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_HAS_ETH */
+
+#if STM32_HAS_OTG2 || defined(__DOXYGEN__)
+/**
+ * @brief EXTI[20] interrupt handler (OTG_HS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector170) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 20);
+ EXTI->PR = pr;
+ if (pr & (1U << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_HAS_OTG2 */
+
+#if !defined(STM32F401xx)
+/**
+ * @brief EXTI[21] interrupt handler (TAMPER_STAMP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 21);
+ EXTI->PR = pr;
+ if (pr & (1U << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* !defined(STM32F401xx) */
+
+/**
+ * @brief EXTI[22] interrupt handler (RTC_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 22);
+ EXTI->PR = pr;
+ if (pr & (1U << 22))
+ EXTD1.config->channels[22].cb(&EXTD1, 22);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+#if STM32_HAS_OTG1
+ nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+#endif
+#if STM32_HAS_ETH
+ nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+#endif
+#if STM32_HAS_OTG2
+ nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+#endif
+#if !defined(STM32F401xx)
+ nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY);
+#endif /* !defined(STM32F401xx) */
+ nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY);
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(EXTI0_IRQn);
+ nvicDisableVector(EXTI1_IRQn);
+ nvicDisableVector(EXTI2_IRQn);
+ nvicDisableVector(EXTI3_IRQn);
+ nvicDisableVector(EXTI4_IRQn);
+ nvicDisableVector(EXTI9_5_IRQn);
+ nvicDisableVector(EXTI15_10_IRQn);
+ nvicDisableVector(PVD_IRQn);
+ nvicDisableVector(RTC_Alarm_IRQn);
+#if STM32_HAS_OTG1
+ nvicDisableVector(OTG_FS_WKUP_IRQn);
+#endif
+#if STM32_HAS_ETH
+ nvicDisableVector(ETH_WKUP_IRQn);
+#endif
+#if STM32_HAS_OTG2
+ nvicDisableVector(OTG_HS_WKUP_IRQn);
+#endif
+#if !defined(STM32F401xx)
+ nvicDisableVector(TAMP_STAMP_IRQn);
+#endif /* !defined(STM32F401xx) */
+ nvicDisableVector(RTC_WKUP_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.h
similarity index 96%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/ext_lld_isr.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.h
index d961d32079..11206dee43 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/ext_lld_isr.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,15 +15,15 @@
*/
/**
- * @file STM32F4xx/ext_lld_isr.h
+ * @file STM32F4xx/hal_ext_lld_isr.h
* @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
-#ifndef _EXT_LLD_ISR_H_
-#define _EXT_LLD_ISR_H_
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
#if HAL_USE_EXT || defined(__DOXYGEN__)
@@ -165,6 +165,6 @@ extern "C" {
#endif /* HAL_USE_EXT */
-#endif /* _EXT_LLD_ISR_H_ */
+#endif /* HAL_EXT_LLD_ISR_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_lld.c
similarity index 75%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/hal_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 8eefa30d7a..1eaee434e7 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,9 +22,6 @@
* @{
*/
-/* TODO: LSEBYP like in F3.*/
-
-#include "ch.h"
#include "hal.h"
/*===========================================================================*/
@@ -35,6 +32,12 @@
/* Driver exported variables. */
/*===========================================================================*/
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32f4xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -111,23 +114,15 @@ static void hal_lld_backup_domain_init(void) {
void hal_lld_init(void) {
/* Reset of all peripherals. AHB3 is not reseted because it could have
- been initialized in the board initialization file (board.c).*/
+ been initialized in the board initialization file (board.c) and AHB2 is not
+ present in STM32F410. */
rccResetAHB1(~0);
+#if !defined(STM32F410xx)
rccResetAHB2(~0);
+#endif
rccResetAPB1(~RCC_APB1RSTR_PWRRST);
rccResetAPB2(~0);
- /* SysTick initialization using the system clock.*/
- SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk |
- SysTick_CTRL_TICKINT_Msk;
-
- /* DWT cycle counter enable.*/
- SCS_DEMCR |= SCS_DEMCR_TRCENA;
- DWT_CTRL |= DWT_CTRL_CYCCNTENA;
-
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
@@ -155,7 +150,11 @@ void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
+#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCAPBEN)
+ RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCAPBEN;
+#else
RCC->APB1ENR = RCC_APB1ENR_PWREN;
+#endif
/* PWR initialization.*/
#if defined(STM32F4XX) || defined(__DOXYGEN__)
@@ -169,11 +168,19 @@ void stm32_clock_init(void) {
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
- RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
- RCC->CFGR = 0; /* CFGR reset value. */
+
+ /* HSI is selected as new source without touching the other fields in
+ CFGR. Clearing the register has to be postponed after HSI is the
+ new source.*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
+ RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
- ; /* Waits until HSI is selected. */
+ ; /* Wait until HSI is selected. */
+ /* Registers finally cleared to reset values.*/
+ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+ RCC->CFGR = 0; /* CFGR reset value. */
+
#if STM32_HSE_ENABLED
/* HSE activation.*/
#if defined(STM32_HSE_BYPASS)
@@ -220,42 +227,73 @@ void stm32_clock_init(void) {
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLRDY))
;
-#endif /* STM32_OVERDRIVE_REQUIRED */
-
-#if STM32_CLOCK48_PLLSAI && defined(STM32F446xx)
- /* Configure 48MHz clock for USB */
- // Set 48MHz clock source
- RCC_48MHzClockSourceConfig(RCC_48MHZCLKSource_PLLSAI);
- // Enable PLLSAI
- RCC_PLLSAICmd(DISABLE);
- #define RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
- // wait for PLLSAI to be disabled
- while (RCC_PLLSAI_GET_FLAG() != 0)
- {}
- RCC_PLLSAIConfig(STM32_PLLSAI_M_VALUE, STM32_PLLSAI_N_VALUE, STM32_PLLSAI_P_VALUE, STM32_PLLSAI_Q_VALUE);
- RCC_PLLSAICmd(ENABLE);
- // wait for PLLSAI to be enabled
- while (RCC_PLLSAI_GET_FLAG() == 0)
- {}
-#endif /* STM32_CLOCK48_PLLSAI && defined(STM32F446xx) */
-
+#endif /* STM32_ACTIVATE_PLL */
#if STM32_ACTIVATE_PLLI2S
/* PLLI2S activation.*/
- RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
+ RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
+ STM32_PLLI2SQ | STM32_PLLI2SM;
RCC->CR |= RCC_CR_PLLI2SON;
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLI2SRDY))
;
-#endif
+#endif /* STM32_ACTIVATE_PLLI2S */
+
+#if STM32_ACTIVATE_PLLSAI
+ /* PLLSAI activation.*/
+ RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP |
+ STM32_PLLSAIQ | STM32_PLLSAIM;
+ RCC->CR |= RCC_CR_PLLSAION;
+
+ /* Waiting for PLL lock.*/
+ while (!(RCC->CR & RCC_CR_PLLSAIRDY))
+ ;
+#endif /* STM32_ACTIVATE_PLLSAI */
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
- STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+ STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
+ STM32_HPRE;
+
+#if defined(STM32F446xx)
+ /* DCKCFGR register initialization, note, must take care of the _OFF
+ pseudo settings.*/
+ {
+ uint32_t dckcfgr = 0;
+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+ dckcfgr |= STM32_SAI2SEL;
+#endif
+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+ dckcfgr |= STM32_SAI1SEL;
+#endif
+#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
+ dckcfgr |= STM32_PLLSAIDIVR;
+#endif
+ RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;
+ }
+ RCC->DCKCFGR2 = STM32_CK48MSEL;
+#elif defined(STM32F469xx) || defined(STM32F479xx)
+ /* DCKCFGR register initialization, note, must take care of the _OFF
+ pseudo settings.*/
+ {
+ uint32_t dckcfgr = 0;
+ #if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+ dckcfgr |= STM32_SAI2SEL;
+ #endif
+ #if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+ dckcfgr |= STM32_SAI1SEL;
+ #endif
+ #if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
+ dckcfgr |= STM32_PLLSAIDIVR;
+ #endif
+ RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ |
+ STM32_CK48MSEL;
+ }
+#endif
/* Flash setup.*/
-#if defined(STM32_USE_REVISION_A_FIX)
+#if !defined(STM32_REMOVE_REVISION_A_FIX)
/* Some old revisions of F4x MCUs randomly crashes with compiler
optimizations enabled AND flash caches enabled. */
if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
@@ -268,7 +306,7 @@ void stm32_clock_init(void) {
FLASH_ACR_DCEN | STM32_FLASHBITS;
#endif
- /* Switching to the configured clock source if it is different from MSI.*/
+ /* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_lld.h
similarity index 62%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/hal_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index 122a8853b5..21b9c6471b 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -26,21 +26,24 @@
* - STM32_VDD (as hundredths of Volt).
* .
* One of the following macros must also be defined:
- * - STM32F2XX for High-performance STM32 F-2 devices.
- * - STM32F401xx for High-performance STM32 F-4 devices.
- * - STM32F40_41xxx for High-performance STM32 F-4 devices.
- * - STM32F427_437xx for High-performance STM32 F-4 devices.
- * - STM32F429_439xx for High-performance STM32 F-4 devices.
+ * - STM32F2XX for High-performance STM32F2 devices.
+ * - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx,
+ * STM32F446xx for High-performance STM32F4 devices of
+ * Foundation line.
+ * - STM32F401xC, STM32F401xE, STM32F410Cx, STM32F410Rx, STM32F411xE
+ * for High-performance STM32F4 devices of Access line.
+ * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx,
+ * STM32F479xx for High-performance STM32F4 devices of Advanced line.
* .
*
* @addtogroup HAL
* @{
*/
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
-#include "stm32.h"
+#include "stm32_registry.h"
/*===========================================================================*/
/* Driver constants. */
@@ -49,34 +52,68 @@
/**
* @brief Defines the support for realtime counters in the HAL.
*/
-#define HAL_IMPLEMENTS_COUNTERS TRUE
+#define HAL_IMPLEMENTS_COUNTERS TRUE
/**
* @name Platform identification macros
* @{
*/
-#if defined(STM32F429_439xx) || defined(__DOXYGEN__)
-#define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU"
-#define STM32F4XX
+#if defined(STM32F205xx) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32F205 High Performance"
-#elif defined(STM32F427_437xx)
-#define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU"
-#define STM32F4XX
+#elif defined(STM32F207xx)
+#define PLATFORM_NAME "STM32F207 High Performance"
-#elif defined(STM32F40_41xxx)
-#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU"
-#define STM32F4XX
+#elif defined(STM32F215xx)
+#define PLATFORM_NAME "STM32F215 High Performance"
+
+#elif defined(STM32F217xx)
+#define PLATFORM_NAME "STM32F217 High Performance"
#elif defined(STM32F401xx)
#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
-#define STM32F4XX
+
+#elif defined(STM32F405xx)
+#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU"
+
+#elif defined(STM32F407xx)
+#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU"
+
+#elif defined(STM32F410xx)
+#define PLATFORM_NAME "STM32F410 High Performance with DSP and FPU"
+
+#elif defined(STM32F411xx)
+#define PLATFORM_NAME "STM32F411 High Performance with DSP and FPU"
+
+#elif defined(STM32F412xx)
+#define PLATFORM_NAME "STM32F412 High Performance with DSP and FPU"
+
+#elif defined(STM32F415xx)
+#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU"
+
+#elif defined(STM32F417xx)
+#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU"
+
+#elif defined(STM32F427xx)
+#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU"
+
+#elif defined(STM32F429xx)
+#define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU"
+
+#elif defined(STM32F437xx)
+#define PLATFORM_NAME "STM32F437 High Performance with DSP and FPU"
+
+#elif defined(STM32F439xx)
+#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU"
#elif defined(STM32F446xx)
#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU"
-#define STM32F4XX
-#elif defined(STM32F2XX)
-#define PLATFORM_NAME "STM32F2xx High Performance"
+#elif defined(STM32F469xx)
+#define PLATFORM_NAME "STM32F469 High Performance with DSP and FPU"
+
+#elif defined(STM32F479xx)
+#define PLATFORM_NAME "STM32F479 High Performance with DSP and FPU"
#else
#error "STM32F2xx/F4xx device not specified"
@@ -87,12 +124,9 @@
* @name Absolute Maximum Ratings
* @{
*/
-/**
- * @name Absolute Maximum Ratings
- * @{
- */
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || \
- defined(__DOXYGEN__)
+#if defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(__DOXYGEN__)
/**
* @brief Absolute maximum system clock.
*/
@@ -149,7 +183,7 @@
#define STM32_PLLVCO_MAX 432000000
/**
- * @brief Maximum PLLs VCO clock frequency.
+ * @brief Minimum PLLs VCO clock frequency.
*/
#define STM32_PLLVCO_MIN 192000000
@@ -163,10 +197,20 @@
*/
#define STM32_PLLOUT_MIN 24000000
+/**
+ * @brief Maximum PLLI2S output clock frequency.
+ */
+#define STM32_PLLI2SOUT_MAX 216000000
+
+/**
+ * @brief Maximum PLLSAI output clock frequency.
+ */
+#define STM32_PLLSAIOUT_MAX 216000000
+
/**
* @brief Maximum APB1 clock frequency.
*/
-#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4)
+#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
/**
* @brief Maximum APB2 clock frequency.
@@ -177,9 +221,9 @@
* @brief Maximum SPI/I2S clock frequency.
*/
#define STM32_SPII2S_MAX 45000000
-#endif /* STM32F40_41xxx */
+#endif
-#if defined(STM32F40_41xxx) || defined(__DOXYGEN__)
+#if defined(STM32F40_41xxx)
#define STM32_SYSCLK_MAX 168000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
@@ -197,9 +241,9 @@
#define STM32_PCLK1_MAX 42000000
#define STM32_PCLK2_MAX 84000000
#define STM32_SPII2S_MAX 42000000
-#endif /* STM32F40_41xxx */
+#endif
-#if defined(STM32F401xx) || defined(__DOXYGEN__)
+#if defined(STM32F401xx)
#define STM32_SYSCLK_MAX 84000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
@@ -217,9 +261,30 @@
#define STM32_PCLK1_MAX 42000000
#define STM32_PCLK2_MAX 84000000
#define STM32_SPII2S_MAX 42000000
-#endif /* STM32F40_41xxx */
+#endif
+
+#if defined(STM32F410xx) || defined(STM32F411xx) || \
+ defined(STM32F412xx)
+#define STM32_SYSCLK_MAX 100000000
+#define STM32_HSECLK_MAX 26000000
+#define STM32_HSECLK_BYP_MAX 50000000
+#define STM32_HSECLK_MIN 4000000
+#define STM32_HSECLK_BYP_MIN 1000000
+#define STM32_LSECLK_MAX 32768
+#define STM32_LSECLK_BYP_MAX 1000000
+#define STM32_LSECLK_MIN 32768
+#define STM32_PLLIN_MAX 2100000
+#define STM32_PLLIN_MIN 950000
+#define STM32_PLLVCO_MAX 432000000
+#define STM32_PLLVCO_MIN 100000000
+#define STM32_PLLOUT_MAX 100000000
+#define STM32_PLLOUT_MIN 24000000
+#define STM32_PCLK1_MAX 50000000
+#define STM32_PCLK2_MAX 100000000
+#define STM32_SPII2S_MAX 50000000
+#endif
-#if defined(STM32F446xx) || defined(__DOXYGEN__)
+#if defined(STM32F446xx)
#define STM32_SYSCLK_MAX 180000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
@@ -231,13 +296,15 @@
#define STM32_PLLIN_MAX 2100000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 192000000
+#define STM32_PLLVCO_MIN 100000000
#define STM32_PLLOUT_MAX 180000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 45000000
-#define STM32_PCLK2_MAX 90000000
+#define STM32_PLLOUT_MIN 12500000
+#define STM32_PLLI2SOUT_MAX 216000000
+#define STM32_PLLSAIOUT_MAX 216000000
+#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
+#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
#define STM32_SPII2S_MAX 45000000
-#endif /* STM32F446xx */
+#endif
#if defined(STM32F2XX)
#define STM32_SYSCLK_MAX 120000000
@@ -257,7 +324,7 @@
#define STM32_PCLK1_MAX 30000000
#define STM32_PCLK2_MAX 60000000
#define STM32_SPII2S_MAX 30000000
-#endif /* defined(STM32F2XX) */
+#endif
/** @} */
/**
@@ -272,9 +339,9 @@
* @name PWR_CR register bits definitions
* @{
*/
-#define STM32_VOS_SCALE3 (PWR_CR_VOS_0)
-#define STM32_VOS_SCALE2 (PWR_CR_VOS_1)
-#define STM32_VOS_SCALE1 (PWR_CR_VOS_1 | PWR_CR_VOS_0)
+#define STM32_VOS_SCALE3 0x00004000
+#define STM32_VOS_SCALE2 0x00008000
+#define STM32_VOS_SCALE1 0x0000C000
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
@@ -290,11 +357,11 @@
* @name RCC_PLLCFGR register bits definitions
* @{
*/
-#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
-#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
-#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
-#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
-#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
+#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
+#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
+#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
+#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
+#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
@@ -320,14 +387,14 @@
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
-#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
+#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
-#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
+#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
@@ -360,26 +427,42 @@
#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
-#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */
-#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */
-#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */
-#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */
-#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */
-
-#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */
-#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */
-#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */
-#define STM32_RTC_HSE (3 << 8) /**< HSE divided by programmable
- prescaler used as RTC clock*/
+#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
+#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
+#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
+#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
+#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
/**
* @name RCC_PLLI2SCFGR register bits definitions
* @{
*/
+#define STM32_PLLI2SM_MASK (31 << 0) /**< PLLI2SM mask. */
#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
+#define STM32_PLLI2SP_MASK (3 << 16) /**< PLLI2SP mask. */
+#define STM32_PLLI2SP_DIV2 (0 << 16) /**< PLLI2S clock divided by 2. */
+#define STM32_PLLI2SP_DIV4 (1 << 16) /**< PLLI2S clock divided by 4. */
+#define STM32_PLLI2SP_DIV6 (2 << 16) /**< PLLI2S clock divided by 6. */
+#define STM32_PLLI2SP_DIV8 (3 << 16) /**< PLLI2S clock divided by 8. */
+#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
/** @} */
+/**
+ * @name RCC_PLLSAICFGR register bits definitions
+ * @{
+ */
+#define STM32_PLLSAIM_MASK (31 << 0) /**< PLLSAIM mask. */
+#define STM32_PLLSAIN_MASK (511 << 6) /**< PLLSAIN mask. */
+#define STM32_PLLSAIP_MASK (3 << 16) /**< PLLSAIP mask. */
+#define STM32_PLLSAIP_DIV2 (0 << 16) /**< PLLSAI clock divided by 2. */
+#define STM32_PLLSAIP_DIV4 (1 << 16) /**< PLLSAI clock divided by 4. */
+#define STM32_PLLSAIP_DIV6 (2 << 16) /**< PLLSAI clock divided by 6. */
+#define STM32_PLLSAIP_DIV8 (3 << 16) /**< PLLSAI clock divided by 8. */
+#define STM32_PLLSAIQ_MASK (15 << 24) /**< PLLSAIQ mask. */
+#define STM32_PLLSAIR_MASK (7 << 28) /**< PLLSAIR mask. */
+/** @} */
+
/**
* @name RCC_BDCR register bits definitions
* @{
@@ -391,358 +474,78 @@
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
/** @} */
-/*===========================================================================*/
-/* Platform capabilities. */
-/*===========================================================================*/
-
/**
- * @name STM32F4xx capabilities
+ * @name RCC_DCKCFGR register bits definitions
* @{
*/
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 TRUE
-#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN 0x00001100
-
-#define STM32_HAS_ADC3 TRUE
-#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \
- STM32_DMA_STREAM_ID_MSK(2, 1))
-#define STM32_ADC3_DMA_CHN 0x00000022
-
-#define STM32_HAS_ADC4 FALSE
-#define STM32_ADC4_DMA_MSK 0x00000000
-#define STM32_ADC4_DMA_CHN 0x00000000
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 TRUE
-
-/* ETH attributes.*/
-#if !defined(STM32F401xx)
-#define STM32_HAS_ETH TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_ETH FALSE
-#endif /* defined(STM32F401xx) */
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 23
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#if !defined(STM32F401xx)
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOI TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOI FALSE
-#endif /* defined(STM32F401xx) */
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) | \
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C3_RX_DMA_CHN 0x00000300
-#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C3_TX_DMA_CHN 0x00030000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#else
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#endif
-#define STM32_RTC_IS_CALENDAR TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) | \
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || \
- defined(STM32F401xx)
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI4_RX_DMA_CHN 0x00005004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-#else
-#define STM32_HAS_SPI4 FALSE
-#endif
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
-#define STM32_HAS_SPI5 TRUE
-#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI5_RX_DMA_CHN 0x00702000
-#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI5_TX_DMA_CHN 0x07020000
-
-#define STM32_HAS_SPI6 TRUE
-#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI6_RX_DMA_CHN 0x01000000
-#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI6_TX_DMA_CHN 0x00100000
-
-#else /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-#endif /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 TRUE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 TRUE
-#define STM32_HAS_TIM5 TRUE
-#if !defined(STM32F401xx)
-#define STM32_HAS_TIM6 TRUE
-#define STM32_HAS_TIM7 TRUE
-#define STM32_HAS_TIM8 TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_TIM6 FALSE
-#define STM32_HAS_TIM7 FALSE
-#define STM32_HAS_TIM8 FALSE
-#endif /* defined(STM32F401xx) */
-#define STM32_HAS_TIM9 TRUE
-#define STM32_HAS_TIM10 TRUE
-#define STM32_HAS_TIM11 TRUE
-#if !defined(STM32F401xx)
-#define STM32_HAS_TIM12 TRUE
-#define STM32_HAS_TIM13 TRUE
-#define STM32_HAS_TIM14 TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#endif /* defined(STM32F401xx) */
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#if !defined(STM32F401xx)
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_USART3_RX_DMA_CHN 0x00000040
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \
- STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_UART4_RX_DMA_CHN 0x00000400
-#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_UART4_TX_DMA_CHN 0x00040000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0))
-#define STM32_UART5_RX_DMA_CHN 0x00000004
-#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_UART5_TX_DMA_CHN 0x40000000
-
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_USART3 FALSE
-#define STM32_HAS_UART4 FALSE
-#define STM32_HAS_UART5 FALSE
-#endif /* defined(STM32F401xx) */
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) | \
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 TRUE
-#if !defined(STM32F401xx)
-#define STM32_HAS_OTG2 TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_OTG2 FALSE
-#endif /* defined(STM32F401xx) */
+#define STM32_PLLI2SDIVQ_MASK (31 << 0) /**< PLLI2SDIVQ mask. */
+
+#define STM32_PLLSAIDIVQ_MASK (31 << 8) /**< PLLSAIDIVQ mask. */
+
+#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
+#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
+#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
+#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
+#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
+#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */
+
+#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
+#define STM32_SAI1SEL_PLLSAI (0 << 20) /**< SAI1 source is PLLSAI. */
+#define STM32_SAI1SEL_PLLI2S (1 << 20) /**< SAI1 source is PLLI2S. */
+#define STM32_SAI1SEL_PLLR (2 << 20) /**< SAI1 source is PLLR. */
+#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
+
+#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
+#define STM32_SAI2SEL_PLLSAI (0 << 22) /**< SAI2 source is PLLSAI. */
+#define STM32_SAI2SEL_PLLI2S (1 << 22) /**< SAI2 source is PLLI2S. */
+#define STM32_SAI2SEL_PLLR (2 << 22) /**< SAI2 source is PLLR. */
+#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
+
+#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
+#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
+#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
+
+#define STM32_I2S1SEL_MASK (3 << 25) /**< I2S1SEL mask. */
+#define STM32_I2S1SEL_PLLR (0 << 25) /**< I2S1 source is PLLR. */
+#define STM32_I2S1SEL_AFIN (1 << 25) /**< I2S1 source is AF Input. */
+#define STM32_I2S1SEL_MCO1 (2 << 25) /**< I2S1 source is MCO1. */
+#define STM32_I2S1SEL_OFF 0xFFFFFFFFU /**< I2S1 clock is not required.*/
+
+#define STM32_I2S2SEL_MASK (3 << 27) /**< I2S2SEL mask. */
+#define STM32_I2S2SEL_PLLR (0 << 27) /**< I2S2 source is PLLR. */
+#define STM32_I2S2SEL_AFIN (1 << 27) /**< I2S2 source is AF Input. */
+#define STM32_I2S2SEL_MCO1 (2 << 27) /**< I2S2 source is MCO1. */
+#define STM32_I2S2SEL_OFF 0xFFFFFFFFU /**< I2S2 clock is not required.*/
+
+#define STM32_DSISEL_MASK (1 << 28) /**< DSISEL mask. */
+#define STM32_DSISEL_PHY (0 << 28) /**< DSI source is DSI-PSY. */
+#define STM32_DSISEL_PLLR (1 << 28) /**< DSI source is PLLR. */
/** @} */
-/*===========================================================================*/
-/* Platform specific friendly IRQ names. */
-/*===========================================================================*/
-
/**
- * @name IRQ VECTOR names
+ * @name RCC_DCKCFGR2 register bits definitions
* @{
*/
-#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
-#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
- detect. */
-#define TAMP_STAMP_IRQHandler Vector48 /**< Tamper and TimeStamp
- through EXTI Line. */
-#define RTC_WKUP_IRQHandler Vector4C /**< RTC wakeup EXTI Line. */
-#define FLASH_IRQHandler Vector50 /**< Flash. */
-#define RCC_IRQHandler Vector54 /**< RCC. */
-#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
-#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
-#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
-#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
-#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
-#define DMA1_Stream0_IRQHandler Vector6C /**< DMA1 Stream 0. */
-#define DMA1_Stream1_IRQHandler Vector70 /**< DMA1 Stream 1. */
-#define DMA1_Stream2_IRQHandler Vector74 /**< DMA1 Stream 2. */
-#define DMA1_Stream3_IRQHandler Vector78 /**< DMA1 Stream 3. */
-#define DMA1_Stream4_IRQHandler Vector7C /**< DMA1 Stream 4. */
-#define DMA1_Stream5_IRQHandler Vector80 /**< DMA1 Stream 5. */
-#define DMA1_Stream6_IRQHandler Vector84 /**< DMA1 Stream 6. */
-#define ADC1_2_3_IRQHandler Vector88 /**< ADC1, ADC2 and ADC3. */
-#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */
-#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */
-#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */
-#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */
-#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
-#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */
-#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */
-#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and
- Commutation. */
-#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */
-#define TIM2_IRQHandler VectorB0 /**< TIM2. */
-#define TIM3_IRQHandler VectorB4 /**< TIM3. */
-#define TIM4_IRQHandler VectorB8 /**< TIM4. */
-#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
-#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
-#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
-#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */
-#define SPI1_IRQHandler VectorCC /**< SPI1. */
-#define SPI2_IRQHandler VectorD0 /**< SPI2. */
-#define USART1_IRQHandler VectorD4 /**< USART1. */
-#define USART2_IRQHandler VectorD8 /**< USART2. */
-#define USART3_IRQHandler VectorDC /**< USART3. */
-#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
-#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarms (A and B)
- through EXTI line. */
-#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through
- EXTI line. */
-#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */
-#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */
-#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and
- Commutation. */
-#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */
-#define DMA1_Stream7_IRQHandler VectorFC /**< DMA1 Stream 7. */
-#define FSMC_IRQHandler Vector100 /**< FSMC. */
-#define SDIO_IRQHandler Vector104 /**< SDIO. */
-#define TIM5_IRQHandler Vector108 /**< TIM5. */
-#define SPI3_IRQHandler Vector10C /**< SPI3. */
-#define UART4_IRQHandler Vector110 /**< UART4. */
-#define UART5_IRQHandler Vector114 /**< UART5. */
-#define TIM6_IRQHandler Vector118 /**< TIM6. */
-#define TIM7_IRQHandler Vector11C /**< TIM7. */
-#define DMA2_Stream0_IRQHandler Vector120 /**< DMA2 Stream0. */
-#define DMA2_Stream1_IRQHandler Vector124 /**< DMA2 Stream1. */
-#define DMA2_Stream2_IRQHandler Vector128 /**< DMA2 Stream2. */
-#define DMA2_Stream3_IRQHandler Vector12C /**< DMA2 Stream3. */
-#define DMA2_Stream4_IRQHandler Vector130 /**< DMA2 Stream4. */
-#define ETH_IRQHandler Vector134 /**< Ethernet. */
-#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through
- EXTI line. */
-#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */
-#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */
-#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */
-#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */
-#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */
-#define DMA2_Stream5_IRQHandler Vector150 /**< DMA2 Stream5. */
-#define DMA2_Stream6_IRQHandler Vector154 /**< DMA2 Stream6. */
-#define DMA2_Stream7_IRQHandler Vector158 /**< DMA2 Stream7. */
-#define USART6_IRQHandler Vector15C /**< USART6. */
-#define I2C3_EV_IRQHandler Vector160 /**< I2C3 Event. */
-#define I2C3_ER_IRQHandler Vector164 /**< I2C3 Error. */
-#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/
-#define OTG_HS_EP1_IN_IRQHandler Vector16C /**< USB OTG HS End Point 1 In. */
-#define OTG_HS_WKUP_IRQHandler Vector170 /**< USB OTG HS Wakeup through
- EXTI line. */
-#define OTG_HS_IRQHandler Vector174 /**< USB OTG HS. */
-#define DCMI_IRQHandler Vector178 /**< DCMI. */
-#define CRYP_IRQHandler Vector17C /**< CRYP. */
-#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-#define FPU_IRQHandler Vector184 /**< Floating Point Unit. */
-#endif
+#define STM32_I2C1SEL_MASK (3 << 22) /**< I2C1SEL mask. */
+#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is PCLK1. */
+#define STM32_I2C1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
+#define STM32_I2C1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
+
+#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
+#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
+#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
+
+#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
+#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
+#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
+
+#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
+#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
+#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
+
+#define STM32_SPDIFSEL_MASK (1 << 29) /**< SPDIFSEL mask. */
+#define STM32_SPDIFSEL_PLLI2S (0 << 29) /**< SPDIF source is PLLI2S. */
+#define STM32_SPDIFSEL_PLL (1 << 29) /**< SPDIF source is PLL. */
/** @} */
/*===========================================================================*/
@@ -932,6 +735,156 @@
#endif
#endif /* !defined(STM32F4XX) */
+/**
+ * @brief I2S clock source.
+ */
+#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#endif
+
+/**
+ * @brief PLLI2SN multiplier value.
+ * @note The allowed values are 192..432, except for
+ * STM32F446 where values are 50...432.
+ * @note The default value is calculated for a 96MHz I2S clock
+ * output from an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SN_VALUE 192
+#endif
+
+/**
+ * @brief PLLI2SM divider value.
+ * @note The allowed values are 2..63.
+ * @note The default value is calculated for a 96MHz I2S clock
+ * output from an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SM_VALUE 4
+#endif
+
+/**
+ * @brief PLLI2SR divider value.
+ * @note The allowed values are 2..7.
+ * @note The default value is calculated for a 96MHz I2S clock
+ * output from an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SR_VALUE 4
+#endif
+
+/**
+ * @brief PLLI2SP divider value.
+ * @note The allowed values are 2, 4, 6 and 8.
+ */
+#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SP_VALUE 4
+#endif
+
+/**
+ * @brief PLLI2SQ divider value.
+ * @note The allowed values are 2..15.
+ */
+#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SQ_VALUE 4
+#endif
+
+/**
+ * @brief STM32_PLLI2SDIVQ divider value (SAI clock divider).
+ */
+#if !defined(STM32_PLLI2SDIVQ) || defined(__DOXYGEN__)
+#define STM32_PLLI2SDIVQ 0
+#endif
+
+/**
+ * @brief PLLSAIM value.
+ * @note The allowed values are 2..63.
+ * @note The default value is calculated for a 96MHz SAI clock
+ * output from an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIM_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAIN value.
+ * @note The allowed values are 50..432.
+ * @note The default value is calculated for a 96MHz SAI clock
+ * output from an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIN_VALUE 192
+#endif
+
+/**
+ * @brief PLLSAIM value.
+ * @note The allowed values are 2..63.
+ * @note The default value is calculated for a 96MHz SAI clock
+ * output from an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIM_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAIR value.
+ * @note The allowed values are 2..7.
+ */
+#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIR_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAIP divider value.
+ * @note The allowed values are 2, 4, 6 and 8.
+ */
+#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIP_VALUE 8
+#endif
+
+/**
+ * @brief PLLSAIQ value.
+ * @note The allowed values are 2..15.
+ */
+#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIQ_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAIDIVR divider value (SAI clock divider).
+ */
+#if !defined(STM32_PLLSAIDIVR) || defined(__DOXYGEN__)
+#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
+#endif
+
+/**
+ * @brief PLLSAIDIVR divider value (LCD clock divider).
+ */
+#if !defined(STM32_PLLSAIDIVQ) || defined(__DOXYGEN__)
+#define STM32_PLLSAIDIVQ 0
+#endif
+
+/**
+ * @brief SAI1SEL value (SAI1 clock source).
+ */
+#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF
+#endif
+
+/**
+ * @brief SAI2SEL value (SAI2 clock source).
+ */
+#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
+#define STM32_SAI2SEL STM32_SAI2SEL_OFF
+#endif
+
+/**
+ * @brief PLL48CLK clock source.
+ */
+#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__)
+#define STM32_CK48MSEL STM32_CK48MSEL_PLL
+#endif
+
/**
* @brief AHB prescaler value.
*/
@@ -968,59 +921,36 @@
#endif
/**
- * @brief MC01 clock source value.
- * @note The default value outputs HSI clock on MC01 pin.
+ * @brief MCO1 clock source value.
+ * @note The default value outputs HSI clock on MCO1 pin.
*/
#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#endif
/**
- * @brief MC01 prescaler value.
- * @note The default value outputs HSI clock on MC01 pin.
+ * @brief MCO1 prescaler value.
+ * @note The default value outputs HSI clock on MCO1 pin.
*/
#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#endif
/**
- * @brief MC02 clock source value.
- * @note The default value outputs SYSCLK / 5 on MC02 pin.
+ * @brief MCO2 clock source value.
+ * @note The default value outputs SYSCLK / 5 on MCO2 pin.
*/
#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#endif
/**
- * @brief MC02 prescaler value.
- * @note The default value outputs SYSCLK / 5 on MC02 pin.
+ * @brief MCO2 prescaler value.
+ * @note The default value outputs SYSCLK / 5 on MCO2 pin.
*/
#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#endif
-
-/**
- * @brief I2S clock source.
- */
-#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
-#define STM32_I2SSRC STM32_I2SSRC_CKIN
-#endif
-
-/**
- * @brief PLLI2SN multiplier value.
- * @note The allowed values are 192..432.
- */
-#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SN_VALUE 192
-#endif
-
-/**
- * @brief PLLI2SR multiplier value.
- * @note The allowed values are 2..7.
- */
-#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SR_VALUE 5
-#endif
/** @} */
/*===========================================================================*/
@@ -1049,7 +979,8 @@
* @note The values are valid for 2.7V to 3.6V supply range.
*/
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
- defined(STM32F40_41xxx) || defined(__DOXYGEN__)
+ defined(STM32F40_41xxx) || defined(STM32F446xx) || \
+ defined(STM32F469_479xx) || defined(__DOXYGEN__)
#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
#define STM32_0WS_THRESHOLD 30000000
#define STM32_1WS_THRESHOLD 60000000
@@ -1120,7 +1051,7 @@
#define STM32_1WS_THRESHOLD 36000000
#define STM32_2WS_THRESHOLD 54000000
#define STM32_3WS_THRESHOLD 72000000
-#define STM32_4WS_THRESHOLD 840000000
+#define STM32_4WS_THRESHOLD 84000000
#define STM32_5WS_THRESHOLD 0
#define STM32_6WS_THRESHOLD 0
#define STM32_7WS_THRESHOLD 0
@@ -1130,11 +1061,56 @@
#define STM32_1WS_THRESHOLD 32000000
#define STM32_2WS_THRESHOLD 48000000
#define STM32_3WS_THRESHOLD 64000000
-#define STM32_4WS_THRESHOLD 800000000
-#define STM32_5WS_THRESHOLD 840000000
+#define STM32_4WS_THRESHOLD 80000000
+#define STM32_5WS_THRESHOLD 84000000
+#define STM32_6WS_THRESHOLD 0
+#define STM32_7WS_THRESHOLD 0
+#define STM32_8WS_THRESHOLD 0
+#else
+#error "invalid VDD voltage specified"
+#endif
+
+#elif defined(STM32F410xx) || defined(STM32F411xx)
+#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
+#define STM32_0WS_THRESHOLD 30000000
+#define STM32_1WS_THRESHOLD 64000000
+#define STM32_2WS_THRESHOLD 90000000
+#define STM32_3WS_THRESHOLD 100000000
+#define STM32_4WS_THRESHOLD 0
+#define STM32_5WS_THRESHOLD 0
+#define STM32_6WS_THRESHOLD 0
+#define STM32_7WS_THRESHOLD 0
+#define STM32_8WS_THRESHOLD 0
+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
+#define STM32_0WS_THRESHOLD 24000000
+#define STM32_1WS_THRESHOLD 48000000
+#define STM32_2WS_THRESHOLD 72000000
+#define STM32_3WS_THRESHOLD 96000000
+#define STM32_4WS_THRESHOLD 100000000
+#define STM32_5WS_THRESHOLD 0
+#define STM32_6WS_THRESHOLD 0
+#define STM32_7WS_THRESHOLD 0
+#define STM32_8WS_THRESHOLD 0
+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
+#define STM32_0WS_THRESHOLD 18000000
+#define STM32_1WS_THRESHOLD 36000000
+#define STM32_2WS_THRESHOLD 54000000
+#define STM32_3WS_THRESHOLD 72000000
+#define STM32_4WS_THRESHOLD 90000000
+#define STM32_5WS_THRESHOLD 100000000
#define STM32_6WS_THRESHOLD 0
#define STM32_7WS_THRESHOLD 0
#define STM32_8WS_THRESHOLD 0
+#elif (STM32_VDD >= 171) && (STM32_VDD < 210)
+#define STM32_0WS_THRESHOLD 16000000
+#define STM32_1WS_THRESHOLD 32000000
+#define STM32_2WS_THRESHOLD 48000000
+#define STM32_3WS_THRESHOLD 64000000
+#define STM32_4WS_THRESHOLD 80000000
+#define STM32_5WS_THRESHOLD 96000000
+#define STM32_6WS_THRESHOLD 100000000
+#define STM32_7WS_THRESHOLD 0
+#define STM32_8WS_THRESHOLD 0
#else
#error "invalid VDD voltage specified"
#endif
@@ -1210,6 +1186,17 @@
#error "HSI not enabled, required by STM32_I2SSRC"
#endif
+#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SAI1SEL"
+#endif
+
+#if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SAI2SEL"
+#endif
#endif /* !STM32_HSI_ENABLED */
/*
@@ -1219,10 +1206,17 @@
#if STM32_HSECLK == 0
#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#else /* STM32_HSECLK != 0 */
+#if defined(STM32_HSE_BYPASS)
+#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)"
+#endif
+#else /* !defined(STM32_HSE_BYPASS) */
+#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
#endif
-
+#endif /* !defined(STM32_HSE_BYPASS) */
+#endif /* STM32_HSECLK != 0 */
#else /* !STM32_HSE_ENABLED */
#if STM32_SW == STM32_SW_HSE
@@ -1300,7 +1294,7 @@
#endif
/**
- * @brief PLLs input clock frequency.
+ * @brief PLL input clock frequency.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
@@ -1347,13 +1341,13 @@
* @brief STM32_PLLP field.
*/
#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLP (0 << 16)
+#define STM32_PLLP STM32_PLLP_DIV2
#elif STM32_PLLP_VALUE == 4
-#define STM32_PLLP (1 << 16)
+#define STM32_PLLP STM32_PLLP_DIV4
#elif STM32_PLLP_VALUE == 6
-#define STM32_PLLP (2 << 16)
+#define STM32_PLLP STM32_PLLP_DIV6
#elif STM32_PLLP_VALUE == 8
-#define STM32_PLLP (3 << 16)
+#define STM32_PLLP STM32_PLLP_DIV8
#else
#error "invalid STM32_PLLP_VALUE value specified"
#endif
@@ -1414,7 +1408,8 @@
/* Calculating VOS settings, it is different for each sub-platform.*/
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
- defined(STM32F446xx) || defined(__DOXYGEN__)
+ defined(STM32F446xx) || defined(STM32F469_479xx) || \
+ defined(__DOXYGEN__)
#if STM32_SYSCLK <= 120000000
#define STM32_VOS STM32_VOS_SCALE3
#define STM32_OVERDRIVE_REQUIRED FALSE
@@ -1445,6 +1440,16 @@
#endif
#define STM32_OVERDRIVE_REQUIRED FALSE
+#elif defined(STM32F410xx) || defined(STM32F411xx) || defined(STM32F412xx)
+#if STM32_SYSCLK <= 64000000
+#define STM32_VOS STM32_VOS_SCALE3
+#elif STM32_SYSCLK <= 84000000
+#define STM32_VOS STM32_VOS_SCALE2
+#else
+#define STM32_VOS STM32_VOS_SCALE1
+#endif
+#define STM32_OVERDRIVE_REQUIRED FALSE
+
#else /* STM32F2XX */
#define STM32_OVERDRIVE_REQUIRED FALSE
#endif
@@ -1532,24 +1537,71 @@
/*
* PLLI2S enable check.
*/
-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__)
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S) || \
+ defined(__DOXYGEN__)
/**
- * @brief PLL activation flag.
+ * @brief PLLI2S activation flag.
*/
#define STM32_ACTIVATE_PLLI2S TRUE
#else
#define STM32_ACTIVATE_PLLI2S FALSE
#endif
+/**
+ * @brief STM32_PLLI2SM field.
+ */
+#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLI2SM (STM32_PLLI2SM_VALUE << 0)
+#else
+#error "invalid STM32_PLLI2SM_VALUE value specified"
+#endif
+
/**
* @brief STM32_PLLI2SN field.
*/
+#if defined (STM32F446xx) || defined(__DOXYGEN__)
+#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
+#else
+#error "invalid STM32_PLLI2SN_VALUE value specified"
+#endif
+#else /* !defined(STM32F446xx) */
#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \
defined(__DOXYGEN__)
#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
#else
#error "invalid STM32_PLLI2SN_VALUE value specified"
#endif
+#endif /* defined(STM32F446xx) */
+
+/**
+ * @brief STM32_PLLI2SP field.
+ */
+#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLI2SP STM32_PLLI2SP_DIV2
+#elif STM32_PLLI2SP_VALUE == 4
+#define STM32_PLLI2SP STM32_PLLI2SP_DIV4
+#elif STM32_PLLI2SP_VALUE == 6
+#define STM32_PLLI2SP STM32_PLLI2SP_DIV6
+#elif STM32_PLLI2SP_VALUE == 8
+#define STM32_PLLI2SP STM32_PLLI2SP_DIV8
+#else
+#error "invalid STM32_PLLI2SP_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLI2SQ field.
+ */
+#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24)
+#else
+#error "invalid STM32_PLLI2SQ_VALUE value specified"
+#endif
/**
* @brief STM32_PLLI2SR field.
@@ -1562,34 +1614,198 @@
#endif
/**
- * @brief PLL VCO frequency.
+ * @brief PLLI2S input clock frequency.
+ */
+#if defined(STM32F446xx)
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SCLKIN (STM32_HSECLK / STM32_PLLI2SM_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLI2SCLKIN (STM32_HSICLK / STM32_PLLI2SM_VALUE)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+#else /* !defined(STM32F446xx) */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLI2SCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+#endif /* defined(STM32F446xx) */
+
+/**
+ * @brief PLLI2S VCO frequency.
*/
-#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)
+#define STM32_PLLI2SVCO (STM32_PLLI2SCLKIN * STM32_PLLI2SN_VALUE)
/*
* PLLI2S VCO frequency range check.
*/
#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
- (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
+ (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) && !defined(STM32F446xx)
+/* dRonin: Exclude F446 from that check. ChibiOS 2.6.6 didn't implement this check
+ and the 16MHz HSECLK from RE1 that triggers this worked fine before. */
#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/**
- * @brief PLLI2S output clock frequency.
+ * @brief PLLI2S P output clock frequency.
+ */
+#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE)
+
+/**
+ * @brief PLLI2S Q output clock frequency.
+ */
+#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)
+
+/**
+ * @brief PLLI2S R output clock frequency.
+ */
+#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
+
+/*
+ * PLLSAI enable check.
+ */
+#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \
+ (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLLSAI activation flag.
+ */
+#define STM32_ACTIVATE_PLLSAI TRUE
+#else
+#define STM32_ACTIVATE_PLLSAI FALSE
+#endif
+
+/**
+ * @brief STM32_PLLSAIM field.
+ */
+#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0)
+#else
+#error "invalid STM32_PLLSAIM_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIN field.
+ */
+#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6)
+#else
+#error "invalid STM32_PLLSAIN_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIQ field.
+ */
+#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24)
+#else
+#error "invalid STM32_PLLSAIQ_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIR field.
+ */
+#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28)
+#else
+#error "invalid STM32_PLLSAIR_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIP field.
+ */
+
+#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAIP STM32_PLLSAIP_DIV2
+
+#elif STM32_PLLSAIP_VALUE == 4
+#define STM32_PLLSAIP STM32_PLLSAIP_DIV4
+
+#elif STM32_PLLSAIP_VALUE == 6
+#define STM32_PLLSAIP STM32_PLLSAIP_DIV6
+
+#elif STM32_PLLSAIP_VALUE == 8
+#define STM32_PLLSAIP STM32_PLLSAIP_DIV8
+
+#else
+#error "invalid STM32_PLLSAIP_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLSAI input clock frequency.
+ */
+#if defined(STM32F446xx)
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLSAIM_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLSAIM_VALUE)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+#else /* !defined(STM32F446xx) */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+#endif /* defined(STM32F446xx) */
+
+/**
+ * @brief PLLSAI VCO frequency.
+ */
+#define STM32_PLLSAIVCO (STM32_PLLSAICLKIN * STM32_PLLSAIN_VALUE)
+
+/*
+ * PLLSAI VCO frequency range check.
+ */
+#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \
+ (STM32_PLLSAIVCO > STM32_PLLVCO_MAX) && !defined(STM32F446xx)
+/* dRonin: Exclude F446 from that check. ChibiOS 2.6.6 didn't implement this check
+ and the 16MHz HSECLK from RE1 that triggers this worked fine before. */
+#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLLSAI P output clock frequency.
+ */
+#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
+
+/**
+ * @brief PLLSAI Q output clock frequency.
+ */
+#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
+
+/**
+ * @brief PLLSAI R output clock frequency.
*/
-#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
+#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
/**
* @brief MCO1 divider clock.
*/
#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
#define STM32_MCO1DIVCLK STM32_HSICLK
+
#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
#define STM32_MCO1DIVCLK STM32_LSECLK
+
#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
#define STM32_MCO1DIVCLK STM32_HSECLK
+
#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
+
#else
#error "invalid STM32_MCO1SEL value specified"
#endif
@@ -1599,14 +1815,19 @@
*/
#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
#define STM32_MCO1CLK STM32_MCO1DIVCLK
+
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
+
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
+
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
+
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
+
#else
#error "invalid STM32_MCO1PRE value specified"
#endif
@@ -1616,12 +1837,16 @@
*/
#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
#define STM32_MCO2DIVCLK STM32_HSECLK
+
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
+
#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
#define STM32_MCO2DIVCLK STM32_SYSCLK
+
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
#define STM32_MCO2DIVCLK STM32_PLLI2S
+
#else
#error "invalid STM32_MCO2SEL value specified"
#endif
@@ -1631,14 +1856,19 @@
*/
#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
#define STM32_MCO2CLK STM32_MCO2DIVCLK
+
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
+
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
+
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
+
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
+
#else
#error "invalid STM32_MCO2PRE value specified"
#endif
@@ -1668,12 +1898,16 @@
*/
#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
#define STM32_RTCCLK 0
+
#elif STM32_RTCSEL == STM32_RTCSEL_LSE
#define STM32_RTCCLK STM32_LSECLK
+
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
#define STM32_RTCCLK STM32_LSICLK
+
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#define STM32_RTCCLK STM32_HSEDIVCLK
+
#else
#error "invalid STM32_RTCSEL value specified"
#endif
@@ -1682,13 +1916,20 @@
* @brief 48MHz frequency.
*/
#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
+#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
+#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI
+#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
#else
-#define STM32_PLL48CLK 0
+#error "invalid source selected for PLL48CLK clock"
#endif
+#else /* !STM32_CLOCK48_REQUIRED */
+#define STM32_PLL48CLK 0
+#endif /* !STM32_CLOCK48_REQUIRED */
/**
- * @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock.
+ * @brief Clock of timers connected to APB1
+ * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
*/
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
@@ -1697,7 +1938,7 @@
#endif
/**
- * @brief Timers 1, 8 clock.
+ * @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
*/
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
@@ -1730,59 +1971,29 @@
/* There are differences in vector names in the various sub-families,
normalizing.*/
+#if 0
#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
+#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() DWT_CYCCNT
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() STM32_HCLK
-
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-/* STM32 helpers and custom drivers.*/
+/* Various helpers.*/
+#include "nvic.h"
#include "stm32_isr.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"
@@ -1796,6 +2007,6 @@ extern "C" {
}
#endif
-#endif /* _HAL_LLD_H_ */
+#endif /* HAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/platform.mk
new file mode 100644
index 0000000000..69e468c8db
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/platform.mk
@@ -0,0 +1,36 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
similarity index 85%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_isr.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
index e8f45b0acc..635cdaadf7 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_isr.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,8 +22,8 @@
* @{
*/
-#ifndef _STM32_ISR_H_
-#define _STM32_ISR_H_
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
@@ -106,8 +106,10 @@
#define STM32_TIM8_UP_HANDLER VectorF0
#define STM32_TIM8_CC_HANDLER VectorF8
#define STM32_TIM9_HANDLER VectorA0
+#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */
#define STM32_TIM11_HANDLER VectorA8
#define STM32_TIM12_HANDLER VectorEC
+#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */
#define STM32_TIM14_HANDLER VectorF4
#define STM32_TIM1_UP_NUMBER 25
@@ -121,8 +123,10 @@
#define STM32_TIM8_UP_NUMBER 44
#define STM32_TIM8_CC_NUMBER 46
#define STM32_TIM9_NUMBER 24
+#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */
#define STM32_TIM11_NUMBER 26
#define STM32_TIM12_NUMBER 43
+#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */
#define STM32_TIM14_NUMBER 45
/*
@@ -134,6 +138,8 @@
#define STM32_UART4_HANDLER Vector110
#define STM32_UART5_HANDLER Vector114
#define STM32_USART6_HANDLER Vector15C
+#define STM32_UART7_HANDLER Vector188
+#define STM32_UART8_HANDLER Vector18C
#define STM32_USART1_NUMBER 37
#define STM32_USART2_NUMBER 38
@@ -141,12 +147,37 @@
#define STM32_UART4_NUMBER 52
#define STM32_UART5_NUMBER 53
#define STM32_USART6_NUMBER 71
+#define STM32_UART7_NUMBER 82
+#define STM32_UART8_NUMBER 83
/*
* Ethernet
*/
#define ETH_IRQHandler Vector134
+/*
+ * FSMC
+ */
+#define STM32_FSMC_HANDLER Vector100
+
+#define STM32_FSMC_NUMBER 48
+
+/*
+ * LTDC
+ */
+#define STM32_LTDC_EV_HANDLER Vector1A0
+#define STM32_LTDC_ER_HANDLER Vector1A4
+
+#define STM32_LTDC_EV_NUMBER 88
+#define STM32_LTDC_ER_NUMBER 89
+
+/*
+ * DMA2D
+ */
+#define STM32_DMA2D_HANDLER Vector1A8
+
+#define STM32_DMA2D_NUMBER 90
+
/** @} */
/*===========================================================================*/
@@ -169,6 +200,6 @@
/* External declarations. */
/*===========================================================================*/
-#endif /* _STM32_ISR_H_ */
+#endif /* STM32_ISR_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
similarity index 84%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_rcc.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
index 91fce72cbf..8a6e6abb84 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/stm32_rcc.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -331,6 +331,36 @@
#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
/** @} */
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
+/** @} */
+
/**
* @name DMA peripheral specific RCC operations
* @{
@@ -439,7 +469,6 @@
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
-
/**
* @name CAN peripherals specific RCC operations
* @{
@@ -663,7 +692,7 @@
*
* @api
*/
-#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHSRST)
+#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST)
/**
* @brief Enables the OTG_HS peripheral clock.
@@ -684,6 +713,36 @@
#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
/** @} */
+/**
+ * @name QUADSPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Disables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Resets the QUADSPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
+/** @} */
+
/**
* @name SDIO peripheral specific RCC operations
* @{
@@ -1087,7 +1146,7 @@
#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
/**
- * @brief Enables the TIM9peripheral clock.
+ * @brief Enables the TIM9 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
@@ -1113,6 +1172,33 @@
*/
#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
+/**
+ * @brief Enables the TIM10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
+
+/**
+ * @brief Disables the TIM10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
+
+/**
+ * @brief Resets the TIM10 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
+
/**
* @brief Enables the TIM11 peripheral clock.
* @note The @p lp parameter is ignored in this family.
@@ -1167,6 +1253,33 @@
*/
#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
+/**
+ * @brief Enables the TIM13 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Disables the TIM13 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Resets the TIM13 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
+
/**
* @brief Enables the TIM14 peripheral clock.
* @note The @p lp parameter is ignored in this family.
@@ -1274,24 +1387,6 @@
*/
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
-/**
- * @brief Enables the USART6 peripheral clock.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
-
-/**
- * @brief Disables the USART6 peripheral clock.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)
-
/**
* @brief Enables the UART4 peripheral clock.
* @note The @p lp parameter is ignored in this family.
@@ -1346,12 +1441,84 @@
*/
#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
+/**
+ * @brief Enables the USART6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
+
+/**
+ * @brief Disables the USART6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)
+
/**
* @brief Resets the USART6 peripheral.
*
* @api
*/
#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
+
+/**
+ * @brief Enables the UART7 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART7(lp) rccEnableAPB1(RCC_APB1ENR_UART7EN, lp)
+
+/**
+ * @brief Disables the UART7 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART7(lp) rccDisableAPB1(RCC_APB1ENR_UART7EN, lp)
+
+/**
+ * @brief Resets the UART7 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART7() rccResetAPB1(RCC_APB1RSTR_UART7RST)
+
+/**
+ * @brief Enables the UART8 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART8(lp) rccEnableAPB1(RCC_APB1ENR_UART8EN, lp)
+
+/**
+ * @brief Disables the UART8 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART8(lp) rccDisableAPB1(RCC_APB1ENR_UART8EN, lp)
+
+/**
+ * @brief Resets the UART8 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART8() rccResetAPB1(RCC_APB1RSTR_UART8RST)
/** @} */
/**
@@ -1382,6 +1549,113 @@
* @api
*/
#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)
+
+/**
+ * @name DMA2D peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA2D peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
+
+/**
+ * @brief Disables the DMA2D peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
+
+/**
+ * @brief Resets the DMA2D peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)
+/** @} */
+
+/**
+ * @name CRC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
+
+/**
+ * @brief Disables the CRC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCRC(lp) rccDisableAHB1(RCC_AHB1ENR_CRCEN, lp)
+
+/**
+ * @brief Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
+/** @} */
+
+/**
+ * @name FSMC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#if STM32_HAS_FSMC || defined(__DOXYGEN__)
+#if STM32_FSMC_IS_FMC || defined(__DOXYGEN__)
+ #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
+#else
+ #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp)
+#endif
+#endif
+
+/**
+ * @brief Disables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#if STM32_HAS_FSMC || defined(__DOXYGEN__)
+#if STM32_FSMC_IS_FMC || defined(__DOXYGEN__)
+ #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp)
+#else
+ #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FSMCEN, lp)
+#endif
+#endif
+
+/**
+ * @brief Resets the FSMC peripheral.
+ *
+ * @api
+ */
+#if STM32_HAS_FSMC || defined(__DOXYGEN__)
+#if STM32_FSMC_IS_FMC || defined(__DOXYGEN__)
+ #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
+#else
+ #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST)
+#endif
+#endif
/** @} */
/*===========================================================================*/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
new file mode 100644
index 0000000000..088bd44bdc
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -0,0 +1,2700 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F4xx/stm32_registry.h
+ * @brief STM32F4xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define STM32F469_479xx
+#define STM32F4XX
+
+#elif defined(STM32F446xx)
+#define STM32F4XX
+
+#elif defined(STM32F439xx) || defined(STM32F429xx)
+#define STM32F429_439xx
+#define STM32F4XX
+
+#elif defined(STM32F437xx) || defined(STM32F427xx)
+#define STM32F427_437xx
+#define STM32F4XX
+
+#elif defined(STM32F412Cx) || defined(STM32F412Rx) || \
+ defined(STM32F412Vx) || defined(STM32F412Zx)
+#define STM32F412xx
+#define STM32F4XX
+
+#elif defined(STM32F411xE)
+#define STM32F411xx
+#define STM32F4XX
+
+#elif defined(STM32F410Cx) || defined(STM32F410Rx) || \
+ defined(STM32F410Tx)
+#define STM32F410xx
+#define STM32F4XX
+
+#elif defined(STM32F405xx) || defined(STM32F415xx) || \
+ defined(STM32F407xx) || defined(STM32F417xx)
+#if !defined(STM32F40_41xxx)
+#define STM32F40_41xxx
+#endif
+#define STM32F4XX
+
+#elif defined(STM32F401xC) || defined(STM32F401xE)
+#define STM32F401xx
+#define STM32F4XX
+
+#elif defined(STM32F205xx) || defined(STM32F215xx) || \
+ defined(STM32F207xx) || defined(STM32F217xx)
+#define STM32F2XX
+
+#else
+#error "STM32F2xx/F4xx device not specified"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32F4xx/STM32F2xx capabilities
+ * @{
+ */
+
+/*===========================================================================*/
+/* STM32F469xx, STM32F479xx. */
+/*===========================================================================*/
+
+#if defined(STM32F469_479xx) || defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00001100
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_ADC3_DMA_CHN 0x00000022
+
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_DAC1_CH1_DMA_CHN 0x00700000
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_DAC1_CH2_DMA_CHN 0x07000000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING FALSE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOI TRUE
+#define STM32_HAS_GPIOJ TRUE
+#define STM32_HAS_GPIOK TRUE
+
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN | \
+ RCC_AHB1ENR_GPIOFEN | \
+ RCC_AHB1ENR_GPIOGEN | \
+ RCC_AHB1ENR_GPIOHEN | \
+ RCC_AHB1ENR_GPIOIEN | \
+ RCC_AHB1ENR_GPIOJEN | \
+ RCC_AHB1ENR_GPIOKEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector1AC
+#define STM32_QUADSPI1_NUMBER 91
+#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_QUADSPI1_DMA_CHN 0x30000000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN 0x04004000
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI4_RX_DMA_CHN 0x00005004
+#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN 0x00050040
+
+#define STM32_HAS_SPI5 TRUE
+#define STM32_SPI5_SUPPORTS_I2S FALSE
+#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI5_RX_DMA_CHN 0x00702000
+#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI5_TX_DMA_CHN 0x07020000
+
+#define STM32_HAS_SPI6 TRUE
+#define STM32_SPI6_SUPPORTS_I2S FALSE
+#define STM32_SPI6_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6)
+#define STM32_SPI6_RX_DMA_CHN 0x01000000
+#define STM32_SPI6_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
+#define STM32_SPI6_TX_DMA_CHN 0x00100000
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 4
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_USART3_RX_DMA_CHN 0x00000040
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN 0x00074000
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_UART4_RX_DMA_CHN 0x00000400
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_UART4_TX_DMA_CHN 0x00040000
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART5_RX_DMA_CHN 0x00000004
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_UART5_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 TRUE
+#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_UART7_RX_DMA_CHN 0x00004000
+#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_UART7_TX_DMA_CHN 0x00000050
+
+#define STM32_HAS_UART8 TRUE
+#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_UART8_RX_DMA_CHN 0x05000000
+#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART8_TX_DMA_CHN 0x00000005
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 5
+#define STM32_HAS_OTG2 TRUE
+#define STM32_OTG2_ENDPOINTS 7
+
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC TRUE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC TRUE
+#define STM32_FSMC_HANDLER Vector100
+#define STM32_FSMC_NUMBER 48
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F469_479xx) */
+
+/*===========================================================================*/
+/* STM32F446xx. */
+/*===========================================================================*/
+
+#if defined(STM32F446xx)
+
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00001100
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_ADC3_DMA_CHN 0x00000022
+
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_DAC1_CH1_DMA_CHN 0x00700000
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_DAC1_CH2_DMA_CHN 0x07000000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING FALSE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN | \
+ RCC_AHB1ENR_GPIOFEN | \
+ RCC_AHB1ENR_GPIOGEN | \
+ RCC_AHB1ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector1B0
+#define STM32_QUADSPI1_NUMBER 92
+#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_QUADSPI1_DMA_CHN 0x30000000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN 0x04004000
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI4_RX_DMA_CHN 0x00005004
+#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN 0x00050040
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 4
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_USART3_RX_DMA_CHN 0x00000040
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN 0x00074000
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_UART4_RX_DMA_CHN 0x00000400
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_UART4_TX_DMA_CHN 0x00040000
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART5_RX_DMA_CHN 0x00000004
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_UART5_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 5
+#define STM32_HAS_OTG2 TRUE
+#define STM32_OTG2_ENDPOINTS 7
+
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC TRUE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC TRUE
+#define STM32_FSMC_HANDLER Vector100
+#define STM32_FSMC_NUMBER 48
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F446xx) */
+
+/*===========================================================================*/
+/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */
+/*===========================================================================*/
+
+#if defined(STM32F429_439xx) || defined(STM32F427_437xx)
+
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00001100
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_ADC3_DMA_CHN 0x00000022
+
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_DAC1_CH1_DMA_CHN 0x00700000
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_DAC1_CH2_DMA_CHN 0x07000000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING FALSE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH TRUE
+#define STM32_ETH_HANDLER Vector134
+#define STM32_ETH_NUMBER 61
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOI TRUE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN | \
+ RCC_AHB1ENR_GPIOFEN | \
+ RCC_AHB1ENR_GPIOGEN | \
+ RCC_AHB1ENR_GPIOHEN | \
+ RCC_AHB1ENR_GPIOIEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN 0x04004000
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI4_RX_DMA_CHN 0x00005004
+#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN 0x00050040
+
+#define STM32_HAS_SPI5 TRUE
+#define STM32_SPI5_SUPPORTS_I2S FALSE
+#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI5_RX_DMA_CHN 0x00702000
+#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI5_TX_DMA_CHN 0x07020000
+
+#define STM32_HAS_SPI6 TRUE
+#define STM32_SPI6_SUPPORTS_I2S FALSE
+#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI6_RX_DMA_CHN 0x01000000
+#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI6_TX_DMA_CHN 0x00100000
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 4
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_USART3_RX_DMA_CHN 0x00000040
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN 0x00074000
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_UART4_RX_DMA_CHN 0x00000400
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_UART4_TX_DMA_CHN 0x00040000
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART5_RX_DMA_CHN 0x00000004
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_UART5_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 TRUE
+#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_UART7_RX_DMA_CHN 0x00005000
+#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_UART7_TX_DMA_CHN 0x00000050
+
+#define STM32_HAS_UART8 TRUE
+#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_UART8_RX_DMA_CHN 0x05000000
+#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART8_TX_DMA_CHN 0x00000005
+
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 1
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 3
+#define STM32_HAS_OTG2 TRUE
+#define STM32_OTG2_ENDPOINTS 5
+
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC TRUE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC TRUE
+#define STM32_FSMC_HANDLER Vector100
+#define STM32_FSMC_NUMBER 48
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
+
+/*===========================================================================*/
+/* STM32F412Cx, STM32F412Rx, STM32F412Vx, STM32F412Zx */
+/*===========================================================================*/
+
+#if defined(STM32F412xx)
+
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING FALSE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN | \
+ RCC_AHB1ENR_GPIOFEN | \
+ RCC_AHB1ENR_GPIOGEN | \
+ RCC_AHB1ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector1B0
+#define STM32_QUADSPI1_NUMBER 92
+#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_QUADSPI1_DMA_CHN 0x30000000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN 0x04004000
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_RX_DMA_CHN 0x00045004
+#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN 0x00050040
+
+#define STM32_HAS_SPI5 TRUE
+#define STM32_SPI5_SUPPORTS_I2S FALSE
+#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI5_RX_DMA_CHN 0x00702000
+#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI5_TX_DMA_CHN 0x07520000
+
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_USART3_RX_DMA_CHN 0x00000040
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN 0x00074000
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 3
+
+#define STM32_HAS_OTG2 FALSE
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F412xx) */
+
+/*===========================================================================*/
+/* STM32F411xC, STM32F411xE */
+/*===========================================================================*/
+
+#if defined(STM32F411xx)
+
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING FALSE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN | \
+ RCC_AHB1ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
++ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_RX_DMA_CHN 0x00000310
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
++ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C3_TX_DMA_CHN 0x00630000
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN 0x04004000
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI4_RX_DMA_CHN 0x00005004
+#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN 0x00050040
+
+#define STM32_HAS_SPI5 TRUE
+#define STM32_SPI5_SUPPORTS_I2S FALSE
+#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI5_RX_DMA_CHN 0x00702000
+#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI5_TX_DMA_CHN 0x07020000
+
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 1
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 3
+
+#define STM32_HAS_OTG2 FALSE
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F411xx) */
+
+/*===========================================================================*/
+/* STM32F410Cx, STM32F410Rx. */
+/*===========================================================================*/
+
+#if defined(STM32F410xx)
+
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_DAC1_CH1_DMA_CHN 0x00700000
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING FALSE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 FALSE
+
+#define STM32_HAS_I2C4 FALSE
+#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C4_RX_DMA_CHN 0x00002007
+#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) |\
+ STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_I2C4_TX_DMA_CHN 0x00040020
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00003200
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI5 TRUE
+#define STM32_SPI5_SUPPORTS_I2S TRUE
+#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI5_RX_DMA_CHN 0x00702000
+#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI5_TX_DMA_CHN 0x07020000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM2 FALSE
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_RX_DMA_CHN 0x60400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F410xx) */
+
+/*===========================================================================*/
+/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx */
+/* STM32F215xx, STM32F207xx, STM32F217xx. */
+/*===========================================================================*/
+
+#if defined(STM32F40_41xxx) || defined(STM32F2XX)
+
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00001100
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_ADC3_DMA_CHN 0x00000022
+
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_DAC1_CH1_DMA_CHN 0x00700000
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_DAC1_CH2_DMA_CHN 0x07000000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING FALSE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F205xx) || \
+ defined(STM32F215xx)
+#define STM32_HAS_ETH FALSE
+#else
+#define STM32_HAS_ETH TRUE
+#define STM32_ETH_HANDLER Vector134
+#define STM32_ETH_NUMBER 61
+#endif
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOI TRUE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN | \
+ RCC_AHB1ENR_GPIOFEN | \
+ RCC_AHB1ENR_GPIOGEN | \
+ RCC_AHB1ENR_GPIOHEN | \
+ RCC_AHB1ENR_GPIOIEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#if !defined(STM32F2XX)
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#else
+#define STM32_RTC_HAS_SUBSECONDS FALSE
+#endif
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN 0x04004000
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_USART3_RX_DMA_CHN 0x00000040
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN 0x00074000
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_UART4_RX_DMA_CHN 0x00000400
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_UART4_TX_DMA_CHN 0x00040000
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART5_RX_DMA_CHN 0x00000004
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_UART5_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 1
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 3
+#define STM32_HAS_OTG2 TRUE
+#define STM32_OTG2_ENDPOINTS 5
+
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */
+
+/*===========================================================================*/
+/* STM32F401xx. */
+/*===========================================================================*/
+
+#if defined(STM32F401xx)
+
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00001100
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_ADC3_DMA_CHN 0x00000022
+
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_HAS_CAN3 FALSE
+#define STM32_CAN_MAX_FILTERS 28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING FALSE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN 0x04004000
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI4_RX_DMA_CHN 0x00005004
+#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN 0x00050040
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 1
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 3
+#define STM32_HAS_OTG2 FALSE
+
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F401xx) */
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c
new file mode 100644
index 0000000000..b62e5c45c7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c
@@ -0,0 +1,391 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F7xx/hal_ext_lld_isr.c
+ * @brief STM32F7xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "hal_ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 0);
+ EXTI->PR = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 1);
+ EXTI->PR = pr;
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 2);
+ EXTI->PR = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 3);
+ EXTI->PR = pr;
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 4);
+ EXTI->PR = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9));
+ EXTI->PR = pr;
+ if (pr & (1U << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1U << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1U << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1U << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1U << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
+ EXTI->PR = pr;
+ if (pr & (1U << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1U << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1U << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1U << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1U << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1U << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 16);
+ EXTI->PR = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[17] interrupt handler (RTC_ALARM).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 17);
+ EXTI->PR = pr;
+ if (pr & (1U << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE8) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 18);
+ EXTI->PR = pr;
+ if (pr & (1U << 18))
+ EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[19] interrupt handler (ETH_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector138) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 19);
+ EXTI->PR = pr;
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[20] interrupt handler (OTG_HS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector170) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 20);
+ EXTI->PR = pr;
+ if (pr & (1U << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[21] interrupt handler (TAMPER_STAMP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 21);
+ EXTI->PR = pr;
+ if (pr & (1U << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[22] interrupt handler (RTC_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 22);
+ EXTI->PR = pr;
+ if (pr & (1U << 22))
+ EXTD1.config->channels[22].cb(&EXTD1, 22);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+ nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+ nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+ nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+ nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY);
+ nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY);
+ nvicEnableVector(LPTIM1_IRQn, STM32_EXT_EXTI23_IRQ_PRIORITY);
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(EXTI0_IRQn);
+ nvicDisableVector(EXTI1_IRQn);
+ nvicDisableVector(EXTI2_IRQn);
+ nvicDisableVector(EXTI3_IRQn);
+ nvicDisableVector(EXTI4_IRQn);
+ nvicDisableVector(EXTI9_5_IRQn);
+ nvicDisableVector(EXTI15_10_IRQn);
+ nvicDisableVector(PVD_IRQn);
+ nvicDisableVector(RTC_Alarm_IRQn);
+ nvicDisableVector(OTG_FS_WKUP_IRQn);
+ nvicDisableVector(ETH_WKUP_IRQn);
+ nvicDisableVector(OTG_HS_WKUP_IRQn);
+ nvicDisableVector(TAMP_STAMP_IRQn);
+ nvicDisableVector(RTC_WKUP_IRQn);
+ nvicDisableVector(LPTIM1_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.h
new file mode 100644
index 0000000000..a8463a6162
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.h
@@ -0,0 +1,177 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F7xx/hal_ext_lld_isr.h
+ * @brief STM32F7xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI2 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI4 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI9..5 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI15..10 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI16 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI17 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI18 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI19 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI20 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI21 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI23 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI23_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI23_IRQ_PRIORITY 6
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_exti_irq_enable(void);
+ void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_lld.c
new file mode 100644
index 0000000000..0a791ab0d0
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -0,0 +1,299 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F7xx/hal_lld.c
+ * @brief STM32F7xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32f7xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ * @note WARNING! Changing clock source impossible without resetting
+ * of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR1 |= PWR_CR1_DBP;
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
+ /* Backup domain reset.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+ }
+
+#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if HAL_USE_RTC
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->BDCR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->BDCR |= RCC_BDCR_RTCEN;
+ }
+#endif /* HAL_USE_RTC */
+
+#if STM32_BKPRAM_ENABLE
+ rccEnableBKPSRAM(false);
+
+ PWR->CSR1 |= PWR_CSR1_BRE;
+ while ((PWR->CSR1 & PWR_CSR1_BRR) == 0)
+ ; /* Waits until the regulator is stable */
+#else
+ PWR->CSR1 &= ~PWR_CSR1_BRE;
+#endif /* STM32_BKPRAM_ENABLE */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Reset of all peripherals. AHB3 is not reseted because it could have
+ been initialized in the board initialization file (board.c).*/
+ rccResetAHB1(~0);
+ rccResetAHB2(~0);
+ rccResetAPB1(~RCC_APB1RSTR_PWRRST);
+ rccResetAPB2(~0);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+#if STM32_SRAM2_NOCACHE
+ /* The SRAM2 bank can optionally made a non cache-able area for use by
+ DMA engines.*/
+ mpuConfigureRegion(MPU_REGION_7,
+ SRAM2_BASE,
+ MPU_RASR_ATTR_AP_RW_RW |
+ MPU_RASR_ATTR_NON_CACHEABLE |
+ MPU_RASR_SIZE_16K |
+ MPU_RASR_ENABLE);
+ mpuEnable(MPU_CTRL_PRIVDEFENA);
+
+ /* Invalidating data cache to make sure that the MPU settings are taken
+ immediately.*/
+ SCB_CleanInvalidateDCache();
+#endif
+
+ /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+ PWR->CR1 |= PWR_CR1_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief STM32F2xx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+ /* PWR clock enabled.*/
+#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCEN)
+ RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCEN;
+#else
+ RCC->APB1ENR = RCC_APB1ENR_PWREN;
+#endif
+
+ /* PWR initialization.*/
+ PWR->CR1 = STM32_VOS;
+
+ /* HSI setup, it enforces the reset situation in order to handle possible
+ problems with JTAG probes and re-initializations.*/
+ RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
+ while (!(RCC->CR & RCC_CR_HSIRDY))
+ ; /* Wait until HSI is stable. */
+
+ /* HSI is selected as new source without touching the other fields in
+ CFGR. Clearing the register has to be postponed after HSI is the
+ new source.*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
+ RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ ; /* Wait until HSI is selected. */
+
+ /* Registers finally cleared to reset values.*/
+ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+ RCC->CFGR = 0; /* CFGR reset value. */
+
+#if STM32_HSE_ENABLED
+ /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+ /* No HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON;
+#endif
+ while ((RCC->CR & RCC_CR_HSERDY) == 0)
+ ; /* Waits until HSE is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Waits until LSI is stable. */
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
+ STM32_PLLM;
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Synchronization with voltage regulator stabilization.*/
+ while ((PWR->CSR1 & PWR_CSR1_VOSRDY) == 0)
+ ; /* Waits until power regulator is stable. */
+
+#if STM32_OVERDRIVE_REQUIRED
+ /* Overdrive activation performed after activating the PLL in order to save
+ time as recommended in RM in "Entering Over-drive mode" paragraph.*/
+ PWR->CR1 |= PWR_CR1_ODEN;
+ while (!(PWR->CSR1 & PWR_CSR1_ODRDY))
+ ;
+ PWR->CR1 |= PWR_CR1_ODSWEN;
+ while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY))
+ ;
+#endif /* STM32_OVERDRIVE_REQUIRED */
+
+ /* Waiting for PLL lock.*/
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ;
+#endif /* STM32_OVERDRIVE_REQUIRED */
+
+#if STM32_ACTIVATE_PLLI2S
+ /* PLLI2S activation.*/
+ RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
+ RCC->CR |= RCC_CR_PLLI2SON;
+
+ /* Waiting for PLL lock.*/
+ while (!(RCC->CR & RCC_CR_PLLI2SRDY))
+ ;
+#endif
+
+#if STM32_ACTIVATE_PLLSAI
+ /* PLLSAI activation.*/
+ RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIQ | STM32_PLLSAIP |
+ STM32_PLLSAIN;
+ RCC->CR |= RCC_CR_PLLSAION;
+
+ /* Waiting for PLL lock.*/
+ while (!(RCC->CR & RCC_CR_PLLSAIRDY))
+ ;
+#endif
+
+ /* Other clock-related settings (dividers, MCO etc).*/
+ RCC->CFGR = STM32_MCO2SEL | STM32_MCO2PRE | STM32_MCO1PRE | STM32_I2SSRC |
+ STM32_MCO1SEL | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
+ STM32_HPRE;
+
+ /* DCKCFGR1 register initialization, note, must take care of the _OFF
+ pseudo settings.*/
+ {
+ uint32_t dckcfgr1 = STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ | STM32_PLLSAIDIVR;
+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+ dckcfgr1 |= STM32_SAI2SEL;
+#endif
+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+ dckcfgr1 |= STM32_SAI1SEL;
+#endif
+ RCC->DCKCFGR1 = dckcfgr1;
+ }
+
+ /* Peripheral clock sources.*/
+ RCC->DCKCFGR2 = STM32_SDMMCSEL | STM32_CK48MSEL | STM32_CECSEL |
+ STM32_LPTIM1SEL | STM32_I2C4SEL | STM32_I2C3SEL |
+ STM32_I2C2SEL | STM32_I2C1SEL | STM32_UART8SEL |
+ STM32_UART7SEL | STM32_USART6SEL | STM32_UART5SEL |
+ STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL |
+ STM32_USART1SEL;
+
+ /* Flash setup.*/
+ FLASH->ACR = FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS;
+
+ /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+#endif
+#endif /* STM32_NO_INIT */
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_lld.h
new file mode 100644
index 0000000000..d3982bab62
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/hal_lld.h
@@ -0,0 +1,2054 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F7xx/hal_lld.h
+ * @brief STM32F7xx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_LSEDRV.
+ * - STM32_LSE_BYPASS (optionally).
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * - STM32_VDD (as hundredths of Volt).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32F745xx, STM32F746xx, STM32F756xx very high-performance MCUs.
+ * - STM32F767xx, STM32F769xx, STM32F777xx, STM32F779xx very
+ * high-performance MCUs.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS TRUE
+
+/**
+ * @name Platform identification macros
+ * @{
+ */
+#if defined(STM32F745xx) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32F745 Very High Performance with DSP and FPU"
+
+#elif defined(STM32F746xx)
+#define PLATFORM_NAME "STM32F746 Very High Performance with DSP and FPU"
+
+#elif defined(STM32F756xx)
+#define PLATFORM_NAME "STM32F756 Very High Performance with DSP and FPU"
+
+#elif defined(STM32F767xx)
+#define PLATFORM_NAME "STM32F767 Very High Performance with DSP and DP FPU"
+
+#elif defined(STM32F769xx)
+#define PLATFORM_NAME "STM32F769 Very High Performance with DSP and DP FPU"
+
+#elif defined(STM32F777xx)
+#define PLATFORM_NAME "STM32F767 Very High Performance with DSP and DP FPU"
+
+#elif defined(STM32F779xx)
+#define PLATFORM_NAME "STM32F769 Very High Performance with DSP and DP FPU"
+
+#else
+#error "STM32F7xx device not specified"
+#endif
+/** @} */
+
+/**
+ * @name Sub-family identifier
+ */
+#if !defined(STM32F7XX) || defined(__DOXYGEN__)
+#define STM32F7XX
+#endif
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Absolute maximum system clock.
+ */
+#define STM32_SYSCLK_MAX 216000000
+
+/**
+ * @brief Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX 26000000
+
+/**
+ * @brief Maximum HSE clock frequency using an external source.
+ */
+#define STM32_HSECLK_BYP_MAX 50000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN 4000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_BYP_MIN 1000000
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX 32768
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_BYP_MAX 1000000
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN 32768
+
+/**
+ * @brief Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX 2100000
+
+/**
+ * @brief Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN 950000
+
+/**
+ * @brief Maximum PLLs VCO clock frequency.
+ */
+#define STM32_PLLVCO_MAX 432000000
+
+/**
+ * @brief Minimum PLLs VCO clock frequency.
+ */
+#define STM32_PLLVCO_MIN 192000000
+
+/**
+ * @brief Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX 216000000
+
+/**
+ * @brief Minimum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN 24000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
+
+/**
+ * @brief Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
+
+/**
+ * @brief Maximum SPI/I2S clock frequency.
+ */
+#define STM32_SPII2S_MAX 54000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK 16000000 /**< High speed internal clock. */
+#define STM32_LSICLK 32000 /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_VOS_SCALE3 (PWR_CR1_VOS_0)
+#define STM32_VOS_SCALE2 (PWR_CR1_VOS_1)
+#define STM32_VOS_SCALE1 (PWR_CR1_VOS_1 | PWR_CR1_VOS_0)
+
+#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
+#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
+/** @} */
+
+/**
+ * @name RCC_PLLCFGR register bits definitions
+ * @{
+ */
+#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
+#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
+#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
+#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
+#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
+
+#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
+#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MASK (3 << 0) /**< SW mask. */
+#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
+#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */
+#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
+#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
+#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
+#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
+#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
+#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
+
+#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
+#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
+#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
+#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
+#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */
+#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */
+
+#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */
+
+#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */
+#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */
+#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */
+#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
+#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
+
+#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */
+#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
+#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
+#define STM32_I2SSRC_OFF (1 << 23) /**< ISS clock not required. */
+
+#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
+#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
+#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
+#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */
+#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */
+#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */
+
+#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */
+#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */
+#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */
+#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */
+#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
+#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
+
+#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
+#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
+#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
+#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
+#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
+
+/**
+ * @name RCC_PLLI2SCFGR register bits definitions
+ * @{
+ */
+#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
+#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
+/** @} */
+
+/**
+ * @name RCC_DCKCFGR1 register bits definitions
+ * @{
+ */
+#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
+#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
+#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
+#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
+#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
+
+#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
+#define STM32_SAI1SEL_SAIPLL (0 << 20) /**< SAI1 source is SAIPLL. */
+#define STM32_SAI1SEL_I2SPLL (1 << 20) /**< SAI1 source is I2SPLL. */
+#define STM32_SAI1SEL_CKIN (2 << 20) /**< SAI1 source is I2S_CKIN. */
+#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
+
+#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
+#define STM32_SAI2SEL_SAIPLL (0 << 22) /**< SAI2 source is SAIPLL. */
+#define STM32_SAI2SEL_I2SPLL (1 << 22) /**< SAI2 source is I2SPLL. */
+#define STM32_SAI2SEL_CKIN (2 << 22) /**< SAI2 source is I2S_CKIN. */
+#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
+
+#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
+#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
+#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
+/** @} */
+
+/**
+ * @name RCC_DCKCFGR2 register bits definitions
+ * @{
+ */
+#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */
+#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */
+#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */
+#define STM32_USART1SEL_HSI (2 << 0) /**< USART1 source is HSI. */
+#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */
+
+#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 mask. */
+#define STM32_USART2SEL_PCLK1 (0 << 2) /**< USART2 source is PCLK1. */
+#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 source is SYSCLK. */
+#define STM32_USART2SEL_HSI (2 << 2) /**< USART2 source is HSI. */
+#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */
+
+#define STM32_USART3SEL_MASK (3 << 4) /**< USART3 mask. */
+#define STM32_USART3SEL_PCLK1 (0 << 4) /**< USART3 source is PCLK1. */
+#define STM32_USART3SEL_SYSCLK (1 << 4) /**< USART3 source is SYSCLK. */
+#define STM32_USART3SEL_HSI (2 << 4) /**< USART3 source is HSI. */
+#define STM32_USART3SEL_LSE (3 << 4) /**< USART3 source is LSE. */
+
+#define STM32_UART4SEL_MASK (3 << 6) /**< UART4 mask. */
+#define STM32_UART4SEL_PCLK1 (0 << 6) /**< UART4 source is PCLK1. */
+#define STM32_UART4SEL_SYSCLK (1 << 6) /**< UART4 source is SYSCLK. */
+#define STM32_UART4SEL_HSI (2 << 6) /**< UART4 source is HSI. */
+#define STM32_UART4SEL_LSE (3 << 6) /**< UART4 source is LSE. */
+
+#define STM32_UART5SEL_MASK (3 << 8) /**< UART5 mask. */
+#define STM32_UART5SEL_PCLK1 (0 << 8) /**< UART5 source is PCLK1. */
+#define STM32_UART5SEL_SYSCLK (1 << 8) /**< UART5 source is SYSCLK. */
+#define STM32_UART5SEL_HSI (2 << 8) /**< UART5 source is HSI. */
+#define STM32_UART5SEL_LSE (3 << 8) /**< UART5 source is LSE. */
+
+#define STM32_USART6SEL_MASK (3 << 10) /**< USART6SEL mask. */
+#define STM32_USART6SEL_PCLK2 (0 << 10) /**< USART6 source is PCLK2. */
+#define STM32_USART6SEL_SYSCLK (1 << 10) /**< USART6 source is SYSCLK. */
+#define STM32_USART6SEL_HSI (2 << 10) /**< USART6 source is HSI. */
+#define STM32_USART6SEL_LSE (3 << 10) /**< USART6 source is LSE. */
+
+#define STM32_UART7SEL_MASK (3 << 12) /**< UART7 mask. */
+#define STM32_UART7SEL_PCLK1 (0 << 12) /**< UART7 source is PCLK1. */
+#define STM32_UART7SEL_SYSCLK (1 << 12) /**< UART7 source is SYSCLK. */
+#define STM32_UART7SEL_HSI (2 << 12) /**< UART7 source is HSI. */
+#define STM32_UART7SEL_LSE (3 << 12) /**< UART7 source is LSE. */
+
+#define STM32_UART8SEL_MASK (3 << 14) /**< UART8 mask. */
+#define STM32_UART8SEL_PCLK1 (0 << 14) /**< UART8 source is PCLK1. */
+#define STM32_UART8SEL_SYSCLK (1 << 14) /**< UART8 source is SYSCLK. */
+#define STM32_UART8SEL_HSI (2 << 14) /**< UART8 source is HSI. */
+#define STM32_UART8SEL_LSE (3 << 14) /**< UART8 source is LSE. */
+
+#define STM32_I2C1SEL_MASK (3 << 16) /**< I2C1SEL mask. */
+#define STM32_I2C1SEL_PCLK1 (0 << 16) /**< I2C1 source is PCLK1. */
+#define STM32_I2C1SEL_SYSCLK (1 << 16) /**< I2C1 source is SYSCLK. */
+#define STM32_I2C1SEL_HSI (2 << 16) /**< I2C1 source is HSI. */
+#define STM32_I2C1SEL_LSE (3 << 16) /**< I2C1 source is LSE. */
+
+#define STM32_I2C2SEL_MASK (3 << 18) /**< I2C2SEL mask. */
+#define STM32_I2C2SEL_PCLK1 (0 << 18) /**< I2C2 source is PCLK1. */
+#define STM32_I2C2SEL_SYSCLK (1 << 18) /**< I2C2 source is SYSCLK. */
+#define STM32_I2C2SEL_HSI (2 << 18) /**< I2C2 source is HSI. */
+#define STM32_I2C2SEL_LSE (3 << 18) /**< I2C2 source is LSE. */
+
+#define STM32_I2C3SEL_MASK (3 << 20) /**< I2C3SEL mask. */
+#define STM32_I2C3SEL_PCLK1 (0 << 20) /**< I2C3 source is PCLK1. */
+#define STM32_I2C3SEL_SYSCLK (1 << 20) /**< I2C3 source is SYSCLK. */
+#define STM32_I2C3SEL_HSI (2 << 20) /**< I2C3 source is HSI. */
+#define STM32_I2C3SEL_LSE (3 << 20) /**< I2C3 source is LSE. */
+
+#define STM32_I2C4SEL_MASK (3 << 22) /**< I2C4SEL mask. */
+#define STM32_I2C4SEL_PCLK1 (0 << 22) /**< I2C4 source is PCLK1. */
+#define STM32_I2C4SEL_SYSCLK (1 << 22) /**< I2C4 source is SYSCLK. */
+#define STM32_I2C4SEL_HSI (2 << 22) /**< I2C4 source is HSI. */
+#define STM32_I2C4SEL_LSE (3 << 22) /**< I2C4 source is LSE. */
+
+#define STM32_LPTIM1SEL_MASK (3 << 24) /**< LPTIM1SEL mask. */
+#define STM32_LPTIM1SEL_PCLK1 (0 << 24) /**< LPTIM1 source is PCLK1. */
+#define STM32_LPTIM1SEL_LSI (1 << 24) /**< LPTIM1 source is LSI. */
+#define STM32_LPTIM1SEL_HSI (2 << 24) /**< LPTIM1 source is HSI. */
+#define STM32_LPTIM1SEL_LSE (3 << 24) /**< LPTIM1 source is LSE. */
+
+#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
+#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
+#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
+
+#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
+#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
+#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
+
+#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
+#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
+#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
+/** @} */
+
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
+#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
+#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
+#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
+#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief Enables the backup RAM regulator.
+ */
+#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)
+#define STM32_BKPRAM_ENABLE FALSE
+#endif
+
+/**
+ * @brief Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED TRUE
+#endif
+
+/**
+ * @brief USB/SDIO clock setting.
+ */
+#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_CLOCK48_REQUIRED TRUE
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLLs.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief PLLM divider value.
+ * @note The allowed values are 2..63.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
+ */
+#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLM_VALUE 25
+#endif
+
+/**
+ * @brief PLLN multiplier value.
+ * @note The allowed values are 192..432.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
+ */
+#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLN_VALUE 432
+#endif
+
+/**
+ * @brief PLLP divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
+ */
+#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLP_VALUE 2
+#endif
+
+/**
+ * @brief PLLQ divider value.
+ * @note The allowed values are 2..15.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
+ */
+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLQ_VALUE 9
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSE
+#endif
+
+/**
+ * @brief RTC HSE prescaler value.
+ * @note The allowed values are 2..31.
+ */
+#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
+#define STM32_RTCPRE_VALUE 25
+#endif
+
+/**
+ * @brief MCO1 clock source value.
+ * @note The default value outputs HSI clock on MCO1 pin.
+ */
+#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#endif
+
+/**
+ * @brief MCO1 prescaler value.
+ * @note The default value outputs HSI clock on MCO1 pin.
+ */
+#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#endif
+
+/**
+ * @brief MCO2 clock source value.
+ * @note The default value outputs SYSCLK / 4 on MCO2 pin.
+ */
+#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#endif
+
+/**
+ * @brief MCO2 prescaler value.
+ * @note The default value outputs SYSCLK / 4 on MCO2 pin.
+ */
+#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
+#endif
+
+/**
+ * @brief I2S clock source.
+ */
+#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
+#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
+#endif
+
+/**
+ * @brief PLLI2SN multiplier value.
+ * @note The allowed values are 49..432.
+ */
+#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SN_VALUE 192
+#endif
+
+/**
+ * @brief PLLI2SP divider value.
+ * @note The allowed values are 2, 4, 6 and 8.
+ */
+#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SP_VALUE 4
+#endif
+
+/**
+ * @brief PLLI2SQ divider value.
+ * @note The allowed values are 2..15.
+ */
+#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SQ_VALUE 4
+#endif
+
+/**
+ * @brief PLLI2SDIVQ divider value (SAI clock divider).
+ */
+#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SDIVQ_VALUE 2
+#endif
+
+/**
+ * @brief PLLI2SR divider value.
+ * @note The allowed values are 2..7.
+ */
+#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SR_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAIN multiplier value.
+ * @note The allowed values are 49..432.
+ */
+#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIN_VALUE 192
+#endif
+
+/**
+ * @brief PLLSAIP divider value.
+ * @note The allowed values are 2, 4, 6 and 8.
+ */
+#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIP_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAIQ divider value.
+ * @note The allowed values are 2..15.
+ */
+#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIQ_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAIR divider value.
+ * @note The allowed values are 2..7.
+ */
+#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIR_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAIDIVQ divider value (SAI clock divider).
+ */
+#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIDIVQ_VALUE 2
+#endif
+
+/**
+ * @brief PLLSAIDIVR divider value (LCD clock divider).
+ */
+#if !defined(STM32_PLLSAIDIVR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIDIVR_VALUE 2
+#endif
+
+/**
+ * @brief SAI1SEL value (SAI1 clock source).
+ */
+#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF
+#endif
+
+/**
+ * @brief SAI2SEL value (SAI2 clock source).
+ */
+#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
+#define STM32_SAI2SEL STM32_SAI2SEL_OFF
+#endif
+
+/**
+ * @brief LCD-TFT clock enable switch.
+ */
+#if !defined(STM32_LCDTFT_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_LCDTFT_REQUIRED FALSE
+#endif
+
+/**
+ * @brief USART1 clock source.
+ */
+#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
+#define STM32_USART1SEL STM32_USART1SEL_PCLK2
+#endif
+
+/**
+ * @brief USART2 clock source.
+ */
+#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
+#define STM32_USART2SEL STM32_USART2SEL_PCLK1
+#endif
+
+/**
+ * @brief USART3 clock source.
+ */
+#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
+#define STM32_USART3SEL STM32_USART3SEL_PCLK1
+#endif
+
+/**
+ * @brief UART4 clock source.
+ */
+#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
+#define STM32_UART4SEL STM32_UART4SEL_PCLK1
+#endif
+
+/**
+ * @brief UART5 clock source.
+ */
+#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
+#define STM32_UART5SEL STM32_UART5SEL_PCLK1
+#endif
+
+/**
+ * @brief USART6 clock source.
+ */
+#if !defined(STM32_USART6SEL) || defined(__DOXYGEN__)
+#define STM32_USART6SEL STM32_USART6SEL_PCLK2
+#endif
+
+/**
+ * @brief UART7 clock source.
+ */
+#if !defined(STM32_UART7SEL) || defined(__DOXYGEN__)
+#define STM32_UART7SEL STM32_UART7SEL_PCLK1
+#endif
+
+/**
+ * @brief UART8 clock source.
+ */
+#if !defined(STM32_UART8SEL) || defined(__DOXYGEN__)
+#define STM32_UART8SEL STM32_UART8SEL_PCLK1
+#endif
+
+/**
+ * @brief I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
+#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
+#endif
+
+/**
+ * @brief I2C2 clock source.
+ */
+#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
+#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
+#endif
+
+/**
+ * @brief I2C3 clock source.
+ */
+#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
+#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
+#endif
+
+/**
+ * @brief I2C4 clock source.
+ */
+#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
+#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
+#endif
+
+/**
+ * @brief LPTIM1 clock source.
+ */
+#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
+#endif
+
+/**
+ * @brief CEC clock source.
+ */
+#if !defined(STM32_CECSEL) || defined(__DOXYGEN__)
+#define STM32_CECSEL STM32_CECSEL_LSE
+#endif
+
+/**
+ * @brief PLL48CLK clock source.
+ */
+#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__)
+#define STM32_CK48MSEL STM32_CK48MSEL_PLL
+#endif
+
+/**
+ * @brief SDMMC clock source.
+ */
+#if !defined(STM32_SDMMCSEL) || defined(__DOXYGEN__)
+#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
+#endif
+
+/**
+ * @brief SRAM2 cache-ability.
+ * @note This setting uses the MPU region 7 if at @p TRUE.
+ */
+#if !defined(STM32_SRAM2_NOCACHE) || defined(__DOXYGEN__)
+#define STM32_SRAM2_NOCACHE FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F7xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F7xx_MCUCONF not defined"
+#endif
+
+/*
+ * Board file checks.
+ */
+#if !defined(STM32_LSECLK)
+#error "STM32_LSECLK not defined in board.h"
+#endif
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined in board.h"
+#endif
+#if !defined(STM32_HSECLK)
+#error "STM32_HSECLK not defined in board.h"
+#endif
+#if !defined(STM32_VDD)
+#error "STM32_VDD not defined in board.h"
+#endif
+
+/**
+ * @brief Maximum frequency thresholds and wait states for flash access.
+ * @note The values are valid for 2.7V to 3.6V supply range.
+ */
+#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
+#define STM32_0WS_THRESHOLD 30000000
+#define STM32_1WS_THRESHOLD 60000000
+#define STM32_2WS_THRESHOLD 90000000
+#define STM32_3WS_THRESHOLD 120000000
+#define STM32_4WS_THRESHOLD 150000000
+#define STM32_5WS_THRESHOLD 180000000
+#define STM32_6WS_THRESHOLD 210000000
+#define STM32_7WS_THRESHOLD 0
+#define STM32_8WS_THRESHOLD 0
+
+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
+#define STM32_0WS_THRESHOLD 24000000
+#define STM32_1WS_THRESHOLD 48000000
+#define STM32_2WS_THRESHOLD 72000000
+#define STM32_3WS_THRESHOLD 96000000
+#define STM32_4WS_THRESHOLD 120000000
+#define STM32_5WS_THRESHOLD 144000000
+#define STM32_6WS_THRESHOLD 168000000
+#define STM32_7WS_THRESHOLD 192000000
+#define STM32_8WS_THRESHOLD 0
+
+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
+#define STM32_0WS_THRESHOLD 22000000
+#define STM32_1WS_THRESHOLD 44000000
+#define STM32_2WS_THRESHOLD 66000000
+#define STM32_3WS_THRESHOLD 88000000
+#define STM32_4WS_THRESHOLD 110000000
+#define STM32_5WS_THRESHOLD 132000000
+#define STM32_6WS_THRESHOLD 154000000
+#define STM32_7WS_THRESHOLD 176000000
+#define STM32_8WS_THRESHOLD 198000000
+
+#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
+#define STM32_0WS_THRESHOLD 20000000
+#define STM32_1WS_THRESHOLD 40000000
+#define STM32_2WS_THRESHOLD 60000000
+#define STM32_3WS_THRESHOLD 80000000
+#define STM32_4WS_THRESHOLD 100000000
+#define STM32_5WS_THRESHOLD 120000000
+#define STM32_6WS_THRESHOLD 140000000
+#define STM32_7WS_THRESHOLD 160000000
+#define STM32_8WS_THRESHOLD 0
+
+#else
+#error "invalid VDD voltage specified"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \
+ ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCO1SEL"
+#endif
+
+#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_MCO2SEL"
+#endif
+
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_I2SSRC"
+#endif
+
+#if ((STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SAI1SEL"
+#endif
+
+#if ((STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SAI2SEL"
+#endif
+
+#if STM32_LCDTFT_REQUIRED && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_LCDTFT_REQUIRED"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#else /* STM32_HSECLK != 0 */
+#if defined(STM32_HSE_BYPASS)
+#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)"
+#endif
+#else /* !defined(STM32_HSE_BYPASS) */
+#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+#endif /* !defined(STM32_HSE_BYPASS) */
+#endif /* STM32_HSECLK != 0 */
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \
+ ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCO1SEL"
+#endif
+
+#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \
+ ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCO2SEL"
+#endif
+
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_I2SSRC"
+#endif
+
+#if ((STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) | \
+ (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SAI1SEL"
+#endif
+
+#if ((STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) | \
+ (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SAI2SEL"
+#endif
+
+#if STM32_LCDTFT_REQUIRED && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_LCDTFT_REQUIRED"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined"
+#endif
+
+#if (STM32_LSEDRV >> 3) > 3
+#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#if STM32_MCO1SEL == STM32_MCO1SEL_LSE
+#error "LSE not enabled, required by STM32_MCO1SEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/**
+ * @brief STM32_PLLM field.
+ */
+#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLM (STM32_PLLM_VALUE << 0)
+#else
+#error "invalid STM32_PLLM_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLs input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
+
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/*
+ * PLLs input frequency range check.
+ */
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/*
+ * PLL enable check.
+ */
+#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLL)) || \
+ (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \
+ (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/**
+ * @brief STM32_PLLN field.
+ */
+#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLN (STM32_PLLN_VALUE << 6)
+#else
+#error "invalid STM32_PLLN_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLP field.
+ */
+#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLP (0 << 16)
+
+#elif STM32_PLLP_VALUE == 4
+#define STM32_PLLP (1 << 16)
+
+#elif STM32_PLLP_VALUE == 6
+#define STM32_PLLP (2 << 16)
+
+#elif STM32_PLLP_VALUE == 8
+#define STM32_PLLP (3 << 16)
+
+#else
+#error "invalid STM32_PLLP_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLQ field.
+ */
+#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLQ (STM32_PLLQ_VALUE << 24)
+#else
+#error "invalid STM32_PLLQ_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL VCO frequency.
+ */
+#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
+
+/*
+ * PLL VCO frequency range check.
+ */
+#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLL P output clock frequency.
+ */
+#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
+
+/**
+ * @brief PLL Q output clock frequency.
+ */
+#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
+
+/*
+ * PLL output frequency range check.
+ */
+#if (STM32_PLL_P_CLKOUT < STM32_PLLOUT_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+#define STM32_SYSCLK STM32_HSICLK
+
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK STM32_HSICLK
+
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+
+#elif (STM32_SW == STM32_SW_PLL)
+#define STM32_SYSCLK STM32_PLL_P_CLKOUT
+
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/* Calculating VOS settings.*/
+#if STM32_SYSCLK <= 144000000
+#define STM32_VOS STM32_VOS_SCALE3
+#define STM32_OVERDRIVE_REQUIRED FALSE
+
+#elif STM32_SYSCLK <= 168000000
+#define STM32_VOS STM32_VOS_SCALE2
+#define STM32_OVERDRIVE_REQUIRED FALSE
+
+#elif STM32_SYSCLK <= 180000000
+#define STM32_VOS STM32_VOS_SCALE1
+#define STM32_OVERDRIVE_REQUIRED FALSE
+
+#else
+#define STM32_VOS STM32_VOS_SCALE1
+#define STM32_OVERDRIVE_REQUIRED TRUE
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/*
+ * AHB frequency check.
+ */
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1 (STM32_HCLK / 1)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1 (STM32_HCLK / 2)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1 (STM32_HCLK / 4)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1 (STM32_HCLK / 8)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1 (STM32_HCLK / 16)
+
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/*
+ * APB1 frequency check.
+ */
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2 (STM32_HCLK / 1)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2 (STM32_HCLK / 2)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2 (STM32_HCLK / 4)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2 (STM32_HCLK / 8)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2 (STM32_HCLK / 16)
+
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/*
+ * APB2 frequency check.
+ */
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/*
+ * PLLI2S enable check.
+ */
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLLI2S activation flag.
+ */
+#define STM32_ACTIVATE_PLLI2S TRUE
+#else
+#define STM32_ACTIVATE_PLLI2S FALSE
+#endif
+
+/**
+ * @brief STM32_PLLI2SN field.
+ */
+#if ((STM32_PLLI2SN_VALUE >= 49) && (STM32_PLLI2SN_VALUE <= 432)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
+#else
+#error "invalid STM32_PLLI2SN_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLI2SQ field.
+ */
+#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24)
+#else
+#error "invalid STM32_PLLI2SQ_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLI2SR field.
+ */
+#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28)
+#else
+#error "invalid STM32_PLLI2SR_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLI2SP field.
+ */
+#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLI2SP (0 << 16)
+
+#elif STM32_PLLI2SP_VALUE == 4
+#define STM32_PLLI2SP (1 << 16)
+
+#elif STM32_PLLI2SP_VALUE == 6
+#define STM32_PLLI2SP (2 << 16)
+
+#elif STM32_PLLI2SP_VALUE == 8
+#define STM32_PLLI2SP (3 << 16)
+
+#else
+#error "invalid STM32_PLLI2SP_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLI2S VCO frequency.
+ */
+#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)
+
+/*
+ * PLLI2S VCO frequency range check.
+ */
+#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
+ (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLLI2S P output clock frequency.
+ */
+#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE)
+
+/**
+ * @brief PLLI2S Q output clock frequency.
+ */
+#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)
+
+/**
+ * @brief PLLI2S R output clock frequency.
+ */
+#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
+
+/**
+ * @brief STM32_PLLI2SDIVQ field.
+ */
+#if (STM32_PLLI2SDIVQ_VALUE < 1) || (STM32_PLLI2SDIVQ_VALUE > 32)
+#error "STM32_PLLI2SDIVQ_VALUE out of acceptable range"
+#endif
+#define STM32_PLLI2SDIVQ ((STM32_PLLI2SDIVQ_VALUE - 1) << 0)
+
+/**
+ * @brief PLLI2S Q output clock frequency after divisor.
+ */
+#define STM32_PLLI2SDIVQ_CLKOUT (STM32_PLLI2S_Q_CLKOUT / STM32_PLLI2SDIVQ_VALUE)
+
+/*
+ * PLLSAI enable check.
+ */
+#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \
+ STM32_LCDTFT_REQUIRED || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLLSAI activation flag.
+ */
+#define STM32_ACTIVATE_PLLSAI TRUE
+#else
+#define STM32_ACTIVATE_PLLSAI FALSE
+#endif
+
+/**
+ * @brief STM32_PLLSAIN field.
+ */
+#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6)
+#else
+#error "invalid STM32_PLLSAIN_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIQ field.
+ */
+#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24)
+#else
+#error "invalid STM32_PLLSAIR_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIR field.
+ */
+#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28)
+#else
+#error "invalid STM32_PLLSAIR_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIP field.
+ */
+#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAIP (0 << 16)
+
+#elif STM32_PLLSAIP_VALUE == 4
+#define STM32_PLLSAIP (1 << 16)
+
+#elif STM32_PLLSAIP_VALUE == 6
+#define STM32_PLLSAIP (2 << 16)
+
+#elif STM32_PLLSAIP_VALUE == 8
+#define STM32_PLLSAIP (3 << 16)
+
+#else
+#error "invalid STM32_PLLSAIP_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLSAI VCO frequency.
+ */
+#define STM32_PLLSAIVCO (STM32_PLLCLKIN * STM32_PLLSAIN_VALUE)
+
+/*
+ * PLLSAI VCO frequency range check.
+ */
+#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \
+ (STM32_PLLSAIVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLLSAI P output clock frequency.
+ */
+#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
+
+/**
+ * @brief PLLSAI Q output clock frequency.
+ */
+#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
+
+/**
+ * @brief PLLSAI R output clock frequency.
+ */
+#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
+
+/**
+ * @brief STM32_PLLSAIDIVQ field.
+ */
+#if (STM32_PLLSAIDIVQ_VALUE < 1) || (STM32_PLLSAIDIVQ_VALUE > 32)
+#error "STM32_PLLSAIDIVQ_VALUE out of acceptable range"
+#endif
+#define STM32_PLLSAIDIVQ ((STM32_PLLSAIDIVQ_VALUE - 1) << 8)
+
+/**
+ * @brief PLLSAI Q output clock frequency after divisor.
+ */
+#define STM32_PLLSAIDIVQ_CLKOUT (STM32_PLLSAI_Q_CLKOUT / STM32_PLLSAIDIVQ_VALUE)
+
+/*
+ * STM32_PLLSAIDIVR field.
+ */
+#if (STM32_PLLSAIDIVR_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAIDIVR (0 << 16)
+
+#elif STM32_PLLSAIDIVR_VALUE == 4
+#define STM32_PLLSAIDIVR (1 << 16)
+
+#elif STM32_PLLSAIDIVR_VALUE == 8
+#define STM32_PLLSAIDIVR (2 << 16)
+
+#elif STM32_PLLSAIDIVR_VALUE == 16
+#define STM32_PLLSAIDIVR (3 << 16)
+
+#else
+#error "invalid STM32_PLLSAIDIVR_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLSAI R output clock frequency after divisor.
+ */
+#define STM32_PLLSAIDIVR_CLKOUT (STM32_PLLSAI_R_CLKOUT / STM32_PLLSAIDIVR_VALUE)
+
+/**
+ * @brief MCO1 divider clock.
+ */
+#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
+#define STM32_MCO1DIVCLK STM32_HSICLK
+
+#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
+#define STM32_MCO1DIVCLK STM32_LSECLK
+
+#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
+#define STM32_MCO1DIVCLK STM32_HSECLK
+
+#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
+#define STM32_MCO1DIVCLK STM32_PLL_P_CLKOUT
+
+#else
+#error "invalid STM32_MCO1SEL value specified"
+#endif
+
+/**
+ * @brief MCO1 output pin clock.
+ */
+#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCO1CLK STM32_MCO1DIVCLK
+
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
+
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
+
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
+
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
+
+#else
+#error "invalid STM32_MCO1PRE value specified"
+#endif
+
+/**
+ * @brief MCO2 divider clock.
+ */
+#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
+#define STM32_MCO2DIVCLK STM32_HSECLK
+
+#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
+#define STM32_MCO2DIVCLK STM32_PLL_P_CLKOUT
+
+#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2DIVCLK STM32_SYSCLK
+
+#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
+#define STM32_MCO2DIVCLK STM32_PLLI2S
+
+#else
+#error "invalid STM32_MCO2SEL value specified"
+#endif
+
+/**
+ * @brief MCO2 output pin clock.
+ */
+#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCO2CLK STM32_MCO2DIVCLK
+
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
+
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
+
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
+
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
+
+#else
+#error "invalid STM32_MCO2PRE value specified"
+#endif
+
+/**
+ * @brief RTC HSE divider setting.
+ */
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief HSE divider toward RTC clock.
+ */
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK 0
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK STM32_LSECLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK STM32_HSEDIVCLK
+
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief USART1 frequency.
+ */
+#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
+#define STM32_USART1CLK STM32_PCLK2
+#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
+#define STM32_USART1CLK STM32_SYSCLK
+#elif STM32_USART1SEL == STM32_USART1SEL_HSI
+#define STM32_USART1CLK STM32_HSICLK
+#elif STM32_USART1SEL == STM32_USART1SEL_LSE
+#define STM32_USART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief USART2 frequency.
+ */
+#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_USART2CLK STM32_PCLK1
+#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
+#define STM32_USART2CLK STM32_SYSCLK
+#elif STM32_USART2SEL == STM32_USART2SEL_HSI
+#define STM32_USART2CLK STM32_HSICLK
+#elif STM32_USART2SEL == STM32_USART2SEL_LSE
+#define STM32_USART2CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART2 clock"
+#endif
+
+/**
+ * @brief USART3 frequency.
+ */
+#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_USART3CLK STM32_PCLK1
+#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
+#define STM32_USART3CLK STM32_SYSCLK
+#elif STM32_USART3SEL == STM32_USART3SEL_HSI
+#define STM32_USART3CLK STM32_HSICLK
+#elif STM32_USART3SEL == STM32_USART3SEL_LSE
+#define STM32_USART3CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART3 clock"
+#endif
+
+/**
+ * @brief UART4 frequency.
+ */
+#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_UART4CLK STM32_PCLK1
+#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
+#define STM32_UART4CLK STM32_SYSCLK
+#elif STM32_UART4SEL == STM32_UART4SEL_HSI
+#define STM32_UART4CLK STM32_HSICLK
+#elif STM32_UART4SEL == STM32_UART4SEL_LSE
+#define STM32_UART4CLK STM32_LSECLK
+#else
+#error "invalid source selected for UART4 clock"
+#endif
+
+/**
+ * @brief UART5 frequency.
+ */
+#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_UART5CLK STM32_PCLK1
+#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
+#define STM32_UART5CLK STM32_SYSCLK
+#elif STM32_UART5SEL == STM32_UART5SEL_HSI
+#define STM32_UART5CLK STM32_HSICLK
+#elif STM32_UART5SEL == STM32_UART5SEL_LSE
+#define STM32_UART5CLK STM32_LSECLK
+#else
+#error "invalid source selected for UART5 clock"
+#endif
+
+/**
+ * @brief USART6 frequency.
+ */
+#if (STM32_USART6SEL == STM32_USART6SEL_PCLK2) || defined(__DOXYGEN__)
+#define STM32_USART6CLK STM32_PCLK2
+#elif STM32_USART6SEL == STM32_USART6SEL_SYSCLK
+#define STM32_USART6CLK STM32_SYSCLK
+#elif STM32_USART6SEL == STM32_USART6SEL_HSI
+#define STM32_USART6CLK STM32_HSICLK
+#elif STM32_USART6SEL == STM32_USART6SEL_LSE
+#define STM32_USART6CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART6 clock"
+#endif
+
+/**
+ * @brief UART7 frequency.
+ */
+#if (STM32_UART7SEL == STM32_UART7SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_UART7CLK STM32_PCLK1
+#elif STM32_UART7SEL == STM32_UART7SEL_SYSCLK
+#define STM32_UART7CLK STM32_SYSCLK
+#elif STM32_UART7SEL == STM32_UART7SEL_HSI
+#define STM32_UART7CLK STM32_HSICLK
+#elif STM32_UART7SEL == STM32_UART7SEL_LSE
+#define STM32_UART7CLK STM32_LSECLK
+#else
+#error "invalid source selected for UART7 clock"
+#endif
+
+/**
+ * @brief UART8 frequency.
+ */
+#if (STM32_UART8SEL == STM32_UART8SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_UART8CLK STM32_PCLK1
+#elif STM32_UART8SEL == STM32_UART8SEL_SYSCLK
+#define STM32_UART8CLK STM32_SYSCLK
+#elif STM32_UART8SEL == STM32_UART8SEL_HSI
+#define STM32_UART8CLK STM32_HSICLK
+#elif STM32_UART8SEL == STM32_UART8SEL_LSE
+#define STM32_UART8CLK STM32_LSECLK
+#else
+#error "invalid source selected for UART8 clock"
+#endif
+
+/**
+ * @brief I2C1 frequency.
+ */
+#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C1CLK STM32_PCLK1
+#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
+#define STM32_I2C1CLK STM32_SYSCLK
+#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI
+#define STM32_I2C1CLK STM32_HSICLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief I2C2 frequency.
+ */
+#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C2CLK STM32_PCLK1
+#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
+#define STM32_I2C2CLK STM32_SYSCLK
+#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI
+#define STM32_I2C2CLK STM32_HSICLK
+#else
+#error "invalid source selected for I2C2 clock"
+#endif
+
+/**
+ * @brief I2C3 frequency.
+ */
+#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C3CLK STM32_PCLK1
+#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
+#define STM32_I2C3CLK STM32_SYSCLK
+#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI
+#define STM32_I2C3CLK STM32_HSICLK
+#else
+#error "invalid source selected for I2C3 clock"
+#endif
+
+/**
+ * @brief I2C4 frequency.
+ */
+#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C4CLK STM32_PCLK1
+#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
+#define STM32_I2C4CLK STM32_SYSCLK
+#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI
+#define STM32_I2C4CLK STM32_HSICLK
+#else
+#error "invalid source selected for I2C4 clock"
+#endif
+
+/**
+ * @brief LPTIM1 frequency.
+ */
+#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_LPTIM1CLK STM32_PCLK1
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
+#define STM32_LPTIM1CLK STM32_LSICLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI
+#define STM32_LPTIM1CLK STM32_HSICLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
+#define STM32_LPTIM1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPTIM1 clock"
+#endif
+
+/**
+ * @brief 48MHz frequency.
+ */
+#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
+#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
+#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
+#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI
+#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
+#else
+#error "invalid source selected for PLL48CLK clock"
+#endif
+#else /* !STM32_CLOCK48_REQUIRED */
+#define STM32_PLL48CLK 0
+#endif /* !STM32_CLOCK48_REQUIRED */
+
+/**
+ * @brief I2S frequency.
+ */
+#if (STM32_I2SSRC == STM32_I2SSRC_OFF) || defined(__DOXYGEN__)
+#define STM32_I2SCLK 0
+#elif STM32_I2SSRC == STM32_I2SSRC_CKIN
+#define STM32_I2SCLK 0 /* Unknown, would require a board value */
+#elif STM32_I2SSRC == STM32_I2SSRC_PLLI2S
+#define STM32_I2SCLK STM32_PLLI2S_R_CLKOUT
+#else
+#error "invalid source selected for I2S clock"
+#endif
+
+/**
+ * @brief SAI1 frequency.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_OFF) || defined(__DOXYGEN__)
+#define STM32_SAI1CLK 0
+#elif STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL
+#define STM32_SAI1CLK STM32_PLLSAIDIVQ_CLKOUT
+#elif STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL
+#define STM32_SAI1CLK STM32_PLLI2SDIVQ_CLKOUT
+#elif STM32_SAI1SEL == STM32_SAI1SEL_CKIN
+#define STM32_SAI1CLK 0 /* Unknown, would require a board value */
+#else
+#error "invalid source selected for SAI1 clock"
+#endif
+
+/**
+ * @brief SAI2 frequency.
+ */
+#if (STM32_SAI2SEL == STM32_SAI2SEL_OFF) || defined(__DOXYGEN__)
+#define STM32_SAI2CLK 0
+#elif STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL
+#define STM32_SAI2CLK STM32_PLLSAIDIVQ_CLKOUT
+#elif STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL
+#define STM32_SAI2CLK STM32_PLLI2SDIVQ_CLKOUT
+#elif STM32_SAI2SEL == STM32_SAI2SEL_CKIN
+#define STM32_SAI2CLK 0 /* Unknown, would require a board value */
+#else
+#error "invalid source selected for SAI2 clock"
+#endif
+
+/**
+ * @brief SDMMC frequency.
+ */
+#if (STM32_SDMMCSEL == STM32_SDMMCSEL_PLL48CLK) || defined(__DOXYGEN__)
+#define STM32_SDMMCCLK STM32_PLL48CLK
+#elif STM32_SDMMCSEL == STM32_SDMMCSEL_SYSCLK
+#define STM32_SDMMCCLK STM32_SYSCLK
+#else
+#error "invalid source selected for SDMMC clock"
+#endif
+
+/**
+ * @brief Clock of timers connected to APB1
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Clock of timers connected to APB2.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS 0x00000000
+
+#elif STM32_HCLK <= STM32_1WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000001
+
+#elif STM32_HCLK <= STM32_2WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000002
+
+#elif STM32_HCLK <= STM32_3WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000003
+
+#elif STM32_HCLK <= STM32_4WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000004
+
+#elif STM32_HCLK <= STM32_5WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000005
+
+#elif STM32_HCLK <= STM32_6WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000006
+
+#elif STM32_HCLK <= STM32_7WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000007
+
+#elif STM32_HCLK <= STM32_8WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000008
+
+#else
+#define STM32_FLASHBITS 0x00000009
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "mpu.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/platform.mk
new file mode 100644
index 0000000000..42044c994e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/platform.mk
@@ -0,0 +1,36 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
new file mode 100644
index 0000000000..0db4d6d5f8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
@@ -0,0 +1,1653 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F7xx/stm32_rcc.h
+ * @brief RCC helper driver header.
+ * @note This file requires definitions from the ST header file
+ * @p stm32f7xx.h.
+ *
+ * @addtogroup STM32F7xx_RCC
+ * @{
+ */
+#ifndef _STM32_RCC_
+#define _STM32_RCC_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1(mask, lp) { \
+ RCC->APB1ENR |= (mask); \
+ if (lp) \
+ RCC->APB1LPENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1(mask, lp) { \
+ RCC->APB1ENR &= ~(mask); \
+ if (lp) \
+ RCC->APB1LPENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1(mask) { \
+ RCC->APB1RSTR |= (mask); \
+ RCC->APB1RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) { \
+ RCC->APB2ENR |= (mask); \
+ if (lp) \
+ RCC->APB2LPENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask, lp) { \
+ RCC->APB2ENR &= ~(mask); \
+ if (lp) \
+ RCC->APB2LPENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) { \
+ RCC->APB2RSTR |= (mask); \
+ RCC->APB2RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB1(mask, lp) { \
+ RCC->AHB1ENR |= (mask); \
+ if (lp) \
+ RCC->AHB1LPENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB1(mask, lp) { \
+ RCC->AHB1ENR &= ~(mask); \
+ if (lp) \
+ RCC->AHB1LPENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB1(mask) { \
+ RCC->AHB1RSTR |= (mask); \
+ RCC->AHB1RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB2(mask, lp) { \
+ RCC->AHB2ENR |= (mask); \
+ if (lp) \
+ RCC->AHB2LPENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB2(mask, lp) { \
+ RCC->AHB2ENR &= ~(mask); \
+ if (lp) \
+ RCC->AHB2LPENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB2(mask) { \
+ RCC->AHB2RSTR |= (mask); \
+ RCC->AHB2RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB3(mask, lp) { \
+ RCC->AHB3ENR |= (mask); \
+ if (lp) \
+ RCC->AHB3LPENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB3(mask, lp) { \
+ RCC->AHB3ENR &= ~(mask); \
+ if (lp) \
+ RCC->AHB3LPENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB3(mask) { \
+ RCC->AHB3RSTR |= (mask); \
+ RCC->AHB3RSTR = 0; \
+}
+/** @} */
+
+/**
+ * @name ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ADC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief Disables the ADC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief Resets the ADC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
+
+/**
+ * @brief Enables the ADC2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp)
+
+/**
+ * @brief Disables the ADC2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp)
+
+/**
+ * @brief Resets the ADC2 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)
+
+/**
+ * @brief Enables the ADC3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp)
+
+/**
+ * @brief Disables the ADC3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp)
+
+/**
+ * @brief Resets the ADC3 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
+/** @} */
+
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
+/** @} */
+
+/**
+ * @name DMA peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
+
+/**
+ * @brief Disables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
+
+/**
+ * @brief Enables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
+
+/**
+ * @brief Disables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp)
+
+/**
+ * @brief Resets the DMA2 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
+/** @} */
+
+/**
+ * @name BKPSRAM specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the BKPSRAM peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)
+
+/**
+ * @brief Disables the BKPSRAM peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableBKPSRAM(lp) rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)
+/** @} */
+
+/**
+ * @name PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
+/** @} */
+
+/**
+ * @name CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CAN1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
+
+/**
+ * @brief Disables the CAN1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
+
+/**
+ * @brief Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
+
+/**
+ * @brief Enables the CAN2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)
+
+/**
+ * @brief Disables the CAN2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)
+
+/**
+ * @brief Resets the CAN2 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)
+
+/**
+ * @brief Resets the CAN3 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN3() rccResetAPB1(RCC_APB1RSTR_CAN3RST)
+
+/**
+ * @brief Enables the CAN3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN3(lp) rccEnableAPB1(RCC_APB1ENR_CAN3EN, lp)
+
+/**
+ * @brief Disables the CAN3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN3(lp) rccDisableAPB1(RCC_APB1ENR_CAN3EN, lp)
+/** @} */
+
+/**
+ * @name ETH peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ETH peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
+ RCC_AHB1ENR_ETHMACTXEN | \
+ RCC_AHB1ENR_ETHMACRXEN, lp)
+
+/**
+ * @brief Disables the ETH peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
+ RCC_AHB1ENR_ETHMACTXEN | \
+ RCC_AHB1ENR_ETHMACRXEN, lp)
+
+/**
+ * @brief Resets the ETH peripheral.
+ *
+ * @api
+ */
+#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
+/** @} */
+
+/**
+ * @name I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Disables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
+
+/**
+ * @brief Enables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Disables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+
+/**
+ * @brief Enables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp)
+
+/**
+ * @brief Disables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp)
+
+/**
+ * @brief Resets the I2C3 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
+
+/**
+ * @brief Enables the I2C4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C4(lp) rccEnableAPB1(RCC_APB1ENR_I2C4EN, lp)
+
+/**
+ * @brief Disables the I2C4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C4(lp) rccDisableAPB1(RCC_APB1ENR_I2C4EN, lp)
+
+/**
+ * @brief Resets the I2C4 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C4() rccResetAPB1(RCC_APB1RSTR_I2C4RST)
+/** @} */
+
+/**
+ * @name OTG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
+
+/**
+ * @brief Disables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
+
+/**
+ * @brief Resets the OTG_FS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
+
+/**
+ * @brief Enables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
+
+/**
+ * @brief Disables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
+
+/**
+ * @brief Resets the OTG_HS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST)
+
+/**
+ * @brief Enables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
+
+/**
+ * @brief Disables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
+/** @} */
+
+/**
+ * @name QUADSPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Disables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Resets the QUADSPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
+/** @} */
+
+/**
+ * @name SDMMC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SDMMC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
+
+/**
+ * @brief Disables the SDMMC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSDMMC1(lp) rccDisableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
+
+/**
+ * @brief Resets the SDMMC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST)
+/** @} */
+
+/**
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Disables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief Enables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Disables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+
+/**
+ * @brief Enables the SPI3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Disables the SPI3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
+
+/**
+ * @brief Enables the SPI4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
+
+/**
+ * @brief Disables the SPI4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI4(lp) rccDisableAPB2(RCC_APB2ENR_SPI4EN, lp)
+
+/**
+ * @brief Resets the SPI4 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
+
+/**
+ * @brief Enables the SPI5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp)
+
+/**
+ * @brief Disables the SPI5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI5(lp) rccDisableAPB2(RCC_APB2ENR_SPI5EN, lp)
+
+/**
+ * @brief Resets the SPI5 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST)
+
+/**
+ * @brief Enables the SPI6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp)
+
+/**
+ * @brief Disables the SPI6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI6(lp) rccDisableAPB2(RCC_APB2ENR_SPI6EN, lp)
+
+/**
+ * @brief Resets the SPI6 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST)
+/** @} */
+
+/**
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Disables the TIM1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
+/**
+ * @brief Enables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Disables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
+/**
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+
+/**
+ * @brief Enables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief Disables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+
+/**
+ * @brief Enables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
+
+/**
+ * @brief Disables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)
+
+/**
+ * @brief Resets the TIM5 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
+ * @brief Enables the TIM8 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Disables the TIM8 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
+
+/**
+ * @brief Enables the TIM9 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
+
+/**
+ * @brief Disables the TIM9 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)
+
+/**
+ * @brief Resets the TIM9 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
+
+/**
+ * @brief Enables the TIM10 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
+
+/**
+ * @brief Disables the TIM10 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
+
+/**
+ * @brief Resets the TIM10 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
+
+/**
+ * @brief Enables the TIM11 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)
+
+/**
+ * @brief Disables the TIM11 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp)
+
+/**
+ * @brief Resets the TIM11 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)
+
+/**
+ * @brief Enables the TIM12 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)
+
+/**
+ * @brief Disables the TIM12 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp)
+
+/**
+ * @brief Resets the TIM12 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
+
+/**
+ * @brief Enables the TIM13 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Disables the TIM13 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Resets the TIM13 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
+
+/**
+ * @brief Enables the TIM14 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
+
+/**
+ * @brief Disables the TIM14 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp)
+
+/**
+ * @brief Resets the TIM14 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
+/** @} */
+
+/**
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Disables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief Enables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Disables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
+
+/**
+ * @brief Enables the USART6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
+
+/**
+ * @brief Disables the USART6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)
+
+/**
+ * @brief Resets the USART6 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
+
+/**
+ * @brief Enables the UART7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART7(lp) rccEnableAPB1(RCC_APB1ENR_UART7EN, lp)
+
+/**
+ * @brief Disables the UART7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART7(lp) rccDisableAPB1(RCC_APB1ENR_UART7EN, lp)
+
+/**
+ * @brief Resets the UART7 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART7() rccResetAPB1(RCC_APB1RSTR_UART7RST)
+
+/**
+ * @brief Enables the UART8 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART8(lp) rccEnableAPB1(RCC_APB1ENR_UART8EN, lp)
+
+/**
+ * @brief Disables the UART8 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART8(lp) rccDisableAPB1(RCC_APB1ENR_UART8EN, lp)
+
+/**
+ * @brief Resets the UART8 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART8() rccResetAPB1(RCC_APB1RSTR_UART8RST)
+/** @} */
+
+/**
+ * @name LTDC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the LTDC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp)
+
+/**
+ * @brief Disables the LTDC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableLTDC(lp) rccDisableAPB2(RCC_APB2ENR_LTDCEN, lp)
+
+/**
+ * @brief Resets the LTDC peripheral.
+ *
+ * @api
+ */
+#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)
+
+/**
+ * @name DMA2D peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA2D peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
+
+/**
+ * @brief Disables the DMA2D peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
+
+/**
+ * @brief Resets the DMA2D peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)
+/** @} */
+
+/**
+ * @name FSMC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#if defined(STM32_FSMC_IS_FMC)
+ #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
+#else
+ #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp)
+#endif
+
+/**
+ * @brief Disables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#if defined(STM32_FSMC_IS_FMC)
+ #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp)
+#else
+ #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FSMCEN, lp)
+#endif
+
+/**
+ * @brief Resets the FSMC peripheral.
+ *
+ * @api
+ */
+#if defined(STM32_FSMC_IS_FMC)
+ #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
+#else
+ #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST)
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_RCC_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
new file mode 100644
index 0000000000..5681c03a92
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
@@ -0,0 +1,1034 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F7xx/stm32_registry.h
+ * @brief STM32F7xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32F7xx capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* STM32F745xx, STM32F746xx, STM32F756xx. */
+/*===========================================================================*/
+#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) || \
+ defined(__DOXYGEN__)
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00001100
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_ADC3_DMA_CHN 0x00000022
+
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_CAN_MAX_FILTERS 28
+
+#define STM32_HAS_CAN1 TRUE
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+
+#define STM32_HAS_CAN2 TRUE
+#define STM32_CAN2_TX_HANDLER Vector13C
+#define STM32_CAN2_RX0_HANDLER Vector140
+#define STM32_CAN2_RX1_HANDLER Vector144
+#define STM32_CAN2_SCE_HANDLER Vector148
+#define STM32_CAN2_TX_NUMBER 63
+#define STM32_CAN2_RX0_NUMBER 64
+#define STM32_CAN2_RX1_NUMBER 65
+#define STM32_CAN2_SCE_NUMBER 66
+
+#define STM32_CAN3_MAX_FILTERS 14
+
+#define STM32_HAS_CAN3 TRUE
+#define STM32_CAN3_TX_HANDLER Vector1E0
+#define STM32_CAN3_RX0_HANDLER Vector1E4
+#define STM32_CAN3_RX1_HANDLER Vector1E8
+#define STM32_CAN3_SCE_HANDLER Vector1EC
+#define STM32_CAN3_TX_NUMBER 104
+#define STM32_CAN3_RX0_NUMBER 105
+#define STM32_CAN3_RX1_NUMBER 106
+#define STM32_CAN3_SCE_NUMBER 107
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_DAC1_CH1_DMA_CHN 0x00700000
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_DAC1_CH2_DMA_CHN 0x07000000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING TRUE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH TRUE
+#define STM32_ETH_HANDLER Vector134
+#define STM32_ETH_NUMBER 61
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 24
+#define STM32_EXTI_IMR_MASK 0xFF000000
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOI TRUE
+#define STM32_HAS_GPIOJ TRUE
+#define STM32_HAS_GPIOK TRUE
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN | \
+ RCC_AHB1ENR_GPIOFEN | \
+ RCC_AHB1ENR_GPIOGEN | \
+ RCC_AHB1ENR_GPIOHEN | \
+ RCC_AHB1ENR_GPIOIEN | \
+ RCC_AHB1ENR_GPIOJEN | \
+ RCC_AHB1ENR_GPIOKEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_NUMBER 32
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_NUMBER 34
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_NUMBER 73
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
+
+#define STM32_HAS_I2C4 TRUE
+#define STM32_I2C4_EVENT_HANDLER Vector1BC
+#define STM32_I2C4_ERROR_HANDLER Vector1C0
+#define STM32_I2C4_EVENT_NUMBER 95
+#define STM32_I2C4_ERROR_NUMBER 96
+#define STM32_I2C4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C4_RX_DMA_CHN 0x00000200
+#define STM32_I2C4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C4_TX_DMA_CHN 0x00200000
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector1B0
+#define STM32_QUADSPI1_NUMBER 92
+#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_QUADSPI1_DMA_CHN 0x30000000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 TRUE
+#define STM32_SDMMC1_HANDLER Vector104
+#define STM32_SDMMC1_NUMBER 49
+#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDMMC1_DMA_CHN 0x04004000
+
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX TRUE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI4_RX_DMA_CHN 0x00005004
+#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN 0x00050040
+
+#define STM32_HAS_SPI5 TRUE
+#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI5_RX_DMA_CHN 0x00702000
+#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI5_TX_DMA_CHN 0x07020000
+
+#define STM32_HAS_SPI6 TRUE
+#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI6_RX_DMA_CHN 0x01000000
+#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI6_TX_DMA_CHN 0x00100000
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+#define STM32_TIM1_UP_HANDLER VectorA4
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM1_UP_NUMBER 25
+#define STM32_TIM1_CC_NUMBER 27
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM2_NUMBER 28
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM3_NUMBER 29
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM4_NUMBER 30
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM5_NUMBER 50
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM6_NUMBER 54
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM7_NUMBER 55
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+#define STM32_TIM8_UP_HANDLER VectorF0
+#define STM32_TIM8_CC_HANDLER VectorF8
+#define STM32_TIM8_UP_NUMBER 44
+#define STM32_TIM8_CC_NUMBER 46
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+#define STM32_TIM9_HANDLER VectorA0
+#define STM32_TIM9_NUMBER 24
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */
+#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+#define STM32_TIM11_HANDLER VectorA8
+#define STM32_TIM11_NUMBER 26
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+#define STM32_TIM12_HANDLER VectorEC
+#define STM32_TIM12_NUMBER 43
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */
+#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+#define STM32_TIM14_HANDLER VectorF4
+#define STM32_TIM14_NUMBER 45
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART1_NUMBER 37
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART2_NUMBER 38
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_USART3_NUMBER 39
+#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_USART3_RX_DMA_CHN 0x00000040
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN 0x00074000
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_HANDLER Vector110
+#define STM32_UART4_NUMBER 52
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_UART4_RX_DMA_CHN 0x00000400
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_UART4_TX_DMA_CHN 0x00040000
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_HANDLER Vector114
+#define STM32_UART5_NUMBER 53
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART5_RX_DMA_CHN 0x00000004
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_UART5_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_HANDLER Vector15C
+#define STM32_USART6_NUMBER 71
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 TRUE
+#define STM32_UART7_HANDLER Vector188
+#define STM32_UART7_NUMBER 82
+#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_UART7_RX_DMA_CHN 0x00005000
+#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_UART7_TX_DMA_CHN 0x00000050
+
+#define STM32_HAS_UART8 TRUE
+#define STM32_UART8_HANDLER Vector18C
+#define STM32_UART8_NUMBER 83
+#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_UART8_RX_DMA_CHN 0x05000000
+#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART8_TX_DMA_CHN 0x00000005
+
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 5
+#define STM32_OTG1_HANDLER Vector14C
+#define STM32_OTG1_NUMBER 67
+
+#define STM32_HAS_OTG2 TRUE
+#define STM32_OTG2_ENDPOINTS 8
+#define STM32_OTG2_HANDLER Vector174
+#define STM32_OTG2_EP1OUT_HANDLER Vector168
+#define STM32_OTG2_EP1IN_HANDLER Vector16C
+#define STM32_OTG2_NUMBER 77
+#define STM32_OTG2_EP1OUT_NUMBER 74
+#define STM32_OTG2_EP1IN_NUMBER 75
+
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC TRUE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC TRUE
+#define STM32_FSMC_HANDLER Vector100
+#define STM32_FSMC_NUMBER 48
+
+/* LTDC attributes.*/
+#define STM32_LTDC_EV_HANDLER Vector1A0
+#define STM32_LTDC_ER_HANDLER Vector1A4
+#define STM32_LTDC_EV_NUMBER 88
+#define STM32_LTDC_ER_NUMBER 89
+
+/* DMA2D attributes.*/
+#define STM32_DMA2D_HANDLER Vector1A8
+#define STM32_DMA2D_NUMBER 90
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) */
+
+/*===========================================================================*/
+/* STM32F767xx, STM32F769xx, STM32F777xx, STM32F779xx. */
+/*===========================================================================*/
+#if defined(STM32F767xx) || defined(STM32F769xx) || \
+ defined(STM32F777xx) || defined(STM32F779xx) || \
+ defined(__DOXYGEN__)
+/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00001100
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_ADC3_DMA_CHN 0x00000022
+
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_CAN_MAX_FILTERS 28
+
+#define STM32_HAS_CAN1 TRUE
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+
+#define STM32_HAS_CAN2 TRUE
+#define STM32_CAN2_TX_HANDLER Vector13C
+#define STM32_CAN2_RX0_HANDLER Vector140
+#define STM32_CAN2_RX1_HANDLER Vector144
+#define STM32_CAN2_SCE_HANDLER Vector148
+#define STM32_CAN2_TX_NUMBER 63
+#define STM32_CAN2_RX0_NUMBER 64
+#define STM32_CAN2_RX1_NUMBER 65
+#define STM32_CAN2_SCE_NUMBER 66
+
+#define STM32_CAN3_MAX_FILTERS 14
+
+#define STM32_HAS_CAN3 TRUE
+#define STM32_CAN3_TX_HANDLER Vector1E0
+#define STM32_CAN3_RX0_HANDLER Vector1E4
+#define STM32_CAN3_RX1_HANDLER Vector1E8
+#define STM32_CAN3_SCE_HANDLER Vector1EC
+#define STM32_CAN3_TX_NUMBER 104
+#define STM32_CAN3_RX0_NUMBER 105
+#define STM32_CAN3_RX1_NUMBER 106
+#define STM32_CAN3_SCE_NUMBER 107
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_DAC1_CH1_DMA_CHN 0x00700000
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_DAC1_CH2_DMA_CHN 0x07000000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_CACHE_HANDLING TRUE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
+#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH TRUE
+#define STM32_ETH_HANDLER Vector134
+#define STM32_ETH_NUMBER 61
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 24
+#define STM32_EXTI_IMR_MASK 0xFF000000
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOI TRUE
+#define STM32_HAS_GPIOJ TRUE
+#define STM32_HAS_GPIOK TRUE
+#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
+ RCC_AHB1ENR_GPIOBEN | \
+ RCC_AHB1ENR_GPIOCEN | \
+ RCC_AHB1ENR_GPIODEN | \
+ RCC_AHB1ENR_GPIOEEN | \
+ RCC_AHB1ENR_GPIOFEN | \
+ RCC_AHB1ENR_GPIOGEN | \
+ RCC_AHB1ENR_GPIOHEN | \
+ RCC_AHB1ENR_GPIOIEN | \
+ RCC_AHB1ENR_GPIOJEN | \
+ RCC_AHB1ENR_GPIOKEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_NUMBER 32
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x11000000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_NUMBER 34
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C2_TX_DMA_CHN 0x70080000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_NUMBER 73
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C3_TX_DMA_CHN 0x00030008
+
+#define STM32_HAS_I2C4 TRUE
+#define STM32_I2C4_EVENT_HANDLER Vector1BC
+#define STM32_I2C4_ERROR_HANDLER Vector1C0
+#define STM32_I2C4_EVENT_NUMBER 95
+#define STM32_I2C4_ERROR_NUMBER 96
+#define STM32_I2C4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_I2C4_RX_DMA_CHN 0x00000080
+#define STM32_I2C4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_I2C4_TX_DMA_CHN 0x08000000
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector1B0
+#define STM32_QUADSPI1_NUMBER 92
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x30000B00
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 TRUE
+#define STM32_SDMMC1_HANDLER Vector104
+#define STM32_SDMMC1_NUMBER 49
+#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDMMC1_DMA_CHN 0x04004000
+
+#define STM32_HAS_SDMMC2 TRUE
+#define STM32_SDMMC2_HANDLER Vector1DC
+#define STM32_SDMMC2_NUMBER 103
+#define STM32_SDC_SDMMC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SDC_SDMMC2_DMA_CHN 0x00B0000B
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S TRUE
+#define STM32_SPI1_I2S_FULLDUPLEX TRUE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000303
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN 0x00303000
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI2_RX_DMA_CHN 0x00000090
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_TX_DMA_CHN 0x09000000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI4_RX_DMA_CHN 0x00005004
+#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN 0x00050940
+
+#define STM32_HAS_SPI5 TRUE
+#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI5_RX_DMA_CHN 0x00902000
+#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI5_TX_DMA_CHN 0x07020000
+
+#define STM32_HAS_SPI6 TRUE
+#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI6_RX_DMA_CHN 0x01000000
+#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI6_TX_DMA_CHN 0x00100000
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+#define STM32_TIM1_UP_HANDLER VectorA4
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM1_UP_NUMBER 25
+#define STM32_TIM1_CC_NUMBER 27
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM2_NUMBER 28
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM3_NUMBER 29
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM4_NUMBER 30
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM5_NUMBER 50
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM6_NUMBER 54
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM7_NUMBER 55
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+#define STM32_TIM8_UP_HANDLER VectorF0
+#define STM32_TIM8_CC_HANDLER VectorF8
+#define STM32_TIM8_UP_NUMBER 44
+#define STM32_TIM8_CC_NUMBER 46
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+#define STM32_TIM9_HANDLER VectorA0
+#define STM32_TIM9_NUMBER 24
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 1
+#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */
+#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 1
+#define STM32_TIM11_HANDLER VectorA8
+#define STM32_TIM11_NUMBER 26
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+#define STM32_TIM12_HANDLER VectorEC
+#define STM32_TIM12_NUMBER 43
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 1
+#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */
+#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+#define STM32_TIM14_HANDLER VectorF4
+#define STM32_TIM14_NUMBER 45
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART1_NUMBER 37
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00400400
+#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART2_NUMBER 38
+#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN 0x00400000
+#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN 0x04000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_USART3_NUMBER 39
+#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_USART3_RX_DMA_CHN 0x00000040
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN 0x00074000
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_HANDLER Vector110
+#define STM32_UART4_NUMBER 52
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_UART4_RX_DMA_CHN 0x00000400
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_UART4_TX_DMA_CHN 0x00040000
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_HANDLER Vector114
+#define STM32_UART5_NUMBER 53
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART5_RX_DMA_CHN 0x00000004
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_UART5_TX_DMA_CHN 0x40000000
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_HANDLER Vector15C
+#define STM32_USART6_NUMBER 71
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN 0x00000550
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN 0x55000000
+
+#define STM32_HAS_UART7 TRUE
+#define STM32_UART7_HANDLER Vector188
+#define STM32_UART7_NUMBER 82
+#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_UART7_RX_DMA_CHN 0x00005000
+#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_UART7_TX_DMA_CHN 0x00000050
+
+#define STM32_HAS_UART8 TRUE
+#define STM32_UART8_HANDLER Vector18C
+#define STM32_UART8_NUMBER 83
+#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_UART8_RX_DMA_CHN 0x05000000
+#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART8_TX_DMA_CHN 0x00000005
+
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 5
+#define STM32_OTG1_HANDLER Vector14C
+#define STM32_OTG1_NUMBER 67
+
+#define STM32_HAS_OTG2 TRUE
+#define STM32_OTG2_ENDPOINTS 8
+#define STM32_OTG2_HANDLER Vector174
+#define STM32_OTG2_EP1OUT_HANDLER Vector168
+#define STM32_OTG2_EP1IN_HANDLER Vector16C
+#define STM32_OTG2_NUMBER 77
+#define STM32_OTG2_EP1OUT_NUMBER 74
+#define STM32_OTG2_EP1IN_NUMBER 75
+
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC TRUE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC TRUE
+#define STM32_FSMC_HANDLER Vector100
+#define STM32_FSMC_NUMBER 48
+
+/* LTDC attributes.*/
+#define STM32_LTDC_EV_HANDLER Vector1A0
+#define STM32_LTDC_ER_HANDLER Vector1A4
+#define STM32_LTDC_EV_NUMBER 88
+#define STM32_LTDC_ER_NUMBER 89
+
+/* DMA2D attributes.*/
+#define STM32_DMA2D_HANDLER Vector1A8
+#define STM32_DMA2D_NUMBER 90
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+#endif /* defined(STM32F767xx) || defined(STM32F769xx) ||
+ defined(STM32F777xx) || defined(STM32F779xx) */
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c
new file mode 100644
index 0000000000..08be8785f0
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c
@@ -0,0 +1,283 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/hal_ext_lld_isr.c
+ * @brief STM32L0xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "hal_ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if !defined(STM32_DISABLE_EXTI01_HANDLER)
+/**
+ * @brief EXTI[0]...EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE01_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 0) | (1U << 1));
+ EXTI->PR = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI23_HANDLER)
+/**
+ * @brief EXTI[2]...EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE23_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 2) | (1U << 3));
+ EXTI->PR = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI4_15_HANDLER)
+/**
+ * @brief EXTI[4]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE4_15_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 4) | (1U << 5) | (1U << 6) | (1U << 7) |
+ (1U << 8) | (1U << 9) | (1U << 10) | (1U << 11) |
+ (1U << 12) | (1U << 13) | (1U << 14) | (1U << 15));
+ EXTI->PR = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+ if (pr & (1U << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1U << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1U << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1U << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1U << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+ if (pr & (1U << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1U << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1U << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1U << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1U << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1U << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI16_HANDLER)
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE16_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 16);
+ EXTI->PR = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI171920_HANDLER)
+/**
+ * @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC, CSS).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE171920_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 17) | (1U << 19) | (1U << 20));
+ EXTI->PR = pr;
+ if (pr & (1U << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+ if (pr & (1U << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+#endif /* HAL_USE_EXT */
+
+#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__)
+#if !defined(STM32_DISABLE_EXTI2122_HANDLER)
+/**
+ * @brief EXTI[21],EXTI[22] interrupt handler (ADC, COMP).
+ * @note This handler is shared with the ADC so it is handled
+ * a bit differently.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE2122_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+#if HAL_USE_EXT
+ {
+ uint32_t pr;
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 21) | (1U << 22));
+ EXTI->PR = pr;
+ if (pr & (1U << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1U << 22))
+ EXTD1.config->channels[21].cb(&EXTD1, 22);
+ }
+#endif
+#if HAL_USE_ADC
+ adc_lld_serve_interrupt(&ADCD1);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+#endif /* HAL_USE_EXT || HAL_USE_ADC */
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(STM32_EXTI_LINE01_NUMBER,
+ STM32_EXT_EXTI0_1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE23_NUMBER,
+ STM32_EXT_EXTI2_3_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE4_15_NUMBER,
+ STM32_EXT_EXTI4_15_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE16_NUMBER,
+ STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE171920_NUMBER,
+ STM32_EXT_EXTI17_20_IRQ_PRIORITY);
+#if HAL_USE_ADC
+ /* If the ADC is not working then the vector can be enabled.*/
+ if (ADCD1.state == ADC_STOP) {
+ nvicEnableVector(STM32_EXTI_LINE2122_NUMBER,
+ STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+ }
+#else
+ nvicEnableVector(STM32_EXTI_LINE2122_NUMBER,
+ STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(STM32_EXTI_LINE01_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE23_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE4_15_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE16_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE2122_NUMBER);
+#if HAL_USE_ADC
+ /* If the ADC is not working then the vector can be disabled.*/
+ if (ADCD1.state == ADC_STOP) {
+ nvicDisableVector(STM32_EXTI_LINE171920_NUMBER);
+ }
+#else
+ nvicDisableVector(STM32_EXTI_LINE171920_NUMBER);
+#endif
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.h
new file mode 100644
index 0000000000..276b9a3cbd
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.h
@@ -0,0 +1,114 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/hal_ext_lld_isr.h
+ * @brief STM32L0xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0..1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI2..3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI4..15 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI16 (PVD) interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI17,19,20 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI21,22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_exti_irq_enable(void);
+ void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_lld.c
new file mode 100644
index 0000000000..ea8c8271a8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_lld.c
@@ -0,0 +1,308 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/hal_lld.c
+ * @brief STM32L0xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32l0xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+ /* Backup domain reset.*/
+ RCC->CSR |= RCC_CSR_RTCRST;
+ RCC->CSR &= ~RCC_CSR_RTCRST;
+ }
+
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ RCC->CSR |= RCC_CSR_LSEON;
+ while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->CSR & RCC_CSR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->CSR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->CSR |= RCC_CSR_RTCEN;
+ }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+#if defined(STM32_DMA1_CH23_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM2);
+
+ /* Check on channel 3.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH23_HANDLER) */
+
+#if defined(STM32_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM4);
+
+ /* Check on channel 5.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM5);
+
+#if STM32_DMA1_NUM_CHANNELS > 5
+ /* Check on channel 6.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM6);
+#endif
+
+#if STM32_DMA1_NUM_CHANNELS > 6
+ /* Check on channel 7.*/
+ dmaServeInterrupt(STM32_DMA1_STREAM7);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH4567_HANDLER) */
+#endif /* defined(STM32_DMA_REQUIRED) */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Reset of all peripherals.*/
+ rccResetAHB(~RCC_AHBRSTR_MIFRST);
+ rccResetAPB1(~RCC_APB1RSTR_PWRRST);
+ rccResetAPB2(~0);
+
+ /* PWR clock enabled.*/
+ rccEnablePWRInterface(FALSE);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+ /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+ PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief STM32L0xx voltage, clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+/**
+ * @brief Clocks and internal voltage initialization.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+ /* PWR clock enable.*/
+ RCC->APB1ENR = RCC_APB1ENR_PWREN;
+
+ /* Core voltage setup.*/
+ while ((PWR->CSR & PWR_CSR_VOSF) != 0)
+ ; /* Waits until regulator is stable. */
+ PWR->CR = STM32_VOS;
+ while ((PWR->CSR & PWR_CSR_VOSF) != 0)
+ ; /* Waits until regulator is stable. */
+
+ /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
+ always enabled because it is the fallback clock when PLL the fails.
+ Trim fields are not altered from reset values.*/
+ RCC->CFGR = 0;
+ RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
+ RCC->CR = RCC_CR_MSION;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ; /* Waits until MSI is stable. */
+
+#if STM32_HSI16_ENABLED
+ /* HSI activation.*/
+ RCC->CR |= RCC_CR_HSION;
+ while ((RCC->CR & RCC_CR_HSIRDY) == 0)
+ ; /* Waits until HSI16 is stable. */
+
+#if STM32_HSI16_DIVIDER_ENABLED
+ RCC->CR |= RCC_CR_HSIDIVEN;
+ while ((RCC->CR & RCC_CR_HSIDIVF) == 0)
+ ;
+#endif
+#endif
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#endif
+ /* HSE activation.*/
+ RCC->CR |= RCC_CR_HSEON;
+ while ((RCC->CR & RCC_CR_HSERDY) == 0)
+ ; /* Waits until HSE is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Waits until LSI is stable. */
+#endif
+
+#if STM32_LSE_ENABLED
+ /* LSE activation, have to unlock the register.*/
+ if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
+ PWR->CR |= PWR_CR_DBP;
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->CSR |= STM32_LSEDRV | RCC_CSR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->CSR |= STM32_LSEDRV;
+#endif
+ RCC->CSR |= RCC_CSR_LSEON;
+ PWR->CR &= ~PWR_CR_DBP;
+ }
+ while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ; /* Waits until PLL is stable. */
+#endif
+
+#if STM32_ACTIVATE_HSI48
+ /* Enabling SYSCFG clock. */
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE);
+ /* Configuring SYSCFG to enable VREFINT and HSI48 VREFINT buffer. */
+ SYSCFG->CFGR3 = STM32_VREFINT_EN | SYSCFG_CFGR3_ENREF_HSI48;
+
+ while (!(SYSCFG->CFGR3 & SYSCFG_CFGR3_VREFINT_RDYF))
+ ; /* Waits until VREFINT is stable. */
+ /* Disabling SYSCFG clock. */
+ rccDisableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE);
+
+ /* Enabling HSI48. */
+ RCC->CRRCR |= RCC_CRRCR_HSI48ON;
+ while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY))
+ ; /* Waits until HSI48 is stable. */
+#endif
+
+ /* Other clock-related settings (dividers, MCO etc).*/
+ RCC->CR |= STM32_RTCPRE;
+ RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
+ STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+ RCC->CSR |= STM32_RTCSEL;
+
+ /* Flash setup and final clock selection.*/
+#if defined(STM32_FLASHBITS)
+ FLASH->ACR = STM32_FLASHBITS;
+#endif
+
+ /* Switching to the configured clock source if it is different from MSI. */
+#if (STM32_SW != STM32_SW_MSI)
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+#endif
+
+ /* Peripherals clock sources setup.*/
+ RCC->CCIPR = STM32_HSI48SEL | STM32_LPTIM1SEL | STM32_I2C1SEL |
+ STM32_LPUART1SEL | STM32_USART2SEL | STM32_USART1SEL;
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+#endif /* STM32_NO_INIT */
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_lld.h
new file mode 100644
index 0000000000..bd61620b4d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/hal_lld.h
@@ -0,0 +1,1205 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/hal_lld.h
+ * @brief STM32L0xx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_LSEDRV.
+ * - STM32_LSE_BYPASS (optionally).
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32L011xx, STM32L031xx,
+ * STM32L051xx, STM32L052xx, STM32L053xx,
+ * STM32L061xx, STM32L062xx, STM32L063xx,
+ * STM32L073xx for ultra-low-power MCUs.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+/*
+ * Registry definitions.
+ */
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification macros
+ * @{
+ */
+#if defined(STM32L011xx) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32L011xx ultra-low-power MCU"
+
+#elif defined(STM32L031xx)
+#define PLATFORM_NAME "STM32L031xx ultra-low-power MCU"
+
+#elif defined(STM32L051xx)
+#define PLATFORM_NAME "STM32L051xx ultra-low-power MCU"
+
+#elif defined(STM32L052xx)
+#define PLATFORM_NAME "STM32L052xx ultra-low-power MCU"
+
+#elif defined(STM32L053xx)
+#define PLATFORM_NAME "STM32L053xx ultra-low-power MCU"
+
+#elif defined(STM32L061xx)
+#define PLATFORM_NAME "STM32L061xx ultra-low-power MCU"
+
+#elif defined(STM32L062xx)
+#define PLATFORM_NAME "STM32L062xx ultra-low-power MCU"
+
+#elif defined(STM32L063xx)
+#define PLATFORM_NAME "STM32L063xx ultra-low-power MCU"
+
+#elif defined(STM32L073xx)
+#define PLATFORM_NAME "STM32L073xx ultra-low-power MCU"
+
+#else
+#error "STM32L0xx device not specified"
+#endif
+/** @} */
+
+/**
+ * @name Sub-family identifier
+ */
+#if !defined(STM32L0XX) || defined(__DOXYGEN__)
+#define STM32L0XX
+#endif
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSI16CLK 16000000 /**< 16MHz internal clock. */
+#define STM32_HSI48CLK 48000000 /**< 48MHz internal clock. */
+#define STM32_LSICLK 37000 /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK (7 << 5) /**< PLS field mask. */
+#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
+#define STM32_PLS_EXT (7 << 5) /**< PVD level 7. */
+
+#define STM32_VOS_MASK (3 << 11) /**< VOS field mask. */
+#define STM32_VOS_1P8 (1 << 11) /**< VOS level 1.8 volts. */
+#define STM32_VOS_1P5 (2 << 11) /**< VOS level 1.5 volts. */
+#define STM32_VOS_1P2 (3 << 11) /**< VOS level 1.2 volts. */
+/** @} */
+
+/**
+ * @name RCC_CR register bits definitions
+ * @{
+ */
+#define STM32_RTCPRE_MASK (3 << 20) /**< RTCPRE mask. */
+#define STM32_RTCPRE_DIV2 (0 << 20) /**< HSE divided by 2. */
+#define STM32_RTCPRE_DIV4 (1 << 20) /**< HSE divided by 4. */
+#define STM32_RTCPRE_DIV8 (2 << 20) /**< HSE divided by 2. */
+#define STM32_RTCPRE_DIV16 (3 << 20) /**< HSE divided by 16. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MASK (3 << 0) /**< SW field mask. */
+#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
+#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI16 */
+#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */
+#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE1_MASK (7 << 8) /**< PPRE2 field mask. */
+#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
+#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
+#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
+#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
+#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
+
+#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */
+#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
+#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
+#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
+#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
+#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
+
+#define STM32_STOPWUCK_MASK (1 << 15) /**< PLLDIV field mask. */
+#define STM32_STOPWUCK_MSI (0 << 15) /**< MSI is wakeup clock. */
+#define STM32_STOPWUCK_HSI16 (1 << 15) /**< HSI16 is wakeup clock. */
+
+#define STM32_PLLSRC_MASK (1 << 16) /**< PLLSRC field mask. */
+#define STM32_PLLSRC_HSI16 (0 << 16) /**< PLL clock source is HSI16. */
+#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
+
+#define STM32_PLLMUL_MASK (15 << 18) /**< PLLMUL field mask. */
+#define STM32_PLLMUL_MUL3 (0 << 18) /**< PLL multiplier is 3. */
+#define STM32_PLLMUL_MUL4 (1 << 18) /**< PLL multiplier is 4. */
+#define STM32_PLLMUL_MUL6 (2 << 18) /**< PLL multiplier is 6. */
+#define STM32_PLLMUL_MUL8 (3 << 18) /**< PLL multiplier is 8. */
+#define STM32_PLLMUL_MUL12 (4 << 18) /**< PLL multiplier is 12. */
+#define STM32_PLLMUL_MUL16 (5 << 18) /**< PLL multiplier is 16. */
+#define STM32_PLLMUL_MUL24 (6 << 18) /**< PLL multiplier is 24. */
+#define STM32_PLLMUL_MUL32 (7 << 18) /**< PLL multiplier is 32. */
+#define STM32_PLLMUL_MUL48 (8 << 18) /**< PLL multiplier is 48. */
+
+#define STM32_PLLDIV_MASK (3 << 22) /**< PLLDIV field mask. */
+#define STM32_PLLDIV_DIV2 (1 << 22) /**< PLL divided by 2. */
+#define STM32_PLLDIV_DIV3 (2 << 22) /**< PLL divided by 3. */
+#define STM32_PLLDIV_DIV4 (3 << 22) /**< PLL divided by 4. */
+
+#define STM32_MCOSEL_MASK (15 << 24) /**< MCOSEL field mask. */
+#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_HSI16 (2 << 24) /**< HSI16 clock on MCO pin. */
+#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */
+#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
+#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
+#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
+#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
+
+#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */
+#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO is divided by 1. */
+#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO is divided by 1. */
+#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO is divided by 1. */
+#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO is divided by 1. */
+#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO is divided by 1. */
+/** @} */
+
+/**
+ * @name RCC_ICSCR register bits definitions
+ * @{
+ */
+#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
+#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */
+#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */
+#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */
+#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */
+#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
+#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
+#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
+/** @} */
+
+/**
+ * @name RCC_CSR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
+#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
+#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
+#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
+#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
+/** @} */
+
+/**
+ * @name RCC_CCIPR register bits definitions
+ * @{
+ */
+#define STM32_USART1SEL_MASK (3 << 0) /**< USART1 clock source mask. */
+#define STM32_USART1SEL_APB (0 << 0) /**< USART1 clock is APB. */
+#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */
+#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 clock is HSI16. */
+#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 clock is LSE. */
+
+#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 clock source mask. */
+#define STM32_USART2SEL_APB (0 << 2) /**< USART2 clock is APB. */
+#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 clock is SYSCLK. */
+#define STM32_USART2SEL_HSI16 (2 << 2) /**< USART2 clock is HSI16. */
+#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 clock is LSE. */
+
+#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 clock source mask. */
+#define STM32_LPUART1SEL_APB (0 << 10) /**< LPUART1 clock is APB. */
+#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 clock is SYSCLK. */
+#define STM32_LPUART1SEL_HSI16 (2 << 10) /**< LPUART1 clock is HSI16. */
+#define STM32_LPUART1SEL_LSE (3 << 10) /**< LPUART1 clock is LSE. */
+
+#define STM32_I2C1SEL_MASK (3 << 12) /**< I2C1 clock source mask. */
+#define STM32_I2C1SEL_APB (0 << 12) /**< I2C1 clock is APB. */
+#define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 clock is SYSCLK. */
+#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 clock is HSI16. */
+
+#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3 clock source mask. */
+#define STM32_I2C3SEL_APB (0 << 16) /**< I2C3 clock is APB. */
+#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 clock is SYSCLK. */
+#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 clock is HSI16. */
+
+#define STM32_LPTIM1SEL_MASK (3 << 18) /**< LPTIM1 clock source mask. */
+#define STM32_LPTIM1SEL_APB (0 << 18) /**< LPTIM1 clock is APB. */
+#define STM32_LPTIM1SEL_LSI (1 << 18) /**< LPTIM1 clock is LSI. */
+#define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 clock is HSI16. */
+#define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 clock is LSE. */
+
+#define STM32_HSI48SEL_MASK (1 << 26) /**< HSI48SEL clock source mask.*/
+#define STM32_HSI48SEL_USBPLL (0 << 26) /**< USB48 clock is PLL/2. */
+#define STM32_HSI48SEL_HSI48 (1 << 26) /**< USB48 clock is HSI48. */
+/** @} */
+
+/**
+ * @name SYSCFG_CFGR3_ register bits definitions
+ * @{
+ */
+#define STM32_VREFINT_EN (1 << 0) /**< VREFINT enable switch. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Core voltage selection.
+ * @note This setting affects all the performance and clock related
+ * settings, the maximum performance is only obtainable selecting
+ * the maximum voltage.
+ */
+#if !defined(STM32_VOS) || defined(__DOXYGEN__)
+#define STM32_VOS STM32_VOS_1P8
+#endif
+
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief Enables or disables the HSI16 clock source.
+ */
+#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI16_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSI16 clock divider.
+ */
+#if !defined(STM32_HSI16_DIVIDER_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI16_DIVIDER_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief ADC clock setting.
+ */
+#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_ADC_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief MSI frequency setting.
+ */
+#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
+#define STM32_MSIRANGE STM32_MSIRANGE_2M
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_HSI16
+#endif
+
+/**
+ * @brief PLL multiplier value.
+ * @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE 4
+#endif
+
+/**
+ * @brief PLL divider value.
+ * @note The allowed values are 2, 3, 4.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLDIV_VALUE 2
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#endif
+
+/**
+ * @brief MCO clock source.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief RTC/LCD clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#endif
+
+/**
+ * @brief HSE divider toward RTC setting.
+ */
+#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
+#define STM32_RTCPRE STM32_RTCPRE_DIV2
+#endif
+
+/**
+ * @brief USART1 clock source.
+ */
+#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
+#define STM32_USART1SEL STM32_USART1SEL_APB
+#endif
+
+/**
+ * @brief USART2 clock source.
+ */
+#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
+#define STM32_USART2SEL STM32_USART2SEL_APB
+#endif
+
+/**
+ * @brief LPUART1 clock source.
+ */
+#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
+#define STM32_LPUART1SEL STM32_LPUART1SEL_APB
+#endif
+
+/**
+ * @brief I2C clock source.
+ */
+#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
+#define STM32_I2C1SEL STM32_I2C1SEL_APB
+#endif
+
+/**
+ * @brief LPTIM1 clock source.
+ */
+#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_APB
+#endif
+
+/**
+ * @bief USB/RNG clock source.
+ */
+#if !defined(STM32_HSI48SEL) || defined(__DOXYGEN__)
+#define STM32_HSI48SEL STM32_HSI48SEL_USBPLL
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32L0xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L0xx_MCUCONF not defined"
+#endif
+
+/*
+ * Board files sanity checks.
+ */
+#if !defined(STM32_LSECLK)
+#error "STM32_LSECLK not defined in board.h"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined in board.h"
+#endif
+
+#if !defined(STM32_HSECLK)
+#error "STM32_HSECLK not defined in board.h"
+#endif
+
+/* Voltage related limits.*/
+#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum SYSCLK clock frequency at current voltage setting.
+ */
+#define STM32_SYSCLK_MAX 32000000
+
+/**
+ * @brief Maximum HSE clock frequency at current voltage setting.
+ */
+#define STM32_HSECLK_MAX 32000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN 1000000
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX 1000000
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN 1000
+
+/**
+ * @brief Maximum PLL input frequency.
+ */
+#define STM32_PLLIN_MAX 24000000
+
+/**
+ * @brief Maximum PLL input frequency.
+ */
+#define STM32_PLLIN_MIN 2000000
+
+/**
+ * @brief Maximum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MAX 96000000
+
+/**
+ * @brief Minimum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MIN 6000000
+
+/**
+ * @brief Maximum PLL output frequency.
+ */
+#define STM32_PLLOUT_MAX 32000000
+
+/**
+ * @brief Maximum PLL output frequency.
+ */
+#define STM32_PLLOUT_MIN 2000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX 32000000
+
+/**
+ * @brief Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX 32000000
+
+/**
+ * @brief Maximum frequency not requiring a wait state for flash accesses.
+ */
+#define STM32_0WS_THRESHOLD 16000000
+
+/**
+ * @brief HSI availability at current voltage settings.
+ */
+#define STM32_HSI_AVAILABLE TRUE
+/** @} */
+
+#elif STM32_VOS == STM32_VOS_1P5
+#define STM32_SYSCLK_MAX 16000000
+#define STM32_HSECLK_MAX 16000000
+#define STM32_HSECLK_MIN 1000000
+#define STM32_LSECLK_MAX 1000000
+#define STM32_LSECLK_MIN 1000
+#define STM32_PLLIN_MAX 16000000
+#define STM32_PLLIN_MIN 2000000
+#define STM32_PLLVCO_MAX 48000000
+#define STM32_PLLVCO_MIN 6000000
+#define STM32_PLLOUT_MAX 16000000
+#define STM32_PLLOUT_MIN 2000000
+#define STM32_PCLK1_MAX 16000000
+#define STM32_PCLK2_MAX 16000000
+#define STM32_0WS_THRESHOLD 8000000
+#define STM32_HSI_AVAILABLE TRUE
+#elif STM32_VOS == STM32_VOS_1P2
+#define STM32_SYSCLK_MAX 4000000
+#define STM32_HSECLK_MAX 8000000
+#define STM32_HSECLK_MIN 1000000
+#define STM32_LSECLK_MAX 1000000
+#define STM32_LSECLK_MIN 1000
+#define STM32_PLLIN_MAX 8000000
+#define STM32_PLLIN_MIN 2000000
+#define STM32_PLLVCO_MAX 24000000
+#define STM32_PLLVCO_MIN 6000000
+#define STM32_PLLOUT_MAX 4000000
+#define STM32_PLLOUT_MIN 2000000
+#define STM32_PCLK1_MAX 4000000
+#define STM32_PCLK2_MAX 4000000
+#define STM32_0WS_THRESHOLD 4000000
+#define STM32_HSI_AVAILABLE FALSE
+#else
+#error "invalid STM32_VOS value specified"
+#endif
+
+/* HSI related checks.*/
+#if STM32_HSI16_ENABLED
+#if !STM32_HSI_AVAILABLE
+ #error "impossible to activate HSI under the current voltage settings"
+#endif
+#else /* !STM32_HSI16_ENABLED */
+
+#if STM32_ADC_CLOCK_ENABLED
+#error "HSI16 not enabled, required by STM32_ADC_CLOCK_ENABLED"
+#endif
+
+#if (STM32_SW == STM32_SW_HSI16)
+#error "HSI16 not enabled, required by STM32_SW"
+#endif
+
+#if ((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16))
+#error "HSI16 not enabled, required by STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI16)
+#error "HSI16 not enabled, required by STM32_MCOSEL"
+#endif
+
+#if ((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16))
+#error "HSI16 not enabled, required by STM32_PLLSRC"
+#endif
+
+#endif /* !STM32_HSI16_ENABLED */
+
+/*
+ * @brief Divided HSI16 clock.
+ */
+#if STM32_HSI16_DIVIDER_ENABLED || defined(__DOXYGEN__)
+#define STM32_HSI16DIVCLK (STM32_HSI16CLK / 4)
+#else
+#define STM32_HSI16DIVCLK STM32_HSI16CLK
+#endif
+
+/* HSE related checks.*/
+#if STM32_HSE_ENABLED
+#if STM32_HSECLK == 0
+#error "impossible to activate HSE, frequency is zero"
+#endif
+#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+#else /* !STM32_HSE_ENABLED */
+
+#if (STM32_SW == STM32_SW_HSE)
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if ((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE)
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if ((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_PLLSRC"
+#endif
+
+#if (STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/* LSI related checks.*/
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_LSI
+#error "LSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/* LSE related checks.*/
+#if STM32_LSE_ENABLED
+#if (STM32_LSECLK == 0)
+#error "impossible to activate LSE, frequency is zero"
+#endif
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_LSE
+#error "LSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL related checks.*/
+#if (STM32_SW == STM32_SW_PLL) || (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
+ (STM32_USB_CLOCK_ENABLED && (STM32_HSI48SEL == STM32_HSI48SEL_USBPLL)) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/* HSI48 related checks.*/
+#if (STM32_USB_CLOCK_ENABLED && (STM32_HSI48SEL == STM32_HSI48SEL_HSI48)) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief HSI48 activation flag.
+ */
+#define STM32_ACTIVATE_HSI48 TRUE
+#else
+#define STM32_ACTIVATE_HSI48 FALSE
+#endif
+
+/**
+ * @brief PLLMUL field.
+ */
+#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)
+#define STM32_PLLMUL STM32_PLLMUL_MUL3
+#elif STM32_PLLMUL_VALUE == 4
+#define STM32_PLLMUL STM32_PLLMUL_MUL4
+#elif STM32_PLLMUL_VALUE == 6
+#define STM32_PLLMUL STM32_PLLMUL_MUL6
+#elif STM32_PLLMUL_VALUE == 8
+#define STM32_PLLMUL STM32_PLLMUL_MUL8
+#elif STM32_PLLMUL_VALUE == 12
+#define STM32_PLLMUL STM32_PLLMUL_MUL12
+#elif STM32_PLLMUL_VALUE == 16
+#define STM32_PLLMUL STM32_PLLMUL_MUL16
+#elif STM32_PLLMUL_VALUE == 24
+#define STM32_PLLMUL STM32_PLLMUL_MUL24
+#elif STM32_PLLMUL_VALUE == 32
+#define STM32_PLLMUL STM32_PLLMUL_MUL32
+#elif STM32_PLLMUL_VALUE == 48
+#define STM32_PLLMUL STM32_PLLMUL_MUL48
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLDIV field.
+ */
+#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLDIV STM32_PLLDIV_DIV2
+#elif STM32_PLLDIV_VALUE == 3
+#define STM32_PLLDIV STM32_PLLDIV_DIV3
+#elif STM32_PLLDIV_VALUE == 4
+#define STM32_PLLDIV STM32_PLLDIV_DIV4
+#else
+#error "invalid STM32_PLLDIV_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN STM32_HSECLK
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
+#define STM32_PLLCLKIN STM32_HSI16DIVCLK
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief PLL VCO frequency.
+ */
+#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief MSI frequency.
+ * @note Values are taken from the STM8Lxx datasheet.
+ */
+#if STM32_MSIRANGE == STM32_MSIRANGE_64K
+#define STM32_MSICLK 65500
+#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
+#define STM32_MSICLK 131000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
+#define STM32_MSICLK 262000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
+#define STM32_MSICLK 524000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
+#define STM32_MSICLK 1050000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
+#define STM32_MSICLK 2100000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
+#define STM32_MSICLK 4200000
+#else
+#error "invalid STM32_MSIRANGE value specified"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+#define STM32_SYSCLK 2100000
+#elif (STM32_SW == STM32_SW_MSI)
+#define STM32_SYSCLK STM32_MSICLK
+#elif (STM32_SW == STM32_SW_HSI16)
+#define STM32_SYSCLK STM32_HSI16DIVCLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+#elif (STM32_SW == STM32_SW_PLL)
+#define STM32_SYSCLK STM32_PLLCLKOUT
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief MCO selector clock.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_MCODIVCLK 0
+#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
+#define STM32_MCODIVCLK STM32_SYSCLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
+#define STM32_MCODIVCLK STM32_HSI16DIVCLK
+#elif STM32_MCOSEL == STM32_MCOSEL_MSI
+#define STM32_MCODIVCLK STM32_MSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+#define STM32_MCODIVCLK STM32_HSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_PLL
+#define STM32_MCODIVCLK STM32_PLLCLKOUT
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+#define STM32_MCODIVCLK STM32_LSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+#define STM32_MCODIVCLK STM32_LSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
+#define STM32_MCODIVCLK STM32_HSI48CLK
+#else
+#error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief MCO output pin clock.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCOCLK STM32_MCODIVCLK
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
+#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
+#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
+#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
+#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
+/**
+ * @brief HSE divider toward RTC clock.
+ */
+#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 2)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 4)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 8)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 16)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief RTC/LCD clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK 0
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK STM32_HSEDIVCLK
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief USART1 frequency.
+ */
+#if (STM32_USART1SEL == STM32_USART1SEL_APB) || defined(__DOXYGEN__)
+#define STM32_USART1CLK STM32_PCLK2
+#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
+#define STM32_USART1CLK STM32_SYSCLK
+#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
+#define STM32_USART1CLK STM32_HSI16DIVCLK
+#elif STM32_USART1SEL == STM32_USART1SEL_LSE
+#define STM32_USART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief USART2 frequency.
+ */
+#if (STM32_USART2SEL == STM32_USART2SEL_APB) || defined(__DOXYGEN__)
+#define STM32_USART2CLK STM32_PCLK1
+#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
+#define STM32_USART2CLK STM32_SYSCLK
+#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
+#define STM32_USART2CLK STM32_HSI16DIVCLK
+#elif STM32_USART2SEL == STM32_USART2SEL_LSE
+#define STM32_USART2CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART2 clock"
+#endif
+
+/**
+ * @brief USART4 frequency.
+ */
+#define STM32_UART4CLK STM32_PCLK1
+
+/**
+ * @brief USART5 frequency.
+ */
+#define STM32_UART5CLK STM32_PCLK1
+
+/**
+ * @brief LPUART1 frequency.
+ */
+#if (STM32_LPUART1SEL == STM32_LPUART1SEL_APB) || defined(__DOXYGEN__)
+#define STM32_LPUART1CLK STM32_PCLK1
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
+#define STM32_LPUART1CLK STM32_SYSCLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
+#define STM32_LPUART1CLK STM32_HSI16DIVCLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
+#define STM32_LPUART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPUART1 clock"
+#endif
+
+/**
+ * @brief I2C1 frequency.
+ */
+#if (STM32_I2C1SEL == STM32_I2C1SEL_APB) || defined(__DOXYGEN__)
+#define STM32_I2C1CLK STM32_PCLK1
+#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
+#define STM32_I2C1CLK STM32_SYSCLK
+#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
+#define STM32_I2C1CLK STM32_HSI16DIVCLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief LPTIM1 frequency.
+ */
+#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_APB) || defined(__DOXYGEN__)
+#define STM32_LPTIM1CLK STM32_PCLK1
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
+#define STM32_LPTIM1CLK STM32_LSICLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
+#define STM32_LPTIM1CLK STM32_HSI16DIVCLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
+#define STM32_LPTIM1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPTIM1 clock"
+#endif
+
+/**
+ * @brief USB/RNG frequency.
+ */
+#if (STM32_HSI48SEL == STM32_HSI48SEL_HSI48) || defined(__DOXYGEN__)
+#define STM32_USBCLK STM32_HSI48CLK
+#elif STM32_HSI48SEL == STM32_HSI48SEL_USBPLL
+#define STM32_USBCLK (STM32_PLLVCO / 2)
+#else
+#error "invalid STM32_HSI48SEL value specified"
+#endif
+
+/**
+ * @brief Timers LPTIM1, TIM2, TIM6 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Timers TIM21, TIM22 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS 0
+#else
+#define STM32_FLASHBITS (FLASH_ACR_PRE_READ | \
+ FLASH_ACR_PRFTEN | \
+ FLASH_ACR_LATENCY)
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/platform.mk
new file mode 100644
index 0000000000..1d56edbf5d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/platform.mk
@@ -0,0 +1,33 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h
new file mode 100644
index 0000000000..89121bea9a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h
@@ -0,0 +1,758 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/stm32_rcc.h
+ * @brief RCC helper driver header.
+ * @note This file requires definitions from the ST header file
+ * @p stm32l0xx.h.
+ *
+ * @addtogroup STM32L1xx_RCC
+ * @{
+ */
+
+#ifndef _STM32_RCC_
+#define _STM32_RCC_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1(mask, lp) { \
+ RCC->APB1ENR |= (mask); \
+ if (lp) \
+ RCC->APB1SMENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1(mask, lp) { \
+ RCC->APB1ENR &= ~(mask); \
+ if (lp) \
+ RCC->APB1SMENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask APB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1(mask) { \
+ RCC->APB1RSTR |= (mask); \
+ RCC->APB1RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) { \
+ RCC->APB2ENR |= (mask); \
+ if (lp) \
+ RCC->APB2SMENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask, lp) { \
+ RCC->APB2ENR &= ~(mask); \
+ if (lp) \
+ RCC->APB2SMENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) { \
+ RCC->APB2RSTR |= (mask); \
+ RCC->APB2RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB(mask, lp) { \
+ RCC->AHBENR |= (mask); \
+ if (lp) \
+ RCC->AHBSMENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB(mask, lp) { \
+ RCC->AHBENR &= ~(mask); \
+ if (lp) \
+ RCC->AHBSMENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask AHB peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB(mask) { \
+ RCC->AHBRSTR |= (mask); \
+ RCC->AHBRSTR = 0; \
+}
+/** @} */
+
+/**
+ * @name ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ADC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief Disables the ADC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief Resets the ADC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
+/** @} */
+
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
+/** @} */
+
+/**
+ * @name DMA peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief Disables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
+/** @} */
+
+/**
+ * @name PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
+/** @} */
+
+/**
+ * @name I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Disables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
+
+/**
+ * @brief Enables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Disables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+
+/**
+ * @brief Enables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp)
+
+/**
+ * @brief Disables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp)
+
+/**
+ * @brief Resets the I2C3 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
+/** @} */
+
+/**
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Disables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief Enables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Disables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+/** @} */
+
+/**
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Disables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
+ * @brief Enables the TIM21 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM21(lp) rccEnableAPB2(RCC_APB2ENR_TIM21EN, lp)
+
+/**
+ * @brief Disables the TIM21 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM21(lp) rccDisableAPB2(RCC_APB2ENR_TIM21EN, lp)
+
+/**
+ * @brief Resets the TIM21 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM21() rccResetAPB2(RCC_APB2RSTR_TIM21RST)
+
+/**
+ * @brief Enables the TIM22 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM22(lp) rccEnableAPB2(RCC_APB2ENR_TIM22EN, lp)
+
+/**
+ * @brief Disables the TIM22 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM22(lp) rccDisableAPB2(RCC_APB2ENR_TIM22EN, lp)
+
+/**
+ * @brief Resets the TIM22 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM22() rccResetAPB2(RCC_APB2RSTR_TIM22RST)
+/** @} */
+
+/**
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Disables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief Enables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Disables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_USART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_USART4EN, lp)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1ENR_USART4EN)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_USART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_USART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1ENR_USART5EN)
+
+/**
+ * @brief Enables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableLPUART1(lp) rccEnableAPB1(RCC_APB1ENR_LPUART1EN, lp)
+
+/**
+ * @brief Disables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableLPUART1(lp) rccDisableAPB1(RCC_APB1ENR_LPUART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetLPUART1() rccResetAPB1(RCC_APB1RSTR_LPUART1RST)
+/** @} */
+
+/**
+ * @name USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_RCC_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/stm32_registry.h
new file mode 100644
index 0000000000..0946498a21
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L0xx/stm32_registry.h
@@ -0,0 +1,1547 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/stm32_registry.h
+ * @brief STM32L0xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32L0xx capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* STM32L011xx */
+/*===========================================================================*/
+#if defined(STM32L011xx) || defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
+ RCC_IOPENR_GPIOBEN | \
+ RCC_IOPENR_GPIOCEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
+
+#define STM32_HAS_TIM21 TRUE
+#define STM32_TIM21_IS_32BITS FALSE
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x04004000
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
+#define STM32_HAS_USART1 FALSE
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32L031xx */
+/*===========================================================================*/
+#elif defined(STM32L031xx) || defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
+ RCC_IOPENR_GPIOBEN | \
+ RCC_IOPENR_GPIOCEN | \
+ RCC_IOPENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
+
+#define STM32_HAS_TIM21 TRUE
+#define STM32_TIM21_IS_32BITS FALSE
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x04004000
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
+#define STM32_HAS_USART1 FALSE
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32L051xx, STM32L061xx */
+/*===========================================================================*/
+#elif defined(STM32L051xx) || defined(STM32L061xx) || \
+ defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
+ RCC_IOPENR_GPIOBEN | \
+ RCC_IOPENR_GPIOCEN | \
+ RCC_IOPENR_GPIODEN | \
+ RCC_IOPENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
+
+#define STM32_HAS_TIM21 TRUE
+#define STM32_TIM21_IS_32BITS FALSE
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x04004000
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32L052xx, STM32L062xx. */
+/*===========================================================================*/
+#elif defined(STM32L052xx) || defined(STM32L062xx) || \
+ defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000090
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
+ RCC_IOPENR_GPIOBEN | \
+ RCC_IOPENR_GPIOCEN | \
+ RCC_IOPENR_GPIODEN | \
+ RCC_IOPENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
+
+#define STM32_HAS_TIM21 TRUE
+#define STM32_TIM21_IS_32BITS FALSE
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x04004000
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32L053xx, STM32L063xx. */
+/*===========================================================================*/
+#elif defined(STM32L053xx) || defined(STM32L063xx) || \
+ defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 FALSE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000090
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
+ RCC_IOPENR_GPIOBEN | \
+ RCC_IOPENR_GPIOCEN | \
+ RCC_IOPENR_GPIODEN | \
+ RCC_IOPENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
+
+#define STM32_HAS_TIM21 TRUE
+#define STM32_TIM21_IS_32BITS FALSE
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x04004000
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/*===========================================================================*/
+/* STM32L073xx */
+/*===========================================================================*/
+#elif defined(STM32L073xx) || defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000090
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_DAC1_CH2_DMA_CHN 0x0000F000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
+ RCC_IOPENR_GPIOBEN | \
+ RCC_IOPENR_GPIOCEN | \
+ RCC_IOPENR_GPIODEN | \
+ RCC_IOPENR_GPIOEEN | \
+ RCC_IOPENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_GLOBAL_HANDLER Vector94
+#define STM32_I2C3_GLOBAL_NUMBER 21
+#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C3_RX_DMA_CHN 0x00E0E000
+#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C3_TX_DMA_CHN 0x0E0E0000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+#define STM32_TIM3_HANDLER Vector80
+#define STM32_TIM3_NUMBER 16
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+#define STM32_TIM7_HANDLER Vector88
+#define STM32_TIM7_NUMBER 18
+
+#define STM32_HAS_TIM21 TRUE
+#define STM32_TIM21_IS_32BITS FALSE
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x04004000
+
+#define STM32_USART3_8_HANDLER Vector78
+#define STM32_USART3_8_NUMBER 14
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_UART4_RX_DMA_CHN 0x00C000C0
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_UART4_TX_DMA_CHN 0x0C000C00
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_UART5_RX_DMA_CHN 0x00D000D0
+#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_UART5_TX_DMA_CHN 0x0D000D00
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#else
+#error "STM32L0xx device not specified"
+#endif
+
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
new file mode 100644
index 0000000000..280fdab524
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
@@ -0,0 +1,291 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/hal_adc_lld.c
+ * @brief STM32L1xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC DMA ISR service routine.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+ /* DMA errors handling.*/
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ /* DMA, this could help only if the DMA tries to access an unmapped
+ address space or violates alignment rules.*/
+ _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+ }
+ else {
+ /* It is possible that the conversion group has already be reset by the
+ ADC error handler, in this case this interrupt is spurious.*/
+ if (adcp->grpp != NULL) {
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _adc_isr_full_code(adcp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _adc_isr_half_code(adcp);
+ }
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief ADC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector88) {
+ uint32_t sr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ sr = ADC1->SR;
+ ADC1->SR = 0;
+ /* Note, an overflow may occur after the conversion ended before the driver
+ is able to stop the ADC, this is why the DMA channel is checked too.*/
+ if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
+ /* ADC overflow condition, this could happen only if the DMA is unable
+ to read data fast enough.*/
+ if (ADCD1.grpp != NULL)
+ _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+ }
+ /* TODO: Add here analog watchdog handling.*/
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.adc = ADC1;
+ ADCD1.dmastp = STM32_DMA1_STREAM1;
+ ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif
+
+ /* The shared vector is initialized on driver initialization and never
+ disabled.*/
+ nvicEnableVector(ADC1_IRQn, STM32_ADC_IRQ_PRIORITY);
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+ /* If in stopped state then enables the ADC and DMA clocks.*/
+ if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+ if (&ADCD1 == adcp) {
+ bool b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
+ dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+ rccEnableADC1(FALSE);
+ }
+#endif /* STM32_ADC_USE_ADC1 */
+
+ ADC->CCR = (ADC->CCR & ADC_CCR_TSVREFE) | (STM32_ADC_ADCPRE << 16);
+
+ /* ADC initial setup, starting the analog part here in order to reduce
+ the latency when starting a conversion.*/
+ adcp->adc->CR1 = 0;
+ adcp->adc->CR2 = 0;
+ adcp->adc->CR2 = ADC_CR2_ADON;
+ }
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+ /* If in ready state then disables the ADC clock and analog part.*/
+ if (adcp->state == ADC_READY) {
+ dmaStreamRelease(adcp->dmastp);
+ adcp->adc->CR1 = 0;
+ adcp->adc->CR2 = 0;
+
+#if STM32_ADC_USE_ADC1
+ if (&ADCD1 == adcp)
+ rccDisableADC1(FALSE);
+#endif
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+ uint32_t mode;
+ uint32_t cr2;
+ const ADCConversionGroup *grpp = adcp->grpp;
+
+ /* DMA setup.*/
+ mode = adcp->dmamode;
+ if (grpp->circular) {
+ mode |= STM32_DMA_CR_CIRC;
+ if (adcp->depth > 1) {
+ /* If circular buffer depth > 1, then the half transfer interrupt
+ is enabled in order to allow streaming processing.*/
+ mode |= STM32_DMA_CR_HTIE;
+ }
+ }
+ dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+ dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+ (uint32_t)adcp->depth);
+ dmaStreamSetMode(adcp->dmastp, mode);
+ dmaStreamEnable(adcp->dmastp);
+
+ /* ADC setup.*/
+ adcp->adc->SR = 0;
+ adcp->adc->SMPR1 = grpp->smpr1;
+ adcp->adc->SMPR2 = grpp->smpr2;
+ adcp->adc->SMPR3 = grpp->smpr3;
+ adcp->adc->SQR1 = grpp->sqr1;
+ adcp->adc->SQR2 = grpp->sqr2;
+ adcp->adc->SQR3 = grpp->sqr3;
+ adcp->adc->SQR4 = grpp->sqr4;
+ adcp->adc->SQR5 = grpp->sqr5;
+
+ /* ADC configuration and start.*/
+ adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
+
+ /* Enforcing the mandatory bits in CR2.*/
+ cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
+
+ /* The start method is different dependign if HW or SW triggered, the
+ start is performed using the method specified in the CR2 configuration.*/
+ if ((cr2 & ADC_CR2_SWSTART) != 0) {
+ /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
+ adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
+
+ /* Finally enabling ADC_CR2_SWSTART.*/
+ adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
+ }
+ else
+ adcp->adc->CR2 = cr2;
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+ dmaStreamDisable(adcp->dmastp);
+ adcp->adc->CR1 = 0;
+ adcp->adc->CR2 = 0;
+ adcp->adc->CR2 = ADC_CR2_ADON;
+}
+
+/**
+ * @brief Enables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ */
+void adcSTM32EnableTSVREFE(void) {
+
+ ADC->CCR |= ADC_CCR_TSVREFE;
+}
+
+/**
+ * @brief Disables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ */
+void adcSTM32DisableTSVREFE(void) {
+
+ ADC->CCR &= ~ADC_CCR_TSVREFE;
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h
new file mode 100644
index 0000000000..4f753c3c1f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h
@@ -0,0 +1,494 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/hal_adc_lld.h
+ * @brief STM32L1xx ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Triggers selection
+ * @{
+ */
+#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */
+/** @} */
+
+/**
+ * @name ADC clock divider settings
+ * @{
+ */
+#define ADC_CCR_ADCPRE_DIV1 0
+#define ADC_CCR_ADCPRE_DIV2 1
+#define ADC_CCR_ADCPRE_DIV4 2
+/** @} */
+
+/**
+ * @name Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
+#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
+#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
+#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
+#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
+#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
+#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
+#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
+#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
+#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
+#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
+#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
+#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
+#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
+#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
+#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
+#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/
+#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */
+#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */
+#define ADC_CHANNEL_IN19 19 /**< @brief External analog input 19. */
+#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */
+#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */
+#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */
+#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */
+#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */
+#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */
+/** @} */
+
+/**
+ * @name Sampling rates
+ * @{
+ */
+#define ADC_SAMPLE_4 0 /**< @brief 4 cycles sampling time. */
+#define ADC_SAMPLE_9 1 /**< @brief 9 cycles sampling time. */
+#define ADC_SAMPLE_16 2 /**< @brief 16 cycles sampling time. */
+#define ADC_SAMPLE_24 3 /**< @brief 24 cycles sampling time. */
+#define ADC_SAMPLE_48 4 /**< @brief 48 cycles sampling time. */
+#define ADC_SAMPLE_96 5 /**< @brief 96 cycles sampling time. */
+#define ADC_SAMPLE_192 6 /**< @brief 192 cycles sampling time. */
+#define ADC_SAMPLE_384 7 /**< @brief 384 cycles sampling time. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1 FALSE
+#endif
+
+/**
+ * @brief ADC common clock divider.
+ * @note This setting is influenced by the VDDA voltage and other
+ * external conditions, please refer to the STM32L15x datasheet
+ * for more info.
+ * See section 6.3.15 "12-bit ADC characteristics".
+ */
+#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1
+#endif
+
+/**
+ * @brief ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief ADC interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief ADC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/**
+ * * @brief ADC frequency.
+ * */
+/* ADC clock related settings and checks.*/
+#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV1
+#define STM32_ADCCLK STM32_HSICLK
+#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2
+#define STM32_ADCCLK (STM32_HSICLK / 2)
+#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4
+#define STM32_ADCCLK (STM32_HSICLK / 4)
+#else
+#error "invalid STM32_ADC_ADCPRE value specified"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ * @note The use of this configuration structure requires knowledge of
+ * STM32 ADC cell registers interface, please refer to the STM32
+ * reference manual for details.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief ADC CR1 register initialization data.
+ * @note All the required bits must be defined into this field except
+ * @p ADC_CR1_SCAN that is enforced inside the driver.
+ */
+ uint32_t cr1;
+ /**
+ * @brief ADC CR2 register initialization data.
+ * @note All the required bits must be defined into this field except
+ * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+ * enforced inside the driver.
+ */
+ uint32_t cr2;
+ /**
+ * @brief ADC SMPR1 register initialization data.
+ * @details In this field must be specified the sample times for channels
+ * 20...25.
+ */
+ uint32_t smpr1;
+ /**
+ * @brief ADC SMPR2 register initialization data.
+ * @details In this field must be specified the sample times for channels
+ * 10...19.
+ */
+ uint32_t smpr2;
+ /**
+ * @brief ADC SMPR3 register initialization data.
+ * @details In this field must be specified the sample times for channels
+ * 0...9.
+ */
+ uint32_t smpr3;
+ /**
+ * @brief ADC SQR1 register initialization data.
+ * @details Conversion group sequence 25...27 + sequence length.
+ */
+ uint32_t sqr1;
+ /**
+ * @brief ADC SQR2 register initialization data.
+ * @details Conversion group sequence 19...24.
+ */
+ uint32_t sqr2;
+ /**
+ * @brief ADC SQR3 register initialization data.
+ * @details Conversion group sequence 13...18.
+ */
+ uint32_t sqr3;
+ /**
+ * @brief ADC SQR3 register initialization data.
+ * @details Conversion group sequence 7...12.
+ */
+ uint32_t sqr4;
+ /**
+ * @brief ADC SQR3 register initialization data.
+ * @details Conversion group sequence 1...6.
+ */
+ uint32_t sqr5;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ uint32_t dummy;
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig *config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t *samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the ADCx registers block.
+ */
+ ADC_TypeDef *adc;
+ /**
+ * @brief Pointer to associated DMA channel.
+ */
+ const stm32_dma_stream_t *dmastp;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Sequences building helper macros
+ * @{
+ */
+/**
+ * @brief Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
+
+#define ADC_SQR5_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
+#define ADC_SQR5_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
+#define ADC_SQR5_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
+#define ADC_SQR5_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
+#define ADC_SQR5_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
+#define ADC_SQR5_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
+
+#define ADC_SQR4_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
+#define ADC_SQR4_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
+#define ADC_SQR4_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
+#define ADC_SQR4_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
+#define ADC_SQR4_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
+#define ADC_SQR4_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
+
+#define ADC_SQR3_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
+#define ADC_SQR3_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
+#define ADC_SQR3_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
+#define ADC_SQR3_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
+#define ADC_SQR3_SQ17_N(n) ((n) << 20) /**< @brief 17th channel in seq.*/
+#define ADC_SQR3_SQ18_N(n) ((n) << 25) /**< @brief 18th channel in seq.*/
+
+#define ADC_SQR2_SQ19_N(n) ((n) << 0) /**< @brief 19th channel in seq.*/
+#define ADC_SQR2_SQ20_N(n) ((n) << 5) /**< @brief 20th channel in seq.*/
+#define ADC_SQR2_SQ21_N(n) ((n) << 10) /**< @brief 21th channel in seq.*/
+#define ADC_SQR2_SQ22_N(n) ((n) << 15) /**< @brief 22th channel in seq.*/
+#define ADC_SQR2_SQ23_N(n) ((n) << 20) /**< @brief 23th channel in seq.*/
+#define ADC_SQR2_SQ24_N(n) ((n) << 25) /**< @brief 24th channel in seq.*/
+
+#define ADC_SQR1_SQ25_N(n) ((n) << 0) /**< @brief 25th channel in seq.*/
+#define ADC_SQR1_SQ26_N(n) ((n) << 5) /**< @brief 26th channel in seq.*/
+#define ADC_SQR1_SQ27_N(n) ((n) << 10) /**< @brief 27th channel in seq.*/
+/** @} */
+
+/**
+ * @name Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR3_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
+#define ADC_SMPR3_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
+#define ADC_SMPR3_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
+#define ADC_SMPR3_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
+#define ADC_SMPR3_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
+#define ADC_SMPR3_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
+#define ADC_SMPR3_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
+#define ADC_SMPR3_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
+#define ADC_SMPR3_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
+#define ADC_SMPR3_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
+
+#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
+#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
+#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
+#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
+#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
+ sampling time. */
+#define ADC_SMPR2_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
+ sampling time. */
+#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */
+#define ADC_SMPR2_SMP_AN19(n) ((n) << 27) /**< @brief AN19 sampling time. */
+
+#define ADC_SMPR1_SMP_AN20(n) ((n) << 0) /**< @brief AN20 sampling time. */
+#define ADC_SMPR1_SMP_AN21(n) ((n) << 3) /**< @brief AN21 sampling time. */
+#define ADC_SMPR1_SMP_AN22(n) ((n) << 6) /**< @brief AN22 sampling time. */
+#define ADC_SMPR1_SMP_AN23(n) ((n) << 9) /**< @brief AN23 sampling time. */
+#define ADC_SMPR1_SMP_AN24(n) ((n) << 12) /**< @brief AN24 sampling time. */
+#define ADC_SMPR1_SMP_AN25(n) ((n) << 15) /**< @brief AN25 sampling time. */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void adc_lld_init(void);
+ void adc_lld_start(ADCDriver *adcp);
+ void adc_lld_stop(ADCDriver *adcp);
+ void adc_lld_start_conversion(ADCDriver *adcp);
+ void adc_lld_stop_conversion(ADCDriver *adcp);
+ void adcSTM32EnableTSVREFE(void);
+ void adcSTM32DisableTSVREFE(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* HAL_ADC_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c
new file mode 100644
index 0000000000..f88142aa3a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c
@@ -0,0 +1,396 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/hal_ext_lld_isr.c
+ * @brief STM32L1xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "hal_ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 0);
+ EXTI->PR = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 1);
+ EXTI->PR = pr;
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 2);
+ EXTI->PR = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 3);
+ EXTI->PR = pr;
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 4);
+ EXTI->PR = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9));
+ EXTI->PR = pr;
+ if (pr & (1U << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1U << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1U << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1U << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1U << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
+ EXTI->PR = pr;
+ if (pr & (1U << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1U << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1U << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1U << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1U << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1U << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 16);
+ EXTI->PR = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[17] interrupt handler (RTC).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 17);
+ EXTI->PR = pr;
+ if (pr & (1U << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+ OSAL_IRQ_EPILOGUE();
+}
+/**
+ * @brief EXTI[18] interrupt handler (USB_FS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE8) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 18);
+ EXTI->PR = pr;
+ if (pr & (1U << 18))
+ EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[19] interrupt handler (TAMPER_STAMP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 19);
+ EXTI->PR = pr;
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[20] interrupt handler (RTC_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 20);
+ EXTI->PR = pr;
+ if (pr & (1U << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[21]...EXTI[22] interrupt handler (COMP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector98) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & ((1U << 21) | (1U << 22));
+ EXTI->PR = pr;
+ if (pr & (1U << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1U << 22))
+ EXTD1.config->channels[22].cb(&EXTD1, 22);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if (STM32_EXTI_NUM_LINES > 23) || defined(__DOXYGEN__)
+/**
+ * @brief EXTI[23] interrupt handler (Channel Acquisition).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector120) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR;
+ pr &= EXTI->IMR & (1U << 23);
+ EXTI->PR = pr;
+ if (pr & (1U << 23))
+ EXTD1.config->channels[23].cb(&EXTD1, 23);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+ nvicEnableVector(USB_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+ nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+ nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+ nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+#if STM32_EXTI_NUM_LINES > 23
+ nvicEnableVector(COMP_ACQ_IRQn, STM32_EXT_EXTI23_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(EXTI0_IRQn);
+ nvicDisableVector(EXTI1_IRQn);
+ nvicDisableVector(EXTI2_IRQn);
+ nvicDisableVector(EXTI3_IRQn);
+ nvicDisableVector(EXTI4_IRQn);
+ nvicDisableVector(EXTI9_5_IRQn);
+ nvicDisableVector(EXTI15_10_IRQn);
+ nvicDisableVector(PVD_IRQn);
+ nvicDisableVector(RTC_Alarm_IRQn);
+ nvicDisableVector(USB_FS_WKUP_IRQn);
+ nvicDisableVector(TAMPER_STAMP_IRQn);
+ nvicDisableVector(RTC_WKUP_IRQn);
+ nvicDisableVector(COMP_IRQn);
+#if STM32_EXTI_NUM_LINES > 23
+ nvicDisableVector(COMP_ACQ_IRQn);
+#endif
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.h
new file mode 100644
index 0000000000..5f1369cc7b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.h
@@ -0,0 +1,170 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/hal_ext_lld_isr.h
+ * @brief STM32L1xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI2 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI4 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI9..5 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI15..10 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI16 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI17 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI18 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI19 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI20 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI21..22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI23 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI23_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI23_IRQ_PRIORITY 6
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_exti_irq_enable(void);
+ void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_lld.c
new file mode 100644
index 0000000000..613e490e3e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_lld.c
@@ -0,0 +1,225 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/hal_lld.c
+ * @brief STM32L1xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+/* TODO: LSEBYP like in F3.*/
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32l1xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+ /* Backup domain reset.*/
+ RCC->CSR |= RCC_CSR_RTCRST;
+ RCC->CSR &= ~RCC_CSR_RTCRST;
+ }
+
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ RCC->CSR |= RCC_CSR_LSEON;
+ while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->CSR & RCC_CSR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->CSR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->CSR |= RCC_CSR_RTCEN;
+ }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Reset of all peripherals.*/
+ rccResetAHB(~RCC_AHBRSTR_FLITFRST);
+ rccResetAPB1(~RCC_APB1RSTR_PWRRST);
+ rccResetAPB2(~0);
+
+ /* PWR clock enabled.*/
+ rccEnablePWRInterface(FALSE);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+ /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+ PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief STM32L1xx voltage, clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+/**
+ * @brief Clocks and internal voltage initialization.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+ /* PWR clock enable.*/
+ RCC->APB1ENR = RCC_APB1ENR_PWREN;
+
+ /* Core voltage setup.*/
+ while ((PWR->CSR & PWR_CSR_VOSF) != 0)
+ ; /* Waits until regulator is stable. */
+ PWR->CR = STM32_VOS;
+ while ((PWR->CSR & PWR_CSR_VOSF) != 0)
+ ; /* Waits until regulator is stable. */
+
+ /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
+ always enabled because it is the fallback clock when PLL the fails.
+ Trim fields are not altered from reset values.*/
+ RCC->CFGR = 0;
+ RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
+ RCC->CR = RCC_CR_MSION;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ; /* Waits until MSI is stable. */
+
+#if STM32_HSI_ENABLED
+ /* HSI activation.*/
+ RCC->CR |= RCC_CR_HSION;
+ while ((RCC->CR & RCC_CR_HSIRDY) == 0)
+ ; /* Waits until HSI is stable. */
+#endif
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#endif
+ /* HSE activation.*/
+ RCC->CR |= RCC_CR_HSEON;
+ while ((RCC->CR & RCC_CR_HSERDY) == 0)
+ ; /* Waits until HSE is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Waits until LSI is stable. */
+#endif
+
+#if STM32_LSE_ENABLED
+ /* LSE activation, have to unlock the register.*/
+ if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
+ PWR->CR |= PWR_CR_DBP;
+ RCC->CSR |= RCC_CSR_LSEON;
+ PWR->CR &= ~PWR_CR_DBP;
+ }
+ while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ; /* Waits until PLL is stable. */
+#endif
+
+ /* Other clock-related settings (dividers, MCO etc).*/
+ RCC->CR |= STM32_RTCPRE;
+ RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
+ STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+ RCC->CSR |= STM32_RTCSEL;
+
+ /* Flash setup and final clock selection.*/
+#if defined(STM32_FLASHBITS1)
+ FLASH->ACR = STM32_FLASHBITS1;
+#endif
+#if defined(STM32_FLASHBITS2)
+ FLASH->ACR = STM32_FLASHBITS2;
+#endif
+
+ /* Switching to the configured clock source if it is different from MSI.*/
+#if (STM32_SW != STM32_SW_MSI)
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+#endif
+#endif /* STM32_NO_INIT */
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_lld.h
new file mode 100644
index 0000000000..2d088045b7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/hal_lld.h
@@ -0,0 +1,859 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/hal_lld.h
+ * @brief STM32L1xx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32L100xB, STM32L100xBA, STM32L100xC.
+ * - STM32L151xB, STM32L151xBA, STM32L151xC, STM32L151xCA,
+ * STM32L151xD, STM32L151xDX, STM32L151xE.
+ * - STM32L152xB, STM32L152xBA, STM32L152xC, STM32L152xCA,
+ * STM32L152xD, STM32L152xDX, STM32L152xE.
+ * - STM32L162xC, STM32L162xCA, STM32L162xD, STM32L162xDX,
+ * STM32L162xE.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#if defined(STM32L100xB) || defined(STM32L151xB) || \
+ defined(STM32L152xB) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density"
+
+#elif defined(STM32L100xBA) || defined(STM32L100xC) || \
+ defined(STM32L151xBA) || defined(STM32L151xC) || \
+ defined(STM32L151xCA) || defined(STM32L152xBA) || \
+ defined(STM32L152xC) || defined(STM32L152xCA) || \
+ defined(STM32L162xC) || defined(STM32L162xCA)
+#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density Plus"
+
+#elif defined(STM32L151xD) || defined(STM32L151xDX) || \
+ defined(STM32L151xE) || defined(STM32L152xD) || \
+ defined(STM32L152xDX) || defined(STM32L152xE) || \
+ defined(STM32L162xD) || defined(STM32L162xDX) || \
+ defined(STM32L162xE)
+#define PLATFORM_NAME "STM32L1xx Ultra Low Power High Density"
+
+#else
+#error "STM32L1xx device not specified"
+#endif
+
+/**
+ * @brief Sub-family identifier.
+ */
+#if !defined(STM32L1XX) || defined(__DOXYGEN__)
+#define STM32L1XX
+#endif
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK 16000000 /**< High speed internal clock. */
+#define STM32_LSICLK 38000 /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */
+#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */
+#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
+#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */
+
+#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
+#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
+/** @} */
+
+/**
+ * @name RCC_CR register bits definitions
+ * @{
+ */
+#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */
+#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */
+#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */
+#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */
+#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
+#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */
+#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
+#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
+#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
+#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
+#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
+
+#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
+#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
+#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
+#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
+#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
+
+#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
+#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
+
+#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_HSI (2 << 24) /**< HSI clock on MCO pin. */
+#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */
+#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
+#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
+#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
+
+#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
+#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
+#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
+#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
+/** @} */
+
+/**
+ * @name RCC_ICSCR register bits definitions
+ * @{
+ */
+#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
+#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */
+#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */
+#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */
+#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */
+#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
+#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
+#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
+/** @} */
+
+/**
+ * @name RCC_CSR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
+#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
+#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
+#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
+#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Core voltage selection.
+ * @note This setting affects all the performance and clock related
+ * settings, the maximum performance is only obtainable selecting
+ * the maximum voltage.
+ */
+#if !defined(STM32_VOS) || defined(__DOXYGEN__)
+#define STM32_VOS STM32_VOS_1P8
+#endif
+
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief ADC clock setting.
+ */
+#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_ADC_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief MSI frequency setting.
+ */
+#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
+#define STM32_MSIRANGE STM32_MSIRANGE_2M
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_HSI
+#endif
+
+/**
+ * @brief PLL multiplier value.
+ * @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE 6
+#endif
+
+/**
+ * @brief PLL divider value.
+ * @note The allowed values are 2, 3, 4.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLDIV_VALUE 3
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#endif
+
+/**
+ * @brief MCO clock source.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief RTC/LCD clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSE
+#endif
+
+/**
+ * @brief HSE divider toward RTC setting.
+ */
+#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
+#define STM32_RTCPRE STM32_RTCPRE_DIV2
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32L1xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L1xx_MCUCONF not defined"
+#endif
+
+/* Voltage related limits.*/
+#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
+/**
+ * @brief Maximum HSE clock frequency at current voltage setting.
+ */
+#define STM32_HSECLK_MAX 32000000
+
+/**
+ * @brief Maximum SYSCLK clock frequency at current voltage setting.
+ */
+#define STM32_SYSCLK_MAX 32000000
+
+/**
+ * @brief Maximum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MAX 96000000
+
+/**
+ * @brief Minimum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MIN 6000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX 32000000
+
+/**
+ * @brief Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX 32000000
+
+/**
+ * @brief Maximum frequency not requiring a wait state for flash accesses.
+ */
+#define STM32_0WS_THRESHOLD 16000000
+
+/**
+ * @brief HSI availability at current voltage settings.
+ */
+#define STM32_HSI_AVAILABLE TRUE
+
+#elif STM32_VOS == STM32_VOS_1P5
+#define STM32_HSECLK_MAX 16000000
+#define STM32_SYSCLK_MAX 16000000
+#define STM32_PLLVCO_MAX 48000000
+#define STM32_PLLVCO_MIN 6000000
+#define STM32_PCLK1_MAX 16000000
+#define STM32_PCLK2_MAX 16000000
+#define STM32_0WS_THRESHOLD 8000000
+#define STM32_HSI_AVAILABLE TRUE
+#elif STM32_VOS == STM32_VOS_1P2
+#define STM32_HSECLK_MAX 4000000
+#define STM32_SYSCLK_MAX 4000000
+#define STM32_PLLVCO_MAX 24000000
+#define STM32_PLLVCO_MIN 6000000
+#define STM32_PCLK1_MAX 4000000
+#define STM32_PCLK2_MAX 4000000
+#define STM32_0WS_THRESHOLD 2000000
+#define STM32_HSI_AVAILABLE FALSE
+#else
+#error "invalid STM32_VOS value specified"
+#endif
+
+/* HSI related checks.*/
+#if STM32_HSI_ENABLED
+#if !STM32_HSI_AVAILABLE
+ #error "impossible to activate HSI under the current voltage settings"
+#endif
+#else /* !STM32_HSI_ENABLED */
+#if STM32_ADC_CLOCK_ENABLED || \
+ (STM32_SW == STM32_SW_HSI) || \
+ ((STM32_SW == STM32_SW_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)) || \
+ (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "required HSI clock is not enabled"
+#endif
+#endif /* !STM32_HSI_ENABLED */
+
+/* HSE related checks.*/
+#if STM32_HSE_ENABLED
+#if STM32_HSECLK == 0
+#error "impossible to activate HSE"
+#endif
+#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
+#endif
+#else /* !STM32_HSE_ENABLED */
+#if (STM32_SW == STM32_SW_HSE) || \
+ ((STM32_SW == STM32_SW_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
+ (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
+ (STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
+#error "required HSE clock is not enabled"
+#endif
+#endif /* !STM32_HSE_ENABLED */
+
+/* LSI related checks.*/
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_LSI
+#error "LSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/* LSE related checks.*/
+#if STM32_LSE_ENABLED
+#if (STM32_LSECLK == 0)
+#error "impossible to activate LSE"
+#endif
+#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
+#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
+#endif
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_LSE
+#error "LSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL related checks.*/
+#if STM32_USB_CLOCK_ENABLED || \
+ (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/**
+ * @brief PLLMUL field.
+ */
+#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)
+#define STM32_PLLMUL (0 << 18)
+#elif STM32_PLLMUL_VALUE == 4
+#define STM32_PLLMUL (1 << 18)
+#elif STM32_PLLMUL_VALUE == 6
+#define STM32_PLLMUL (2 << 18)
+#elif STM32_PLLMUL_VALUE == 8
+#define STM32_PLLMUL (3 << 18)
+#elif STM32_PLLMUL_VALUE == 12
+#define STM32_PLLMUL (4 << 18)
+#elif STM32_PLLMUL_VALUE == 16
+#define STM32_PLLMUL (5 << 18)
+#elif STM32_PLLMUL_VALUE == 24
+#define STM32_PLLMUL (6 << 18)
+#elif STM32_PLLMUL_VALUE == 32
+#define STM32_PLLMUL (7 << 18)
+#elif STM32_PLLMUL_VALUE == 48
+#define STM32_PLLMUL (8 << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLDIV field.
+ */
+#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLDIV (1 << 22)
+#elif STM32_PLLDIV_VALUE == 3
+#define STM32_PLLDIV (2 << 22)
+#elif STM32_PLLDIV_VALUE == 4
+#define STM32_PLLDIV (3 << 22)
+#else
+#error "invalid STM32_PLLDIV_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN STM32_HSECLK
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN STM32_HSICLK
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000)
+#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)"
+#endif
+
+/**
+ * @brief PLL VCO frequency.
+ */
+#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000)
+#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"
+#endif
+
+/**
+ * @brief MSI frequency.
+ */
+#if STM32_MSIRANGE == STM32_MSIRANGE_64K
+#define STM32_MSICLK 65500
+#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
+#define STM32_MSICLK 131000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
+#define STM32_MSICLK 262000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
+#define STM32_MSICLK 524000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
+#define STM32_MSICLK 1050000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
+#define STM32_MSICLK 2100000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
+#define STM32_MSICLK 4200000
+#else
+#error "invalid STM32_MSIRANGE value specified"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+#define STM32_SYSCLK 2100000
+#elif (STM32_SW == STM32_SW_MSI)
+#define STM32_SYSCLK STM32_MSICLK
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+#elif (STM32_SW == STM32_SW_PLL)
+#define STM32_SYSCLK STM32_PLLCLKOUT
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief MCO clock before divider.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_MCODIVCLK 0
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI
+#define STM32_MCODIVCLK STM32_HSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_MSI
+#define STM32_MCODIVCLK STM32_MSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+#define STM32_MCODIVCLK STM32_HSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_PLL
+#define STM32_MCODIVCLK STM32_PLLCLKOUT
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+#define STM32_MCODIVCLK STM32_LSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+#define STM32_MCODIVCLK STM32_LSECLK
+#else
+#error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief MCO output pin clock.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCOCLK STM32_MCODIVCLK
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
+#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
+#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
+#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
+#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
+/**
+ * @brief HSE divider toward RTC clock.
+ */
+#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 2)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 4)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 8)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 16)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief RTC/LCD clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK 0
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK STM32_HSEDIVCLK
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief USB frequency.
+ */
+#define STM32_USBCLK (STM32_PLLVCO / 2)
+
+/**
+ * @brief Timers 2, 3, 4, 6, 7 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Timers 9, 10, 11 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS1 0x00000000
+#else
+#define STM32_FLASHBITS1 0x00000004
+#define STM32_FLASHBITS2 0x00000007
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/platform.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/platform.dox
similarity index 54%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/platform.dox
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/platform.dox
index d64d5764d6..f1fc5be6b1 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F4xx/platform.dox
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/platform.dox
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,25 +15,23 @@
*/
/**
- * @defgroup STM32F4xx_DRIVERS STM32F4xx/STM32F2xx Drivers
- * @details This section describes all the supported drivers on the STM32F4xx
- * and STM32F2xx platform and the implementation details of the single
- * drivers.
+ * @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers
+ * @details This section describes all the supported drivers on the STM32L1xx
+ * platform and the implementation details of the single drivers.
*
* @ingroup platforms
*/
/**
- * @defgroup STM32F4xx_HAL STM32F4xx Initialization Support
- * @details The STM32F4xx HAL support is responsible for system initialization.
+ * @defgroup STM32L1xx_HAL STM32L1xx Initialization Support
+ * @details The STM32L1xx HAL support is responsible for system initialization.
*
- * @section stm32f4xx_hal_1 Supported HW resources
+ * @section stm32l1xx_hal_1 Supported HW resources
* - PLL1.
- * - PLL2.
* - RCC.
* - Flash.
* .
- * @section stm32f4xx_hal_2 STM32F4xx HAL driver implementation features
+ * @section stm32l1xx_hal_2 STM32L1xx HAL driver implementation features
* - PLL startup and stabilization.
* - Clock tree initialization.
* - Clock source selection.
@@ -41,21 +39,19 @@
* - SYSTICK initialization based on current clock and kernel required rate.
* - DMA support initialization.
* .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_ADC STM32F4xx ADC Support
- * @details The STM32F4xx ADC driver supports the ADC peripherals using DMA
+ * @defgroup STM32L1xx_ADC STM32L1xx ADC Support
+ * @details The STM32L1xx ADC driver supports the ADC peripherals using DMA
* channels for maximum performance.
*
- * @section stm32f4xx_adc_1 Supported HW resources
+ * @section stm32l1xx_adc_1 Supported HW resources
* - ADC1.
- * - ADC2.
- * - ADC3.
- * - DMA2.
+ * - DMA1.
* .
- * @section stm32f4xx_adc_2 STM32F4xx ADC driver implementation features
+ * @section stm32l1xx_adc_2 STM32L1xx ADC driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Streaming conversion using DMA for maximum performance.
* - Programmable ADC interrupt priority level.
@@ -63,110 +59,71 @@
* - Programmable DMA interrupt priority for each DMA channel.
* - DMA and ADC errors detection.
* .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_CAN STM32F4xx CAN Support
- * @details The STM32F4xx CAN driver uses the CAN peripherals.
- *
- * @section stm32f4xx_can_1 Supported HW resources
- * - bxCAN1.
- * .
- * @section stm32f4xx_can_2 STM32F4xx CAN driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Support for bxCAN sleep mode.
- * - Programmable bxCAN interrupts priority level.
- * .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_EXT STM32F4xx EXT Support
- * @details The STM32F4xx EXT driver uses the EXTI peripheral.
+ * @defgroup STM32L1xx_EXT STM32L1xx EXT Support
+ * @details The STM32L1xx EXT driver uses the EXTI peripheral.
*
- * @section stm32f4xx_ext_1 Supported HW resources
+ * @section stm32l1xx_ext_1 Supported HW resources
* - EXTI.
* .
- * @section stm32f4xx_ext_2 STM32F4xx EXT driver implementation features
+ * @section stm32l1xx_ext_2 STM32L1xx EXT driver implementation features
* - Each EXTI channel can be independently enabled and programmed.
* - Programmable EXTI interrupts priority level.
* - Capability to work as event sources (WFE) rather than interrupt sources.
* .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_GPT STM32F4xx GPT Support
- * @details The STM32F4xx GPT driver uses the TIMx peripherals.
+ * @defgroup STM32L1xx_GPT STM32L1xx GPT Support
+ * @details The STM32L1xx GPT driver uses the TIMx peripherals.
*
- * @section stm32f4xx_gpt_1 Supported HW resources
- * - TIM1.
+ * @section stm32l1xx_gpt_1 Supported HW resources
* - TIM2.
* - TIM3.
* - TIM4.
- * - TIM5.
- * - TIM8.
* .
- * @section stm32f4xx_gpt_2 STM32F4xx GPT driver implementation features
+ * @section stm32l1xx_gpt_2 STM32L1xx GPT driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_ICU STM32F4xx ICU Support
- * @details The STM32F4xx ICU driver uses the TIMx peripherals.
+ * @defgroup STM32L1xx_ICU STM32L1xx ICU Support
+ * @details The STM32L1xx ICU driver uses the TIMx peripherals.
*
- * @section stm32f4xx_icu_1 Supported HW resources
- * - TIM1.
+ * @section stm32l1xx_icu_1 Supported HW resources
* - TIM2.
* - TIM3.
* - TIM4.
- * - TIM5.
- * - TIM8.
* .
- * @section stm32f4xx_icu_2 STM32F4xx ICU driver implementation features
+ * @section stm32l1xx_icu_2 STM32L1xx ICU driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_MAC STM32F4xx MAC Support
- * @details The STM32F4xx MAC driver supports the ETH peripheral.
- *
- * @section stm32f4xx_mac_1 Supported HW resources
- * - ETH.
- * - PHY (external).
- * .
- * @section stm32f4xx_mac_2 STM32F4xx MAC driver implementation features
- * - Dedicated DMA operations.
- * - Support for checksum off-loading.
- * .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_PAL STM32F4xx PAL Support
- * @details The STM32F4xx PAL driver uses the GPIO peripherals.
+ * @defgroup STM32L1xx_PAL STM32L1xx PAL Support
+ * @details The STM32L1xx PAL driver uses the GPIO peripherals.
*
- * @section stm32f4xx_pal_1 Supported HW resources
+ * @section stm32l1xx_pal_1 Supported HW resources
* - GPIOA.
* - GPIOB.
* - GPIOC.
* - GPIOD.
* - GPIOE.
- * - GPIOF.
- * - GPIOG.
* - GPIOH.
- * - GPIOI.
* .
- * @section stm32f4xx_pal_2 STM32F4xx PAL driver implementation features
+ * @section stm32l1xx_pal_2 STM32L1xx PAL driver implementation features
* The PAL driver implementation fully supports the following hardware
* capabilities:
* - 16 bits wide ports.
@@ -175,8 +132,8 @@
* - Output latched regardless of the pad setting.
* - Direct read of input pads regardless of the pad setting.
* .
- * @section stm32f4xx_pal_3 Supported PAL setup modes
- * The STM32F4xx PAL driver supports the following I/O modes:
+ * @section stm32l1xx_pal_3 Supported PAL setup modes
+ * The STM32L1xx PAL driver supports the following I/O modes:
* - @p PAL_MODE_RESET.
* - @p PAL_MODE_UNCONNECTED.
* - @p PAL_MODE_INPUT.
@@ -189,90 +146,70 @@
* .
* Any attempt to setup an invalid mode is ignored.
*
- * @section stm32f4xx_pal_4 Suboptimal behavior
- * The STM32F4xx GPIO is less than optimal in several areas, the limitations
+ * @section stm32l1xx_pal_4 Suboptimal behavior
+ * The STM32L1xx GPIO is less than optimal in several areas, the limitations
* should be taken in account while using the PAL driver:
* - Pad/port toggling operations are not atomic.
* - Pad/group mode setup is not atomic.
* .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_PWM STM32F4xx PWM Support
- * @details The STM32F4xx PWM driver uses the TIMx peripherals.
+ * @defgroup STM32L1xx_PWM STM32L1xx PWM Support
+ * @details The STM32L1xx PWM driver uses the TIMx peripherals.
*
- * @section stm32f4xx_pwm_1 Supported HW resources
+ * @section stm32l1xx_pwm_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
- * - TIM5.
- * - TIM8.
* .
- * @section stm32f4xx_pwm_2 STM32F4xx PWM driver implementation features
+ * @section stm32l1xx_pwm_2 STM32L1xx PWM driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Four independent PWM channels per timer.
* - Programmable TIMx interrupts priority level.
* .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_SDC STM32F4xx SDC Support
- * @details The STM32F4xx SDC driver uses the SDIO peripheral.
- *
- * @section stm32f4xx_sdc_1 Supported HW resources
- * - SDIO.
- * - DMA2.
- * .
- * @section stm32f4xx_sdc_2 STM32F4xx SDC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_SERIAL STM32F4xx Serial Support
- * @details The STM32F4xx Serial driver uses the USART/UART peripherals in a
+ * @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support
+ * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a
* buffered, interrupt driven, implementation.
*
- * @section stm32f4xx_serial_1 Supported HW resources
+ * @section stm32l1xx_serial_1 Supported HW resources
* The serial driver can support any of the following hardware resources:
* - USART1.
* - USART2.
- * - USART3.
- * - UART4.
- * - UART5.
- * - USART6.
+ * - USART3 (where present).
+ * - UART4 (where present).
+ * - UART5 (where present).
* .
- * @section stm32f4xx_serial_2 STM32F4xx Serial driver implementation features
+ * @section stm32l1xx_serial_2 STM32L1xx Serial driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Fully interrupt driven.
* - Programmable priority levels for each UART/USART.
* .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_SPI STM32F4xx SPI Support
- * @details The SPI driver supports the STM32F4xx SPI peripherals using DMA
+ * @defgroup STM32L1xx_SPI STM32L1xx SPI Support
+ * @details The SPI driver supports the STM32L1xx SPI peripherals using DMA
* channels for maximum performance.
*
- * @section stm32f4xx_spi_1 Supported HW resources
+ * @section stm32l1xx_spi_1 Supported HW resources
* - SPI1.
* - SPI2.
- * - SPI3.
+ * - SPI3 (where present).
* - DMA1.
- * - DMA2.
+ * - DMA2 (where present).
* .
- * @section stm32f4xx_spi_2 STM32F4xx SPI driver implementation features
+ * @section stm32l1xx_spi_2 STM32L1xx SPI driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each SPI can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
@@ -282,23 +219,22 @@
* - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_UART STM32F4xx UART Support
- * @details The UART driver supports the STM32F4xx USART peripherals using DMA
+ * @defgroup STM32L1xx_UART STM32L1xx UART Support
+ * @details The UART driver supports the STM32L1xx USART peripherals using DMA
* channels for maximum performance.
*
- * @section stm32f4xx_uart_1 Supported HW resources
+ * @section stm32l1xx_uart_1 Supported HW resources
* The UART driver can support any of the following hardware resources:
* - USART1.
* - USART2.
- * - USART3.
+ * - USART3 (where present).
* - DMA1.
- * - DMA2.
* .
- * @section stm32f4xx_uart_2 STM32F4xx UART driver implementation features
+ * @section stm32l1xx_uart_2 STM32L1xx UART driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
@@ -308,57 +244,72 @@
* - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_USB STM32L1xx USB Support
+ * @details The USB driver supports the STM32L1xx USB peripheral.
+ *
+ * @section stm32l1xx_usb_1 Supported HW resources
+ * The USB driver can support any of the following hardware resources:
+ * - USB.
+ * .
+ * @section stm32l1xx_usb_2 STM32L1xx USB driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Programmable interrupt priority levels.
+ * - Each endpoint programmable in Control, Bulk and Interrupt modes.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_PLATFORM_DRIVERS STM32F4xx Platform Drivers
+ * @defgroup STM32L1xx_PLATFORM_DRIVERS STM32L1xx Platform Drivers
* @details Platform support drivers. Platform drivers do not implement HAL
* standard driver templates, their role is to support platform
* specific functionalities.
*
- * @ingroup STM32F4xx_DRIVERS
+ * @ingroup STM32L1xx_DRIVERS
*/
/**
- * @defgroup STM32F4xx_DMA STM32F4xx DMA Support
+ * @defgroup STM32L1xx_DMA STM32L1xx DMA Support
* @details This DMA helper driver is used by the other drivers in order to
* access the shared DMA resources in a consistent way.
*
- * @section stm32f4xx_dma_1 Supported HW resources
+ * @section stm32l1xx_dma_1 Supported HW resources
* The DMA driver can support any of the following hardware resources:
* - DMA1.
- * - DMA2.
* .
- * @section stm32f4xx_dma_2 STM32F4xx DMA driver implementation features
+ * @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features
* - Exports helper functions/macros to the other drivers that share the
* DMA resource.
* - Automatic DMA clock stop when not in use by any driver.
* - DMA streams and interrupt vectors sharing among multiple drivers.
* .
- * @ingroup STM32F4xx_PLATFORM_DRIVERS
+ * @ingroup STM32L1xx_PLATFORM_DRIVERS
*/
/**
- * @defgroup STM32F4xx_ISR STM32F4xx ISR Support
+ * @defgroup STM32L1xx_ISR STM32L1xx ISR Support
* @details This ISR helper driver is used by the other drivers in order to
* map ISR names to physical vector names.
*
- * @ingroup STM32F4xx_PLATFORM_DRIVERS
+ * @ingroup STM32L1xx_PLATFORM_DRIVERS
*/
/**
- * @defgroup STM32F4xx_RCC STM32F4xx RCC Support
+ * @defgroup STM32L1xx_RCC STM32L1xx RCC Support
* @details This RCC helper driver is used by the other drivers in order to
* access the shared RCC resources in a consistent way.
*
- * @section stm32f4xx_rcc_1 Supported HW resources
+ * @section stm32f1xx_rcc_1 Supported HW resources
* - RCC.
* .
- * @section stm32f4xx_rcc_2 STM32F4xx RCC driver implementation features
+ * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
* - Peripherals clock disable.
* .
- * @ingroup STM32F4xx_PLATFORM_DRIVERS
+ * @ingroup STM32L1xx_PLATFORM_DRIVERS
*/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/platform.mk
new file mode 100644
index 0000000000..84f6daa250
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/platform.mk
@@ -0,0 +1,35 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c
+endif
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
+endif
+else
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_isr.h
new file mode 100644
index 0000000000..2f3e6e7142
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_isr.h
@@ -0,0 +1,118 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/stm32_isr.h
+ * @brief ISR remapper driver header.
+ *
+ * @addtogroup STM32L1xx_ISR
+ * @{
+ */
+
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name ISR names and numbers remapping
+ * @{
+ */
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_NUMBER 32
+
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_NUMBER 34
+
+/*
+ * TIM units.
+ */
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM5_HANDLER VectorF8
+#define STM32_TIM6_HANDLER VectorEC
+#define STM32_TIM7_HANDLER VectorF0
+#define STM32_TIM9_HANDLER VectorA4
+#define STM32_TIM10_HANDLER VectorA8
+#define STM32_TIM11_HANDLER VectorAC
+
+#define STM32_TIM2_NUMBER 28
+#define STM32_TIM3_NUMBER 29
+#define STM32_TIM4_NUMBER 30
+#define STM32_TIM5_NUMBER 46
+#define STM32_TIM6_NUMBER 43
+#define STM32_TIM7_NUMBER 44
+#define STM32_TIM9_NUMBER 25
+#define STM32_TIM10_NUMBER 26
+#define STM32_TIM11_NUMBER 27
+
+/*
+ * USART units.
+ */
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_UART4_HANDLER Vector100
+#define STM32_UART5_HANDLER Vector104
+
+#define STM32_USART1_NUMBER 37
+#define STM32_USART2_NUMBER 38
+#define STM32_USART3_NUMBER 39
+#define STM32_UART4_NUMBER 48
+#define STM32_UART5_NUMBER 49
+/*
+ * USB units.
+ */
+#define STM32_USB1_HP_HANDLER Vector8C
+#define STM32_USB1_LP_HANDLER Vector90
+
+#define STM32_USB1_HP_NUMBER 19
+#define STM32_USB1_LP_NUMBER 20
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#endif /* STM32_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
similarity index 84%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_rcc.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
index 4d57382afd..f0b8b0e937 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32F30x/stm32_rcc.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,12 +15,12 @@
*/
/**
- * @file STM32F30x/stm32_rcc.h
+ * @file STM32L1xx/stm32_rcc.h
* @brief RCC helper driver header.
* @note This file requires definitions from the ST header file
- * @p stm32f30x.h.
+ * @p stm32l1xx.h.
*
- * @addtogroup STM32F30x_RCC
+ * @addtogroup STM32L1xx_RCC
* @{
*/
@@ -61,6 +61,8 @@
*/
#define rccEnableAPB1(mask, lp) { \
RCC->APB1ENR |= (mask); \
+ if (lp) \
+ RCC->APB1LPENR |= (mask); \
}
/**
@@ -73,6 +75,8 @@
*/
#define rccDisableAPB1(mask, lp) { \
RCC->APB1ENR &= ~(mask); \
+ if (lp) \
+ RCC->APB1LPENR &= ~(mask); \
}
/**
@@ -97,6 +101,8 @@
*/
#define rccEnableAPB2(mask, lp) { \
RCC->APB2ENR |= (mask); \
+ if (lp) \
+ RCC->APB2LPENR |= (mask); \
}
/**
@@ -109,6 +115,8 @@
*/
#define rccDisableAPB2(mask, lp) { \
RCC->APB2ENR &= ~(mask); \
+ if (lp) \
+ RCC->APB2LPENR &= ~(mask); \
}
/**
@@ -133,6 +141,8 @@
*/
#define rccEnableAHB(mask, lp) { \
RCC->AHBENR |= (mask); \
+ if (lp) \
+ RCC->AHBLPENR |= (mask); \
}
/**
@@ -145,6 +155,8 @@
*/
#define rccDisableAHB(mask, lp) { \
RCC->AHBENR &= ~(mask); \
+ if (lp) \
+ RCC->AHBLPENR &= ~(mask); \
}
/**
@@ -165,86 +177,59 @@
* @{
*/
/**
- * @brief Enables the ADC1/ADC2 peripheral clock.
+ * @brief Enables the ADC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
+#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
/**
- * @brief Disables the ADC1/ADC2 peripheral clock.
+ * @brief Disables the ADC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
+#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
/**
- * @brief Resets the ADC1/ADC2 peripheral.
+ * @brief Resets the ADC1 peripheral.
*
* @api
*/
-#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
-
-/**
- * @brief Enables the ADC3/ADC4 peripheral clock.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
-
-/**
- * @brief Disables the ADC3/ADC4 peripheral clock.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
-
-/**
- * @brief Resets the ADC3/ADC4 peripheral.
- *
- * @api
- */
-#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
+#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */
/**
- * @name CAN peripherals specific RCC operations
+ * @name DAC peripheral specific RCC operations
* @{
*/
/**
- * @brief Enables the CAN1 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
/**
- * @brief Disables the CAN1 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
/**
- * @brief Resets the CAN1 peripheral.
+ * @brief Resets the DAC1 peripheral.
*
* @api
*/
-#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
/** @} */
/**
@@ -442,217 +427,243 @@
* @api
*/
#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+/** @} */
/**
- * @brief Enables the SPI3 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
- * @brief Disables the SPI3 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Disables the TIM2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
- * @brief Resets the SPI3 peripheral.
+ * @brief Resets the TIM2 peripheral.
*
* @api
*/
-#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
-/** @} */
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
/**
- * @name TIM peripherals specific RCC operations
- * @{
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
*/
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
/**
- * @brief Enables the TIM1 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Disables the TIM3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
- * @brief Disables the TIM1 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+
+/**
+ * @brief Enables the TIM4 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
/**
- * @brief Resets the TIM1 peripheral.
+ * @brief Disables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
*
* @api
*/
-#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
/**
- * @brief Enables the TIM2 peripheral clock.
+ * @brief Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+
+/**
+ * @brief Enables the TIM5 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
/**
- * @brief Disables the TIM2 peripheral clock.
+ * @brief Disables the TIM5 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)
/**
- * @brief Resets the TIM2 peripheral.
+ * @brief Resets the TIM5 peripheral.
*
* @api
*/
-#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
/**
- * @brief Enables the TIM3 peripheral clock.
+ * @brief Enables the TIM6 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
/**
- * @brief Disables the TIM3 peripheral clock.
+ * @brief Disables the TIM6 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
/**
- * @brief Resets the TIM3 peripheral.
+ * @brief Resets the TIM6 peripheral.
*
* @api
*/
-#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
/**
- * @brief Enables the TIM4 peripheral clock.
+ * @brief Enables the TIM7 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
/**
- * @brief Disables the TIM4 peripheral clock.
+ * @brief Disables the TIM7 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
/**
- * @brief Resets the TIM4 peripheral.
+ * @brief Resets the TIM7 peripheral.
*
* @api
*/
-#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
/**
- * @brief Enables the TIM6 peripheral clock.
+ * @brief Enables the TIM9 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
/**
- * @brief Disables the TIM6 peripheral clock.
+ * @brief Disables the TIM9 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)
/**
- * @brief Resets the TIM6 peripheral.
+ * @brief Resets the TIM9 peripheral.
*
* @api
*/
-#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
/**
- * @brief Enables the TIM7 peripheral clock.
+ * @brief Enables the TIM10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
/**
- * @brief Disables the TIM7 peripheral clock.
+ * @brief Disables the TIM10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
/**
- * @brief Resets the TIM7 peripheral.
+ * @brief Resets the TIM10 peripheral.
*
* @api
*/
-#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
/**
- * @brief Enables the TIM8 peripheral clock.
+ * @brief Enables the TIM10 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)
/**
- * @brief Disables the TIM8 peripheral clock.
+ * @brief Disables the TIM11 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp)
/**
- * @brief Resets the TIM8 peripheral.
+ * @brief Resets the TIM11 peripheral.
*
* @api
*/
-#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
+#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)
+
/** @} */
/**
@@ -736,7 +747,6 @@
/**
* @brief Enables the UART4 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
@@ -746,7 +756,6 @@
/**
* @brief Disables the UART4 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
@@ -763,7 +772,6 @@
/**
* @brief Enables the UART5 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
@@ -773,7 +781,6 @@
/**
* @brief Disables the UART5 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
new file mode 100644
index 0000000000..b593b1519a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
@@ -0,0 +1,350 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/stm32_registry.h
+ * @brief STM32L1xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
+#define STM32L1XX_PROD_CAT 1
+
+#elif defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)
+#define STM32L1XX_PROD_CAT 2
+
+#elif defined(STM32L100xC) || defined(STM32L151xC) || \
+ defined(STM32L151xCA) || defined(STM32L152xC) || \
+ defined(STM32L152xCA) || defined(STM32L162xC) || \
+ defined(STM32L162xCA)
+#define STM32L1XX_PROD_CAT 3
+
+#elif defined(STM32L151xD) || defined(STM32L152xD) || \
+ defined(STM32L162xD)
+#define STM32L1XX_PROD_CAT 4
+
+#elif defined(STM32L151xE) || defined (STM32L152xE) || \
+ defined(STM32L162xE)
+#define STM32L1XX_PROD_CAT 5
+
+#elif defined(STM32L151xDX) || defined (STM32L152xDX) || \
+ defined(STM32L162xDX)
+#define STM32L1XX_PROD_CAT 6
+
+#else
+#error "STM32L1xx device not specified"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32L1xx capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
+ defined(__DOXYGEN__)
+#define STM32_DMA2_NUM_CHANNELS 0
+#else
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector108
+#define STM32_DMA2_CH2_HANDLER Vector10C
+#define STM32_DMA2_CH3_HANDLER Vector110
+#define STM32_DMA2_CH4_HANDLER Vector114
+#define STM32_DMA2_CH5_HANDLER Vector118
+#define STM32_DMA2_CH1_NUMBER 50
+#define STM32_DMA2_CH2_NUMBER 51
+#define STM32_DMA2_CH3_NUMBER 52
+#define STM32_DMA2_CH4_NUMBER 53
+#define STM32_DMA2_CH5_NUMBER 54
+#endif
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
+ defined(__DOXYGEN__)
+#define STM32_EXTI_NUM_LINES 23
+#else
+#define STM32_EXTI_NUM_LINES 24
+#endif
+#define STM32_EXTI_IMR_MASK 0x00000000U
+
+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
+ (STM32L1XX_PROD_CAT == 3) || defined(__DOXYGEN__)
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOHEN)
+#else
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+#endif
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#if (STM32L1XX_PROD_CAT == 1) || defined(__DOXYGEN__)
+#define STM32_RTC_HAS_SUBSECONDS FALSE
+#else
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#endif
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
+ defined(__DOXYGEN__)
+#define STM32_HAS_SPI3 FALSE
+#else
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#endif
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
+ defined(__DOXYGEN__)
+#define STM32_HAS_TIM5 FALSE
+#else
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+#endif
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 2
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 2
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
+ (STM32L1XX_PROD_CAT == 3) || defined(__DOXYGEN__)
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#else
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#endif
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
+#define STM32_USB_PMA_SIZE 512
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE FALSE
+
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c
new file mode 100644
index 0000000000..9babc93057
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c
@@ -0,0 +1,361 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/hal_ext_lld_isr.c
+ * @brief STM32L4xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "hal_ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 0);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 1);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 2);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 3);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 4);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9));
+ EXTI->PR1 = pr;
+ if (pr & (1U << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1U << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1U << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1U << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1U << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
+ EXTI->PR1 = pr;
+ if (pr & (1U << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1U << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1U << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1U << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1U << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1U << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[16/35/36/37/38] interrupt handler (PVD/PVM1/PVM2/PVM3/PVM4)
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 16);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ pr = EXTI->PR2 & EXTI->IMR2 & ( (1U << (35-32)) | (1U << (36-32)) |
+ (1U << (37-32)) | (1U << (38-32)) );
+ EXTI->PR2 = pr;
+ if (pr & (1U << (35-32)))
+ EXTD1.config->channels[35].cb(&EXTD1, 35);
+ if (pr & (1U << (36-32)))
+ EXTD1.config->channels[36].cb(&EXTD1, 36);
+ if (pr & (1U << (37-32)))
+ EXTD1.config->channels[37].cb(&EXTD1, 37);
+ if (pr & (1U << (38-32)))
+ EXTD1.config->channels[38].cb(&EXTD1, 38);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[18] interrupt handler (RTC_ALARM).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 18);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 18))
+ EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[19] interrupt handler (RTC_TAMP_STAMP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 19);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[20] interrupt handler (RTC_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 20);
+ EXTI->PR1 = pr;
+ if (pr & (1U << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[21/22] interrupt handler (COMP1,COMP2).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector140) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & ( (1U << 21) | ( 1U << 22 ) );
+ EXTI->PR1 = pr;
+ if (pr & (1U << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1U << 22))
+ EXTD1.config->channels[22].cb(&EXTD1, 22);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_PVM_IRQn, STM32_EXT_EXTI1635_38_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+ nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+ nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+ nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(EXTI0_IRQn);
+ nvicDisableVector(EXTI1_IRQn);
+ nvicDisableVector(EXTI2_IRQn);
+ nvicDisableVector(EXTI3_IRQn);
+ nvicDisableVector(EXTI4_IRQn);
+ nvicDisableVector(EXTI9_5_IRQn);
+ nvicDisableVector(EXTI15_10_IRQn);
+ nvicDisableVector(PVD_PVM_IRQn);
+ nvicDisableVector(RTC_Alarm_IRQn);
+ nvicDisableVector(TAMP_STAMP_IRQn);
+ nvicDisableVector(RTC_WKUP_IRQn);
+ nvicDisableVector(COMP_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.h
new file mode 100644
index 0000000000..a57199af35
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.h
@@ -0,0 +1,156 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/hal_ext_lld_isr.h
+ * @brief STM32L4xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_ISR_H
+#define HAL_EXT_LLD_ISR_H
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI2 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI4 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI9..5 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI15..10 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI16-EXTI35..38 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI1635_38_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI1635_38_IRQ_PRIORIT 6
+#endif
+
+/**
+ * @brief EXTI18 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI19 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI20 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI21..22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_exti_irq_enable(void);
+ void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_ISR_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_lld.c
new file mode 100644
index 0000000000..e2f4832e4a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_lld.c
@@ -0,0 +1,337 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/hal_lld.c
+ * @brief STM32L4xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32f7xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ * @note WARNING! Changing RTC clock source impossible without resetting
+ * of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
+ /* Backup domain reset.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+ }
+
+#if STM32_LSE_ENABLED
+ /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Wait until LSE is stable. */
+#endif
+
+#if STM32_MSIPLL_ENABLED
+ /* MSI PLL activation depends on LSE. Reactivating and checking for
+ MSI stability.*/
+ RCC->CR |= RCC_CR_MSIPLLEN;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ; /* Wait until MSI is stable. */
+#endif
+
+#if HAL_USE_RTC
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->BDCR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->BDCR |= RCC_BDCR_RTCEN;
+ }
+#endif /* HAL_USE_RTC */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Reset of all peripherals.*/
+ rccResetAHB1(~0);
+ rccResetAHB2(~0);
+ rccResetAHB3(~0);
+ rccResetAPB1R1(~RCC_APB1RSTR1_PWRRST);
+ rccResetAPB1R2(~0);
+ rccResetAPB2(~0);
+
+ /* PWR clock enabled.*/
+ rccEnablePWRInterface(FALSE);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+ /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+ PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#else
+ PWR->CR2 = 0;
+#endif /* STM32_PVD_ENABLE */
+
+ /* Enabling independent VDDUSB.*/
+#if HAL_USE_USB
+ PWR->CR2 |= PWR_CR2_USV;
+#endif /* HAL_USE_USB */
+
+ /* Enabling independent VDDIO2 required by GPIOG.*/
+#if STM32_HAS_GPIOG
+ PWR->CR2 |= PWR_CR2_IOSV;
+#endif /* STM32_HAS_GPIOG */
+}
+
+/**
+ * @brief STM32L4xx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+ /* PWR clock enable.*/
+#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
+ RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
+#else
+ RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
+#endif
+
+ /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
+ always enabled because it is the fall back clock when PLL the fails.
+ Trim fields are not altered from reset values.*/
+
+ /* MSIRANGE can be set only when MSI is OFF or READY.*/
+ RCC->CR = RCC_CR_MSION;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ; /* Wait until MSI is stable. */
+
+ /* Clocking from MSI, in case MSI was not the default source.*/
+ RCC->CFGR = 0;
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
+ ; /* Wait until MSI is selected. */
+
+ /* Core voltage setup.*/
+ PWR->CR1 = STM32_VOS;
+ while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
+ ; /* stable. */
+
+#if STM32_HSI16_ENABLED
+ /* HSI activation.*/
+ RCC->CR |= RCC_CR_HSION;
+ while ((RCC->CR & RCC_CR_HSIRDY) == 0)
+ ; /* Wait until HSI is stable. */
+#endif
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#endif
+ /* HSE activation.*/
+ RCC->CR |= RCC_CR_HSEON;
+ while ((RCC->CR & RCC_CR_HSERDY) == 0)
+ ; /* Wait until HSE is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Wait until LSI is stable. */
+#endif
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR1 |= PWR_CR1_DBP;
+
+#if STM32_LSE_ENABLED
+ /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Wait until LSE is stable. */
+#endif
+
+ /* Flash setup for selected MSI speed setting.*/
+ FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
+ STM32_MSI_FLASHBITS;
+
+ /* Changing MSIRANGE to configured value.*/
+ RCC->CR |= STM32_MSIRANGE;
+
+ /* Switching from MSISRANGE to MSIRANGE.*/
+ RCC->CR |= RCC_CR_MSIRGSEL;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ;
+
+ /* MSI is configured SYSCLK source so wait for it to be stable as well.*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
+ ;
+
+#if STM32_MSIPLL_ENABLED
+ /* MSI PLL (to LSE) activation */
+ RCC->CR |= RCC_CR_MSIPLLEN;
+#endif
+
+ /* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high.
+ This range is used exiting the Standby mode until MSIRGSEL is set.*/
+ RCC->CSR |= STM32_MSISRANGE;
+
+#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
+ /* PLLM and PLLSRC are common to all PLLs.*/
+ RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
+ STM32_PLLQ | STM32_PLLQEN |
+ STM32_PLLP | STM32_PLLPEN |
+ STM32_PLLN | STM32_PLLM |
+ STM32_PLLSRC;
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Waiting for PLL lock.*/
+ while ((RCC->CR & RCC_CR_PLLRDY) == 0)
+ ;
+#endif
+
+#if STM32_ACTIVATE_PLLSAI1
+ /* PLLSAI1 activation.*/
+ RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
+ STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
+ STM32_PLLSAI1P | STM32_PLLSAI1PEN |
+ STM32_PLLSAI1N;
+ RCC->CR |= RCC_CR_PLLSAI1ON;
+
+ /* Waiting for PLL lock.*/
+ while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0)
+ ;
+#endif
+
+#if STM32_ACTIVATE_PLLSAI2
+ /* PLLSAI2 activation.*/
+ RCC->PLLSAI2CFGR = STM32_PLLSAI2R | STM32_PLLSAI2REN |
+ STM32_PLLSAI2P | STM32_PLLSAI2PEN |
+ STM32_PLLSAI2N;
+ RCC->CR |= RCC_CR_PLLSAI2ON;
+
+ /* Waiting for PLL lock.*/
+ while ((RCC->CR & RCC_CR_PLLSAI2RDY) == 0)
+ ;
+#endif
+
+ /* Other clock-related settings (dividers, MCO etc).*/
+ RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
+ STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+ /* CCIPR register initialization, note, must take care of the _OFF
+ pseudo settings.*/
+ {
+ uint32_t ccipr = STM32_DFSDMSEL | STM32_SWPMI1SEL | STM32_ADCSEL |
+ STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
+ STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
+ STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
+ STM32_USART2SEL | STM32_USART1SEL | STM32_LPUART1SEL;
+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+ ccipr |= STM32_SAI2SEL;
+#endif
+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+ ccipr |= STM32_SAI1SEL;
+#endif
+ RCC->CCIPR = ccipr;
+ }
+
+ /* Set flash WS's for SYSCLK source */
+ if (STM32_FLASHBITS > STM32_MSI_FLASHBITS)
+ FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
+
+ /* Switching to the configured SYSCLK source if it is different from MSI.*/
+#if (STM32_SW != STM32_SW_MSI)
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
+ /* Wait until SYSCLK is stable.*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+#endif
+
+ /* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
+ if (STM32_FLASHBITS < STM32_MSI_FLASHBITS)
+ FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
+
+#endif /* STM32_NO_INIT */
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_lld.h
new file mode 100644
index 0000000000..ffbca3b186
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/hal_lld.h
@@ -0,0 +1,2105 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/hal_lld.h
+ * @brief STM32L4xx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_LSEDRV.
+ * - STM32_LSE_BYPASS (optionally).
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32L471xx, STM32L475xx, STM32L476xx.
+ * - STM32L485xx, STM32L486xx.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#if defined(STM32L432xx) || defined(STM32L471xx) || \
+ defined(STM32L475xx) || defined(STM32L476xx) || \
+ defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32L4xx Ultra Low Power"
+
+#elif defined(STM32L485xx) || defined(STM32L486xx)
+#define PLATFORM_NAME "STM32L4xx Ultra Low Power with Crypto"
+
+#else
+#error "STM32L4xx device not specified"
+#endif
+
+/**
+ * @brief Sub-family identifier.
+ */
+#if !defined(STM32L4XX) || defined(__DOXYGEN__)
+#define STM32L4XX
+#endif
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSI16CLK 16000000 /**< High speed internal clock. */
+#define STM32_LSICLK 32000 /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name PWR_CR1 register bits definitions
+ * @{
+ */
+#define STM32_VOS_MASK (3 << 9) /**< Core voltage mask. */
+#define STM32_VOS_RANGE1 (1 << 9) /**< Core voltage 1.2 Volts. */
+#define STM32_VOS_RANGE2 (2 << 9) /**< Core voltage 1.0 Volts. */
+/** @} */
+
+/**
+ * @name PWR_CR2 register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK (7 << 1) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 1) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 1) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2 << 1) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3 << 1) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4 << 1) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5 << 1) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6 << 1) /**< PVD level 6. */
+#define STM32_PLS_EXT (7 << 1) /**< PVD level 7. */
+/** @} */
+
+/**
+ * @name RCC_CR register bits definitions
+ * @{
+ */
+#define STM32_MSIRANGE_MASK (15 << 4) /**< MSIRANGE field mask. */
+#define STM32_MSIRANGE_100K (0 << 4) /**< 100kHz nominal. */
+#define STM32_MSIRANGE_200K (1 << 4) /**< 200kHz nominal. */
+#define STM32_MSIRANGE_400K (2 << 4) /**< 400kHz nominal. */
+#define STM32_MSIRANGE_800K (3 << 4) /**< 800kHz nominal. */
+#define STM32_MSIRANGE_1M (4 << 4) /**< 1MHz nominal. */
+#define STM32_MSIRANGE_2M (5 << 4) /**< 2MHz nominal. */
+#define STM32_MSIRANGE_4M (6 << 4) /**< 4MHz nominal. */
+#define STM32_MSIRANGE_8M (7 << 4) /**< 8MHz nominal. */
+#define STM32_MSIRANGE_16M (8 << 4) /**< 16MHz nominal. */
+#define STM32_MSIRANGE_24M (9 << 4) /**< 24MHz nominal. */
+#define STM32_MSIRANGE_32M (10 << 4) /**< 32MHz nominal. */
+#define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MASK (3 << 0) /**< SW field mask. */
+#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
+#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI. */
+#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */
+#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE1_MASK (7 << 8) /**< PPRE1 field mask. */
+#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
+#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
+#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
+#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
+#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
+
+#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */
+#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
+#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
+#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
+#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
+#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
+
+#define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */
+#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */
+#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */
+
+#define STM32_MCOSEL_MASK (7 << 24) /**< MCOSEL field mask. */
+#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */
+#define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */
+#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
+#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
+#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
+
+#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */
+#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
+#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
+#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
+#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
+/** @} */
+
+/**
+ * @name RCC_PLLCFGR register bits definitions
+ * @{
+ */
+#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
+#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
+#define STM32_PLLSRC_MSI (1 << 0) /**< PLL clock source is MSI. */
+#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
+#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
+/** @} */
+
+/**
+ * @name RCC_CCIPR register bits definitions
+ * @{
+ */
+#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */
+#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */
+#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */
+#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 source is HSI16. */
+#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */
+
+#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 mask. */
+#define STM32_USART2SEL_PCLK1 (0 << 2) /**< USART2 source is PCLK1. */
+#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 source is SYSCLK. */
+#define STM32_USART2SEL_HSI16 (2 << 2) /**< USART2 source is HSI16. */
+#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */
+
+#define STM32_USART3SEL_MASK (3 << 4) /**< USART3 mask. */
+#define STM32_USART3SEL_PCLK1 (0 << 4) /**< USART3 source is PCLK1. */
+#define STM32_USART3SEL_SYSCLK (1 << 4) /**< USART3 source is SYSCLK. */
+#define STM32_USART3SEL_HSI16 (2 << 4) /**< USART3 source is HSI16. */
+#define STM32_USART3SEL_LSE (3 << 4) /**< USART3 source is LSE. */
+
+#define STM32_UART4SEL_MASK (3 << 6) /**< UART4 mask. */
+#define STM32_UART4SEL_PCLK1 (0 << 6) /**< UART4 source is PCLK1. */
+#define STM32_UART4SEL_SYSCLK (1 << 6) /**< UART4 source is SYSCLK. */
+#define STM32_UART4SEL_HSI16 (2 << 6) /**< UART4 source is HSI16. */
+#define STM32_UART4SEL_LSE (3 << 6) /**< UART4 source is LSE. */
+
+#define STM32_UART5SEL_MASK (3 << 8) /**< UART5 mask. */
+#define STM32_UART5SEL_PCLK1 (0 << 8) /**< UART5 source is PCLK1. */
+#define STM32_UART5SEL_SYSCLK (1 << 8) /**< UART5 source is SYSCLK. */
+#define STM32_UART5SEL_HSI16 (2 << 8) /**< UART5 source is HSI16. */
+#define STM32_UART5SEL_LSE (3 << 8) /**< UART5 source is LSE. */
+
+#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 mask. */
+#define STM32_LPUART1SEL_PCLK1 (0 << 10) /**< LPUART1 source is PCLK1. */
+#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 source is SYSCLK. */
+#define STM32_LPUART1SEL_HSI16 (2 << 10) /**< LPUART1 source is HSI16. */
+#define STM32_LPUART1SEL_LSE (3 << 10) /**< LPUART1 source is LSE. */
+
+#define STM32_I2C1SEL_MASK (3 << 12) /**< I2C1SEL mask. */
+#define STM32_I2C1SEL_PCLK1 (0 << 12) /**< I2C1 source is PCLK1. */
+#define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 source is SYSCLK. */
+#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 source is HSI16. */
+
+#define STM32_I2C2SEL_MASK (3 << 14) /**< I2C2SEL mask. */
+#define STM32_I2C2SEL_PCLK1 (0 << 14) /**< I2C2 source is PCLK1. */
+#define STM32_I2C2SEL_SYSCLK (1 << 14) /**< I2C2 source is SYSCLK. */
+#define STM32_I2C2SEL_HSI16 (2 << 14) /**< I2C2 source is HSI16. */
+
+#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3SEL mask. */
+#define STM32_I2C3SEL_PCLK1 (0 << 16) /**< I2C3 source is PCLK1. */
+#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 source is SYSCLK. */
+#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 source is HSI16. */
+
+#define STM32_LPTIM1SEL_MASK (3 << 18) /**< LPTIM1SEL mask. */
+#define STM32_LPTIM1SEL_PCLK1 (0 << 18) /**< LPTIM1 source is PCLK1. */
+#define STM32_LPTIM1SEL_LSI (1 << 18) /**< LPTIM1 source is LSI. */
+#define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 source is HSI16. */
+#define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 source is LSE. */
+
+#define STM32_LPTIM2SEL_MASK (3 << 20) /**< LPTIM2SEL mask. */
+#define STM32_LPTIM2SEL_PCLK1 (0 << 20) /**< LPTIM2 source is PCLK1. */
+#define STM32_LPTIM2SEL_LSI (1 << 20) /**< LPTIM2 source is LSI. */
+#define STM32_LPTIM2SEL_HSI16 (2 << 20) /**< LPTIM2 source is HSI16. */
+#define STM32_LPTIM2SEL_LSE (3 << 20) /**< LPTIM2 source is LSE. */
+
+#define STM32_SAI1SEL_MASK (3 << 22) /**< SAI1SEL mask. */
+#define STM32_SAI1SEL_PLLSAI1 (0 << 22) /**< SAI1 source is PLLSAI1-P. */
+#define STM32_SAI1SEL_PLLSAI2 (1 << 22) /**< SAI1 source is PLLSAI2-P. */
+#define STM32_SAI1SEL_PLL (2 << 22) /**< SAI1 source is PLL-P. */
+#define STM32_SAI1SEL_EXTCLK (3 << 22) /**< SAI1 source is external. */
+#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
+
+#define STM32_SAI2SEL_MASK (3 << 24) /**< SAI2SEL mask. */
+#define STM32_SAI2SEL_PLLSAI1 (0 << 24) /**< SAI2 source is PLLSAI1-P. */
+#define STM32_SAI2SEL_PLLSAI2 (1 << 24) /**< SAI2 source is PLLSAI2-P. */
+#define STM32_SAI2SEL_PLL (2 << 24) /**< SAI2 source is PLL-P. */
+#define STM32_SAI2SEL_EXTCLK (3 << 24) /**< SAI2 source is external. */
+#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
+
+#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */
+#define STM32_CLK48SEL_NOCLK (0 << 26) /**< CLK48 disabled. */
+#define STM32_CLK48SEL_PLLSAI1 (1 << 26) /**< CLK48 source is PLLSAI1-Q. */
+#define STM32_CLK48SEL_PLL (2 << 26) /**< CLK48 source is PLL-Q. */
+#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */
+
+#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */
+#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */
+#define STM32_ADCSEL_PLLSAI1 (1 << 28) /**< ADC source is PLLSAI1-R. */
+#define STM32_ADCSEL_PLLSAI2 (2 << 28) /**< ADC source is PLLSAI2-R. */
+#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */
+
+#define STM32_SWPMI1SEL_MASK (1 << 30) /**< SWPMI1SEL mask. */
+#define STM32_SWPMI1SEL_PCLK1 (0 << 30) /**< SWPMI1 source is PCLK1. */
+#define STM32_SWPMI1SEL_HSI16 (1 << 30) /**< SWPMI1 source is HSI16. */
+
+#define STM32_DFSDMSEL_MASK (1 << 31) /**< DFSDMSEL mask. */
+#define STM32_DFSDMSEL_PCLK1 (0 << 31) /**< DFSDM source is PCLK1. */
+#define STM32_DFSDMSEL_SYSCLK (1 << 31) /**< DFSDM source is SYSCLK. */
+/** @} */
+
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
+#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
+#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
+#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
+#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
+
+#define STM32_LSCOSEL_MASK (3 << 24) /**< LSCO pin clock source. */
+#define STM32_LSCOSEL_NOCLOCK (0 << 24) /**< No clock on LSCO pin. */
+#define STM32_LSCOSEL_LSI (1 << 24) /**< LSI on LSCO pin. */
+#define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */
+/** @} */
+
+/**
+ * @name RCC_CSR register bits definitions
+ * @{
+ */
+#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */
+#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */
+#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */
+#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */
+#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Core voltage selection.
+ * @note This setting affects all the performance and clock related
+ * settings, the maximum performance is only obtainable selecting
+ * the maximum voltage.
+ */
+#if !defined(STM32_VOS) || defined(__DOXYGEN__)
+#define STM32_VOS STM32_VOS_RANGE1
+#endif
+
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief Enables or disables the HSI16 clock source.
+ */
+#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI16_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the MSI PLL on LSE clock source.
+ */
+#if !defined(STM32_MSIPLL_ENABLED) || defined(__DOXYGEN__)
+#define STM32_MSIPLL_ENABLED FALSE
+#endif
+
+/**
+ * @brief ADC clock setting.
+ */
+#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_ADC_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief SAI1 clock setting.
+ */
+#if !defined(STM32_SAI1_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_SAI1_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief SAI2 clock setting.
+ */
+#if !defined(STM32_SAI2_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_SAI2_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief MSI frequency setting.
+ */
+#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
+#define STM32_MSIRANGE STM32_MSIRANGE_4M
+#endif
+
+/**
+ * @brief MSI frequency setting after standby.
+ */
+#if !defined(STM32_MSISRANGE) || defined(__DOXYGEN__)
+#define STM32_MSISRANGE STM32_MSISRANGE_4M
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_MSI
+#endif
+
+/**
+ * @brief PLLM divider value.
+ * @note The allowed values are 1..8.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLM_VALUE 1
+#endif
+
+/**
+ * @brief PLLN multiplier value.
+ * @note The allowed values are 8..86.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLN_VALUE 80
+#endif
+
+/**
+ * @brief PLLP divider value.
+ * @note The allowed values are 7, 17.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLP_VALUE 7
+#endif
+
+/**
+ * @brief PLLQ divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLQ_VALUE 6
+#endif
+
+/**
+ * @brief PLLR divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLR_VALUE 4
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#endif
+
+/**
+ * @brief STOPWUCK clock setting.
+ */
+#if !defined(STM32_STOPWUCK) || defined(__DOXYGEN__)
+#define STM32_STOPWUCK STM32_STOPWUCK_MSI
+#endif
+
+/**
+ * @brief MCO clock source.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief LSCO clock source.
+ */
+#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief PLLSAI1N multiplier value.
+ * @note The allowed values are 8..86.
+ */
+#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1N_VALUE 80
+#endif
+
+/**
+ * @brief PLLSAI1P divider value.
+ * @note The allowed values are 7, 17.
+ */
+#if !defined(STM32_PLLSAI1P_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1P_VALUE 7
+#endif
+
+/**
+ * @brief PLLSAI1Q divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ */
+#if !defined(STM32_PLLSAI1Q_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1Q_VALUE 6
+#endif
+
+/**
+ * @brief PLLSAI1R divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ */
+#if !defined(STM32_PLLSAI1R_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1R_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAI2N multiplier value.
+ * @note The allowed values are 8..86.
+ */
+#if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2N_VALUE 80
+#endif
+
+/**
+ * @brief PLLSAI2P divider value.
+ * @note The allowed values are 7, 17.
+ */
+#if !defined(STM32_PLLSAI2P_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2P_VALUE 7
+#endif
+
+/**
+ * @brief PLLSAI2R divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ */
+#if !defined(STM32_PLLSAI2R_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2R_VALUE 4
+#endif
+
+/**
+ * @brief USART1 clock source.
+ */
+#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
+#endif
+
+/**
+ * @brief USART2 clock source.
+ */
+#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
+#endif
+
+/**
+ * @brief USART3 clock source.
+ */
+#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
+#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
+#endif
+
+/**
+ * @brief UART4 clock source.
+ */
+#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
+#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
+#endif
+
+/**
+ * @brief UART5 clock source.
+ */
+#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
+#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
+#endif
+
+/**
+ * @brief LPUART1 clock source.
+ */
+#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
+#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2C2 clock source.
+ */
+#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
+#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2C3 clock source.
+ */
+#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
+#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
+#endif
+
+/**
+ * @brief LPTIM1 clock source.
+ */
+#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
+#endif
+
+/**
+ * @brief LPTIM2 clock source.
+ */
+#if !defined(STM32_LPTIM2SEL) || defined(__DOXYGEN__)
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
+#endif
+
+/**
+ * @brief SAI1SEL value (SAI1 clock source).
+ */
+#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF
+#endif
+
+/**
+ * @brief SAI2SEL value (SAI2 clock source).
+ */
+#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
+#define STM32_SAI2SEL STM32_SAI2SEL_OFF
+#endif
+
+/**
+ * @brief CLK48SEL value (48MHz clock source).
+ */
+#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__)
+#define STM32_CLK48SEL STM32_CLK48SEL_PLL
+#endif
+
+/**
+ * @brief ADCSEL value (ADCs clock source).
+ */
+#if !defined(STM32_ADCSEL) || defined(__DOXYGEN__)
+#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
+#endif
+
+/**
+ * @brief SWPMI1SEL value (SWPMI clock source).
+ */
+#if !defined(STM32_SWPMI1SEL) || defined(__DOXYGEN__)
+#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
+#endif
+
+/**
+ * @brief DFSDMSEL value (DFSDM clock source).
+ */
+#if !defined(STM32_DFSDMSEL) || defined(__DOXYGEN__)
+#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
+#endif
+
+/**
+ * @brief RTC/LCD clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32L4xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L4xx_MCUCONF not defined"
+#endif
+
+/*
+ * Board files sanity checks.
+ */
+#if !defined(STM32_LSECLK)
+#error "STM32_LSECLK not defined in board.h"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined in board.h"
+#endif
+
+#if !defined(STM32_HSECLK)
+#error "STM32_HSECLK not defined in board.h"
+#endif
+
+/* Voltage related limits.*/
+#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__)
+/**
+ * @name System Limits
+ * @{
+ */
+/**
+ * @brief Maximum SYSCLK clock frequency at current voltage setting.
+ */
+#define STM32_SYSCLK_MAX 80000000
+
+/**
+ * @brief Maximum HSE clock frequency at current voltage setting.
+ */
+#define STM32_HSECLK_MAX 48000000
+
+/**
+ * @brief Maximum HSE clock frequency using an external source.
+ */
+#define STM32_HSECLK_BYP_MAX 48000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN 4000000
+
+/**
+ * @brief Minimum HSE clock frequency using an external source.
+ */
+#define STM32_HSECLK_BYP_MIN 8000000
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX 32768
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_BYP_MAX 1000000
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN 32768
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_BYP_MIN 32768
+
+/**
+ * @brief Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX 16000000
+
+/**
+ * @brief Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN 4000000
+
+/**
+ * @brief Maximum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MAX 344000000
+
+/**
+ * @brief Minimum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MIN 64000000
+
+/**
+ * @brief Maximum PLL-P output clock frequency.
+ */
+#define STM32_PLLP_MAX 80000000
+
+/**
+ * @brief Minimum PLL-P output clock frequency.
+ */
+#define STM32_PLLP_MIN 2064500
+
+/**
+ * @brief Maximum PLL-Q output clock frequency.
+ */
+#define STM32_PLLQ_MAX 80000000
+
+/**
+ * @brief Minimum PLL-Q output clock frequency.
+ */
+#define STM32_PLLQ_MIN 8000000
+
+/**
+ * @brief Maximum PLL-R output clock frequency.
+ */
+#define STM32_PLLR_MAX 80000000
+
+/**
+ * @brief Minimum PLL-R output clock frequency.
+ */
+#define STM32_PLLR_MIN 8000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX 80000000
+
+/**
+ * @brief Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX 80000000
+
+/**
+ * @brief Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX 80000000
+/** @} */
+
+/**
+ * @name Flash Wait states
+ * @{
+ */
+#define STM32_0WS_THRESHOLD 16000000
+#define STM32_1WS_THRESHOLD 32000000
+#define STM32_2WS_THRESHOLD 48000000
+#define STM32_3WS_THRESHOLD 64000000
+/** @} */
+
+#elif STM32_VOS == STM32_VOS_RANGE2
+#define STM32_SYSCLK_MAX 26000000
+#define STM32_HSECLK_MAX 48000000
+#define STM32_HSECLK_BYP_MAX 26000000
+#define STM32_HSECLK_MIN 4000000
+#define STM32_HSECLK_BYP_MIN 8000000
+#define STM32_LSECLK_MAX 32768
+#define STM32_LSECLK_BYP_MAX 1000000
+#define STM32_LSECLK_MIN 32768
+#define STM32_LSECLK_BYP_MIN 32768
+#define STM32_PLLIN_MAX 16000000
+#define STM32_PLLIN_MIN 4000000
+#define STM32_PLLVCO_MAX 128000000
+#define STM32_PLLVCO_MIN 64000000
+#define STM32_PLLP_MAX 26000000
+#define STM32_PLLP_MIN 2064500
+#define STM32_PLLQ_MAX 26000000
+#define STM32_PLLQ_MIN 8000000
+#define STM32_PLLR_MAX 26000000
+#define STM32_PLLR_MIN 8000000
+#define STM32_PCLK1_MAX 26000000
+#define STM32_PCLK2_MAX 26000000
+#define STM32_ADCCLK_MAX 26000000
+
+#define STM32_0WS_THRESHOLD 6000000
+#define STM32_1WS_THRESHOLD 12000000
+#define STM32_2WS_THRESHOLD 18000000
+#define STM32_3WS_THRESHOLD 26000000
+
+#else
+#error "invalid STM32_VOS value specified"
+#endif
+
+/**
+ * @brief MSI frequency.
+ */
+#if STM32_MSIRANGE == STM32_MSIRANGE_100K
+#define STM32_MSICLK 100000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_200K
+#define STM32_MSICLK 200000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_400K
+#define STM32_MSICLK 400000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_800K
+#define STM32_MSICLK 800000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
+#define STM32_MSICLK 1000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
+#define STM32_MSICLK 2000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
+#define STM32_MSICLK 4000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_8M
+#define STM32_MSICLK 8000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_16M
+#define STM32_MSICLK 16000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_24M
+#define STM32_MSICLK 24000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_32M
+#define STM32_MSICLK 32000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_48M
+#define STM32_MSICLK 48000000
+#else
+#error "invalid STM32_MSIRANGE value specified"
+#endif
+
+/**
+ * @brief MSIS frequency.
+ */
+#if STM32_MSISRANGE == STM32_MSISRANGE_1M
+#define STM32_MSISCLK 1000000
+#elif STM32_MSISRANGE == STM32_MSISRANGE_2M
+#define STM32_MSISCLK 2000000
+#elif STM32_MSISRANGE == STM32_MSISRANGE_4M
+#define STM32_MSISCLK 4000000
+#elif STM32_MSISRANGE == STM32_MSISRANGE_8M
+#define STM32_MSISCLK 8000000
+#else
+#error "invalid STM32_MSISRANGE value specified"
+#endif
+
+/*
+ * HSI16 related checks.
+ */
+#if STM32_HSI16_ENABLED
+#else /* !STM32_HSI16_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI16
+#error "HSI16 not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
+#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI16))
+#error "HSI16 not enabled, required by STM32_MCOSEL"
+#endif
+
+#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI16)
+#error "HSI16 not enabled, required by STM32_SAI1SEL"
+#endif
+
+#if ((STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI1) || \
+ (STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI16)
+#error "HSI16 not enabled, required by STM32_SAI2SEL"
+#endif
+
+#endif /* !STM32_HSI16_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+ #if STM32_HSECLK == 0
+ #error "HSE frequency not defined"
+ #else /* STM32_HSECLK != 0 */
+ #if defined(STM32_HSE_BYPASS)
+ #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
+ #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
+ #endif
+ #else /* !defined(STM32_HSE_BYPASS) */
+ #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+ #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+ #endif
+ #endif /* !defined(STM32_HSE_BYPASS) */
+ #endif /* STM32_HSECLK != 0 */
+
+ #else /* !STM32_HSE_ENABLED */
+
+ #if STM32_SW == STM32_SW_HSE
+ #error "HSE not enabled, required by STM32_SW"
+ #endif
+
+ #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+ #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+ #endif
+
+ #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
+ #error "HSE not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) | \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+ #error "HSE not enabled, required by STM32_SAI1SEL"
+ #endif
+
+ #if ((STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI1) | \
+ (STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+ #error "HSE not enabled, required by STM32_SAI2SEL"
+ #endif
+
+ #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+ #error "HSE not enabled, required by STM32_RTCSEL"
+ #endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+ #if STM32_RTCSEL == STM32_RTCSEL_LSI
+ #error "LSI not enabled, required by STM32_RTCSEL"
+ #endif
+
+ #if STM32_MCOSEL == STM32_MCOSEL_LSI
+ #error "LSI not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if STM32_LSCOSEL == STM32_LSCOSEL_LSI
+ #error "LSI not enabled, required by STM32_LSCOSEL"
+ #endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+ #if (STM32_LSECLK == 0)
+ #error "LSE frequency not defined"
+ #endif
+
+ #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+ #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+ #endif
+
+#else /* !STM32_LSE_ENABLED */
+
+ #if STM32_RTCSEL == STM32_RTCSEL_LSE
+ #error "LSE not enabled, required by STM32_RTCSEL"
+ #endif
+
+ #if STM32_MCOSEL == STM32_MCOSEL_LSE
+ #error "LSE not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if STM32_LSCOSEL == STM32_LSCOSEL_LSE
+ #error "LSE not enabled, required by STM32_LSCOSEL"
+ #endif
+
+ #if STM32_MSIPLL_ENABLED == TRUE
+ #error "LSE not enabled, required by STM32_MSIPLL_ENABLED"
+ #endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/*
+ * MSI related checks.
+ */
+#if (STM32_MSIRANGE == STM32_MSIRANGE_48M) && !STM32_MSIPLL_ENABLED
+#warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED"
+#endif
+
+/**
+ * @brief STM32_PLLM field.
+ */
+#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 8)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
+#else
+#error "invalid STM32_PLLM_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLs input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_MSI
+#define STM32_PLLCLKIN (STM32_MSICLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
+#define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
+#define STM32_PLLCLKIN 0
+
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/*
+ * PLLs input frequency range check.
+ */
+#if (STM32_PLLCLKIN != 0) && \
+ ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/*
+ * PLL enable check.
+ */
+#if (STM32_CLK48SEL == STM32_CLK48SEL_PLL) || \
+ (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \
+ defined(__DOXYGEN__)
+
+#if STM32_PLLCLKIN == 0
+#error "PLL activation required but no PLL clock selected"
+#endif
+
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/**
+ * @brief STM32_PLLN field.
+ */
+#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 86)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLN (STM32_PLLN_VALUE << 8)
+#else
+#error "invalid STM32_PLLN_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLP field.
+ */
+#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
+#define STM32_PLLP (0 << 17)
+
+#elif STM32_PLLP_VALUE == 17
+#define STM32_PLLP (1 << 17)
+
+#else
+#error "invalid STM32_PLLP_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLQ field.
+ */
+#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLQ (0 << 21)
+
+#elif STM32_PLLQ_VALUE == 4
+#define STM32_PLLQ (1 << 21)
+
+#elif STM32_PLLQ_VALUE == 6
+#define STM32_PLLQ (2 << 21)
+
+#elif STM32_PLLQ_VALUE == 8
+#define STM32_PLLQ (3 << 21)
+
+#else
+#error "invalid STM32_PLLQ_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLR field.
+ */
+#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLR (0 << 25)
+
+#elif STM32_PLLR_VALUE == 4
+#define STM32_PLLR (1 << 25)
+
+#elif STM32_PLLR_VALUE == 6
+#define STM32_PLLR (2 << 25)
+
+#elif STM32_PLLR_VALUE == 8
+#define STM32_PLLR (3 << 25)
+
+#else
+#error "invalid STM32_PLLR_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLPEN field.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLPEN (1 << 16)
+#else
+#define STM32_PLLPEN (0 << 16)
+#endif
+
+/**
+ * @brief STM32_PLLQEN field.
+ */
+#if (STM32_CLK48SEL == STM32_CLK48SEL_PLL) || defined(__DOXYGEN__)
+#define STM32_PLLQEN (1 << 20)
+#else
+#define STM32_PLLQEN (0 << 20)
+#endif
+
+/**
+ * @brief STM32_PLLREN field.
+ */
+#if (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLREN (1 << 24)
+#else
+#define STM32_PLLREN (0 << 24)
+#endif
+
+/**
+ * @brief PLL VCO frequency.
+ */
+#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
+
+/*
+ * PLL VCO frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLL P output clock frequency.
+ */
+#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
+
+/**
+ * @brief PLL Q output clock frequency.
+ */
+#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
+
+/**
+ * @brief PLL R output clock frequency.
+ */
+#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
+
+/*
+ * PLL-P output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
+#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
+#endif
+
+/*
+ * PLL-Q output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
+#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
+#endif
+
+/*
+ * PLL-R output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
+#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+#define STM32_SYSCLK STM32_MSICLK
+
+#elif (STM32_SW == STM32_SW_MSI)
+#define STM32_SYSCLK STM32_MSICLK
+
+#elif (STM32_SW == STM32_SW_HSI16)
+#define STM32_SYSCLK STM32_HSI16CLK
+
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+
+#elif (STM32_SW == STM32_SW_PLL)
+#define STM32_SYSCLK STM32_PLL_R_CLKOUT
+
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/*
+ * AHB frequency check.
+ */
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1 (STM32_HCLK / 1)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1 (STM32_HCLK / 2)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1 (STM32_HCLK / 4)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1 (STM32_HCLK / 8)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1 (STM32_HCLK / 16)
+
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/*
+ * APB1 frequency check.
+ */
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2 (STM32_HCLK / 1)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2 (STM32_HCLK / 2)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2 (STM32_HCLK / 4)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2 (STM32_HCLK / 8)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2 (STM32_HCLK / 16)
+
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/*
+ * APB2 frequency check.
+ */
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/*
+ * PLLSAI1 enable check.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
+ (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \
+ (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
+ defined(__DOXYGEN__)
+
+#if STM32_PLLCLKIN == 0
+#error "PLLSAI1 activation required but no PLL clock selected"
+#endif
+
+/**
+ * @brief PLLSAI1 activation flag.
+ */
+#define STM32_ACTIVATE_PLLSAI1 TRUE
+#else
+#define STM32_ACTIVATE_PLLSAI1 FALSE
+#endif
+
+/**
+ * @brief STM32_PLLSAI1N field.
+ */
+#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 86)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << 8)
+#else
+#error "invalid STM32_PLLSAI1N_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI1P field.
+ */
+#if (STM32_PLLSAI1P_VALUE == 7) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1P (0 << 17)
+
+#elif STM32_PLLSAI1P_VALUE == 17
+#define STM32_PLLSAI1P (1 << 17)
+
+#else
+#error "invalid STM32_PLLSAI1P_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI1Q field.
+ */
+#if (STM32_PLLSAI1Q_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1Q (0 << 21)
+
+#elif STM32_PLLSAI1Q_VALUE == 4
+#define STM32_PLLSAI1Q (1 << 21)
+
+#elif STM32_PLLSAI1Q_VALUE == 6
+#define STM32_PLLSAI1Q (2 << 21)
+
+#elif STM32_PLLSAI1Q_VALUE == 8
+#define STM32_PLLSAI1Q (3 << 21)
+
+#else
+#error "invalid STM32_PLLSAI1Q_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI1R field.
+ */
+#if (STM32_PLLSAI1R_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1R (0 << 25)
+
+#elif STM32_PLLSAI1R_VALUE == 4
+#define STM32_PLLSAI1R (1 << 25)
+
+#elif STM32_PLLSAI1R_VALUE == 6
+#define STM32_PLLSAI1R (2 << 25)
+
+#elif STM32_PLLSAI1R_VALUE == 8
+#define STM32_PLLSAI1R (3 << 25)
+
+#else
+#error "invalid STM32_PLLSAI1R_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI1PEN field.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI1PEN (1 << 16)
+#else
+#define STM32_PLLSAI1PEN (0 << 16)
+#endif
+
+/**
+ * @brief STM32_PLLSAI1QEN field.
+ */
+#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1QEN (1 << 20)
+#else
+#define STM32_PLLSAI1QEN (0 << 20)
+#endif
+
+/**
+ * @brief STM32_PLLSAI1REN field.
+ */
+#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1REN (1 << 24)
+#else
+#define STM32_PLLSAI1REN (0 << 24)
+#endif
+
+/**
+ * @brief PLLSAI1 VCO frequency.
+ */
+#define STM32_PLLSAI1VCO (STM32_PLLCLKIN * STM32_PLLSAI1N_VALUE)
+
+/*
+ * PLLSAI1 VCO frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI1 && \
+ ((STM32_PLLSAI1VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI1VCO > STM32_PLLVCO_MAX))
+#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLLSAI1-P output clock frequency.
+ */
+#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
+
+/**
+ * @brief PLLSAI1-Q output clock frequency.
+ */
+#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
+
+/**
+ * @brief PLLSAI1-R output clock frequency.
+ */
+#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE)
+
+/*
+ * PLLSAI1-P output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI1 && \
+ ((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX))
+#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
+#endif
+
+/*
+ * PLLSAI1-Q output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI1 && \
+ ((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX))
+#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
+#endif
+
+/*
+ * PLLSAI1-R output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI1 && \
+ ((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX))
+#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
+#endif
+
+/*
+ * PLLSAI2 enable check.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
+ (STM32_ADCSEL == STM32_ADCSEL_PLLSAI2) || \
+ defined(__DOXYGEN__)
+
+#if STM32_PLLCLKIN == 0
+#error "PLLSAI2 activation required but no PLL clock selected"
+#endif
+
+/**
+ * @brief PLLSAI2 activation flag.
+ */
+#define STM32_ACTIVATE_PLLSAI2 TRUE
+#else
+#define STM32_ACTIVATE_PLLSAI2 FALSE
+#endif
+
+/**
+ * @brief STM32_PLLSAI2N field.
+ */
+#if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 86)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI2N (STM32_PLLSAI2N_VALUE << 8)
+#else
+#error "invalid STM32_PLLSAI2N_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI2P field.
+ */
+#if (STM32_PLLSAI2P_VALUE == 7) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2P (0 << 17)
+
+#elif STM32_PLLSAI2P_VALUE == 17
+#define STM32_PLLSAI2P (1 << 17)
+
+#else
+#error "invalid STM32_PLLSAI2P_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI2R field.
+ */
+#if (STM32_PLLSAI2R_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2R (0 << 25)
+
+#elif STM32_PLLSAI2R_VALUE == 4
+#define STM32_PLLSAI2R (1 << 25)
+
+#elif STM32_PLLSAI2R_VALUE == 6
+#define STM32_PLLSAI2R (2 << 25)
+
+#elif STM32_PLLSAI2R_VALUE == 8
+#define STM32_PLLSAI2R (3 << 25)
+
+#else
+#error "invalid STM32_PLLSAI2R_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI2PEN field.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI2PEN (1 << 16)
+#else
+#define STM32_PLLSAI2PEN (0 << 16)
+#endif
+
+/**
+ * @brief STM32_PLLSAI2REN field.
+ */
+#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI2) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2REN (1 << 24)
+#else
+#define STM32_PLLSAI2REN (0 << 24)
+#endif
+
+/**
+ * @brief PLLSAI2 VCO frequency.
+ */
+#define STM32_PLLSAI2VCO (STM32_PLLCLKIN * STM32_PLLSAI2N_VALUE)
+
+/*
+ * PLLSAI2 VCO frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI2 && \
+ ((STM32_PLLSAI2VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI2VCO > STM32_PLLVCO_MAX))
+#error "STM32_PLLSAI2VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLLSAI2-P output clock frequency.
+ */
+#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
+
+/**
+ * @brief PLLSAI2-R output clock frequency.
+ */
+#define STM32_PLLSAI2_R_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2R_VALUE)
+
+/*
+ * PLLSAI2-P output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI2 && \
+ ((STM32_PLLSAI2_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI2_P_CLKOUT > STM32_PLLP_MAX))
+#error "STM32_PLLSAI2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
+#endif
+
+/*
+ * PLLSAI2-R output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI2 && \
+ ((STM32_PLLSAI2_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI2_R_CLKOUT > STM32_PLLR_MAX))
+#error "STM32_PLLSAI2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
+#endif
+
+/**
+ * @brief MCO divider clock frequency.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_MCODIVCLK 0
+
+#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
+#define STM32_MCODIVCLK STM32_SYSCLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_MSI
+#define STM32_MCODIVCLK STM32_MSICLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
+#define STM32_MCODIVCLK STM32_HSI16CLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+#define STM32_MCODIVCLK STM32_HSECLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_PLL
+#define STM32_MCODIVCLK STM32_PLL_P_CLKOUT
+
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+#define STM32_MCODIVCLK STM32_LSICLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+#define STM32_MCODIVCLK STM32_LSECLK
+
+#else
+#error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief MCO output pin clock frequency.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCOCLK STM32_MCODIVCLK
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
+#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
+#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
+#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
+#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
+
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
+/**
+ * @brief RTC clock frequency.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK 0
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK STM32_LSECLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK (STM32_HSECLK / 32)
+
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief USART1 clock frequency.
+ */
+#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
+#define STM32_USART1CLK STM32_PCLK2
+#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
+#define STM32_USART1CLK STM32_SYSCLK
+#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
+#define STM32_USART1CLK STM32_HSI16CLK
+#elif STM32_USART1SEL == STM32_USART1SEL_LSE
+#define STM32_USART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief USART2 clock frequency.
+ */
+#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_USART2CLK STM32_PCLK1
+#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
+#define STM32_USART2CLK STM32_SYSCLK
+#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
+#define STM32_USART2CLK STM32_HSI16CLK
+#elif STM32_USART2SEL == STM32_USART2SEL_LSE
+#define STM32_USART2CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART2 clock"
+#endif
+
+/**
+ * @brief USART3 clock frequency.
+ */
+#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_USART3CLK STM32_PCLK1
+#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
+#define STM32_USART3CLK STM32_SYSCLK
+#elif STM32_USART3SEL == STM32_USART3SEL_HSI16
+#define STM32_USART3CLK STM32_HSI16CLK
+#elif STM32_USART3SEL == STM32_USART3SEL_LSE
+#define STM32_USART3CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART3 clock"
+#endif
+
+/**
+ * @brief UART4 clock frequency.
+ */
+#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_UART4CLK STM32_PCLK1
+#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
+#define STM32_UART4CLK STM32_SYSCLK
+#elif STM32_UART4SEL == STM32_UART4SEL_HSI16
+#define STM32_UART4CLK STM32_HSI16CLK
+#elif STM32_UART4SEL == STM32_UART4SEL_LSE
+#define STM32_UART4CLK STM32_LSECLK
+#else
+#error "invalid source selected for UART4 clock"
+#endif
+
+/**
+ * @brief UART5 clock frequency.
+ */
+#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_UART5CLK STM32_PCLK1
+#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
+#define STM32_UART5CLK STM32_SYSCLK
+#elif STM32_UART5SEL == STM32_UART5SEL_HSI16
+#define STM32_UART5CLK STM32_HSI16CLK
+#elif STM32_UART5SEL == STM32_UART5SEL_LSE
+#define STM32_UART5CLK STM32_LSECLK
+#else
+#error "invalid source selected for UART5 clock"
+#endif
+
+/**
+ * @brief LPUART1 clock frequency.
+ */
+#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_LPUART1CLK STM32_PCLK1
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
+#define STM32_LPUART1CLK STM32_SYSCLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
+#define STM32_LPUART1CLK STM32_HSI16CLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
+#define STM32_LPUART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPUART1 clock"
+#endif
+
+/**
+ * @brief I2C1 clock frequency.
+ */
+#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C1CLK STM32_PCLK1
+#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
+#define STM32_I2C1CLK STM32_SYSCLK
+#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
+#define STM32_I2C1CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief I2C2 clock frequency.
+ */
+#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C2CLK STM32_PCLK1
+#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
+#define STM32_I2C2CLK STM32_SYSCLK
+#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI16
+#define STM32_I2C2CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for I2C2 clock"
+#endif
+
+/**
+ * @brief I2C3 clock frequency.
+ */
+#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C3CLK STM32_PCLK1
+#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
+#define STM32_I2C3CLK STM32_SYSCLK
+#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16
+#define STM32_I2C3CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for I2C3 clock"
+#endif
+
+/**
+ * @brief LPTIM1 clock frequency.
+ */
+#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_LPTIM1CLK STM32_PCLK1
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
+#define STM32_LPTIM1CLK STM32_LSICLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
+#define STM32_LPTIM1CLK STM32_HSI16CLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
+#define STM32_LPTIM1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPTIM1 clock"
+#endif
+
+/**
+ * @brief LPTIM2 clock frequency.
+ */
+#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_LPTIM2CLK STM32_PCLK1
+#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
+#define STM32_LPTIM2CLK STM32_LSICLK
+#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16
+#define STM32_LPTIM2CLK STM32_HSI16CLK
+#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE
+#define STM32_LPTIM2CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPTIM2 clock"
+#endif
+
+/**
+ * @brief 48MHz clock frequency.
+ */
+#if (STM32_CLK48SEL == STM32_CLK48SEL_NOCLK) || defined(__DOXYGEN__)
+#define STM32_48CLK 0
+#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
+#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
+#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
+#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
+#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
+#define STM32_48CLK STM32_MSICLK
+#else
+#error "invalid source selected for 48CLK clock"
+#endif
+#define STM32_USBCLK STM32_48CLK
+
+/**
+ * @brief ADC clock frequency.
+ */
+#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__)
+#define STM32_ADCCLK 0
+#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1
+#define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT
+#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI2
+#define STM32_ADCCLK STM32_PLLSAI2_R_CLKOUT
+#elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK
+#define STM32_ADCCLK STM32_SYSCLK
+#else
+#error "invalid source selected for ADC clock"
+#endif
+
+/**
+ * @brief SWPMI1 clock frequency.
+ */
+#if (STM32_SWPMI1SEL == STM32_SWPMI1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_SWPMI1CLK STM32_PCLK1
+#elif STM32_SWPMI1SEL == STM32_SWPMI1SEL_HSI16
+#define STM32_SWPMI1CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for SWPMI1 clock"
+#endif
+
+/**
+ * @brief DFSDM clock frequency.
+ */
+#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_DFSDMCLK STM32_PCLK1
+#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
+#define STM32_DFSDMCLK STM32_SYSCLK
+#else
+#error "invalid source selected for DFSDM clock"
+#endif
+
+/**
+ * @brief SDMMC frequency.
+ */
+#define STM32_SDMMCCLK STM32_48CLK
+
+/**
+ * @brief Clock of timers connected to APB1
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Clock of timers connected to APB2.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS
+
+#elif STM32_HCLK <= STM32_1WS_THRESHOLD
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS
+
+#elif STM32_HCLK <= STM32_2WS_THRESHOLD
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
+
+#elif STM32_HCLK <= STM32_3WS_THRESHOLD
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
+
+#else
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
+#endif
+
+/**
+ * @brief Flash settings for MSI.
+ */
+#if (STM32_MSICLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_0WS
+
+#elif STM32_MSICLK <= STM32_1WS_THRESHOLD
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_1WS
+
+#elif STM32_MSICLK <= STM32_2WS_THRESHOLD
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_2WS
+
+#elif STM32_MSICLK <= STM32_3WS_THRESHOLD
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_3WS
+
+#else
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_4WS
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/platform.mk
new file mode 100644
index 0000000000..a9f37b222e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/platform.mk
@@ -0,0 +1,35 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/platform_l432.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/platform_l432.mk
new file mode 100644
index 0000000000..59382e527f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/platform_l432.mk
@@ -0,0 +1,35 @@
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h
new file mode 100644
index 0000000000..b74901e6d9
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h
@@ -0,0 +1,1203 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/stm32_rcc.h
+ * @brief RCC helper driver header.
+ * @note This file requires definitions from the ST header file
+ * @p stm32l4xx.h.
+ *
+ * @addtogroup STM32L4xx_RCC
+ * @{
+ */
+#ifndef _STM32_RCC_
+#define _STM32_RCC_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1R1(mask, lp) { \
+ RCC->APB1ENR1 |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1R1(mask, lp) { \
+ RCC->APB1ENR1 &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1R1(mask) { \
+ RCC->APB1RSTR1 |= (mask); \
+ RCC->APB1RSTR1 = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1R2(mask, lp) { \
+ RCC->APB1ENR2 |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1R2(mask, lp) { \
+ RCC->APB1ENR2 &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1R2(mask) { \
+ RCC->APB1RSTR2 |= (mask); \
+ RCC->APB1RSTR2 = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) { \
+ RCC->APB2ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask, lp) { \
+ RCC->APB2ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) { \
+ RCC->APB2RSTR |= (mask); \
+ RCC->APB2RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB1(mask, lp) { \
+ RCC->AHB1ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB1(mask, lp) { \
+ RCC->AHB1ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB1(mask) { \
+ RCC->AHB1RSTR |= (mask); \
+ RCC->AHB1RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB2(mask, lp) { \
+ RCC->AHB2ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB2(mask, lp) { \
+ RCC->AHB2ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB2(mask) { \
+ RCC->AHB2RSTR |= (mask); \
+ RCC->AHB2RSTR = 0; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB3(mask, lp) { \
+ RCC->AHB3ENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB3(mask, lp) { \
+ RCC->AHB3ENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB3(mask) { \
+ RCC->AHB3RSTR |= (mask); \
+ RCC->AHB3RSTR = 0; \
+}
+/** @} */
+
+/**
+ * @name ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ADC1/ADC2/ADC3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC123(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
+
+/**
+ * @brief Disables the ADC1/ADC2/ADC3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC123(lp) rccDisableAHB2(RCC_AHB2ENR_ADCEN, lp)
+
+/**
+ * @brief Resets the ADC1/ADC2/ADC3 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC123() rccResetAHB2(RCC_AHB2RSTR_ADCRST)
+/** @} */
+
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDAC1(lp) rccDisableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DAC1RST)
+/** @} */
+
+/**
+ * @name DMA peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
+
+/**
+ * @brief Disables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
+
+/**
+ * @brief Enables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
+
+/**
+ * @brief Disables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp)
+
+/**
+ * @brief Resets the DMA2 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
+/** @} */
+
+/**
+ * @name PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1R1(RCC_APB1ENR1_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1R1(RCC_APB1ENR1_PWREN, lp)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST)
+/** @} */
+
+/**
+ * @name CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CAN1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1R1(RCC_APB1ENR1_CAN1EN, lp)
+
+/**
+ * @brief Disables the CAN1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN1(lp) rccDisableAPB1R1(RCC_APB1ENR1_CAN1EN, lp)
+
+/**
+ * @brief Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1R1(RCC_APB1RSTR1_CAN1RST)
+/** @} */
+
+/**
+ * @name I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
+
+/**
+ * @brief Disables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C1(lp) rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
+
+/**
+ * @brief Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
+
+/**
+ * @brief Enables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
+
+/**
+ * @brief Disables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C2(lp) rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
+
+/**
+ * @brief Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
+
+/**
+ * @brief Enables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
+
+/**
+ * @brief Disables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C3(lp) rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
+
+/**
+ * @brief Resets the I2C3 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
+/** @} */
+
+/**
+ * @name OTG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
+
+/**
+ * @brief Disables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
+
+/**
+ * @brief Resets the OTG_FS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
+/** @} */
+
+/**
+ * @name QUADSPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Disables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Resets the QUADSPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
+/** @} */
+
+/**
+ * @name SDMMC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SDMMC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
+
+/**
+ * @brief Disables the SDMMC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSDMMC1(lp) rccDisableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
+
+/**
+ * @brief Resets the SDMMC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST)
+/** @} */
+
+/**
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Disables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief Enables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
+
+/**
+ * @brief Disables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI2(lp) rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
+
+/**
+ * @brief Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
+
+/**
+ * @brief Enables the SPI3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI3EN, lp)
+
+/**
+ * @brief Disables the SPI3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI3(lp) rccDisableAPB1R1(RCC_APB1ENR1_SPI3EN, lp)
+
+/**
+ * @brief Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1R1(RCC_APB1RSTR1_SPI3RST)
+/** @} */
+
+/**
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Disables the TIM1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
+/**
+ * @brief Enables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
+
+/**
+ * @brief Disables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM2(lp) rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
+
+/**
+ * @brief Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
+
+/**
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM3(lp) rccDisableAPB1R1(RCC_APB1ENR1_TIM3EN, lp)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1R1(RCC_APB1RSTR1_TIM3RST)
+
+/**
+ * @brief Enables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM4EN, lp)
+
+/**
+ * @brief Disables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM4(lp) rccDisableAPB1R1(RCC_APB1ENR1_TIM4EN, lp)
+
+/**
+ * @brief Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1R1(RCC_APB1RSTR1_TIM4RST)
+
+/**
+ * @brief Enables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM5(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM5EN, lp)
+
+/**
+ * @brief Disables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM5(lp) rccDisableAPB1R1(RCC_APB1ENR1_TIM5EN, lp)
+
+/**
+ * @brief Resets the TIM5 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM5() rccResetAPB1R1(RCC_APB1RSTR1_TIM5RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1R1(RCC_APB1ENR1_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1R1(RCC_APB1RSTR1_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1R1(RCC_APB1ENR1_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1R1(RCC_APB1RSTR1_TIM7RST)
+
+/**
+ * @brief Enables the TIM8 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Disables the TIM8 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
+
+/**
+ * @brief Enables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Disables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Resets the TIM15 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
+
+/**
+ * @brief Enables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Disables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Resets the TIM16 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
+
+/**
+ * @brief Enables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Disables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Resets the TIM17 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+/** @} */
+
+/**
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Disables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief Enables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
+
+/**
+ * @brief Disables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART2(lp) rccDisableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
+
+/**
+ * @brief Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART3(lp) rccDisableAPB1R1(RCC_APB1ENR1_USART3EN, lp)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1R1(RCC_APB1RSTR1_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1R1(RCC_APB1ENR1_UART4EN, lp)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1R1(RCC_APB1RSTR1_UART4RST)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1R1(RCC_APB1RSTR1_UART5RST)
+
+/**
+ * @brief Enables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
+
+/**
+ * @brief Disables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableLPUART1(lp) rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
+/** @} */
+
+/**
+ * @name USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBFSEN, lp)
+
+/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSB(lp) rccDisableAPB1R1(RCC_APB1ENR1_USBFSEN, lp)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBFSRST)
+/** @} */
+
+/**
+ * @name FSMC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
+
+/**
+ * @brief Disables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp)
+
+/**
+ * @brief Resets the FSMC peripheral.
+ *
+ * @api
+ */
+#define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_RCC_ */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
new file mode 100644
index 0000000000..197a110a1f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
@@ -0,0 +1,773 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/stm32_registry.h
+ * @brief STM32L4xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+#if defined(STM32L432xx)
+#define STM32L432xx
+
+#elif defined(STM32L476xx)
+#define STM32L476xx
+
+#else
+#error "STM32L4xx device not specified"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32L4xx capabilities
+ * @{
+ */
+
+/*===========================================================================*/
+/* STM32L432xx. */
+/*===========================================================================*/
+
+#if defined(STM32L432xx) || defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00003600
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_DAC1_CH2_DMA_CHN 0x00035000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 7
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH6_HANDLER Vector150
+#define STM32_DMA2_CH7_HANDLER Vector154
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+#define STM32_DMA2_CH6_NUMBER 68
+#define STM32_DMA2_CH7_NUMBER 69
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 37
+#define STM32_EXTI_IMR_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0x00000087U
+
+#define STM32_EXTI_LINE0_HANDLER Vector58
+#define STM32_EXTI_LINE1_HANDLER Vector5C
+#define STM32_EXTI_LINE2_HANDLER Vector60
+#define STM32_EXTI_LINE3_HANDLER Vector64
+#define STM32_EXTI_LINE4_HANDLER Vector68
+#define STM32_EXTI_LINE5_9_HANDLER Vector9C
+#define STM32_EXTI_LINE10_15_HANDLER VectorE0
+#define STM32_EXTI_LINE1635_38_HANDLER Vector44
+#define STM32_EXTI_LINE18_HANDLER VectorE4
+#define STM32_EXTI_LINE19_HANDLER Vector48
+#define STM32_EXTI_LINE20_HANDLER Vector4C
+#define STM32_EXTI_LINE2122_HANDLER Vector140
+
+#define STM32_EXTI_LINE0_NUMBER 6
+#define STM32_EXTI_LINE1_NUMBER 7
+#define STM32_EXTI_LINE2_NUMBER 8
+#define STM32_EXTI_LINE3_NUMBER 9
+#define STM32_EXTI_LINE4_NUMBER 10
+#define STM32_EXTI_LINE5_9_NUMBER 23
+#define STM32_EXTI_LINE10_15_NUMBER 40
+#define STM32_EXTI_LINE1635_38_NUMBER 1
+#define STM32_EXTI_LINE18_NUMBER 41
+#define STM32_EXTI_LINE19_NUMBER 2
+#define STM32_EXTI_LINE20_NUMBER 3
+#define STM32_EXTI_LINE2122_NUMBER 64
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_ERROR_NUMBER 32
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_I2C1_RX_DMA_CHN 0x03500000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_I2C1_TX_DMA_CHN 0x05300000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C3_ERROR_NUMBER 73
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector15C
+#define STM32_QUADSPI1_NUMBER 71
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 FALSE
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000410
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00004100
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S FALSE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_SPI3_RX_DMA_CHN 0x00000003
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+#define STM32_TIM1_UP_HANDLER VectorA4
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM1_UP_NUMBER 25
+#define STM32_TIM1_CC_NUMBER 27
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM2_NUMBER 28
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM6_NUMBER 54
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM7_NUMBER 55
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+#define STM32_TIM15_HANDLER VectorA0
+#define STM32_TIM15_NUMBER 24
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_HANDLER VectorA4
+#define STM32_TIM16_NUMBER 25
+
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART1_NUMBER 37
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART1_RX_DMA_CHN 0x02020000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_USART1_TX_DMA_CHN 0x00202000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART2_NUMBER 38
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00200000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x02000000
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER Vector158
+#define STM32_LPUART1_NUMBER 70
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+#define STM32_USB1_HP_HANDLER Vector14C
+#define STM32_USB1_LP_HANDLER Vector14C
+#define STM32_USB1_HP_NUMBER 67
+#define STM32_USB1_LP_NUMBER 67
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#endif /* defined(STM32L432xx) */
+
+/*===========================================================================*/
+/* STM32L476xx. */
+/*===========================================================================*/
+
+#if defined(STM32L476xx)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00003600
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_DAC1_CH2_DMA_CHN 0x00035000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 7
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH6_HANDLER Vector150
+#define STM32_DMA2_CH7_HANDLER Vector154
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+#define STM32_DMA2_CH6_NUMBER 68
+#define STM32_DMA2_CH7_NUMBER 69
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 39
+#define STM32_EXTI_IMR_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
+
+#define STM32_EXTI_LINE0_HANDLER Vector58
+#define STM32_EXTI_LINE1_HANDLER Vector5C
+#define STM32_EXTI_LINE2_HANDLER Vector60
+#define STM32_EXTI_LINE3_HANDLER Vector64
+#define STM32_EXTI_LINE4_HANDLER Vector68
+#define STM32_EXTI_LINE5_9_HANDLER Vector9C
+#define STM32_EXTI_LINE10_15_HANDLER VectorE0
+#define STM32_EXTI_LINE1635_38_HANDLER Vector44
+#define STM32_EXTI_LINE18_HANDLER VectorE4
+#define STM32_EXTI_LINE19_HANDLER Vector48
+#define STM32_EXTI_LINE20_HANDLER Vector4C
+#define STM32_EXTI_LINE2122_HANDLER Vector140
+
+#define STM32_EXTI_LINE0_NUMBER 6
+#define STM32_EXTI_LINE1_NUMBER 7
+#define STM32_EXTI_LINE2_NUMBER 8
+#define STM32_EXTI_LINE3_NUMBER 9
+#define STM32_EXTI_LINE4_NUMBER 10
+#define STM32_EXTI_LINE5_9_NUMBER 23
+#define STM32_EXTI_LINE10_15_NUMBER 40
+#define STM32_EXTI_LINE1635_38_NUMBER 1
+#define STM32_EXTI_LINE18_NUMBER 41
+#define STM32_EXTI_LINE19_NUMBER 2
+#define STM32_EXTI_LINE20_NUMBER 3
+#define STM32_EXTI_LINE2122_NUMBER 64
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN | \
+ RCC_AHB2ENR_GPIODEN | \
+ RCC_AHB2ENR_GPIOEEN | \
+ RCC_AHB2ENR_GPIOFEN | \
+ RCC_AHB2ENR_GPIOGEN | \
+ RCC_AHB2ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_ERROR_NUMBER 32
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_I2C1_RX_DMA_CHN 0x03500000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_I2C1_TX_DMA_CHN 0x05300000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C2_ERROR_NUMBER 34
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN 0x00030000
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN 0x00003000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C3_ERROR_NUMBER 73
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector15C
+#define STM32_QUADSPI1_NUMBER 71
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 TRUE
+#define STM32_SDMMC1_HANDLER Vector104
+#define STM32_SDMMC1_NUMBER 49
+#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
+
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000410
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00004100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_SPI2_RX_DMA_CHN 0x00001000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_SPI2_TX_DMA_CHN 0x00010000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S FALSE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_SPI3_RX_DMA_CHN 0x00000003
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+#define STM32_TIM1_UP_HANDLER VectorA4
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM1_UP_NUMBER 25
+#define STM32_TIM1_CC_NUMBER 27
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM2_NUMBER 28
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM3_NUMBER 29
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM4_NUMBER 30
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM5_NUMBER 50
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM6_NUMBER 54
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM7_NUMBER 55
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+#define STM32_TIM8_UP_HANDLER VectorF0
+#define STM32_TIM8_CC_HANDLER VectorF8
+#define STM32_TIM8_UP_NUMBER 44
+#define STM32_TIM8_CC_NUMBER 46
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+#define STM32_TIM15_HANDLER VectorA0
+#define STM32_TIM15_NUMBER 24
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_HANDLER VectorA4
+#define STM32_TIM16_NUMBER 25
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_HANDLER VectorA8
+#define STM32_TIM17_NUMBER 26
+
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART1_NUMBER 37
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART1_RX_DMA_CHN 0x02020000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_USART1_TX_DMA_CHN 0x00202000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART2_NUMBER 38
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00200000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x02000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_USART3_NUMBER 39
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000200
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000020
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_HANDLER Vector110
+#define STM32_UART4_NUMBER 52
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
+#define STM32_UART4_RX_DMA_CHN 0x00020000
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3)
+#define STM32_UART4_TX_DMA_CHN 0x00000200
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_HANDLER Vector114
+#define STM32_UART5_NUMBER 53
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
+#define STM32_UART5_RX_DMA_CHN 0x00000020
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
+#define STM32_UART5_TX_DMA_CHN 0x00000002
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER Vector158
+#define STM32_LPUART1_NUMBER 70
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_SEQUENCE_WORKAROUND
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 5
+#define STM32_OTG1_HANDLER Vector14C
+#define STM32_OTG1_NUMBER 67
+
+#define STM32_HAS_OTG2 FALSE
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#endif /* defined(STM32L476xx) */
+
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/todo.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/todo.txt
new file mode 100644
index 0000000000..5dc50c8689
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/STM32/todo.txt
@@ -0,0 +1,4 @@
+- BOFF handling in DACv1.
+- Oversampling support for ADCv1 and ADCv3.
+- Implement missing ICU/PWM/GPT/ST units using shared IRQ handlers.
+- Implement I2S driver over SAI interfaces.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/common/ARMCMx/nvic.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/common/ARMCMx/nvic.c
new file mode 100644
index 0000000000..0bbaf20c96
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/common/ARMCMx/nvic.c
@@ -0,0 +1,114 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file common/ARMCMx/nvic.c
+ * @brief Cortex-Mx NVIC support code.
+ *
+ * @addtogroup COMMON_ARMCMx_NVIC
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Sets the priority of an interrupt handler and enables it.
+ *
+ * @param[in] n the interrupt number
+ * @param[in] prio the interrupt priority
+ */
+void nvicEnableVector(uint32_t n, uint32_t prio) {
+
+#if defined(__CORE_CM0_H_GENERIC)
+ NVIC->IP[_IP_IDX(n)] = (NVIC->IP[_IP_IDX(n)] & ~(0xFFU << _BIT_SHIFT(n))) |
+ (NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(n));
+#else
+ NVIC->IP[n] = NVIC_PRIORITY_MASK(prio);
+#endif
+ NVIC->ICPR[n >> 5U] = 1U << (n & 0x1FU);
+ NVIC->ISER[n >> 5U] = 1U << (n & 0x1FU);
+}
+
+/**
+ * @brief Disables an interrupt handler.
+ *
+ * @param[in] n the interrupt number
+ */
+void nvicDisableVector(uint32_t n) {
+
+ NVIC->ICER[n >> 5U] = 1U << (n & 0x1FU);
+#if defined(__CORE_CM0_H_GENERIC)
+ NVIC->IP[_IP_IDX(n)] = NVIC->IP[_IP_IDX(n)] & ~(0xFFU << _BIT_SHIFT(n));
+#else
+ NVIC->IP[n] = 0U;
+#endif
+}
+
+/**
+ * @brief Changes the priority of a system handler.
+ *
+ * @param[in] handler the system handler number
+ * @param[in] prio the system handler priority
+ */
+void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
+
+ osalDbgCheck(handler < 12U);
+
+#if defined(__CORE_CM0_H_GENERIC)
+ SCB->SHP[_SHP_IDX(handler)] = (SCB->SHP[_SHP_IDX(handler)] & ~(0xFFU << _BIT_SHIFT(handler))) |
+ (NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(handler));
+#elif defined(__CORE_CM7_H_GENERIC)
+ SCB->SHPR[handler] = NVIC_PRIORITY_MASK(prio);
+#else
+ SCB->SHP[handler] = NVIC_PRIORITY_MASK(prio);
+#endif
+}
+
+/**
+ * @brief Clears a pending interrupt source.
+ *
+ * @param[in] n the interrupt number
+ */
+void nvicClearPending(uint32_t n) {
+
+ NVIC->ICPR[n >> 5] = 1 << (n & 0x1F);
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/common/ARMCMx/nvic.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/common/ARMCMx/nvic.h
new file mode 100644
index 0000000000..72ef7aff0e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/ports/common/ARMCMx/nvic.h
@@ -0,0 +1,88 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file common/ARMCMx/nvic.h
+ * @brief Cortex-Mx NVIC support macros and structures.
+ *
+ * @addtogroup COMMON_ARMCMx_NVIC
+ * @{
+ */
+
+#ifndef NVIC_H
+#define NVIC_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name System vectors numbers
+ * @{
+ */
+#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */
+#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */
+#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */
+#define HANDLER_RESERVED_3 3
+#define HANDLER_RESERVED_4 4
+#define HANDLER_RESERVED_5 5
+#define HANDLER_RESERVED_6 6
+#define HANDLER_SVCALL 7 /**< SVCALL vector id. */
+#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */
+#define HANDLER_RESERVED_9 9
+#define HANDLER_PENDSV 10 /**< PENDSV vector id. */
+#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Priority level to priority mask conversion macro.
+ */
+#define NVIC_PRIORITY_MASK(prio) ((prio) << (8U - (unsigned)__NVIC_PRIO_BITS))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void nvicEnableVector(uint32_t n, uint32_t prio);
+ void nvicDisableVector(uint32_t n);
+ void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
+ void nvicClearPending(uint32_t n);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NVIC_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/can.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/can.c
deleted file mode 100644
index 8ce09ef674..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/can.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file can.c
- * @brief CAN Driver code.
- *
- * @addtogroup CAN
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief CAN Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void canInit(void) {
-
- can_lld_init();
-}
-
-/**
- * @brief Initializes the standard part of a @p CANDriver structure.
- *
- * @param[out] canp pointer to the @p CANDriver object
- *
- * @init
- */
-void canObjectInit(CANDriver *canp) {
-
- canp->state = CAN_STOP;
- canp->config = NULL;
- chSemInit(&canp->txsem, 0);
- chSemInit(&canp->rxsem, 0);
- chEvtInit(&canp->rxfull_event);
- chEvtInit(&canp->txempty_event);
- chEvtInit(&canp->error_event);
-#if CAN_USE_SLEEP_MODE
- chEvtInit(&canp->sleep_event);
- chEvtInit(&canp->wakeup_event);
-#endif /* CAN_USE_SLEEP_MODE */
-}
-
-/**
- * @brief Configures and activates the CAN peripheral.
- * @note Activating the CAN bus can be a slow operation this this function
- * is not atomic, it waits internally for the initialization to
- * complete.
- *
- * @param[in] canp pointer to the @p CANDriver object
- * @param[in] config pointer to the @p CANConfig object. Depending on
- * the implementation the value can be @p NULL.
- *
- * @api
- */
-void canStart(CANDriver *canp, const CANConfig *config) {
-
- chDbgCheck(canp != NULL, "canStart");
-
- chSysLock();
- chDbgAssert((canp->state == CAN_STOP) ||
- (canp->state == CAN_STARTING) ||
- (canp->state == CAN_READY),
- "canStart(), #1", "invalid state");
- while (canp->state == CAN_STARTING)
- chThdSleepS(1);
- if (canp->state == CAN_STOP) {
- canp->config = config;
- can_lld_start(canp);
- canp->state = CAN_READY;
- }
- chSysUnlock();
-}
-
-/**
- * @brief Deactivates the CAN peripheral.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @api
- */
-void canStop(CANDriver *canp) {
-
- chDbgCheck(canp != NULL, "canStop");
-
- chSysLock();
- chDbgAssert((canp->state == CAN_STOP) || (canp->state == CAN_READY),
- "canStop(), #1", "invalid state");
- can_lld_stop(canp);
- canp->state = CAN_STOP;
- chSemResetI(&canp->rxsem, 0);
- chSemResetI(&canp->txsem, 0);
- chSchRescheduleS();
- chSysUnlock();
-}
-
-/**
- * @brief Can frame transmission.
- * @details The specified frame is queued for transmission, if the hardware
- * queue is full then the invoking thread is queued.
- * @note Trying to transmit while in sleep mode simply enqueues the thread.
- *
- * @param[in] canp pointer to the @p CANDriver object
- * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[in] ctfp pointer to the CAN frame to be transmitted
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation result.
- * @retval RDY_OK the frame has been queued for transmission.
- * @retval RDY_TIMEOUT The operation has timed out.
- * @retval RDY_RESET The driver has been stopped while waiting.
- *
- * @api
- */
-msg_t canTransmit(CANDriver *canp,
- canmbx_t mailbox,
- const CANTxFrame *ctfp,
- systime_t timeout) {
-
- chDbgCheck((canp != NULL) && (ctfp != NULL) && (mailbox <= CAN_TX_MAILBOXES),
- "canTransmit");
-
- chSysLock();
- chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
- "canTransmit(), #1", "invalid state");
- while ((canp->state == CAN_SLEEP) || !can_lld_is_tx_empty(canp, mailbox)) {
- msg_t msg = chSemWaitTimeoutS(&canp->txsem, timeout);
- if (msg != RDY_OK) {
- chSysUnlock();
- return msg;
- }
- }
- can_lld_transmit(canp, mailbox, ctfp);
- chSysUnlock();
- return RDY_OK;
-}
-
-/**
- * @brief Can frame receive.
- * @details The function waits until a frame is received.
- * @note Trying to receive while in sleep mode simply enqueues the thread.
- *
- * @param[in] canp pointer to the @p CANDriver object
- * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[out] crfp pointer to the buffer where the CAN frame is copied
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout (useful in an
- * event driven scenario where a thread never blocks
- * for I/O).
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation result.
- * @retval RDY_OK a frame has been received and placed in the buffer.
- * @retval RDY_TIMEOUT The operation has timed out.
- * @retval RDY_RESET The driver has been stopped while waiting.
- *
- * @api
- */
-msg_t canReceive(CANDriver *canp,
- canmbx_t mailbox,
- CANRxFrame *crfp,
- systime_t timeout) {
-
- chDbgCheck((canp != NULL) && (crfp != NULL) && (mailbox < CAN_RX_MAILBOXES),
- "canReceive");
-
- chSysLock();
- chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
- "canReceive(), #1", "invalid state");
- while ((canp->state == CAN_SLEEP) || !can_lld_is_rx_nonempty(canp, mailbox)) {
- msg_t msg = chSemWaitTimeoutS(&canp->rxsem, timeout);
- if (msg != RDY_OK) {
- chSysUnlock();
- return msg;
- }
- }
- can_lld_receive(canp, mailbox, crfp);
- chSysUnlock();
- return RDY_OK;
-}
-
-#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
-/**
- * @brief Enters the sleep mode.
- * @details This function puts the CAN driver in sleep mode and broadcasts
- * the @p sleep_event event source.
- * @pre In order to use this function the option @p CAN_USE_SLEEP_MODE must
- * be enabled and the @p CAN_SUPPORTS_SLEEP mode must be supported
- * by the low level driver.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @api
- */
-void canSleep(CANDriver *canp) {
-
- chDbgCheck(canp != NULL, "canSleep");
-
- chSysLock();
- chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
- "canSleep(), #1", "invalid state");
- if (canp->state == CAN_READY) {
- can_lld_sleep(canp);
- canp->state = CAN_SLEEP;
- chEvtBroadcastI(&canp->sleep_event);
- chSchRescheduleS();
- }
- chSysUnlock();
-}
-
-/**
- * @brief Enforces leaving the sleep mode.
- * @note The sleep mode is supposed to be usually exited automatically by
- * an hardware event.
- *
- * @param[in] canp pointer to the @p CANDriver object
- */
-void canWakeup(CANDriver *canp) {
-
- chDbgCheck(canp != NULL, "canWakeup");
-
- chSysLock();
- chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
- "canWakeup(), #1", "invalid state");
- if (canp->state == CAN_SLEEP) {
- can_lld_wakeup(canp);
- canp->state = CAN_READY;
- chEvtBroadcastI(&canp->wakeup_event);
- chSchRescheduleS();
- }
- chSysUnlock();
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-#endif /* HAL_USE_CAN */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal.c
index e70d87fd63..c702de6d8e 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal.c
@@ -1,28 +1,17 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
@@ -33,7 +22,6 @@
* @{
*/
-#include "ch.h"
#include "hal.h"
/*===========================================================================*/
@@ -67,135 +55,93 @@
*/
void halInit(void) {
+ /* Initializes the OS Abstraction Layer.*/
+ osalInit();
+
+ /* Platform low level initializations.*/
hal_lld_init();
-#if HAL_USE_TM || defined(__DOXYGEN__)
- tmInit();
-#endif
-#if HAL_USE_PAL || defined(__DOXYGEN__)
+#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
palInit(&pal_default_config);
#endif
-#if HAL_USE_ADC || defined(__DOXYGEN__)
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
adcInit();
#endif
-#if HAL_USE_CAN || defined(__DOXYGEN__)
+#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__)
canInit();
#endif
-#if HAL_USE_EXT || defined(__DOXYGEN__)
+#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__)
+ dacInit();
+#endif
+#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__)
extInit();
#endif
-#if HAL_USE_GPT || defined(__DOXYGEN__)
+#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__)
gptInit();
#endif
-#if HAL_USE_I2C || defined(__DOXYGEN__)
+#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__)
i2cInit();
#endif
-#if HAL_USE_ICU || defined(__DOXYGEN__)
+#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__)
+ i2sInit();
+#endif
+#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__)
icuInit();
#endif
-#if HAL_USE_MAC || defined(__DOXYGEN__)
+#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__)
macInit();
#endif
-#if HAL_USE_PWM || defined(__DOXYGEN__)
+#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__)
pwmInit();
#endif
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+#if (HAL_USE_QSPI == TRUE) || defined(__DOXYGEN__)
+ qspiInit();
+#endif
+#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
sdInit();
#endif
-#if HAL_USE_SDC || defined(__DOXYGEN__)
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
sdcInit();
#endif
-#if HAL_USE_SPI || defined(__DOXYGEN__)
+#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__)
spiInit();
#endif
-#if HAL_USE_UART || defined(__DOXYGEN__)
+#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__)
uartInit();
#endif
-#if HAL_USE_USB || defined(__DOXYGEN__)
+#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__)
usbInit();
#endif
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+#if (HAL_USE_MMC_SPI == TRUE) || defined(__DOXYGEN__)
mmcInit();
#endif
-#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__)
+#if (HAL_USE_SERIAL_USB == TRUE) || defined(__DOXYGEN__)
sduInit();
#endif
-#if HAL_USE_RTC || defined(__DOXYGEN__)
+#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__)
rtcInit();
#endif
- /* Board specific initialization.*/
- boardInit();
-}
+#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__)
+ wdgInit();
+#endif
-#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__)
-/**
- * @brief Realtime window test.
- * @details This function verifies if the current realtime counter value
- * lies within the specified range or not. The test takes care
- * of the realtime counter wrapping to zero on overflow.
- * @note When start==end then the function returns always true because the
- * whole time range is specified.
- * @note This is an optional service that could not be implemented in
- * all HAL implementations.
- * @note This function can be called from any context.
- *
- * @par Example 1
- * Example of a guarded loop using the realtime counter. The loop implements
- * a timeout after one second.
- * @code
- * halrtcnt_t start = halGetCounterValue();
- * halrtcnt_t timeout = start + S2RTT(1);
- * while (my_condition) {
- * if (!halIsCounterWithin(start, timeout)
- * return TIMEOUT;
- * // Do something.
- * }
- * // Continue.
- * @endcode
- *
- * @par Example 2
- * Example of a loop that lasts exactly 50 microseconds.
- * @code
- * halrtcnt_t start = halGetCounterValue();
- * halrtcnt_t timeout = start + US2RTT(50);
- * while (halIsCounterWithin(start, timeout)) {
- * // Do something.
- * }
- * // Continue.
- * @endcode
- *
- * @param[in] start the start of the time window (inclusive)
- * @param[in] end the end of the time window (non inclusive)
- * @retval TRUE current time within the specified time window.
- * @retval FALSE current time not within the specified time window.
- *
- * @special
- */
-bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end) {
- halrtcnt_t now = halGetCounterValue();
+ /* Community driver overlay initialization.*/
+#if defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#if (HAL_USE_COMMUNITY == TRUE) || defined(__DOXYGEN__)
+ halCommunityInit();
+#endif
+#endif
- return end > start ? (now >= start) && (now < end) :
- (now >= start) || (now < end);
-}
+ /* Board specific initialization.*/
+ boardInit();
-/**
- * @brief Polled delay.
- * @note The real delays is always few cycles in excess of the specified
- * value.
- * @note This is an optional service that could not be implemented in
- * all HAL implementations.
- * @note This function can be called from any context.
- *
- * @param[in] ticks number of ticks
- *
- * @special
+/*
+ * The ST driver is a special case, it is only initialized if the OSAL is
+ * configured to require it.
*/
-void halPolledDelay(halrtcnt_t ticks) {
- halrtcnt_t start = halGetCounterValue();
- halrtcnt_t timeout = start + (ticks);
- while (halIsCounterWithin(start, timeout))
- ;
+#if OSAL_ST_MODE != OSAL_ST_MODE_NONE
+ stInit();
+#endif
}
-#endif /* HAL_IMPLEMENTS_COUNTERS */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/adc.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_adc.c
similarity index 68%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/adc.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_adc.c
index bdb5cef6ce..3a94069ad9 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/adc.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_adc.c
@@ -1,42 +1,30 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file adc.c
+ * @file hal_adc.c
* @brief ADC Driver code.
*
* @addtogroup ADC
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_ADC || defined(__DOXYGEN__)
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -84,16 +72,12 @@ void adcObjectInit(ADCDriver *adcp) {
adcp->samples = NULL;
adcp->depth = 0;
adcp->grpp = NULL;
-#if ADC_USE_WAIT
+#if ADC_USE_WAIT == TRUE
adcp->thread = NULL;
-#endif /* ADC_USE_WAIT */
-#if ADC_USE_MUTUAL_EXCLUSION
-#if CH_USE_MUTEXES
- chMtxInit(&adcp->mutex);
-#else
- chSemInit(&adcp->semaphore, 1);
#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if ADC_USE_MUTUAL_EXCLUSION == TRUE
+ osalMutexObjectInit(&adcp->mutex);
+#endif
#if defined(ADC_DRIVER_EXT_INIT_HOOK)
ADC_DRIVER_EXT_INIT_HOOK(adcp);
#endif
@@ -110,15 +94,15 @@ void adcObjectInit(ADCDriver *adcp) {
*/
void adcStart(ADCDriver *adcp, const ADCConfig *config) {
- chDbgCheck(adcp != NULL, "adcStart");
+ osalDbgCheck(adcp != NULL);
- chSysLock();
- chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY),
- "adcStart(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY),
+ "invalid state");
adcp->config = config;
adc_lld_start(adcp);
adcp->state = ADC_READY;
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -130,14 +114,18 @@ void adcStart(ADCDriver *adcp, const ADCConfig *config) {
*/
void adcStop(ADCDriver *adcp) {
- chDbgCheck(adcp != NULL, "adcStop");
+ osalDbgCheck(adcp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY),
+ "invalid state");
- chSysLock();
- chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY),
- "adcStop(), #1", "invalid state");
adc_lld_stop(adcp);
- adcp->state = ADC_STOP;
- chSysUnlock();
+ adcp->config = NULL;
+ adcp->state = ADC_STOP;
+
+ osalSysUnlock();
}
/**
@@ -161,9 +149,9 @@ void adcStartConversion(ADCDriver *adcp,
adcsample_t *samples,
size_t depth) {
- chSysLock();
+ osalSysLock();
adcStartConversionI(adcp, grpp, samples, depth);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -189,14 +177,13 @@ void adcStartConversionI(ADCDriver *adcp,
adcsample_t *samples,
size_t depth) {
- chDbgCheckClassI();
- chDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) &&
- ((depth == 1) || ((depth & 1) == 0)),
- "adcStartConversionI");
- chDbgAssert((adcp->state == ADC_READY) ||
- (adcp->state == ADC_COMPLETE) ||
- (adcp->state == ADC_ERROR),
- "adcStartConversionI(), #1", "not ready");
+ osalDbgCheckClassI();
+ osalDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) &&
+ (depth > 0U) && ((depth == 1U) || ((depth & 1U) == 0U)));
+ osalDbgAssert((adcp->state == ADC_READY) ||
+ (adcp->state == ADC_COMPLETE) ||
+ (adcp->state == ADC_ERROR),
+ "not ready");
adcp->samples = samples;
adcp->depth = depth;
@@ -217,19 +204,18 @@ void adcStartConversionI(ADCDriver *adcp,
*/
void adcStopConversion(ADCDriver *adcp) {
- chDbgCheck(adcp != NULL, "adcStopConversion");
+ osalDbgCheck(adcp != NULL);
- chSysLock();
- chDbgAssert((adcp->state == ADC_READY) ||
- (adcp->state == ADC_ACTIVE),
- "adcStopConversion(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert((adcp->state == ADC_READY) || (adcp->state == ADC_ACTIVE),
+ "invalid state");
if (adcp->state != ADC_READY) {
adc_lld_stop_conversion(adcp);
adcp->grpp = NULL;
adcp->state = ADC_READY;
_adc_reset_s(adcp);
}
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -244,12 +230,12 @@ void adcStopConversion(ADCDriver *adcp) {
*/
void adcStopConversionI(ADCDriver *adcp) {
- chDbgCheckClassI();
- chDbgCheck(adcp != NULL, "adcStopConversionI");
- chDbgAssert((adcp->state == ADC_READY) ||
- (adcp->state == ADC_ACTIVE) ||
- (adcp->state == ADC_COMPLETE),
- "adcStopConversionI(), #1", "invalid state");
+ osalDbgCheckClassI();
+ osalDbgCheck(adcp != NULL);
+ osalDbgAssert((adcp->state == ADC_READY) ||
+ (adcp->state == ADC_ACTIVE) ||
+ (adcp->state == ADC_COMPLETE),
+ "invalid state");
if (adcp->state != ADC_READY) {
adc_lld_stop_conversion(adcp);
@@ -259,7 +245,7 @@ void adcStopConversionI(ADCDriver *adcp) {
}
}
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
/**
* @brief Performs an ADC conversion.
* @details Performs a synchronous conversion operation.
@@ -274,11 +260,11 @@ void adcStopConversionI(ADCDriver *adcp) {
* @param[in] depth buffer depth (matrix rows number). The buffer depth
* must be one or an even number.
* @return The operation result.
- * @retval RDY_OK Conversion finished.
- * @retval RDY_RESET The conversion has been stopped using
+ * @retval MSG_OK Conversion finished.
+ * @retval MSG_RESET The conversion has been stopped using
* @p acdStopConversion() or @p acdStopConversionI(),
* the result buffer may contain incorrect data.
- * @retval RDY_TIMEOUT The conversion has been stopped because an hardware
+ * @retval MSG_TIMEOUT The conversion has been stopped because an hardware
* error.
*
* @api
@@ -289,18 +275,16 @@ msg_t adcConvert(ADCDriver *adcp,
size_t depth) {
msg_t msg;
- chSysLock();
- chDbgAssert(adcp->thread == NULL, "adcConvert(), #1", "already waiting");
+ osalSysLock();
+ osalDbgAssert(adcp->thread == NULL, "already waiting");
adcStartConversionI(adcp, grpp, samples, depth);
- adcp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- msg = chThdSelf()->p_u.rdymsg;
- chSysUnlock();
+ msg = osalThreadSuspendS(&adcp->thread);
+ osalSysUnlock();
return msg;
}
-#endif /* ADC_USE_WAIT */
+#endif /* ADC_USE_WAIT == TRUE */
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
/**
* @brief Gains exclusive access to the ADC peripheral.
* @details This function tries to gain ownership to the ADC bus, if the bus
@@ -314,13 +298,9 @@ msg_t adcConvert(ADCDriver *adcp,
*/
void adcAcquireBus(ADCDriver *adcp) {
- chDbgCheck(adcp != NULL, "adcAcquireBus");
+ osalDbgCheck(adcp != NULL);
-#if CH_USE_MUTEXES
- chMtxLock(&adcp->mutex);
-#elif CH_USE_SEMAPHORES
- chSemWait(&adcp->semaphore);
-#endif
+ osalMutexLock(&adcp->mutex);
}
/**
@@ -334,17 +314,12 @@ void adcAcquireBus(ADCDriver *adcp) {
*/
void adcReleaseBus(ADCDriver *adcp) {
- chDbgCheck(adcp != NULL, "adcReleaseBus");
+ osalDbgCheck(adcp != NULL);
-#if CH_USE_MUTEXES
- (void)adcp;
- chMtxUnlock();
-#elif CH_USE_SEMAPHORES
- chSemSignal(&adcp->semaphore);
-#endif
+ osalMutexUnlock(&adcp->mutex);
}
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#endif /* ADC_USE_MUTUAL_EXCLUSION == TRUE */
-#endif /* HAL_USE_ADC */
+#endif /* HAL_USE_ADC == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_buffers.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_buffers.c
new file mode 100644
index 0000000000..db143956c8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_buffers.c
@@ -0,0 +1,885 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_buffers.c
+ * @brief I/O Buffers code.
+ *
+ * @addtogroup HAL_BUFFERS
+ * @details Buffers Queues are used when there is the need to exchange
+ * fixed-length data buffers between ISRs and threads.
+ * On the ISR side data can be exchanged only using buffers,
+ * on the thread side data can be exchanged both using buffers and/or
+ * using an emulation of regular byte queues.
+ * There are several kind of buffers queues:
+ * - Input queue, unidirectional queue where the writer is the
+ * ISR side and the reader is the thread side.
+ * - Output queue, unidirectional queue where the writer is the
+ * ISR side and the reader is the thread side.
+ * - Full duplex queue, bidirectional queue. Full duplex queues
+ * are implemented by pairing an input queue and an output queue
+ * together.
+ * .
+ * @{
+ */
+
+#include
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes an input buffers queue object.
+ *
+ * @param[out] ibqp pointer to the @p input_buffers_queue_t object
+ * @param[in] suspended initial state of the queue
+ * @param[in] bp pointer to a memory area allocated for buffers
+ * @param[in] size buffers size
+ * @param[in] n number of buffers
+ * @param[in] infy callback called when a buffer is returned to the queue
+ * @param[in] link application defined pointer
+ *
+ * @init
+ */
+void ibqObjectInit(input_buffers_queue_t *ibqp, bool suspended, uint8_t *bp,
+ size_t size, size_t n, bqnotify_t infy, void *link) {
+
+ osalDbgCheck((ibqp != NULL) && (bp != NULL) && (size >= 2U));
+
+ osalThreadQueueObjectInit(&ibqp->waiting);
+ ibqp->suspended = suspended;
+ ibqp->bcounter = 0;
+ ibqp->brdptr = bp;
+ ibqp->bwrptr = bp;
+ ibqp->btop = bp + ((size + sizeof (size_t)) * n);
+ ibqp->bsize = size + sizeof (size_t);
+ ibqp->bn = n;
+ ibqp->buffers = bp;
+ ibqp->ptr = NULL;
+ ibqp->top = NULL;
+ ibqp->notify = infy;
+ ibqp->link = link;
+}
+
+/**
+ * @brief Resets an input buffers queue.
+ * @details All the data in the input buffers queue is erased and lost, any
+ * waiting thread is resumed with status @p MSG_RESET.
+ * @note A reset operation can be used by a low level driver in order to
+ * obtain immediate attention from the high level layers.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ *
+ * @iclass
+ */
+void ibqResetI(input_buffers_queue_t *ibqp) {
+
+ osalDbgCheckClassI();
+
+ ibqp->bcounter = 0;
+ ibqp->brdptr = ibqp->buffers;
+ ibqp->bwrptr = ibqp->buffers;
+ ibqp->ptr = NULL;
+ ibqp->top = NULL;
+ osalThreadDequeueAllI(&ibqp->waiting, MSG_RESET);
+}
+
+/**
+ * @brief Gets the next empty buffer from the queue.
+ * @note The function always returns the same buffer if called repeatedly.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ * @return A pointer to the next buffer to be filled.
+ * @retval NULL if the queue is full.
+ *
+ * @iclass
+ */
+uint8_t *ibqGetEmptyBufferI(input_buffers_queue_t *ibqp) {
+
+ osalDbgCheckClassI();
+
+ if (ibqIsFullI(ibqp)) {
+ return NULL;
+ }
+
+ return ibqp->bwrptr + sizeof (size_t);
+}
+
+/**
+ * @brief Posts a new filled buffer to the queue.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ * @param[in] size used size of the buffer, cannot be zero
+ *
+ * @iclass
+ */
+void ibqPostFullBufferI(input_buffers_queue_t *ibqp, size_t size) {
+
+ osalDbgCheckClassI();
+
+ osalDbgCheck((size > 0U) && (size <= (ibqp->bsize - sizeof (size_t))));
+ osalDbgAssert(!ibqIsFullI(ibqp), "buffers queue full");
+
+ /* Writing size field in the buffer.*/
+ *((size_t *)ibqp->bwrptr) = size;
+
+ /* Posting the buffer in the queue.*/
+ ibqp->bcounter++;
+ ibqp->bwrptr += ibqp->bsize;
+ if (ibqp->bwrptr >= ibqp->btop) {
+ ibqp->bwrptr = ibqp->buffers;
+ }
+
+ /* Waking up one waiting thread, if any.*/
+ osalThreadDequeueNextI(&ibqp->waiting, MSG_OK);
+}
+
+/**
+ * @brief Gets the next filled buffer from the queue.
+ * @note The function always acquires the same buffer if called repeatedly.
+ * @post After calling the function the fields @p ptr and @p top are set
+ * at beginning and end of the buffer data or @p NULL if the queue
+ * is empty.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a buffer has been acquired.
+ * @retval MSG_TIMEOUT if the specified time expired.
+ * @retval MSG_RESET if the queue has been reset or has been put in
+ * suspended state.
+ *
+ * @api
+ */
+msg_t ibqGetFullBufferTimeout(input_buffers_queue_t *ibqp,
+ systime_t timeout) {
+ msg_t msg;
+
+ osalSysLock();
+ msg = ibqGetFullBufferTimeoutS(ibqp, timeout);
+ osalSysUnlock();
+
+ return msg;
+}
+
+ /**
+ * @brief Gets the next filled buffer from the queue.
+ * @note The function always acquires the same buffer if called repeatedly.
+ * @post After calling the function the fields @p ptr and @p top are set
+ * at beginning and end of the buffer data or @p NULL if the queue
+ * is empty.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a buffer has been acquired.
+ * @retval MSG_TIMEOUT if the specified time expired.
+ * @retval MSG_RESET if the queue has been reset or has been put in
+ * suspended state.
+ *
+ * @sclass
+ */
+ msg_t ibqGetFullBufferTimeoutS(input_buffers_queue_t *ibqp,
+ systime_t timeout) {
+
+ osalDbgCheckClassS();
+
+ while (ibqIsEmptyI(ibqp)) {
+ if (ibqp->suspended) {
+ return MSG_RESET;
+ }
+ msg_t msg = osalThreadEnqueueTimeoutS(&ibqp->waiting, timeout);
+ if (msg < MSG_OK) {
+ return msg;
+ }
+ }
+
+ osalDbgAssert(!ibqIsEmptyI(ibqp), "still empty");
+
+ /* Setting up the "current" buffer and its boundary.*/
+ ibqp->ptr = ibqp->brdptr + sizeof (size_t);
+ ibqp->top = ibqp->ptr + *((size_t *)ibqp->brdptr);
+
+ return MSG_OK;
+}
+
+/**
+ * @brief Releases the buffer back in the queue.
+ * @note The object callback is called after releasing the buffer.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ *
+ * @api
+ */
+void ibqReleaseEmptyBuffer(input_buffers_queue_t *ibqp) {
+
+ osalSysLock();
+ ibqReleaseEmptyBufferS(ibqp);
+ osalSysUnlock();
+}
+
+ /**
+ * @brief Releases the buffer back in the queue.
+ * @note The object callback is called after releasing the buffer.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ *
+ * @sclass
+ */
+ void ibqReleaseEmptyBufferS(input_buffers_queue_t *ibqp) {
+
+ osalDbgCheckClassS();
+ osalDbgAssert(!ibqIsEmptyI(ibqp), "buffers queue empty");
+
+ /* Freeing a buffer slot in the queue.*/
+ ibqp->bcounter--;
+ ibqp->brdptr += ibqp->bsize;
+ if (ibqp->brdptr >= ibqp->btop) {
+ ibqp->brdptr = ibqp->buffers;
+ }
+
+ /* No "current" buffer.*/
+ ibqp->ptr = NULL;
+
+ /* Notifying the buffer release.*/
+ if (ibqp->notify != NULL) {
+ ibqp->notify(ibqp);
+ }
+}
+
+/**
+ * @brief Input queue read with timeout.
+ * @details This function reads a byte value from an input queue. If
+ * the queue is empty then the calling thread is suspended until a
+ * new buffer arrives in the queue or a timeout occurs.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return A byte value from the queue.
+ * @retval MSG_TIMEOUT if the specified time expired.
+ * @retval MSG_RESET if the queue has been reset or has been put in
+ * suspended state.
+ *
+ * @api
+ */
+msg_t ibqGetTimeout(input_buffers_queue_t *ibqp, systime_t timeout) {
+ msg_t msg;
+
+ osalSysLock();
+
+ /* This condition indicates that a new buffer must be acquired.*/
+ if (ibqp->ptr == NULL) {
+ msg = ibqGetFullBufferTimeoutS(ibqp, timeout);
+ if (msg != MSG_OK) {
+ osalSysUnlock();
+ return msg;
+ }
+ }
+
+ /* Next byte from the buffer.*/
+ msg = (msg_t)*ibqp->ptr;
+ ibqp->ptr++;
+
+ /* If the current buffer has been fully read then it is returned as
+ empty in the queue.*/
+ if (ibqp->ptr >= ibqp->top) {
+ ibqReleaseEmptyBufferS(ibqp);
+ }
+
+ osalSysUnlock();
+ return msg;
+}
+
+/**
+ * @brief Input queue read with timeout.
+ * @details The function reads data from an input queue into a buffer.
+ * The operation completes when the specified amount of data has been
+ * transferred or after the specified timeout or if the queue has
+ * been reset.
+ *
+ * @param[in] ibqp pointer to the @p input_buffers_queue_t object
+ * @param[out] bp pointer to the data buffer
+ * @param[in] n the maximum amount of data to be transferred, the
+ * value 0 is reserved
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The number of bytes effectively transferred.
+ * @retval 0 if a timeout occurred.
+ *
+ * @api
+ */
+size_t ibqReadTimeout(input_buffers_queue_t *ibqp, uint8_t *bp,
+ size_t n, systime_t timeout) {
+ size_t r = 0;
+ systime_t deadline;
+
+ osalDbgCheck(n > 0U);
+
+ osalSysLock();
+
+ /* Time window for the whole operation.*/
+ deadline = osalOsGetSystemTimeX() + timeout;
+
+ while (true) {
+ size_t size;
+
+ /* This condition indicates that a new buffer must be acquired.*/
+ if (ibqp->ptr == NULL) {
+ msg_t msg;
+
+ /* TIME_INFINITE and TIME_IMMEDIATE are handled differently, no
+ deadline.*/
+ if ((timeout == TIME_INFINITE) || (timeout == TIME_IMMEDIATE)) {
+ msg = ibqGetFullBufferTimeoutS(ibqp, timeout);
+ }
+ else {
+ systime_t next_timeout = deadline - osalOsGetSystemTimeX();
+
+ /* Handling the case where the system time went past the deadline,
+ in this case next becomes a very high number because the system
+ time is an unsigned type.*/
+ if (next_timeout > timeout) {
+ osalSysUnlock();
+ return r;
+ }
+ msg = ibqGetFullBufferTimeoutS(ibqp, next_timeout);
+ }
+
+ /* Anything except MSG_OK interrupts the operation.*/
+ if (msg != MSG_OK) {
+ osalSysUnlock();
+ return r;
+ }
+ }
+
+ /* Size of the data chunk present in the current buffer.*/
+ size = (size_t)ibqp->top - (size_t)ibqp->ptr;
+ if (size > (n - r)) {
+ size = n - r;
+ }
+
+ /* Smaller chunks in order to not make the critical zone too long,
+ this impacts throughput however.*/
+ if (size > 64U) {
+ /* Giving the compiler a chance to optimize for a fixed size move.*/
+ memcpy(bp, ibqp->ptr, 64U);
+ bp += 64U;
+ ibqp->ptr += 64U;
+ r += 64U;
+ }
+ else {
+ memcpy(bp, ibqp->ptr, size);
+ bp += size;
+ ibqp->ptr += size;
+ r += size;
+ }
+
+ /* Has the current data buffer been finished? if so then release it.*/
+ if (ibqp->ptr >= ibqp->top) {
+ ibqReleaseEmptyBufferS(ibqp);
+ }
+
+ /* Giving a preemption chance.*/
+ osalSysUnlock();
+ if (r >= n) {
+ return r;
+ }
+ osalSysLock();
+ }
+}
+
+/**
+ * @brief Initializes an output buffers queue object.
+ *
+ * @param[out] obqp pointer to the @p output_buffers_queue_t object
+ * @param[in] suspended initial state of the queue
+ * @param[in] bp pointer to a memory area allocated for buffers
+ * @param[in] size buffers size
+ * @param[in] n number of buffers
+ * @param[in] onfy callback called when a buffer is posted in the queue
+ * @param[in] link application defined pointer
+ *
+ * @init
+ */
+void obqObjectInit(output_buffers_queue_t *obqp, bool suspended, uint8_t *bp,
+ size_t size, size_t n, bqnotify_t onfy, void *link) {
+
+ osalDbgCheck((obqp != NULL) && (bp != NULL) && (size >= 2U));
+
+ osalThreadQueueObjectInit(&obqp->waiting);
+ obqp->suspended = suspended;
+ obqp->bcounter = n;
+ obqp->brdptr = bp;
+ obqp->bwrptr = bp;
+ obqp->btop = bp + ((size + sizeof (size_t)) * n);
+ obqp->bsize = size + sizeof (size_t);
+ obqp->bn = n;
+ obqp->buffers = bp;
+ obqp->ptr = NULL;
+ obqp->top = NULL;
+ obqp->notify = onfy;
+ obqp->link = link;
+}
+
+/**
+ * @brief Resets an output buffers queue.
+ * @details All the data in the output buffers queue is erased and lost, any
+ * waiting thread is resumed with status @p MSG_RESET.
+ * @note A reset operation can be used by a low level driver in order to
+ * obtain immediate attention from the high level layers.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ *
+ * @iclass
+ */
+void obqResetI(output_buffers_queue_t *obqp) {
+
+ osalDbgCheckClassI();
+
+ obqp->bcounter = bqSizeX(obqp);
+ obqp->brdptr = obqp->buffers;
+ obqp->bwrptr = obqp->buffers;
+ obqp->ptr = NULL;
+ obqp->top = NULL;
+ osalThreadDequeueAllI(&obqp->waiting, MSG_RESET);
+}
+
+/**
+ * @brief Gets the next filled buffer from the queue.
+ * @note The function always returns the same buffer if called repeatedly.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ * @param[out] sizep pointer to the filled buffer size
+ * @return A pointer to the filled buffer.
+ * @retval NULL if the queue is empty.
+ *
+ * @iclass
+ */
+uint8_t *obqGetFullBufferI(output_buffers_queue_t *obqp,
+ size_t *sizep) {
+
+ osalDbgCheckClassI();
+
+ if (obqIsEmptyI(obqp)) {
+ return NULL;
+ }
+
+ /* Buffer size.*/
+ *sizep = *((size_t *)obqp->brdptr);
+
+ return obqp->brdptr + sizeof (size_t);
+}
+
+/**
+ * @brief Releases the next filled buffer back in the queue.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ *
+ * @iclass
+ */
+void obqReleaseEmptyBufferI(output_buffers_queue_t *obqp) {
+
+ osalDbgCheckClassI();
+ osalDbgAssert(!obqIsEmptyI(obqp), "buffers queue empty");
+
+ /* Freeing a buffer slot in the queue.*/
+ obqp->bcounter++;
+ obqp->brdptr += obqp->bsize;
+ if (obqp->brdptr >= obqp->btop) {
+ obqp->brdptr = obqp->buffers;
+ }
+
+ /* Waking up one waiting thread, if any.*/
+ osalThreadDequeueNextI(&obqp->waiting, MSG_OK);
+}
+
+/**
+ * @brief Gets the next empty buffer from the queue.
+ * @note The function always acquires the same buffer if called repeatedly.
+ * @post After calling the function the fields @p ptr and @p top are set
+ * at beginning and end of the buffer data or @p NULL if the queue
+ * is empty.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a buffer has been acquired.
+ * @retval MSG_TIMEOUT if the specified time expired.
+ * @retval MSG_RESET if the queue has been reset or has been put in
+ * suspended state.
+ *
+ * @api
+ */
+msg_t obqGetEmptyBufferTimeout(output_buffers_queue_t *obqp,
+ systime_t timeout) {
+ msg_t msg;
+
+ osalSysLock();
+ msg = obqGetEmptyBufferTimeoutS(obqp, timeout);
+ osalSysUnlock();
+
+ return msg;
+}
+
+/**
+ * @brief Gets the next empty buffer from the queue.
+ * @note The function always acquires the same buffer if called repeatedly.
+ * @post After calling the function the fields @p ptr and @p top are set
+ * at beginning and end of the buffer data or @p NULL if the queue
+ * is empty.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if a buffer has been acquired.
+ * @retval MSG_TIMEOUT if the specified time expired.
+ * @retval MSG_RESET if the queue has been reset or has been put in
+ * suspended state.
+ *
+ * @sclass
+ */
+msg_t obqGetEmptyBufferTimeoutS(output_buffers_queue_t *obqp,
+ systime_t timeout) {
+
+ osalDbgCheckClassS();
+
+ while (obqIsFullI(obqp)) {
+ if (obqp->suspended) {
+ return MSG_RESET;
+ }
+ msg_t msg = osalThreadEnqueueTimeoutS(&obqp->waiting, timeout);
+ if (msg < MSG_OK) {
+ return msg;
+ }
+ }
+
+ osalDbgAssert(!obqIsFullI(obqp), "still full");
+
+ /* Setting up the "current" buffer and its boundary.*/
+ obqp->ptr = obqp->bwrptr + sizeof (size_t);
+ obqp->top = obqp->bwrptr + obqp->bsize;
+
+ return MSG_OK;
+}
+
+/**
+ * @brief Posts a new filled buffer to the queue.
+ * @note The object callback is called after releasing the buffer.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ * @param[in] size used size of the buffer, cannot be zero
+ *
+ * @api
+ */
+void obqPostFullBuffer(output_buffers_queue_t *obqp, size_t size) {
+
+ osalSysLock();
+ obqPostFullBufferS(obqp, size);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Posts a new filled buffer to the queue.
+ * @note The object callback is called after releasing the buffer.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ * @param[in] size used size of the buffer, cannot be zero
+ *
+ * @sclass
+ */
+void obqPostFullBufferS(output_buffers_queue_t *obqp, size_t size) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck((size > 0U) && (size <= (obqp->bsize - sizeof (size_t))));
+ osalDbgAssert(!obqIsFullI(obqp), "buffers queue full");
+
+ /* Writing size field in the buffer.*/
+ *((size_t *)obqp->bwrptr) = size;
+
+ /* Posting the buffer in the queue.*/
+ obqp->bcounter--;
+ obqp->bwrptr += obqp->bsize;
+ if (obqp->bwrptr >= obqp->btop) {
+ obqp->bwrptr = obqp->buffers;
+ }
+
+ /* No "current" buffer.*/
+ obqp->ptr = NULL;
+
+ /* Notifying the buffer release.*/
+ if (obqp->notify != NULL) {
+ obqp->notify(obqp);
+ }
+}
+
+/**
+ * @brief Output queue write with timeout.
+ * @details This function writes a byte value to an output queue. If
+ * the queue is full then the calling thread is suspended until a
+ * new buffer is freed in the queue or a timeout occurs.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ * @param[in] b byte value to be transferred
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return A byte value from the queue.
+ * @retval MSG_TIMEOUT if the specified time expired.
+ * @retval MSG_RESET if the queue has been reset or has been put in
+ * suspended state.
+ *
+ * @api
+ */
+msg_t obqPutTimeout(output_buffers_queue_t *obqp, uint8_t b,
+ systime_t timeout) {
+ msg_t msg;
+
+ osalSysLock();
+
+ /* This condition indicates that a new buffer must be acquired.*/
+ if (obqp->ptr == NULL) {
+ msg = obqGetEmptyBufferTimeoutS(obqp, timeout);
+ if (msg != MSG_OK) {
+ osalSysUnlock();
+ return msg;
+ }
+ }
+
+ /* Writing the byte to the buffer.*/
+ *obqp->ptr = b;
+ obqp->ptr++;
+
+ /* If the current buffer has been fully written then it is posted as
+ full in the queue.*/
+ if (obqp->ptr >= obqp->top) {
+ obqPostFullBufferS(obqp, obqp->bsize - sizeof (size_t));
+ }
+
+ osalSysUnlock();
+ return MSG_OK;
+}
+
+/**
+ * @brief Output queue write with timeout.
+ * @details The function writes data from a buffer to an output queue. The
+ * operation completes when the specified amount of data has been
+ * transferred or after the specified timeout or if the queue has
+ * been reset.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ * @param[in] bp pointer to the data buffer
+ * @param[in] n the maximum amount of data to be transferred, the
+ * value 0 is reserved
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The number of bytes effectively transferred.
+ * @retval 0 if a timeout occurred.
+ *
+ * @api
+ */
+size_t obqWriteTimeout(output_buffers_queue_t *obqp, const uint8_t *bp,
+ size_t n, systime_t timeout) {
+ size_t w = 0;
+ systime_t deadline;
+
+ osalDbgCheck(n > 0U);
+
+ osalSysLock();
+
+ /* Time window for the whole operation.*/
+ deadline = osalOsGetSystemTimeX() + timeout;
+
+ while (true) {
+ size_t size;
+
+ /* This condition indicates that a new buffer must be acquired.*/
+ if (obqp->ptr == NULL) {
+ msg_t msg;
+
+ /* TIME_INFINITE and TIME_IMMEDIATE are handled differently, no
+ deadline.*/
+ if ((timeout == TIME_INFINITE) || (timeout == TIME_IMMEDIATE)) {
+ msg = obqGetEmptyBufferTimeoutS(obqp, timeout);
+ }
+ else {
+ systime_t next_timeout = deadline - osalOsGetSystemTimeX();
+
+ /* Handling the case where the system time went past the deadline,
+ in this case next becomes a very high number because the system
+ time is an unsigned type.*/
+ if (next_timeout > timeout) {
+ osalSysUnlock();
+ return w;
+ }
+ msg = obqGetEmptyBufferTimeoutS(obqp, next_timeout);
+ }
+
+ /* Anything except MSG_OK interrupts the operation.*/
+ if (msg != MSG_OK) {
+ osalSysUnlock();
+ return w;
+ }
+ }
+
+ /* Size of the space available in the current buffer.*/
+ size = (size_t)obqp->top - (size_t)obqp->ptr;
+ if (size > (n - w)) {
+ size = n - w;
+ }
+
+ /* Smaller chunks in order to not make the critical zone too long,
+ this impacts throughput however.*/
+ if (size > 64U) {
+ /* Giving the compiler a chance to optimize for a fixed size move.*/
+ memcpy(obqp->ptr, bp, 64U);
+ bp += 64U;
+ obqp->ptr += 64U;
+ w += 64U;
+ }
+ else {
+ memcpy(obqp->ptr, bp, size);
+ bp += size;
+ obqp->ptr += size;
+ w += size;
+ }
+
+ /* Has the current data buffer been finished? if so then release it.*/
+ if (obqp->ptr >= obqp->top) {
+ obqPostFullBufferS(obqp, obqp->bsize - sizeof (size_t));
+ }
+
+ /* Giving a preemption chance.*/
+ osalSysUnlock();
+ if (w >= n) {
+ return w;
+ }
+ osalSysLock();
+ }
+}
+
+/**
+ * @brief Flushes the current, partially filled, buffer to the queue.
+ * @note The notification callback is not invoked because the function
+ * is meant to be called from ISR context. An operation status is
+ * returned instead.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ * @return The operation status.
+ * @retval false if no new filled buffer has been posted to the queue.
+ * @retval true if a new filled buffer has been posted to the queue.
+ *
+ * @iclass
+ */
+bool obqTryFlushI(output_buffers_queue_t *obqp) {
+
+ osalDbgCheckClassI();
+
+ /* If queue is empty and there is a buffer partially filled and
+ it is not being written.*/
+ if (obqIsEmptyI(obqp) && (obqp->ptr != NULL)) {
+ size_t size = (size_t)obqp->ptr - ((size_t)obqp->bwrptr + sizeof (size_t));
+
+ if (size > 0U) {
+
+ /* Writing size field in the buffer.*/
+ *((size_t *)obqp->bwrptr) = size;
+
+ /* Posting the buffer in the queue.*/
+ obqp->bcounter--;
+ obqp->bwrptr += obqp->bsize;
+ if (obqp->bwrptr >= obqp->btop) {
+ obqp->bwrptr = obqp->buffers;
+ }
+
+ /* No "current" buffer.*/
+ obqp->ptr = NULL;
+
+ return true;
+ }
+ }
+ return false;
+}
+
+/**
+ * @brief Flushes the current, partially filled, buffer to the queue.
+ *
+ * @param[in] obqp pointer to the @p output_buffers_queue_t object
+ *
+ * @api
+ */
+void obqFlush(output_buffers_queue_t *obqp) {
+
+ osalSysLock();
+
+ /* If there is a buffer partially filled and not being written.*/
+ if (obqp->ptr != NULL) {
+ size_t size = ((size_t)obqp->ptr - (size_t)obqp->bwrptr) - sizeof (size_t);
+
+ if (size > 0U) {
+ obqPostFullBufferS(obqp, size);
+ }
+ }
+
+ osalSysUnlock();
+}
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_can.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_can.c
new file mode 100644
index 0000000000..a66bf500c3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_can.c
@@ -0,0 +1,362 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_can.c
+ * @brief CAN Driver code.
+ *
+ * @addtogroup CAN
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief CAN Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void canInit(void) {
+
+ can_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p CANDriver structure.
+ *
+ * @param[out] canp pointer to the @p CANDriver object
+ *
+ * @init
+ */
+void canObjectInit(CANDriver *canp) {
+
+ canp->state = CAN_STOP;
+ canp->config = NULL;
+ osalThreadQueueObjectInit(&canp->txqueue);
+ osalThreadQueueObjectInit(&canp->rxqueue);
+ osalEventObjectInit(&canp->rxfull_event);
+ osalEventObjectInit(&canp->txempty_event);
+ osalEventObjectInit(&canp->error_event);
+#if CAN_USE_SLEEP_MODE == TRUE
+ osalEventObjectInit(&canp->sleep_event);
+ osalEventObjectInit(&canp->wakeup_event);
+#endif
+}
+
+/**
+ * @brief Configures and activates the CAN peripheral.
+ * @note Activating the CAN bus can be a slow operation.
+ * @note Unlike other drivers it is not possible to restart the CAN
+ * driver without first stopping it using canStop().
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] config pointer to the @p CANConfig object. Depending on
+ * the implementation the value can be @p NULL.
+ *
+ * @api
+ */
+void canStart(CANDriver *canp, const CANConfig *config) {
+
+ osalDbgCheck(canp != NULL);
+
+ osalSysLock();
+ osalDbgAssert(canp->state == CAN_STOP, "invalid state");
+
+ /* Entering initialization mode. */
+ canp->state = CAN_STARTING;
+ canp->config = config;
+
+ /* Low level initialization, could be a slow process and sleeps could
+ be performed inside.*/
+ can_lld_start(canp);
+
+ /* The driver finally goes into the ready state.*/
+ canp->state = CAN_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the CAN peripheral.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @api
+ */
+void canStop(CANDriver *canp) {
+
+ osalDbgCheck(canp != NULL);
+
+ osalSysLock();
+ osalDbgAssert((canp->state == CAN_STOP) || (canp->state == CAN_READY),
+ "invalid state");
+
+ /* The low level driver is stopped.*/
+ can_lld_stop(canp);
+ canp->config = NULL;
+ canp->state = CAN_STOP;
+
+ /* Threads waiting on CAN APIs are notified that the driver has been
+ stopped in order to not have stuck threads.*/
+ osalThreadDequeueAllI(&canp->rxqueue, MSG_RESET);
+ osalThreadDequeueAllI(&canp->txqueue, MSG_RESET);
+ osalOsRescheduleS();
+ osalSysUnlock();
+}
+
+/**
+ * @brief Can frame transmission attempt.
+ * @details The specified frame is queued for transmission, if the hardware
+ * queue is full then the function fails.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ * @param[in] ctfp pointer to the CAN frame to be transmitted
+ * @return The operation result.
+ * @retval false Frame transmitted.
+ * @retval true Mailbox full.
+ *
+ * @iclass
+ */
+bool canTryTransmitI(CANDriver *canp,
+ canmbx_t mailbox,
+ const CANTxFrame *ctfp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck((canp != NULL) && (ctfp != NULL) &&
+ (mailbox <= (canmbx_t)CAN_TX_MAILBOXES));
+ osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+ "invalid state");
+
+ /* If the RX mailbox is full then the function fails.*/
+ if (!can_lld_is_tx_empty(canp, mailbox)) {
+ return true;
+ }
+
+ /* Transmitting frame.*/
+ can_lld_transmit(canp, mailbox, ctfp);
+
+ return false;
+}
+
+/**
+ * @brief Can frame receive attempt.
+ * @details The function tries to fetch a frame from a mailbox.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ * @param[out] crfp pointer to the buffer where the CAN frame is copied
+ * @return The operation result.
+ * @retval false Frame fetched.
+ * @retval true Mailbox empty.
+ *
+ * @iclass
+ */
+bool canTryReceiveI(CANDriver *canp,
+ canmbx_t mailbox,
+ CANRxFrame *crfp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck((canp != NULL) && (crfp != NULL) &&
+ (mailbox <= (canmbx_t)CAN_RX_MAILBOXES));
+ osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+ "invalid state");
+
+ /* If the RX mailbox is empty then the function fails.*/
+ if (!can_lld_is_rx_nonempty(canp, mailbox)) {
+ return true;
+ }
+
+ /* Fetching the frame.*/
+ can_lld_receive(canp, mailbox, crfp);
+
+ return false;
+}
+
+/**
+ * @brief Can frame transmission.
+ * @details The specified frame is queued for transmission, if the hardware
+ * queue is full then the invoking thread is queued.
+ * @note Trying to transmit while in sleep mode simply enqueues the thread.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ * @param[in] ctfp pointer to the CAN frame to be transmitted
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation result.
+ * @retval MSG_OK the frame has been queued for transmission.
+ * @retval MSG_TIMEOUT The operation has timed out.
+ * @retval MSG_RESET The driver has been stopped while waiting.
+ *
+ * @api
+ */
+msg_t canTransmitTimeout(CANDriver *canp,
+ canmbx_t mailbox,
+ const CANTxFrame *ctfp,
+ systime_t timeout) {
+
+ osalDbgCheck((canp != NULL) && (ctfp != NULL) &&
+ (mailbox <= (canmbx_t)CAN_TX_MAILBOXES));
+
+ osalSysLock();
+ osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+ "invalid state");
+
+ /*lint -save -e9007 [13.5] Right side is supposed to be pure.*/
+ while ((canp->state == CAN_SLEEP) || !can_lld_is_tx_empty(canp, mailbox)) {
+ /*lint -restore*/
+ msg_t msg = osalThreadEnqueueTimeoutS(&canp->txqueue, timeout);
+ if (msg != MSG_OK) {
+ osalSysUnlock();
+ return msg;
+ }
+ }
+ can_lld_transmit(canp, mailbox, ctfp);
+ osalSysUnlock();
+ return MSG_OK;
+}
+
+/**
+ * @brief Can frame receive.
+ * @details The function waits until a frame is received.
+ * @note Trying to receive while in sleep mode simply enqueues the thread.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ * @param[out] crfp pointer to the buffer where the CAN frame is copied
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout (useful in an
+ * event driven scenario where a thread never blocks
+ * for I/O).
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation result.
+ * @retval MSG_OK a frame has been received and placed in the buffer.
+ * @retval MSG_TIMEOUT The operation has timed out.
+ * @retval MSG_RESET The driver has been stopped while waiting.
+ *
+ * @api
+ */
+msg_t canReceiveTimeout(CANDriver *canp,
+ canmbx_t mailbox,
+ CANRxFrame *crfp,
+ systime_t timeout) {
+
+ osalDbgCheck((canp != NULL) && (crfp != NULL) &&
+ (mailbox <= (canmbx_t)CAN_RX_MAILBOXES));
+
+ osalSysLock();
+ osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+ "invalid state");
+
+ /*lint -save -e9007 [13.5] Right side is supposed to be pure.*/
+ while ((canp->state == CAN_SLEEP) || !can_lld_is_rx_nonempty(canp, mailbox)) {
+ /*lint -restore*/
+ msg_t msg = osalThreadEnqueueTimeoutS(&canp->rxqueue, timeout);
+ if (msg != MSG_OK) {
+ osalSysUnlock();
+ return msg;
+ }
+ }
+ can_lld_receive(canp, mailbox, crfp);
+ osalSysUnlock();
+ return MSG_OK;
+}
+
+#if (CAN_USE_SLEEP_MODE == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Enters the sleep mode.
+ * @details This function puts the CAN driver in sleep mode and broadcasts
+ * the @p sleep_event event source.
+ * @pre In order to use this function the option @p CAN_USE_SLEEP_MODE must
+ * be enabled and the @p CAN_SUPPORTS_SLEEP mode must be supported
+ * by the low level driver.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @api
+ */
+void canSleep(CANDriver *canp) {
+
+ osalDbgCheck(canp != NULL);
+
+ osalSysLock();
+ osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+ "invalid state");
+ if (canp->state == CAN_READY) {
+ can_lld_sleep(canp);
+ canp->state = CAN_SLEEP;
+ osalEventBroadcastFlagsI(&canp->sleep_event, (eventflags_t)0);
+ osalOsRescheduleS();
+ }
+ osalSysUnlock();
+}
+
+/**
+ * @brief Enforces leaving the sleep mode.
+ * @note The sleep mode is supposed to be usually exited automatically by
+ * an hardware event.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ */
+void canWakeup(CANDriver *canp) {
+
+ osalDbgCheck(canp != NULL);
+
+ osalSysLock();
+ osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+ "invalid state");
+ if (canp->state == CAN_SLEEP) {
+ can_lld_wakeup(canp);
+ canp->state = CAN_READY;
+ osalEventBroadcastFlagsI(&canp->wakeup_event, (eventflags_t)0);
+ osalOsRescheduleS();
+ }
+ osalSysUnlock();
+}
+#endif /* CAN_USE_SLEEP_MODE == TRUE */
+
+#endif /* HAL_USE_CAN == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_dac.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_dac.c
new file mode 100644
index 0000000000..a2a3c53ee1
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_dac.c
@@ -0,0 +1,350 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_dac.c
+ * @brief DAC Driver code.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief DAC Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void dacInit(void) {
+
+ dac_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p DACDriver structure.
+ *
+ * @param[out] dacp pointer to the @p DACDriver object
+ *
+ * @init
+ */
+void dacObjectInit(DACDriver *dacp) {
+
+ dacp->state = DAC_STOP;
+ dacp->config = NULL;
+#if DAC_USE_WAIT
+ dacp->thread = NULL;
+#endif
+#if DAC_USE_MUTUAL_EXCLUSION
+ osalMutexObjectInit(&dacp->mutex);
+#endif
+#if defined(DAC_DRIVER_EXT_INIT_HOOK)
+ DAC_DRIVER_EXT_INIT_HOOK(dacp);
+#endif
+}
+
+/**
+ * @brief Configures and activates the DAC peripheral.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] config pointer to the @p DACConfig object, it can be
+ * @p NULL if the low level driver implementation
+ * supports a default configuration
+ *
+ * @api
+ */
+void dacStart(DACDriver *dacp, const DACConfig *config) {
+
+ osalDbgCheck(dacp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((dacp->state == DAC_STOP) || (dacp->state == DAC_READY),
+ "invalid state");
+
+ dacp->config = config;
+ dac_lld_start(dacp);
+ dacp->state = DAC_READY;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the DAC peripheral.
+ * @note Deactivating the peripheral also enforces a release of the slave
+ * select line.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @api
+ */
+void dacStop(DACDriver *dacp) {
+
+ osalDbgCheck(dacp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((dacp->state == DAC_STOP) || (dacp->state == DAC_READY),
+ "invalid state");
+
+ dac_lld_stop(dacp);
+ dacp->config = NULL;
+ dacp->state = DAC_STOP;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Outputs a value directly on a DAC channel.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] channel DAC channel number
+ * @param[in] sample value to be output
+ *
+ * @xclass
+ */
+void dacPutChannelX(DACDriver *dacp, dacchannel_t channel, dacsample_t sample) {
+
+ osalDbgCheck(channel < DAC_MAX_CHANNELS);
+ osalDbgAssert(dacp->state == DAC_READY, "invalid state");
+
+ dac_lld_put_channel(dacp, channel, sample);
+}
+
+/**
+ * @brief Starts a DAC conversion.
+ * @details Starts an asynchronous conversion operation.
+ * @note The buffer is organized as a matrix of M*N elements where M is the
+ * channels number configured into the conversion group and N is the
+ * buffer depth. The samples are sequentially written into the buffer
+ * with no gaps.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] grpp pointer to a @p DACConversionGroup object
+ * @param[in] samples pointer to the samples buffer
+ * @param[in] depth buffer depth (matrix rows number). The buffer depth
+ * must be one or an even number.
+ *
+ * @api
+ */
+void dacStartConversion(DACDriver *dacp,
+ const DACConversionGroup *grpp,
+ dacsample_t *samples,
+ size_t depth) {
+
+ osalSysLock();
+ dacStartConversionI(dacp, grpp, samples, depth);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Starts a DAC conversion.
+ * @details Starts an asynchronous conversion operation.
+ * @post The callbacks associated to the conversion group will be invoked
+ * on buffer fill and error events.
+ * @note The buffer is organized as a matrix of M*N elements where M is the
+ * channels number configured into the conversion group and N is the
+ * buffer depth. The samples are sequentially written into the buffer
+ * with no gaps.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] grpp pointer to a @p DACConversionGroup object
+ * @param[in] samples pointer to the samples buffer
+ * @param[in] depth buffer depth (matrix rows number). The buffer depth
+ * must be one or an even number.
+ *
+ * @iclass
+ */
+void dacStartConversionI(DACDriver *dacp,
+ const DACConversionGroup *grpp,
+ dacsample_t *samples,
+ size_t depth) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck((dacp != NULL) && (grpp != NULL) && (samples != NULL) &&
+ ((depth == 1) || ((depth & 1) == 0)));
+ osalDbgAssert((dacp->state == DAC_READY) ||
+ (dacp->state == DAC_COMPLETE) ||
+ (dacp->state == DAC_ERROR),
+ "not ready");
+
+ dacp->samples = samples;
+ dacp->depth = depth;
+ dacp->grpp = grpp;
+ dacp->state = DAC_ACTIVE;
+ dac_lld_start_conversion(dacp);
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ * @details This function stops the currently ongoing conversion and returns
+ * the driver in the @p DAC_READY state. If there was no conversion
+ * being processed then the function does nothing.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @api
+ */
+void dacStopConversion(DACDriver *dacp) {
+
+ osalDbgCheck(dacp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((dacp->state == DAC_READY) ||
+ (dacp->state == DAC_ACTIVE),
+ "invalid state");
+
+ if (dacp->state != DAC_READY) {
+ dac_lld_stop_conversion(dacp);
+ dacp->grpp = NULL;
+ dacp->state = DAC_READY;
+ _dac_reset_s(dacp);
+ }
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ * @details This function stops the currently ongoing conversion and returns
+ * the driver in the @p DAC_READY state. If there was no conversion
+ * being processed then the function does nothing.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @iclass
+ */
+void dacStopConversionI(DACDriver *dacp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dacp != NULL);
+ osalDbgAssert((dacp->state == DAC_READY) ||
+ (dacp->state == DAC_ACTIVE) ||
+ (dacp->state == DAC_COMPLETE),
+ "invalid state");
+
+ if (dacp->state != DAC_READY) {
+ dac_lld_stop_conversion(dacp);
+ dacp->grpp = NULL;
+ dacp->state = DAC_READY;
+ _dac_reset_i(dacp);
+ }
+}
+
+#if (DAC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Performs a DAC conversion.
+ * @details Performs a synchronous conversion operation.
+ * @note The buffer is organized as a matrix of M*N elements where M is the
+ * channels number configured into the conversion group and N is the
+ * buffer depth. The samples are sequentially written into the buffer
+ * with no gaps.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] grpp pointer to a @p DACConversionGroup object
+ * @param[out] samples pointer to the samples buffer
+ * @param[in] depth buffer depth (matrix rows number). The buffer depth
+ * must be one or an even number.
+ * @return The operation result.
+ * @retval MSG_OK Conversion finished.
+ * @retval MSG_RESET The conversion has been stopped using
+ * @p acdStopConversion() or @p acdStopConversionI(),
+ * the result buffer may contain incorrect data.
+ * @retval MSG_TIMEOUT The conversion has been stopped because an hardware
+ * error.
+ *
+ * @api
+ */
+msg_t dacConvert(DACDriver *dacp,
+ const DACConversionGroup *grpp,
+ dacsample_t *samples,
+ size_t depth) {
+ msg_t msg;
+
+ osalSysLock();
+
+ dacStartConversionI(dacp, grpp, samples, depth);
+ msg = osalThreadSuspendS(&dacp->thread);
+
+ osalSysUnlock();
+ return msg;
+}
+#endif /* DAC_USE_WAIT == TRUE */
+
+#if (DAC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Gains exclusive access to the DAC bus.
+ * @details This function tries to gain ownership to the DAC bus, if the bus
+ * is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option @p DAC_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @api
+ */
+void dacAcquireBus(DACDriver *dacp) {
+
+ osalDbgCheck(dacp != NULL);
+
+ osalMutexLock(&dacp->mutex);
+}
+
+/**
+ * @brief Releases exclusive access to the DAC bus.
+ * @pre In order to use this function the option @p DAC_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @api
+ */
+void dacReleaseBus(DACDriver *dacp) {
+
+ osalDbgCheck(dacp != NULL);
+
+ osalMutexUnlock(&dacp->mutex);
+}
+#endif /* DAC_USE_MUTUAL_EXCLUSION == TRUE */
+
+#endif /* HAL_USE_DAC == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/ext.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_ext.c
similarity index 60%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/ext.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_ext.c
index e45ed2134d..31bfa3c740 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/ext.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_ext.c
@@ -1,42 +1,30 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file ext.c
+ * @file hal_ext.c
* @brief EXT Driver code.
*
* @addtogroup EXT
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_EXT || defined(__DOXYGEN__)
+#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -95,15 +83,15 @@ void extObjectInit(EXTDriver *extp) {
*/
void extStart(EXTDriver *extp, const EXTConfig *config) {
- chDbgCheck((extp != NULL) && (config != NULL), "extStart");
+ osalDbgCheck((extp != NULL) && (config != NULL));
- chSysLock();
- chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE),
- "extStart(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE),
+ "invalid state");
extp->config = config;
ext_lld_start(extp);
extp->state = EXT_ACTIVE;
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -115,14 +103,18 @@ void extStart(EXTDriver *extp, const EXTConfig *config) {
*/
void extStop(EXTDriver *extp) {
- chDbgCheck(extp != NULL, "extStop");
+ osalDbgCheck(extp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE),
+ "invalid state");
- chSysLock();
- chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE),
- "extStop(), #1", "invalid state");
ext_lld_stop(extp);
- extp->state = EXT_STOP;
- chSysUnlock();
+ extp->config = NULL;
+ extp->state = EXT_STOP;
+
+ osalSysUnlock();
}
/**
@@ -136,16 +128,15 @@ void extStop(EXTDriver *extp) {
*/
void extChannelEnable(EXTDriver *extp, expchannel_t channel) {
- chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS),
- "extChannelEnable");
+ osalDbgCheck((extp != NULL) && (channel < (expchannel_t)EXT_MAX_CHANNELS));
- chSysLock();
- chDbgAssert((extp->state == EXT_ACTIVE) &&
- ((extp->config->channels[channel].mode &
- EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED),
- "extChannelEnable(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert((extp->state == EXT_ACTIVE) &&
+ ((extp->config->channels[channel].mode &
+ EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED),
+ "invalid state");
extChannelEnableI(extp, channel);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -159,16 +150,15 @@ void extChannelEnable(EXTDriver *extp, expchannel_t channel) {
*/
void extChannelDisable(EXTDriver *extp, expchannel_t channel) {
- chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS),
- "extChannelDisable");
+ osalDbgCheck((extp != NULL) && (channel < (expchannel_t)EXT_MAX_CHANNELS));
- chSysLock();
- chDbgAssert((extp->state == EXT_ACTIVE) &&
- ((extp->config->channels[channel].mode &
- EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED),
- "extChannelDisable(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert((extp->state == EXT_ACTIVE) &&
+ ((extp->config->channels[channel].mode &
+ EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED),
+ "invalid state");
extChannelDisableI(extp, channel);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -193,22 +183,24 @@ void extSetChannelModeI(EXTDriver *extp,
const EXTChannelConfig *extcp) {
EXTChannelConfig *oldcp;
- chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS) &&
- (extcp != NULL), "extSetChannelModeI");
+ osalDbgCheck((extp != NULL) &&
+ (channel < (expchannel_t)EXT_MAX_CHANNELS) &&
+ (extcp != NULL));
- chDbgAssert(extp->state == EXT_ACTIVE,
- "extSetChannelModeI(), #1", "invalid state");
+ osalDbgAssert(extp->state == EXT_ACTIVE, "invalid state");
/* Note that here the access is enforced as non-const, known access
violation.*/
+ /*lint -save -e9005 [11.8] Known issue, the driver needs rework here.*/
oldcp = (EXTChannelConfig *)&extp->config->channels[channel];
+ /*lint -restore*/
- /* Overwiting the old channels configuration then the channel is reconfigured
- by the low level driver.*/
+ /* Overwriting the old channels configuration then the channel is
+ reconfigured by the low level driver.*/
*oldcp = *extcp;
ext_lld_channel_enable(extp, channel);
}
-#endif /* HAL_USE_EXT */
+#endif /* HAL_USE_EXT == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/gpt.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_gpt.c
similarity index 63%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/gpt.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_gpt.c
index e9a3c0f21b..3181781d7c 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/gpt.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_gpt.c
@@ -1,42 +1,30 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file gpt.c
+ * @file hal_gpt.c
* @brief GPT Driver code.
*
* @addtogroup GPT
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_GPT || defined(__DOXYGEN__)
+#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -93,15 +81,15 @@ void gptObjectInit(GPTDriver *gptp) {
*/
void gptStart(GPTDriver *gptp, const GPTConfig *config) {
- chDbgCheck((gptp != NULL) && (config != NULL), "gptStart");
+ osalDbgCheck((gptp != NULL) && (config != NULL));
- chSysLock();
- chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY),
- "gptStart(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY),
+ "invalid state");
gptp->config = config;
gpt_lld_start(gptp);
gptp->state = GPT_READY;
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -113,22 +101,24 @@ void gptStart(GPTDriver *gptp, const GPTConfig *config) {
*/
void gptStop(GPTDriver *gptp) {
- chDbgCheck(gptp != NULL, "gptStop");
+ osalDbgCheck(gptp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY),
+ "invalid state");
- chSysLock();
- chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY),
- "gptStop(), #1", "invalid state");
gpt_lld_stop(gptp);
- gptp->state = GPT_STOP;
- chSysUnlock();
+ gptp->config = NULL;
+ gptp->state = GPT_STOP;
+
+ osalSysUnlock();
}
/**
* @brief Changes the interval of GPT peripheral.
* @details This function changes the interval of a running GPT unit.
- * @pre The GPT unit must have been activated using @p gptStart().
- * @pre The GPT unit must have been running in continuous mode using
- * @p gptStartContinuous().
+ * @pre The GPT unit must be running in continuous mode.
* @post The GPT unit interval is changed to the new value.
*
* @param[in] gptp pointer to a @p GPTDriver object
@@ -138,13 +128,13 @@ void gptStop(GPTDriver *gptp) {
*/
void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval) {
- chDbgCheck(gptp != NULL, "gptChangeInterval");
+ osalDbgCheck(gptp != NULL);
- chSysLock();
- chDbgAssert(gptp->state == GPT_CONTINUOUS,
- "gptChangeInterval(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert(gptp->state == GPT_CONTINUOUS,
+ "invalid state");
gptChangeIntervalI(gptp, interval);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -157,9 +147,9 @@ void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval) {
*/
void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval) {
- chSysLock();
+ osalSysLock();
gptStartContinuousI(gptp, interval);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -172,10 +162,10 @@ void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval) {
*/
void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval) {
- chDbgCheckClassI();
- chDbgCheck(gptp != NULL, "gptStartContinuousI");
- chDbgAssert(gptp->state == GPT_READY,
- "gptStartContinuousI(), #1", "invalid state");
+ osalDbgCheckClassI();
+ osalDbgCheck(gptp != NULL);
+ osalDbgAssert(gptp->state == GPT_READY,
+ "invalid state");
gptp->state = GPT_CONTINUOUS;
gpt_lld_start_timer(gptp, interval);
@@ -191,9 +181,9 @@ void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval) {
*/
void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval) {
- chSysLock();
+ osalSysLock();
gptStartOneShotI(gptp, interval);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -206,10 +196,11 @@ void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval) {
*/
void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval) {
- chDbgCheckClassI();
- chDbgCheck(gptp != NULL, "gptStartOneShotI");
- chDbgAssert(gptp->state == GPT_READY,
- "gptStartOneShotI(), #1", "invalid state");
+ osalDbgCheckClassI();
+ osalDbgCheck(gptp != NULL);
+ osalDbgCheck(gptp->config->callback != NULL);
+ osalDbgAssert(gptp->state == GPT_READY,
+ "invalid state");
gptp->state = GPT_ONESHOT;
gpt_lld_start_timer(gptp, interval);
@@ -224,9 +215,9 @@ void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval) {
*/
void gptStopTimer(GPTDriver *gptp) {
- chSysLock();
+ osalSysLock();
gptStopTimerI(gptp);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -238,11 +229,11 @@ void gptStopTimer(GPTDriver *gptp) {
*/
void gptStopTimerI(GPTDriver *gptp) {
- chDbgCheckClassI();
- chDbgCheck(gptp != NULL, "gptStopTimerI");
- chDbgAssert((gptp->state == GPT_READY) || (gptp->state == GPT_CONTINUOUS) ||
- (gptp->state == GPT_ONESHOT),
- "gptStopTimerI(), #1", "invalid state");
+ osalDbgCheckClassI();
+ osalDbgCheck(gptp != NULL);
+ osalDbgAssert((gptp->state == GPT_READY) || (gptp->state == GPT_CONTINUOUS) ||
+ (gptp->state == GPT_ONESHOT),
+ "invalid state");
gptp->state = GPT_READY;
gpt_lld_stop_timer(gptp);
@@ -262,14 +253,14 @@ void gptStopTimerI(GPTDriver *gptp) {
*/
void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval) {
- chDbgAssert(gptp->state == GPT_READY,
- "gptPolledDelay(), #1", "invalid state");
+ osalDbgAssert(gptp->state == GPT_READY,
+ "invalid state");
gptp->state = GPT_ONESHOT;
gpt_lld_polled_delay(gptp, interval);
gptp->state = GPT_READY;
}
-#endif /* HAL_USE_GPT */
+#endif /* HAL_USE_GPT == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/i2c.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_i2c.c
similarity index 63%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/i2c.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_i2c.c
index 5f6410222b..c99eb02f28 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/i2c.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_i2c.c
@@ -1,28 +1,17 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Uladzimir Pylinsky
@@ -30,16 +19,15 @@
*/
/**
- * @file i2c.c
+ * @file hal_i2c.c
* @brief I2C Driver code.
*
* @addtogroup I2C
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_I2C || defined(__DOXYGEN__)
+#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -69,6 +57,7 @@
* @init
*/
void i2cInit(void) {
+
i2c_lld_init();
}
@@ -84,13 +73,9 @@ void i2cObjectInit(I2CDriver *i2cp) {
i2cp->state = I2C_STOP;
i2cp->config = NULL;
-#if I2C_USE_MUTUAL_EXCLUSION
-#if CH_USE_MUTEXES
- chMtxInit(&i2cp->mutex);
-#else
- chSemInit(&i2cp->semaphore, 1);
-#endif /* CH_USE_MUTEXES */
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if I2C_USE_MUTUAL_EXCLUSION == TRUE
+ osalMutexObjectInit(&i2cp->mutex);
+#endif
#if defined(I2C_DRIVER_EXT_INIT_HOOK)
I2C_DRIVER_EXT_INIT_HOOK(i2cp);
@@ -107,17 +92,15 @@ void i2cObjectInit(I2CDriver *i2cp) {
*/
void i2cStart(I2CDriver *i2cp, const I2CConfig *config) {
- chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart");
- chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) ||
- (i2cp->state == I2C_LOCKED),
- "i2cStart(), #1",
- "invalid state");
+ osalDbgCheck((i2cp != NULL) && (config != NULL));
+ osalDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) ||
+ (i2cp->state == I2C_LOCKED), "invalid state");
- chSysLock();
+ osalSysLock();
i2cp->config = config;
i2c_lld_start(i2cp);
i2cp->state = I2C_READY;
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -129,16 +112,18 @@ void i2cStart(I2CDriver *i2cp, const I2CConfig *config) {
*/
void i2cStop(I2CDriver *i2cp) {
- chDbgCheck(i2cp != NULL, "i2cStop");
- chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) ||
- (i2cp->state == I2C_LOCKED),
- "i2cStop(), #1",
- "invalid state");
+ osalDbgCheck(i2cp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) ||
+ (i2cp->state == I2C_LOCKED), "invalid state");
- chSysLock();
i2c_lld_stop(i2cp);
- i2cp->state = I2C_STOP;
- chSysUnlock();
+ i2cp->config = NULL;
+ i2cp->state = I2C_STOP;
+
+ osalSysUnlock();
}
/**
@@ -151,7 +136,7 @@ void i2cStop(I2CDriver *i2cp) {
*/
i2cflags_t i2cGetErrors(I2CDriver *i2cp) {
- chDbgCheck(i2cp != NULL, "i2cGetErrors");
+ osalDbgCheck(i2cp != NULL);
return i2c_lld_get_errors(i2cp);
}
@@ -175,10 +160,10 @@ i2cflags_t i2cGetErrors(I2CDriver *i2cp) {
* .
*
* @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT if a timeout occurred before operation end.
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end.
*
* @api
*/
@@ -191,25 +176,25 @@ msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp,
systime_t timeout) {
msg_t rdymsg;
- chDbgCheck((i2cp != NULL) && (addr != 0) &&
- (txbytes > 0) && (txbuf != NULL) &&
- ((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))) &&
- (timeout != TIME_IMMEDIATE),
- "i2cMasterTransmitTimeout");
+ osalDbgCheck((i2cp != NULL) && (addr != 0U) &&
+ (txbytes > 0U) && (txbuf != NULL) &&
+ ((rxbytes == 0U) || ((rxbytes > 0U) && (rxbuf != NULL))) &&
+ (timeout != TIME_IMMEDIATE));
- chDbgAssert(i2cp->state == I2C_READY,
- "i2cMasterTransmitTimeout(), #1", "not ready");
+ osalDbgAssert(i2cp->state == I2C_READY, "not ready");
- chSysLock();
- i2cp->errors = I2CD_NO_ERROR;
+ osalSysLock();
+ i2cp->errors = I2C_NO_ERROR;
i2cp->state = I2C_ACTIVE_TX;
rdymsg = i2c_lld_master_transmit_timeout(i2cp, addr, txbuf, txbytes,
rxbuf, rxbytes, timeout);
- if (rdymsg == RDY_TIMEOUT)
+ if (rdymsg == MSG_TIMEOUT) {
i2cp->state = I2C_LOCKED;
- else
+ }
+ else {
i2cp->state = I2C_READY;
- chSysUnlock();
+ }
+ osalSysUnlock();
return rdymsg;
}
@@ -226,10 +211,10 @@ msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp,
* .
*
* @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT if a timeout occurred before operation end.
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end.
*
* @api
*/
@@ -241,27 +226,27 @@ msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp,
msg_t rdymsg;
- chDbgCheck((i2cp != NULL) && (addr != 0) &&
- (rxbytes > 0) && (rxbuf != NULL) &&
- (timeout != TIME_IMMEDIATE),
- "i2cMasterReceiveTimeout");
+ osalDbgCheck((i2cp != NULL) && (addr != 0U) &&
+ (rxbytes > 0U) && (rxbuf != NULL) &&
+ (timeout != TIME_IMMEDIATE));
- chDbgAssert(i2cp->state == I2C_READY,
- "i2cMasterReceive(), #1", "not ready");
+ osalDbgAssert(i2cp->state == I2C_READY, "not ready");
- chSysLock();
- i2cp->errors = I2CD_NO_ERROR;
+ osalSysLock();
+ i2cp->errors = I2C_NO_ERROR;
i2cp->state = I2C_ACTIVE_RX;
rdymsg = i2c_lld_master_receive_timeout(i2cp, addr, rxbuf, rxbytes, timeout);
- if (rdymsg == RDY_TIMEOUT)
+ if (rdymsg == MSG_TIMEOUT) {
i2cp->state = I2C_LOCKED;
- else
+ }
+ else {
i2cp->state = I2C_READY;
- chSysUnlock();
+ }
+ osalSysUnlock();
return rdymsg;
}
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if (I2C_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
/**
* @brief Gains exclusive access to the I2C bus.
* @details This function tries to gain ownership to the I2C bus, if the bus
@@ -275,13 +260,9 @@ msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp,
*/
void i2cAcquireBus(I2CDriver *i2cp) {
- chDbgCheck(i2cp != NULL, "i2cAcquireBus");
+ osalDbgCheck(i2cp != NULL);
-#if CH_USE_MUTEXES
- chMtxLock(&i2cp->mutex);
-#elif CH_USE_SEMAPHORES
- chSemWait(&i2cp->semaphore);
-#endif
+ osalMutexLock(&i2cp->mutex);
}
/**
@@ -295,16 +276,12 @@ void i2cAcquireBus(I2CDriver *i2cp) {
*/
void i2cReleaseBus(I2CDriver *i2cp) {
- chDbgCheck(i2cp != NULL, "i2cReleaseBus");
+ osalDbgCheck(i2cp != NULL);
-#if CH_USE_MUTEXES
- chMtxUnlock();
-#elif CH_USE_SEMAPHORES
- chSemSignal(&i2cp->semaphore);
-#endif
+ osalMutexUnlock(&i2cp->mutex);
}
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#endif /* I2C_USE_MUTUAL_EXCLUSION == TRUE */
-#endif /* HAL_USE_I2C */
+#endif /* HAL_USE_I2C == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_i2s.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_i2s.c
new file mode 100644
index 0000000000..0f0bdacbad
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_i2s.c
@@ -0,0 +1,159 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_i2s.c
+ * @brief I2S Driver code.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief I2S Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void i2sInit(void) {
+
+ i2s_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p I2SDriver structure.
+ *
+ * @param[out] i2sp pointer to the @p I2SDriver object
+ *
+ * @init
+ */
+void i2sObjectInit(I2SDriver *i2sp) {
+
+ i2sp->state = I2S_STOP;
+ i2sp->config = NULL;
+}
+
+/**
+ * @brief Configures and activates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] config pointer to the @p I2SConfig object
+ *
+ * @api
+ */
+void i2sStart(I2SDriver *i2sp, const I2SConfig *config) {
+
+ osalDbgCheck((i2sp != NULL) && (config != NULL));
+
+ osalSysLock();
+ osalDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY),
+ "invalid state");
+ i2sp->config = config;
+ i2s_lld_start(i2sp);
+ i2sp->state = I2S_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @api
+ */
+void i2sStop(I2SDriver *i2sp) {
+
+ osalDbgCheck(i2sp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY),
+ "invalid state");
+
+ i2s_lld_stop(i2sp);
+ i2sp->config = NULL;
+ i2sp->state = I2S_STOP;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Starts a I2S data exchange.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @api
+ */
+void i2sStartExchange(I2SDriver *i2sp) {
+
+ osalDbgCheck(i2sp != NULL);
+
+ osalSysLock();
+ osalDbgAssert(i2sp->state == I2S_READY, "not ready");
+ i2sStartExchangeI(i2sp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ * was not active the function does nothing.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @api
+ */
+void i2sStopExchange(I2SDriver *i2sp) {
+
+ osalDbgCheck((i2sp != NULL));
+
+ osalSysLock();
+ osalDbgAssert((i2sp->state == I2S_READY) ||
+ (i2sp->state == I2S_ACTIVE) ||
+ (i2sp->state == I2S_COMPLETE),
+ "invalid state");
+ i2sStopExchangeI(i2sp);
+ osalSysUnlock();
+}
+
+#endif /* HAL_USE_I2S == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_icu.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_icu.c
new file mode 100644
index 0000000000..3d7f26e842
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_icu.c
@@ -0,0 +1,229 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_icu.c
+ * @brief ICU Driver code.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief ICU Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void icuInit(void) {
+
+ icu_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p ICUDriver structure.
+ *
+ * @param[out] icup pointer to the @p ICUDriver object
+ *
+ * @init
+ */
+void icuObjectInit(ICUDriver *icup) {
+
+ icup->state = ICU_STOP;
+ icup->config = NULL;
+}
+
+/**
+ * @brief Configures and activates the ICU peripheral.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @param[in] config pointer to the @p ICUConfig object
+ *
+ * @api
+ */
+void icuStart(ICUDriver *icup, const ICUConfig *config) {
+
+ osalDbgCheck((icup != NULL) && (config != NULL));
+
+ osalSysLock();
+ osalDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY),
+ "invalid state");
+ icup->config = config;
+ icu_lld_start(icup);
+ icup->state = ICU_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the ICU peripheral.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @api
+ */
+void icuStop(ICUDriver *icup) {
+
+ osalDbgCheck(icup != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY),
+ "invalid state");
+
+ icu_lld_stop(icup);
+ icup->config = NULL;
+ icup->state = ICU_STOP;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Starts the input capture.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @api
+ */
+void icuStartCapture(ICUDriver *icup) {
+
+ osalDbgCheck(icup != NULL);
+
+ osalSysLock();
+ osalDbgAssert(icup->state == ICU_READY, "invalid state");
+ icuStartCaptureI(icup);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Waits for a completed capture.
+ * @note The operation could be performed in polled mode depending on.
+ * @note In order to use this function notifications must be disabled.
+ * @pre The driver must be in @p ICU_WAITING or @p ICU_ACTIVE states.
+ * @post After the capture is available the driver is in @p ICU_ACTIVE
+ * state. If a capture fails then the driver is in @p ICU_WAITING
+ * state.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The capture status.
+ * @retval false if the capture is successful.
+ * @retval true if a timer overflow occurred.
+ *
+ * @api
+ */
+bool icuWaitCapture(ICUDriver *icup) {
+ bool result;
+
+ osalDbgCheck(icup != NULL);
+
+ osalSysLock();
+ osalDbgAssert((icup->state == ICU_WAITING) || (icup->state == ICU_ACTIVE),
+ "invalid state");
+ osalDbgAssert(icuAreNotificationsEnabledX(icup) == false,
+ "notifications enabled");
+ result = icu_lld_wait_capture(icup);
+ icup->state = result ? ICU_WAITING : ICU_ACTIVE;
+ osalSysUnlock();
+
+ return result;
+}
+
+/**
+ * @brief Stops the input capture.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @api
+ */
+void icuStopCapture(ICUDriver *icup) {
+
+ osalDbgCheck(icup != NULL);
+
+ osalSysLock();
+ osalDbgAssert((icup->state == ICU_READY) || (icup->state == ICU_WAITING) ||
+ (icup->state == ICU_ACTIVE),
+ "invalid state");
+ icuStopCaptureI(icup);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Enables notifications.
+ * @pre The ICU unit must have been activated using @p icuStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @api
+ */
+void icuEnableNotifications(ICUDriver *icup) {
+
+ osalDbgCheck(icup != NULL);
+
+ osalSysLock();
+ osalDbgAssert((icup->state == ICU_WAITING) || (icup->state == ICU_ACTIVE),
+ "invalid state");
+ icuEnableNotificationsI(icup);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disables notifications.
+ * @pre The ICU unit must have been activated using @p icuStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @api
+ */
+void icuDisableNotifications(ICUDriver *icup) {
+
+ osalDbgCheck(icup != NULL);
+
+ osalSysLock();
+ osalDbgAssert((icup->state == ICU_WAITING) || (icup->state == ICU_ACTIVE),
+ "invalid state");
+ icuDisableNotificationsI(icup);
+ osalSysUnlock();
+}
+
+#endif /* HAL_USE_ICU == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mac.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mac.c
similarity index 59%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mac.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mac.c
index 64d576845d..d2d94ff4d2 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mac.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mac.c
@@ -1,48 +1,36 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file mac.c
+ * @file hal_mac.c
* @brief MAC Driver code.
*
* @addtogroup MAC
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_MAC || defined(__DOXYGEN__)
+#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
-#if MAC_USE_ZERO_COPY && !MAC_SUPPORTS_ZERO_COPY
+#if (MAC_USE_ZERO_COPY == TRUE) && (MAC_SUPPORTS_ZERO_COPY == FALSE)
#error "MAC_USE_ZERO_COPY not supported by this implementation"
#endif
@@ -89,10 +77,10 @@ void macObjectInit(MACDriver *macp) {
macp->state = MAC_STOP;
macp->config = NULL;
- chSemInit(&macp->tdsem, 0);
- chSemInit(&macp->rdsem, 0);
-#if MAC_USE_EVENTS
- chEvtInit(&macp->rdevent);
+ osalThreadQueueObjectInit(&macp->tdqueue);
+ osalThreadQueueObjectInit(&macp->rdqueue);
+#if MAC_USE_EVENTS == TRUE
+ osalEventObjectInit(&macp->rdevent);
#endif
}
@@ -106,15 +94,15 @@ void macObjectInit(MACDriver *macp) {
*/
void macStart(MACDriver *macp, const MACConfig *config) {
- chDbgCheck((macp != NULL) && (config != NULL), "macStart");
+ osalDbgCheck((macp != NULL) && (config != NULL));
- chSysLock();
- chDbgAssert(macp->state == MAC_STOP,
- "macStart(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert(macp->state == MAC_STOP,
+ "invalid state");
macp->config = config;
mac_lld_start(macp);
macp->state = MAC_ACTIVE;
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -126,14 +114,18 @@ void macStart(MACDriver *macp, const MACConfig *config) {
*/
void macStop(MACDriver *macp) {
- chDbgCheck(macp != NULL, "macStop");
+ osalDbgCheck(macp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((macp->state == MAC_STOP) || (macp->state == MAC_ACTIVE),
+ "invalid state");
- chSysLock();
- chDbgAssert((macp->state == MAC_STOP) || (macp->state == MAC_ACTIVE),
- "macStop(), #1", "invalid state");
mac_lld_stop(macp);
- macp->state = MAC_STOP;
- chSysUnlock();
+ macp->config = NULL;
+ macp->state = MAC_STOP;
+
+ osalSysUnlock();
}
/**
@@ -144,38 +136,39 @@ void macStop(MACDriver *macp) {
*
* @param[in] macp pointer to the @p MACDriver object
* @param[out] tdp pointer to a @p MACTransmitDescriptor structure
- * @param[in] time the number of ticks before the operation timeouts,
+ * @param[in] timeout the number of ticks before the operation timeouts,
* the following special values are allowed:
* - @a TIME_IMMEDIATE immediate timeout.
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK the descriptor was obtained.
- * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized.
+ * @retval MSG_OK the descriptor was obtained.
+ * @retval MSG_TIMEOUT the operation timed out, descriptor not initialized.
*
* @api
*/
msg_t macWaitTransmitDescriptor(MACDriver *macp,
MACTransmitDescriptor *tdp,
- systime_t time) {
+ systime_t timeout) {
msg_t msg;
systime_t now;
- chDbgCheck((macp != NULL) && (tdp != NULL), "macWaitTransmitDescriptor");
- chDbgAssert(macp->state == MAC_ACTIVE, "macWaitTransmitDescriptor(), #1",
- "not active");
+ osalDbgCheck((macp != NULL) && (tdp != NULL));
+ osalDbgAssert(macp->state == MAC_ACTIVE, "not active");
- while (((msg = mac_lld_get_transmit_descriptor(macp, tdp)) != RDY_OK) &&
- (time > 0)) {
- chSysLock();
- now = chTimeNow();
- if ((msg = chSemWaitTimeoutS(&macp->tdsem, time)) == RDY_TIMEOUT) {
- chSysUnlock();
+ while (((msg = mac_lld_get_transmit_descriptor(macp, tdp)) != MSG_OK) &&
+ (timeout > (systime_t)0)) {
+ osalSysLock();
+ now = osalOsGetSystemTimeX();
+ msg = osalThreadEnqueueTimeoutS(&macp->tdqueue, timeout);
+ if (msg == MSG_TIMEOUT) {
+ osalSysUnlock();
break;
}
- if (time != TIME_INFINITE)
- time -= (chTimeNow() - now);
- chSysUnlock();
+ if (timeout != TIME_INFINITE) {
+ timeout -= (osalOsGetSystemTimeX() - now);
+ }
+ osalSysUnlock();
}
return msg;
}
@@ -190,7 +183,7 @@ msg_t macWaitTransmitDescriptor(MACDriver *macp,
*/
void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) {
- chDbgCheck((tdp != NULL), "macReleaseTransmitDescriptor");
+ osalDbgCheck(tdp != NULL);
mac_lld_release_transmit_descriptor(tdp);
}
@@ -203,38 +196,39 @@ void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) {
*
* @param[in] macp pointer to the @p MACDriver object
* @param[out] rdp pointer to a @p MACReceiveDescriptor structure
- * @param[in] time the number of ticks before the operation timeouts,
+ * @param[in] timeout the number of ticks before the operation timeouts,
* the following special values are allowed:
* - @a TIME_IMMEDIATE immediate timeout.
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK the descriptor was obtained.
- * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized.
+ * @retval MSG_OK the descriptor was obtained.
+ * @retval MSG_TIMEOUT the operation timed out, descriptor not initialized.
*
* @api
*/
msg_t macWaitReceiveDescriptor(MACDriver *macp,
MACReceiveDescriptor *rdp,
- systime_t time) {
+ systime_t timeout) {
msg_t msg;
systime_t now;
- chDbgCheck((macp != NULL) && (rdp != NULL), "macWaitReceiveDescriptor");
- chDbgAssert(macp->state == MAC_ACTIVE, "macWaitReceiveDescriptor(), #1",
- "not active");
+ osalDbgCheck((macp != NULL) && (rdp != NULL));
+ osalDbgAssert(macp->state == MAC_ACTIVE, "not active");
- while (((msg = mac_lld_get_receive_descriptor(macp, rdp)) != RDY_OK) &&
- (time > 0)) {
- chSysLock();
- now = chTimeNow();
- if ((msg = chSemWaitTimeoutS(&macp->rdsem, time)) == RDY_TIMEOUT) {
- chSysUnlock();
+ while (((msg = mac_lld_get_receive_descriptor(macp, rdp)) != MSG_OK) &&
+ (timeout > (systime_t)0)) {
+ osalSysLock();
+ now = osalOsGetSystemTimeX();
+ msg = osalThreadEnqueueTimeoutS(&macp->rdqueue, timeout);
+ if (msg == MSG_TIMEOUT) {
+ osalSysUnlock();
break;
}
- if (time != TIME_INFINITE)
- time -= (chTimeNow() - now);
- chSysUnlock();
+ if (timeout != TIME_INFINITE) {
+ timeout -= (osalOsGetSystemTimeX() - now);
+ }
+ osalSysUnlock();
}
return msg;
}
@@ -250,7 +244,7 @@ msg_t macWaitReceiveDescriptor(MACDriver *macp,
*/
void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) {
- chDbgCheck((rdp != NULL), "macReleaseReceiveDescriptor");
+ osalDbgCheck(rdp != NULL);
mac_lld_release_receive_descriptor(rdp);
}
@@ -260,20 +254,19 @@ void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) {
*
* @param[in] macp pointer to the @p MACDriver object
* @return The link status.
- * @retval TRUE if the link is active.
- * @retval FALSE if the link is down.
+ * @retval true if the link is active.
+ * @retval false if the link is down.
*
* @api
*/
-bool_t macPollLinkStatus(MACDriver *macp) {
+bool macPollLinkStatus(MACDriver *macp) {
- chDbgCheck((macp != NULL), "macPollLinkStatus");
- chDbgAssert(macp->state == MAC_ACTIVE, "macPollLinkStatus(), #1",
- "not active");
+ osalDbgCheck(macp != NULL);
+ osalDbgAssert(macp->state == MAC_ACTIVE, "not active");
return mac_lld_poll_link_status(macp);
}
-#endif /* HAL_USE_MAC */
+#endif /* HAL_USE_MAC == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mmc_spi.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mmc_spi.c
similarity index 65%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mmc_spi.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mmc_spi.c
index 19a2173ccb..9983083b8c 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mmc_spi.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mmc_spi.c
@@ -1,35 +1,24 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/*
Parts of this file have been contributed by Matthias Blaicher.
*/
/**
- * @file mmc_spi.c
+ * @file hal_mmc_spi.c
* @brief MMC over SPI driver code.
*
* @addtogroup MMC_SPI
@@ -38,10 +27,9 @@
#include
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+#if (HAL_USE_MMC_SPI == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -56,23 +44,23 @@
/*===========================================================================*/
/* Forward declarations required by mmc_vmt.*/
-static bool_t mmc_read(void *instance, uint32_t startblk,
+static bool mmc_read(void *instance, uint32_t startblk,
uint8_t *buffer, uint32_t n);
-static bool_t mmc_write(void *instance, uint32_t startblk,
+static bool mmc_write(void *instance, uint32_t startblk,
const uint8_t *buffer, uint32_t n);
/**
* @brief Virtual methods table.
*/
static const struct MMCDriverVMT mmc_vmt = {
- (bool_t (*)(void *))mmc_lld_is_card_inserted,
- (bool_t (*)(void *))mmc_lld_is_write_protected,
- (bool_t (*)(void *))mmcConnect,
- (bool_t (*)(void *))mmcDisconnect,
+ (bool (*)(void *))mmc_lld_is_card_inserted,
+ (bool (*)(void *))mmc_lld_is_write_protected,
+ (bool (*)(void *))mmcConnect,
+ (bool (*)(void *))mmcDisconnect,
mmc_read,
mmc_write,
- (bool_t (*)(void *))mmcSync,
- (bool_t (*)(void *, BlockDeviceInfo *))mmcGetInfo
+ (bool (*)(void *))mmcSync,
+ (bool (*)(void *, BlockDeviceInfo *))mmcGetInfo
};
/**
@@ -107,36 +95,46 @@ static const uint8_t crc7_lookup_table[256] = {
/* Driver local functions. */
/*===========================================================================*/
-static bool_t mmc_read(void *instance, uint32_t startblk,
+static bool mmc_read(void *instance, uint32_t startblk,
uint8_t *buffer, uint32_t n) {
- if (mmcStartSequentialRead((MMCDriver *)instance, startblk))
- return CH_FAILED;
- while (n > 0) {
- if (mmcSequentialRead((MMCDriver *)instance, buffer))
- return CH_FAILED;
+ if (mmcStartSequentialRead((MMCDriver *)instance, startblk)) {
+ return HAL_FAILED;
+ }
+
+ while (n > 0U) {
+ if (mmcSequentialRead((MMCDriver *)instance, buffer)) {
+ return HAL_FAILED;
+ }
buffer += MMCSD_BLOCK_SIZE;
n--;
}
- if (mmcStopSequentialRead((MMCDriver *)instance))
- return CH_FAILED;
- return CH_SUCCESS;
+
+ if (mmcStopSequentialRead((MMCDriver *)instance)) {
+ return HAL_FAILED;
+ }
+ return HAL_SUCCESS;
}
-static bool_t mmc_write(void *instance, uint32_t startblk,
+static bool mmc_write(void *instance, uint32_t startblk,
const uint8_t *buffer, uint32_t n) {
- if (mmcStartSequentialWrite((MMCDriver *)instance, startblk))
- return CH_FAILED;
- while (n > 0) {
- if (mmcSequentialWrite((MMCDriver *)instance, buffer))
- return CH_FAILED;
- buffer += MMCSD_BLOCK_SIZE;
- n--;
- }
- if (mmcStopSequentialWrite((MMCDriver *)instance))
- return CH_FAILED;
- return CH_SUCCESS;
+ if (mmcStartSequentialWrite((MMCDriver *)instance, startblk)) {
+ return HAL_FAILED;
+ }
+
+ while (n > 0U) {
+ if (mmcSequentialWrite((MMCDriver *)instance, buffer)) {
+ return HAL_FAILED;
+ }
+ buffer += MMCSD_BLOCK_SIZE;
+ n--;
+ }
+
+ if (mmcStopSequentialWrite((MMCDriver *)instance)) {
+ return HAL_FAILED;
+ }
+ return HAL_SUCCESS;
}
/**
@@ -149,8 +147,10 @@ static bool_t mmc_write(void *instance, uint32_t startblk,
*/
static uint8_t crc7(uint8_t crc, const uint8_t *buffer, size_t len) {
- while (len--)
+ while (len > 0U) {
crc = crc7_lookup_table[(crc << 1) ^ (*buffer++)];
+ len--;
+ }
return crc;
}
@@ -167,17 +167,19 @@ static void wait(MMCDriver *mmcp) {
for (i = 0; i < 16; i++) {
spiReceive(mmcp->config->spip, 1, buf);
- if (buf[0] == 0xFF)
+ if (buf[0] == 0xFFU) {
return;
+ }
}
/* Looks like it is a long wait.*/
- while (TRUE) {
+ while (true) {
spiReceive(mmcp->config->spip, 1, buf);
- if (buf[0] == 0xFF)
+ if (buf[0] == 0xFFU) {
break;
-#ifdef MMC_NICE_WAITING
+ }
+#if MMC_NICE_WAITING == TRUE
/* Trying to be nice with the other threads.*/
- chThdSleep(1);
+ osalThreadSleepMilliseconds(1);
#endif
}
}
@@ -197,13 +199,13 @@ static void send_hdr(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) {
/* Wait for the bus to become idle if a write operation was in progress.*/
wait(mmcp);
- buf[0] = 0x40 | cmd;
- buf[1] = arg >> 24;
- buf[2] = arg >> 16;
- buf[3] = arg >> 8;
- buf[4] = arg;
+ buf[0] = (uint8_t)0x40U | cmd;
+ buf[1] = (uint8_t)(arg >> 24U);
+ buf[2] = (uint8_t)(arg >> 16U);
+ buf[3] = (uint8_t)(arg >> 8U);
+ buf[4] = (uint8_t)arg;
/* Calculate CRC for command header, shift to right position, add stop bit.*/
- buf[5] = ((crc7(0, buf, 5) & 0x7F) << 1) | 0x01;
+ buf[5] = ((crc7(0, buf, 5U) & 0x7FU) << 1U) | 0x01U;
spiSend(mmcp->config->spip, 6, buf);
}
@@ -223,10 +225,11 @@ static uint8_t recvr1(MMCDriver *mmcp) {
for (i = 0; i < 9; i++) {
spiReceive(mmcp->config->spip, 1, r1);
- if (r1[0] != 0xFF)
+ if (r1[0] != 0xFFU) {
return r1[0];
+ }
}
- return 0xFF;
+ return 0xFFU;
}
/**
@@ -297,36 +300,37 @@ static uint8_t send_command_R3(MMCDriver *mmcp, uint8_t cmd, uint32_t arg,
* @brief Reads the CSD.
*
* @param[in] mmcp pointer to the @p MMCDriver object
- * @param[out] csd pointer to the CSD buffer
+ * @param[out] cmd command
+ * @param[out] cxd pointer to the CSD/CID buffer
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @notapi
*/
-static bool_t read_CxD(MMCDriver *mmcp, uint8_t cmd, uint32_t cxd[4]) {
+static bool read_CxD(MMCDriver *mmcp, uint8_t cmd, uint32_t cxd[4]) {
unsigned i;
uint8_t *bp, buf[16];
spiSelect(mmcp->config->spip);
send_hdr(mmcp, cmd, 0);
- if (recvr1(mmcp) != 0x00) {
+ if (recvr1(mmcp) != 0x00U) {
spiUnselect(mmcp->config->spip);
- return CH_FAILED;
+ return HAL_FAILED;
}
/* Wait for data availability.*/
- for (i = 0; i < MMC_WAIT_DATA; i++) {
+ for (i = 0U; i < MMC_WAIT_DATA; i++) {
spiReceive(mmcp->config->spip, 1, buf);
- if (buf[0] == 0xFE) {
+ if (buf[0] == 0xFEU) {
uint32_t *wp;
spiReceive(mmcp->config->spip, 16, buf);
bp = buf;
for (wp = &cxd[3]; wp >= cxd; wp--) {
- *wp = ((uint32_t)bp[0] << 24) | ((uint32_t)bp[1] << 16) |
- ((uint32_t)bp[2] << 8) | (uint32_t)bp[3];
+ *wp = ((uint32_t)bp[0] << 24U) | ((uint32_t)bp[1] << 16U) |
+ ((uint32_t)bp[2] << 8U) | (uint32_t)bp[3];
bp += 4;
}
@@ -334,10 +338,10 @@ static bool_t read_CxD(MMCDriver *mmcp, uint8_t cmd, uint32_t cxd[4]) {
spiIgnore(mmcp->config->spip, 2);
spiUnselect(mmcp->config->spip);
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
}
- return CH_FAILED;
+ return HAL_FAILED;
}
/**
@@ -351,12 +355,14 @@ static void sync(MMCDriver *mmcp) {
uint8_t buf[1];
spiSelect(mmcp->config->spip);
- while (TRUE) {
+ while (true) {
spiReceive(mmcp->config->spip, 1, buf);
- if (buf[0] == 0xFF)
+ if (buf[0] == 0xFFU) {
break;
-#ifdef MMC_NICE_WAITING
- chThdSleep(1); /* Trying to be nice with the other threads.*/
+ }
+#if MMC_NICE_WAITING == TRUE
+ /* Trying to be nice with the other threads.*/
+ osalThreadSleepMilliseconds(1);
#endif
}
spiUnselect(mmcp->config->spip);
@@ -389,7 +395,7 @@ void mmcObjectInit(MMCDriver *mmcp) {
mmcp->vmt = &mmc_vmt;
mmcp->state = BLK_STOP;
mmcp->config = NULL;
- mmcp->block_addresses = FALSE;
+ mmcp->block_addresses = false;
}
/**
@@ -402,9 +408,9 @@ void mmcObjectInit(MMCDriver *mmcp) {
*/
void mmcStart(MMCDriver *mmcp, const MMCConfig *config) {
- chDbgCheck((mmcp != NULL) && (config != NULL), "mmcStart");
- chDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE),
- "mmcStart(), #1", "invalid state");
+ osalDbgCheck((mmcp != NULL) && (config != NULL));
+ osalDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE),
+ "invalid state");
mmcp->config = config;
mmcp->state = BLK_ACTIVE;
@@ -419,12 +425,13 @@ void mmcStart(MMCDriver *mmcp, const MMCConfig *config) {
*/
void mmcStop(MMCDriver *mmcp) {
- chDbgCheck(mmcp != NULL, "mmcStop");
- chDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE),
- "mmcStop(), #1", "invalid state");
+ osalDbgCheck(mmcp != NULL);
+ osalDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE),
+ "invalid state");
spiStop(mmcp->config->spip);
- mmcp->state = BLK_STOP;
+ mmcp->config = NULL;
+ mmcp->state = BLK_STOP;
}
/**
@@ -438,24 +445,24 @@ void mmcStop(MMCDriver *mmcp) {
* @param[in] mmcp pointer to the @p MMCDriver object
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded and the driver is now
+ * @retval HAL_SUCCESS the operation succeeded and the driver is now
* in the @p MMC_READY state.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcConnect(MMCDriver *mmcp) {
+bool mmcConnect(MMCDriver *mmcp) {
unsigned i;
uint8_t r3[4];
- chDbgCheck(mmcp != NULL, "mmcConnect");
+ osalDbgCheck(mmcp != NULL);
- chDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY),
- "mmcConnect(), #1", "invalid state");
+ osalDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY),
+ "invalid state");
/* Connection procedure in progress.*/
mmcp->state = BLK_CONNECTING;
- mmcp->block_addresses = FALSE;
+ mmcp->block_addresses = false;
/* Slow clock mode and 128 clock pulses.*/
spiStart(mmcp->config->spip, mmcp->config->lscfg);
@@ -463,12 +470,14 @@ bool_t mmcConnect(MMCDriver *mmcp) {
/* SPI mode selection.*/
i = 0;
- while (TRUE) {
- if (send_command_R1(mmcp, MMCSD_CMD_GO_IDLE_STATE, 0) == 0x01)
+ while (true) {
+ if (send_command_R1(mmcp, MMCSD_CMD_GO_IDLE_STATE, 0) == 0x01U) {
break;
- if (++i >= MMC_CMD0_RETRY)
+ }
+ if (++i >= MMC_CMD0_RETRY) {
goto failed;
- chThdSleepMilliseconds(10);
+ }
+ osalThreadSleepMilliseconds(10);
}
/* Try to detect if this is a high capacity card and switch to block
@@ -476,40 +485,47 @@ bool_t mmcConnect(MMCDriver *mmcp) {
This method is based on "How to support SDC Ver2 and high capacity cards"
by ElmChan.*/
if (send_command_R3(mmcp, MMCSD_CMD_SEND_IF_COND,
- MMCSD_CMD8_PATTERN, r3) != 0x05) {
+ MMCSD_CMD8_PATTERN, r3) != 0x05U) {
/* Switch to SDHC mode.*/
i = 0;
- while (TRUE) {
- if ((send_command_R1(mmcp, MMCSD_CMD_APP_CMD, 0) == 0x01) &&
- (send_command_R3(mmcp, MMCSD_CMD_APP_OP_COND,
- 0x400001aa, r3) == 0x00))
+ while (true) {
+ /*lint -save -e9007 [13.5] Side effect unimportant.*/
+ if ((send_command_R1(mmcp, MMCSD_CMD_APP_CMD, 0) == 0x01U) &&
+ (send_command_R3(mmcp, MMCSD_CMD_APP_OP_COND, 0x400001AAU, r3) == 0x00U)) {
+ /*lint -restore*/
break;
+ }
- if (++i >= MMC_ACMD41_RETRY)
+ if (++i >= MMC_ACMD41_RETRY) {
goto failed;
- chThdSleepMilliseconds(10);
+ }
+ osalThreadSleepMilliseconds(10);
}
/* Execute dedicated read on OCR register */
- send_command_R3(mmcp, MMCSD_CMD_READ_OCR, 0, r3);
+ (void) send_command_R3(mmcp, MMCSD_CMD_READ_OCR, 0, r3);
/* Check if CCS is set in response. Card operates in block mode if set.*/
- if (r3[0] & 0x40)
- mmcp->block_addresses = TRUE;
+ if ((r3[0] & 0x40U) != 0U) {
+ mmcp->block_addresses = true;
+ }
}
/* Initialization.*/
i = 0;
- while (TRUE) {
+ while (true) {
uint8_t b = send_command_R1(mmcp, MMCSD_CMD_INIT, 0);
- if (b == 0x00)
+ if (b == 0x00U) {
break;
- if (b != 0x01)
+ }
+ if (b != 0x01U) {
goto failed;
- if (++i >= MMC_CMD1_RETRY)
+ }
+ if (++i >= MMC_CMD1_RETRY) {
goto failed;
- chThdSleepMilliseconds(10);
+ }
+ osalThreadSleepMilliseconds(10);
}
/* Initialization complete, full speed.*/
@@ -517,27 +533,32 @@ bool_t mmcConnect(MMCDriver *mmcp) {
/* Setting block size.*/
if (send_command_R1(mmcp, MMCSD_CMD_SET_BLOCKLEN,
- MMCSD_BLOCK_SIZE) != 0x00)
+ MMCSD_BLOCK_SIZE) != 0x00U) {
goto failed;
+ }
/* Determine capacity.*/
- if (read_CxD(mmcp, MMCSD_CMD_SEND_CSD, mmcp->csd))
+ if (read_CxD(mmcp, MMCSD_CMD_SEND_CSD, mmcp->csd)) {
goto failed;
- mmcp->capacity = mmcsdGetCapacity(mmcp->csd);
- if (mmcp->capacity == 0)
+ }
+
+ mmcp->capacity = _mmcsd_get_capacity(mmcp->csd);
+ if (mmcp->capacity == 0U) {
goto failed;
+ }
- if (read_CxD(mmcp, MMCSD_CMD_SEND_CID, mmcp->cid))
+ if (read_CxD(mmcp, MMCSD_CMD_SEND_CID, mmcp->cid)) {
goto failed;
+ }
mmcp->state = BLK_READY;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
/* Connection failed, state reset to BLK_ACTIVE.*/
failed:
spiStop(mmcp->config->spip);
mmcp->state = BLK_ACTIVE;
- return CH_FAILED;
+ return HAL_FAILED;
}
/**
@@ -546,25 +567,25 @@ bool_t mmcConnect(MMCDriver *mmcp) {
* @param[in] mmcp pointer to the @p MMCDriver object
* @return The operation status.
*
- * @retval CH_SUCCESS the operation succeeded and the driver is now
+ * @retval HAL_SUCCESS the operation succeeded and the driver is now
* in the @p MMC_INSERTED state.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcDisconnect(MMCDriver *mmcp) {
+bool mmcDisconnect(MMCDriver *mmcp) {
- chDbgCheck(mmcp != NULL, "mmcDisconnect");
+ osalDbgCheck(mmcp != NULL);
- chSysLock();
- chDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY),
- "mmcDisconnect(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY),
+ "invalid state");
if (mmcp->state == BLK_ACTIVE) {
- chSysUnlock();
- return CH_SUCCESS;
+ osalSysUnlock();
+ return HAL_SUCCESS;
}
mmcp->state = BLK_DISCONNECTING;
- chSysUnlock();
+ osalSysUnlock();
/* Wait for the pending write operations to complete.*/
spiStart(mmcp->config->spip, mmcp->config->hscfg);
@@ -572,7 +593,7 @@ bool_t mmcDisconnect(MMCDriver *mmcp) {
spiStop(mmcp->config->spip);
mmcp->state = BLK_ACTIVE;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -582,16 +603,15 @@ bool_t mmcDisconnect(MMCDriver *mmcp) {
* @param[in] startblk first block to read
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) {
+bool mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) {
- chDbgCheck(mmcp != NULL, "mmcStartSequentialRead");
- chDbgAssert(mmcp->state == BLK_READY,
- "mmcStartSequentialRead(), #1", "invalid state");
+ osalDbgCheck(mmcp != NULL);
+ osalDbgAssert(mmcp->state == BLK_READY, "invalid state");
/* Read operation in progress.*/
mmcp->state = BLK_READING;
@@ -601,17 +621,19 @@ bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) {
spiStart(mmcp->config->spip, mmcp->config->hscfg);
spiSelect(mmcp->config->spip);
- if (mmcp->block_addresses)
+ if (mmcp->block_addresses) {
send_hdr(mmcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, startblk);
- else
+ }
+ else {
send_hdr(mmcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, startblk * MMCSD_BLOCK_SIZE);
+ }
- if (recvr1(mmcp) != 0x00) {
+ if (recvr1(mmcp) != 0x00U) {
spiStop(mmcp->config->spip);
mmcp->state = BLK_READY;
- return CH_FAILED;
+ return HAL_FAILED;
}
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -621,33 +643,34 @@ bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) {
* @param[out] buffer pointer to the read buffer
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) {
- int i;
+bool mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) {
+ unsigned i;
- chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialRead");
+ osalDbgCheck((mmcp != NULL) && (buffer != NULL));
- if (mmcp->state != BLK_READING)
- return CH_FAILED;
+ if (mmcp->state != BLK_READING) {
+ return HAL_FAILED;
+ }
for (i = 0; i < MMC_WAIT_DATA; i++) {
spiReceive(mmcp->config->spip, 1, buffer);
- if (buffer[0] == 0xFE) {
+ if (buffer[0] == 0xFEU) {
spiReceive(mmcp->config->spip, MMCSD_BLOCK_SIZE, buffer);
/* CRC ignored. */
spiIgnore(mmcp->config->spip, 2);
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
}
/* Timeout.*/
spiUnselect(mmcp->config->spip);
spiStop(mmcp->config->spip);
mmcp->state = BLK_READY;
- return CH_FAILED;
+ return HAL_FAILED;
}
/**
@@ -656,29 +679,31 @@ bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) {
* @param[in] mmcp pointer to the @p MMCDriver object
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcStopSequentialRead(MMCDriver *mmcp) {
- static const uint8_t stopcmd[] = {0x40 | MMCSD_CMD_STOP_TRANSMISSION,
- 0, 0, 0, 0, 1, 0xFF};
+bool mmcStopSequentialRead(MMCDriver *mmcp) {
+ static const uint8_t stopcmd[] = {
+ (uint8_t)(0x40U | MMCSD_CMD_STOP_TRANSMISSION), 0, 0, 0, 0, 1, 0xFF
+ };
- chDbgCheck(mmcp != NULL, "mmcStopSequentialRead");
+ osalDbgCheck(mmcp != NULL);
- if (mmcp->state != BLK_READING)
- return CH_FAILED;
+ if (mmcp->state != BLK_READING) {
+ return HAL_FAILED;
+ }
spiSend(mmcp->config->spip, sizeof(stopcmd), stopcmd);
-/* result = recvr1(mmcp) != 0x00;*/
+/* result = recvr1(mmcp) != 0x00U;*/
/* Note, ignored r1 response, it can be not zero, unknown issue.*/
(void) recvr1(mmcp);
/* Read operation finished.*/
spiUnselect(mmcp->config->spip);
mmcp->state = BLK_READY;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -688,34 +713,35 @@ bool_t mmcStopSequentialRead(MMCDriver *mmcp) {
* @param[in] startblk first block to write
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) {
+bool mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) {
- chDbgCheck(mmcp != NULL, "mmcStartSequentialWrite");
- chDbgAssert(mmcp->state == BLK_READY,
- "mmcStartSequentialWrite(), #1", "invalid state");
+ osalDbgCheck(mmcp != NULL);
+ osalDbgAssert(mmcp->state == BLK_READY, "invalid state");
/* Write operation in progress.*/
mmcp->state = BLK_WRITING;
spiStart(mmcp->config->spip, mmcp->config->hscfg);
spiSelect(mmcp->config->spip);
- if (mmcp->block_addresses)
+ if (mmcp->block_addresses) {
send_hdr(mmcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, startblk);
- else
+ }
+ else {
send_hdr(mmcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK,
startblk * MMCSD_BLOCK_SIZE);
+ }
- if (recvr1(mmcp) != 0x00) {
+ if (recvr1(mmcp) != 0x00U) {
spiStop(mmcp->config->spip);
mmcp->state = BLK_READY;
- return CH_FAILED;
+ return HAL_FAILED;
}
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -725,34 +751,35 @@ bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) {
* @param[out] buffer pointer to the write buffer
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) {
+bool mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) {
static const uint8_t start[] = {0xFF, 0xFC};
uint8_t b[1];
- chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialWrite");
+ osalDbgCheck((mmcp != NULL) && (buffer != NULL));
- if (mmcp->state != BLK_WRITING)
- return CH_FAILED;
+ if (mmcp->state != BLK_WRITING) {
+ return HAL_FAILED;
+ }
spiSend(mmcp->config->spip, sizeof(start), start); /* Data prologue. */
spiSend(mmcp->config->spip, MMCSD_BLOCK_SIZE, buffer);/* Data. */
spiIgnore(mmcp->config->spip, 2); /* CRC ignored. */
spiReceive(mmcp->config->spip, 1, b);
- if ((b[0] & 0x1F) == 0x05) {
+ if ((b[0] & 0x1FU) == 0x05U) {
wait(mmcp);
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/* Error.*/
spiUnselect(mmcp->config->spip);
spiStop(mmcp->config->spip);
mmcp->state = BLK_READY;
- return CH_FAILED;
+ return HAL_FAILED;
}
/**
@@ -761,25 +788,26 @@ bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) {
* @param[in] mmcp pointer to the @p MMCDriver object
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcStopSequentialWrite(MMCDriver *mmcp) {
+bool mmcStopSequentialWrite(MMCDriver *mmcp) {
static const uint8_t stop[] = {0xFD, 0xFF};
- chDbgCheck(mmcp != NULL, "mmcStopSequentialWrite");
+ osalDbgCheck(mmcp != NULL);
- if (mmcp->state != BLK_WRITING)
- return CH_FAILED;
+ if (mmcp->state != BLK_WRITING) {
+ return HAL_FAILED;
+ }
spiSend(mmcp->config->spip, sizeof(stop), stop);
spiUnselect(mmcp->config->spip);
/* Write operation finished.*/
mmcp->state = BLK_READY;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -788,17 +816,18 @@ bool_t mmcStopSequentialWrite(MMCDriver *mmcp) {
* @param[in] mmcp pointer to the @p MMCDriver object
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcSync(MMCDriver *mmcp) {
+bool mmcSync(MMCDriver *mmcp) {
- chDbgCheck(mmcp != NULL, "mmcSync");
+ osalDbgCheck(mmcp != NULL);
- if (mmcp->state != BLK_READY)
- return CH_FAILED;
+ if (mmcp->state != BLK_READY) {
+ return HAL_FAILED;
+ }
/* Synchronization operation in progress.*/
mmcp->state = BLK_SYNCING;
@@ -808,7 +837,7 @@ bool_t mmcSync(MMCDriver *mmcp) {
/* Synchronization operation finished.*/
mmcp->state = BLK_READY;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -818,22 +847,23 @@ bool_t mmcSync(MMCDriver *mmcp) {
* @param[out] bdip pointer to a @p BlockDeviceInfo structure
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) {
+bool mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) {
- chDbgCheck((mmcp != NULL) && (bdip != NULL), "mmcGetInfo");
+ osalDbgCheck((mmcp != NULL) && (bdip != NULL));
- if (mmcp->state != BLK_READY)
- return CH_FAILED;
+ if (mmcp->state != BLK_READY) {
+ return HAL_FAILED;
+ }
bdip->blk_num = mmcp->capacity;
bdip->blk_size = MMCSD_BLOCK_SIZE;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -844,14 +874,14 @@ bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) {
* @param[in] endblk ending block number
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk) {
+bool mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk) {
- chDbgCheck((mmcp != NULL), "mmcErase");
+ osalDbgCheck((mmcp != NULL));
/* Erase operation in progress.*/
mmcp->state = BLK_WRITING;
@@ -862,25 +892,28 @@ bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk) {
endblk *= MMCSD_BLOCK_SIZE;
}
- if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_START, startblk))
+ if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_START, startblk) != 0x00U) {
goto failed;
+ }
- if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_END, endblk))
+ if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_END, endblk) != 0x00U) {
goto failed;
+ }
- if (send_command_R1(mmcp, MMCSD_CMD_ERASE, 0))
+ if (send_command_R1(mmcp, MMCSD_CMD_ERASE, 0) != 0x00U) {
goto failed;
+ }
mmcp->state = BLK_READY;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
/* Command failed, state reset to BLK_ACTIVE.*/
failed:
spiStop(mmcp->config->spip);
mmcp->state = BLK_READY;
- return CH_FAILED;
+ return HAL_FAILED;
}
-#endif /* HAL_USE_MMC_SPI */
+#endif /* HAL_USE_MMC_SPI == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mmcsd.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mmcsd.c
new file mode 100644
index 0000000000..5d781a1cdf
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_mmcsd.c
@@ -0,0 +1,331 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_mmcsd.c
+ * @brief MMC/SD cards common code.
+ *
+ * @addtogroup MMCSD
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_MMC_SPI == TRUE) || (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Gets a bit field from a words array.
+ * @note The bit zero is the LSb of the first word.
+ *
+ * @param[in] data pointer to the words array
+ * @param[in] end bit offset of the last bit of the field, inclusive
+ * @param[in] start bit offset of the first bit of the field, inclusive
+ *
+ * @return The bits field value, left aligned.
+ *
+ * @notapi
+ */
+uint32_t _mmcsd_get_slice(const uint32_t *data,
+ uint32_t end,
+ uint32_t start) {
+ unsigned startidx, endidx, startoff;
+ uint32_t endmask;
+
+ osalDbgCheck((end >= start) && ((end - start) < 32U));
+
+ startidx = start / 32U;
+ startoff = start % 32U;
+ endidx = end / 32U;
+ endmask = ((uint32_t)1U << ((end % 32U) + 1U)) - 1U;
+
+ /* One or two pieces?*/
+ if (startidx < endidx) {
+ return (data[startidx] >> startoff) | /* Two pieces case. */
+ ((data[endidx] & endmask) << (32U - startoff));
+ }
+ return (data[startidx] & endmask) >> startoff; /* One piece case. */
+}
+
+/**
+ * @brief Extract card capacity from a CSD.
+ * @details The capacity is returned as number of available blocks.
+ *
+ * @param[in] csd the CSD record
+ *
+ * @return The card capacity.
+ * @retval 0 CSD format error
+ *
+ * @notapi
+ */
+uint32_t _mmcsd_get_capacity(const uint32_t *csd) {
+ uint32_t a, b, c;
+
+ osalDbgCheck(NULL != csd);
+
+ switch (_mmcsd_get_slice(csd, MMCSD_CSD_10_CSD_STRUCTURE_SLICE)) {
+ case 0:
+ /* CSD version 1.0 */
+ a = _mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE);
+ b = _mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE);
+ c = _mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE);
+ return ((a + 1U) << (b + 2U)) << (c - 9U); /* 2^9 == MMCSD_BLOCK_SIZE. */
+ case 1:
+ /* CSD version 2.0.*/
+ return 1024U * (_mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE) + 1U);
+ default:
+ /* Reserved value detected.*/
+ break;
+ }
+ return 0U;
+}
+
+/**
+ * @brief Extract MMC card capacity from EXT_CSD.
+ * @details The capacity is returned as number of available blocks.
+ *
+ * @param[in] ext_csd the extended CSD record
+ *
+ * @return The card capacity.
+ *
+ * @notapi
+ */
+uint32_t _mmcsd_get_capacity_ext(const uint8_t *ext_csd) {
+
+ osalDbgCheck(NULL != ext_csd);
+
+ return ((uint32_t)ext_csd[215] << 24U) +
+ ((uint32_t)ext_csd[214] << 16U) +
+ ((uint32_t)ext_csd[213] << 8U) +
+ (uint32_t)ext_csd[212];
+}
+
+/**
+ * @brief Unpacks SDC CID array in structure.
+ *
+ * @param[in] sdcp pointer to the @p MMCSDBlockDevice object
+ * @param[out] cidsdc pointer to the @p unpacked_sdc_cid_t object
+ *
+ * @notapi
+ */
+void _mmcsd_unpack_sdc_cid(const MMCSDBlockDevice *sdcp,
+ unpacked_sdc_cid_t *cidsdc) {
+ const uint32_t *cid;
+
+ osalDbgCheck((NULL != sdcp) && (NULL != cidsdc));
+
+ cid = sdcp->cid;
+ cidsdc->crc = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_CRC_SLICE);
+ cidsdc->mdt_y = (uint16_t)_mmcsd_get_slice(cid, MMCSD_CID_SDC_MDT_Y_SLICE) +
+ 2000U;
+ cidsdc->mdt_m = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_MDT_M_SLICE);
+ cidsdc->mid = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_MID_SLICE);
+ cidsdc->oid = (uint16_t)_mmcsd_get_slice(cid, MMCSD_CID_SDC_OID_SLICE);
+ cidsdc->pnm[4] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM0_SLICE);
+ cidsdc->pnm[3] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM1_SLICE);
+ cidsdc->pnm[2] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM2_SLICE);
+ cidsdc->pnm[1] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM3_SLICE);
+ cidsdc->pnm[0] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM4_SLICE);
+ cidsdc->prv_n = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PRV_N_SLICE);
+ cidsdc->prv_m = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PRV_M_SLICE);
+ cidsdc->psn = _mmcsd_get_slice(cid, MMCSD_CID_SDC_PSN_SLICE);
+}
+
+/**
+ * @brief Unpacks MMC CID array in structure.
+ *
+ * @param[in] sdcp pointer to the @p MMCSDBlockDevice object
+ * @param[out] cidmmc pointer to the @p unpacked_mmc_cid_t object
+ *
+ * @notapi
+ */
+void _mmcsd_unpack_mmc_cid(const MMCSDBlockDevice *sdcp,
+ unpacked_mmc_cid_t *cidmmc) {
+ const uint32_t *cid;
+
+ osalDbgCheck((NULL != sdcp) && (NULL != cidmmc));
+
+ cid = sdcp->cid;
+ cidmmc->crc = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_CRC_SLICE);
+ cidmmc->mdt_y = (uint16_t)_mmcsd_get_slice(cid, MMCSD_CID_MMC_MDT_Y_SLICE) +
+ 1997U;
+ cidmmc->mdt_m = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_MDT_M_SLICE);
+ cidmmc->mid = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_MID_SLICE);
+ cidmmc->oid = (uint16_t)_mmcsd_get_slice(cid, MMCSD_CID_MMC_OID_SLICE);
+ cidmmc->pnm[5] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM0_SLICE);
+ cidmmc->pnm[4] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM1_SLICE);
+ cidmmc->pnm[3] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM2_SLICE);
+ cidmmc->pnm[2] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM3_SLICE);
+ cidmmc->pnm[1] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM4_SLICE);
+ cidmmc->pnm[0] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM5_SLICE);
+ cidmmc->prv_n = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PRV_N_SLICE);
+ cidmmc->prv_m = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PRV_M_SLICE);
+ cidmmc->psn = _mmcsd_get_slice(cid, MMCSD_CID_MMC_PSN_SLICE);
+}
+
+/**
+ * @brief Unpacks MMC CSD array in structure.
+ *
+ * @param[in] sdcp pointer to the @p MMCSDBlockDevice object
+ * @param[out] csdmmc pointer to the @p unpacked_mmc_csd_t object
+ *
+ * @notapi
+ */
+void _mmcsd_unpack_csd_mmc(const MMCSDBlockDevice *sdcp,
+ unpacked_mmc_csd_t *csdmmc) {
+ const uint32_t *csd;
+
+ osalDbgCheck((NULL != sdcp) && (NULL != csdmmc));
+
+ csd = sdcp->csd;
+ csdmmc->c_size = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_MMC_C_SIZE_SLICE);
+ csdmmc->c_size_mult = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_C_SIZE_MULT_SLICE);
+ csdmmc->ccc = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_MMC_CCC_SLICE);
+ csdmmc->copy = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_COPY_SLICE);
+ csdmmc->crc = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_CRC_SLICE);
+ csdmmc->csd_structure = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_CSD_STRUCTURE_SLICE);
+ csdmmc->dsr_imp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_DSR_IMP_SLICE);
+ csdmmc->ecc = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_ECC_SLICE);
+ csdmmc->erase_grp_mult = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_ERASE_GRP_MULT_SLICE);
+ csdmmc->erase_grp_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_ERASE_GRP_SIZE_SLICE);
+ csdmmc->file_format = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_FILE_FORMAT_SLICE);
+ csdmmc->file_format_grp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_FILE_FORMAT_GRP_SLICE);
+ csdmmc->nsac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_NSAC_SLICE);
+ csdmmc->perm_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_PERM_WRITE_PROTECT_SLICE);
+ csdmmc->r2w_factor = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_R2W_FACTOR_SLICE);
+ csdmmc->read_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_READ_BL_LEN_SLICE);
+ csdmmc->read_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_READ_BL_PARTIAL_SLICE);
+ csdmmc->read_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_READ_BLK_MISALIGN_SLICE);
+ csdmmc->spec_vers = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_SPEC_VERS_SLICE);
+ csdmmc->taac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_TAAC_SLICE);
+ csdmmc->tmp_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_TMP_WRITE_PROTECT_SLICE);
+ csdmmc->tran_speed = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_TRAN_SPEED_SLICE);
+ csdmmc->vdd_r_curr_max = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_VDD_R_CURR_MAX_SLICE);
+ csdmmc->vdd_r_curr_min = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_VDD_R_CURR_MIN_SLICE);
+ csdmmc->vdd_w_curr_max = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_VDD_W_CURR_MAX_SLICE);
+ csdmmc->vdd_w_curr_min = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_VDD_W_CURR_MIN_SLICE);
+ csdmmc->wp_grp_enable = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WP_GRP_ENABLE_SLICE);
+ csdmmc->wp_grp_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WP_GRP_SIZE_SLICE);
+ csdmmc->write_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WRITE_BL_LEN_SLICE);
+ csdmmc->write_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WRITE_BL_PARTIAL_SLICE);
+ csdmmc->write_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WRITE_BLK_MISALIGN_SLICE);
+}
+
+/**
+ * @brief Unpacks SDC CSD v1.0 array in structure.
+ *
+ * @param[in] sdcp pointer to the @p MMCSDBlockDevice object
+ * @param[out] csd10 pointer to the @p unpacked_sdc_csd_10_t object
+ *
+ * @notapi
+ */
+void _mmcsd_unpack_csd_v10(const MMCSDBlockDevice *sdcp,
+ unpacked_sdc_csd_10_t *csd10) {
+ const uint32_t *csd;
+
+ osalDbgCheck(NULL != sdcp);
+
+ csd = sdcp->csd;
+ csd10->c_size = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE);
+ csd10->c_size_mult = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE);
+ csd10->ccc = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_10_CCC_SLICE);
+ csd10->copy = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_COPY_SLICE);
+ csd10->crc = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_CRC_SLICE);
+ csd10->csd_structure = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_CSD_STRUCTURE_SLICE);
+ csd10->dsr_imp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_DSR_IMP_SLICE);
+ csd10->erase_blk_en = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_ERASE_BLK_EN_SLICE);
+ csd10->erase_sector_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE);
+ csd10->file_format = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_FILE_FORMAT_SLICE);
+ csd10->file_format_grp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE);
+ csd10->nsac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_NSAC_SLICE);
+ csd10->perm_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE);
+ csd10->r2w_factor = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_R2W_FACTOR_SLICE);
+ csd10->read_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE);
+ csd10->read_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_PARTIAL_SLICE);
+ csd10->read_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE);
+ csd10->taac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_TAAC_SLICE);
+ csd10->tmp_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE);
+ csd10->tran_speed = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_TRANS_SPEED_SLICE);
+ csd10->wp_grp_enable = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WP_GRP_ENABLE_SLICE);
+ csd10->wp_grp_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WP_GRP_SIZE_SLICE);
+ csd10->write_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WRITE_BL_LEN_SLICE);
+ csd10->write_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE);
+ csd10->write_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE);
+}
+
+/**
+ * @brief Unpacks SDC CSD v2.0 array in structure.
+ *
+ * @param[in] sdcp pointer to the @p MMCSDBlockDevice object
+ * @param[out] csd20 pointer to the @p unpacked_sdc_csd_20_t object
+ *
+ * @notapi
+ */
+void _mmcsd_unpack_csd_v20(const MMCSDBlockDevice *sdcp,
+ unpacked_sdc_csd_20_t *csd20) {
+ const uint32_t *csd;
+
+ osalDbgCheck(NULL != sdcp);
+
+ csd = sdcp->csd;
+ csd20->c_size = _mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE);
+ csd20->crc = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_CRC_SLICE);
+ csd20->ccc = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_20_CCC_SLICE);
+ csd20->copy = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_COPY_SLICE);
+ csd20->csd_structure = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_CSD_STRUCTURE_SLICE);
+ csd20->dsr_imp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_DSR_IMP_SLICE);
+ csd20->erase_blk_en = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_ERASE_BLK_EN_SLICE);
+ csd20->file_format = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_FILE_FORMAT_SLICE);
+ csd20->file_format_grp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE);
+ csd20->nsac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_NSAC_SLICE);
+ csd20->perm_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE);
+ csd20->r2w_factor = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_R2W_FACTOR_SLICE);
+ csd20->read_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_READ_BL_LEN_SLICE);
+ csd20->read_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_READ_BL_PARTIAL_SLICE);
+ csd20->read_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE);
+ csd20->erase_sector_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE);
+ csd20->taac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_TAAC_SLICE);
+ csd20->tmp_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE);
+ csd20->tran_speed = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_TRANS_SPEED_SLICE);
+ csd20->wp_grp_enable = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WP_GRP_ENABLE_SLICE);
+ csd20->wp_grp_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WP_GRP_SIZE_SLICE);
+ csd20->write_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WRITE_BL_LEN_SLICE);
+ csd20->write_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE);
+ csd20->write_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE);
+}
+
+#endif /* (HAL_USE_MMC_SPI == TRUE) || (HAL_USE_SDC == TRUE) */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/pal.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_pal.c
similarity index 65%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/pal.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_pal.c
index 38ec087aa7..c398ed4530 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/pal.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_pal.c
@@ -1,42 +1,30 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file pal.c
+ * @file hal_pal.c
* @brief I/O Ports Abstraction Layer code.
*
* @addtogroup PAL
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_PAL || defined(__DOXYGEN__)
+#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -62,8 +50,8 @@
* @brief Read from an I/O bus.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The function internally uses the @p palReadGroup() macro. The use
* of this function is preferred when you value code size, readability
* and error checking over speed.
@@ -76,8 +64,7 @@
*/
ioportmask_t palReadBus(IOBus *bus) {
- chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH),
- "palReadBus");
+ osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH));
return palReadGroup(bus->portid, bus->mask, bus->offset);
}
@@ -86,8 +73,8 @@ ioportmask_t palReadBus(IOBus *bus) {
* @brief Write to an I/O bus.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The default implementation is non atomic and not necessarily
* optimal. Low level drivers may optimize the function by using
* specific hardware or coding.
@@ -102,8 +89,7 @@ ioportmask_t palReadBus(IOBus *bus) {
*/
void palWriteBus(IOBus *bus, ioportmask_t bits) {
- chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH),
- "palWriteBus");
+ osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH));
palWriteGroup(bus->portid, bus->mask, bus->offset, bits);
}
@@ -112,8 +98,8 @@ void palWriteBus(IOBus *bus, ioportmask_t bits) {
* @brief Programs a bus with the specified mode.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
- * need to enclose port I/O operations between @p chSysLock() and
- * @p chSysUnlock().
+ * need to enclose port I/O operations between @p osalSysLock() and
+ * @p osalSysUnlock().
* @note The default implementation is non atomic and not necessarily
* optimal. Low level drivers may optimize the function by using
* specific hardware or coding.
@@ -126,12 +112,11 @@ void palWriteBus(IOBus *bus, ioportmask_t bits) {
*/
void palSetBusMode(IOBus *bus, iomode_t mode) {
- chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH),
- "palSetBusMode");
+ osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH));
palSetGroupMode(bus->portid, bus->mask, bus->offset, mode);
}
-#endif /* HAL_USE_PAL */
+#endif /* HAL_USE_PAL == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_pwm.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_pwm.c
new file mode 100644
index 0000000000..9cae5613d5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_pwm.c
@@ -0,0 +1,313 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_pwm.c
+ * @brief PWM Driver code.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief PWM Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void pwmInit(void) {
+
+ pwm_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p PWMDriver structure.
+ *
+ * @param[out] pwmp pointer to a @p PWMDriver object
+ *
+ * @init
+ */
+void pwmObjectInit(PWMDriver *pwmp) {
+
+ pwmp->state = PWM_STOP;
+ pwmp->config = NULL;
+ pwmp->enabled = 0;
+ pwmp->channels = 0;
+#if defined(PWM_DRIVER_EXT_INIT_HOOK)
+ PWM_DRIVER_EXT_INIT_HOOK(pwmp);
+#endif
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] config pointer to a @p PWMConfig object
+ *
+ * @api
+ */
+void pwmStart(PWMDriver *pwmp, const PWMConfig *config) {
+
+ osalDbgCheck((pwmp != NULL) && (config != NULL));
+
+ osalSysLock();
+ osalDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY),
+ "invalid state");
+ pwmp->config = config;
+ pwmp->period = config->period;
+ pwm_lld_start(pwmp);
+ pwmp->enabled = 0;
+ pwmp->state = PWM_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @api
+ */
+void pwmStop(PWMDriver *pwmp) {
+
+ osalDbgCheck(pwmp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY),
+ "invalid state");
+
+ pwm_lld_stop(pwmp);
+ pwmp->enabled = 0;
+ pwmp->config = NULL;
+ pwmp->state = PWM_STOP;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @api
+ */
+void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period) {
+
+ osalDbgCheck(pwmp != NULL);
+
+ osalSysLock();
+ osalDbgAssert(pwmp->state == PWM_READY, "invalid state");
+ pwmChangePeriodI(pwmp, period);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note Depending on the hardware implementation this function has
+ * effect starting on the next cycle (recommended implementation)
+ * or immediately (fallback implementation).
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @api
+ */
+void pwmEnableChannel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+
+ osalDbgCheck((pwmp != NULL) && (channel < pwmp->channels));
+
+ osalSysLock();
+
+ osalDbgAssert(pwmp->state == PWM_READY, "not ready");
+
+ pwmEnableChannelI(pwmp, channel, width);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disables a PWM channel and its notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note Depending on the hardware implementation this function has
+ * effect starting on the next cycle (recommended implementation)
+ * or immediately (fallback implementation).
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @api
+ */
+void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ osalDbgCheck((pwmp != NULL) && (channel < pwmp->channels));
+
+ osalSysLock();
+
+ osalDbgAssert(pwmp->state == PWM_READY, "not ready");
+
+ pwmDisableChannelI(pwmp, channel);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @api
+ */
+void pwmEnablePeriodicNotification(PWMDriver *pwmp) {
+
+ osalDbgCheck(pwmp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert(pwmp->state == PWM_READY, "not ready");
+ osalDbgAssert(pwmp->config->callback != NULL, "undefined periodic callback");
+
+ pwmEnablePeriodicNotificationI(pwmp);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @api
+ */
+void pwmDisablePeriodicNotification(PWMDriver *pwmp) {
+
+ osalDbgCheck(pwmp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert(pwmp->state == PWM_READY, "not ready");
+ osalDbgAssert(pwmp->config->callback != NULL, "undefined periodic callback");
+
+ pwmDisablePeriodicNotificationI(pwmp);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @api
+ */
+void pwmEnableChannelNotification(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ osalDbgCheck((pwmp != NULL) && (channel < pwmp->channels));
+
+ osalSysLock();
+
+ osalDbgAssert(pwmp->state == PWM_READY, "not ready");
+ osalDbgAssert((pwmp->enabled & ((pwmchnmsk_t)1U << (pwmchnmsk_t)channel)) != 0U,
+ "channel not enabled");
+ osalDbgAssert(pwmp->config->channels[channel].callback != NULL,
+ "undefined channel callback");
+
+ pwmEnableChannelNotificationI(pwmp, channel);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @api
+ */
+void pwmDisableChannelNotification(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ osalDbgCheck((pwmp != NULL) && (channel < pwmp->channels));
+
+ osalSysLock();
+
+ osalDbgAssert(pwmp->state == PWM_READY, "not ready");
+ osalDbgAssert((pwmp->enabled & ((pwmchnmsk_t)1U << (pwmchnmsk_t)channel)) != 0U,
+ "channel not enabled");
+ osalDbgAssert(pwmp->config->channels[channel].callback != NULL,
+ "undefined channel callback");
+
+ pwmDisableChannelNotificationI(pwmp, channel);
+
+ osalSysUnlock();
+}
+
+#endif /* HAL_USE_PWM == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_qspi.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_qspi.c
new file mode 100644
index 0000000000..9ae18be52c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_qspi.c
@@ -0,0 +1,392 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_qspi.c
+ * @brief QSPI Driver code.
+ *
+ * @addtogroup QSPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_QSPI == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief QSPI Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void qspiInit(void) {
+
+ qspi_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p QSPIDriver structure.
+ *
+ * @param[out] qspip pointer to the @p QSPIDriver object
+ *
+ * @init
+ */
+void qspiObjectInit(QSPIDriver *qspip) {
+
+ qspip->state = QSPI_STOP;
+ qspip->config = NULL;
+#if QSPI_USE_WAIT == TRUE
+ qspip->thread = NULL;
+#endif
+#if QSPI_USE_MUTUAL_EXCLUSION == TRUE
+ osalMutexObjectInit(&qspip->mutex);
+#endif
+#if defined(QSPI_DRIVER_EXT_INIT_HOOK)
+ QSPI_DRIVER_EXT_INIT_HOOK(qspip);
+#endif
+}
+
+/**
+ * @brief Configures and activates the QSPI peripheral.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] config pointer to the @p QSPIConfig object
+ *
+ * @api
+ */
+void qspiStart(QSPIDriver *qspip, const QSPIConfig *config) {
+
+ osalDbgCheck((qspip != NULL) && (config != NULL));
+
+ osalSysLock();
+
+ osalDbgAssert((qspip->state == QSPI_STOP) || (qspip->state == QSPI_READY),
+ "invalid state");
+
+ qspip->config = config;
+ qspi_lld_start(qspip);
+ qspip->state = QSPI_READY;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the QSPI peripheral.
+ * @note Deactivating the peripheral also enforces a release of the slave
+ * select line.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @api
+ */
+void qspiStop(QSPIDriver *qspip) {
+
+ osalDbgCheck(qspip != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((qspip->state == QSPI_STOP) || (qspip->state == QSPI_READY),
+ "invalid state");
+
+ qspi_lld_stop(qspip);
+ qspip->config = NULL;
+ qspip->state = QSPI_STOP;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Sends a command without data phase.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ *
+ * @api
+ */
+void qspiStartCommand(QSPIDriver *qspip, const qspi_command_t *cmdp) {
+
+ osalDbgCheck((qspip != NULL) && (cmdp != NULL));
+
+ osalSysLock();
+
+ osalDbgAssert(qspip->state == QSPI_READY, "not ready");
+
+ qspiStartCommandI(qspip, cmdp);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Sends a command with data over the QSPI bus.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[in] n number of bytes to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @api
+ */
+void qspiStartSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, const uint8_t *txbuf) {
+
+ osalDbgCheck((qspip != NULL) && (cmdp != NULL));
+ osalDbgCheck((n > 0U) && (txbuf != NULL));
+
+ osalSysLock();
+
+ osalDbgAssert(qspip->state == QSPI_READY, "not ready");
+
+ qspiStartSendI(qspip, cmdp, n, txbuf);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Sends a command then receives data over the QSPI bus.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[in] n number of bytes to send
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @api
+ */
+void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, uint8_t *rxbuf) {
+
+ osalDbgCheck((qspip != NULL) && (cmdp != NULL));
+ osalDbgCheck((n > 0U) && (rxbuf != NULL));
+
+ osalSysLock();
+
+ osalDbgAssert(qspip->state == QSPI_READY, "not ready");
+
+ qspiStartReceiveI(qspip, cmdp, n, rxbuf);
+
+ osalSysUnlock();
+}
+
+#if (QSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Sends a command without data phase.
+ * @pre In order to use this function the option @p QSPI_USE_WAIT must be
+ * enabled.
+ * @pre In order to use this function the driver must have been configured
+ * without callbacks (@p end_cb = @p NULL).
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ *
+ * @api
+ */
+void qspiCommand(QSPIDriver *qspip, const qspi_command_t *cmdp) {
+
+ osalDbgCheck((qspip != NULL) && (cmdp != NULL));
+ osalDbgCheck((cmdp->cfg & QSPI_CFG_DATA_MODE_MASK) == QSPI_CFG_DATA_MODE_NONE);
+
+ osalSysLock();
+
+ osalDbgAssert(qspip->state == QSPI_READY, "not ready");
+ osalDbgAssert(qspip->config->end_cb == NULL, "has callback");
+
+ qspiStartCommandI(qspip, cmdp);
+ (void) osalThreadSuspendS(&qspip->thread);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Sends a command with data over the QSPI bus.
+ * @pre In order to use this function the option @p QSPI_USE_WAIT must be
+ * enabled.
+ * @pre In order to use this function the driver must have been configured
+ * without callbacks (@p end_cb = @p NULL).
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[in] n number of bytes to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @api
+ */
+void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, const uint8_t *txbuf) {
+
+ osalDbgCheck((qspip != NULL) && (cmdp != NULL));
+ osalDbgCheck((n > 0U) && (txbuf != NULL));
+ osalDbgCheck((cmdp->cfg & QSPI_CFG_DATA_MODE_MASK) != QSPI_CFG_DATA_MODE_NONE);
+
+ osalSysLock();
+
+ osalDbgAssert(qspip->state == QSPI_READY, "not ready");
+ osalDbgAssert(qspip->config->end_cb == NULL, "has callback");
+
+ qspiStartSendI(qspip, cmdp, n, txbuf);
+ (void) osalThreadSuspendS(&qspip->thread);
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Sends a command then receives data over the QSPI bus.
+ * @pre In order to use this function the option @p QSPI_USE_WAIT must be
+ * enabled.
+ * @pre In order to use this function the driver must have been configured
+ * without callbacks (@p end_cb = @p NULL).
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[in] n number of bytes to send
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @api
+ */
+void qspiReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, uint8_t *rxbuf) {
+
+ osalDbgCheck((qspip != NULL) && (cmdp != NULL));
+ osalDbgCheck((n > 0U) && (rxbuf != NULL));
+ osalDbgCheck((cmdp->cfg & QSPI_CFG_DATA_MODE_MASK) != QSPI_CFG_DATA_MODE_NONE);
+
+ osalSysLock();
+
+ osalDbgAssert(qspip->state == QSPI_READY, "not ready");
+ osalDbgAssert(qspip->config->end_cb == NULL, "has callback");
+
+ qspiStartReceiveI(qspip, cmdp, n, rxbuf);
+ (void) osalThreadSuspendS(&qspip->thread);
+
+ osalSysUnlock();
+}
+#endif /* QSPI_USE_WAIT == TRUE */
+
+#if (QSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Maps in memory space a QSPI flash device.
+ * @pre The memory flash device must be initialized appropriately
+ * before mapping it in memory space.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[out] addrp pointer to the memory start address of the mapped
+ * flash or @p NULL
+ *
+ * @api
+ */
+void qspiMapFlash(QSPIDriver *qspip,
+ const qspi_command_t *cmdp,
+ uint8_t **addrp) {
+
+ osalDbgCheck((qspip != NULL) && (cmdp != NULL));
+ osalDbgCheck((cmdp->cfg & QSPI_CFG_DATA_MODE_MASK) != QSPI_CFG_DATA_MODE_NONE);
+
+ osalSysLock();
+
+ osalDbgAssert(qspip->state == QSPI_READY, "not ready");
+
+ qspiMapFlashI(qspip, cmdp, addrp);
+ qspip->state = QSPI_MEMMAP;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Maps in memory space a QSPI flash device.
+ * @post The memory flash device must be re-initialized for normal
+ * commands exchange.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @api
+ */
+void qspiUnmapFlash(QSPIDriver *qspip) {
+
+ osalDbgCheck(qspip != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert(qspip->state == QSPI_MEMMAP, "not ready");
+
+ qspiUnmapFlashI(qspip);
+ qspip->state = QSPI_READY;
+
+ osalSysUnlock();
+}
+#endif /* QSPI_SUPPORTS_MEMMAP == TRUE */
+
+#if (QSPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Gains exclusive access to the QSPI bus.
+ * @details This function tries to gain ownership to the QSPI bus, if the bus
+ * is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option @p QSPI_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @api
+ */
+void qspiAcquireBus(QSPIDriver *qspip) {
+
+ osalDbgCheck(qspip != NULL);
+
+ osalMutexLock(&qspip->mutex);
+}
+
+/**
+ * @brief Releases exclusive access to the QSPI bus.
+ * @pre In order to use this function the option @p QSPI_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @api
+ */
+void qspiReleaseBus(QSPIDriver *qspip) {
+
+ osalDbgCheck(qspip != NULL);
+
+ osalMutexUnlock(&qspip->mutex);
+}
+#endif /* QSPI_USE_MUTUAL_EXCLUSION == TRUE */
+
+#endif /* HAL_USE_QSPI == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_queues.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_queues.c
new file mode 100644
index 0000000000..59c5dc504b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_queues.c
@@ -0,0 +1,490 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_queues.c
+ * @brief I/O Queues code.
+ *
+ * @addtogroup HAL_QUEUES
+ * @details Queues are mostly used in serial-like device drivers.
+ * Serial device drivers are usually designed to have a lower side
+ * (lower driver, it is usually an interrupt service routine) and an
+ * upper side (upper driver, accessed by the application threads).
+ * There are several kind of queues:
+ * - Input queue, unidirectional queue where the writer is the
+ * lower side and the reader is the upper side.
+ * - Output queue, unidirectional queue where the writer is the
+ * upper side and the reader is the lower side.
+ * - Full duplex queue, bidirectional queue. Full duplex queues
+ * are implemented by pairing an input queue and an output queue
+ * together.
+ * .
+ * @{
+ */
+
+#include "hal.h"
+
+/**
+ * @brief Initializes an input queue.
+ * @details A Semaphore is internally initialized and works as a counter of
+ * the bytes contained in the queue.
+ * @note The callback is invoked from within the S-Locked system state.
+ *
+ * @param[out] iqp pointer to an @p input_queue_t structure
+ * @param[in] bp pointer to a memory area allocated as queue buffer
+ * @param[in] size size of the queue buffer
+ * @param[in] infy pointer to a callback function that is invoked when
+ * data is read from the queue. The value can be @p NULL.
+ * @param[in] link application defined pointer
+ *
+ * @init
+ */
+void iqObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size,
+ qnotify_t infy, void *link) {
+
+ osalThreadQueueObjectInit(&iqp->q_waiting);
+ iqp->q_counter = 0;
+ iqp->q_buffer = bp;
+ iqp->q_rdptr = bp;
+ iqp->q_wrptr = bp;
+ iqp->q_top = bp + size;
+ iqp->q_notify = infy;
+ iqp->q_link = link;
+}
+
+/**
+ * @brief Resets an input queue.
+ * @details All the data in the input queue is erased and lost, any waiting
+ * thread is resumed with status @p MSG_RESET.
+ * @note A reset operation can be used by a low level driver in order to
+ * obtain immediate attention from the high level layers.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ *
+ * @iclass
+ */
+void iqResetI(input_queue_t *iqp) {
+
+ osalDbgCheckClassI();
+
+ iqp->q_rdptr = iqp->q_buffer;
+ iqp->q_wrptr = iqp->q_buffer;
+ iqp->q_counter = 0;
+ osalThreadDequeueAllI(&iqp->q_waiting, MSG_RESET);
+}
+
+/**
+ * @brief Input queue write.
+ * @details A byte value is written into the low end of an input queue.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ * @param[in] b the byte value to be written in the queue
+ * @return The operation status.
+ * @retval MSG_OK if the operation has been completed with success.
+ * @retval MSG_TIMEOUT if the queue is full and the operation cannot be
+ * completed.
+ *
+ * @iclass
+ */
+msg_t iqPutI(input_queue_t *iqp, uint8_t b) {
+
+ osalDbgCheckClassI();
+
+ if (iqIsFullI(iqp)) {
+ return MSG_TIMEOUT;
+ }
+
+ iqp->q_counter++;
+ *iqp->q_wrptr++ = b;
+ if (iqp->q_wrptr >= iqp->q_top) {
+ iqp->q_wrptr = iqp->q_buffer;
+ }
+
+ osalThreadDequeueNextI(&iqp->q_waiting, MSG_OK);
+
+ return MSG_OK;
+}
+
+/**
+ * @brief Input queue read with timeout.
+ * @details This function reads a byte value from an input queue. If the queue
+ * is empty then the calling thread is suspended until a byte arrives
+ * in the queue or a timeout occurs.
+ * @note The callback is invoked after removing a character from the
+ * queue.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return A byte value from the queue.
+ * @retval MSG_TIMEOUT if the specified time expired.
+ * @retval MSG_RESET if the queue has been reset.
+ *
+ * @api
+ */
+msg_t iqGetTimeout(input_queue_t *iqp, systime_t timeout) {
+ uint8_t b;
+
+ osalSysLock();
+
+ /* Waiting until there is a character available or a timeout occurs.*/
+ while (iqIsEmptyI(iqp)) {
+ msg_t msg = osalThreadEnqueueTimeoutS(&iqp->q_waiting, timeout);
+ if (msg < MSG_OK) {
+ osalSysUnlock();
+ return msg;
+ }
+ }
+
+ /* Getting the character from the queue.*/
+ iqp->q_counter--;
+ b = *iqp->q_rdptr++;
+ if (iqp->q_rdptr >= iqp->q_top) {
+ iqp->q_rdptr = iqp->q_buffer;
+ }
+
+ /* Inform the low side that the queue has at least one slot available.*/
+ if (iqp->q_notify != NULL) {
+ iqp->q_notify(iqp);
+ }
+
+ osalSysUnlock();
+
+ return (msg_t)b;
+}
+
+/**
+ * @brief Input queue read with timeout.
+ * @details The function reads data from an input queue into a buffer. The
+ * operation completes when the specified amount of data has been
+ * transferred or after the specified timeout or if the queue has
+ * been reset.
+ * @note The function is not atomic, if you need atomicity it is suggested
+ * to use a semaphore or a mutex for mutual exclusion.
+ * @note The callback is invoked after removing each character from the
+ * queue.
+ *
+ * @param[in] iqp pointer to an @p input_queue_t structure
+ * @param[out] bp pointer to the data buffer
+ * @param[in] n the maximum amount of data to be transferred, the
+ * value 0 is reserved
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The number of bytes effectively transferred.
+ *
+ * @api
+ */
+size_t iqReadTimeout(input_queue_t *iqp, uint8_t *bp,
+ size_t n, systime_t timeout) {
+ systime_t deadline;
+ qnotify_t nfy = iqp->q_notify;
+ size_t r = 0;
+
+ osalDbgCheck(n > 0U);
+
+ osalSysLock();
+
+ /* Time deadline for the whole operation, note the result is invalid
+ when timeout is TIME_INFINITE or TIME_IMMEDIATE but in that case
+ the deadline is not used.*/
+ deadline = osalOsGetSystemTimeX() + timeout;
+
+ while (true) {
+ /* Waiting until there is a character available or a timeout occurs.*/
+ while (iqIsEmptyI(iqp)) {
+ msg_t msg;
+
+ /* TIME_INFINITE and TIME_IMMEDIATE are handled differently, no
+ deadline.*/
+ if ((timeout == TIME_INFINITE) || (timeout == TIME_IMMEDIATE)) {
+ msg = osalThreadEnqueueTimeoutS(&iqp->q_waiting, timeout);
+ }
+ else {
+ systime_t next_timeout = deadline - osalOsGetSystemTimeX();
+
+ /* Handling the case where the system time went past the deadline,
+ in this case next becomes a very high number because the system
+ time is an unsigned type.*/
+ if (next_timeout > timeout) {
+ osalSysUnlock();
+ return r;
+ }
+
+ msg = osalThreadEnqueueTimeoutS(&iqp->q_waiting, next_timeout);
+ }
+
+ /* Anything except MSG_OK causes the operation to stop.*/
+ if (msg != MSG_OK) {
+ osalSysUnlock();
+ return r;
+ }
+ }
+
+ /* Getting the character from the queue.*/
+ iqp->q_counter--;
+ *bp++ = *iqp->q_rdptr++;
+ if (iqp->q_rdptr >= iqp->q_top) {
+ iqp->q_rdptr = iqp->q_buffer;
+ }
+
+ /* Inform the low side that the queue has at least one slot available.*/
+ if (nfy != NULL) {
+ nfy(iqp);
+ }
+
+ /* Giving a preemption chance in a controlled point.*/
+ osalSysUnlock();
+
+ r++;
+ if (--n == 0U) {
+ return r;
+ }
+
+ osalSysLock();
+ }
+}
+
+/**
+ * @brief Initializes an output queue.
+ * @details A Semaphore is internally initialized and works as a counter of
+ * the free bytes in the queue.
+ * @note The callback is invoked from within the S-Locked system state.
+ *
+ * @param[out] oqp pointer to an @p output_queue_t structure
+ * @param[in] bp pointer to a memory area allocated as queue buffer
+ * @param[in] size size of the queue buffer
+ * @param[in] onfy pointer to a callback function that is invoked when
+ * data is written to the queue. The value can be @p NULL.
+ * @param[in] link application defined pointer
+ *
+ * @init
+ */
+void oqObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size,
+ qnotify_t onfy, void *link) {
+
+ osalThreadQueueObjectInit(&oqp->q_waiting);
+ oqp->q_counter = size;
+ oqp->q_buffer = bp;
+ oqp->q_rdptr = bp;
+ oqp->q_wrptr = bp;
+ oqp->q_top = bp + size;
+ oqp->q_notify = onfy;
+ oqp->q_link = link;
+}
+
+/**
+ * @brief Resets an output queue.
+ * @details All the data in the output queue is erased and lost, any waiting
+ * thread is resumed with status @p MSG_RESET.
+ * @note A reset operation can be used by a low level driver in order to
+ * obtain immediate attention from the high level layers.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ *
+ * @iclass
+ */
+void oqResetI(output_queue_t *oqp) {
+
+ osalDbgCheckClassI();
+
+ oqp->q_rdptr = oqp->q_buffer;
+ oqp->q_wrptr = oqp->q_buffer;
+ oqp->q_counter = qSizeX(oqp);
+ osalThreadDequeueAllI(&oqp->q_waiting, MSG_RESET);
+}
+
+/**
+ * @brief Output queue write with timeout.
+ * @details This function writes a byte value to an output queue. If the queue
+ * is full then the calling thread is suspended until there is space
+ * in the queue or a timeout occurs.
+ * @note The callback is invoked after putting the character into the
+ * queue.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ * @param[in] b the byte value to be written in the queue
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the operation succeeded.
+ * @retval MSG_TIMEOUT if the specified time expired.
+ * @retval MSG_RESET if the queue has been reset.
+ *
+ * @api
+ */
+msg_t oqPutTimeout(output_queue_t *oqp, uint8_t b, systime_t timeout) {
+
+ osalSysLock();
+
+ /* Waiting until there is a slot available or a timeout occurs.*/
+ while (oqIsFullI(oqp)) {
+ msg_t msg = osalThreadEnqueueTimeoutS(&oqp->q_waiting, timeout);
+ if (msg < MSG_OK) {
+ osalSysUnlock();
+ return msg;
+ }
+ }
+
+ /* Putting the character into the queue.*/
+ oqp->q_counter--;
+ *oqp->q_wrptr++ = b;
+ if (oqp->q_wrptr >= oqp->q_top) {
+ oqp->q_wrptr = oqp->q_buffer;
+ }
+
+ /* Inform the low side that the queue has at least one character available.*/
+ if (oqp->q_notify != NULL) {
+ oqp->q_notify(oqp);
+ }
+
+ osalSysUnlock();
+
+ return MSG_OK;
+}
+
+/**
+ * @brief Output queue read.
+ * @details A byte value is read from the low end of an output queue.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ * @return The byte value from the queue.
+ * @retval MSG_TIMEOUT if the queue is empty.
+ *
+ * @iclass
+ */
+msg_t oqGetI(output_queue_t *oqp) {
+ uint8_t b;
+
+ osalDbgCheckClassI();
+
+ if (oqIsEmptyI(oqp)) {
+ return MSG_TIMEOUT;
+ }
+
+ oqp->q_counter++;
+ b = *oqp->q_rdptr++;
+ if (oqp->q_rdptr >= oqp->q_top) {
+ oqp->q_rdptr = oqp->q_buffer;
+ }
+
+ osalThreadDequeueNextI(&oqp->q_waiting, MSG_OK);
+
+ return (msg_t)b;
+}
+
+/**
+ * @brief Output queue write with timeout.
+ * @details The function writes data from a buffer to an output queue. The
+ * operation completes when the specified amount of data has been
+ * transferred or after the specified timeout or if the queue has
+ * been reset.
+ * @note The function is not atomic, if you need atomicity it is suggested
+ * to use a semaphore or a mutex for mutual exclusion.
+ * @note The callback is invoked after putting each character into the
+ * queue.
+ *
+ * @param[in] oqp pointer to an @p output_queue_t structure
+ * @param[in] bp pointer to the data buffer
+ * @param[in] n the maximum amount of data to be transferred, the
+ * value 0 is reserved
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The number of bytes effectively transferred.
+ *
+ * @api
+ */
+size_t oqWriteTimeout(output_queue_t *oqp, const uint8_t *bp,
+ size_t n, systime_t timeout) {
+ systime_t deadline;
+ qnotify_t nfy = oqp->q_notify;
+ size_t w = 0;
+
+ osalDbgCheck(n > 0U);
+
+ osalSysLock();
+
+ /* Time deadline for the whole operation, note the result is invalid
+ when timeout is TIME_INFINITE or TIME_IMMEDIATE but in that case
+ the deadline is not used.*/
+ deadline = osalOsGetSystemTimeX() + timeout;
+
+ while (true) {
+ msg_t msg;
+
+ while (oqIsFullI(oqp)) {
+ /* TIME_INFINITE and TIME_IMMEDIATE are handled differently, no
+ deadline.*/
+ if ((timeout == TIME_INFINITE) || (timeout == TIME_IMMEDIATE)) {
+ msg = osalThreadEnqueueTimeoutS(&oqp->q_waiting, timeout);
+ }
+ else {
+ systime_t next_timeout = deadline - osalOsGetSystemTimeX();
+
+ /* Handling the case where the system time went past the deadline,
+ in this case next becomes a very high number because the system
+ time is an unsigned type.*/
+ if (next_timeout > timeout) {
+ osalSysUnlock();
+ return w;
+ }
+
+ msg = osalThreadEnqueueTimeoutS(&oqp->q_waiting, next_timeout);
+ }
+
+ /* Anything except MSG_OK causes the operation to stop.*/
+ if (msg != MSG_OK) {
+ osalSysUnlock();
+ return w;
+ }
+ }
+
+ /* Putting the character into the queue.*/
+ oqp->q_counter--;
+ *oqp->q_wrptr++ = *bp++;
+ if (oqp->q_wrptr >= oqp->q_top) {
+ oqp->q_wrptr = oqp->q_buffer;
+ }
+
+ /* Inform the low side that the queue has at least one character available.*/
+ if (nfy != NULL) {
+ nfy(oqp);
+ }
+
+ /* Giving a preemption chance in a controlled point.*/
+ osalSysUnlock();
+
+ w++;
+ if (--n == 0U) {
+ return w;
+ }
+
+ osalSysLock();
+ }
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_rtc.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_rtc.c
new file mode 100644
index 0000000000..34b62c9889
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_rtc.c
@@ -0,0 +1,321 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file hal_rtc.c
+ * @brief RTC Driver code.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*
+ * Lookup table with months' length
+ */
+static const uint8_t month_len[12] = {
+ 31, 30, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief RTC Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void rtcInit(void) {
+
+ rtc_lld_init();
+}
+
+/**
+ * @brief Initializes a generic RTC driver object.
+ * @details The HW dependent part of the initialization has to be performed
+ * outside, usually in the hardware initialization code.
+ *
+ * @param[out] rtcp pointer to RTC driver structure
+ *
+ * @init
+ */
+void rtcObjectInit(RTCDriver *rtcp) {
+
+#if RTC_HAS_STORAGE == TRUE
+ rtcp->vmt = &_rtc_lld_vmt;
+#else
+ (void)rtcp;
+#endif
+}
+
+/**
+ * @brief Set current time.
+ * @note This function can be called from any context but limitations
+ * could be imposed by the low level implementation. It is
+ * guaranteed that the function can be called from thread
+ * context.
+ * @note The function can be reentrant or not reentrant depending on
+ * the low level implementation.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] timespec pointer to a @p RTCDateTime structure
+ *
+ * @special
+ */
+void rtcSetTime(RTCDriver *rtcp, const RTCDateTime *timespec) {
+
+ osalDbgCheck((rtcp != NULL) && (timespec != NULL));
+
+ rtc_lld_set_time(rtcp, timespec);
+}
+
+/**
+ * @brief Get current time.
+ * @note This function can be called from any context but limitations
+ * could be imposed by the low level implementation. It is
+ * guaranteed that the function can be called from thread
+ * context.
+ * @note The function can be reentrant or not reentrant depending on
+ * the low level implementation.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[out] timespec pointer to a @p RTCDateTime structure
+ *
+ * @special
+ */
+void rtcGetTime(RTCDriver *rtcp, RTCDateTime *timespec) {
+
+ osalDbgCheck((rtcp != NULL) && (timespec != NULL));
+
+ rtc_lld_get_time(rtcp, timespec);
+}
+
+#if (RTC_ALARMS > 0) || defined(__DOXYGEN__)
+/**
+ * @brief Set alarm time.
+ * @note This function can be called from any context but limitations
+ * could be imposed by the low level implementation. It is
+ * guaranteed that the function can be called from thread
+ * context.
+ * @note The function can be reentrant or not reentrant depending on
+ * the low level implementation.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] alarm alarm identifier
+ * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL
+ *
+ * @special
+ */
+void rtcSetAlarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ const RTCAlarm *alarmspec) {
+
+ osalDbgCheck((rtcp != NULL) && (alarm < (rtcalarm_t)RTC_ALARMS));
+
+ rtc_lld_set_alarm(rtcp, alarm, alarmspec);
+}
+
+/**
+ * @brief Get current alarm.
+ * @note If an alarm has not been set then the returned alarm specification
+ * is not meaningful.
+ * @note This function can be called from any context but limitations
+ * could be imposed by the low level implementation. It is
+ * guaranteed that the function can be called from thread
+ * context.
+ * @note The function can be reentrant or not reentrant depending on
+ * the low level implementation.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] alarm alarm identifier
+ * @param[out] alarmspec pointer to a @p RTCAlarm structure
+ *
+ * @special
+ */
+void rtcGetAlarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ RTCAlarm *alarmspec) {
+
+ osalDbgCheck((rtcp != NULL) &&
+ (alarm < (rtcalarm_t)RTC_ALARMS) &&
+ (alarmspec != NULL));
+
+ rtc_lld_get_alarm(rtcp, alarm, alarmspec);
+}
+#endif /* RTC_ALARMS > 0 */
+
+#if (RTC_SUPPORTS_CALLBACKS == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Enables or disables RTC callbacks.
+ * @details This function enables or disables the callback, use a @p NULL
+ * pointer in order to disable it.
+ * @note This function can be called from any context but limitations
+ * could be imposed by the low level implementation. It is
+ * guaranteed that the function can be called from thread
+ * context.
+ * @note The function can be reentrant or not reentrant depending on
+ * the low level implementation.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] callback callback function pointer or @p NULL
+ *
+ * @special
+ */
+void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback) {
+
+ osalDbgCheck(rtcp != NULL);
+
+ rtc_lld_set_callback(rtcp, callback);
+}
+#endif /* RTC_SUPPORTS_CALLBACKS == TRUE */
+
+/**
+ * @brief Convert @p RTCDateTime to broken-down time structure.
+ *
+ * @param[in] timespec pointer to a @p RTCDateTime structure
+ * @param[out] timp pointer to a broken-down time structure
+ * @param[out] tv_msec pointer to milliseconds value or @p NULL
+ *
+ * @api
+ */
+void rtcConvertDateTimeToStructTm(const RTCDateTime *timespec,
+ struct tm *timp,
+ uint32_t *tv_msec) {
+ int sec;
+
+ timp->tm_year = (int)timespec->year + (1980 - 1900);
+ timp->tm_mon = (int)timespec->month - 1;
+ timp->tm_mday = (int)timespec->day;
+ timp->tm_isdst = (int)timespec->dstflag;
+ timp->tm_wday = (int)timespec->dayofweek - 1;
+
+ sec = (int)timespec->millisecond / 1000;
+ timp->tm_hour = sec / 3600;
+ sec %= 3600;
+ timp->tm_min = sec / 60;
+ timp->tm_sec = sec % 60;
+
+ if (NULL != tv_msec) {
+ *tv_msec = (uint32_t)timespec->millisecond % 1000U;
+ }
+}
+
+/**
+ * @brief Convert broken-down time structure to @p RTCDateTime.
+ *
+ * @param[in] timp pointer to a broken-down time structure
+ * @param[in] tv_msec milliseconds value
+ * @param[out] timespec pointer to a @p RTCDateTime structure
+ *
+ * @api
+ */
+void rtcConvertStructTmToDateTime(const struct tm *timp,
+ uint32_t tv_msec,
+ RTCDateTime *timespec) {
+
+ /*lint -save -e9034 [10.4] Verified assignments to bit fields.*/
+ timespec->year = (uint32_t)timp->tm_year - (1980U - 1900U);
+ timespec->month = (uint32_t)timp->tm_mon + 1U;
+ timespec->day = (uint32_t)timp->tm_mday;
+ timespec->dayofweek = (uint32_t)timp->tm_wday + 1U;
+ if (-1 == timp->tm_isdst) {
+ timespec->dstflag = 0U; /* set zero if dst is unknown */
+ }
+ else {
+ timespec->dstflag = (uint32_t)timp->tm_isdst;
+ }
+ /*lint -restore*/
+ /*lint -save -e9033 [10.8] Verified assignments to bit fields.*/
+ timespec->millisecond = tv_msec + (uint32_t)(((timp->tm_hour * 3600) +
+ (timp->tm_min * 60) +
+ timp->tm_sec) * 1000);
+ /*lint -restore*/
+}
+
+/**
+ * @brief Get current time in format suitable for usage in FAT file system.
+ * @note The information about day of week and DST is lost in DOS
+ * format, the second field loses its least significant bit.
+ *
+ * @param[out] timespec pointer to a @p RTCDateTime structure
+ * @return FAT date/time value.
+ *
+ * @api
+ */
+uint32_t rtcConvertDateTimeToFAT(const RTCDateTime *timespec) {
+ uint32_t fattime;
+ uint32_t sec, min, hour, day, month;
+
+ sec = timespec->millisecond / 1000U;
+ hour = sec / 3600U;
+ sec %= 3600U;
+ min = sec / 60U;
+ sec %= 60U;
+ day = timespec->day;
+ month = timespec->month;
+
+ /* handle DST flag */
+ if (1U == timespec->dstflag) {
+ hour += 1U;
+ if (hour == 24U) {
+ hour = 0U;
+ day += 1U;
+ if (day > month_len[month - 1U]) {
+ day = 1U;
+ month += 1U;
+ }
+ }
+ }
+
+ fattime = sec >> 1U;
+ fattime |= min << 5U;
+ fattime |= hour << 11U;
+ fattime |= day << 16U;
+ fattime |= month << 21U;
+ fattime |= (uint32_t)timespec->year << 25U;
+
+ return fattime;
+}
+
+#endif /* HAL_USE_RTC == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_sdc.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_sdc.c
new file mode 100644
index 0000000000..3ad1e8a81b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_sdc.c
@@ -0,0 +1,1009 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_sdc.c
+ * @brief SDC Driver code.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#include
+
+#include "hal.h"
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/**
+ * @brief MMC switch mode.
+ */
+typedef enum {
+ MMC_SWITCH_COMMAND_SET = 0,
+ MMC_SWITCH_SET_BITS = 1,
+ MMC_SWITCH_CLEAR_BITS = 2,
+ MMC_SWITCH_WRITE_BYTE = 3
+} mmc_switch_t;
+
+/**
+ * @brief SDC switch mode.
+ */
+typedef enum {
+ SD_SWITCH_CHECK = 0,
+ SD_SWITCH_SET = 1
+} sd_switch_t;
+
+/**
+ * @brief SDC switch function.
+ */
+typedef enum {
+ SD_SWITCH_FUNCTION_SPEED = 0,
+ SD_SWITCH_FUNCTION_CMD_SYSTEM = 1,
+ SD_SWITCH_FUNCTION_DRIVER_STRENGTH = 2,
+ SD_SWITCH_FUNCTION_CURRENT_LIMIT = 3
+} sd_switch_function_t;
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Virtual methods table.
+ */
+static const struct SDCDriverVMT sdc_vmt = {
+ (bool (*)(void *))sdc_lld_is_card_inserted,
+ (bool (*)(void *))sdc_lld_is_write_protected,
+ (bool (*)(void *))sdcConnect,
+ (bool (*)(void *))sdcDisconnect,
+ (bool (*)(void *, uint32_t, uint8_t *, uint32_t))sdcRead,
+ (bool (*)(void *, uint32_t, const uint8_t *, uint32_t))sdcWrite,
+ (bool (*)(void *))sdcSync,
+ (bool (*)(void *, BlockDeviceInfo *))sdcGetInfo
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+/**
+ * @brief Detects card mode.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool mode_detect(SDCDriver *sdcp) {
+ uint32_t resp[1];
+
+ /* V2.0 cards detection.*/
+ if (!sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_IF_COND,
+ MMCSD_CMD8_PATTERN, resp)) {
+ sdcp->cardmode = SDC_MODE_CARDTYPE_SDV20;
+ /* Voltage verification.*/
+ if (((resp[0] >> 8U) & 0xFU) != 1U) {
+ return HAL_FAILED;
+ }
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ return HAL_FAILED;
+ }
+ }
+ else {
+ /* MMC or SD V1.1 detection.*/
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ sdcp->cardmode = SDC_MODE_CARDTYPE_MMC;
+ }
+ else {
+ sdcp->cardmode = SDC_MODE_CARDTYPE_SDV11;
+
+ /* Reset error flag illegal command.*/
+ sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0);
+ }
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Init procedure for MMC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool mmc_init(SDCDriver *sdcp) {
+ uint32_t ocr;
+ unsigned i;
+ uint32_t resp[1];
+
+ ocr = 0xC0FF8000U;
+ i = 0;
+ while (true) {
+ if (sdc_lld_send_cmd_short(sdcp, MMCSD_CMD_INIT, ocr, resp)) {
+ return HAL_FAILED;
+ }
+ if ((resp[0] & 0x80000000U) != 0U) {
+ if ((resp[0] & 0x40000000U) != 0U) {
+ sdcp->cardmode |= SDC_MODE_HIGH_CAPACITY;
+ }
+ break;
+ }
+ if (++i >= (unsigned)SDC_INIT_RETRY) {
+ return HAL_FAILED;
+ }
+ osalThreadSleepMilliseconds(10);
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Init procedure for SDC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_init(SDCDriver *sdcp) {
+ unsigned i;
+ uint32_t ocr;
+ uint32_t resp[1];
+
+ if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_SDV20) {
+ ocr = SDC_INIT_OCR_V20;
+ }
+ else {
+ ocr = SDC_INIT_OCR;
+ }
+
+ i = 0;
+ while (true) {
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ return HAL_FAILED;
+ }
+ if (sdc_lld_send_cmd_short(sdcp, MMCSD_CMD_APP_OP_COND, ocr, resp)) {
+ return HAL_FAILED;
+ }
+ if ((resp[0] & 0x80000000U) != 0U) {
+ if ((resp[0] & 0x40000000U) != 0U) {
+ sdcp->cardmode |= SDC_MODE_HIGH_CAPACITY;
+ }
+ break;
+ }
+ if (++i >= (unsigned)SDC_INIT_RETRY) {
+ return HAL_FAILED;
+ }
+ osalThreadSleepMilliseconds(10);
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Constructs CMD6 argument for MMC.
+ *
+ * @param[in] access EXT_CSD access mode
+ * @param[in] idx EXT_CSD byte number
+ * @param[in] value value to be written in target field
+ * @param[in] cmd_set switch current command set
+ *
+ * @return CMD6 argument.
+ *
+ * @notapi
+ */
+static uint32_t mmc_cmd6_construct(mmc_switch_t access, uint32_t idx,
+ uint32_t value, uint32_t cmd_set) {
+
+ osalDbgAssert(idx <= 191U, "This field is not writable");
+ osalDbgAssert(cmd_set < 8U, "This field has only 3 bits");
+
+ return ((uint32_t)access << 24U) | (idx << 16U) | (value << 8U) | cmd_set;
+}
+
+/**
+ * @brief Constructs CMD6 argument for SDC.
+ *
+ * @param[in] mode switch/test mode
+ * @param[in] function function number to be switched
+ * @param[in] value value to be written in target function
+ *
+ * @return CMD6 argument.
+ *
+ * @notapi
+ */
+static uint32_t sdc_cmd6_construct(sd_switch_t mode,
+ sd_switch_function_t function,
+ uint32_t value) {
+ uint32_t ret = 0xFFFFFF;
+
+ osalDbgAssert((value < 16U), "This field has only 4 bits");
+
+ ret &= ~((uint32_t)0xFU << ((uint32_t)function * 4U));
+ ret |= value << ((uint32_t)function * 4U);
+ return ret | ((uint32_t)mode << 31U);
+}
+
+/**
+ * @brief Extracts information from CMD6 answer.
+ *
+ * @param[in] function function number to be switched
+ * @param[in] buf buffer with answer
+ *
+ * @return extracted answer.
+ *
+ * @notapi
+ */
+static uint16_t sdc_cmd6_extract_info(sd_switch_function_t function,
+ const uint8_t *buf) {
+
+ unsigned start = 12U - ((unsigned)function * 2U);
+
+ return ((uint16_t)buf[start] << 8U) | (uint16_t)buf[start + 1U];
+}
+
+/**
+ * @brief Checks status after switching using CMD6.
+ *
+ * @param[in] function function number to be switched
+ * @param[in] buf buffer with answer
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_cmd6_check_status(sd_switch_function_t function,
+ const uint8_t *buf) {
+
+ uint32_t tmp;
+ uint32_t status;
+
+ tmp = ((uint32_t)buf[14] << 16U) |
+ ((uint32_t)buf[15] << 8U) |
+ (uint32_t)buf[16];
+ status = (tmp >> ((uint32_t)function * 4U)) & 0xFU;
+ if (0xFU != status) {
+ return HAL_SUCCESS;
+ }
+ return HAL_FAILED;
+}
+
+/**
+ * @brief Reads supported bus clock and switch SDC to appropriate mode.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[out] clk pointer to clock enum
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) {
+ uint32_t cmdarg;
+ const size_t N = 64;
+ uint8_t tmp[N];
+
+ /* Safe default.*/
+ *clk = SDC_CLK_25MHz;
+
+ /* Looks like only "high capacity" cards produce meaningful results during
+ this clock detection procedure.*/
+ if (0U == _mmcsd_get_slice(sdcp->csd, MMCSD_CSD_10_CSD_STRUCTURE_SLICE)) {
+ *clk = SDC_CLK_25MHz;
+ return HAL_SUCCESS;
+ }
+
+ /* Read switch functions' register.*/
+ if (sdc_lld_read_special(sdcp, tmp, N, MMCSD_CMD_SWITCH, 0)) {
+ return HAL_FAILED;
+ }
+
+ /* Check card capabilities parsing acquired data.*/
+ if ((sdc_cmd6_extract_info(SD_SWITCH_FUNCTION_SPEED, tmp) & 2U) == 2U) {
+ /* Construct command to set the bus speed.*/
+ cmdarg = sdc_cmd6_construct(SD_SWITCH_SET, SD_SWITCH_FUNCTION_SPEED, 1);
+
+ /* Write constructed command and read operation status in single call.*/
+ if (sdc_lld_read_special(sdcp, tmp, N, MMCSD_CMD_SWITCH, cmdarg)) {
+ return HAL_FAILED;
+ }
+
+ /* Check card answer for success status bits.*/
+ if (HAL_SUCCESS == sdc_cmd6_check_status(SD_SWITCH_FUNCTION_SPEED, tmp)) {
+ *clk = SDC_CLK_50MHz;
+ }
+ else {
+ *clk = SDC_CLK_25MHz;
+ }
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Reads supported bus clock and switch MMC to appropriate mode.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[out] clk pointer to clock enum
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool mmc_detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) {
+ uint32_t cmdarg;
+ uint32_t resp[1];
+ uint8_t *scratchpad = sdcp->config->scratchpad;
+
+ /* Safe default.*/
+ *clk = SDC_CLK_25MHz;
+
+ /* Use safe default when there is no space for data.*/
+ if (NULL == scratchpad) {
+ return HAL_SUCCESS;
+ }
+
+ cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 185, 1, 0);
+ if (!(sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SWITCH, cmdarg, resp) ||
+ MMCSD_R1_ERROR(resp[0]))) {
+ *clk = SDC_CLK_50MHz;
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Reads supported bus clock and switch card to appropriate mode.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[out] clk pointer to clock enum
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) {
+
+ if (SDC_MODE_CARDTYPE_MMC == (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK)) {
+ return mmc_detect_bus_clk(sdcp, clk);
+ }
+ return sdc_detect_bus_clk(sdcp, clk);
+}
+
+/**
+ * @brief Sets bus width for SDC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_set_bus_width(SDCDriver *sdcp) {
+ uint32_t resp[1];
+
+ if (SDC_MODE_1BIT == sdcp->config->bus_width) {
+ /* Nothing to do. Bus is already in 1bit mode.*/
+ return HAL_SUCCESS;
+ }
+ else if (SDC_MODE_4BIT == sdcp->config->bus_width) {
+ sdc_lld_set_bus_mode(sdcp, SDC_MODE_4BIT);
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, sdcp->rca, resp) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ return HAL_FAILED;
+ }
+
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BUS_WIDTH, 2, resp) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ return HAL_FAILED;
+ }
+ }
+ else {
+ /* SD card does not support 8bit bus.*/
+ return HAL_FAILED;
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Sets bus width for MMC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+static bool mmc_set_bus_width(SDCDriver *sdcp) {
+ uint32_t resp[1];
+ uint32_t cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 183, 0, 0);
+
+ switch (sdcp->config->bus_width) {
+ case SDC_MODE_1BIT:
+ /* Nothing to do. Bus is already in 1bit mode.*/
+ return HAL_SUCCESS;
+ case SDC_MODE_4BIT:
+ cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 183, 1, 0);
+ break;
+ case SDC_MODE_8BIT:
+ cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 183, 2, 0);
+ break;
+ default:
+ osalDbgAssert(false, "unexpected case");
+ break;
+ }
+
+ sdc_lld_set_bus_mode(sdcp, sdcp->config->bus_width);
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SWITCH, cmdarg, resp) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ return HAL_FAILED;
+ }
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Wait for the card to complete pending operations.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool _sdc_wait_for_transfer_state(SDCDriver *sdcp) {
+ uint32_t resp[1];
+
+ while (true) {
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_STATUS,
+ sdcp->rca, resp) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ return HAL_FAILED;
+ }
+
+ switch (MMCSD_R1_STS(resp[0])) {
+ case MMCSD_STS_TRAN:
+ return HAL_SUCCESS;
+ case MMCSD_STS_DATA:
+ case MMCSD_STS_RCV:
+ case MMCSD_STS_PRG:
+#if SDC_NICE_WAITING == TRUE
+ osalThreadSleepMilliseconds(1);
+#endif
+ continue;
+ default:
+ /* The card should have been initialized so any other state is not
+ valid and is reported as an error.*/
+ return HAL_FAILED;
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief SDC Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void sdcInit(void) {
+
+ sdc_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p SDCDriver structure.
+ *
+ * @param[out] sdcp pointer to the @p SDCDriver object
+ *
+ * @init
+ */
+void sdcObjectInit(SDCDriver *sdcp) {
+
+ sdcp->vmt = &sdc_vmt;
+ sdcp->state = BLK_STOP;
+ sdcp->errors = SDC_NO_ERROR;
+ sdcp->config = NULL;
+ sdcp->capacity = 0;
+}
+
+/**
+ * @brief Configures and activates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] config pointer to the @p SDCConfig object, can be @p NULL if
+ * the driver supports a default configuration or
+ * requires no configuration
+ *
+ * @api
+ */
+void sdcStart(SDCDriver *sdcp, const SDCConfig *config) {
+
+ osalDbgCheck(sdcp != NULL);
+
+ osalSysLock();
+ osalDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE),
+ "invalid state");
+ sdcp->config = config;
+ sdc_lld_start(sdcp);
+ sdcp->state = BLK_ACTIVE;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @api
+ */
+void sdcStop(SDCDriver *sdcp) {
+
+ osalDbgCheck(sdcp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE),
+ "invalid state");
+
+ sdc_lld_stop(sdcp);
+ sdcp->config = NULL;
+ sdcp->state = BLK_STOP;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Performs the initialization procedure on the inserted card.
+ * @details This function should be invoked when a card is inserted and
+ * brings the driver in the @p BLK_READY state where it is possible
+ * to perform read and write operations.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @api
+ */
+bool sdcConnect(SDCDriver *sdcp) {
+ uint32_t resp[1];
+ sdcbusclk_t clk = SDC_CLK_25MHz;
+
+ osalDbgCheck(sdcp != NULL);
+ osalDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY),
+ "invalid state");
+
+ /* Connection procedure in progress.*/
+ sdcp->state = BLK_CONNECTING;
+
+ /* Card clock initialization.*/
+ sdc_lld_start_clk(sdcp);
+
+ /* Enforces the initial card state.*/
+ sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0);
+
+ /* Detect card type.*/
+ if (HAL_FAILED == mode_detect(sdcp)) {
+ goto failed;
+ }
+
+ /* Perform specific initialization procedure.*/
+ if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_MMC) {
+ if (HAL_FAILED == mmc_init(sdcp)) {
+ goto failed;
+ }
+ }
+ else {
+ if (HAL_FAILED == sdc_init(sdcp)) {
+ goto failed;
+ }
+ }
+
+ /* Reads CID.*/
+ if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_ALL_SEND_CID, 0, sdcp->cid)) {
+ goto failed;
+ }
+
+ /* Asks for the RCA.*/
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_RELATIVE_ADDR,
+ 0, &sdcp->rca)) {
+ goto failed;
+ }
+
+ /* Reads CSD.*/
+ if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_SEND_CSD,
+ sdcp->rca, sdcp->csd)) {
+ goto failed;
+ }
+
+ /* Selects the card for operations.*/
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEL_DESEL_CARD,
+ sdcp->rca, resp)) {
+ goto failed;
+ }
+
+ /* Switches to high speed.*/
+ if (HAL_SUCCESS != detect_bus_clk(sdcp, &clk)) {
+ goto failed;
+ }
+ sdc_lld_set_data_clk(sdcp, clk);
+
+ /* Reads extended CSD if needed and possible.*/
+ if (SDC_MODE_CARDTYPE_MMC == (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK)) {
+
+ /* The card is a MMC, checking if it is a large device.*/
+ if (_mmcsd_get_slice(sdcp->csd, MMCSD_CSD_MMC_CSD_STRUCTURE_SLICE) > 1U) {
+ uint8_t *ext_csd = sdcp->config->scratchpad;
+
+ /* Size detection requires the buffer.*/
+ if (NULL == ext_csd) {
+ goto failed;
+ }
+
+ if(sdc_lld_read_special(sdcp, ext_csd, 512, MMCSD_CMD_SEND_EXT_CSD, 0)) {
+ goto failed;
+ }
+
+ /* Capacity from the EXT_CSD.*/
+ sdcp->capacity = _mmcsd_get_capacity_ext(ext_csd);
+ }
+ else {
+ /* Capacity from the normal CSD.*/
+ sdcp->capacity = _mmcsd_get_capacity(sdcp->csd);
+ }
+ }
+ else {
+ /* The card is an SDC, capacity from the normal CSD.*/
+ sdcp->capacity = _mmcsd_get_capacity(sdcp->csd);
+ }
+
+ /* Block length fixed at 512 bytes.*/
+ if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BLOCKLEN,
+ MMCSD_BLOCK_SIZE, resp) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ goto failed;
+ }
+
+ /* Switches to wide bus mode.*/
+ switch (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) {
+ case SDC_MODE_CARDTYPE_SDV11:
+ case SDC_MODE_CARDTYPE_SDV20:
+ if (HAL_FAILED == sdc_set_bus_width(sdcp)) {
+ goto failed;
+ }
+ break;
+ case SDC_MODE_CARDTYPE_MMC:
+ if (HAL_FAILED == mmc_set_bus_width(sdcp)) {
+ goto failed;
+ }
+ break;
+ default:
+ /* Unknown type.*/
+ goto failed;
+ }
+
+ /* Initialization complete.*/
+ sdcp->state = BLK_READY;
+ return HAL_SUCCESS;
+
+ /* Connection failed, state reset to BLK_ACTIVE.*/
+failed:
+ sdc_lld_stop_clk(sdcp);
+ sdcp->state = BLK_ACTIVE;
+ return HAL_FAILED;
+}
+
+/**
+ * @brief Brings the driver in a state safe for card removal.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @api
+ */
+bool sdcDisconnect(SDCDriver *sdcp) {
+
+ osalDbgCheck(sdcp != NULL);
+
+ osalSysLock();
+ osalDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY),
+ "invalid state");
+ if (sdcp->state == BLK_ACTIVE) {
+ osalSysUnlock();
+ return HAL_SUCCESS;
+ }
+ sdcp->state = BLK_DISCONNECTING;
+ osalSysUnlock();
+
+ /* Waits for eventual pending operations completion.*/
+ if (_sdc_wait_for_transfer_state(sdcp)) {
+ sdc_lld_stop_clk(sdcp);
+ sdcp->state = BLK_ACTIVE;
+ return HAL_FAILED;
+ }
+
+ /* Card clock stopped.*/
+ sdc_lld_stop_clk(sdcp);
+ sdcp->state = BLK_ACTIVE;
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Reads one or more blocks.
+ * @pre The driver must be in the @p BLK_READY state after a successful
+ * sdcConnect() invocation.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to read
+ * @param[out] buf pointer to the read buffer
+ * @param[in] n number of blocks to read
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @api
+ */
+bool sdcRead(SDCDriver *sdcp, uint32_t startblk, uint8_t *buf, uint32_t n) {
+ bool status;
+
+ osalDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0U));
+ osalDbgAssert(sdcp->state == BLK_READY, "invalid state");
+
+ if ((startblk + n - 1U) > sdcp->capacity) {
+ sdcp->errors |= SDC_OVERFLOW_ERROR;
+ return HAL_FAILED;
+ }
+
+ /* Read operation in progress.*/
+ sdcp->state = BLK_READING;
+
+ status = sdc_lld_read(sdcp, startblk, buf, n);
+
+ /* Read operation finished.*/
+ sdcp->state = BLK_READY;
+ return status;
+}
+
+/**
+ * @brief Writes one or more blocks.
+ * @pre The driver must be in the @p BLK_READY state after a successful
+ * sdcConnect() invocation.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to write
+ * @param[out] buf pointer to the write buffer
+ * @param[in] n number of blocks to write
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @api
+ */
+bool sdcWrite(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n) {
+ bool status;
+
+ osalDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0U));
+ osalDbgAssert(sdcp->state == BLK_READY, "invalid state");
+
+ if ((startblk + n - 1U) > sdcp->capacity) {
+ sdcp->errors |= SDC_OVERFLOW_ERROR;
+ return HAL_FAILED;
+ }
+
+ /* Write operation in progress.*/
+ sdcp->state = BLK_WRITING;
+
+ status = sdc_lld_write(sdcp, startblk, buf, n);
+
+ /* Write operation finished.*/
+ sdcp->state = BLK_READY;
+ return status;
+}
+
+/**
+ * @brief Returns the errors mask associated to the previous operation.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @return The errors mask.
+ *
+ * @api
+ */
+sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp) {
+ sdcflags_t flags;
+
+ osalDbgCheck(sdcp != NULL);
+ osalDbgAssert(sdcp->state == BLK_READY, "invalid state");
+
+ osalSysLock();
+ flags = sdcp->errors;
+ sdcp->errors = SDC_NO_ERROR;
+ osalSysUnlock();
+ return flags;
+}
+
+/**
+ * @brief Waits for card idle condition.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
+ *
+ * @api
+ */
+bool sdcSync(SDCDriver *sdcp) {
+ bool result;
+
+ osalDbgCheck(sdcp != NULL);
+
+ if (sdcp->state != BLK_READY) {
+ return HAL_FAILED;
+ }
+
+ /* Synchronization operation in progress.*/
+ sdcp->state = BLK_SYNCING;
+
+ result = sdc_lld_sync(sdcp);
+
+ /* Synchronization operation finished.*/
+ sdcp->state = BLK_READY;
+ return result;
+}
+
+/**
+ * @brief Returns the media info.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[out] bdip pointer to a @p BlockDeviceInfo structure
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
+ *
+ * @api
+ */
+bool sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip) {
+
+ osalDbgCheck((sdcp != NULL) && (bdip != NULL));
+
+ if (sdcp->state != BLK_READY) {
+ return HAL_FAILED;
+ }
+
+ bdip->blk_num = sdcp->capacity;
+ bdip->blk_size = MMCSD_BLOCK_SIZE;
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Erases the supplied blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk starting block number
+ * @param[in] endblk ending block number
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
+ *
+ * @api
+ */
+bool sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) {
+ uint32_t resp[1];
+
+ osalDbgCheck((sdcp != NULL));
+ osalDbgAssert(sdcp->state == BLK_READY, "invalid state");
+
+ /* Erase operation in progress.*/
+ sdcp->state = BLK_WRITING;
+
+ /* Handling command differences between HC and normal cards.*/
+ if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) != 0U) {
+ startblk *= MMCSD_BLOCK_SIZE;
+ endblk *= MMCSD_BLOCK_SIZE;
+ }
+
+ if (_sdc_wait_for_transfer_state(sdcp)) {
+ goto failed;
+ }
+
+ if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_START,
+ startblk, resp) != HAL_SUCCESS) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ goto failed;
+ }
+
+ if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_END,
+ endblk, resp) != HAL_SUCCESS) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ goto failed;
+ }
+
+ if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE,
+ 0, resp) != HAL_SUCCESS) ||
+ MMCSD_R1_ERROR(resp[0])) {
+ goto failed;
+ }
+
+ /* Quick sleep to allow it to transition to programming or receiving state */
+ /* TODO: ??????????????????????????? */
+
+ /* Wait for it to return to transfer state to indicate it has finished erasing */
+ if (_sdc_wait_for_transfer_state(sdcp)) {
+ goto failed;
+ }
+
+ sdcp->state = BLK_READY;
+ return HAL_SUCCESS;
+
+failed:
+ sdcp->state = BLK_READY;
+ return HAL_FAILED;
+}
+
+#endif /* HAL_USE_SDC == TRUE */
+
+/** @} */
+
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/serial.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_serial.c
similarity index 51%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/serial.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_serial.c
index 533adb4372..fd3c92cbd9 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/serial.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_serial.c
@@ -1,42 +1,30 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file serial.c
+ * @file hal_serial.c
* @brief Serial Driver code.
*
* @addtogroup SERIAL
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -59,51 +47,51 @@
* queue-level function or macro.
*/
-static size_t write(void *ip, const uint8_t *bp, size_t n) {
+static size_t _write(void *ip, const uint8_t *bp, size_t n) {
- return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp,
- n, TIME_INFINITE);
+ return oqWriteTimeout(&((SerialDriver *)ip)->oqueue, bp,
+ n, TIME_INFINITE);
}
-static size_t read(void *ip, uint8_t *bp, size_t n) {
+static size_t _read(void *ip, uint8_t *bp, size_t n) {
- return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp,
- n, TIME_INFINITE);
+ return iqReadTimeout(&((SerialDriver *)ip)->iqueue, bp,
+ n, TIME_INFINITE);
}
-static msg_t put(void *ip, uint8_t b) {
+static msg_t _put(void *ip, uint8_t b) {
- return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, TIME_INFINITE);
+ return oqPutTimeout(&((SerialDriver *)ip)->oqueue, b, TIME_INFINITE);
}
-static msg_t get(void *ip) {
+static msg_t _get(void *ip) {
- return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, TIME_INFINITE);
+ return iqGetTimeout(&((SerialDriver *)ip)->iqueue, TIME_INFINITE);
}
-static msg_t putt(void *ip, uint8_t b, systime_t timeout) {
+static msg_t _putt(void *ip, uint8_t b, systime_t timeout) {
- return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout);
+ return oqPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout);
}
-static msg_t gett(void *ip, systime_t timeout) {
+static msg_t _gett(void *ip, systime_t timeout) {
- return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, timeout);
+ return iqGetTimeout(&((SerialDriver *)ip)->iqueue, timeout);
}
-static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) {
+static size_t _writet(void *ip, const uint8_t *bp, size_t n, systime_t timeout) {
- return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, time);
+ return oqWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, timeout);
}
-static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) {
+static size_t _readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) {
- return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, time);
+ return iqReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, timeout);
}
static const struct SerialDriverVMT vmt = {
- write, read, put, get,
- putt, gett, writet, readt
+ _write, _read, _put, _get,
+ _putt, _gett, _writet, _readt
};
/*===========================================================================*/
@@ -137,14 +125,25 @@ void sdInit(void) {
*
* @init
*/
+#if !defined(SERIAL_ADVANCED_BUFFERING_SUPPORT) || \
+ (SERIAL_ADVANCED_BUFFERING_SUPPORT == FALSE) || \
+ defined(__DOXYGEN__)
void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) {
sdp->vmt = &vmt;
- chEvtInit(&sdp->event);
+ osalEventObjectInit(&sdp->event);
sdp->state = SD_STOP;
- chIQInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify, sdp);
- chOQInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify, sdp);
+ iqObjectInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify, sdp);
+ oqObjectInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify, sdp);
}
+#else
+void sdObjectInit(SerialDriver *sdp) {
+
+ sdp->vmt = &vmt;
+ osalEventObjectInit(&sdp->event);
+ sdp->state = SD_STOP;
+}
+#endif
/**
* @brief Configures and starts the driver.
@@ -158,21 +157,20 @@ void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) {
*/
void sdStart(SerialDriver *sdp, const SerialConfig *config) {
- chDbgCheck(sdp != NULL, "sdStart");
+ osalDbgCheck(sdp != NULL);
- chSysLock();
- chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY),
- "sdStart(), #1",
- "invalid state");
+ osalSysLock();
+ osalDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY),
+ "invalid state");
sd_lld_start(sdp, config);
sdp->state = SD_READY;
- chSysUnlock();
+ osalSysUnlock();
}
/**
* @brief Stops the driver.
* @details Any thread waiting on the driver's queues will be awakened with
- * the message @p Q_RESET.
+ * the message @p MSG_RESET.
*
* @param[in] sdp pointer to a @p SerialDriver object
*
@@ -180,18 +178,20 @@ void sdStart(SerialDriver *sdp, const SerialConfig *config) {
*/
void sdStop(SerialDriver *sdp) {
- chDbgCheck(sdp != NULL, "sdStop");
+ osalDbgCheck(sdp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY),
+ "invalid state");
- chSysLock();
- chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY),
- "sdStop(), #1",
- "invalid state");
sd_lld_stop(sdp);
sdp->state = SD_STOP;
- chOQResetI(&sdp->oqueue);
- chIQResetI(&sdp->iqueue);
- chSchRescheduleS();
- chSysUnlock();
+ oqResetI(&sdp->oqueue);
+ iqResetI(&sdp->iqueue);
+ osalOsRescheduleS();
+
+ osalSysUnlock();
}
/**
@@ -212,13 +212,13 @@ void sdStop(SerialDriver *sdp) {
*/
void sdIncomingDataI(SerialDriver *sdp, uint8_t b) {
- chDbgCheckClassI();
- chDbgCheck(sdp != NULL, "sdIncomingDataI");
+ osalDbgCheckClassI();
+ osalDbgCheck(sdp != NULL);
- if (chIQIsEmptyI(&sdp->iqueue))
+ if (iqIsEmptyI(&sdp->iqueue))
chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
- if (chIQPutI(&sdp->iqueue, b) < Q_OK)
- chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+ if (iqPutI(&sdp->iqueue, b) < MSG_OK)
+ chnAddFlagsI(sdp, SD_QUEUE_FULL_ERROR);
}
/**
@@ -231,7 +231,7 @@ void sdIncomingDataI(SerialDriver *sdp, uint8_t b) {
*
* @param[in] sdp pointer to a @p SerialDriver structure
* @return The byte value read from the driver's output queue.
- * @retval Q_EMPTY if the queue is empty (the lower driver usually
+ * @retval MSG_TIMEOUT if the queue is empty (the lower driver usually
* disables the interrupt source when this happens).
*
* @iclass
@@ -239,15 +239,65 @@ void sdIncomingDataI(SerialDriver *sdp, uint8_t b) {
msg_t sdRequestDataI(SerialDriver *sdp) {
msg_t b;
- chDbgCheckClassI();
- chDbgCheck(sdp != NULL, "sdRequestDataI");
+ osalDbgCheckClassI();
+ osalDbgCheck(sdp != NULL);
- b = chOQGetI(&sdp->oqueue);
- if (b < Q_OK)
+ b = oqGetI(&sdp->oqueue);
+ if (b < MSG_OK)
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
return b;
}
-#endif /* HAL_USE_SERIAL */
+/**
+ * @brief Direct output check on a @p SerialDriver.
+ * @note This function bypasses the indirect access to the channel and
+ * checks directly the output queue. This is faster but cannot
+ * be used to check different channels implementations.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver structure
+ * @return The queue status.
+ * @retval false if the next write operation would not block.
+ * @retval true if the next write operation would block.
+ *
+ * @deprecated
+ *
+ * @api
+ */
+bool sdPutWouldBlock(SerialDriver *sdp) {
+ bool b;
+
+ osalSysLock();
+ b = oqIsFullI(&sdp->oqueue);
+ osalSysUnlock();
+
+ return b;
+}
+
+/**
+ * @brief Direct input check on a @p SerialDriver.
+ * @note This function bypasses the indirect access to the channel and
+ * checks directly the input queue. This is faster but cannot
+ * be used to check different channels implementations.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver structure
+ * @return The queue status.
+ * @retval false if the next write operation would not block.
+ * @retval true if the next write operation would block.
+ *
+ * @deprecated
+ *
+ * @api
+ */
+bool sdGetWouldBlock(SerialDriver *sdp) {
+ bool b;
+
+ osalSysLock();
+ b = iqIsEmptyI(&sdp->iqueue);
+ osalSysUnlock();
+
+ return b;
+}
+
+#endif /* HAL_USE_SERIAL == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_serial_usb.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_serial_usb.c
new file mode 100644
index 0000000000..5714c35d26
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_serial_usb.c
@@ -0,0 +1,495 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_serial_usb.c
+ * @brief Serial over USB Driver code.
+ *
+ * @addtogroup SERIAL_USB
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_SERIAL_USB == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*
+ * Current Line Coding.
+ */
+static cdc_linecoding_t linecoding = {
+ {0x00, 0x96, 0x00, 0x00}, /* 38400. */
+ LC_STOP_1, LC_PARITY_NONE, 8
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static bool sdu_start_receive(SerialUSBDriver *sdup) {
+ uint8_t *buf;
+
+ /* If the USB driver is not in the appropriate state then transactions
+ must not be started.*/
+ if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) ||
+ (sdup->state != SDU_READY)) {
+ return true;
+ }
+
+ /* Checking if there is already a transaction ongoing on the endpoint.*/
+ if (usbGetReceiveStatusI(sdup->config->usbp, sdup->config->bulk_in)) {
+ return true;
+ }
+
+ /* Checking if there is a buffer ready for incoming data.*/
+ buf = ibqGetEmptyBufferI(&sdup->ibqueue);
+ if (buf == NULL) {
+ return true;
+ }
+
+ /* Buffer found, starting a new transaction.*/
+ usbStartReceiveI(sdup->config->usbp, sdup->config->bulk_out,
+ buf, SERIAL_USB_BUFFERS_SIZE);
+
+ return false;
+}
+
+/*
+ * Interface implementation.
+ */
+
+static size_t _write(void *ip, const uint8_t *bp, size_t n) {
+
+ return obqWriteTimeout(&((SerialUSBDriver *)ip)->obqueue, bp,
+ n, TIME_INFINITE);
+}
+
+static size_t _read(void *ip, uint8_t *bp, size_t n) {
+
+ return ibqReadTimeout(&((SerialUSBDriver *)ip)->ibqueue, bp,
+ n, TIME_INFINITE);
+}
+
+static msg_t _put(void *ip, uint8_t b) {
+
+ return obqPutTimeout(&((SerialUSBDriver *)ip)->obqueue, b, TIME_INFINITE);
+}
+
+static msg_t _get(void *ip) {
+
+ return ibqGetTimeout(&((SerialUSBDriver *)ip)->ibqueue, TIME_INFINITE);
+}
+
+static msg_t _putt(void *ip, uint8_t b, systime_t timeout) {
+
+ return obqPutTimeout(&((SerialUSBDriver *)ip)->obqueue, b, timeout);
+}
+
+static msg_t _gett(void *ip, systime_t timeout) {
+
+ return ibqGetTimeout(&((SerialUSBDriver *)ip)->ibqueue, timeout);
+}
+
+static size_t _writet(void *ip, const uint8_t *bp, size_t n, systime_t timeout) {
+
+ return obqWriteTimeout(&((SerialUSBDriver *)ip)->obqueue, bp, n, timeout);
+}
+
+static size_t _readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) {
+
+ return ibqReadTimeout(&((SerialUSBDriver *)ip)->ibqueue, bp, n, timeout);
+}
+
+static const struct SerialUSBDriverVMT vmt = {
+ _write, _read, _put, _get,
+ _putt, _gett, _writet, _readt
+};
+
+/**
+ * @brief Notification of empty buffer released into the input buffers queue.
+ *
+ * @param[in] bqp the buffers queue pointer.
+ */
+static void ibnotify(io_buffers_queue_t *bqp) {
+ SerialUSBDriver *sdup = bqGetLinkX(bqp);
+ (void) sdu_start_receive(sdup);
+}
+
+/**
+ * @brief Notification of filled buffer inserted into the output buffers queue.
+ *
+ * @param[in] bqp the buffers queue pointer.
+ */
+static void obnotify(io_buffers_queue_t *bqp) {
+ size_t n;
+ SerialUSBDriver *sdup = bqGetLinkX(bqp);
+
+ /* If the USB driver is not in the appropriate state then transactions
+ must not be started.*/
+ if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) ||
+ (sdup->state != SDU_READY)) {
+ return;
+ }
+
+ /* Checking if there is already a transaction ongoing on the endpoint.*/
+ if (!usbGetTransmitStatusI(sdup->config->usbp, sdup->config->bulk_in)) {
+ /* Trying to get a full buffer.*/
+ uint8_t *buf = obqGetFullBufferI(&sdup->obqueue, &n);
+ if (buf != NULL) {
+ /* Buffer found, starting a new transaction.*/
+ usbStartTransmitI(sdup->config->usbp, sdup->config->bulk_in, buf, n);
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void sduInit(void) {
+}
+
+/**
+ * @brief Initializes a generic full duplex driver object.
+ * @details The HW dependent part of the initialization has to be performed
+ * outside, usually in the hardware initialization code.
+ *
+ * @param[out] sdup pointer to a @p SerialUSBDriver structure
+ *
+ * @init
+ */
+void sduObjectInit(SerialUSBDriver *sdup) {
+
+ sdup->vmt = &vmt;
+ osalEventObjectInit(&sdup->event);
+ sdup->state = SDU_STOP;
+ ibqObjectInit(&sdup->ibqueue, true, sdup->ib,
+ SERIAL_USB_BUFFERS_SIZE, SERIAL_USB_BUFFERS_NUMBER,
+ ibnotify, sdup);
+ obqObjectInit(&sdup->obqueue, true, sdup->ob,
+ SERIAL_USB_BUFFERS_SIZE, SERIAL_USB_BUFFERS_NUMBER,
+ obnotify, sdup);
+}
+
+/**
+ * @brief Configures and starts the driver.
+ *
+ * @param[in] sdup pointer to a @p SerialUSBDriver object
+ * @param[in] config the serial over USB driver configuration
+ *
+ * @api
+ */
+void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config) {
+ USBDriver *usbp = config->usbp;
+
+ osalDbgCheck(sdup != NULL);
+
+ osalSysLock();
+ osalDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY),
+ "invalid state");
+ usbp->in_params[config->bulk_in - 1U] = sdup;
+ usbp->out_params[config->bulk_out - 1U] = sdup;
+ if (config->int_in > 0U) {
+ usbp->in_params[config->int_in - 1U] = sdup;
+ }
+ sdup->config = config;
+ sdup->state = SDU_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Stops the driver.
+ * @details Any thread waiting on the driver's queues will be awakened with
+ * the message @p MSG_RESET.
+ *
+ * @param[in] sdup pointer to a @p SerialUSBDriver object
+ *
+ * @api
+ */
+void sduStop(SerialUSBDriver *sdup) {
+ USBDriver *usbp = sdup->config->usbp;
+
+ osalDbgCheck(sdup != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY),
+ "invalid state");
+
+ /* Driver in stopped state.*/
+ usbp->in_params[sdup->config->bulk_in - 1U] = NULL;
+ usbp->out_params[sdup->config->bulk_out - 1U] = NULL;
+ if (sdup->config->int_in > 0U) {
+ usbp->in_params[sdup->config->int_in - 1U] = NULL;
+ }
+ sdup->config = NULL;
+ sdup->state = SDU_STOP;
+
+ /* Enforces a disconnection.*/
+ chnAddFlagsI(sdup, CHN_DISCONNECTED);
+ ibqResetI(&sdup->ibqueue);
+ obqResetI(&sdup->obqueue);
+ osalOsRescheduleS();
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief USB device suspend handler.
+ * @details Generates a @p CHN_DISCONNECT event and puts queues in
+ * non-blocking mode, this way the application cannot get stuck
+ * in the middle of an I/O operations.
+ * @note If this function is not called from an ISR then an explicit call
+ * to @p osalOsRescheduleS() in necessary afterward.
+ *
+ * @param[in] sdup pointer to a @p SerialUSBDriver object
+ *
+ * @iclass
+ */
+void sduSuspendHookI(SerialUSBDriver *sdup) {
+
+ chnAddFlagsI(sdup, CHN_DISCONNECTED);
+ bqSuspendI(&sdup->ibqueue);
+ bqSuspendI(&sdup->obqueue);
+}
+
+/**
+ * @brief USB device wakeup handler.
+ * @details Generates a @p CHN_CONNECT event and resumes normal queues
+ * operations.
+ *
+ * @note If this function is not called from an ISR then an explicit call
+ * to @p osalOsRescheduleS() in necessary afterward.
+ *
+ * @param[in] sdup pointer to a @p SerialUSBDriver object
+ *
+ * @iclass
+ */
+void sduWakeupHookI(SerialUSBDriver *sdup) {
+
+ chnAddFlagsI(sdup, CHN_CONNECTED);
+ bqResumeX(&sdup->ibqueue);
+ bqResumeX(&sdup->obqueue);
+}
+
+/**
+ * @brief USB device configured handler.
+ *
+ * @param[in] sdup pointer to a @p SerialUSBDriver object
+ *
+ * @iclass
+ */
+void sduConfigureHookI(SerialUSBDriver *sdup) {
+
+ ibqResetI(&sdup->ibqueue);
+ bqResumeX(&sdup->ibqueue);
+ obqResetI(&sdup->obqueue);
+ bqResumeX(&sdup->obqueue);
+ chnAddFlagsI(sdup, CHN_CONNECTED);
+ (void) sdu_start_receive(sdup);
+}
+
+/**
+ * @brief Default requests hook.
+ * @details Applications wanting to use the Serial over USB driver can use
+ * this function as requests hook in the USB configuration.
+ * The following requests are emulated:
+ * - CDC_GET_LINE_CODING.
+ * - CDC_SET_LINE_CODING.
+ * - CDC_SET_CONTROL_LINE_STATE.
+ * .
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return The hook status.
+ * @retval true Message handled internally.
+ * @retval false Message not handled.
+ */
+bool sduRequestsHook(USBDriver *usbp) {
+
+ if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) {
+ switch (usbp->setup[1]) {
+ case CDC_GET_LINE_CODING:
+ usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL);
+ return true;
+ case CDC_SET_LINE_CODING:
+ usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL);
+ return true;
+ case CDC_SET_CONTROL_LINE_STATE:
+ /* Nothing to do, there are no control lines.*/
+ usbSetupTransfer(usbp, NULL, 0, NULL);
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+}
+
+/**
+ * @brief SOF handler.
+ * @details The SOF interrupt is used for automatic flushing of incomplete
+ * buffers pending in the output queue.
+ *
+ * @param[in] sdup pointer to a @p SerialUSBDriver object
+ *
+ * @iclass
+ */
+void sduSOFHookI(SerialUSBDriver *sdup) {
+
+ /* If the USB driver is not in the appropriate state then transactions
+ must not be started.*/
+ if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) ||
+ (sdup->state != SDU_READY)) {
+ return;
+ }
+
+ /* If there is already a transaction ongoing then another one cannot be
+ started.*/
+ if (usbGetTransmitStatusI(sdup->config->usbp, sdup->config->bulk_in)) {
+ return;
+ }
+
+ /* Checking if there only a buffer partially filled, if so then it is
+ enforced in the queue and transmitted.*/
+ if (obqTryFlushI(&sdup->obqueue)) {
+ size_t n;
+ uint8_t *buf = obqGetFullBufferI(&sdup->obqueue, &n);
+
+ osalDbgAssert(buf != NULL, "queue is empty");
+
+ usbStartTransmitI(sdup->config->usbp, sdup->config->bulk_in, buf, n);
+ }
+}
+
+/**
+ * @brief Default data transmitted callback.
+ * @details The application must use this function as callback for the IN
+ * data endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep IN endpoint number
+ */
+void sduDataTransmitted(USBDriver *usbp, usbep_t ep) {
+ uint8_t *buf;
+ size_t n;
+ SerialUSBDriver *sdup = usbp->in_params[ep - 1U];
+
+ if (sdup == NULL) {
+ return;
+ }
+
+ osalSysLockFromISR();
+
+ /* Signaling that space is available in the output queue.*/
+ chnAddFlagsI(sdup, CHN_OUTPUT_EMPTY);
+
+ /* Freeing the buffer just transmitted, if it was not a zero size packet.*/
+ if (usbp->epc[ep]->in_state->txsize > 0U) {
+ obqReleaseEmptyBufferI(&sdup->obqueue);
+ }
+
+ /* Checking if there is a buffer ready for transmission.*/
+ buf = obqGetFullBufferI(&sdup->obqueue, &n);
+
+ if (buf != NULL) {
+ /* The endpoint cannot be busy, we are in the context of the callback,
+ so it is safe to transmit without a check.*/
+ usbStartTransmitI(usbp, ep, buf, n);
+ }
+ else if ((usbp->epc[ep]->in_state->txsize > 0U) &&
+ ((usbp->epc[ep]->in_state->txsize &
+ ((size_t)usbp->epc[ep]->in_maxsize - 1U)) == 0U)) {
+ /* Transmit zero sized packet in case the last one has maximum allowed
+ size. Otherwise the recipient may expect more data coming soon and
+ not return buffered data to app. See section 5.8.3 Bulk Transfer
+ Packet Size Constraints of the USB Specification document.*/
+ usbStartTransmitI(usbp, ep, usbp->setup, 0);
+
+ }
+ else {
+ /* Nothing to transmit.*/
+ }
+
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Default data received callback.
+ * @details The application must use this function as callback for the OUT
+ * data endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep OUT endpoint number
+ */
+void sduDataReceived(USBDriver *usbp, usbep_t ep) {
+ SerialUSBDriver *sdup = usbp->out_params[ep - 1U];
+ if (sdup == NULL) {
+ return;
+ }
+
+ osalSysLockFromISR();
+
+ /* Signaling that data is available in the input queue.*/
+ chnAddFlagsI(sdup, CHN_INPUT_AVAILABLE);
+
+ /* Posting the filled buffer in the queue.*/
+ ibqPostFullBufferI(&sdup->ibqueue,
+ usbGetReceiveTransactionSizeX(sdup->config->usbp,
+ sdup->config->bulk_out));
+
+ /* The endpoint cannot be busy, we are in the context of the callback,
+ so a packet is in the buffer for sure. Trying to get a free buffer
+ for the next transaction.*/
+ (void) sdu_start_receive(sdup);
+
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Default data received callback.
+ * @details The application must use this function as callback for the IN
+ * interrupt endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ */
+void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+ (void)ep;
+}
+
+#endif /* HAL_USE_SERIAL_USB == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/spi.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_spi.c
similarity index 66%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/spi.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_spi.c
index 608c7b7d65..2d43076d11 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/spi.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_spi.c
@@ -1,42 +1,30 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
- * @file spi.c
+ * @file hal_spi.c
* @brief SPI Driver code.
*
* @addtogroup SPI
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_SPI || defined(__DOXYGEN__)
+#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -81,16 +69,12 @@ void spiObjectInit(SPIDriver *spip) {
spip->state = SPI_STOP;
spip->config = NULL;
-#if SPI_USE_WAIT
+#if SPI_USE_WAIT == TRUE
spip->thread = NULL;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION
-#if CH_USE_MUTEXES
- chMtxInit(&spip->mutex);
-#else
- chSemInit(&spip->semaphore, 1);
#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if SPI_USE_MUTUAL_EXCLUSION == TRUE
+ osalMutexObjectInit(&spip->mutex);
+#endif
#if defined(SPI_DRIVER_EXT_INIT_HOOK)
SPI_DRIVER_EXT_INIT_HOOK(spip);
#endif
@@ -106,21 +90,21 @@ void spiObjectInit(SPIDriver *spip) {
*/
void spiStart(SPIDriver *spip, const SPIConfig *config) {
- chDbgCheck((spip != NULL) && (config != NULL), "spiStart");
+ osalDbgCheck((spip != NULL) && (config != NULL));
- chSysLock();
- chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY),
- "spiStart(), #1", "invalid state");
+ osalSysLock();
+ osalDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY),
+ "invalid state");
spip->config = config;
spi_lld_start(spip);
spip->state = SPI_READY;
- chSysUnlock();
+ osalSysUnlock();
}
/**
- * @brief Deactivates the SPI peripheral.
- * @note Deactivating the peripheral also enforces a release of the slave
- * select line.
+ * @brief Deactivates the SPI peripheral.
+ * @note Deactivating the peripheral also enforces a release of the slave
+ * select line.
*
* @param[in] spip pointer to the @p SPIDriver object
*
@@ -128,15 +112,18 @@ void spiStart(SPIDriver *spip, const SPIConfig *config) {
*/
void spiStop(SPIDriver *spip) {
- chDbgCheck(spip != NULL, "spiStop");
+ osalDbgCheck(spip != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY),
+ "invalid state");
- chSysLock();
- chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY),
- "spiStop(), #1", "invalid state");
- spi_lld_unselect(spip);
spi_lld_stop(spip);
- spip->state = SPI_STOP;
- chSysUnlock();
+ spip->config = NULL;
+ spip->state = SPI_STOP;
+
+ osalSysUnlock();
}
/**
@@ -148,12 +135,12 @@ void spiStop(SPIDriver *spip) {
*/
void spiSelect(SPIDriver *spip) {
- chDbgCheck(spip != NULL, "spiSelect");
+ osalDbgCheck(spip != NULL);
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiSelect(), #1", "not ready");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
spiSelectI(spip);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -166,12 +153,12 @@ void spiSelect(SPIDriver *spip) {
*/
void spiUnselect(SPIDriver *spip) {
- chDbgCheck(spip != NULL, "spiUnselect");
+ osalDbgCheck(spip != NULL);
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiUnselect(), #1", "not ready");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
spiUnselectI(spip);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -189,12 +176,12 @@ void spiUnselect(SPIDriver *spip) {
*/
void spiStartIgnore(SPIDriver *spip, size_t n) {
- chDbgCheck((spip != NULL) && (n > 0), "spiStartIgnore");
+ osalDbgCheck((spip != NULL) && (n > 0U));
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiStartIgnore(), #1", "not ready");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
spiStartIgnoreI(spip, n);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -217,13 +204,13 @@ void spiStartIgnore(SPIDriver *spip, size_t n) {
void spiStartExchange(SPIDriver *spip, size_t n,
const void *txbuf, void *rxbuf) {
- chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL),
- "spiStartExchange");
+ osalDbgCheck((spip != NULL) && (n > 0U) &&
+ (rxbuf != NULL) && (txbuf != NULL));
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiStartExchange(), #1", "not ready");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
spiStartExchangeI(spip, n, txbuf, rxbuf);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -243,13 +230,12 @@ void spiStartExchange(SPIDriver *spip, size_t n,
*/
void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf) {
- chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL),
- "spiStartSend");
+ osalDbgCheck((spip != NULL) && (n > 0U) && (txbuf != NULL));
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiStartSend(), #1", "not ready");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
spiStartSendI(spip, n, txbuf);
- chSysUnlock();
+ osalSysUnlock();
}
/**
@@ -269,16 +255,15 @@ void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf) {
*/
void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf) {
- chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL),
- "spiStartReceive");
+ osalDbgCheck((spip != NULL) && (n > 0U) && (rxbuf != NULL));
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiStartReceive(), #1", "not ready");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
spiStartReceiveI(spip, n, rxbuf);
- chSysUnlock();
+ osalSysUnlock();
}
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
+#if (SPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
/**
* @brief Ignores data on the SPI bus.
* @details This synchronous function performs the transmission of a series of
@@ -295,14 +280,14 @@ void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf) {
*/
void spiIgnore(SPIDriver *spip, size_t n) {
- chDbgCheck((spip != NULL) && (n > 0), "spiIgnoreWait");
+ osalDbgCheck((spip != NULL) && (n > 0U));
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiIgnore(), #1", "not ready");
- chDbgAssert(spip->config->end_cb == NULL, "spiIgnore(), #2", "has callback");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
+ osalDbgAssert(spip->config->end_cb == NULL, "has callback");
spiStartIgnoreI(spip, n);
- _spi_wait_s(spip);
- chSysUnlock();
+ (void) osalThreadSuspendS(&spip->thread);
+ osalSysUnlock();
}
/**
@@ -326,16 +311,15 @@ void spiIgnore(SPIDriver *spip, size_t n) {
void spiExchange(SPIDriver *spip, size_t n,
const void *txbuf, void *rxbuf) {
- chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL),
- "spiExchange");
+ osalDbgCheck((spip != NULL) && (n > 0U) &&
+ (rxbuf != NULL) && (txbuf != NULL));
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiExchange(), #1", "not ready");
- chDbgAssert(spip->config->end_cb == NULL,
- "spiExchange(), #2", "has callback");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
+ osalDbgAssert(spip->config->end_cb == NULL, "has callback");
spiStartExchangeI(spip, n, txbuf, rxbuf);
- _spi_wait_s(spip);
- chSysUnlock();
+ (void) osalThreadSuspendS(&spip->thread);
+ osalSysUnlock();
}
/**
@@ -356,14 +340,14 @@ void spiExchange(SPIDriver *spip, size_t n,
*/
void spiSend(SPIDriver *spip, size_t n, const void *txbuf) {
- chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), "spiSend");
+ osalDbgCheck((spip != NULL) && (n > 0U) && (txbuf != NULL));
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiSend(), #1", "not ready");
- chDbgAssert(spip->config->end_cb == NULL, "spiSend(), #2", "has callback");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
+ osalDbgAssert(spip->config->end_cb == NULL, "has callback");
spiStartSendI(spip, n, txbuf);
- _spi_wait_s(spip);
- chSysUnlock();
+ (void) osalThreadSuspendS(&spip->thread);
+ osalSysUnlock();
}
/**
@@ -384,20 +368,18 @@ void spiSend(SPIDriver *spip, size_t n, const void *txbuf) {
*/
void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) {
- chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL),
- "spiReceive");
+ osalDbgCheck((spip != NULL) && (n > 0U) && (rxbuf != NULL));
- chSysLock();
- chDbgAssert(spip->state == SPI_READY, "spiReceive(), #1", "not ready");
- chDbgAssert(spip->config->end_cb == NULL,
- "spiReceive(), #2", "has callback");
+ osalSysLock();
+ osalDbgAssert(spip->state == SPI_READY, "not ready");
+ osalDbgAssert(spip->config->end_cb == NULL, "has callback");
spiStartReceiveI(spip, n, rxbuf);
- _spi_wait_s(spip);
- chSysUnlock();
+ (void) osalThreadSuspendS(&spip->thread);
+ osalSysUnlock();
}
-#endif /* SPI_USE_WAIT */
+#endif /* SPI_USE_WAIT == TRUE */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if (SPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
/**
* @brief Gains exclusive access to the SPI bus.
* @details This function tries to gain ownership to the SPI bus, if the bus
@@ -411,13 +393,9 @@ void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) {
*/
void spiAcquireBus(SPIDriver *spip) {
- chDbgCheck(spip != NULL, "spiAcquireBus");
+ osalDbgCheck(spip != NULL);
-#if CH_USE_MUTEXES
- chMtxLock(&spip->mutex);
-#elif CH_USE_SEMAPHORES
- chSemWait(&spip->semaphore);
-#endif
+ osalMutexLock(&spip->mutex);
}
/**
@@ -431,17 +409,12 @@ void spiAcquireBus(SPIDriver *spip) {
*/
void spiReleaseBus(SPIDriver *spip) {
- chDbgCheck(spip != NULL, "spiReleaseBus");
+ osalDbgCheck(spip != NULL);
-#if CH_USE_MUTEXES
- (void)spip;
- chMtxUnlock();
-#elif CH_USE_SEMAPHORES
- chSemSignal(&spip->semaphore);
-#endif
+ osalMutexUnlock(&spip->mutex);
}
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#endif /* SPI_USE_MUTUAL_EXCLUSION == TRUE */
-#endif /* HAL_USE_SPI */
+#endif /* HAL_USE_SPI == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_st.c
similarity index 57%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_st.c
index b04f6b3c4c..c1f0e39aa9 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_st.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file xxx.c
- * @brief XXX Driver code.
+ * @file hal_st.c
+ * @brief ST Driver code.
*
- * @addtogroup XXX
+ * @addtogroup ST
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_XXX || defined(__DOXYGEN__)
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -52,70 +51,79 @@
/*===========================================================================*/
/**
- * @brief XXX Driver initialization.
+ * @brief ST Driver initialization.
* @note This function is implicitly invoked by @p halInit(), there is
* no need to explicitly initialize the driver.
*
* @init
*/
-void xxxInit(void) {
+void stInit(void) {
- xxx_lld_init();
+ st_lld_init();
}
/**
- * @brief Initializes the standard part of a @p XXXDriver structure.
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ * @note This functionality is only available in free running mode, the
+ * behavior in periodic mode is undefined.
*
- * @param[out] xxxp pointer to the @p XXXDriver object
+ * @param[in] abstime the time to be set for the first alarm
*
- * @init
+ * @api
+ */
+void stStartAlarm(systime_t abstime) {
+
+ osalDbgAssert(stIsAlarmActive() == false, "already active");
+
+ st_lld_start_alarm(abstime);
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ * @note This functionality is only available in free running mode, the
+ * behavior in periodic mode is undefined.
+ *
+ * @api
*/
-void xxxObjectInit(XXXDriver *xxxp) {
+void stStopAlarm(void) {
- xxxp->state = XXX_STOP;
- xxxp->config = NULL;
+ st_lld_stop_alarm();
}
/**
- * @brief Configures and activates the XXX peripheral.
+ * @brief Sets the alarm time.
+ * @note This functionality is only available in free running mode, the
+ * behavior in periodic mode is undefined.
*
- * @param[in] xxxp pointer to the @p XXXDriver object
- * @param[in] config pointer to the @p XXXConfig object
+ * @param[in] abstime the time to be set for the next alarm
*
* @api
*/
-void xxxStart(XXXDriver *xxxp, const XXXConfig *config) {
+void stSetAlarm(systime_t abstime) {
- chDbgCheck((xxxp != NULL) && (config != NULL), "xxxStart");
+ osalDbgAssert(stIsAlarmActive() != false, "not active");
- chSysLock();
- chDbgAssert((xxxp->state == XXX_STOP) || (xxxp->state == XXX_READY),
- "xxxStart(), #1", "invalid state");
- xxxp->config = config;
- xxx_lld_start(xxxp);
- xxxp->state = XXX_READY;
- chSysUnlock();
+ st_lld_set_alarm(abstime);
}
/**
- * @brief Deactivates the XXX peripheral.
+ * @brief Returns the current alarm time.
+ * @note This functionality is only available in free running mode, the
+ * behavior in periodic mode is undefined.
*
- * @param[in] xxxp pointer to the @p XXXDriver object
+ * @return The currently set alarm time.
*
* @api
*/
-void xxxStop(XXXDriver *xxxp) {
+systime_t stGetAlarm(void) {
- chDbgCheck(xxxp != NULL, "xxxStop");
+ osalDbgAssert(stIsAlarmActive() != false, "not active");
- chSysLock();
- chDbgAssert((xxxp->state == XXX_STOP) || (xxxp->state == XXX_READY),
- "xxxStop(), #1", "invalid state");
- xxx_lld_stop(xxxp);
- xxxp->state = XXX_STOP;
- chSysUnlock();
+ return st_lld_get_alarm();
}
-#endif /* HAL_USE_XXX */
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_uart.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_uart.c
new file mode 100644
index 0000000000..eb65d78d41
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_uart.c
@@ -0,0 +1,524 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_uart.c
+ * @brief UART Driver code.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief UART Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void uartInit(void) {
+
+ uart_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p UARTDriver structure.
+ *
+ * @param[out] uartp pointer to the @p UARTDriver object
+ *
+ * @init
+ */
+void uartObjectInit(UARTDriver *uartp) {
+
+ uartp->state = UART_STOP;
+ uartp->txstate = UART_TX_IDLE;
+ uartp->rxstate = UART_RX_IDLE;
+ uartp->config = NULL;
+#if UART_USE_WAIT == TRUE
+ uartp->early = false;
+ uartp->threadrx = NULL;
+ uartp->threadtx = NULL;
+#endif /* UART_USE_WAIT */
+#if UART_USE_MUTUAL_EXCLUSION == TRUE
+ osalMutexObjectInit(&uartp->mutex);
+#endif /* UART_USE_MUTUAL_EXCLUSION */
+
+ /* Optional, user-defined initializer.*/
+#if defined(UART_DRIVER_EXT_INIT_HOOK)
+ UART_DRIVER_EXT_INIT_HOOK(uartp);
+#endif
+}
+
+/**
+ * @brief Configures and activates the UART peripheral.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] config pointer to the @p UARTConfig object
+ *
+ * @api
+ */
+void uartStart(UARTDriver *uartp, const UARTConfig *config) {
+
+ osalDbgCheck((uartp != NULL) && (config != NULL));
+
+ osalSysLock();
+ osalDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY),
+ "invalid state");
+
+ uartp->config = config;
+ uart_lld_start(uartp);
+ uartp->state = UART_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the UART peripheral.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @api
+ */
+void uartStop(UARTDriver *uartp) {
+
+ osalDbgCheck(uartp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY),
+ "invalid state");
+
+ uart_lld_stop(uartp);
+ uartp->config = NULL;
+ uartp->state = UART_STOP;
+ uartp->txstate = UART_TX_IDLE;
+ uartp->rxstate = UART_RX_IDLE;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Starts a transmission on the UART peripheral.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] n number of data frames to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @api
+ */
+void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf) {
+
+ osalDbgCheck((uartp != NULL) && (n > 0U) && (txbuf != NULL));
+
+ osalSysLock();
+ osalDbgAssert(uartp->state == UART_READY, "is active");
+ osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active");
+
+ uart_lld_start_send(uartp, n, txbuf);
+ uartp->txstate = UART_TX_ACTIVE;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Starts a transmission on the UART peripheral.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ * @note This function has to be invoked from a lock zone.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] n number of data frames to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @iclass
+ */
+void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck((uartp != NULL) && (n > 0U) && (txbuf != NULL));
+ osalDbgAssert(uartp->state == UART_READY, "is active");
+ osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active");
+
+ uart_lld_start_send(uartp, n, txbuf);
+ uartp->txstate = UART_TX_ACTIVE;
+}
+
+/**
+ * @brief Stops any ongoing transmission.
+ * @note Stopping a transmission also suppresses the transmission callbacks.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @return The number of data frames not transmitted by the
+ * stopped transmit operation.
+ * @retval 0 There was no transmit operation in progress.
+ *
+ * @api
+ */
+size_t uartStopSend(UARTDriver *uartp) {
+ size_t n;
+
+ osalDbgCheck(uartp != NULL);
+
+ osalSysLock();
+ osalDbgAssert(uartp->state == UART_READY, "not active");
+
+ if (uartp->txstate == UART_TX_ACTIVE) {
+ n = uart_lld_stop_send(uartp);
+ uartp->txstate = UART_TX_IDLE;
+ }
+ else {
+ n = 0;
+ }
+ osalSysUnlock();
+
+ return n;
+}
+
+/**
+ * @brief Stops any ongoing transmission.
+ * @note Stopping a transmission also suppresses the transmission callbacks.
+ * @note This function has to be invoked from a lock zone.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @return The number of data frames not transmitted by the
+ * stopped transmit operation.
+ * @retval 0 There was no transmit operation in progress.
+ *
+ * @iclass
+ */
+size_t uartStopSendI(UARTDriver *uartp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(uartp != NULL);
+ osalDbgAssert(uartp->state == UART_READY, "not active");
+
+ if (uartp->txstate == UART_TX_ACTIVE) {
+ size_t n = uart_lld_stop_send(uartp);
+ uartp->txstate = UART_TX_IDLE;
+ return n;
+ }
+ return 0;
+}
+
+/**
+ * @brief Starts a receive operation on the UART peripheral.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] n number of data frames to receive
+ * @param[in] rxbuf the pointer to the receive buffer
+ *
+ * @api
+ */
+void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf) {
+
+ osalDbgCheck((uartp != NULL) && (n > 0U) && (rxbuf != NULL));
+
+ osalSysLock();
+ osalDbgAssert(uartp->state == UART_READY, "is active");
+ osalDbgAssert(uartp->rxstate != UART_RX_ACTIVE, "rx active");
+
+ uart_lld_start_receive(uartp, n, rxbuf);
+ uartp->rxstate = UART_RX_ACTIVE;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Starts a receive operation on the UART peripheral.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ * @note This function has to be invoked from a lock zone.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in] n number of data frames to receive
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @iclass
+ */
+void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck((uartp != NULL) && (n > 0U) && (rxbuf != NULL));
+ osalDbgAssert(uartp->state == UART_READY, "is active");
+ osalDbgAssert(uartp->rxstate != UART_RX_ACTIVE, "rx active");
+
+ uart_lld_start_receive(uartp, n, rxbuf);
+ uartp->rxstate = UART_RX_ACTIVE;
+}
+
+/**
+ * @brief Stops any ongoing receive operation.
+ * @note Stopping a receive operation also suppresses the receive callbacks.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @return The number of data frames not received by the
+ * stopped receive operation.
+ * @retval 0 There was no receive operation in progress.
+ *
+ * @api
+ */
+size_t uartStopReceive(UARTDriver *uartp) {
+ size_t n;
+
+ osalDbgCheck(uartp != NULL);
+
+ osalSysLock();
+ osalDbgAssert(uartp->state == UART_READY, "not active");
+
+ if (uartp->rxstate == UART_RX_ACTIVE) {
+ n = uart_lld_stop_receive(uartp);
+ uartp->rxstate = UART_RX_IDLE;
+ }
+ else {
+ n = 0;
+ }
+ osalSysUnlock();
+
+ return n;
+}
+
+/**
+ * @brief Stops any ongoing receive operation.
+ * @note Stopping a receive operation also suppresses the receive callbacks.
+ * @note This function has to be invoked from a lock zone.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @return The number of data frames not received by the
+ * stopped receive operation.
+ * @retval 0 There was no receive operation in progress.
+ *
+ * @iclass
+ */
+size_t uartStopReceiveI(UARTDriver *uartp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(uartp != NULL);
+ osalDbgAssert(uartp->state == UART_READY, "not active");
+
+ if (uartp->rxstate == UART_RX_ACTIVE) {
+ size_t n = uart_lld_stop_receive(uartp);
+ uartp->rxstate = UART_RX_IDLE;
+ return n;
+ }
+ return 0;
+}
+
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Performs a transmission on the UART peripheral.
+ * @note The function returns when the specified number of frames have been
+ * sent to the UART or on timeout.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ * @note This function implements a software timeout, it does not use
+ * any underlying HW timeout mechanism.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in,out] np number of data frames to transmit, on exit the number
+ * of frames actually transmitted
+ * @param[in] txbuf the pointer to the transmit buffer
+ * @param[in] timeout operation timeout
+ * @return The operation status.
+ * @retval MSG_OK if the operation completed successfully.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ *
+ * @api
+ */
+msg_t uartSendTimeout(UARTDriver *uartp, size_t *np,
+ const void *txbuf, systime_t timeout) {
+ msg_t msg;
+
+ osalDbgCheck((uartp != NULL) && (*np > 0U) && (txbuf != NULL));
+
+ osalSysLock();
+ osalDbgAssert(uartp->state == UART_READY, "is active");
+ osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active");
+
+ /* Transmission start.*/
+ uartp->early = true;
+ uart_lld_start_send(uartp, *np, txbuf);
+ uartp->txstate = UART_TX_ACTIVE;
+
+ /* Waiting for result.*/
+ msg = osalThreadSuspendTimeoutS(&uartp->threadtx, timeout);
+ if (msg != MSG_OK) {
+ *np -= uartStopSendI(uartp);
+ }
+ osalSysUnlock();
+
+ return msg;
+}
+
+/**
+ * @brief Performs a transmission on the UART peripheral.
+ * @note The function returns when the specified number of frames have been
+ * physically transmitted or on timeout.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ * @note This function implements a software timeout, it does not use
+ * any underlying HW timeout mechanism.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in,out] np number of data frames to transmit, on exit the number
+ * of frames actually transmitted
+ * @param[in] txbuf the pointer to the transmit buffer
+ * @param[in] timeout operation timeout
+ * @return The operation status.
+ * @retval MSG_OK if the operation completed successfully.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ *
+ * @api
+ */
+msg_t uartSendFullTimeout(UARTDriver *uartp, size_t *np,
+ const void *txbuf, systime_t timeout) {
+ msg_t msg;
+
+ osalDbgCheck((uartp != NULL) && (*np > 0U) && (txbuf != NULL));
+
+ osalSysLock();
+ osalDbgAssert(uartp->state == UART_READY, "is active");
+ osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active");
+
+ /* Transmission start.*/
+ uartp->early = false;
+ uart_lld_start_send(uartp, *np, txbuf);
+ uartp->txstate = UART_TX_ACTIVE;
+
+ /* Waiting for result.*/
+ msg = osalThreadSuspendTimeoutS(&uartp->threadtx, timeout);
+ if (msg != MSG_OK) {
+ *np = uartStopSendI(uartp);
+ }
+ osalSysUnlock();
+
+ return msg;
+}
+
+/**
+ * @brief Performs a receive operation on the UART peripheral.
+ * @note The function returns when the specified number of frames have been
+ * received or on error/timeout.
+ * @note The buffers are organized as uint8_t arrays for data sizes below
+ * or equal to 8 bits else it is organized as uint16_t arrays.
+ * @note This function implements a software timeout, it does not use
+ * any underlying HW timeout mechanism.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ * @param[in,out] np number of data frames to receive, on exit the number
+ * of frames actually received
+ * @param[in] rxbuf the pointer to the receive buffer
+ * @param[in] timeout operation timeout
+ *
+ * @return The operation status.
+ * @retval MSG_OK if the operation completed successfully.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ * @retval MSG_RESET in case of a receive error.
+ *
+ * @api
+ */
+msg_t uartReceiveTimeout(UARTDriver *uartp, size_t *np,
+ void *rxbuf, systime_t timeout) {
+ msg_t msg;
+
+ osalDbgCheck((uartp != NULL) && (*np > 0U) && (rxbuf != NULL));
+
+ osalSysLock();
+ osalDbgAssert(uartp->state == UART_READY, "is active");
+ osalDbgAssert(uartp->rxstate != UART_RX_ACTIVE, "rx active");
+
+ /* Receive start.*/
+ uart_lld_start_receive(uartp, *np, rxbuf);
+ uartp->rxstate = UART_RX_ACTIVE;
+
+ /* Waiting for result.*/
+ msg = osalThreadSuspendTimeoutS(&uartp->threadrx, timeout);
+ if (msg != MSG_OK) {
+ *np -= uartStopReceiveI(uartp);
+ }
+ osalSysUnlock();
+
+ return msg;
+}
+#endif
+
+#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Gains exclusive access to the UART bus.
+ * @details This function tries to gain ownership to the UART bus, if the bus
+ * is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option @p UART_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @api
+ */
+void uartAcquireBus(UARTDriver *uartp) {
+
+ osalDbgCheck(uartp != NULL);
+
+ osalMutexLock(&uartp->mutex);
+}
+
+/**
+ * @brief Releases exclusive access to the UART bus.
+ * @pre In order to use this function the option @p UART_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] uartp pointer to the @p UARTDriver object
+ *
+ * @api
+ */
+void uartReleaseBus(UARTDriver *uartp) {
+
+ osalDbgCheck(uartp != NULL);
+
+ osalMutexUnlock(&uartp->mutex);
+}
+#endif
+
+#endif /* HAL_USE_UART == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_usb.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_usb.c
new file mode 100644
index 0000000000..6eac266224
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_usb.c
@@ -0,0 +1,995 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_usb.c
+ * @brief USB Driver code.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#include
+
+#include "hal.h"
+
+#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+static const uint8_t zero_status[] = {0x00, 0x00};
+static const uint8_t active_status[] ={0x00, 0x00};
+static const uint8_t halted_status[] = {0x01, 0x00};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static uint16_t get_hword(uint8_t *p) {
+ uint16_t hw;
+
+ hw = (uint16_t)*p++;
+ hw |= (uint16_t)*p << 8U;
+ return hw;
+}
+
+/**
+ * @brief SET ADDRESS transaction callback.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ */
+static void set_address(USBDriver *usbp) {
+
+ usbp->address = usbp->setup[2];
+ usb_lld_set_address(usbp);
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS);
+ usbp->state = USB_SELECTED;
+}
+
+/**
+ * @brief Standard requests handler.
+ * @details This is the standard requests default handler, most standard
+ * requests are handled here, the user can override the standard
+ * handling using the @p requests_hook_cb hook in the
+ * @p USBConfig structure.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return The request handling exit code.
+ * @retval false Request not recognized by the handler or error.
+ * @retval true Request handled.
+ */
+static bool default_handler(USBDriver *usbp) {
+ const USBDescriptor *dp;
+
+ /* Decoding the request.*/
+ switch ((((uint32_t)usbp->setup[0] & (USB_RTYPE_RECIPIENT_MASK |
+ USB_RTYPE_TYPE_MASK)) |
+ ((uint32_t)usbp->setup[1] << 8U))) {
+ case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_GET_STATUS << 8):
+ /* Just returns the current status word.*/
+ usbSetupTransfer(usbp, (uint8_t *)&usbp->status, 2, NULL);
+ return true;
+ case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_CLEAR_FEATURE << 8):
+ /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature
+ number is handled as an error.*/
+ if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) {
+ usbp->status &= ~2U;
+ usbSetupTransfer(usbp, NULL, 0, NULL);
+ return true;
+ }
+ return false;
+ case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_SET_FEATURE << 8):
+ /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature
+ number is handled as an error.*/
+ if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) {
+ usbp->status |= 2U;
+ usbSetupTransfer(usbp, NULL, 0, NULL);
+ return true;
+ }
+ return false;
+ case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_SET_ADDRESS << 8):
+ /* The SET_ADDRESS handling can be performed here or postponed after
+ the status packed depending on the USB_SET_ADDRESS_MODE low
+ driver setting.*/
+#if USB_SET_ADDRESS_MODE == USB_EARLY_SET_ADDRESS
+ if ((usbp->setup[0] == USB_RTYPE_RECIPIENT_DEVICE) &&
+ (usbp->setup[1] == USB_REQ_SET_ADDRESS)) {
+ set_address(usbp);
+ }
+ usbSetupTransfer(usbp, NULL, 0, NULL);
+#else
+ usbSetupTransfer(usbp, NULL, 0, set_address);
+#endif
+ return true;
+ case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_GET_DESCRIPTOR << 8):
+ case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_GET_DESCRIPTOR << 8):
+ /* Handling descriptor requests from the host.*/
+ dp = usbp->config->get_descriptor_cb(usbp, usbp->setup[3],
+ usbp->setup[2],
+ get_hword(&usbp->setup[4]));
+ if (dp == NULL) {
+ return false;
+ }
+ /*lint -save -e9005 [11.8] Removing const is fine.*/
+ usbSetupTransfer(usbp, (uint8_t *)dp->ud_string, dp->ud_size, NULL);
+ /*lint -restore*/
+ return true;
+ case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_GET_CONFIGURATION << 8):
+ /* Returning the last selected configuration.*/
+ usbSetupTransfer(usbp, &usbp->configuration, 1, NULL);
+ return true;
+ case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_SET_CONFIGURATION << 8):
+ /* Handling configuration selection from the host only if it is different
+ from the current configuration.*/
+ if (usbp->configuration != usbp->setup[2]) {
+ /* If the USB device is already active then we have to perform the clear
+ procedure on the current configuration.*/
+ if (usbp->state == USB_ACTIVE) {
+ /* Current configuration cleared.*/
+ osalSysLockFromISR ();
+ usbDisableEndpointsI(usbp);
+ osalSysUnlockFromISR ();
+ usbp->configuration = 0U;
+ usbp->state = USB_SELECTED;
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_UNCONFIGURED);
+ }
+ if (usbp->setup[2] != 0U) {
+ /* New configuration.*/
+ usbp->configuration = usbp->setup[2];
+ usbp->state = USB_ACTIVE;
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_CONFIGURED);
+ }
+ }
+ usbSetupTransfer(usbp, NULL, 0, NULL);
+ return true;
+ case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_GET_STATUS << 8):
+ case (uint32_t)USB_RTYPE_RECIPIENT_ENDPOINT | ((uint32_t)USB_REQ_SYNCH_FRAME << 8):
+ /* Just sending two zero bytes, the application can change the behavior
+ using a hook..*/
+ /*lint -save -e9005 [11.8] Removing const is fine.*/
+ usbSetupTransfer(usbp, (uint8_t *)zero_status, 2, NULL);
+ /*lint -restore*/
+ return true;
+ case (uint32_t)USB_RTYPE_RECIPIENT_ENDPOINT | ((uint32_t)USB_REQ_GET_STATUS << 8):
+ /* Sending the EP status.*/
+ if ((usbp->setup[4] & 0x80U) != 0U) {
+ switch (usb_lld_get_status_in(usbp, usbp->setup[4] & 0x0FU)) {
+ case EP_STATUS_STALLED:
+ /*lint -save -e9005 [11.8] Removing const is fine.*/
+ usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL);
+ /*lint -restore*/
+ return true;
+ case EP_STATUS_ACTIVE:
+ /*lint -save -e9005 [11.8] Removing const is fine.*/
+ usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL);
+ /*lint -restore*/
+ return true;
+ case EP_STATUS_DISABLED:
+ default:
+ return false;
+ }
+ }
+ else {
+ switch (usb_lld_get_status_out(usbp, usbp->setup[4] & 0x0FU)) {
+ case EP_STATUS_STALLED:
+ /*lint -save -e9005 [11.8] Removing const is fine.*/
+ usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL);
+ /*lint -restore*/
+ return true;
+ case EP_STATUS_ACTIVE:
+ /*lint -save -e9005 [11.8] Removing const is fine.*/
+ usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL);
+ /*lint -restore*/
+ return true;
+ case EP_STATUS_DISABLED:
+ default:
+ return false;
+ }
+ }
+ case (uint32_t)USB_RTYPE_RECIPIENT_ENDPOINT | ((uint32_t)USB_REQ_CLEAR_FEATURE << 8):
+ /* Only ENDPOINT_HALT is handled as feature.*/
+ if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) {
+ return false;
+ }
+ /* Clearing the EP status, not valid for EP0, it is ignored in that case.*/
+ if ((usbp->setup[4] & 0x0FU) != 0U) {
+ if ((usbp->setup[4] & 0x80U) != 0U) {
+ usb_lld_clear_in(usbp, usbp->setup[4] & 0x0FU);
+ }
+ else {
+ usb_lld_clear_out(usbp, usbp->setup[4] & 0x0FU);
+ }
+ }
+ usbSetupTransfer(usbp, NULL, 0, NULL);
+ return true;
+ case (uint32_t)USB_RTYPE_RECIPIENT_ENDPOINT | ((uint32_t)USB_REQ_SET_FEATURE << 8):
+ /* Only ENDPOINT_HALT is handled as feature.*/
+ if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) {
+ return false;
+ }
+ /* Stalling the EP, not valid for EP0, it is ignored in that case.*/
+ if ((usbp->setup[4] & 0x0FU) != 0U) {
+ if ((usbp->setup[4] & 0x80U) != 0U) {
+ usb_lld_stall_in(usbp, usbp->setup[4] & 0x0FU);
+ }
+ else {
+ usb_lld_stall_out(usbp, usbp->setup[4] & 0x0FU);
+ }
+ }
+ usbSetupTransfer(usbp, NULL, 0, NULL);
+ return true;
+ case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_SET_DESCRIPTOR << 8):
+ case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_CLEAR_FEATURE << 8):
+ case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_SET_FEATURE << 8):
+ case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_GET_INTERFACE << 8):
+ case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_SET_INTERFACE << 8):
+ /* All the above requests are not handled here, if you need them then
+ use the hook mechanism and provide handling.*/
+ default:
+ return false;
+ }
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief USB Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void usbInit(void) {
+
+ usb_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p USBDriver structure.
+ *
+ * @param[out] usbp pointer to the @p USBDriver object
+ *
+ * @init
+ */
+void usbObjectInit(USBDriver *usbp) {
+ unsigned i;
+
+ usbp->state = USB_STOP;
+ usbp->config = NULL;
+ for (i = 0; i < (unsigned)USB_MAX_ENDPOINTS; i++) {
+ usbp->in_params[i] = NULL;
+ usbp->out_params[i] = NULL;
+ }
+ usbp->transmitting = 0;
+ usbp->receiving = 0;
+}
+
+/**
+ * @brief Configures and activates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] config pointer to the @p USBConfig object
+ *
+ * @api
+ */
+void usbStart(USBDriver *usbp, const USBConfig *config) {
+ unsigned i;
+
+ osalDbgCheck((usbp != NULL) && (config != NULL));
+
+ osalSysLock();
+ osalDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY),
+ "invalid state");
+ usbp->config = config;
+ for (i = 0; i <= (unsigned)USB_MAX_ENDPOINTS; i++) {
+ usbp->epc[i] = NULL;
+ }
+ usb_lld_start(usbp);
+ usbp->state = USB_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @api
+ */
+void usbStop(USBDriver *usbp) {
+ unsigned i;
+
+ osalDbgCheck(usbp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY) ||
+ (usbp->state == USB_SELECTED) || (usbp->state == USB_ACTIVE) ||
+ (usbp->state == USB_SUSPENDED),
+ "invalid state");
+
+ usb_lld_stop(usbp);
+ usbp->config = NULL;
+ usbp->state = USB_STOP;
+
+ /* Resetting all ongoing synchronous operations.*/
+ for (i = 0; i <= (unsigned)USB_MAX_ENDPOINTS; i++) {
+#if USB_USE_WAIT == TRUE
+ if (usbp->epc[i] != NULL) {
+ if (usbp->epc[i]->in_state != NULL) {
+ osalThreadResumeI(&usbp->epc[i]->in_state->thread, MSG_RESET);
+ }
+ if (usbp->epc[i]->out_state != NULL) {
+ osalThreadResumeI(&usbp->epc[i]->out_state->thread, MSG_RESET);
+ }
+ }
+#endif
+ usbp->epc[i] = NULL;
+ }
+ osalOsRescheduleS();
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Enables an endpoint.
+ * @details This function enables an endpoint, both IN and/or OUT directions
+ * depending on the configuration structure.
+ * @note This function must be invoked in response of a SET_CONFIGURATION
+ * or SET_INTERFACE message.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[in] epcp the endpoint configuration
+ *
+ * @iclass
+ */
+void usbInitEndpointI(USBDriver *usbp, usbep_t ep,
+ const USBEndpointConfig *epcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck((usbp != NULL) && (epcp != NULL));
+ osalDbgAssert(usbp->state == USB_ACTIVE,
+ "invalid state");
+ osalDbgAssert(usbp->epc[ep] == NULL, "already initialized");
+
+ /* Logically enabling the endpoint in the USBDriver structure.*/
+ usbp->epc[ep] = epcp;
+
+ /* Clearing the state structures, custom fields as well.*/
+ if (epcp->in_state != NULL) {
+ memset(epcp->in_state, 0, sizeof(USBInEndpointState));
+ }
+ if (epcp->out_state != NULL) {
+ memset(epcp->out_state, 0, sizeof(USBOutEndpointState));
+ }
+
+ /* Low level endpoint activation.*/
+ usb_lld_init_endpoint(usbp, ep);
+}
+
+/**
+ * @brief Disables all the active endpoints.
+ * @details This function disables all the active endpoints except the
+ * endpoint zero.
+ * @note This function must be invoked in response of a SET_CONFIGURATION
+ * message with configuration number zero.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @iclass
+ */
+void usbDisableEndpointsI(USBDriver *usbp) {
+ unsigned i;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(usbp != NULL);
+ osalDbgAssert(usbp->state == USB_ACTIVE, "invalid state");
+
+ usbp->transmitting &= 1U;
+ usbp->receiving &= 1U;
+
+ for (i = 1; i <= (unsigned)USB_MAX_ENDPOINTS; i++) {
+#if USB_USE_WAIT == TRUE
+ /* Signaling the event to threads waiting on endpoints.*/
+ if (usbp->epc[i] != NULL) {
+ if (usbp->epc[i]->in_state != NULL) {
+ osalThreadResumeI(&usbp->epc[i]->in_state->thread, MSG_RESET);
+ }
+ if (usbp->epc[i]->out_state != NULL) {
+ osalThreadResumeI(&usbp->epc[i]->out_state->thread, MSG_RESET);
+ }
+ }
+#endif
+ usbp->epc[i] = NULL;
+ }
+
+ /* Low level endpoints deactivation.*/
+ usb_lld_disable_endpoints(usbp);
+}
+
+/**
+ * @brief Starts a receive transaction on an OUT endpoint.
+ * @note This function is meant to be called from ISR context outside
+ * critical zones because there is a potentially slow operation
+ * inside.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[out] buf buffer where to copy the received data
+ * @param[in] n transaction size. It is recommended a multiple of
+ * the packet size because the excess is discarded.
+ *
+ * @iclass
+ */
+void usbStartReceiveI(USBDriver *usbp, usbep_t ep,
+ uint8_t *buf, size_t n) {
+ USBOutEndpointState *osp;
+
+ osalDbgCheckClassI();
+ osalDbgCheck((usbp != NULL) && (ep <= (usbep_t)USB_MAX_ENDPOINTS));
+ osalDbgAssert(!usbGetReceiveStatusI(usbp, ep), "already receiving");
+
+ /* Marking the endpoint as active.*/
+ usbp->receiving |= (uint16_t)((unsigned)1U << (unsigned)ep);
+
+ /* Setting up the transfer.*/
+ /*lint -save -e661 [18.1] pclint is confused by the check on ep.*/
+ osp = usbp->epc[ep]->out_state;
+ /*lint -restore*/
+ osp->rxbuf = buf;
+ osp->rxsize = n;
+ osp->rxcnt = 0;
+#if USB_USE_WAIT == TRUE
+ osp->thread = NULL;
+#endif
+
+ /* Starting transfer.*/
+ usb_lld_start_out(usbp, ep);
+}
+
+/**
+ * @brief Starts a transmit transaction on an IN endpoint.
+ * @note This function is meant to be called from ISR context outside
+ * critical zones because there is a potentially slow operation
+ * inside.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[in] buf buffer where to fetch the data to be transmitted
+ * @param[in] n transaction size
+ *
+ * @iclass
+ */
+void usbStartTransmitI(USBDriver *usbp, usbep_t ep,
+ const uint8_t *buf, size_t n) {
+ USBInEndpointState *isp;
+
+ osalDbgCheckClassI();
+ osalDbgCheck((usbp != NULL) && (ep <= (usbep_t)USB_MAX_ENDPOINTS));
+ osalDbgAssert(!usbGetTransmitStatusI(usbp, ep), "already transmitting");
+
+ /* Marking the endpoint as active.*/
+ usbp->transmitting |= (uint16_t)((unsigned)1U << (unsigned)ep);
+
+ /* Setting up the transfer.*/
+ /*lint -save -e661 [18.1] pclint is confused by the check on ep.*/
+ isp = usbp->epc[ep]->in_state;
+ /*lint -restore*/
+ isp->txbuf = buf;
+ isp->txsize = n;
+ isp->txcnt = 0;
+#if USB_USE_WAIT == TRUE
+ isp->thread = NULL;
+#endif
+
+ /* Starting transfer.*/
+ usb_lld_start_in(usbp, ep);
+}
+
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Performs a receive transaction on an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[out] buf buffer where to copy the received data
+ * @param[in] n transaction size. It is recommended a multiple of
+ * the packet size because the excess is discarded.
+ *
+ * @return The received effective data size, it can be less than
+ * the amount specified.
+ * @retval MSG_RESET driver not in @p USB_ACTIVE state or the operation
+ * has been aborted by an USB reset or a transition to
+ * the @p USB_SUSPENDED state.
+ *
+ * @api
+ */
+msg_t usbReceive(USBDriver *usbp, usbep_t ep, uint8_t *buf, size_t n) {
+ msg_t msg;
+
+ osalSysLock();
+
+ if (usbGetDriverStateI(usbp) != USB_ACTIVE) {
+ osalSysUnlock();
+ return MSG_RESET;
+ }
+
+ usbStartReceiveI(usbp, ep, buf, n);
+ msg = osalThreadSuspendS(&usbp->epc[ep]->out_state->thread);
+ osalSysUnlock();
+
+ return msg;
+}
+
+/**
+ * @brief Performs a transmit transaction on an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[in] buf buffer where to fetch the data to be transmitted
+ * @param[in] n transaction size
+ *
+ * @return The operation status.
+ * @retval MSG_OK operation performed successfully.
+ * @retval MSG_RESET driver not in @p USB_ACTIVE state or the operation
+ * has been aborted by an USB reset or a transition to
+ * the @p USB_SUSPENDED state.
+ *
+ * @api
+ */
+msg_t usbTransmit(USBDriver *usbp, usbep_t ep, const uint8_t *buf, size_t n) {
+ msg_t msg;
+
+ osalSysLock();
+
+ if (usbGetDriverStateI(usbp) != USB_ACTIVE) {
+ osalSysUnlock();
+ return MSG_RESET;
+ }
+
+ usbStartTransmitI(usbp, ep, buf, n);
+ msg = osalThreadSuspendS(&usbp->epc[ep]->in_state->thread);
+ osalSysUnlock();
+
+ return msg;
+}
+#endif /* USB_USE_WAIT == TRUE */
+
+/**
+ * @brief Stalls an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @return The operation status.
+ * @retval false Endpoint stalled.
+ * @retval true Endpoint busy, not stalled.
+ *
+ * @iclass
+ */
+bool usbStallReceiveI(USBDriver *usbp, usbep_t ep) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(usbp != NULL);
+
+ if (usbGetReceiveStatusI(usbp, ep)) {
+ return true;
+ }
+
+ usb_lld_stall_out(usbp, ep);
+ return false;
+}
+
+/**
+ * @brief Stalls an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @return The operation status.
+ * @retval false Endpoint stalled.
+ * @retval true Endpoint busy, not stalled.
+ *
+ * @iclass
+ */
+bool usbStallTransmitI(USBDriver *usbp, usbep_t ep) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(usbp != NULL);
+
+ if (usbGetTransmitStatusI(usbp, ep)) {
+ return true;
+ }
+
+ usb_lld_stall_in(usbp, ep);
+ return false;
+}
+
+/**
+ * @brief Host wake-up procedure.
+ * @note It is silently ignored if the USB device is not in the
+ * @p USB_SUSPENDED state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @api
+ */
+void usbWakeupHost(USBDriver *usbp) {
+
+ if (usbp->state == USB_SUSPENDED) {
+ /* Starting host wakeup procedure.*/
+ usb_lld_wakeup_host(usbp);
+ }
+}
+
+/**
+ * @brief USB reset routine.
+ * @details This function must be invoked when an USB bus reset condition is
+ * detected.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void _usb_reset(USBDriver *usbp) {
+ unsigned i;
+
+ /* State transition.*/
+ usbp->state = USB_READY;
+
+ /* Resetting internal state.*/
+ usbp->status = 0;
+ usbp->address = 0;
+ usbp->configuration = 0;
+ usbp->transmitting = 0;
+ usbp->receiving = 0;
+
+ /* Invalidates all endpoints into the USBDriver structure.*/
+ for (i = 0; i <= (unsigned)USB_MAX_ENDPOINTS; i++) {
+#if USB_USE_WAIT == TRUE
+ /* Signaling the event to threads waiting on endpoints.*/
+ if (usbp->epc[i] != NULL) {
+ osalSysLockFromISR();
+ if (usbp->epc[i]->in_state != NULL) {
+ osalThreadResumeI(&usbp->epc[i]->in_state->thread, MSG_RESET);
+ }
+ if (usbp->epc[i]->out_state != NULL) {
+ osalThreadResumeI(&usbp->epc[i]->out_state->thread, MSG_RESET);
+ }
+ osalSysUnlockFromISR();
+ }
+#endif
+ usbp->epc[i] = NULL;
+ }
+
+ /* EP0 state machine initialization.*/
+ usbp->ep0state = USB_EP0_STP_WAITING;
+
+ /* Low level reset.*/
+ usb_lld_reset(usbp);
+
+ /* Notification of reset event.*/
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
+}
+
+/**
+ * @brief USB suspend routine.
+ * @details This function must be invoked when an USB bus suspend condition is
+ * detected.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void _usb_suspend(USBDriver *usbp) {
+ /* No state change, suspend always returns to previous state. */
+
+ /* State transition.*/
+ usbp->saved_state = usbp->state;
+ usbp->state = USB_SUSPENDED;
+
+ /* Notification of suspend event.*/
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND);
+
+ /* Signaling the event to threads waiting on endpoints.*/
+#if USB_USE_WAIT == TRUE
+ {
+ unsigned i;
+
+ for (i = 0; i <= (unsigned)USB_MAX_ENDPOINTS; i++) {
+ if (usbp->epc[i] != NULL) {
+ osalSysLockFromISR();
+ if (usbp->epc[i]->in_state != NULL) {
+ osalThreadResumeI(&usbp->epc[i]->in_state->thread, MSG_RESET);
+ }
+ if (usbp->epc[i]->out_state != NULL) {
+ osalThreadResumeI(&usbp->epc[i]->out_state->thread, MSG_RESET);
+ }
+ osalSysUnlockFromISR();
+ }
+ }
+ }
+#endif
+}
+
+/**
+ * @brief USB wake-up routine.
+ * @details This function must be invoked when an USB bus wake-up condition is
+ * detected.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void _usb_wakeup(USBDriver *usbp) {
+
+ /* State transition, returning to the previous state.*/
+ usbp->state = usbp->saved_state;
+
+ /* Notification of suspend event.*/
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP);
+}
+
+/**
+ * @brief Default EP0 SETUP callback.
+ * @details This function is used by the low level driver as default handler
+ * for EP0 SETUP events.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number, always zero
+ *
+ * @notapi
+ */
+void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
+ size_t max;
+
+ /* Is the EP0 state machine in the correct state for handling setup
+ packets?*/
+ if (usbp->ep0state != USB_EP0_STP_WAITING) {
+ /* This is unexpected could require handling with a warning event.*/
+ /* TODO: handling here.*/
+
+ /* Resetting the EP0 state machine and going ahead.*/
+ usbp->ep0state = USB_EP0_STP_WAITING;
+ }
+
+ /* Reading the setup data into the driver buffer.*/
+ usbReadSetup(usbp, ep, usbp->setup);
+
+ /* First verify if the application has an handler installed for this
+ request.*/
+ /*lint -save -e9007 [13.5] No side effects, it is intentional.*/
+ if ((usbp->config->requests_hook_cb == NULL) ||
+ !(usbp->config->requests_hook_cb(usbp))) {
+ /*lint -restore*/
+ /* Invoking the default handler, if this fails then stalls the
+ endpoint zero as error.*/
+ /*lint -save -e9007 [13.5] No side effects, it is intentional.*/
+ if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) != USB_RTYPE_TYPE_STD) ||
+ !default_handler(usbp)) {
+ /*lint -restore*/
+ /* Error response, the state machine goes into an error state, the low
+ level layer will have to reset it to USB_EP0_WAITING_SETUP after
+ receiving a SETUP packet.*/
+ usb_lld_stall_in(usbp, 0);
+ usb_lld_stall_out(usbp, 0);
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED);
+ usbp->ep0state = USB_EP0_ERROR;
+ return;
+ }
+ }
+#if (USB_SET_ADDRESS_ACK_HANDLING == USB_SET_ADDRESS_ACK_HW)
+ if (usbp->setup[1] == USB_REQ_SET_ADDRESS) {
+ /* Zero-length packet sent by hardware */
+ return;
+ }
+#endif
+ /* Transfer preparation. The request handler must have populated
+ correctly the fields ep0next, ep0n and ep0endcb using the macro
+ usbSetupTransfer().*/
+ max = (size_t)get_hword(&usbp->setup[6]);
+ /* The transfer size cannot exceed the specified amount.*/
+ if (usbp->ep0n > max) {
+ usbp->ep0n = max;
+ }
+ if ((usbp->setup[0] & USB_RTYPE_DIR_MASK) == USB_RTYPE_DIR_DEV2HOST) {
+ /* IN phase.*/
+ if (usbp->ep0n != 0U) {
+ /* Starts the transmit phase.*/
+ usbp->ep0state = USB_EP0_IN_TX;
+ osalSysLockFromISR();
+ usbStartTransmitI(usbp, 0, usbp->ep0next, usbp->ep0n);
+ osalSysUnlockFromISR();
+ }
+ else {
+ /* No transmission phase, directly receiving the zero sized status
+ packet.*/
+ usbp->ep0state = USB_EP0_OUT_WAITING_STS;
+#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
+ osalSysLockFromISR();
+ usbStartReceiveI(usbp, 0, NULL, 0);
+ osalSysUnlockFromISR();
+#else
+ usb_lld_end_setup(usbp, ep);
+#endif
+ }
+ }
+ else {
+ /* OUT phase.*/
+ if (usbp->ep0n != 0U) {
+ /* Starts the receive phase.*/
+ usbp->ep0state = USB_EP0_OUT_RX;
+ osalSysLockFromISR();
+ usbStartReceiveI(usbp, 0, usbp->ep0next, usbp->ep0n);
+ osalSysUnlockFromISR();
+ }
+ else {
+ /* No receive phase, directly sending the zero sized status
+ packet.*/
+ usbp->ep0state = USB_EP0_IN_SENDING_STS;
+#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
+ osalSysLockFromISR();
+ usbStartTransmitI(usbp, 0, NULL, 0);
+ osalSysUnlockFromISR();
+#else
+ usb_lld_end_setup(usbp, ep);
+#endif
+ }
+ }
+}
+
+/**
+ * @brief Default EP0 IN callback.
+ * @details This function is used by the low level driver as default handler
+ * for EP0 IN events.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number, always zero
+ *
+ * @notapi
+ */
+void _usb_ep0in(USBDriver *usbp, usbep_t ep) {
+ size_t max;
+
+ (void)ep;
+ switch (usbp->ep0state) {
+ case USB_EP0_IN_TX:
+ max = (size_t)get_hword(&usbp->setup[6]);
+ /* If the transmitted size is less than the requested size and it is a
+ multiple of the maximum packet size then a zero size packet must be
+ transmitted.*/
+ if ((usbp->ep0n < max) &&
+ ((usbp->ep0n % usbp->epc[0]->in_maxsize) == 0U)) {
+ osalSysLockFromISR();
+ usbStartTransmitI(usbp, 0, NULL, 0);
+ osalSysUnlockFromISR();
+ usbp->ep0state = USB_EP0_IN_WAITING_TX0;
+ return;
+ }
+ /* Falls into, it is intentional.*/
+ case USB_EP0_IN_WAITING_TX0:
+ /* Transmit phase over, receiving the zero sized status packet.*/
+ usbp->ep0state = USB_EP0_OUT_WAITING_STS;
+#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
+ osalSysLockFromISR();
+ usbStartReceiveI(usbp, 0, NULL, 0);
+ osalSysUnlockFromISR();
+#else
+ usb_lld_end_setup(usbp, ep);
+#endif
+ return;
+ case USB_EP0_IN_SENDING_STS:
+ /* Status packet sent, invoking the callback if defined.*/
+ if (usbp->ep0endcb != NULL) {
+ usbp->ep0endcb(usbp);
+ }
+ usbp->ep0state = USB_EP0_STP_WAITING;
+ return;
+ case USB_EP0_STP_WAITING:
+ case USB_EP0_OUT_WAITING_STS:
+ case USB_EP0_OUT_RX:
+ /* All the above are invalid states in the IN phase.*/
+ osalDbgAssert(false, "EP0 state machine error");
+ /* Falling through is intentional.*/
+ case USB_EP0_ERROR:
+ /* Error response, the state machine goes into an error state, the low
+ level layer will have to reset it to USB_EP0_WAITING_SETUP after
+ receiving a SETUP packet.*/
+ usb_lld_stall_in(usbp, 0);
+ usb_lld_stall_out(usbp, 0);
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED);
+ usbp->ep0state = USB_EP0_ERROR;
+ return;
+ default:
+ osalDbgAssert(false, "EP0 state machine invalid state");
+ }
+}
+
+/**
+ * @brief Default EP0 OUT callback.
+ * @details This function is used by the low level driver as default handler
+ * for EP0 OUT events.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number, always zero
+ *
+ * @notapi
+ */
+void _usb_ep0out(USBDriver *usbp, usbep_t ep) {
+
+ (void)ep;
+ switch (usbp->ep0state) {
+ case USB_EP0_OUT_RX:
+ /* Receive phase over, sending the zero sized status packet.*/
+ usbp->ep0state = USB_EP0_IN_SENDING_STS;
+#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
+ osalSysLockFromISR();
+ usbStartTransmitI(usbp, 0, NULL, 0);
+ osalSysUnlockFromISR();
+#else
+ usb_lld_end_setup(usbp, ep);
+#endif
+ return;
+ case USB_EP0_OUT_WAITING_STS:
+ /* Status packet received, it must be zero sized, invoking the callback
+ if defined.*/
+#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
+ if (usbGetReceiveTransactionSizeX(usbp, 0) != 0U) {
+ break;
+ }
+#endif
+ if (usbp->ep0endcb != NULL) {
+ usbp->ep0endcb(usbp);
+ }
+ usbp->ep0state = USB_EP0_STP_WAITING;
+ return;
+ case USB_EP0_STP_WAITING:
+ case USB_EP0_IN_TX:
+ case USB_EP0_IN_WAITING_TX0:
+ case USB_EP0_IN_SENDING_STS:
+ /* All the above are invalid states in the IN phase.*/
+ osalDbgAssert(false, "EP0 state machine error");
+ /* Falling through is intentional.*/
+ case USB_EP0_ERROR:
+ /* Error response, the state machine goes into an error state, the low
+ level layer will have to reset it to USB_EP0_WAITING_SETUP after
+ receiving a SETUP packet.*/
+ usb_lld_stall_in(usbp, 0);
+ usb_lld_stall_out(usbp, 0);
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED);
+ usbp->ep0state = USB_EP0_ERROR;
+ return;
+ default:
+ osalDbgAssert(false, "EP0 state machine invalid state");
+ }
+}
+
+#endif /* HAL_USE_USB == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_wdg.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_wdg.c
new file mode 100644
index 0000000000..ed338e9e0d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/hal_wdg.c
@@ -0,0 +1,124 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_wdg.c
+ * @brief WDG Driver code.
+ *
+ * @addtogroup WDG
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief WDG Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void wdgInit(void) {
+
+ wdg_lld_init();
+}
+
+/**
+ * @brief Configures and activates the WDG peripheral.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ * @param[in] config pointer to the @p WDGConfig object
+ *
+ * @api
+ */
+void wdgStart(WDGDriver *wdgp, const WDGConfig *config) {
+
+ osalDbgCheck((wdgp != NULL) && (config != NULL));
+
+ osalSysLock();
+ osalDbgAssert((wdgp->state == WDG_STOP) || (wdgp->state == WDG_READY),
+ "invalid state");
+ wdgp->config = config;
+ wdg_lld_start(wdgp);
+ wdgp->state = WDG_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the WDG peripheral.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @api
+ */
+void wdgStop(WDGDriver *wdgp) {
+
+ osalDbgCheck(wdgp != NULL);
+
+ osalSysLock();
+
+ osalDbgAssert((wdgp->state == WDG_STOP) || (wdgp->state == WDG_READY),
+ "invalid state");
+
+ wdg_lld_stop(wdgp);
+ wdgp->config = NULL;
+ wdgp->state = WDG_STOP;
+
+ osalSysUnlock();
+}
+
+/**
+ * @brief Resets WDG's counter.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @api
+ */
+void wdgReset(WDGDriver *wdgp) {
+
+ osalDbgCheck(wdgp != NULL);
+
+ osalSysLock();
+ osalDbgAssert(wdgp->state == WDG_READY, "not ready");
+ wdgResetI(wdgp);
+ osalSysUnlock();
+}
+
+#endif /* HAL_USE_WDG == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/icu.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/icu.c
deleted file mode 100644
index 698a776218..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/icu.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file icu.c
- * @brief ICU Driver code.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief ICU Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void icuInit(void) {
-
- icu_lld_init();
-}
-
-/**
- * @brief Initializes the standard part of a @p ICUDriver structure.
- *
- * @param[out] icup pointer to the @p ICUDriver object
- *
- * @init
- */
-void icuObjectInit(ICUDriver *icup) {
-
- icup->state = ICU_STOP;
- icup->config = NULL;
-}
-
-/**
- * @brief Configures and activates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @param[in] config pointer to the @p ICUConfig object
- *
- * @api
- */
-void icuStart(ICUDriver *icup, const ICUConfig *config) {
-
- chDbgCheck((icup != NULL) && (config != NULL), "icuStart");
-
- chSysLock();
- chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY),
- "icuStart(), #1", "invalid state");
- icup->config = config;
- icu_lld_start(icup);
- icup->state = ICU_READY;
- chSysUnlock();
-}
-
-/**
- * @brief Deactivates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @api
- */
-void icuStop(ICUDriver *icup) {
-
- chDbgCheck(icup != NULL, "icuStop");
-
- chSysLock();
- chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY),
- "icuStop(), #1", "invalid state");
- icu_lld_stop(icup);
- icup->state = ICU_STOP;
- chSysUnlock();
-}
-
-/**
- * @brief Enables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @api
- */
-void icuEnable(ICUDriver *icup) {
-
- chDbgCheck(icup != NULL, "icuEnable");
-
- chSysLock();
- chDbgAssert(icup->state == ICU_READY, "icuEnable(), #1", "invalid state");
- icu_lld_enable(icup);
- icup->state = ICU_WAITING;
- chSysUnlock();
-}
-
-/**
- * @brief Disables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @api
- */
-void icuDisable(ICUDriver *icup) {
-
- chDbgCheck(icup != NULL, "icuDisable");
-
- chSysLock();
- chDbgAssert((icup->state == ICU_READY) || (icup->state == ICU_WAITING) ||
- (icup->state == ICU_ACTIVE) || (icup->state == ICU_IDLE),
- "icuDisable(), #1", "invalid state");
- icu_lld_disable(icup);
- icup->state = ICU_READY;
- chSysUnlock();
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mmcsd.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mmcsd.c
deleted file mode 100644
index 6b21a6214d..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/mmcsd.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file mmcsd.c
- * @brief MMC/SD cards common code.
- *
- * @addtogroup MMCSD
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Gets a bit field from a words array.
- * @note The bit zero is the LSb of the first word.
- *
- * @param[in] data pointer to the words array
- * @param[in] end bit offset of the last bit of the field, inclusive
- * @param[in] start bit offset of the first bit of the field, inclusive
- *
- * @return The bits field value, left aligned.
- *
- * @notapi
- */
-static uint32_t mmcsd_get_slice(uint32_t *data, uint32_t end, uint32_t start) {
- unsigned startidx, endidx, startoff;
- uint32_t endmask;
-
- chDbgCheck((end >= start) && ((end - start) < 32), "mmcsd_get_slice");
-
- startidx = start / 32;
- startoff = start % 32;
- endidx = end / 32;
- endmask = (1 << ((end % 32) + 1)) - 1;
-
- /* One or two pieces?*/
- if (startidx < endidx)
- return (data[startidx] >> startoff) | /* Two pieces case. */
- ((data[endidx] & endmask) << (32 - startoff));
- return (data[startidx] & endmask) >> startoff; /* One piece case. */
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Extract card capacity from a CSD.
- * @details The capacity is returned as number of available blocks.
- *
- * @param[in] csd the CSD record
- *
- * @return The card capacity.
- * @retval 0 CSD format error
- */
-uint32_t mmcsdGetCapacity(uint32_t csd[4]) {
-
- switch (csd[3] >> 30) {
- uint32_t a, b, c;
- case 0:
- /* CSD version 1.0 */
- a = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE);
- b = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE);
- c = mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE);
- return (a + 1) << (b + 2) << (c - 9); /* 2^9 == MMCSD_BLOCK_SIZE. */
- case 1:
- /* CSD version 2.0.*/
- return 1024 * (mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE) + 1);
- default:
- /* Reserved value detected.*/
- return 0;
- }
-}
-
-#endif /* HAL_USE_MMC_SPI || HAL_USE_SDC */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/pwm.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/pwm.c
deleted file mode 100644
index dbf403d9f3..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/pwm.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file pwm.c
- * @brief PWM Driver code.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief PWM Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void pwmInit(void) {
-
- pwm_lld_init();
-}
-
-/**
- * @brief Initializes the standard part of a @p PWMDriver structure.
- *
- * @param[out] pwmp pointer to a @p PWMDriver object
- *
- * @init
- */
-void pwmObjectInit(PWMDriver *pwmp) {
-
- pwmp->state = PWM_STOP;
- pwmp->config = NULL;
-#if defined(PWM_DRIVER_EXT_INIT_HOOK)
- PWM_DRIVER_EXT_INIT_HOOK(pwmp);
-#endif
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- * @note Starting a driver that is already in the @p PWM_READY state
- * disables all the active channels.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] config pointer to a @p PWMConfig object
- *
- * @api
- */
-void pwmStart(PWMDriver *pwmp, const PWMConfig *config) {
-
- chDbgCheck((pwmp != NULL) && (config != NULL), "pwmStart");
-
- chSysLock();
- chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY),
- "pwmStart(), #1", "invalid state");
- pwmp->config = config;
- pwmp->period = config->period;
- pwm_lld_start(pwmp);
- pwmp->state = PWM_READY;
- chSysUnlock();
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @api
- */
-void pwmStop(PWMDriver *pwmp) {
-
- chDbgCheck(pwmp != NULL, "pwmStop");
-
- chSysLock();
- chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY),
- "pwmStop(), #1", "invalid state");
- pwm_lld_stop(pwmp);
- pwmp->state = PWM_STOP;
- chSysUnlock();
-}
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @api
- */
-void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period) {
-
- chDbgCheck(pwmp != NULL, "pwmChangePeriod");
-
- chSysLock();
- chDbgAssert(pwmp->state == PWM_READY,
- "pwmChangePeriod(), #1", "invalid state");
- pwmChangePeriodI(pwmp, period);
- chSysUnlock();
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @api
- */
-void pwmEnableChannel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
-
- chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS),
- "pwmEnableChannel");
-
- chSysLock();
- chDbgAssert(pwmp->state == PWM_READY,
- "pwmEnableChannel(), #1", "not ready");
- pwm_lld_enable_channel(pwmp, channel, width);
- chSysUnlock();
-}
-
-/**
- * @brief Disables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @api
- */
-void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel) {
-
- chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS),
- "pwmEnableChannel");
-
- chSysLock();
- chDbgAssert(pwmp->state == PWM_READY,
- "pwmDisableChannel(), #1", "not ready");
- pwm_lld_disable_channel(pwmp, channel);
- chSysUnlock();
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/rtc.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/rtc.c
deleted file mode 100644
index 25ae0e6796..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/rtc.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file rtc.c
- * @brief RTC Driver code.
- *
- * @addtogroup RTC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief RTC Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void rtcInit(void) {
-
- rtc_lld_init();
-}
-
-/**
- * @brief Set current time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec) {
-
- chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcSetTime");
-
- chSysLock();
- rtcSetTimeI(rtcp, timespec);
- chSysUnlock();
-}
-
-/**
- * @brief Get current time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec) {
-
- chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcGetTime");
-
- chSysLock();
- rtcGetTimeI(rtcp, timespec);
- chSysUnlock();
-}
-
-#if (RTC_ALARMS > 0) || defined(__DOXYGEN__)
-/**
- * @brief Set alarm time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] alarm alarm identifier
- * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL
- *
- * @api
- */
-void rtcSetAlarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
- const RTCAlarm *alarmspec) {
-
- chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS), "rtcSetAlarm");
-
- chSysLock();
- rtcSetAlarmI(rtcp, alarm, alarmspec);
- chSysUnlock();
-}
-
-/**
- * @brief Get current alarm.
- * @note If an alarm has not been set then the returned alarm specification
- * is not meaningful.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] alarm alarm identifier
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @api
- */
-void rtcGetAlarm(RTCDriver *rtcp,
- rtcalarm_t alarm,
- RTCAlarm *alarmspec) {
-
- chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS) && (alarmspec != NULL),
- "rtcGetAlarm");
-
- chSysLock();
- rtcGetAlarmI(rtcp, alarm, alarmspec);
- chSysUnlock();
-}
-#endif /* RTC_ALARMS > 0 */
-
-#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__)
-/**
- * @brief Enables or disables RTC callbacks.
- * @details This function enables or disables the callback, use a @p NULL
- * pointer in order to disable it.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] callback callback function pointer or @p NULL
- *
- * @api
- */
-void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback) {
-
- chDbgCheck((rtcp != NULL), "rtcSetCallback");
-
- chSysLock();
- rtcSetCallbackI(rtcp, callback);
- chSysUnlock();
-}
-#endif /* RTC_SUPPORTS_CALLBACKS */
-
-/**
- * @brief Get current time in format suitable for usage in FatFS.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @return FAT time value.
- *
- * @api
- */
-uint32_t rtcGetTimeFat(RTCDriver *rtcp) {
-
- chDbgCheck((rtcp != NULL), "rtcSetTime");
- return rtc_lld_get_time_fat(rtcp);
-}
-
-#endif /* HAL_USE_RTC */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/sdc.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/sdc.c
deleted file mode 100644
index 55baa6e7a4..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/sdc.c
+++ /dev/null
@@ -1,587 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file sdc.c
- * @brief SDC Driver code.
- *
- * @addtogroup SDC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Virtual methods table.
- */
-static const struct SDCDriverVMT sdc_vmt = {
- (bool_t (*)(void *))sdc_lld_is_card_inserted,
- (bool_t (*)(void *))sdc_lld_is_write_protected,
- (bool_t (*)(void *))sdcConnect,
- (bool_t (*)(void *))sdcDisconnect,
- (bool_t (*)(void *, uint32_t, uint8_t *, uint32_t))sdcRead,
- (bool_t (*)(void *, uint32_t, const uint8_t *, uint32_t))sdcWrite,
- (bool_t (*)(void *))sdcSync,
- (bool_t (*)(void *, BlockDeviceInfo *))sdcGetInfo
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Wait for the card to complete pending operations.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- *
- * @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
- *
- * @notapi
- */
-bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp) {
- uint32_t resp[1];
-
- while (TRUE) {
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_STATUS,
- sdcp->rca, resp) ||
- MMCSD_R1_ERROR(resp[0]))
- return CH_FAILED;
- switch (MMCSD_R1_STS(resp[0])) {
- case MMCSD_STS_TRAN:
- return CH_SUCCESS;
- case MMCSD_STS_DATA:
- case MMCSD_STS_RCV:
- case MMCSD_STS_PRG:
-#if SDC_NICE_WAITING
- chThdSleepMilliseconds(1);
-#endif
- continue;
- default:
- /* The card should have been initialized so any other state is not
- valid and is reported as an error.*/
- return CH_FAILED;
- }
- }
- /* If something going too wrong.*/
- return CH_FAILED;
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief SDC Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void sdcInit(void) {
-
- sdc_lld_init();
-}
-
-/**
- * @brief Initializes the standard part of a @p SDCDriver structure.
- *
- * @param[out] sdcp pointer to the @p SDCDriver object
- *
- * @init
- */
-void sdcObjectInit(SDCDriver *sdcp) {
-
- sdcp->vmt = &sdc_vmt;
- sdcp->state = BLK_STOP;
- sdcp->errors = SDC_NO_ERROR;
- sdcp->config = NULL;
- sdcp->capacity = 0;
-}
-
-/**
- * @brief Configures and activates the SDC peripheral.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- * @param[in] config pointer to the @p SDCConfig object, can be @p NULL if
- * the driver supports a default configuration or
- * requires no configuration
- *
- * @api
- */
-void sdcStart(SDCDriver *sdcp, const SDCConfig *config) {
-
- chDbgCheck(sdcp != NULL, "sdcStart");
-
- chSysLock();
- chDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE),
- "sdcStart(), #1", "invalid state");
- sdcp->config = config;
- sdc_lld_start(sdcp);
- sdcp->state = BLK_ACTIVE;
- chSysUnlock();
-}
-
-/**
- * @brief Deactivates the SDC peripheral.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- *
- * @api
- */
-void sdcStop(SDCDriver *sdcp) {
-
- chDbgCheck(sdcp != NULL, "sdcStop");
-
- chSysLock();
- chDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE),
- "sdcStop(), #1", "invalid state");
- sdc_lld_stop(sdcp);
- sdcp->state = BLK_STOP;
- chSysUnlock();
-}
-
-/**
- * @brief Performs the initialization procedure on the inserted card.
- * @details This function should be invoked when a card is inserted and
- * brings the driver in the @p BLK_READY state where it is possible
- * to perform read and write operations.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- *
- * @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
- *
- * @api
- */
-bool_t sdcConnect(SDCDriver *sdcp) {
- uint32_t resp[1];
-
- chDbgCheck(sdcp != NULL, "sdcConnect");
- chDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY),
- "mmcConnect(), #1", "invalid state");
-
- /* Connection procedure in progress.*/
- sdcp->state = BLK_CONNECTING;
-
- /* Card clock initialization.*/
- sdc_lld_start_clk(sdcp);
-
- /* Enforces the initial card state.*/
- sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0);
-
- /* V2.0 cards detection.*/
- if (!sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_IF_COND,
- MMCSD_CMD8_PATTERN, resp)) {
- sdcp->cardmode = SDC_MODE_CARDTYPE_SDV20;
- /* Voltage verification.*/
- if (((resp[0] >> 8) & 0xF) != 1)
- goto failed;
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) ||
- MMCSD_R1_ERROR(resp[0]))
- goto failed;
- }
- else {
-#if SDC_MMC_SUPPORT
- /* MMC or SD V1.1 detection.*/
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) ||
- MMCSD_R1_ERROR(resp[0]))
- sdcp->cardmode = SDC_MODE_CARDTYPE_MMC;
- else
-#endif /* SDC_MMC_SUPPORT */
- {
- sdcp->cardmode = SDC_MODE_CARDTYPE_SDV11;
-
- /* Reset error flag illegal command.*/
- sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0);
- }
- }
-
-#if SDC_MMC_SUPPORT
- if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_MMC) {
- /* TODO: MMC initialization.*/
- goto failed;
- }
- else
-#endif /* SDC_MMC_SUPPORT */
- {
- unsigned i;
- uint32_t ocr;
-
- /* SD initialization.*/
- if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_SDV20)
- ocr = 0xC0100000;
- else
- ocr = 0x80100000;
-
- /* SD-type initialization. */
- i = 0;
- while (TRUE) {
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) ||
- MMCSD_R1_ERROR(resp[0]))
- goto failed;
- if (sdc_lld_send_cmd_short(sdcp, MMCSD_CMD_APP_OP_COND, ocr, resp))
- goto failed;
- if ((resp[0] & 0x80000000) != 0) {
- if (resp[0] & 0x40000000)
- sdcp->cardmode |= SDC_MODE_HIGH_CAPACITY;
- break;
- }
- if (++i >= SDC_INIT_RETRY)
- goto failed;
- chThdSleepMilliseconds(10);
- }
- }
-
- /* Reads CID.*/
- if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_ALL_SEND_CID, 0, sdcp->cid))
- goto failed;
-
- /* Asks for the RCA.*/
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_RELATIVE_ADDR,
- 0, &sdcp->rca))
- goto failed;
-
- /* Reads CSD.*/
- if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_SEND_CSD,
- sdcp->rca, sdcp->csd))
- goto failed;
-
- /* Switches to high speed.*/
- sdc_lld_set_data_clk(sdcp);
-
- /* Selects the card for operations.*/
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEL_DESEL_CARD,
- sdcp->rca, resp))
- goto failed;
-
- /* Block length fixed at 512 bytes.*/
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BLOCKLEN,
- MMCSD_BLOCK_SIZE, resp) ||
- MMCSD_R1_ERROR(resp[0]))
- goto failed;
-
- /* Switches to wide bus mode.*/
- switch (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) {
- case SDC_MODE_CARDTYPE_SDV11:
- case SDC_MODE_CARDTYPE_SDV20:
- sdc_lld_set_bus_mode(sdcp, SDC_MODE_4BIT);
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, sdcp->rca, resp) ||
- MMCSD_R1_ERROR(resp[0]))
- goto failed;
- if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BUS_WIDTH, 2, resp) ||
- MMCSD_R1_ERROR(resp[0]))
- goto failed;
- break;
- }
-
- /* Determine capacity.*/
- sdcp->capacity = mmcsdGetCapacity(sdcp->csd);
- if (sdcp->capacity == 0)
- goto failed;
-
- /* Initialization complete.*/
- sdcp->state = BLK_READY;
- return CH_SUCCESS;
-
- /* Connection failed, state reset to BLK_ACTIVE.*/
-failed:
- sdc_lld_stop_clk(sdcp);
- sdcp->state = BLK_ACTIVE;
- return CH_FAILED;
-}
-
-/**
- * @brief Brings the driver in a state safe for card removal.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- *
- * @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
- *
- * @api
- */
-bool_t sdcDisconnect(SDCDriver *sdcp) {
-
- chDbgCheck(sdcp != NULL, "sdcDisconnect");
-
- chSysLock();
- chDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY),
- "sdcDisconnect(), #1", "invalid state");
- if (sdcp->state == BLK_ACTIVE) {
- chSysUnlock();
- return CH_SUCCESS;
- }
- sdcp->state = BLK_DISCONNECTING;
- chSysUnlock();
-
- /* Waits for eventual pending operations completion.*/
- if (_sdc_wait_for_transfer_state(sdcp)) {
- sdc_lld_stop_clk(sdcp);
- sdcp->state = BLK_ACTIVE;
- return CH_FAILED;
- }
-
- /* Card clock stopped.*/
- sdc_lld_stop_clk(sdcp);
- sdcp->state = BLK_ACTIVE;
- return CH_SUCCESS;
-}
-
-/**
- * @brief Reads one or more blocks.
- * @pre The driver must be in the @p BLK_READY state after a successful
- * sdcConnect() invocation.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- * @param[in] startblk first block to read
- * @param[out] buf pointer to the read buffer
- * @param[in] n number of blocks to read
- *
- * @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
- *
- * @api
- */
-bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk,
- uint8_t *buf, uint32_t n) {
- bool_t status;
-
- chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcRead");
- chDbgAssert(sdcp->state == BLK_READY, "sdcRead(), #1", "invalid state");
-
- if ((startblk + n - 1) > sdcp->capacity){
- sdcp->errors |= SDC_OVERFLOW_ERROR;
- return CH_FAILED;
- }
-
- /* Read operation in progress.*/
- sdcp->state = BLK_READING;
-
- status = sdc_lld_read(sdcp, startblk, buf, n);
-
- /* Read operation finished.*/
- sdcp->state = BLK_READY;
- return status;
-}
-
-/**
- * @brief Writes one or more blocks.
- * @pre The driver must be in the @p BLK_READY state after a successful
- * sdcConnect() invocation.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- * @param[in] startblk first block to write
- * @param[out] buf pointer to the write buffer
- * @param[in] n number of blocks to write
- *
- * @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
- *
- * @api
- */
-bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk,
- const uint8_t *buf, uint32_t n) {
- bool_t status;
-
- chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcWrite");
- chDbgAssert(sdcp->state == BLK_READY, "sdcWrite(), #1", "invalid state");
-
- if ((startblk + n - 1) > sdcp->capacity){
- sdcp->errors |= SDC_OVERFLOW_ERROR;
- return CH_FAILED;
- }
-
- /* Write operation in progress.*/
- sdcp->state = BLK_WRITING;
-
- status = sdc_lld_write(sdcp, startblk, buf, n);
-
- /* Write operation finished.*/
- sdcp->state = BLK_READY;
- return status;
-}
-
-/**
- * @brief Returns the errors mask associated to the previous operation.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- * @return The errors mask.
- *
- * @api
- */
-sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp) {
- sdcflags_t flags;
-
- chDbgCheck(sdcp != NULL, "sdcGetAndClearErrors");
- chDbgAssert(sdcp->state == BLK_READY,
- "sdcGetAndClearErrors(), #1", "invalid state");
-
- chSysLock();
- flags = sdcp->errors;
- sdcp->errors = SDC_NO_ERROR;
- chSysUnlock();
- return flags;
-}
-
-/**
- * @brief Waits for card idle condition.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- *
- * @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
- *
- * @api
- */
-bool_t sdcSync(SDCDriver *sdcp) {
- bool_t result;
-
- chDbgCheck(sdcp != NULL, "sdcSync");
-
- if (sdcp->state != BLK_READY)
- return CH_FAILED;
-
- /* Synchronization operation in progress.*/
- sdcp->state = BLK_SYNCING;
-
- result = sdc_lld_sync(sdcp);
-
- /* Synchronization operation finished.*/
- sdcp->state = BLK_READY;
- return result;
-}
-
-/**
- * @brief Returns the media info.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- * @param[out] bdip pointer to a @p BlockDeviceInfo structure
- *
- * @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
- *
- * @api
- */
-bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip) {
-
- chDbgCheck((sdcp != NULL) && (bdip != NULL), "sdcGetInfo");
-
- if (sdcp->state != BLK_READY)
- return CH_FAILED;
-
- bdip->blk_num = sdcp->capacity;
- bdip->blk_size = MMCSD_BLOCK_SIZE;
-
- return CH_SUCCESS;
-}
-
-
-/**
- * @brief Erases the supplied blocks.
- *
- * @param[in] sdcp pointer to the @p SDCDriver object
- * @param[in] startblk starting block number
- * @param[in] endblk ending block number
- *
- * @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
- *
- * @api
- */
-bool_t sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) {
- uint32_t resp[1];
-
- chDbgCheck((sdcp != NULL), "sdcErase");
- chDbgAssert(sdcp->state == BLK_READY, "sdcErase(), #1", "invalid state");
-
- /* Erase operation in progress.*/
- sdcp->state = BLK_WRITING;
-
- /* Handling command differences between HC and normal cards.*/
- if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) {
- startblk *= MMCSD_BLOCK_SIZE;
- endblk *= MMCSD_BLOCK_SIZE;
- }
-
- _sdc_wait_for_transfer_state(sdcp);
-
- if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_START,
- startblk, resp) != CH_SUCCESS) ||
- MMCSD_R1_ERROR(resp[0]))
- goto failed;
-
- if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_END,
- endblk, resp) != CH_SUCCESS) ||
- MMCSD_R1_ERROR(resp[0]))
- goto failed;
-
- if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE,
- 0, resp) != CH_SUCCESS) ||
- MMCSD_R1_ERROR(resp[0]))
- goto failed;
-
- /* Quick sleep to allow it to transition to programming or receiving state */
- /* TODO: ??????????????????????????? */
-
- /* Wait for it to return to transfer state to indicate it has finished erasing */
- _sdc_wait_for_transfer_state(sdcp);
-
- sdcp->state = BLK_READY;
- return CH_SUCCESS;
-
-failed:
- sdcp->state = BLK_READY;
- return CH_FAILED;
-}
-
-#endif /* HAL_USE_SDC */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/serial_usb.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/serial_usb.c
deleted file mode 100644
index 565b2ce1a7..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/serial_usb.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file serial_usb.c
- * @brief Serial over USB Driver code.
- *
- * @addtogroup SERIAL_USB
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*
- * Current Line Coding.
- */
-static cdc_linecoding_t linecoding = {
- {0x00, 0x96, 0x00, 0x00}, /* 38400. */
- LC_STOP_1, LC_PARITY_NONE, 8
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*
- * Interface implementation.
- */
-
-static size_t write(void *ip, const uint8_t *bp, size_t n) {
-
- return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp,
- n, TIME_INFINITE);
-}
-
-static size_t read(void *ip, uint8_t *bp, size_t n) {
-
- return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp,
- n, TIME_INFINITE);
-}
-
-static msg_t put(void *ip, uint8_t b) {
-
- return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, TIME_INFINITE);
-}
-
-static msg_t get(void *ip) {
-
- return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, TIME_INFINITE);
-}
-
-static msg_t putt(void *ip, uint8_t b, systime_t timeout) {
-
- return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, timeout);
-}
-
-static msg_t gett(void *ip, systime_t timeout) {
-
- return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, timeout);
-}
-
-static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) {
-
- return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, n, time);
-}
-
-static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) {
-
- return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, n, time);
-}
-
-static const struct SerialUSBDriverVMT vmt = {
- write, read, put, get,
- putt, gett, writet, readt
-};
-
-/**
- * @brief Notification of data removed from the input queue.
- */
-static void inotify(GenericQueue *qp) {
- size_t n, maxsize;
- SerialUSBDriver *sdup = chQGetLink(qp);
-
- /* If the USB driver is not in the appropriate state then transactions
- must not be started.*/
- if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) ||
- (sdup->state != SDU_READY))
- return;
-
- /* If there is in the queue enough space to hold at least one packet and
- a transaction is not yet started then a new transaction is started for
- the available space.*/
- maxsize = sdup->config->usbp->epc[sdup->config->bulk_out]->out_maxsize;
- if (!usbGetReceiveStatusI(sdup->config->usbp, sdup->config->bulk_out) &&
- ((n = chIQGetEmptyI(&sdup->iqueue)) >= maxsize)) {
- chSysUnlock();
-
- n = (n / maxsize) * maxsize;
- usbPrepareQueuedReceive(sdup->config->usbp,
- sdup->config->bulk_out,
- &sdup->iqueue, n);
-
- chSysLock();
- usbStartReceiveI(sdup->config->usbp, sdup->config->bulk_out);
- }
-}
-
-/**
- * @brief Notification of data inserted into the output queue.
- */
-static void onotify(GenericQueue *qp) {
- size_t n;
- SerialUSBDriver *sdup = chQGetLink(qp);
-
- /* If the USB driver is not in the appropriate state then transactions
- must not be started.*/
- if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) ||
- (sdup->state != SDU_READY))
- return;
-
- /* If there is not an ongoing transaction and the output queue contains
- data then a new transaction is started.*/
- if (!usbGetTransmitStatusI(sdup->config->usbp, sdup->config->bulk_in) &&
- ((n = chOQGetFullI(&sdup->oqueue)) > 0)) {
- chSysUnlock();
-
- usbPrepareQueuedTransmit(sdup->config->usbp,
- sdup->config->bulk_in,
- &sdup->oqueue, n);
-
- chSysLock();
- usbStartTransmitI(sdup->config->usbp, sdup->config->bulk_in);
- }
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Serial Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void sduInit(void) {
-}
-
-/**
- * @brief Initializes a generic full duplex driver object.
- * @details The HW dependent part of the initialization has to be performed
- * outside, usually in the hardware initialization code.
- *
- * @param[out] sdup pointer to a @p SerialUSBDriver structure
- *
- * @init
- */
-void sduObjectInit(SerialUSBDriver *sdup) {
-
- sdup->vmt = &vmt;
- chEvtInit(&sdup->event);
- sdup->state = SDU_STOP;
- chIQInit(&sdup->iqueue, sdup->ib, SERIAL_USB_BUFFERS_SIZE, inotify, sdup);
- chOQInit(&sdup->oqueue, sdup->ob, SERIAL_USB_BUFFERS_SIZE, onotify, sdup);
-}
-
-/**
- * @brief Configures and starts the driver.
- *
- * @param[in] sdup pointer to a @p SerialUSBDriver object
- * @param[in] config the serial over USB driver configuration
- *
- * @api
- */
-void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config) {
- USBDriver *usbp = config->usbp;
-
- chDbgCheck(sdup != NULL, "sduStart");
-
- chSysLock();
- chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY),
- "sduStart(), #1",
- "invalid state");
- usbp->in_params[config->bulk_in - 1] = sdup;
- usbp->out_params[config->bulk_out - 1] = sdup;
- usbp->in_params[config->int_in - 1] = sdup;
- sdup->config = config;
- sdup->state = SDU_READY;
- chSysUnlock();
-}
-
-/**
- * @brief Stops the driver.
- * @details Any thread waiting on the driver's queues will be awakened with
- * the message @p Q_RESET.
- *
- * @param[in] sdup pointer to a @p SerialUSBDriver object
- *
- * @api
- */
-void sduStop(SerialUSBDriver *sdup) {
- USBDriver *usbp = sdup->config->usbp;
-
- chDbgCheck(sdup != NULL, "sdStop");
-
- chSysLock();
-
- chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY),
- "sduStop(), #1",
- "invalid state");
-
- /* Driver in stopped state.*/
- usbp->in_params[sdup->config->bulk_in - 1] = NULL;
- usbp->out_params[sdup->config->bulk_out - 1] = NULL;
- usbp->in_params[sdup->config->int_in - 1] = NULL;
- sdup->state = SDU_STOP;
-
- /* Queues reset in order to signal the driver stop to the application.*/
- chnAddFlagsI(sdup, CHN_DISCONNECTED);
- chIQResetI(&sdup->iqueue);
- chOQResetI(&sdup->oqueue);
- chSchRescheduleS();
-
- chSysUnlock();
-}
-
-/**
- * @brief USB device configured handler.
- *
- * @param[in] sdup pointer to a @p SerialUSBDriver object
- *
- * @iclass
- */
-void sduConfigureHookI(SerialUSBDriver *sdup) {
- USBDriver *usbp = sdup->config->usbp;
-
- chIQResetI(&sdup->iqueue);
- chOQResetI(&sdup->oqueue);
- chnAddFlagsI(sdup, CHN_CONNECTED);
-
- /* Starts the first OUT transaction immediately.*/
- usbPrepareQueuedReceive(usbp, sdup->config->bulk_out, &sdup->iqueue,
- usbp->epc[sdup->config->bulk_out]->out_maxsize);
- usbStartReceiveI(usbp, sdup->config->bulk_out);
-}
-
-/**
- * @brief Default requests hook.
- * @details Applications wanting to use the Serial over USB driver can use
- * this function as requests hook in the USB configuration.
- * The following requests are emulated:
- * - CDC_GET_LINE_CODING.
- * - CDC_SET_LINE_CODING.
- * - CDC_SET_CONTROL_LINE_STATE.
- * .
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @return The hook status.
- * @retval TRUE Message handled internally.
- * @retval FALSE Message not handled.
- */
-bool_t sduRequestsHook(USBDriver *usbp) {
-
- if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) {
- switch (usbp->setup[1]) {
- case CDC_GET_LINE_CODING:
- usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL);
- return TRUE;
- case CDC_SET_LINE_CODING:
- usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL);
- return TRUE;
- case CDC_SET_CONTROL_LINE_STATE:
- /* Nothing to do, there are no control lines.*/
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return TRUE;
- default:
- return FALSE;
- }
- }
- return FALSE;
-}
-
-/**
- * @brief Default data transmitted callback.
- * @details The application must use this function as callback for the IN
- * data endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- */
-void sduDataTransmitted(USBDriver *usbp, usbep_t ep) {
- size_t n;
- SerialUSBDriver *sdup = usbp->in_params[ep - 1];
-
- if (sdup == NULL)
- return;
-
- chSysLockFromIsr();
- chnAddFlagsI(sdup, CHN_OUTPUT_EMPTY);
-
- if ((n = chOQGetFullI(&sdup->oqueue)) > 0) {
- /* The endpoint cannot be busy, we are in the context of the callback,
- so it is safe to transmit without a check.*/
- chSysUnlockFromIsr();
-
- usbPrepareQueuedTransmit(usbp, ep, &sdup->oqueue, n);
-
- chSysLockFromIsr();
- usbStartTransmitI(usbp, ep);
- }
- else if ((usbp->epc[ep]->in_state->txsize > 0) &&
- !(usbp->epc[ep]->in_state->txsize &
- (usbp->epc[ep]->in_maxsize - 1))) {
- /* Transmit zero sized packet in case the last one has maximum allowed
- size. Otherwise the recipient may expect more data coming soon and
- not return buffered data to app. See section 5.8.3 Bulk Transfer
- Packet Size Constraints of the USB Specification document.*/
- chSysUnlockFromIsr();
-
- usbPrepareQueuedTransmit(usbp, ep, &sdup->oqueue, 0);
-
- chSysLockFromIsr();
- usbStartTransmitI(usbp, ep);
- }
-
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief Default data received callback.
- * @details The application must use this function as callback for the OUT
- * data endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- */
-void sduDataReceived(USBDriver *usbp, usbep_t ep) {
- size_t n, maxsize;
- SerialUSBDriver *sdup = usbp->out_params[ep - 1];
-
- if (sdup == NULL)
- return;
-
- chSysLockFromIsr();
- chnAddFlagsI(sdup, CHN_INPUT_AVAILABLE);
-
- /* Writes to the input queue can only happen when there is enough space
- to hold at least one packet.*/
- maxsize = usbp->epc[ep]->out_maxsize;
- if ((n = chIQGetEmptyI(&sdup->iqueue)) >= maxsize) {
- /* The endpoint cannot be busy, we are in the context of the callback,
- so a packet is in the buffer for sure.*/
- chSysUnlockFromIsr();
-
- n = (n / maxsize) * maxsize;
- usbPrepareQueuedReceive(usbp, ep, &sdup->iqueue, n);
-
- chSysLockFromIsr();
- usbStartReceiveI(usbp, ep);
- }
-
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief Default data received callback.
- * @details The application must use this function as callback for the IN
- * interrupt endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- */
-void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep) {
-
- (void)usbp;
- (void)ep;
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/tm.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/tm.c
deleted file mode 100644
index de69a55246..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/tm.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file tm.c
- * @brief Time Measurement driver code.
- *
- * @addtogroup TM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_TM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Subsystem calibration value.
- */
-static halrtcnt_t measurement_offset;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Starts a measurement.
- *
- * @param[in,out] tmp pointer to a @p TimeMeasurement structure
- *
- * @notapi
- */
-static void tm_start(TimeMeasurement *tmp) {
-
- tmp->last = halGetCounterValue();
-}
-
-/**
- * @brief Stops a measurement.
- *
- * @param[in,out] tmp pointer to a @p TimeMeasurement structure
- *
- * @notapi
- */
-static void tm_stop(TimeMeasurement *tmp) {
-
- halrtcnt_t now = halGetCounterValue();
- tmp->last = now - tmp->last - measurement_offset;
- if (tmp->last > tmp->worst)
- tmp->worst = tmp->last;
- else if (tmp->last < tmp->best)
- tmp->best = tmp->last;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Initializes the Time Measurement unit.
- *
- * @init
- */
-void tmInit(void) {
- TimeMeasurement tm;
-
- /* Time Measurement subsystem calibration, it does a null measurement
- and calculates the call overhead which is subtracted to real
- measurements.*/
- measurement_offset = 0;
- tmObjectInit(&tm);
- tmStartMeasurement(&tm);
- tmStopMeasurement(&tm);
- measurement_offset = tm.last;
-}
-
-/**
- * @brief Initializes a @p TimeMeasurement object.
- *
- * @param[out] tmp pointer to a @p TimeMeasurement structure
- *
- * @init
- */
-void tmObjectInit(TimeMeasurement *tmp) {
-
- tmp->start = tm_start;
- tmp->stop = tm_stop;
- tmp->last = (halrtcnt_t)0;
- tmp->worst = (halrtcnt_t)0;
- tmp->best = (halrtcnt_t)-1;
-}
-
-#endif /* HAL_USE_TM */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/uart.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/uart.c
deleted file mode 100644
index e8b8479351..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/uart.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file uart.c
- * @brief UART Driver code.
- *
- * @addtogroup UART
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief UART Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void uartInit(void) {
-
- uart_lld_init();
-}
-
-/**
- * @brief Initializes the standard part of a @p UARTDriver structure.
- *
- * @param[out] uartp pointer to the @p UARTDriver object
- *
- * @init
- */
-void uartObjectInit(UARTDriver *uartp) {
-
- uartp->state = UART_STOP;
- uartp->txstate = UART_TX_IDLE;
- uartp->rxstate = UART_RX_IDLE;
- uartp->config = NULL;
- /* Optional, user-defined initializer.*/
-#if defined(UART_DRIVER_EXT_INIT_HOOK)
- UART_DRIVER_EXT_INIT_HOOK(uartp);
-#endif
-}
-
-/**
- * @brief Configures and activates the UART peripheral.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] config pointer to the @p UARTConfig object
- *
- * @api
- */
-void uartStart(UARTDriver *uartp, const UARTConfig *config) {
-
- chDbgCheck((uartp != NULL) && (config != NULL), "uartStart");
-
- chSysLock();
- chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY),
- "uartStart(), #1", "invalid state");
-
- uartp->config = config;
- uart_lld_start(uartp);
- uartp->state = UART_READY;
- chSysUnlock();
-}
-
-/**
- * @brief Deactivates the UART peripheral.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @api
- */
-void uartStop(UARTDriver *uartp) {
-
- chDbgCheck(uartp != NULL, "uartStop");
-
- chSysLock();
- chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY),
- "uartStop(), #1", "invalid state");
-
- uart_lld_stop(uartp);
- uartp->state = UART_STOP;
- uartp->txstate = UART_TX_IDLE;
- uartp->rxstate = UART_RX_IDLE;
- chSysUnlock();
-}
-
-/**
- * @brief Starts a transmission on the UART peripheral.
- * @note The buffers are organized as uint8_t arrays for data sizes below
- * or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] n number of data frames to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @api
- */
-void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf) {
-
- chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL),
- "uartStartSend");
-
- chSysLock();
- chDbgAssert(uartp->state == UART_READY,
- "uartStartSend(), #1", "is active");
- chDbgAssert(uartp->txstate != UART_TX_ACTIVE,
- "uartStartSend(), #2", "tx active");
-
- uart_lld_start_send(uartp, n, txbuf);
- uartp->txstate = UART_TX_ACTIVE;
- chSysUnlock();
-}
-
-/**
- * @brief Starts a transmission on the UART peripheral.
- * @note The buffers are organized as uint8_t arrays for data sizes below
- * or equal to 8 bits else it is organized as uint16_t arrays.
- * @note This function has to be invoked from a lock zone.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] n number of data frames to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @iclass
- */
-void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf) {
-
- chDbgCheckClassI();
- chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL),
- "uartStartSendI");
- chDbgAssert(uartp->state == UART_READY,
- "uartStartSendI(), #1", "is active");
- chDbgAssert(uartp->txstate != UART_TX_ACTIVE,
- "uartStartSendI(), #2", "tx active");
-
- uart_lld_start_send(uartp, n, txbuf);
- uartp->txstate = UART_TX_ACTIVE;
-}
-
-/**
- * @brief Stops any ongoing transmission.
- * @note Stopping a transmission also suppresses the transmission callbacks.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @return The number of data frames not transmitted by the
- * stopped transmit operation.
- * @retval 0 There was no transmit operation in progress.
- *
- * @api
- */
-size_t uartStopSend(UARTDriver *uartp) {
- size_t n;
-
- chDbgCheck(uartp != NULL, "uartStopSend");
-
- chSysLock();
- chDbgAssert(uartp->state == UART_READY, "uartStopSend(), #1", "not active");
-
- if (uartp->txstate == UART_TX_ACTIVE) {
- n = uart_lld_stop_send(uartp);
- uartp->txstate = UART_TX_IDLE;
- }
- else
- n = 0;
- chSysUnlock();
- return n;
-}
-
-/**
- * @brief Stops any ongoing transmission.
- * @note Stopping a transmission also suppresses the transmission callbacks.
- * @note This function has to be invoked from a lock zone.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @return The number of data frames not transmitted by the
- * stopped transmit operation.
- * @retval 0 There was no transmit operation in progress.
- *
- * @iclass
- */
-size_t uartStopSendI(UARTDriver *uartp) {
-
- chDbgCheckClassI();
- chDbgCheck(uartp != NULL, "uartStopSendI");
- chDbgAssert(uartp->state == UART_READY, "uartStopSendI(), #1", "not active");
-
- if (uartp->txstate == UART_TX_ACTIVE) {
- size_t n = uart_lld_stop_send(uartp);
- uartp->txstate = UART_TX_IDLE;
- return n;
- }
- return 0;
-}
-
-/**
- * @brief Starts a receive operation on the UART peripheral.
- * @note The buffers are organized as uint8_t arrays for data sizes below
- * or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] n number of data frames to send
- * @param[in] rxbuf the pointer to the receive buffer
- *
- * @api
- */
-void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf) {
-
- chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL),
- "uartStartReceive");
-
- chSysLock();
- chDbgAssert(uartp->state == UART_READY,
- "uartStartReceive(), #1", "is active");
- chDbgAssert(uartp->rxstate != UART_RX_ACTIVE,
- "uartStartReceive(), #2", "rx active");
-
- uart_lld_start_receive(uartp, n, rxbuf);
- uartp->rxstate = UART_RX_ACTIVE;
- chSysUnlock();
-}
-
-/**
- * @brief Starts a receive operation on the UART peripheral.
- * @note The buffers are organized as uint8_t arrays for data sizes below
- * or equal to 8 bits else it is organized as uint16_t arrays.
- * @note This function has to be invoked from a lock zone.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- * @param[in] n number of data frames to send
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @iclass
- */
-void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf) {
-
- chDbgCheckClassI();
- chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL),
- "uartStartReceiveI");
- chDbgAssert(uartp->state == UART_READY,
- "uartStartReceiveI(), #1", "is active");
- chDbgAssert(uartp->rxstate != UART_RX_ACTIVE,
- "uartStartReceiveI(), #2", "rx active");
-
- uart_lld_start_receive(uartp, n, rxbuf);
- uartp->rxstate = UART_RX_ACTIVE;
-}
-
-/**
- * @brief Stops any ongoing receive operation.
- * @note Stopping a receive operation also suppresses the receive callbacks.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @return The number of data frames not received by the
- * stopped receive operation.
- * @retval 0 There was no receive operation in progress.
- *
- * @api
- */
-size_t uartStopReceive(UARTDriver *uartp) {
- size_t n;
-
- chDbgCheck(uartp != NULL, "uartStopReceive");
-
- chSysLock();
- chDbgAssert(uartp->state == UART_READY,
- "uartStopReceive(), #1", "not active");
-
- if (uartp->rxstate == UART_RX_ACTIVE) {
- n = uart_lld_stop_receive(uartp);
- uartp->rxstate = UART_RX_IDLE;
- }
- else
- n = 0;
- chSysUnlock();
- return n;
-}
-
-/**
- * @brief Stops any ongoing receive operation.
- * @note Stopping a receive operation also suppresses the receive callbacks.
- * @note This function has to be invoked from a lock zone.
- *
- * @param[in] uartp pointer to the @p UARTDriver object
- *
- * @return The number of data frames not received by the
- * stopped receive operation.
- * @retval 0 There was no receive operation in progress.
- *
- * @iclass
- */
-size_t uartStopReceiveI(UARTDriver *uartp) {
-
- chDbgCheckClassI();
- chDbgCheck(uartp != NULL, "uartStopReceiveI");
- chDbgAssert(uartp->state == UART_READY,
- "uartStopReceiveI(), #1", "not active");
-
- if (uartp->rxstate == UART_RX_ACTIVE) {
- size_t n = uart_lld_stop_receive(uartp);
- uartp->rxstate = UART_RX_IDLE;
- return n;
- }
- return 0;
-}
-
-#endif /* HAL_USE_UART */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/usb.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/usb.c
deleted file mode 100644
index db1bf4341a..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/src/usb.c
+++ /dev/null
@@ -1,810 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file usb.c
- * @brief USB Driver code.
- *
- * @addtogroup USB
- * @{
- */
-
-#include
-
-#include "ch.h"
-#include "hal.h"
-#include "usb.h"
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-static const uint8_t zero_status[] = {0x00, 0x00};
-static const uint8_t active_status[] ={0x00, 0x00};
-static const uint8_t halted_status[] = {0x01, 0x00};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief SET ADDRESS transaction callback.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- */
-static void set_address(USBDriver *usbp) {
-
- usbp->address = usbp->setup[2];
- usb_lld_set_address(usbp);
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS);
- usbp->state = USB_SELECTED;
-}
-
-/**
- * @brief Standard requests handler.
- * @details This is the standard requests default handler, most standard
- * requests are handled here, the user can override the standard
- * handling using the @p requests_hook_cb hook in the
- * @p USBConfig structure.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @return The request handling exit code.
- * @retval FALSE Request not recognized by the handler or error.
- * @retval TRUE Request handled.
- */
-static bool_t default_handler(USBDriver *usbp) {
- const USBDescriptor *dp;
-
- /* Decoding the request.*/
- switch (((usbp->setup[0] & (USB_RTYPE_RECIPIENT_MASK |
- USB_RTYPE_TYPE_MASK)) |
- (usbp->setup[1] << 8))) {
- case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_STATUS << 8):
- /* Just returns the current status word.*/
- usbSetupTransfer(usbp, (uint8_t *)&usbp->status, 2, NULL);
- return TRUE;
- case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_CLEAR_FEATURE << 8):
- /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature
- number is handled as an error.*/
- if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) {
- usbp->status &= ~2;
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return TRUE;
- }
- return FALSE;
- case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_FEATURE << 8):
- /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature
- number is handled as an error.*/
- if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) {
- usbp->status |= 2;
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return TRUE;
- }
- return FALSE;
- case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_ADDRESS << 8):
- /* The SET_ADDRESS handling can be performed here or postponed after
- the status packed depending on the USB_SET_ADDRESS_MODE low
- driver setting.*/
-#if USB_SET_ADDRESS_MODE == USB_EARLY_SET_ADDRESS
- if ((usbp->setup[0] == USB_RTYPE_RECIPIENT_DEVICE) &&
- (usbp->setup[1] == USB_REQ_SET_ADDRESS))
- set_address(usbp);
- usbSetupTransfer(usbp, NULL, 0, NULL);
-#else
- usbSetupTransfer(usbp, NULL, 0, set_address);
-#endif
- return TRUE;
- case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_DESCRIPTOR << 8):
- /* Handling descriptor requests from the host.*/
- dp = usbp->config->get_descriptor_cb(
- usbp, usbp->setup[3], usbp->setup[2],
- usbFetchWord(&usbp->setup[4]));
- if (dp == NULL)
- return FALSE;
- usbSetupTransfer(usbp, (uint8_t *)dp->ud_string, dp->ud_size, NULL);
- return TRUE;
- case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_CONFIGURATION << 8):
- /* Returning the last selected configuration.*/
- usbSetupTransfer(usbp, &usbp->configuration, 1, NULL);
- return TRUE;
- case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_CONFIGURATION << 8):
- /* Handling configuration selection from the host.*/
- usbp->configuration = usbp->setup[2];
- if (usbp->configuration == 0)
- usbp->state = USB_SELECTED;
- else
- usbp->state = USB_ACTIVE;
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_CONFIGURED);
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return TRUE;
- case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_GET_STATUS << 8):
- case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_SYNCH_FRAME << 8):
- /* Just sending two zero bytes, the application can change the behavior
- using a hook..*/
- usbSetupTransfer(usbp, (uint8_t *)zero_status, 2, NULL);
- return TRUE;
- case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_GET_STATUS << 8):
- /* Sending the EP status.*/
- if (usbp->setup[4] & 0x80) {
- switch (usb_lld_get_status_in(usbp, usbp->setup[4] & 0x0F)) {
- case EP_STATUS_STALLED:
- usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL);
- return TRUE;
- case EP_STATUS_ACTIVE:
- usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL);
- return TRUE;
- default:
- return FALSE;
- }
- }
- else {
- switch (usb_lld_get_status_out(usbp, usbp->setup[4] & 0x0F)) {
- case EP_STATUS_STALLED:
- usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL);
- return TRUE;
- case EP_STATUS_ACTIVE:
- usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL);
- return TRUE;
- default:
- return FALSE;
- }
- }
- case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_CLEAR_FEATURE << 8):
- /* Only ENDPOINT_HALT is handled as feature.*/
- if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT)
- return FALSE;
- /* Clearing the EP status, not valid for EP0, it is ignored in that case.*/
- if ((usbp->setup[4] & 0x0F) > 0) {
- if (usbp->setup[4] & 0x80)
- usb_lld_clear_in(usbp, usbp->setup[4] & 0x0F);
- else
- usb_lld_clear_out(usbp, usbp->setup[4] & 0x0F);
- }
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return TRUE;
- case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_SET_FEATURE << 8):
- /* Only ENDPOINT_HALT is handled as feature.*/
- if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT)
- return FALSE;
- /* Stalling the EP, not valid for EP0, it is ignored in that case.*/
- if ((usbp->setup[4] & 0x0F) > 0) {
- if (usbp->setup[4] & 0x80)
- usb_lld_stall_in(usbp, usbp->setup[4] & 0x0F);
- else
- usb_lld_stall_out(usbp, usbp->setup[4] & 0x0F);
- }
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return TRUE;
- case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_DESCRIPTOR << 8):
- case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_CLEAR_FEATURE << 8):
- case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_SET_FEATURE << 8):
- case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_GET_INTERFACE << 8):
- case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_SET_INTERFACE << 8):
- /* All the above requests are not handled here, if you need them then
- use the hook mechanism and provide handling.*/
- default:
- return FALSE;
- }
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief USB Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void usbInit(void) {
-
- usb_lld_init();
-}
-
-/**
- * @brief Initializes the standard part of a @p USBDriver structure.
- *
- * @param[out] usbp pointer to the @p USBDriver object
- *
- * @init
- */
-void usbObjectInit(USBDriver *usbp) {
- unsigned i;
-
- usbp->state = USB_STOP;
- usbp->config = NULL;
- for (i = 0; i < USB_MAX_ENDPOINTS; i++) {
- usbp->in_params[i] = NULL;
- usbp->out_params[i] = NULL;
- }
- usbp->transmitting = 0;
- usbp->receiving = 0;
-}
-
-/**
- * @brief Configures and activates the USB peripheral.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] config pointer to the @p USBConfig object
- *
- * @api
- */
-void usbStart(USBDriver *usbp, const USBConfig *config) {
- unsigned i;
-
- chDbgCheck((usbp != NULL) && (config != NULL), "usbStart");
-
- chSysLock();
- chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY),
- "usbStart(), #1", "invalid state");
- usbp->config = config;
- for (i = 0; i <= USB_MAX_ENDPOINTS; i++)
- usbp->epc[i] = NULL;
- usb_lld_start(usbp);
- usbp->state = USB_READY;
- chSysUnlock();
-}
-
-/**
- * @brief Deactivates the USB peripheral.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @api
- */
-void usbStop(USBDriver *usbp) {
-
- chDbgCheck(usbp != NULL, "usbStop");
-
- chSysLock();
- chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY) ||
- (usbp->state == USB_SELECTED) || (usbp->state == USB_ACTIVE),
- "usbStop(), #1", "invalid state");
- usb_lld_stop(usbp);
- usbp->state = USB_STOP;
- chSysUnlock();
-}
-
-/**
- * @brief Enables an endpoint.
- * @details This function enables an endpoint, both IN and/or OUT directions
- * depending on the configuration structure.
- * @note This function must be invoked in response of a SET_CONFIGURATION
- * or SET_INTERFACE message.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @param[in] epcp the endpoint configuration
- *
- * @iclass
- */
-void usbInitEndpointI(USBDriver *usbp, usbep_t ep,
- const USBEndpointConfig *epcp) {
-
- chDbgCheckClassI();
- chDbgCheck((usbp != NULL) && (epcp != NULL), "usbInitEndpointI");
- chDbgAssert(usbp->state == USB_ACTIVE,
- "usbEnableEndpointI(), #1", "invalid state");
- chDbgAssert(usbp->epc[ep] == NULL,
- "usbEnableEndpointI(), #2", "already initialized");
-
- /* Logically enabling the endpoint in the USBDriver structure.*/
- if (epcp->in_state != NULL)
- memset(epcp->in_state, 0, sizeof(USBInEndpointState));
- if (epcp->out_state != NULL)
- memset(epcp->out_state, 0, sizeof(USBOutEndpointState));
-
- usbp->epc[ep] = epcp;
-
- /* Low level endpoint activation.*/
- usb_lld_init_endpoint(usbp, ep);
-}
-
-/**
- * @brief Disables all the active endpoints.
- * @details This function disables all the active endpoints except the
- * endpoint zero.
- * @note This function must be invoked in response of a SET_CONFIGURATION
- * message with configuration number zero.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @iclass
- */
-void usbDisableEndpointsI(USBDriver *usbp) {
- unsigned i;
-
- chDbgCheckClassI();
- chDbgCheck(usbp != NULL, "usbDisableEndpointsI");
- chDbgAssert(usbp->state == USB_SELECTED,
- "usbDisableEndpointsI(), #1", "invalid state");
-
- usbp->transmitting &= ~1;
- usbp->receiving &= ~1;
- for (i = 1; i <= USB_MAX_ENDPOINTS; i++)
- usbp->epc[i] = NULL;
-
- /* Low level endpoints deactivation.*/
- usb_lld_disable_endpoints(usbp);
-}
-
-/**
- * @brief Prepares for a receive transaction on an OUT endpoint.
- * @post The endpoint is ready for @p usbStartReceiveI().
- * @note This function can be called both in ISR and thread context.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @param[out] buf buffer where to copy the received data
- * @param[in] n transaction size
- *
- * @special
- */
-void usbPrepareReceive(USBDriver *usbp, usbep_t ep, uint8_t *buf, size_t n) {
- USBOutEndpointState *osp = usbp->epc[ep]->out_state;
-
- osp->rxqueued = FALSE;
- osp->mode.linear.rxbuf = buf;
- osp->rxsize = n;
- osp->rxcnt = 0;
-
- usb_lld_prepare_receive(usbp, ep);
-}
-
-/**
- * @brief Prepares for a transmit transaction on an IN endpoint.
- * @post The endpoint is ready for @p usbStartTransmitI().
- * @note This function can be called both in ISR and thread context.
- * @note The queue must contain at least the amount of data specified
- * as transaction size.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @param[in] buf buffer where to fetch the data to be transmitted
- * @param[in] n transaction size
- *
- * @special
- */
-void usbPrepareTransmit(USBDriver *usbp, usbep_t ep,
- const uint8_t *buf, size_t n) {
- USBInEndpointState *isp = usbp->epc[ep]->in_state;
-
- isp->txqueued = FALSE;
- isp->mode.linear.txbuf = buf;
- isp->txsize = n;
- isp->txcnt = 0;
-
- usb_lld_prepare_transmit(usbp, ep);
-}
-
-/**
- * @brief Prepares for a receive transaction on an OUT endpoint.
- * @post The endpoint is ready for @p usbStartReceiveI().
- * @note This function can be called both in ISR and thread context.
- * @note The queue must have enough free space to accommodate the
- * specified transaction size rounded to the next packet size
- * boundary. For example if the transaction size is 1 and the
- * packet size is 64 then the queue must have space for at least
- * 64 bytes.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @param[in] iqp input queue to be filled with incoming data
- * @param[in] n transaction size
- *
- * @special
- */
-void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep,
- InputQueue *iqp, size_t n) {
- USBOutEndpointState *osp = usbp->epc[ep]->out_state;
-
- osp->rxqueued = TRUE;
- osp->mode.queue.rxqueue = iqp;
- osp->rxsize = n;
- osp->rxcnt = 0;
-
- usb_lld_prepare_receive(usbp, ep);
-}
-
-/**
- * @brief Prepares for a transmit transaction on an IN endpoint.
- * @post The endpoint is ready for @p usbStartTransmitI().
- * @note This function can be called both in ISR and thread context.
- * @note The transmit transaction size is equal to the data contained
- * in the queue.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @param[in] oqp output queue to be fetched for outgoing data
- * @param[in] n transaction size
- *
- * @special
- */
-void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep,
- OutputQueue *oqp, size_t n) {
- USBInEndpointState *isp = usbp->epc[ep]->in_state;
-
- isp->txqueued = TRUE;
- isp->mode.queue.txqueue = oqp;
- isp->txsize = n;
- isp->txcnt = 0;
-
- usb_lld_prepare_transmit(usbp, ep);
-}
-
-/**
- * @brief Starts a receive transaction on an OUT endpoint.
- * @post The endpoint callback is invoked when the transfer has been
- * completed.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @return The operation status.
- * @retval FALSE Operation started successfully.
- * @retval TRUE Endpoint busy, operation not started.
- *
- * @iclass
- */
-bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep) {
-
- chDbgCheckClassI();
- chDbgCheck(usbp != NULL, "usbStartReceiveI");
-
- if (usbGetReceiveStatusI(usbp, ep))
- return TRUE;
-
- usbp->receiving |= (1 << ep);
- usb_lld_start_out(usbp, ep);
- return FALSE;
-}
-
-/**
- * @brief Starts a transmit transaction on an IN endpoint.
- * @post The endpoint callback is invoked when the transfer has been
- * completed.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @return The operation status.
- * @retval FALSE Operation started successfully.
- * @retval TRUE Endpoint busy, operation not started.
- *
- * @iclass
- */
-bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep) {
-
- chDbgCheckClassI();
- chDbgCheck(usbp != NULL, "usbStartTransmitI");
-
- if (usbGetTransmitStatusI(usbp, ep))
- return TRUE;
-
- usbp->transmitting |= (1 << ep);
- usb_lld_start_in(usbp, ep);
- return FALSE;
-}
-
-/**
- * @brief Stalls an OUT endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @return The operation status.
- * @retval FALSE Endpoint stalled.
- * @retval TRUE Endpoint busy, not stalled.
- *
- * @iclass
- */
-bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep) {
-
- chDbgCheckClassI();
- chDbgCheck(usbp != NULL, "usbStallReceiveI");
-
- if (usbGetReceiveStatusI(usbp, ep))
- return TRUE;
-
- usb_lld_stall_out(usbp, ep);
- return FALSE;
-}
-
-/**
- * @brief Stalls an IN endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @return The operation status.
- * @retval FALSE Endpoint stalled.
- * @retval TRUE Endpoint busy, not stalled.
- *
- * @iclass
- */
-bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep) {
-
- chDbgCheckClassI();
- chDbgCheck(usbp != NULL, "usbStallTransmitI");
-
- if (usbGetTransmitStatusI(usbp, ep))
- return TRUE;
-
- usb_lld_stall_in(usbp, ep);
- return FALSE;
-}
-
-/**
- * @brief USB reset routine.
- * @details This function must be invoked when an USB bus reset condition is
- * detected.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void _usb_reset(USBDriver *usbp) {
- unsigned i;
-
- usbp->state = USB_READY;
- usbp->status = 0;
- usbp->address = 0;
- usbp->configuration = 0;
- usbp->transmitting = 0;
- usbp->receiving = 0;
-
- /* Invalidates all endpoints into the USBDriver structure.*/
- for (i = 0; i <= USB_MAX_ENDPOINTS; i++)
- usbp->epc[i] = NULL;
-
- /* EP0 state machine initialization.*/
- usbp->ep0state = USB_EP0_WAITING_SETUP;
-
- /* Low level reset.*/
- usb_lld_reset(usbp);
-}
-
-/**
- * @brief Default EP0 SETUP callback.
- * @details This function is used by the low level driver as default handler
- * for EP0 SETUP events.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number, always zero
- *
- * @notapi
- */
-void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
- size_t max;
-
- usbp->ep0state = USB_EP0_WAITING_SETUP;
- usbReadSetup(usbp, ep, usbp->setup);
-
- /* First verify if the application has an handler installed for this
- request.*/
- if (!(usbp->config->requests_hook_cb) ||
- !(usbp->config->requests_hook_cb(usbp))) {
- /* Invoking the default handler, if this fails then stalls the
- endpoint zero as error.*/
- if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) != USB_RTYPE_TYPE_STD) ||
- !default_handler(usbp)) {
- /* Error response, the state machine goes into an error state, the low
- level layer will have to reset it to USB_EP0_WAITING_SETUP after
- receiving a SETUP packet.*/
- usb_lld_stall_in(usbp, 0);
- usb_lld_stall_out(usbp, 0);
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED);
- usbp->ep0state = USB_EP0_ERROR;
- return;
- }
- }
-#if (USB_SET_ADDRESS_ACK_HANDLING == USB_SET_ADDRESS_ACK_HW)
- if (usbp->setup[1] == USB_REQ_SET_ADDRESS) {
- /* Zero-length packet sent by hardware */
- return;
- }
-#endif
- /* Transfer preparation. The request handler must have populated
- correctly the fields ep0next, ep0n and ep0endcb using the macro
- usbSetupTransfer().*/
- max = usbFetchWord(&usbp->setup[6]);
- /* The transfer size cannot exceed the specified amount.*/
- if (usbp->ep0n > max)
- usbp->ep0n = max;
- if ((usbp->setup[0] & USB_RTYPE_DIR_MASK) == USB_RTYPE_DIR_DEV2HOST) {
- /* IN phase.*/
- if (usbp->ep0n > 0) {
- /* Starts the transmit phase.*/
- usbp->ep0state = USB_EP0_TX;
- usbPrepareTransmit(usbp, 0, usbp->ep0next, usbp->ep0n);
- chSysLockFromIsr();
- usbStartTransmitI(usbp, 0);
- chSysUnlockFromIsr();
- }
- else {
- /* No transmission phase, directly receiving the zero sized status
- packet.*/
- usbp->ep0state = USB_EP0_WAITING_STS;
-#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
- usbPrepareReceive(usbp, 0, NULL, 0);
- chSysLockFromIsr();
- usbStartReceiveI(usbp, 0);
- chSysUnlockFromIsr();
-#else
- usb_lld_end_setup(usbp, ep);
-#endif
- }
- }
- else {
- /* OUT phase.*/
- if (usbp->ep0n > 0) {
- /* Starts the receive phase.*/
- usbp->ep0state = USB_EP0_RX;
- usbPrepareReceive(usbp, 0, usbp->ep0next, usbp->ep0n);
- chSysLockFromIsr();
- usbStartReceiveI(usbp, 0);
- chSysUnlockFromIsr();
- }
- else {
- /* No receive phase, directly sending the zero sized status
- packet.*/
- usbp->ep0state = USB_EP0_SENDING_STS;
-#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
- usbPrepareTransmit(usbp, 0, NULL, 0);
- chSysLockFromIsr();
- usbStartTransmitI(usbp, 0);
- chSysUnlockFromIsr();
-#else
- usb_lld_end_setup(usbp, ep);
-#endif
- }
- }
-}
-
-/**
- * @brief Default EP0 IN callback.
- * @details This function is used by the low level driver as default handler
- * for EP0 IN events.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number, always zero
- *
- * @notapi
- */
-void _usb_ep0in(USBDriver *usbp, usbep_t ep) {
- size_t max;
-
- (void)ep;
- switch (usbp->ep0state) {
- case USB_EP0_TX:
- max = usbFetchWord(&usbp->setup[6]);
- /* If the transmitted size is less than the requested size and it is a
- multiple of the maximum packet size then a zero size packet must be
- transmitted.*/
- if ((usbp->ep0n < max) && ((usbp->ep0n % usbp->epc[0]->in_maxsize) == 0)) {
- usbPrepareTransmit(usbp, 0, NULL, 0);
- chSysLockFromIsr();
- usbStartTransmitI(usbp, 0);
- chSysUnlockFromIsr();
- usbp->ep0state = USB_EP0_WAITING_TX0;
- return;
- }
- /* Falls into, it is intentional.*/
- case USB_EP0_WAITING_TX0:
- /* Transmit phase over, receiving the zero sized status packet.*/
- usbp->ep0state = USB_EP0_WAITING_STS;
-#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
- usbPrepareReceive(usbp, 0, NULL, 0);
- chSysLockFromIsr();
- usbStartReceiveI(usbp, 0);
- chSysUnlockFromIsr();
-#else
- usb_lld_end_setup(usbp, ep);
-#endif
- return;
- case USB_EP0_SENDING_STS:
- /* Status packet sent, invoking the callback if defined.*/
- if (usbp->ep0endcb != NULL)
- usbp->ep0endcb(usbp);
- usbp->ep0state = USB_EP0_WAITING_SETUP;
- return;
- default:
- ;
- }
- /* Error response, the state machine goes into an error state, the low
- level layer will have to reset it to USB_EP0_WAITING_SETUP after
- receiving a SETUP packet.*/
- usb_lld_stall_in(usbp, 0);
- usb_lld_stall_out(usbp, 0);
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED);
- usbp->ep0state = USB_EP0_ERROR;
-}
-
-/**
- * @brief Default EP0 OUT callback.
- * @details This function is used by the low level driver as default handler
- * for EP0 OUT events.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number, always zero
- *
- * @notapi
- */
-void _usb_ep0out(USBDriver *usbp, usbep_t ep) {
-
- (void)ep;
- switch (usbp->ep0state) {
- case USB_EP0_RX:
- /* Receive phase over, sending the zero sized status packet.*/
- usbp->ep0state = USB_EP0_SENDING_STS;
-#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
- usbPrepareTransmit(usbp, 0, NULL, 0);
- chSysLockFromIsr();
- usbStartTransmitI(usbp, 0);
- chSysUnlockFromIsr();
-#else
- usb_lld_end_setup(usbp, ep);
-#endif
- return;
- case USB_EP0_WAITING_STS:
- /* Status packet received, it must be zero sized, invoking the callback
- if defined.*/
-#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
- if (usbGetReceiveTransactionSizeI(usbp, 0) != 0)
- break;
-#endif
- if (usbp->ep0endcb != NULL)
- usbp->ep0endcb(usbp);
- usbp->ep0state = USB_EP0_WAITING_SETUP;
- return;
- default:
- ;
- }
- /* Error response, the state machine goes into an error state, the low
- level layer will have to reset it to USB_EP0_WAITING_SETUP after
- receiving a SETUP packet.*/
- usb_lld_stall_in(usbp, 0);
- usb_lld_stall_out(usbp, 0);
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED);
- usbp->ep0state = USB_EP0_ERROR;
-}
-
-#endif /* HAL_USE_USB */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/platforms.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.c
similarity index 60%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/platforms.dox
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.c
index 8351192068..05668b4c75 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/platforms.dox
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,11 +14,11 @@
limitations under the License.
*/
+#include "hal.h"
+
/**
- * @defgroup platforms Platforms
- * @brief Supported platforms.
- * @details The implementation of the device drivers can be slightly different
- * on the various platforms because architectural constrains. This section
- * describes the implementation of the various device drivers on the various
- * supported platforms.
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
*/
+void boardInit(void) {
+}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.h
new file mode 100644
index 0000000000..4f2ba2a79f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.h
@@ -0,0 +1,40 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*
+ * Setup for a generic board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_GENERIC
+#define BOARD_NAME "Generic Board"
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.mk
new file mode 100644
index 0000000000..27724a903b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/board/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/templates/board/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/templates/board
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/adc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_adc_lld.c
similarity index 87%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/adc_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_adc_lld.c
index 3b4b2851bd..5e9fda89b3 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/adc_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_adc_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/adc_lld.c
- * @brief ADC Driver subsystem low level driver source template.
+ * @file hal_adc_lld.c
+ * @brief PLATFORM ADC subsystem low level driver source.
*
* @addtogroup ADC
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_ADC || defined(__DOXYGEN__)
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief ADC1 driver identifier.
*/
-#if PLATFORM_ADC_USE_ADC1 || defined(__DOXYGEN__)
+#if (PLATFORM_ADC_USE_ADC1 == TRUE) || defined(__DOXYGEN__)
ADCDriver ADCD1;
#endif
@@ -65,10 +64,10 @@ ADCDriver ADCD1;
*/
void adc_lld_init(void) {
-#if PLATFORM_ADC_USE_ADC1
+#if PLATFORM_ADC_USE_ADC1 == TRUE
/* Driver initialization.*/
adcObjectInit(&ADCD1);
-#endif /* PLATFORM_ADC_USE_ADC1 */
+#endif
}
/**
@@ -82,11 +81,11 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_ADC_USE_ADC1
+#if PLATFORM_ADC_USE_ADC1 == TRUE
if (&ADCD1 == adcp) {
}
-#endif /* PLATFORM_ADC_USE_ADC1 */
+#endif
}
/* Configures the peripheral.*/
@@ -105,11 +104,11 @@ void adc_lld_stop(ADCDriver *adcp) {
/* Resets the peripheral.*/
/* Disables the peripheral.*/
-#if PLATFORM_ADC_USE_ADC1
+#if PLATFORM_ADC_USE_ADC1 == TRUE
if (&ADCD1 == adcp) {
}
-#endif /* PLATFORM_ADC_USE_ADC1 */
+#endif
}
}
@@ -137,6 +136,6 @@ void adc_lld_stop_conversion(ADCDriver *adcp) {
(void)adcp;
}
-#endif /* HAL_USE_ADC */
+#endif /* HAL_USE_ADC == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/adc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_adc_lld.h
similarity index 79%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/adc_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_adc_lld.h
index 7027d441d2..f587fb4bb8 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/adc_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_adc_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/adc_lld.h
- * @brief ADC Driver subsystem low level driver header template.
+ * @file hal_adc_lld.h
+ * @brief PLATFORM ADC subsystem low level driver header.
*
* @addtogroup ADC
* @{
*/
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
-#if HAL_USE_ADC || defined(__DOXYGEN__)
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -36,7 +36,7 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
@@ -45,7 +45,7 @@
* @note The default is @p FALSE.
*/
#if !defined(PLATFORM_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define PLATFORM_ADC_USE_ADC1 FALSE
+#define PLATFORM_ADC_USE_ADC1 FALSE
#endif
/** @} */
@@ -74,7 +74,8 @@ typedef uint16_t adc_channels_num_t;
*/
typedef enum {
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
- ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
+ ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
+ ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
} adcerror_t;
/**
@@ -105,14 +106,15 @@ typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
* @brief Conversion group configuration structure.
* @details This implementation-dependent structure describes a conversion
* operation.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
+ * @note The use of this configuration structure requires knowledge of
+ * PLATFORM ADC cell registers interface, please refer to the PLATFORM
+ * reference manual for details.
*/
typedef struct {
/**
* @brief Enables the circular buffer mode for the group.
*/
- bool_t circular;
+ bool circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
@@ -141,41 +143,37 @@ typedef struct {
*/
struct ADCDriver {
/**
- * @brief Driver state.
+ * @brief Driver state.
*/
adcstate_t state;
/**
- * @brief Current configuration data.
+ * @brief Current configuration data.
*/
const ADCConfig *config;
/**
- * @brief Current samples buffer pointer or @p NULL.
+ * @brief Current samples buffer pointer or @p NULL.
*/
adcsample_t *samples;
/**
- * @brief Current samples buffer depth or @p 0.
+ * @brief Current samples buffer depth or @p 0.
*/
size_t depth;
/**
- * @brief Current conversion group pointer or @p NULL.
+ * @brief Current conversion group pointer or @p NULL.
*/
const ADCConversionGroup *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
/**
- * @brief Waiting thread.
+ * @brief Waiting thread.
*/
- Thread *thread;
+ thread_reference_t thread;
#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
+#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
/**
- * @brief Mutex protecting the peripheral.
+ * @brief Mutex protecting the peripheral.
*/
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
+ mutex_t mutex;
#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS)
ADC_DRIVER_EXT_FIELDS
#endif
@@ -190,7 +188,7 @@ struct ADCDriver {
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+#if (PLATFORM_ADC_USE_ADC1 == TRUE) && !defined(__DOXYGEN__)
extern ADCDriver ADCD1;
#endif
@@ -206,8 +204,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_ADC */
+#endif /* HAL_USE_ADC == TRUE */
-#endif /* _ADC_LLD_H_ */
+#endif /* HAL_ADC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/can_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_can_lld.c
similarity index 86%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/can_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_can_lld.c
index 4e49791dd7..2f9261a1bf 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/can_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_can_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/can_lld.c
- * @brief CAN Driver subsystem low level driver source template.
+ * @file hal_can_lld.c
+ * @brief PLATFORM CAN subsystem low level driver source.
*
* @addtogroup CAN
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_CAN || defined(__DOXYGEN__)
+#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief CAN1 driver identifier.
*/
-#if PLATFORM_CAN_USE_CAN1 || defined(__DOXYGEN__)
+#if (PLATFORM_CAN_USE_CAN1 == TRUE) || defined(__DOXYGEN__)
CANDriver CAND1;
#endif
@@ -65,10 +64,10 @@ CANDriver CAND1;
*/
void can_lld_init(void) {
-#if PLATFORM_CAN_USE_CAN1
+#if PLATFORM_CAN_USE_CAN1 == TRUE
/* Driver initialization.*/
canObjectInit(&CAND1);
-#endif /* PLATFORM_CAN_USE_CAN1 */
+#endif
}
/**
@@ -82,11 +81,11 @@ void can_lld_start(CANDriver *canp) {
if (canp->state == CAN_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_CAN_USE_CAN1
+#if PLATFORM_CAN_USE_CAN1 == TRUE
if (&CAND1 == canp) {
}
-#endif /* PLATFORM_CAN_USE_CAN1 */
+#endif
}
/* Configures the peripheral.*/
@@ -105,11 +104,11 @@ void can_lld_stop(CANDriver *canp) {
/* Resets the peripheral.*/
/* Disables the peripheral.*/
-#if PLATFORM_CAN_USE_CAN1
+#if PLATFORM_CAN_USE_CAN1 == TRUE
if (&CAND1 == canp) {
}
-#endif /* PLATFORM_CAN_USE_CAN1 */
+#endif
}
}
@@ -125,21 +124,21 @@ void can_lld_stop(CANDriver *canp) {
*
* @notapi
*/
-bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
+bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
(void)canp;
switch (mailbox) {
case CAN_ANY_MAILBOX:
- return FALSE;
+ return false;
case 1:
- return FALSE;
+ return false;
case 2:
- return FALSE;
+ return false;
case 3:
- return FALSE;
+ return false;
default:
- return FALSE;
+ return false;
}
}
@@ -174,20 +173,20 @@ void can_lld_transmit(CANDriver *canp,
*
* @notapi
*/
-bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
+bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
(void)canp;
(void)mailbox;
switch (mailbox) {
case CAN_ANY_MAILBOX:
- return FALSE;
+ return false;
case 1:
- return FALSE;
+ return false;
case 2:
- return FALSE;
+ return false;
default:
- return FALSE;
+ return false;
}
}
@@ -210,7 +209,7 @@ void can_lld_receive(CANDriver *canp,
}
-#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
+#if (CAN_USE_SLEEP_MODE == TRUE) || defined(__DOXYGEN__)
/**
* @brief Enters the sleep mode.
*
@@ -236,8 +235,8 @@ void can_lld_wakeup(CANDriver *canp) {
(void)canp;
}
-#endif /* CAN_USE_SLEEP_MODE */
+#endif /* CAN_USE_SLEEP_MOD == TRUEE */
-#endif /* HAL_USE_CAN */
+#endif /* HAL_USE_CAN == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/can_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_can_lld.h
similarity index 65%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/can_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_can_lld.h
index cffdf03129..c01d9ae43a 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/can_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_can_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,52 +15,47 @@
*/
/**
- * @file templates/can_lld.h
- * @brief CAN Driver subsystem low level driver header template.
+ * @file hal_can_lld.h
+ * @brief PLATFORM CAN subsystem low level driver header.
*
* @addtogroup CAN
* @{
*/
-#ifndef _CAN_LLD_H_
-#define _CAN_LLD_H_
+#ifndef HAL_CAN_LLD_H
+#define HAL_CAN_LLD_H
-#if HAL_USE_CAN || defined(__DOXYGEN__)
+#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
- * @brief This switch defines whether the driver implementation supports
- * a low power switch mode with automatic an wakeup feature.
+ * @brief Number of transmit mailboxes.
*/
-#define CAN_SUPPORTS_SLEEP TRUE
+#define CAN_TX_MAILBOXES 1
/**
- * @brief This implementation supports three transmit mailboxes.
+ * @brief Number of receive mailboxes.
*/
-#define CAN_TX_MAILBOXES 3
-
-/**
- * @brief This implementation supports two receive mailboxes.
- */
-#define CAN_RX_MAILBOXES 2
+#define CAN_RX_MAILBOXES 1
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
* @brief CAN1 driver enable switch.
* @details If set to @p TRUE the support for CAN1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_CAN_USE_CAN1) || defined(__DOXYGEN__)
-#define PLATFORM_CAN_USE_CAN1 FALSE
+#define PLATFORM_CAN_USE_CAN1 FALSE
#endif
/** @} */
@@ -68,10 +63,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
-#error "CAN sleep mode not supported in this architecture"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -87,19 +78,16 @@ typedef uint32_t canmbx_t;
* machine data endianness, it can be still useful for a quick filling.
*/
typedef struct {
- struct {
- uint8_t DLC:4; /**< @brief Data length. */
- uint8_t RTR:1; /**< @brief Frame type. */
- uint8_t IDE:1; /**< @brief Identifier type. */
- };
+ /*lint -save -e46 [6.1] Standard types are fine too.*/
+ uint8_t DLC:4; /**< @brief Data length. */
+ uint8_t RTR:1; /**< @brief Frame type. */
+ uint8_t IDE:1; /**< @brief Identifier type. */
union {
- struct {
- uint32_t SID:11; /**< @brief Standard identifier.*/
- };
- struct {
- uint32_t EID:29; /**< @brief Extended identifier.*/
- };
+ uint32_t SID:11; /**< @brief Standard identifier.*/
+ uint32_t EID:29; /**< @brief Extended identifier.*/
+ uint32_t _align1;
};
+ /*lint -restore*/
union {
uint8_t data8[8]; /**< @brief Frame data. */
uint16_t data16[4]; /**< @brief Frame data. */
@@ -113,19 +101,18 @@ typedef struct {
* machine data endianness, it can be still useful for a quick filling.
*/
typedef struct {
- struct {
- uint8_t DLC:4; /**< @brief Data length. */
- uint8_t RTR:1; /**< @brief Frame type. */
- uint8_t IDE:1; /**< @brief Identifier type. */
- };
+ /*lint -save -e46 [6.1] Standard types are fine too.*/
+ uint8_t FMI; /**< @brief Filter id. */
+ uint16_t TIME; /**< @brief Time stamp. */
+ uint8_t DLC:4; /**< @brief Data length. */
+ uint8_t RTR:1; /**< @brief Frame type. */
+ uint8_t IDE:1; /**< @brief Identifier type. */
union {
- struct {
- uint32_t SID:11; /**< @brief Standard identifier.*/
- };
- struct {
- uint32_t EID:29; /**< @brief Extended identifier.*/
- };
+ uint32_t SID:11; /**< @brief Standard identifier.*/
+ uint32_t EID:29; /**< @brief Extended identifier.*/
+ uint32_t _align1;
};
+ /*lint -restore*/
union {
uint8_t data8[8]; /**< @brief Frame data. */
uint16_t data16[4]; /**< @brief Frame data. */
@@ -133,23 +120,11 @@ typedef struct {
};
} CANRxFrame;
-/**
- * @brief CAN filter.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- * @note It could not be present on some architectures.
- */
-typedef struct {
- uint32_t dummy;
-} CANFilter;
-
/**
* @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- * @note It could be empty on some architectures.
*/
typedef struct {
+ /* End of the mandatory fields.*/
uint32_t dummy;
} CANConfig;
@@ -166,13 +141,13 @@ typedef struct {
*/
const CANConfig *config;
/**
- * @brief Transmission queue semaphore.
+ * @brief Transmission threads queue.
*/
- Semaphore txsem;
+ threads_queue_t txqueue;
/**
- * @brief Receive queue semaphore.
+ * @brief Receive threads queue.
*/
- Semaphore rxsem;
+ threads_queue_t rxqueue;
/**
* @brief One or more frames become available.
* @note After broadcasting this event it will not be broadcasted again
@@ -185,30 +160,30 @@ typedef struct {
* @note The flags associated to the listeners will indicate which
* receive mailboxes become non-empty.
*/
- EventSource rxfull_event;
+ event_source_t rxfull_event;
/**
* @brief One or more transmission mailbox become available.
* @note The flags associated to the listeners will indicate which
* transmit mailboxes become empty.
*
*/
- EventSource txempty_event;
+ event_source_t txempty_event;
/**
* @brief A CAN bus error happened.
* @note The flags associated to the listeners will indicate the
* error(s) that have occurred.
*/
- EventSource error_event;
-#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
+ event_source_t error_event;
+#if (CAN_USE_SLEEP_MODE == TRUE) || defined (__DOXYGEN__)
/**
* @brief Entering sleep state event.
*/
- EventSource sleep_event;
+ event_source_t sleep_event;
/**
* @brief Exiting sleep state event.
*/
- EventSource wakeup_event;
-#endif /* CAN_USE_SLEEP_MODE */
+ event_source_t wakeup_event;
+#endif
/* End of the mandatory fields.*/
} CANDriver;
@@ -220,7 +195,7 @@ typedef struct {
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_CAN_USE_CAN1 && !defined(__DOXYGEN__)
+#if (PLATFORM_CAN_USE_CAN1 == TRUE) && !defined(__DOXYGEN__)
extern CANDriver CAND1;
#endif
@@ -230,26 +205,24 @@ extern "C" {
void can_lld_init(void);
void can_lld_start(CANDriver *canp);
void can_lld_stop(CANDriver *canp);
- bool_t can_lld_is_tx_empty(CANDriver *canp,
- canmbx_t mailbox);
+ bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox);
void can_lld_transmit(CANDriver *canp,
canmbx_t mailbox,
- const CANTxFrame *crfp);
- bool_t can_lld_is_rx_nonempty(CANDriver *canp,
- canmbx_t mailbox);
+ const CANTxFrame *ctfp);
+ bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox);
void can_lld_receive(CANDriver *canp,
canmbx_t mailbox,
- CANRxFrame *ctfp);
-#if CAN_USE_SLEEP_MODE
+ CANRxFrame *crfp);
+#if CAN_USE_SLEEP_MODE == TRUE
void can_lld_sleep(CANDriver *canp);
void can_lld_wakeup(CANDriver *canp);
-#endif /* CAN_USE_SLEEP_MODE */
+#endif
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_CAN */
+#endif /* HAL_USE_CAN == TRUE */
-#endif /* _CAN_LLD_H_ */
+#endif /* HAL_CAN_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_dac_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_dac_lld.c
new file mode 100644
index 0000000000..6a80576cc9
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_dac_lld.c
@@ -0,0 +1,170 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_dac_lld.c
+ * @brief PLATFORM DAC subsystem low level driver source.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief DAC1 driver identifier.*/
+#if (PLATFORM_DAC_USE_DAC1 == TRUE) || defined(__DOXYGEN__)
+DACDriver DACD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level DAC driver initialization.
+ *
+ * @notapi
+ */
+void dac_lld_init(void) {
+
+#if PLATFORM_DAC_USE_DAC1 == TRUE
+ dacObjectInit(&DACD1);
+#endif
+}
+
+/**
+ * @brief Configures and activates the DAC peripheral.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_start(DACDriver *dacp) {
+
+ /* If the driver is in DAC_STOP state then a full initialization is
+ required.*/
+ if (dacp->state == DAC_STOP) {
+ /* Enabling the clock source.*/
+#if PLATFORM_DAC_USE_DAC1 == TRUE
+ if (&DACD1 == dacp) {
+
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Deactivates the DAC peripheral.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_stop(DACDriver *dacp) {
+
+ /* If in ready state then disables the DAC clock.*/
+ if (dacp->state == DAC_READY) {
+
+ /* Disabling DAC.*/
+ dacp->params->dac->CR &= dacp->params->regmask;
+
+#if PLATFORM_DAC_USE_DAC1 == TRUE
+ if (&DACD1 == dacp) {
+
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Outputs a value directly on a DAC channel.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ * @param[in] channel DAC channel number
+ * @param[in] sample value to be output
+ *
+ * @api
+ */
+void dac_lld_put_channel(DACDriver *dacp,
+ dacchannel_t channel,
+ dacsample_t sample) {
+
+ (void)dacp;
+ (void)channel;
+ (void)sample;
+}
+
+/**
+ * @brief Starts a DAC conversion.
+ * @details Starts an asynchronous conversion operation.
+ * @note In @p DAC_DHRM_8BIT_RIGHT mode the parameters passed to the
+ * callback are wrong because two samples are packed in a single
+ * dacsample_t element. This will not be corrected, do not rely
+ * on those parameters.
+ * @note In @p DAC_DHRM_8BIT_RIGHT_DUAL mode two samples are treated
+ * as a single 16 bits sample and packed into a single dacsample_t
+ * element. The num_channels must be set to one in the group
+ * conversion configuration structure.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_start_conversion(DACDriver *dacp) {
+
+ (void)dacp;
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ * @details This function stops the currently ongoing conversion and returns
+ * the driver in the @p DAC_READY state. If there was no conversion
+ * being processed then the function does nothing.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object
+ *
+ * @iclass
+ */
+void dac_lld_stop_conversion(DACDriver *dacp) {
+
+ (void)dacp;
+}
+
+#endif /* HAL_USE_DAC == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_dac_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_dac_lld.h
new file mode 100644
index 0000000000..98479ed84c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_dac_lld.h
@@ -0,0 +1,209 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_dac_lld.h
+ * @brief PLATFORM DAC subsystem low level driver header.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#ifndef HAL_DAC_LLD_H
+#define HAL_DAC_LLD_H
+
+#if HAL_USE_DAC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum number of DAC channels per unit.
+ */
+#define DAC_MAX_CHANNELS 2
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief DAC1 CH1 driver enable switch.
+ * @details If set to @p TRUE the support for DAC1 channel 1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(PLATFORM_DAC_USE_DAC1) || defined(__DOXYGEN__)
+#define PLATFORM_DAC_USE_DAC1 FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a DAC channel index.
+ */
+typedef uint32_t dacchannel_t;
+
+/**
+ * @brief Type of a structure representing an DAC driver.
+ */
+typedef struct DACDriver DACDriver;
+
+/**
+ * @brief Type representing a DAC sample.
+ */
+typedef uint16_t dacsample_t;
+
+/**
+ * @brief Possible DAC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ DAC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ DAC_ERR_UNDERFLOW = 1 /**< DAC overflow condition. */
+} dacerror_t;
+
+/**
+ * @brief DAC notification callback type.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object triggering the
+ * @param[in] buffer pointer to the next semi-buffer to be filled
+ * @param[in] n number of buffer rows available starting from @p buffer
+ * callback
+ */
+typedef void (*daccallback_t)(DACDriver *dacp, dacsample_t *buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*dacerrorcallback_t)(DACDriver *dacp, dacerror_t err);
+
+/**
+ * @brief DAC Conversion group structure.
+ */
+typedef struct {
+ /**
+ * @brief Number of DAC channels.
+ */
+ uint32_t num_channels;
+ /**
+ * @brief Operation complete callback or @p NULL.
+ */
+ daccallback_t end_cb;
+ /**
+ * @brief Error handling callback or @p NULL.
+ */
+ dacerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+} DACConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /* End of the mandatory fields.*/
+ uint32_t dummy;
+} DACConfig;
+
+/**
+ * @brief Structure representing a DAC driver.
+ */
+struct DACDriver {
+ /**
+ * @brief Driver state.
+ */
+ dacstate_t state;
+ /**
+ * @brief Conversion group.
+ */
+ const DACConversionGroup *grpp;
+ /**
+ * @brief Samples buffer pointer.
+ */
+ dacsample_t *samples;
+ /**
+ * @brief Samples buffer size.
+ */
+ uint16_t depth;
+ /**
+ * @brief Current configuration data.
+ */
+ const DACConfig *config;
+#if DAC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif /* DAC_USE_WAIT */
+#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#endif /* DAC_USE_MUTUAL_EXCLUSION */
+#if defined(DAC_DRIVER_EXT_FIELDS)
+ DAC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if PLATFORM_DAC_USE_DAC1 && !defined(__DOXYGEN__)
+extern DACDriver DACD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void dac_lld_init(void);
+ void dac_lld_start(DACDriver *dacp);
+ void dac_lld_stop(DACDriver *dacp);
+ void dac_lld_put_channel(DACDriver *dacp,
+ dacchannel_t channel,
+ dacsample_t sample);
+ void dac_lld_start_conversion(DACDriver *dacp);
+ void dac_lld_stop_conversion(DACDriver *dacp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_DAC */
+
+#endif /* HAL_DAC_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/ext_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_ext_lld.c
similarity index 88%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/ext_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_ext_lld.c
index 106c11c5d2..d9ad5c5ef1 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/ext_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_ext_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/ext_lld.c
- * @brief EXT Driver subsystem low level driver source template.
+ * @file hal_ext_lld.c
+ * @brief PLATFORM EXT subsystem low level driver source.
*
* @addtogroup EXT
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_EXT || defined(__DOXYGEN__)
+#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief EXT1 driver identifier.
*/
-#if PLATFORM_EXT_USE_EXT1 || defined(__DOXYGEN__)
+#if (PLATFORM_EXT_USE_EXT1 == TRUE) || defined(__DOXYGEN__)
EXTDriver EXTD1;
#endif
@@ -65,10 +64,10 @@ EXTDriver EXTD1;
*/
void ext_lld_init(void) {
-#if PLATFORM_EXT_USE_EXT1
+#if PLATFORM_EXT_USE_EXT1 == TRUE
/* Driver initialization.*/
extObjectInit(&EXTD1);
-#endif /* PLATFORM_EXT_USE_EXT1 */
+#endif
}
/**
@@ -82,11 +81,11 @@ void ext_lld_start(EXTDriver *extp) {
if (extp->state == EXT_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_EXT_USE_EXT1
+#if PLATFORM_EXT_USE_EXT1 == TRUE
if (&EXTD1 == extp) {
}
-#endif /* PLATFORM_EXT_USE_EXT1 */
+#endif
}
/* Configures the peripheral.*/
@@ -105,11 +104,11 @@ void ext_lld_stop(EXTDriver *extp) {
/* Resets the peripheral.*/
/* Disables the peripheral.*/
-#if PLATFORM_EXT_USE_EXT1
+#if PLATFORM_EXT_USE_EXT1 == TRUE
if (&EXTD1 == extp) {
}
-#endif /* PLATFORM_EXT_USE_EXT1 */
+#endif
}
}
@@ -143,6 +142,6 @@ void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
}
-#endif /* HAL_USE_EXT */
+#endif /* HAL_USE_EXT == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/ext_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_ext_lld.h
similarity index 90%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/ext_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_ext_lld.h
index b03c770a78..bdfdbe29fe 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/ext_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_ext_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/ext_lld.h
- * @brief EXT Driver subsystem low level driver header template.
+ * @file hal_ext_lld.h
+ * @brief PLATFORM EXT subsystem low level driver header.
*
* @addtogroup EXT
* @{
*/
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
+#ifndef HAL_EXT_LLD_H
+#define HAL_EXT_LLD_H
-#if HAL_USE_EXT || defined(__DOXYGEN__)
+#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -41,12 +41,13 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
* @brief EXT driver enable switch.
* @details If set to @p TRUE the support for EXT1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_EXT_USE_EXT1) || defined(__DOXYGEN__)
#define PLATFORM_EXT_USE_EXT1 FALSE
@@ -126,7 +127,7 @@ struct EXTDriver {
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_EXT_USE_EXT1 && !defined(__DOXYGEN__)
+#if (PLATFORM_EXT_USE_EXT1 == TRUE) && !defined(__DOXYGEN__)
extern EXTDriver EXTD1;
#endif
@@ -142,8 +143,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_EXT */
+#endif /* HAL_USE_EXT == TRUE */
-#endif /* _EXT_LLD_H_ */
+#endif /* HAL_EXT_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/gpt_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_gpt_lld.c
similarity index 89%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/gpt_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_gpt_lld.c
index d7833c902e..6aec78f3f7 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/gpt_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_gpt_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/gpt_lld.c
- * @brief GPT Driver subsystem low level driver source template.
+ * @file hal_gpt_lld.c
+ * @brief PLATFORM GPT subsystem low level driver source.
*
* @addtogroup GPT
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_GPT || defined(__DOXYGEN__)
+#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief GPTD1 driver identifier.
*/
-#if PLATFORM_GPT_USE_GPT1 || defined(__DOXYGEN__)
+#if (PLATFORM_GPT_USE_GPT1 == TRUE) || defined(__DOXYGEN__)
GPTDriver GPTD1;
#endif
@@ -65,7 +64,7 @@ GPTDriver GPTD1;
*/
void gpt_lld_init(void) {
-#if PLATFORM2_GPT_USE_TIM1
+#if PLATFORM_GPT_USE_GPT1 == TRUE
/* Driver initialization.*/
gptObjectInit(&GPTD1);
#endif
@@ -82,11 +81,11 @@ void gpt_lld_start(GPTDriver *gptp) {
if (gptp->state == GPT_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_GPT_USE_GPT1
+#if PLATFORM_GPT_USE_GPT1 == TRUE
if (&GPTD1 == gptp) {
}
-#endif /* PLATFORM_GPT_USE_GPT1 */
+#endif
}
/* Configures the peripheral.*/
@@ -105,11 +104,11 @@ void gpt_lld_stop(GPTDriver *gptp) {
/* Resets the peripheral.*/
/* Disables the peripheral.*/
-#if PLATFORM_GPT_USE_GPT1
+#if PLATFORM_GPT_USE_GPT1 == TRUE
if (&GPTD1 == gptp) {
}
-#endif /* PLATFORM_GPT_USE_GPT1 */
+#endif
}
}
@@ -159,6 +158,6 @@ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
}
-#endif /* HAL_USE_GPT */
+#endif /* HAL_USE_GPT == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/gpt_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_gpt_lld.h
similarity index 87%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/gpt_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_gpt_lld.h
index a650b829bc..89b68ad4a0 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/gpt_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_gpt_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/gpt_lld.h
- * @brief GPT Driver subsystem low level driver header template.
+ * @file hal_gpt_lld.h
+ * @brief PLATFORM GPT subsystem low level driver header.
*
* @addtogroup GPT
* @{
*/
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
+#ifndef HAL_GPT_LLD_H
+#define HAL_GPT_LLD_H
-#if HAL_USE_GPT || defined(__DOXYGEN__)
+#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -36,16 +36,16 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
* @brief GPTD1 driver enable switch.
* @details If set to @p TRUE the support for GPTD1 is included.
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
*/
-#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM1 FALSE
+#if !defined(PLATFORM_GPT_USE_GPT1) || defined(__DOXYGEN__)
+#define PLATFORM_GPT_USE_GPT1 FALSE
#endif
/** @} */
@@ -130,24 +130,25 @@ struct GPTDriver {
/* External declarations. */
/*===========================================================================*/
-#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__)
+#if (PLATFORM_GPT_USE_GPT1 == TRUE) && !defined(__DOXYGEN__)
extern GPTDriver GPTD1;
#endif
+
#ifdef __cplusplus
extern "C" {
#endif
void gpt_lld_init(void);
void gpt_lld_start(GPTDriver *gptp);
void gpt_lld_stop(GPTDriver *gptp);
- void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
+ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval);
void gpt_lld_stop_timer(GPTDriver *gptp);
void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_GPT */
+#endif /* HAL_USE_GPT == TRUE */
-#endif /* _GPT_LLD_H_ */
+#endif /* HAL_GPT_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/i2c_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2c_lld.c
similarity index 81%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/i2c_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2c_lld.c
index 8566f3a181..1cb82eacd8 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/i2c_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2c_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/i2c_lld.c
- * @brief I2C Driver subsystem low level driver source template.
+ * @file hal_i2c_lld.c
+ * @brief PLATFORM I2C subsystem low level driver source.
*
* @addtogroup I2C
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_I2C || defined(__DOXYGEN__)
+#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief I2C1 driver identifier.
*/
-#if PLATFORM_I2C_USE_I2C1 || defined(__DOXYGEN__)
+#if (PLATFORM_I2C_USE_I2C1 == TRUE) || defined(__DOXYGEN__)
I2CDriver I2CD1;
#endif
@@ -65,9 +64,9 @@ I2CDriver I2CD1;
*/
void i2c_lld_init(void) {
-#if PLATFORM_I2C_USE_I2C1
+#if PLATFORM_I2C_USE_I2C1 == TRUE
i2cObjectInit(&I2CD1);
-#endif /* PLATFORM_I2C_USE_I2C1 */
+#endif
}
/**
@@ -81,13 +80,12 @@ void i2c_lld_start(I2CDriver *i2cp) {
if (i2cp->state == I2C_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_I2C_USE_I2C1
+#if PLATFORM_I2C_USE_I2C1 == TRUE
if (&I2CD1 == i2cp) {
}
-#endif /* PLATFORM_I2C_USE_I2C1 */
+#endif
}
- /* Configures the peripheral.*/
}
@@ -101,21 +99,18 @@ void i2c_lld_start(I2CDriver *i2cp) {
void i2c_lld_stop(I2CDriver *i2cp) {
if (i2cp->state != I2C_STOP) {
- /* Resets the peripheral.*/
/* Disables the peripheral.*/
-#if PLATFORM_I2C_USE_I2C1
+#if PLATFORM_I2C_USE_I2C1 == TRUE
if (&I2CD1 == i2cp) {
}
-#endif /* PLATFORM_I2C_USE_I2C1 */
+#endif
}
}
/**
* @brief Receives data via the I2C bus as master.
- * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
- * hardware restriction.
*
* @param[in] i2cp pointer to the @p I2CDriver object
* @param[in] addr slave device address
@@ -126,10 +121,10 @@ void i2c_lld_stop(I2CDriver *i2cp) {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a
* timeout the driver must be stopped and restarted
* because the bus is in an uncertain state.
*
@@ -145,13 +140,11 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
(void)rxbytes;
(void)timeout;
- return RDY_OK;
+ return MSG_OK;
}
/**
* @brief Transmits data via the I2C bus as master.
- * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
- * This is hardware restriction.
*
* @param[in] i2cp pointer to the @p I2CDriver object
* @param[in] addr slave device address
@@ -164,10 +157,10 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a
* timeout the driver must be stopped and restarted
* because the bus is in an uncertain state.
*
@@ -186,9 +179,9 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
(void)rxbytes;
(void)timeout;
- return RDY_OK;
+ return MSG_OK;
}
-#endif /* HAL_USE_I2C */
+#endif /* HAL_USE_I2C == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/i2c_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2c_lld.h
similarity index 81%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/i2c_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2c_lld.h
index af94c413ff..2a54c62abb 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/i2c_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2c_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/i2c_lld.h
- * @brief I2C Driver subsystem low level driver header template.
+ * @file hal_i2c_lld.h
+ * @brief PLATFORM I2C subsystem low level driver header.
*
* @addtogroup I2C
* @{
*/
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
+#ifndef HAL_I2C_LLD_H
+#define HAL_I2C_LLD_H
-#if HAL_USE_I2C || defined(__DOXYGEN__)
+#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -36,7 +36,7 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
@@ -45,7 +45,7 @@
* @note The default is @p FALSE.
*/
#if !defined(PLATFORM_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define PLATFORM_I2C_USE_I2C1 FALSE
+#define PLATFORM_I2C_USE_I2C1 FALSE
#endif
/** @} */
@@ -58,7 +58,7 @@
/*===========================================================================*/
/**
- * @brief Type representing I2C address.
+ * @brief Type representing an I2C address.
*/
typedef uint16_t i2caddr_t;
@@ -68,15 +68,12 @@ typedef uint16_t i2caddr_t;
typedef uint32_t i2cflags_t;
/**
- * @brief Driver configuration structure.
+ * @brief Type of I2C driver configuration structure.
* @note Implementations may extend this structure to contain more,
* architecture dependent, fields.
*/
-
-/**
- * @brief Driver configuration structure.
- */
typedef struct {
+ /* End of the mandatory fields.*/
uint32_t dummy;
} I2CConfig;
@@ -86,7 +83,7 @@ typedef struct {
typedef struct I2CDriver I2CDriver;
/**
- * @brief Structure representing an I2C driver.
+ * @brief Structure representing an I2C driver.
*/
struct I2CDriver {
/**
@@ -101,16 +98,9 @@ struct I2CDriver {
* @brief Error flags.
*/
i2cflags_t errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
+#if (I2C_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ mutex_t mutex;
#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
#if defined(I2C_DRIVER_EXT_FIELDS)
I2C_DRIVER_EXT_FIELDS
#endif
@@ -134,11 +124,9 @@ struct I2CDriver {
/* External declarations. */
/*===========================================================================*/
-#if !defined(__DOXYGEN__)
-#if PLATFORM_I2C_USE_I2C1
+#if (PLATFORM_I2C_USE_I2C1 == TRUE) && !defined(__DOXYGEN__)
extern I2CDriver I2CD1;
#endif
-#endif
#ifdef __cplusplus
extern "C" {
@@ -157,8 +145,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_I2C */
+#endif /* HAL_USE_I2C == TRUE */
-#endif /* _I2C_LLD_H_ */
+#endif /* HAL_I2C_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/i2s_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2s_lld.c
similarity index 70%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/i2s_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2s_lld.c
index b92ca0a865..64f90615c9 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/platforms/STM32/i2s_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2s_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file STM32/i2s_lld.c
- * @brief I2S Driver subsystem low level driver source template.
+ * @file hal_i2s_lld.c
+ * @brief PLATFORM I2S subsystem low level driver source.
*
* @addtogroup I2S
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_I2S || defined(__DOXYGEN__)
+#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -35,6 +34,11 @@
/* Driver exported variables. */
/*===========================================================================*/
+/** @brief I2S2 driver identifier.*/
+#if (PLATFORM_I2S_USE_I2S1 == TRUE) || defined(__DOXYGEN__)
+I2SDriver I2SD1;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -58,14 +62,8 @@
*/
void i2s_lld_init(void) {
-#if STM32_I2S_USE_I2S2
- spiObjectInit(&I2SD2);
- I2SD2.spi = SPI2;
-#endif
-
-#if STM32_I2S_USE_I2S3
- spiObjectInit(&I2SD3);
- I2SD3.spi = SPI3;
+#if PLATFORM_I2S_USE_I2S1
+ i2sObjectInit(&I2SD1);
#endif
}
@@ -80,30 +78,13 @@ void i2s_lld_start(I2SDriver *i2sp) {
/* If in stopped state then enables the SPI and DMA clocks.*/
if (i2sp->state == I2S_STOP) {
-#if STM32_SPI_USE_SPI2
- if (&SPID2 == spip) {
- bool_t b;
- b = dmaStreamAllocate(spip->dma,
- STM32_I2S_I2S2_IRQ_PRIORITY,
- (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
- (void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
- rccEnableSPI2(FALSE);
- }
-#endif
-#if STM32_SPI_USE_SPI3
- if (&SPID3 == spip) {
- bool_t b;
- b = dmaStreamAllocate(spip->dma,
- STM32_I2S_I2S3_IRQ_PRIORITY,
- (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
- (void *)spip);
- chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
- rccEnableSPI3(FALSE);
+
+#if PLATFORM_I2S_USE_I2S1
+ if (&I2SD1 == i2sp) {
+
}
#endif
}
- /* Configuration.*/
}
/**
@@ -115,9 +96,13 @@ void i2s_lld_start(I2SDriver *i2sp) {
*/
void i2s_lld_stop(I2SDriver *i2sp) {
+ /* If in ready state then disables the SPI clock.*/
if (i2sp->state == I2S_READY) {
- /* Clock deactivation.*/
+#if PLATFORM_I2S_USE_I2S1
+ if (&I2SD1 == i2sp) {
+ }
+#endif
}
}
@@ -130,17 +115,7 @@ void i2s_lld_stop(I2SDriver *i2sp) {
*/
void i2s_lld_start_exchange(I2SDriver *i2sp) {
-}
-
-/**
- * @brief Starts a I2S data exchange in continuous mode.
- *
- * @param[in] i2sp pointer to the @p I2SDriver object
- *
- * @notapi
- */
-void i2s_lld_start_exchange_continuous(I2SDriver *i2sp) {
-
+ (void)i2sp;
}
/**
@@ -154,6 +129,7 @@ void i2s_lld_start_exchange_continuous(I2SDriver *i2sp) {
*/
void i2s_lld_stop_exchange(I2SDriver *i2sp) {
+ (void)i2sp;
}
#endif /* HAL_USE_I2S */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2s_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2s_lld.h
new file mode 100644
index 0000000000..3bc2564244
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_i2s_lld.h
@@ -0,0 +1,143 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_i2s_lld.h
+ * @brief PLATFORM I2S subsystem low level driver header.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#ifndef HAL_I2S_LLD_H
+#define HAL_I2S_LLD_H
+
+#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name PLATFORM configuration options
+ * @{
+ */
+/**
+ * @brief I2SD1 driver enable switch.
+ * @details If set to @p TRUE the support for I2S1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(PLATFORM_I2S_USE_I2S1) || defined(__DOXYGEN__)
+#define PLATFORM_I2S_USE_I2S1 FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an I2S driver.
+ */
+typedef struct I2SDriver I2SDriver;
+
+/**
+ * @brief I2S notification callback type.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] offset offset in buffers of the data to read/write
+ * @param[in] n number of samples to read/write
+ */
+typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n);
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Transmission buffer pointer.
+ * @note Can be @p NULL if TX is not required.
+ */
+ const void *tx_buffer;
+ /**
+ * @brief Receive buffer pointer.
+ * @note Can be @p NULL if RX is not required.
+ */
+ void *rx_buffer;
+ /**
+ * @brief TX and RX buffers size as number of samples.
+ */
+ size_t size;
+ /**
+ * @brief Callback function called during streaming.
+ */
+ i2scallback_t end_cb;
+ /* End of the mandatory fields.*/
+} I2SConfig;
+
+/**
+ * @brief Structure representing an I2S driver.
+ */
+struct I2SDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2sstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2SConfig *config;
+ /* End of the mandatory fields.*/
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (PLATFORM_I2S_USE_I2S1 == TRUE) && !defined(__DOXYGEN__)
+extern I2SDriver I2SD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2s_lld_init(void);
+ void i2s_lld_start(I2SDriver *i2sp);
+ void i2s_lld_stop(I2SDriver *i2sp);
+ void i2s_lld_start_exchange(I2SDriver *i2sp);
+ void i2s_lld_stop_exchange(I2SDriver *i2sp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2S == TRUE */
+
+#endif /* HAL_I2S_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/icu_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_icu_lld.c
similarity index 64%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/icu_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_icu_lld.c
index 73127df36b..bbe15d8d61 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/icu_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_icu_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/icu_lld.c
- * @brief ICU Driver subsystem low level driver source template.
+ * @file hal_icu_lld.c
+ * @brief PLATFORM ADC subsystem low level driver source.
*
* @addtogroup ICU
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_ICU || defined(__DOXYGEN__)
+#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -36,9 +35,10 @@
/*===========================================================================*/
/**
- * @brief ICU1 driver identifier.
+ * @brief ICUD1 driver identifier.
+ * @note The driver ICUD1 allocates the complex timer TIM1 when enabled.
*/
-#if PLATFORM_ICU_USE_ICU1 || defined(__DOXYGEN__)
+#if (PLATFORM_ICU_USE_ICU1 == TRUE) || defined(__DOXYGEN__)
ICUDriver ICUD1;
#endif
@@ -65,10 +65,10 @@ ICUDriver ICUD1;
*/
void icu_lld_init(void) {
-#if PLATFORM_ICU_USE_ICU1
+#if PLATFORM_ICU_USE_ICU1 == TRUE
/* Driver initialization.*/
icuObjectInit(&ICUD1);
-#endif /* PLATFORM_ICU_USE_ICU1 */
+#endif
}
/**
@@ -81,15 +81,13 @@ void icu_lld_init(void) {
void icu_lld_start(ICUDriver *icup) {
if (icup->state == ICU_STOP) {
- /* Enables the peripheral.*/
-#if PLATFORM_ICU_USE_ICU1
+ /* Clock activation and timer reset.*/
+#if PLATFORM_ICU_USE_ICU1 == TRUE
if (&ICUD1 == icup) {
}
-#endif /* PLATFORM_ICU_USE_ICU1 */
+#endif
}
- /* Configures the peripheral.*/
-
}
/**
@@ -102,77 +100,86 @@ void icu_lld_start(ICUDriver *icup) {
void icu_lld_stop(ICUDriver *icup) {
if (icup->state == ICU_READY) {
- /* Resets the peripheral.*/
-
- /* Disables the peripheral.*/
-#if PLATFORM_ICU_USE_ICU1
+ /* Clock deactivation.*/
+#if PLATFORM_ICU_USE_ICU1 == TRUE
if (&ICUD1 == icup) {
}
-#endif /* PLATFORM_ICU_USE_ICU1 */
+#endif
}
}
/**
- * @brief Enables the input capture.
+ * @brief Starts the input capture.
*
* @param[in] icup pointer to the @p ICUDriver object
*
* @notapi
*/
-void icu_lld_enable(ICUDriver *icup) {
+void icu_lld_start_capture(ICUDriver *icup) {
(void)icup;
-
}
/**
- * @brief Disables the input capture.
+ * @brief Waits for a completed capture.
+ * @note The operation is performed in polled mode.
+ * @note In order to use this function notifications must be disabled.
*
* @param[in] icup pointer to the @p ICUDriver object
+ * @return The capture status.
+ * @retval false if the capture is successful.
+ * @retval true if a timer overflow occurred.
*
* @notapi
*/
-void icu_lld_disable(ICUDriver *icup) {
+bool icu_lld_wait_capture(ICUDriver *icup) {
(void)icup;
+ return false;
}
/**
- * @brief Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- * edge and the stop edge.
+ * @brief Stops the input capture.
*
* @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
*
* @notapi
*/
-icucnt_t icu_lld_get_width(ICUDriver *icup) {
+void icu_lld_stop_capture(ICUDriver *icup) {
(void)icup;
-
- return 0;
}
/**
- * @brief Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- * edge and the next start edge.
+ * @brief Enables notifications.
+ * @pre The ICU unit must have been activated using @p icuStart().
+ * @note If the notification is already enabled then the call has no effect.
*
* @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
*
- * @notapi
+ * @api
*/
-icucnt_t icu_lld_get_period(ICUDriver *icup) {
+void icu_lld_enable_notifications(ICUDriver *icup) {
(void)icup;
+}
+
+/**
+ * @brief Disables notifications.
+ * @pre The ICU unit must have been activated using @p icuStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @api
+ */
+void icu_lld_disable_notifications(ICUDriver *icup) {
- return 0;
+ (void)icup;
}
-#endif /* HAL_USE_ICU */
+#endif /* HAL_USE_ICU == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/icu_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_icu_lld.h
similarity index 65%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/icu_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_icu_lld.h
index dbe31ca795..baf0dff2f0 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/icu_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_icu_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -13,23 +13,19 @@
See the License for the specific language governing permissions and
limitations under the License.
*/
-/*
- Concepts and parts of this file have been contributed by Fabio Utzig and
- Xo Wang.
- */
/**
- * @file templates/icu_lld.h
- * @brief ICU Driver subsystem low level driver header template.
+ * @file hal_icu_lld.h
+ * @brief PLATFORM ICU subsystem low level driver header.
*
* @addtogroup ICU
* @{
*/
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
+#ifndef HAL_ICU_LLD_H
+#define HAL_ICU_LLD_H
-#if HAL_USE_ICU || defined(__DOXYGEN__)
+#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -40,15 +36,16 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
- * @brief ICU driver enable switch.
- * @details If set to @p TRUE the support for ICU1 is included.
+ * @brief ICUD1 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_ICU_USE_ICU1) || defined(__DOXYGEN__)
-#define PLATFORM_ICU_USE_ICU1 FALSE
+#define PLATFORM_ICU_USE_ICU1 FALSE
#endif
/** @} */
@@ -61,11 +58,11 @@
/*===========================================================================*/
/**
- * @brief ICU driver mode.
+ * @brief ICU driver mode.
*/
typedef enum {
ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */
- ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */
+ ICU_INPUT_ACTIVE_LOW = 1 /**< Trigger on falling edge. */
} icumode_t;
/**
@@ -76,7 +73,7 @@ typedef uint32_t icufreq_t;
/**
* @brief ICU counter type.
*/
-typedef uint16_t icucnt_t;
+typedef uint32_t icucnt_t;
/**
* @brief Driver configuration structure.
@@ -130,11 +127,47 @@ struct ICUDriver {
/* Driver macros. */
/*===========================================================================*/
+/**
+ * @brief Returns the width of the latest pulse.
+ * @details The pulse width is defined as number of ticks between the start
+ * edge and the stop edge.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+#define icu_lld_get_width(icup) 0
+
+/**
+ * @brief Returns the width of the latest cycle.
+ * @details The cycle width is defined as number of ticks between a start
+ * edge and the next start edge.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+#define icu_lld_get_period(icup) 0
+
+/**
+ * @brief Check on notifications status.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The notifications status.
+ * @retval false if notifications are not enabled.
+ * @retval true if notifications are enabled.
+ *
+ * @notapi
+ */
+#define icu_lld_are_notifications_enabled(icup) false
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_ICU_USE_ICU1 && !defined(__DOXYGEN__)
+#if (PLATFORM_ICU_USE_ICU1 == TRUE) && !defined(__DOXYGEN__)
extern ICUDriver ICUD1;
#endif
@@ -144,16 +177,17 @@ extern "C" {
void icu_lld_init(void);
void icu_lld_start(ICUDriver *icup);
void icu_lld_stop(ICUDriver *icup);
- void icu_lld_enable(ICUDriver *icup);
- void icu_lld_disable(ICUDriver *icup);
- icucnt_t icu_lld_get_width(ICUDriver *icup);
- icucnt_t icu_lld_get_period(ICUDriver *icup);
+ void icu_lld_start_capture(ICUDriver *icup);
+ bool icu_lld_wait_capture(ICUDriver *icup);
+ void icu_lld_stop_capture(ICUDriver *icup);
+ void icu_lld_enable_notifications(ICUDriver *icup);
+ void icu_lld_disable_notifications(ICUDriver *icup);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_ICU */
+#endif /* HAL_USE_ICU == TRUE */
-#endif /* _ICU_LLD_H_ */
+#endif /* HAL_ICU_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_lld.c
index e4bcc03318..85c831fd95 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,14 +15,13 @@
*/
/**
- * @file templates/hal_lld.c
- * @brief HAL Driver subsystem low level driver source template.
+ * @file hal_lld.c
+ * @brief PLATFORM HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
-#include "ch.h"
#include "hal.h"
/*===========================================================================*/
@@ -58,17 +57,4 @@ void hal_lld_init(void) {
}
-/**
- * @brief Platform early initialization.
- * @note All the involved constants come from the file @p board.h.
- * @note This function is meant to be invoked early during the system
- * initialization, it is usually invoked from the file
- * @p board.c.
- *
- * @special
- */
-void platform_early_init(void) {
-
-}
-
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_lld.h
index 66ea8ccf9d..9c4d9760ad 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,8 +15,8 @@
*/
/**
- * @file templates/hal_lld.h
- * @brief HAL subsystem low level driver header template.
+ * @file hal_lld.h
+ * @brief PLATFORM HAL subsystem low level driver header.
*
* @addtogroup HAL
* @{
@@ -30,21 +30,22 @@
/*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name Platform identification
+ * @name Platform identification macros
* @{
*/
-#define PLATFORM_NAME ""
+#define PLATFORM_NAME "templates"
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
+/**
+ * @name PLATFORM configuration options
+ * @{
+ */
+/** @} */
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -60,43 +61,10 @@
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() 0
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() 0
-
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mac_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_mac_lld.c
similarity index 89%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mac_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_mac_lld.c
index 2dc9d960a8..580c4235fd 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mac_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_mac_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,8 +15,8 @@
*/
/**
- * @file templates/mac_lld.c
- * @brief MAC Driver subsystem low level driver source template.
+ * @file hal_mac_lld.c
+ * @brief PLATFORM MAC subsystem low level driver source.
*
* @addtogroup MAC
* @{
@@ -24,11 +24,11 @@
#include
-#include "ch.h"
#include "hal.h"
-#include "mii.h"
-#if HAL_USE_MAC || defined(__DOXYGEN__)
+#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__)
+
+#include "hal_mii.h"
/*===========================================================================*/
/* Driver local definitions. */
@@ -41,7 +41,7 @@
/**
* @brief MAC1 driver identifier.
*/
-#if PLATFORM_MAC_USE_MAC1 || defined(__DOXYGEN__)
+#if (PLATFORM_MAC_USE_MAC1 == TRUE) || defined(__DOXYGEN__)
MACDriver ETHD1;
#endif
@@ -68,10 +68,10 @@ MACDriver ETHD1;
*/
void mac_lld_init(void) {
-#if PLATFORM_MAC_USE_MAC1
+#if PLATFORM_MAC_USE_MAC1 == TRUE
/* Driver initialization.*/
macObjectInit(&MACD1);
-#endif /* PLATFORM_MAC_USE_MAC1 */
+#endif
}
/**
@@ -85,11 +85,11 @@ void mac_lld_start(MACDriver *macp) {
if (macp->state == MAC_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_MAC_USE_MAC1
+#if PLATFORM_MAC_USE_MAC1 == TRUE
if (&MACD1 == macp) {
}
-#endif /* PLATFORM_MAC_USE_MAC1 */
+#endif
}
/* Configures the peripheral.*/
@@ -104,15 +104,15 @@ void mac_lld_start(MACDriver *macp) {
*/
void mac_lld_stop(MACDriver *macp) {
- if (macp->state == MAC_ACTIVE) {
+ if (macp->state != MAC_STOP) {
/* Resets the peripheral.*/
/* Disables the peripheral.*/
-#if PLATFORM_MAC_USE_MAC1
+#if PLATFORM_MAC_USE_MAC1 == TRUE
if (&MACD1 == macp) {
}
-#endif /* PLATFORM_MAC_USE_MAC1 */
+#endif
}
}
@@ -124,8 +124,8 @@ void mac_lld_stop(MACDriver *macp) {
* @param[in] macp pointer to the @p MACDriver object
* @param[out] tdp pointer to a @p MACTransmitDescriptor structure
* @return The operation status.
- * @retval RDY_OK the descriptor has been obtained.
- * @retval RDY_TIMEOUT descriptor not available.
+ * @retval MSG_OK the descriptor has been obtained.
+ * @retval MSG_TIMEOUT descriptor not available.
*
* @notapi
*/
@@ -135,7 +135,7 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
(void)macp;
(void)tdp;
- return RDY_OK;
+ return MSG_OK;
}
/**
@@ -158,8 +158,8 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
* @param[in] macp pointer to the @p MACDriver object
* @param[out] rdp pointer to a @p MACReceiveDescriptor structure
* @return The operation status.
- * @retval RDY_OK the descriptor has been obtained.
- * @retval RDY_TIMEOUT descriptor not available.
+ * @retval MSG_OK the descriptor has been obtained.
+ * @retval MSG_TIMEOUT descriptor not available.
*
* @notapi
*/
@@ -169,7 +169,7 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
(void)macp;
(void)rdp;
- return RDY_OK;
+ return MSG_OK;
}
/**
@@ -192,16 +192,16 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
*
* @param[in] macp pointer to the @p MACDriver object
* @return The link status.
- * @retval TRUE if the link is active.
- * @retval FALSE if the link is down.
+ * @retval true if the link is active.
+ * @retval false if the link is down.
*
* @notapi
*/
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
+bool mac_lld_poll_link_status(MACDriver *macp) {
(void)macp;
- return FALSE;
+ return false;
}
/**
@@ -251,7 +251,7 @@ size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
return size;
}
-#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
+#if (MAC_USE_ZERO_COPY == TRUE) || defined(__DOXYGEN__)
/**
* @brief Returns a pointer to the next transmit buffer in the descriptor
* chain.
@@ -306,8 +306,8 @@ const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
return NULL;
}
-#endif /* MAC_USE_ZERO_COPY */
+#endif /* MAC_USE_ZERO_COPY == TRUE */
-#endif /* HAL_USE_MAC */
+#endif /* HAL_USE_MAC == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mac_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_mac_lld.h
similarity index 87%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mac_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_mac_lld.h
index 7f0222aff5..1a19234d95 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mac_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_mac_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/mac_lld.h
- * @brief MAC Driver subsystem low level driver header template.
+ * @file hal_mac_lld.h
+ * @brief PLATFORM MAC subsystem low level driver header.
*
* @addtogroup MAC
* @{
*/
-#ifndef _MAC_LLD_H_
-#define _MAC_LLD_H_
+#ifndef HAL_MAC_LLD_H
+#define HAL_MAC_LLD_H
-#if HAL_USE_MAC || defined(__DOXYGEN__)
+#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -34,19 +34,20 @@
/**
* @brief This implementation supports the zero-copy mode API.
*/
-#define MAC_SUPPORTS_ZERO_COPY TRUE
+#define MAC_SUPPORTS_ZERO_COPY TRUE
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
* @brief MAC driver enable switch.
* @details If set to @p TRUE the support for MAC1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_MAC_USE_MAC1) || defined(__DOXYGEN__)
#define PLATFORM_MAC_USE_MAC1 FALSE
@@ -87,16 +88,16 @@ struct MACDriver {
/**
* @brief Transmit semaphore.
*/
- Semaphore tdsem;
+ threads_queue_t tdqueue;
/**
* @brief Receive semaphore.
*/
- Semaphore rdsem;
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
+ threads_queue_t rdqueue;
+#if (MAC_USE_EVENTS == TRUE) || defined(__DOXYGEN__)
/**
* @brief Receive event.
*/
- EventSource rdevent;
+ event_source_t rdevent;
#endif
/* End of the mandatory fields.*/
};
@@ -139,7 +140,7 @@ typedef struct {
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_MAC_USE_MAC1 && !defined(__DOXYGEN__)
+#if (PLATFORM_MAC_USE_MAC1 == TRUE) && !defined(__DOXYGEN__)
extern MACDriver ETHD1;
#endif
@@ -155,26 +156,26 @@ extern "C" {
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp);
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
- bool_t mac_lld_poll_link_status(MACDriver *macp);
+ bool mac_lld_poll_link_status(MACDriver *macp);
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size);
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
uint8_t *buf,
size_t size);
-#if MAC_USE_ZERO_COPY
+#if MAC_USE_ZERO_COPY == TRUE
uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
size_t size,
size_t *sizep);
const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
size_t *sizep);
-#endif /* MAC_USE_ZERO_COPY */
+#endif
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_MAC */
+#endif /* HAL_USE_MAC == TRUE */
-#endif /* _MAC_LLD_H_ */
+#endif /* HAL_MAC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pal_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pal_lld.c
similarity index 92%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pal_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pal_lld.c
index 599fc58576..ff950595f6 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pal_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pal_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/pal_lld.c
- * @brief PAL subsystem low level driver template.
+ * @file hal_pal_lld.c
+ * @brief PLATFORM PAL subsystem low level driver source.
*
* @addtogroup PAL
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_PAL || defined(__DOXYGEN__)
+#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -86,6 +85,6 @@ void _pal_lld_setgroupmode(ioportid_t port,
}
-#endif /* HAL_USE_PAL */
+#endif /* HAL_USE_PAL == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pal_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pal_lld.h
similarity index 64%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pal_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pal_lld.h
index be240ea671..0594b0855c 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pal_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pal_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/pal_lld.h
- * @brief PAL subsystem low level driver header template.
+ * @file hal_pal_lld.h
+ * @brief PLATFORM PAL subsystem low level driver header.
*
* @addtogroup PAL
* @{
*/
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
+#ifndef HAL_PAL_LLD_H
+#define HAL_PAL_LLD_H
-#if HAL_USE_PAL || defined(__DOXYGEN__)
+#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Unsupported modes and specific modes */
@@ -35,6 +35,52 @@
/* I/O Ports Types and constants. */
/*===========================================================================*/
+/**
+ * @name Port related definitions
+ * @{
+ */
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 16U
+
+/**
+ * @brief Whole port mask.
+ * @details This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU)
+/** @} */
+
+/**
+ * @name Line handling macros
+ * @{
+ */
+/**
+ * @brief Forms a line identifier.
+ * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
+ * of this type is platform-dependent.
+ */
+#define PAL_LINE(port, pad) \
+ ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
+
+/**
+ * @brief Decodes a port identifier from a line identifier.
+ */
+#define PAL_PORT(line) \
+ ((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U))
+
+/**
+ * @brief Decodes a pad identifier from a line identifier.
+ */
+#define PAL_PAD(line) \
+ ((uint32_t)((uint32_t)(line) & 0x0000000FU))
+
+/**
+ * @brief Value identifying an invalid line.
+ */
+#define PAL_NOLINE 0U
+/** @} */
+
/**
* @brief Generic I/O ports static initializer.
* @details An instance of this structure must be passed to @p palInit() at
@@ -48,17 +94,6 @@ typedef struct {
} PALConfig;
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief Whole port mask.
- * @brief This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
/**
* @brief Digital I/O port sized unsigned type.
*/
@@ -69,6 +104,11 @@ typedef uint32_t ioportmask_t;
*/
typedef uint32_t iomode_t;
+/**
+ * @brief Type of an I/O line.
+ */
+typedef uint32_t ioline_t;
+
/**
* @brief Port Identifier.
* @details This type can be a scalar or some kind of pointer, do not make
@@ -110,7 +150,7 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_readport(port) 0
+#define pal_lld_readport(port) 0U
/**
* @brief Reads the output latch.
@@ -122,7 +162,7 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_readlatch(port) 0
+#define pal_lld_readlatch(port) 0U
/**
* @brief Writes a bits mask on a I/O port.
@@ -132,7 +172,12 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_writeport(port, bits)
+#define pal_lld_writeport(port, bits) \
+ do { \
+ (void)port; \
+ (void)bits; \
+ } while (false)
+
/**
* @brief Sets a bits mask on a I/O port.
@@ -145,7 +190,12 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_setport(port, bits)
+#define pal_lld_setport(port, bits) \
+ do { \
+ (void)port; \
+ (void)bits; \
+ } while (false)
+
/**
* @brief Clears a bits mask on a I/O port.
@@ -158,7 +208,12 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_clearport(port, bits)
+#define pal_lld_clearport(port, bits) \
+ do { \
+ (void)port; \
+ (void)bits; \
+ } while (false)
+
/**
* @brief Toggles a bits mask on a I/O port.
@@ -171,7 +226,12 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_toggleport(port, bits)
+#define pal_lld_toggleport(port, bits) \
+ do { \
+ (void)port; \
+ (void)bits; \
+ } while (false)
+
/**
* @brief Reads a group of bits.
@@ -186,7 +246,7 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_readgroup(port, mask, offset) 0
+#define pal_lld_readgroup(port, mask, offset) 0U
/**
* @brief Writes a group of bits.
@@ -202,7 +262,13 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
+#define pal_lld_writegroup(port, mask, offset, bits) \
+ do { \
+ (void)port; \
+ (void)mask; \
+ (void)offset; \
+ (void)bits; \
+ } while (false)
/**
* @brief Pads group mode setup.
@@ -251,7 +317,12 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_writepad(port, pad, bit)
+#define pal_lld_writepad(port, pad, bit) \
+ do { \
+ (void)port; \
+ (void)pad; \
+ (void)bit; \
+ } while (false)
/**
* @brief Sets a pad logical state to @p PAL_HIGH.
@@ -264,7 +335,12 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_setpad(port, pad)
+#define pal_lld_setpad(port, pad) \
+ do { \
+ (void)port; \
+ (void)pad; \
+ } while (false)
+
/**
* @brief Clears a pad logical state to @p PAL_LOW.
@@ -277,7 +353,12 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_clearpad(port, pad)
+#define pal_lld_clearpad(port, pad) \
+ do { \
+ (void)port; \
+ (void)pad; \
+ } while (false)
+
/**
* @brief Toggles a pad logical state.
@@ -290,7 +371,12 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_togglepad(port, pad)
+#define pal_lld_togglepad(port, pad) \
+ do { \
+ (void)port; \
+ (void)pad; \
+ } while (false)
+
/**
* @brief Pad mode setup.
@@ -306,7 +392,13 @@ typedef uint32_t ioportid_t;
*
* @notapi
*/
-#define pal_lld_setpadmode(port, pad, mode)
+#define pal_lld_setpadmode(port, pad, mode) \
+ do { \
+ (void)port; \
+ (void)pad; \
+ (void)mode; \
+ } while (false)
+
#if !defined(__DOXYGEN__)
extern const PALConfig pal_default_config;
@@ -323,8 +415,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_PAL */
+#endif /* HAL_USE_PAL == TRUE */
-#endif /* _PAL_LLD_H_ */
+#endif /* HAL_PAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pwm_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pwm_lld.c
similarity index 56%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pwm_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pwm_lld.c
index c75c1d0f9d..69e0e708c6 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pwm_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pwm_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/pwm_lld.c
- * @brief PWM Driver subsystem low level driver source template.
+ * @file hal_pwm_lld.c
+ * @brief PLATFORM PWM subsystem low level driver source.
*
* @addtogroup PWM
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_PWM || defined(__DOXYGEN__)
+#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -36,9 +35,10 @@
/*===========================================================================*/
/**
- * @brief PWM1 driver identifier.
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the complex timer TIM1 when enabled.
*/
-#if PLATFORM_PWM_USE_PWM1 || defined(__DOXYGEN__)
+#if (PLATFORM_PWM_USE_PWM1 == TRUE) || defined(__DOXYGEN__)
PWMDriver PWMD1;
#endif
@@ -65,122 +65,156 @@ PWMDriver PWMD1;
*/
void pwm_lld_init(void) {
-#if PLATFORM_PWM_USE_PWM1
+#if PLATFORM_PWM_USE_PWM1 == TRUE
/* Driver initialization.*/
pwmObjectInit(&PWMD1);
-#endif /* PLATFORM_PWM_USE_PWM1 */
+#endif
}
/**
* @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
*
- * @param[in] pwmp pointer to the @p PWMDriver object
+ * @param[in] pwmp pointer to a @p PWMDriver object
*
* @notapi
*/
void pwm_lld_start(PWMDriver *pwmp) {
if (pwmp->state == PWM_STOP) {
- /* Enables the peripheral.*/
-#if PLATFORM_PWM_USE_PWM1
+ /* Clock activation and timer reset.*/
+#if PLATFORM_PWM_USE_PWM1 == TRUE
if (&PWMD1 == pwmp) {
}
-#endif /* PLATFORM_PWM_USE_PWM1 */
+#endif
}
- /* Configures the peripheral.*/
-
}
/**
* @brief Deactivates the PWM peripheral.
*
- * @param[in] pwmp pointer to the @p PWMDriver object
+ * @param[in] pwmp pointer to a @p PWMDriver object
*
* @notapi
*/
void pwm_lld_stop(PWMDriver *pwmp) {
+ /* If in ready state then disables the PWM clock.*/
if (pwmp->state == PWM_READY) {
- /* Resets the peripheral.*/
-
- /* Disables the peripheral.*/
-#if PLATFORM_PWM_USE_PWM1
+#if PLATFORM_PWM_USE_PWM1 == TRUE
if (&PWMD1 == pwmp) {
}
-#endif /* PLATFORM_PWM_USE_PWM1 */
+#endif
}
}
/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
+ * @brief Enables a PWM channel.
* @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
+ * @post The channel is active using the specified configuration.
* @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
+ * @note Channel notification is not enabled.
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
*
* @notapi
*/
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
(void)pwmp;
- (void)period;
-
+ (void)channel;
+ (void)width;
}
/**
- * @brief Enables a PWM channel.
+ * @brief Disables a PWM channel and its notification.
* @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note The function has effect at the next cycle start.
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width PWM pulse width as clock pulses number
+ * @param[in] channel PWM channel identifier (0...channels-1)
*
* @notapi
*/
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
(void)pwmp;
(void)channel;
- (void)width;
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+ (void)pwmp;
}
/**
- * @brief Disables a PWM channel.
+ * @brief Disables the periodic activation edge notification.
* @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
+ * @note If the notification is already disabled then the call has no effect.
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
*
* @notapi
*/
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+
+ (void)pwmp;
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
(void)pwmp;
(void)channel;
+}
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+
+ (void)pwmp;
+ (void)channel;
}
-#endif /* HAL_USE_PWM */
+#endif /* HAL_USE_PWM == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pwm_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pwm_lld.h
similarity index 66%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pwm_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pwm_lld.h
index 71f315cfb7..458157ec96 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/pwm_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_pwm_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/pwm_lld.h
- * @brief PWM Driver subsystem low level driver header template.
+ * @file hal_pwm_lld.h
+ * @brief PLATFORM PWM subsystem low level driver header.
*
* @addtogroup PWM
* @{
*/
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
+#ifndef HAL_PWM_LLD_H
+#define HAL_PWM_LLD_H
-#if HAL_USE_PWM || defined(__DOXYGEN__)
+#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -34,27 +34,28 @@
/**
* @brief Number of PWM channels per PWM driver.
*/
-#define PWM_CHANNELS 4
+#define PWM_CHANNELS 4
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
- * @brief PWM driver enable switch.
+ * @brief PWMD1 driver enable switch.
* @details If set to @p TRUE the support for PWM1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_PWM_USE_PWM1) || defined(__DOXYGEN__)
-#define PLATFORM_PWM_USE_PWM1 FALSE
+#define PLATFORM_PWM_USE_PWM1 FALSE
#endif
/** @} */
/*===========================================================================*/
-/* Derived constants and error checks. */
+/* Configuration checks. */
/*===========================================================================*/
/*===========================================================================*/
@@ -62,24 +63,27 @@
/*===========================================================================*/
/**
- * @brief PWM mode type.
+ * @brief Type of a PWM mode.
*/
typedef uint32_t pwmmode_t;
/**
- * @brief PWM channel type.
+ * @brief Type of a PWM channel.
*/
typedef uint8_t pwmchannel_t;
/**
- * @brief PWM counter type.
+ * @brief Type of a channels mask.
*/
-typedef uint16_t pwmcnt_t;
+typedef uint32_t pwmchnmsk_t;
/**
- * @brief PWM driver channel configuration structure.
- * @note Some architectures may not be able to support the channel mode
- * or the callback, in this case the fields are ignored.
+ * @brief Type of a PWM counter.
+ */
+typedef uint32_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
*/
typedef struct {
/**
@@ -96,9 +100,7 @@ typedef struct {
} PWMChannelConfig;
/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
+ * @brief Type of a PWM driver configuration structure.
*/
typedef struct {
/**
@@ -127,9 +129,7 @@ typedef struct {
} PWMConfig;
/**
- * @brief Structure representing an PWM driver.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
+ * @brief Structure representing a PWM driver.
*/
struct PWMDriver {
/**
@@ -137,13 +137,21 @@ struct PWMDriver {
*/
pwmstate_t state;
/**
- * @brief Current configuration data.
+ * @brief Current driver configuration data.
*/
const PWMConfig *config;
/**
* @brief Current PWM period in ticks.
*/
pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
#if defined(PWM_DRIVER_EXT_FIELDS)
PWM_DRIVER_EXT_FIELDS
#endif
@@ -155,21 +163,28 @@ struct PWMDriver {
/*===========================================================================*/
/**
- * @brief Returns a PWM channel status.
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
* @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
*
* @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] period new cycle time in ticks
*
* @notapi
*/
-#define pwm_lld_is_channel_enabled(pwmp, channel) FALSE
+#define pwm_lld_change_period(pwmp, period)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_PWM_USE_PWM1 && !defined(__DOXYGEN__)
+#if (PLATFORM_PWM_USE_PWM1 == TRUE) && !defined(__DOXYGEN__)
extern PWMDriver PWMD1;
#endif
@@ -179,17 +194,22 @@ extern "C" {
void pwm_lld_init(void);
void pwm_lld_start(PWMDriver *pwmp);
void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width);
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_PWM */
+#endif /* HAL_USE_PWM == TRUE */
-#endif /* _PWM_LLD_H_ */
+#endif /* HAL_PWM_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_qspi_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_qspi_lld.c
new file mode 100644
index 0000000000..ad2e615435
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_qspi_lld.c
@@ -0,0 +1,208 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_qspi_lld.c
+ * @brief PLATFORM QSPI subsystem low level driver source.
+ *
+ * @addtogroup QSPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_QSPI == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief QSPID1 driver identifier.*/
+#if (PLATFORM_QSPI_USE_QSPI1 == TRUE) || defined(__DOXYGEN__)
+QSPIDriver QSPID1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level QSPI driver initialization.
+ *
+ * @notapi
+ */
+void qspi_lld_init(void) {
+
+#if PLATFORM_QSPI_USE_QSPI1
+ qspiObjectInit(&QSPID1);
+#endif
+}
+
+/**
+ * @brief Configures and activates the QSPI peripheral.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @notapi
+ */
+void qspi_lld_start(QSPIDriver *qspip) {
+
+ /* If in stopped state then full initialization.*/
+ if (qspip->state == QSPI_STOP) {
+#if PLATFORM_QSPI_USE_QSPI1
+ if (&QSPID1 == qspip) {
+ }
+#endif
+
+ /* Common initializations.*/
+ }
+
+ /* QSPI setup and enable.*/
+}
+
+/**
+ * @brief Deactivates the QSPI peripheral.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @notapi
+ */
+void qspi_lld_stop(QSPIDriver *qspip) {
+
+ /* If in ready state then disables QSPI.*/
+ if (qspip->state == QSPI_READY) {
+
+ /* QSPI disable.*/
+
+ /* Stopping involved clocks.*/
+#if PLATFORM_QSPI_USE_QSPI1
+ if (&QSPID1 == qspip) {
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Sends a command without data phase.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ *
+ * @notapi
+ */
+void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp) {
+
+ (void)qspip;
+ (void)cmdp;
+}
+
+/**
+ * @brief Sends a command with data over the QSPI bus.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[in] n number of bytes to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, const uint8_t *txbuf) {
+
+ (void)qspip;
+ (void)cmdp;
+ (void)n;
+ (void)txbuf;
+}
+
+/**
+ * @brief Sends a command then receives data over the QSPI bus.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[in] n number of bytes to send
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, uint8_t *rxbuf) {
+
+ (void)qspip;
+ (void)cmdp;
+ (void)n;
+ (void)rxbuf;
+}
+
+#if (QSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Maps in memory space a QSPI flash device.
+ * @pre The memory flash device must be initialized appropriately
+ * before mapping it in memory space.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ * @param[in] cmdp pointer to the command descriptor
+ * @param[out] addrp pointer to the memory start address of the mapped
+ * flash or @p NULL
+ *
+ * @notapi
+ */
+void qspi_lld_map_flash(QSPIDriver *qspip,
+ const qspi_command_t *cmdp,
+ uint8_t **addrp) {
+
+ (void)qspip;
+ (void)cmdp;
+ (void)addrp;
+}
+
+/**
+ * @brief Maps in memory space a QSPI flash device.
+ * @post The memory flash device must be re-initialized for normal
+ * commands exchange.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object
+ *
+ * @notapi
+ */
+void qspi_lld_unmap_flash(QSPIDriver *qspip) {
+
+ (void)qspip;
+}
+#endif /* QSPI_SUPPORTS_MEMMAP == TRUE */
+
+#endif /* HAL_USE_QSPI */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_qspi_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_qspi_lld.h
new file mode 100644
index 0000000000..ce4c486783
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_qspi_lld.h
@@ -0,0 +1,158 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_qspi_lld.h
+ * @brief PLATFORM QSPI subsystem low level driver header.
+ *
+ * @addtogroup QSPI
+ * @{
+ */
+
+#ifndef HAL_QSPI_LLD_H
+#define HAL_QSPI_LLD_H
+
+#if (HAL_USE_QSPI == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name QSPI capabilities
+ * @{
+ */
+#define QSPI_SUPPORTS_MEMMAP TRUE
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief QSPID1 driver enable switch.
+ * @details If set to @p TRUE the support for QSPID1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(PLATFORM_QSPI_USE_QSPI1) || defined(__DOXYGEN__)
+#define PLATFORM_QSPI_USE_QSPI1 FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an QSPI driver.
+ */
+typedef struct QSPIDriver QSPIDriver;
+
+/**
+ * @brief Type of a QSPI notification callback.
+ *
+ * @param[in] qspip pointer to the @p QSPIDriver object triggering the
+ * callback
+ */
+typedef void (*qspicallback_t)(QSPIDriver *qspip);
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Operation complete callback or @p NULL.
+ */
+ qspicallback_t end_cb;
+ /* End of the mandatory fields.*/
+} QSPIConfig;
+
+/**
+ * @brief Structure representing an QSPI driver.
+ */
+struct QSPIDriver {
+ /**
+ * @brief Driver state.
+ */
+ qspistate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const QSPIConfig *config;
+#if (QSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif /* QSPI_USE_WAIT */
+#if (QSPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* QSPI_USE_MUTUAL_EXCLUSION */
+#if defined(QSPI_DRIVER_EXT_FIELDS)
+ QSPI_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (PLATFORM_QSPI_USE_QSPI1 == TRUE) && !defined(__DOXYGEN__)
+extern QSPIDriver QSPID1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void qspi_lld_init(void);
+ void qspi_lld_start(QSPIDriver *qspip);
+ void qspi_lld_stop(QSPIDriver *qspip);
+ void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp);
+ void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, const uint8_t *txbuf);
+ void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
+ size_t n, uint8_t *rxbuf);
+#if QSPI_SUPPORTS_MEMMAP == TRUE
+ void qspi_lld_map_flash(QSPIDriver *qspip,
+ const qspi_command_t *cmdp,
+ uint8_t **addrp);
+ void qspi_lld_unmap_flash(QSPIDriver *qspip);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_QSPI */
+
+#endif /* HAL_QSPI_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_rtc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_rtc_lld.c
new file mode 100644
index 0000000000..bcdf950d0d
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_rtc_lld.c
@@ -0,0 +1,153 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file hal_rtc_lld.c
+ * @brief PLATFORM RTC subsystem low level driver source.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief RTC driver identifier.
+ */
+#if (PLATFORM_RTC_USE_RTC1 == TRUE) && !defined(__DOXYGEN__)
+RTCDriver RTCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enable access to registers.
+ *
+ * @notapi
+ */
+void rtc_lld_init(void) {
+
+ /* RTC object initialization.*/
+#if PLATFORM_RTC_USE_RTC1 == TRUE
+ rtcObjectInit(&RTCD1);
+#endif
+}
+
+/**
+ * @brief Set current time.
+ * @note Fractional part will be silently ignored. There is no possibility
+ * to set it on PLATFORM platform.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] timespec pointer to a @p RTCDateTime structure
+ *
+ * @notapi
+ */
+void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) {
+
+ (void)rtcp;
+ (void)timespec;
+}
+
+/**
+ * @brief Get current time.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[out] timespec pointer to a @p RTCDateTime structure
+ *
+ * @notapi
+ */
+void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) {
+
+ (void)rtcp;
+ (void)timespec;
+}
+
+#if (RTC_ALARMS > 0) || defined(__DOXYGEN__)
+/**
+ * @brief Set alarm time.
+ * @note Default value after BKP domain reset for both comparators is 0.
+ * @note Function does not performs any checks of alarm time validity.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure.
+ * @param[in] alarm alarm identifier. Can be 1 or 2.
+ * @param[in] alarmspec pointer to a @p RTCAlarm structure.
+ *
+ * @notapi
+ */
+void rtc_lld_set_alarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ const RTCAlarm *alarmspec) {
+
+ (void)rtcp;
+ (void)alarm;
+ (void)alarmspec;
+}
+
+/**
+ * @brief Get alarm time.
+ * @note The function can be called from any context.
+ *
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] alarm alarm identifier
+ * @param[out] alarmspec pointer to a @p RTCAlarm structure
+ *
+ * @notapi
+ */
+void rtc_lld_get_alarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ RTCAlarm *alarmspec) {
+
+ (void)rtcp;
+ (void)alarm;
+ (void)alarmspec;
+}
+#endif /* RTC_ALARMS > 0 */
+
+#endif /* HAL_USE_RTC */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_rtc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_rtc_lld.h
new file mode 100644
index 0000000000..02d250a5c1
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_rtc_lld.h
@@ -0,0 +1,182 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file hal_rtc_lld.h
+ * @brief PLATFORM RTC subsystem low level driver header.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#ifndef HAL_RTC_LLD_H
+#define HAL_RTC_LLD_H
+
+#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Implementation capabilities
+ */
+/**
+ * @brief Callback support int the driver.
+ */
+#define RTC_SUPPORTS_CALLBACKS TRUE
+
+/**
+ * @brief Number of alarms available.
+ */
+#define RTC_ALARMS 2
+
+/**
+ * @brief Presence of a local persistent storage.
+ */
+#define RTC_HAS_STORAGE FALSE
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name PLATFORM configuration options
+ * @{
+ */
+/**
+ * @brief RTCD1 driver enable switch.
+ * @details If set to @p TRUE the support for RTC1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(PLATFORM_RTC_USE_RTC1) || defined(__DOXYGEN__)
+#define PLATFORM_RTC_USE_RTC1 FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief FileStream specific methods.
+ */
+#define _rtc_driver_methods \
+ _file_stream_methods
+
+/**
+ * @brief Type of an RTC alarm number.
+ */
+typedef uint32_t rtcalarm_t;
+
+#if (RTC_SUPPORTS_CALLBACKS == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Type of an RTC event.
+ */
+typedef enum {
+ RTC_EVENT_SECOND = 0 /** Triggered every second. */
+} rtcevent_t;
+
+/**
+ * @brief Type of a generic RTC callback.
+ */
+typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event);
+#endif
+
+/**
+ * @brief Type of a structure representing an RTC alarm time stamp.
+ */
+typedef struct {
+ /* End of the mandatory fields.*/
+ uint32_t dummy;
+} RTCAlarm;
+
+#if (RTC_HAS_STORAGE == TRUE) || defined(__DOXYGEN__)
+/**
+ * @extends FileStream
+ *
+ * @brief @p RTCDriver virtual methods table.
+ */
+struct RTCDriverVMT {
+ _rtc_driver_methods
+};
+#endif
+
+/**
+ * @brief Structure representing an RTC driver.
+ */
+struct RTCDriver {
+#if (RTC_HAS_STORAGE == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Virtual Methods Table.
+ */
+ const struct RTCDriverVMT *vmt;
+#endif
+ /* End of the mandatory fields.*/
+ uint32_t dummy;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (PLATFORM_RTC_USE_RTC1 == TRUE) && !defined(__DOXYGEN__)
+extern RTCDriver RTCD1;
+#endif
+
+#if (RTC_HAS_STORAGE == TRUE) && !defined(__DOXYGEN__)
+extern struct RTCDriverVMT _rtc_lld_vmt;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void rtc_lld_init(void);
+ void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec);
+ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec);
+#if RTC_ALARMS > 0
+ void rtc_lld_set_alarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ const RTCAlarm *alarmspec);
+ void rtc_lld_get_alarm(RTCDriver *rtcp,
+ rtcalarm_t alarm,
+ RTCAlarm *alarmspec);
+#endif
+#if RTC_SUPPORTS_CALLBACKS == TRUE
+ void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_RTC == TRUE */
+
+#endif /* HAL_RTC_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/sdc_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_sdc_lld.c
similarity index 77%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/sdc_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_sdc_lld.c
index 21dda99eb9..3fc26fe188 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/sdc_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_sdc_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/sdc_lld.c
- * @brief SDC Driver subsystem low level driver source template.
+ * @file hal_sdc_lld.c
+ * @brief PLATFORM SDC subsystem low level driver source.
*
* @addtogroup SDC
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_SDC || defined(__DOXYGEN__)
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief SDCD1 driver identifier.
*/
-#if PLATFORM_SDC_USE_SDC1 || defined(__DOXYGEN__)
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
SDCDriver SDCD1;
#endif
@@ -65,7 +64,9 @@ SDCDriver SDCD1;
*/
void sdc_lld_init(void) {
+#if PLATFORM_SDC_USE_SDC1 == TRUE
sdcObjectInit(&SDCD1);
+#endif
}
/**
@@ -112,12 +113,14 @@ void sdc_lld_start_clk(SDCDriver *sdcp) {
* @brief Sets the SDIO clock to data mode (25MHz or less).
*
* @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] clk the clock mode
*
* @notapi
*/
-void sdc_lld_set_data_clk(SDCDriver *sdcp) {
+void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
(void)sdcp;
+ (void)clk;
}
/**
@@ -153,6 +156,9 @@ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
break;
case SDC_MODE_8BIT:
+ break;
+ default:
+ osalDbgAssert(false, "invalid bus mode");
break;
}
}
@@ -183,20 +189,20 @@ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
* @param[out] resp pointer to the response buffer (one word)
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp) {
+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
(void)sdcp;
(void)cmd;
(void)arg;
(void)resp;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -208,20 +214,20 @@ bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
* @param[out] resp pointer to the response buffer (one word)
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp) {
+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
(void)sdcp;
(void)cmd;
(void)arg;
(void)resp;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -233,20 +239,20 @@ bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
* @param[out] resp pointer to the response buffer (four words)
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp) {
+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
(void)sdcp;
(void)cmd;
(void)arg;
(void)resp;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -258,20 +264,20 @@ bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
* @param[in] n number of blocks to read
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
- uint8_t *buf, uint32_t n) {
+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n) {
(void)sdcp;
(void)startblk;
(void)buf;
(void)n;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -283,20 +289,20 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
* @param[in] n number of blocks to write
*
* @return The operation status.
- * @retval CH_SUCCESS operation succeeded.
- * @retval CH_FAILED operation failed.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
*
* @notapi
*/
-bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
- const uint8_t *buf, uint32_t n) {
+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n) {
(void)sdcp;
(void)startblk;
(void)buf;
(void)n;
- return CH_SUCCESS;
+ return HAL_SUCCESS;
}
/**
@@ -305,18 +311,18 @@ bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
* @param[in] sdcp pointer to the @p SDCDriver object
*
* @return The operation status.
- * @retval CH_SUCCESS the operation succeeded.
- * @retval CH_FAILED the operation failed.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
*
* @api
*/
-bool_t sdc_lld_sync(SDCDriver *sdcp) {
+bool sdc_lld_sync(SDCDriver *sdcp) {
(void)sdcp;
-
- return CH_SUCCESS;
+
+ return HAL_SUCCESS;
}
-#endif /* HAL_USE_SDC */
+#endif /* HAL_USE_SDC == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/sdc_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_sdc_lld.h
similarity index 64%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/sdc_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_sdc_lld.h
index da161ffc7f..e4f21a8f00 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/sdc_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_sdc_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/sdc_lld.h
- * @brief SDC Driver subsystem low level driver header template.
+ * @file hal_sdc_lld.h
+ * @brief PLATFORM SDC subsystem low level driver header.
*
* @addtogroup SDC
* @{
*/
-#ifndef _SDC_LLD_H_
-#define _SDC_LLD_H_
+#ifndef HAL_SDC_LLD_H
+#define HAL_SDC_LLD_H
-#if HAL_USE_SDC || defined(__DOXYGEN__)
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -36,15 +36,16 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
- * @brief SDC driver enable switch.
- * @details If set to @p TRUE the support for SDC1 is included.
+ * @brief PWMD1 driver enable switch.
+ * @details If set to @p TRUE the support for PWM1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__)
-#define PLATFORM_SDC_USE_SDC1 TRUE
+#define PLATFORM_SDC_USE_SDC1 FALSE
#endif
/** @} */
@@ -56,15 +57,6 @@
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type of SDIO bus mode.
- */
-typedef enum {
- SDC_MODE_1BIT = 0,
- SDC_MODE_4BIT,
- SDC_MODE_8BIT
-} sdcbusmode_t;
-
/**
* @brief Type of card flags.
*/
@@ -85,7 +77,19 @@ typedef struct SDCDriver SDCDriver;
* @note It could be empty on some architectures.
*/
typedef struct {
- uint32_t dummy;
+ /**
+ * @brief Working area for memory consuming operations.
+ * @note It is mandatory for detecting MMC cards bigger than 2GB else it
+ * can be @p NULL.
+ * @note Memory pointed by this buffer is only used by @p sdcConnect(),
+ * afterward it can be reused for other purposes.
+ */
+ uint8_t *scratchpad;
+ /**
+ * @brief Bus width.
+ */
+ sdcbusmode_t bus_width;
+ /* End of the mandatory fields.*/
} SDCConfig;
/**
@@ -135,37 +139,11 @@ struct SDCDriver {
/* Driver macros. */
/*===========================================================================*/
-/**
- * @name R1 response utilities
- * @{
- */
-/**
- * @brief Evaluates to @p TRUE if the R1 response contains error flags.
- *
- * @param[in] r1 the r1 response
- */
-#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0)
-
-/**
- * @brief Returns the status field of an R1 response.
- *
- * @param[in] r1 the r1 response
- */
-#define MMCSD_R1_STS(r1) (((r1) >> 9) & 15)
-
-/**
- * @brief Evaluates to @p TRUE if the R1 response indicates a locked card.
- *
- * @param[in] r1 the r1 response
- */
-#define MMCSD_R1_IS_CARD_LOCKED(r1) (((r1) >> 21) & 1)
-/** @} */
-
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_SDC_USE_SDC1 && !defined(__DOXYGEN__)
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) && !defined(__DOXYGEN__)
extern SDCDriver SDCD1;
#endif
@@ -176,29 +154,31 @@ extern "C" {
void sdc_lld_start(SDCDriver *sdcp);
void sdc_lld_stop(SDCDriver *sdcp);
void sdc_lld_start_clk(SDCDriver *sdcp);
- void sdc_lld_set_data_clk(SDCDriver *sdcp);
+ void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk);
void sdc_lld_stop_clk(SDCDriver *sdcp);
void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
- bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp);
- bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp);
- bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
- uint32_t *resp);
- bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
- uint8_t *buf, uint32_t n);
- bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
- const uint8_t *buf, uint32_t n);
- bool_t sdc_lld_sync(SDCDriver *sdcp);
- bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp);
- bool_t sdc_lld_is_write_protected(SDCDriver *sdcp);
+ bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument);
+ bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n);
+ bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n);
+ bool sdc_lld_sync(SDCDriver *sdcp);
+ bool sdc_lld_is_card_inserted(SDCDriver *sdcp);
+ bool sdc_lld_is_write_protected(SDCDriver *sdcp);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_SDC */
+#endif /* HAL_USE_SDC == TRUE */
-#endif /* _SDC_LLD_H_ */
+#endif /* HAL_SDC_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/serial_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_serial_lld.c
similarity index 81%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/serial_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_serial_lld.c
index 2eef6de9cc..30bd069407 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/serial_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_serial_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/serial_lld.c
- * @brief Serial Driver subsystem low level driver source template.
+ * @file hal_serial_lld.c
+ * @brief PLATFORM serial subsystem low level driver source.
*
* @addtogroup SERIAL
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -35,10 +34,8 @@
/* Driver exported variables. */
/*===========================================================================*/
-/**
- * @brief SD1 driver identifier.
- */
-#if PLATFORM_SERIAL_USE_SD1 || defined(__DOXYGEN__)
+/** @brief USART1 serial driver identifier.*/
+#if (PLATFORM_SERIAL_USE_USART1 == TRUE) || defined(__DOXYGEN__)
SerialDriver SD1;
#endif
@@ -72,10 +69,9 @@ static const SerialConfig default_config = {
*/
void sd_lld_init(void) {
-#if PLATFORM_SERIAL_USE_SD1
- /* Driver initialization.*/
- sdObjectInit(&SD1);
-#endif /* PLATFORM_SERIAL_USE_SD1 */
+#if PLATFORM_SERIAL_USE_USART1 == TRUE
+ sdObjectInit(&SD1, NULL, notify1);
+#endif
}
/**
@@ -90,19 +86,20 @@ void sd_lld_init(void) {
*/
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
- if (config == NULL)
+ if (config == NULL) {
config = &default_config;
+ }
+
if (sdp->state == SD_STOP) {
- /* Enables the peripheral.*/
-#if PLATFORM_SERIAL_USE_SD1
+#if PLATFORM_SERIAL_USE_USART1 == TRUE
if (&SD1 == sdp) {
}
-#endif /* PLATFORM_SD_USE_SD1 */
+#endif
}
/* Configures the peripheral.*/
-
+ (void)config; /* Warning suppression, remove this.*/
}
/**
@@ -117,17 +114,14 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) {
- /* Resets the peripheral.*/
-
- /* Disables the peripheral.*/
-#if PLATFORM_SERIAL_USE_SD1
+#if PLATFORM_SERIAL_USE_USART1 == TRUE
if (&SD1 == sdp) {
}
-#endif /* PLATFORM_SERIAL_USE_SD1 */
+#endif
}
}
-#endif /* HAL_USE_SERIAL */
+#endif /* HAL_USE_SERIAL == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/serial_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_serial_lld.h
similarity index 75%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/serial_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_serial_lld.h
index 675adaf8d7..55e1257433 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/serial_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_serial_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/serial_lld.h
- * @brief Serial Driver subsystem low level driver header template.
+ * @file hal_serial_lld.h
+ * @brief PLATFORM serial subsystem low level driver header.
*
* @addtogroup SERIAL
* @{
*/
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
+#ifndef HAL_SERIAL_LLD_H
+#define HAL_SERIAL_LLD_H
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -36,15 +36,16 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
- * @brief SD1 driver enable switch.
- * @details If set to @p TRUE the support for SD1 is included.
+ * @brief USART1 driver enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note The default is @p FALSE.
*/
-#if !defined(PLATFORM_SERIAL_USE_SD1) || defined(__DOXYGEN__)
-#define PLATFORM_SERIAL_USE_SD1 FALSE
+#if !defined(PLATFORM_SERIAL_USE_USART1) || defined(__DOXYGEN__)
+#define PLATFORM_SERIAL_USE_USART1 FALSE
#endif
/** @} */
@@ -57,31 +58,32 @@
/*===========================================================================*/
/**
- * @brief Generic Serial Driver configuration structure.
+ * @brief PLATFORM Serial Driver configuration structure.
* @details An instance of this structure must be passed to @p sdStart()
* in order to configure and start a serial driver operations.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
+ * @note This structure content is architecture dependent, each driver
+ * implementation defines its own version and the custom static
+ * initializers.
*/
typedef struct {
/**
* @brief Bit rate.
*/
- uint32_t sc_speed;
+ uint32_t speed;
/* End of the mandatory fields.*/
} SerialConfig;
/**
- * @brief @p SerialDriver specific data.
+ * @brief @p SerialDriver specific data.
*/
#define _serial_driver_data \
_base_asynchronous_channel_data \
/* Driver state.*/ \
sdstate_t state; \
/* Input queue.*/ \
- InputQueue iqueue; \
+ input_queue_t iqueue; \
/* Output queue.*/ \
- OutputQueue oqueue; \
+ output_queue_t oqueue; \
/* Input circular buffer.*/ \
uint8_t ib[SERIAL_BUFFERS_SIZE]; \
/* Output circular buffer.*/ \
@@ -96,7 +98,7 @@ typedef struct {
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_SERIAL_USE_SD1 && !defined(__DOXYGEN__)
+#if (PLATFORM_SERIAL_USE_USART1 == TRUE) && !defined(__DOXYGEN__)
extern SerialDriver SD1;
#endif
@@ -110,8 +112,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_SERIAL */
+#endif /* HAL_USE_SERIAL == TRUE */
-#endif /* _SERIAL_LLD_H_ */
+#endif /* HAL_SERIAL_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/spi_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_spi_lld.c
similarity index 92%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/spi_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_spi_lld.c
index 8f92cc7021..38cedb2860 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/spi_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_spi_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/spi_lld.c
- * @brief SPI Driver subsystem low level driver source template.
+ * @file hal_spi_lld.c
+ * @brief PLATFORM SPI subsystem low level driver source.
*
* @addtogroup SPI
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_SPI || defined(__DOXYGEN__)
+#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief SPI1 driver identifier.
*/
-#if PLATFORM_SPI_USE_SPI1 || defined(__DOXYGEN__)
+#if (PLATFORM_SPI_USE_SPI1 == TRUE) || defined(__DOXYGEN__)
SPIDriver SPID1;
#endif
@@ -65,10 +64,10 @@ SPIDriver SPID1;
*/
void spi_lld_init(void) {
-#if PLATFORM_SPI_USE_SPI1
+#if PLATFORM_SPI_USE_SPI1 == TRUE
/* Driver initialization.*/
spiObjectInit(&SPID1);
-#endif /* PLATFORM_SPI_USE_SPI1 */
+#endif
}
/**
@@ -82,11 +81,11 @@ void spi_lld_start(SPIDriver *spip) {
if (spip->state == SPI_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_SPI_USE_SPI1
+#if PLATFORM_SPI_USE_SPI1 == TRUE
if (&SPID1 == spip) {
}
-#endif /* PLATFORM_SPI_USE_SPI1 */
+#endif
}
/* Configures the peripheral.*/
@@ -102,14 +101,12 @@ void spi_lld_start(SPIDriver *spip) {
void spi_lld_stop(SPIDriver *spip) {
if (spip->state == SPI_READY) {
- /* Resets the peripheral.*/
-
/* Disables the peripheral.*/
-#if PLATFORM_SPI_USE_SPI1
+#if PLATFORM_SPI_USE_SPI1 == TRUE
if (&SPID1 == spip) {
}
-#endif /* PLATFORM_SPI_USE_SPI1 */
+#endif
}
}
@@ -245,6 +242,6 @@ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
return 0;
}
-#endif /* HAL_USE_SPI */
+#endif /* HAL_USE_SPI == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/spi_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_spi_lld.h
similarity index 79%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/spi_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_spi_lld.h
index 08e5915030..573aada6c5 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/spi_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_spi_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/spi_lld.h
- * @brief SPI Driver subsystem low level driver header template.
+ * @file hal_spi_lld.h
+ * @brief PLATFORM SPI subsystem low level driver header.
*
* @addtogroup SPI
* @{
*/
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
+#ifndef HAL_SPI_LLD_H
+#define HAL_SPI_LLD_H
-#if HAL_USE_SPI || defined(__DOXYGEN__)
+#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -36,15 +36,16 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
- * @brief SPI driver enable switch.
+ * @brief SPI1 driver enable switch.
* @details If set to @p TRUE the support for SPI1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define PLATFORM_SPI_USE_SPI1 FALSE
+#define PLATFORM_SPI_USE_SPI1 FALSE
#endif
/** @} */
@@ -76,9 +77,9 @@ typedef void (*spicallback_t)(SPIDriver *spip);
*/
typedef struct {
/**
- * @brief Operation complete callback.
+ * @brief Operation complete callback or @p NULL.
*/
- spicallback_t end_cb;
+ spicallback_t end_cb;
/* End of the mandatory fields.*/
} SPIConfig;
@@ -91,27 +92,23 @@ struct SPIDriver {
/**
* @brief Driver state.
*/
- spistate_t state;
+ spistate_t state;
/**
* @brief Current configuration data.
*/
- const SPIConfig *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
+ const SPIConfig *config;
+#if (SPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
/**
- * @brief Waiting thread.
+ * @brief Waiting thread.
*/
- Thread *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
+ thread_reference_t thread;
+#endif
+#if (SPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
/**
- * @brief Mutex protecting the bus.
+ * @brief Mutex protecting the peripheral.
*/
- Mutex mutex;
-#elif CH_USE_SEMAPHORES
- Semaphore semaphore;
+ mutex_t mutex;
#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
#if defined(SPI_DRIVER_EXT_FIELDS)
SPI_DRIVER_EXT_FIELDS
#endif
@@ -126,7 +123,7 @@ struct SPIDriver {
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_SPI_USE_SPI1 && !defined(__DOXYGEN__)
+#if (PLATFORM_SPI_USE_SPI1 == TRUE) && !defined(__DOXYGEN__)
extern SPIDriver SPID1;
#endif
@@ -148,8 +145,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_SPI */
+#endif /* HAL_USE_SPI == TRUE */
-#endif /* _SPI_LLD_H_ */
+#endif /* HAL_SPI_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_st_lld.c
similarity index 63%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_st_lld.c
index 50f2d9e49c..7558380292 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_st_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/xxx_lld.c
- * @brief XXX Driver subsystem low level driver source template.
+ * @file hal_st_lld.c
+ * @brief PLATFORM ST subsystem low level driver source.
*
- * @addtogroup XXX
+ * @addtogroup ST
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_XXX || defined(__DOXYGEN__)
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -35,13 +34,6 @@
/* Driver exported variables. */
/*===========================================================================*/
-/**
- * @brief XXX1 driver identifier.
- */
-#if PLATFORM_XXX_USE_XXX1 || defined(__DOXYGEN__)
-XXXDriver XXXD1;
-#endif
-
/*===========================================================================*/
/* Driver local types. */
/*===========================================================================*/
@@ -63,60 +55,13 @@ XXXDriver XXXD1;
/*===========================================================================*/
/**
- * @brief Low level XXX driver initialization.
- *
- * @notapi
- */
-void xxx_lld_init(void) {
-
-#if PLATFORM_XXX_USE_XXX1
- /* Driver initialization.*/
- xxxObjectInit(&XXXD1);
-#endif /* PLATFORM_XXX_USE_XXX1 */
-}
-
-/**
- * @brief Configures and activates the XXX peripheral.
- *
- * @param[in] xxxp pointer to the @p XXXDriver object
- *
- * @notapi
- */
-void xxx_lld_start(XXXDriver *xxxp) {
-
- if (xxxp->state == XXX_STOP) {
- /* Enables the peripheral.*/
-#if PLATFORM_XXX_USE_XXX1
- if (&XXXD1 == xxxp) {
-
- }
-#endif /* PLATFORM_XXX_USE_XXX1 */
- }
- /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief Deactivates the XXX peripheral.
- *
- * @param[in] xxxp pointer to the @p XXXDriver object
+ * @brief Low level ST driver initialization.
*
* @notapi
*/
-void xxx_lld_stop(XXXDriver *xxxp) {
-
- if (xxxp->state == XXX_READY) {
- /* Resets the peripheral.*/
-
- /* Disables the peripheral.*/
-#if PLATFORM_XXX_USE_XXX1
- if (&XXXD1 == xxxp) {
-
- }
-#endif /* PLATFORM_XXX_USE_XXX1 */
- }
+void st_lld_init(void) {
}
-#endif /* HAL_USE_XXX */
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_st_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_st_lld.h
new file mode 100644
index 0000000000..4ef97e8292
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_st_lld.h
@@ -0,0 +1,141 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_st_lld.h
+ * @brief PLATFORM ST subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef HAL_ST_LLD_H
+#define HAL_ST_LLD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the time counter value.
+ *
+ * @return The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] abstime the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t abstime) {
+
+ (void)abstime;
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] abstime the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t abstime) {
+
+ (void)abstime;
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+ return false;
+}
+
+#endif /* HAL_ST_LLD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/uart_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_uart_lld.c
similarity index 90%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/uart_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_uart_lld.c
index 89ade89e31..eabc199d2e 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/uart_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_uart_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/uart_lld.c
- * @brief UART Driver subsystem low level driver source template.
+ * @file hal_uart_lld.c
+ * @brief PLATFORM UART subsystem low level driver source.
*
* @addtogroup UART
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_UART || defined(__DOXYGEN__)
+#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief UART1 driver identifier.
*/
-#if PLATFORM_UART_USE_UART1 || defined(__DOXYGEN__)
+#if (PLATFORM_UART_USE_UART1 == TRUE) || defined(__DOXYGEN__)
UARTDriver UARTD1;
#endif
@@ -65,10 +64,10 @@ UARTDriver UARTD1;
*/
void uart_lld_init(void) {
-#if PLATFORM_UART_USE_UART1
+#if PLATFORM_UART_USE_UART1 == TRUE
/* Driver initialization.*/
uartObjectInit(&UARTD1);
-#endif /* PLATFORM_UART_USE_UART1 */
+#endif
}
/**
@@ -82,11 +81,11 @@ void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_UART_USE_UART1
+#if PLATFORM_UART_USE_UART1 == TRUE
if (&UARTD1 == uartp) {
}
-#endif /* PLATFORM_UART_USE_UART1 */
+#endif
}
/* Configures the peripheral.*/
@@ -105,11 +104,11 @@ void uart_lld_stop(UARTDriver *uartp) {
/* Resets the peripheral.*/
/* Disables the peripheral.*/
-#if PLATFORM_UART_USE_UART1
+#if PLATFORM_UART_USE_UART1 == TRUE
if (&UARTD1 == uartp) {
}
-#endif /* PLATFORM_UART_USE_UART1 */
+#endif
}
}
@@ -187,6 +186,6 @@ size_t uart_lld_stop_receive(UARTDriver *uartp) {
return 0;
}
-#endif /* HAL_USE_UART */
+#endif /* HAL_USE_UART == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/uart_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_uart_lld.h
similarity index 83%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/uart_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_uart_lld.h
index 330b855e87..fda02eff26 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/uart_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_uart_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/uart_lld.h
- * @brief UART Driver subsystem low level driver header template.
+ * @file hal_uart_lld.h
+ * @brief PLATFORM UART subsystem low level driver header.
*
* @addtogroup UART
* @{
*/
-#ifndef _UART_LLD_H_
-#define _UART_LLD_H_
+#ifndef HAL_UART_LLD_H
+#define HAL_UART_LLD_H
-#if HAL_USE_UART || defined(__DOXYGEN__)
+#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -36,12 +36,13 @@
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
* @brief UART driver enable switch.
* @details If set to @p TRUE the support for UART1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_UART_USE_UART1) || defined(__DOXYGEN__)
#define PLATFORM_UART_USE_UART1 FALSE
@@ -142,6 +143,26 @@ struct UARTDriver {
* @brief Current configuration data.
*/
const UARTConfig *config;
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Synchronization flag for transmit operations.
+ */
+ bool early;
+ /**
+ * @brief Waiting thread on RX.
+ */
+ thread_reference_t threadrx;
+ /**
+ * @brief Waiting thread on TX.
+ */
+ thread_reference_t threadtx;
+#endif /* UART_USE_WAIT */
+#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* UART_USE_MUTUAL_EXCLUSION */
#if defined(UART_DRIVER_EXT_FIELDS)
UART_DRIVER_EXT_FIELDS
#endif
@@ -156,7 +177,7 @@ struct UARTDriver {
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_UART_USE_UART1 && !defined(__DOXYGEN__)
+#if (PLATFORM_UART_USE_UART1 == TRUE) && !defined(__DOXYGEN__)
extern UARTDriver UARTD1;
#endif
@@ -174,8 +195,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_UART */
+#endif /* HAL_USE_UART == TRUE */
-#endif /* _UART_LLD_H_ */
+#endif /* HAL_UART_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/usb_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_usb_lld.c
similarity index 94%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/usb_lld.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_usb_lld.c
index d27fcff784..ae8bb2f2fa 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/usb_lld.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_usb_lld.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,16 @@
*/
/**
- * @file templates/usb_lld.c
- * @brief USB Driver subsystem low level driver source template.
+ * @file hal_usb_lld.c
+ * @brief PLATFORM USB subsystem low level driver source.
*
* @addtogroup USB
* @{
*/
-#include "ch.h"
#include "hal.h"
-#if HAL_USE_USB || defined(__DOXYGEN__)
+#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@@ -38,7 +37,7 @@
/**
* @brief USB1 driver identifier.
*/
-#if PLATFORM_USB_USE_USB1 || defined(__DOXYGEN__)
+#if (PLATFORM_USB_USE_USB1 == TRUE) || defined(__DOXYGEN__)
USBDriver USBD1;
#endif
@@ -99,10 +98,10 @@ static const USBEndpointConfig ep0config = {
*/
void usb_lld_init(void) {
-#if PLATFORM_USB_USE_USB1
+#if PLATFORM_USB_USE_USB1 == TRUE
/* Driver initialization.*/
usbObjectInit(&USBD1);
-#endif /* PLATFORM_USB_USE_USB1 */
+#endif
}
/**
@@ -116,11 +115,11 @@ void usb_lld_start(USBDriver *usbp) {
if (usbp->state == USB_STOP) {
/* Enables the peripheral.*/
-#if PLATFORM_USB_USE_USB1
+#if PLATFORM_USB_USE_USB1 == TRUE
if (&USBD1 == usbp) {
}
-#endif /* PLATFORM_USB_USE_USB1 */
+#endif
}
/* Configures the peripheral.*/
@@ -139,11 +138,11 @@ void usb_lld_stop(USBDriver *usbp) {
/* Resets the peripheral.*/
/* Disables the peripheral.*/
-#if PLATFORM_USB_USE_USB1
+#if PLATFORM_USB_USE_USB1 == TRUE
if (&USBD1 == usbp) {
}
-#endif /* PLATFORM_USB_USE_USB1 */
+#endif
}
}
@@ -386,6 +385,6 @@ void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
}
-#endif /* HAL_USE_USB */
+#endif /* HAL_USE_USB == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/usb_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_usb_lld.h
similarity index 84%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/usb_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_usb_lld.h
index 0f6c339f60..6b138da988 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/usb_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_usb_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/usb_lld.h
- * @brief USB Driver subsystem low level driver header template.
+ * @file hal_usb_lld.h
+ * @brief PLATFORM USB subsystem low level driver header.
*
* @addtogroup USB
* @{
*/
-#ifndef _USB_LLD_H_
-#define _USB_LLD_H_
+#ifndef HAL_USB_LLD_H
+#define HAL_USB_LLD_H
-#if HAL_USE_USB || defined(__DOXYGEN__)
+#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -36,25 +36,36 @@
*/
#define USB_MAX_ENDPOINTS 4
+/**
+ * @brief Status stage handling method.
+ */
+#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW
+
/**
* @brief The address can be changed immediately upon packet reception.
*/
-#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS
+#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS
+
+/**
+ * @brief Method for set address acknowledge.
+ */
+#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
- * @name Configuration options
+ * @name PLATFORM configuration options
* @{
*/
/**
* @brief USB driver enable switch.
* @details If set to @p TRUE the support for USB1 is included.
+ * @note The default is @p FALSE.
*/
#if !defined(PLATFORM_USB_USE_USB1) || defined(__DOXYGEN__)
-#define PLATFORM_USB_USE_USB1 FALSE
+#define PLATFORM_USB_USE_USB1 FALSE
#endif
/** @} */
@@ -70,10 +81,6 @@
* @brief Type of an IN endpoint state structure.
*/
typedef struct {
- /**
- * @brief Buffer mode, queue or linear.
- */
- bool_t txqueued;
/**
* @brief Requested transmit transfer size.
*/
@@ -82,30 +89,23 @@ typedef struct {
* @brief Transmitted bytes so far.
*/
size_t txcnt;
- union {
- struct {
- /**
- * @brief Pointer to the transmission linear buffer.
- */
- const uint8_t *txbuf;
- } linear;
- struct {
- /**
- * @brief Pointer to the output queue.
- */
- OutputQueue *txqueue;
- } queue;
- } mode;
+ /**
+ * @brief Pointer to the transmission linear buffer.
+ */
+ const uint8_t *txbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
} USBInEndpointState;
/**
* @brief Type of an OUT endpoint state structure.
*/
typedef struct {
- /**
- * @brief Buffer mode, queue or linear.
- */
- bool_t rxqueued;
/**
* @brief Requested receive transfer size.
*/
@@ -114,20 +114,17 @@ typedef struct {
* @brief Received bytes so far.
*/
size_t rxcnt;
- union {
- struct {
- /**
- * @brief Pointer to the receive linear buffer.
- */
- uint8_t *rxbuf;
- } linear;
- struct {
- /**
- * @brief Pointer to the input queue.
- */
- InputQueue *rxqueue;
- } queue;
- } mode;
+ /**
+ * @brief Pointer to the receive linear buffer.
+ */
+ uint8_t *rxbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
} USBOutEndpointState;
/**
@@ -284,6 +281,10 @@ struct USBDriver {
* @brief Current USB device configuration.
*/
uint8_t configuration;
+ /**
+ * @brief State of the driver when a suspend happened.
+ */
+ usbstate_t saved_state;
#if defined(USB_DRIVER_EXT_FIELDS)
USB_DRIVER_EXT_FIELDS
#endif
@@ -294,6 +295,16 @@ struct USBDriver {
/* Driver macros. */
/*===========================================================================*/
+/**
+ * @brief Returns the current frame number.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return The current frame number.
+ *
+ * @notapi
+ */
+#define usb_lld_get_frame_number(usbp) 0
+
/**
* @brief Returns the exact size of a receive transaction.
* @details The received size can be different from the size specified in
@@ -325,11 +336,18 @@ struct USBDriver {
*/
#define usb_lld_disconnect_bus(usbp)
+/**
+ * @brief Start of host wake-up procedure.
+ *
+ * @notapi
+ */
+#define usb_lld_wakeup_host(usbp)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_USB_USE_USB1 && !defined(__DOXYGEN__)
+#if (PLATFORM_USB_USE_USB1 == TRUE) && !defined(__DOXYGEN__)
extern USBDriver USBD1;
#endif
@@ -358,8 +376,8 @@ extern "C" {
}
#endif
-#endif /* HAL_USE_USB */
+#endif /* HAL_USE_USB == TRUE */
-#endif /* _USB_LLD_H_ */
+#endif /* HAL_USB_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_wdg_lld.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_wdg_lld.c
new file mode 100644
index 0000000000..1bf8c6e627
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_wdg_lld.c
@@ -0,0 +1,104 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_wdg_lld.c
+ * @brief WDG Driver subsystem low level driver source template.
+ *
+ * @addtogroup WDG
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+#if (PLATFORM_WDG_USE_WDG1 == TRUE) || defined(__DOXYGEN__)
+WDGDriver WDGD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level WDG driver initialization.
+ *
+ * @notapi
+ */
+void wdg_lld_init(void) {
+
+}
+
+/**
+ * @brief Configures and activates the WDG peripheral.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @notapi
+ */
+void wdg_lld_start(WDGDriver *wdgp) {
+
+ (void)wdgp;
+}
+
+/**
+ * @brief Deactivates the WDG peripheral.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @api
+ */
+void wdg_lld_stop(WDGDriver *wdgp) {
+
+ (void)wdgp;
+}
+
+/**
+ * @brief Reloads WDG's counter.
+ *
+ * @param[in] wdgp pointer to the @p WDGDriver object
+ *
+ * @notapi
+ */
+void wdg_lld_reset(WDGDriver * wdgp) {
+
+ (void)wdgp;
+}
+
+#endif /* HAL_USE_WDG */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver_lld.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_wdg_lld.h
similarity index 69%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver_lld.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_wdg_lld.h
index deaf592cb7..70a756a166 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/meta/driver_lld.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/hal_wdg_lld.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,17 +15,17 @@
*/
/**
- * @file templates/xxx_lld.h
- * @brief XXX Driver subsystem low level driver header template.
+ * @file hal_wdg_lld.h
+ * @brief WDG Driver subsystem low level driver header template.
*
- * @addtogroup XXX
+ * @addtogroup WDG
* @{
*/
-#ifndef _XXX_LLD_H_
-#define _XXX_LLD_H_
+#ifndef HAL_WDG_LLD_H
+#define HAL_WDG_LLD_H
-#if HAL_USE_XXX || defined(__DOXYGEN__)
+#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -40,11 +40,11 @@
* @{
*/
/**
- * @brief XXX driver enable switch.
- * @details If set to @p TRUE the support for XXX1 is included.
+ * @brief WDG1 driver enable switch.
+ * @note The default is @p FALSE.
*/
-#if !defined(PLATFORM_XXX_USE_XXX1) || defined(__DOXYGEN__)
-#define PLATFORM_XXX_USE_XXX1 FALSE
+#if !defined(PLATFORM_WDG_USE_WDG1) || defined(__DOXYGEN__)
+#define PLATFORM_WDG_USE_WDG1 FALSE
#endif
/** @} */
@@ -57,30 +57,29 @@
/*===========================================================================*/
/**
- * @brief Type of a structure representing an XXX driver.
+ * @brief Type of a structure representing an WDG driver.
*/
-typedef struct XXXDriver XXXDriver;
+typedef struct WDGDriver WDGDriver;
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
*/
typedef struct {
-
-} XXXConfig;
+} WDGConfig;
/**
- * @brief Structure representing an XXX driver.
+ * @brief Structure representing an WDG driver.
*/
-struct XXXDriver {
+struct WDGDriver {
/**
- * @brief Driver state.
+ * @brief Driver state.
*/
- xxxstate_t state;
+ wdgstate_t state;
/**
- * @brief Current configuration data.
+ * @brief Current configuration data.
*/
- const XXXConfig *config;
+ const WDGConfig *config;
/* End of the mandatory fields.*/
};
@@ -92,22 +91,23 @@ struct XXXDriver {
/* External declarations. */
/*===========================================================================*/
-#if PLATFORM_XXX_USE_XXX1 && !defined(__DOXYGEN__)
-extern XXXDriver XXXD1;
+#if (PLATFORM_WDG_USE_WDG1 == TRUE) && !defined(__DOXYGEN__)
+extern WDGDriver WDGD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
- void xxx_lld_init(void);
- void xxx_lld_start(XXXDriver *xxxp);
- void xxx_lld_stop(XXXDriver *xxxp);
+ void wdg_lld_init(void);
+ void wdg_lld_start(WDGDriver *wdgp);
+ void wdg_lld_stop(WDGDriver *wdgp);
+ void wdg_lld_reset(WDGDriver *wdgp);
#ifdef __cplusplus
}
#endif
-#endif /* HAL_USE_XXX */
+#endif /* HAL_USE_WDG == TRUE */
-#endif /* _XXX_LLD_H_ */
+#endif /* HAL_WDG_LLD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/halconf.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/halconf.h
index e936dd0dcd..b17918296d 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/halconf.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/halconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,21 +25,14 @@
* @{
*/
-#ifndef _HALCONF_H_
-#define _HALCONF_H_
+#ifndef HALCONF_H
+#define HALCONF_H
#include "mcuconf.h"
/**
* @name Drivers enable switches
*/
-/**
- * @brief Enables the TM subsystem.
- */
-#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
-#define HAL_USE_TM TRUE
-#endif
-
/**
* @brief Enables the PAL subsystem.
*/
@@ -61,6 +54,13 @@
#define HAL_USE_CAN TRUE
#endif
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
/**
* @brief Enables the EXT subsystem.
*/
@@ -82,6 +82,13 @@
#define HAL_USE_I2C TRUE
#endif
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S TRUE
+#endif
+
/**
* @brief Enables the ICU subsystem.
*/
@@ -110,11 +117,18 @@
#define HAL_USE_PWM TRUE
#endif
+/**
+ * @brief Enables the QSPI subsystem.
+ */
+#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
+#define HAL_USE_QSPI TRUE
+#endif
+
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
-#define HAL_USE_RTC FALSE
+#define HAL_USE_RTC TRUE
#endif
/**
@@ -158,6 +172,13 @@
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG TRUE
+#endif
/** @} */
/*===========================================================================*/
@@ -311,7 +332,7 @@
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
- * @note The default is 64 bytes for both the transmission and receive
+ * @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
@@ -330,11 +351,19 @@
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
- * @note The default is 64 bytes for both the transmission and receive
+ * @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define SERIAL_USB_BUFFERS_SIZE 64
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/** @} */
@@ -362,6 +391,46 @@
#endif
/** @} */
-#endif /* _HALCONF_H_ */
+/*===========================================================================*/
+/**
+ * @name UART driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name USB driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT TRUE
+#endif
+/** @} */
+
+#endif /* HALCONF_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mcuconf.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mcuconf.h
index d290c19486..4fc96794e0 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mcuconf.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/mcuconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,6 +14,9 @@
limitations under the License.
*/
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
/*
* Platform drivers configuration.
* The following settings override the default settings present in
@@ -23,3 +26,5 @@
*/
#define PLATFORM_MCUCONF
+
+#endif /* MCUCONF_H */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.c b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.c
new file mode 100644
index 0000000000..be86bbf4fc
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.c
@@ -0,0 +1,411 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.c
+ * @brief OSAL module code.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#include "osal.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief Pointer to a halt error message.
+ * @note The message is meant to be retrieved by the debugger after the
+ * system halt caused by an unexpected error.
+ */
+const char *osal_halt_msg;
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief OSAL module initialization.
+ *
+ * @api
+ */
+void osalInit(void) {
+
+}
+
+/**
+ * @brief System halt with error message.
+ *
+ * @param[in] reason the halt message pointer
+ *
+ * @api
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak, noreturn))
+#endif
+void osalSysHalt(const char *reason) {
+
+ osalSysDisable();
+ osal_halt_msg = reason;
+ while (true) {
+ }
+}
+
+/**
+ * @brief Polled delay.
+ * @note The real delay is always few cycles in excess of the specified
+ * value.
+ *
+ * @param[in] cycles number of cycles
+ *
+ * @xclass
+ */
+void osalSysPolledDelayX(rtcnt_t cycles) {
+
+ (void)cycles;
+}
+
+/**
+ * @brief System timer handler.
+ * @details The handler is used for scheduling and Virtual Timers management.
+ *
+ * @iclass
+ */
+void osalOsTimerHandlerI(void) {
+
+ osalDbgCheckClassI();
+}
+
+/**
+ * @brief Checks if a reschedule is required and performs it.
+ * @note I-Class functions invoked from thread context must not reschedule
+ * by themselves, an explicit reschedule using this function is
+ * required in this scenario.
+ * @note Not implemented in this simplified OSAL.
+ *
+ * @sclass
+ */
+void osalOsRescheduleS(void) {
+
+}
+
+/**
+ * @brief Current system time.
+ * @details Returns the number of system ticks since the @p osalInit()
+ * invocation.
+ * @note The counter can reach its maximum and then restart from zero.
+ * @note This function can be called from any context but its atomicity
+ * is not guaranteed on architectures whose word size is less than
+ * @p systime_t size.
+ *
+ * @return The system time in ticks.
+ *
+ * @xclass
+ */
+systime_t osalOsGetSystemTimeX(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @sclass
+ */
+void osalThreadSleepS(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @api
+ */
+void osalThreadSleep(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @return The wake up message.
+ *
+ * @sclass
+ */
+msg_t osalThreadSuspendS(thread_reference_t *trp) {
+
+ osalDbgCheck(trp != NULL);
+
+ return MSG_OK;
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The wake up message.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ *
+ * @sclass
+ */
+msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) {
+
+ osalDbgCheck(trp != NULL);
+
+ (void)timeout;
+
+ return MSG_OK;
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must not reschedule because it can be called from
+ * ISR context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadResumeI(thread_reference_t *trp, msg_t msg) {
+
+ osalDbgCheck(trp != NULL);
+
+ (void)msg;
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadResumeS(thread_reference_t *trp, msg_t msg) {
+
+ osalDbgCheck(trp != NULL);
+
+ (void)msg;
+}
+
+/**
+ * @brief Enqueues the caller thread.
+ * @details The caller thread is enqueued and put to sleep until it is
+ * dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The message from @p osalQueueWakeupOneI() or
+ * @p osalQueueWakeupAllI() functions.
+ * @retval MSG_TIMEOUT if the thread has not been dequeued within the
+ * specified timeout or if the function has been
+ * invoked with @p TIME_IMMEDIATE as timeout
+ * specification.
+ *
+ * @sclass
+ */
+msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) {
+
+ osalDbgCheck(tqp != NULL);
+
+ (void)timeout;
+
+ return MSG_OK;
+}
+
+/**
+ * @brief Dequeues and wakes up one thread from the queue, if any.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+
+ osalDbgCheck(tqp != NULL);
+
+ (void)msg;
+}
+
+/**
+ * @brief Dequeues and wakes up all threads from the queue.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+
+ (void)tqp;
+ (void)msg;
+}
+
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->flags |= flags;
+ if (esp->cb != NULL) {
+ esp->cb(esp);
+ }
+}
+
+/**
+ * @brief Add flags to an event source object.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] flags flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags) {
+
+ osalDbgCheck(esp != NULL);
+
+ osalSysLock();
+ osalEventBroadcastFlagsI(esp, flags);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Event callback setup.
+ * @note The callback is invoked from ISR context and can
+ * only invoke I-Class functions. The callback is meant
+ * to wakeup the task that will handle the event by
+ * calling @p osalEventGetAndClearFlagsI().
+ * @note This function is not part of the OSAL API and is provided
+ * exclusively as an example and for convenience.
+ *
+ * @param[in] esp pointer to the event flags object
+ * @param[in] cb pointer to the callback function
+ * @param[in] param parameter to be passed to the callback function
+ *
+ * @api
+ */
+void osalEventSetCallback(event_source_t *esp,
+ eventcallback_t cb,
+ void *param) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->cb = cb;
+ esp->param = param;
+}
+
+/**
+ * @brief Locks the specified mutex.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+void osalMutexLock(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 1;
+}
+
+/**
+ * @brief Unlocks the specified mutex.
+ * @note The HAL guarantees to release mutex in reverse lock order. The
+ * mutex being unlocked is guaranteed to be the last locked mutex
+ * by the invoking thread.
+ * The implementation can rely on this behavior and eventually
+ * ignore the @p mp parameter which is supplied in order to support
+ * those OSes not supporting a stack of the owned mutexes.
+ *
+ * @param[in,out] mp pointer to the @p mutex_t object
+ *
+ * @api
+ */
+void osalMutexUnlock(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 0;
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.h b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.h
new file mode 100644
index 0000000000..22545384f5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.h
@@ -0,0 +1,648 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file osal.h
+ * @brief OSAL module header.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#ifndef OSAL_H
+#define OSAL_H
+
+#include
+#include
+#include
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Common constants
+ * @{
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define OSAL_SUCCESS false
+#define OSAL_FAILED true
+/** @} */
+
+/**
+ * @name Messages
+ * @{
+ */
+#define MSG_OK (msg_t)0
+#define MSG_RESET (msg_t)-1
+#define MSG_TIMEOUT (msg_t)-2
+/** @} */
+
+
+/**
+ * @name Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE ((systime_t)0)
+#define TIME_INFINITE ((systime_t)-1)
+/** @} */
+
+/**
+ * @name Systick modes.
+ * @{
+ */
+#define OSAL_ST_MODE_NONE 0
+#define OSAL_ST_MODE_PERIODIC 1
+#define OSAL_ST_MODE_FREERUNNING 2
+/** @} */
+
+/**
+ * @name Systick parameters.
+ * @{
+ */
+/**
+ * @brief Size in bits of the @p systick_t type.
+ */
+#define OSAL_ST_RESOLUTION 32
+
+/**
+ * @brief Required systick frequency or resolution.
+ */
+#define OSAL_ST_FREQUENCY 1000
+
+/**
+ * @brief Systick mode required by the underlying OS.
+ */
+#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC
+/** @} */
+
+/**
+ * @name IRQ-related constants
+ * @{
+ */
+/**
+ * @brief Total priority levels.
+ * @brief Implementation not mandatory.
+ */
+#define OSAL_IRQ_PRIORITY_LEVELS 16U
+
+/**
+ * @brief Highest IRQ priority for HAL drivers.
+ * @brief Implementation not mandatory.
+ */
+#define OSAL_IRQ_MAXIMUM_PRIORITY 0U
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables OSAL assertions.
+ */
+#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define OSAL_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Enables OSAL functions parameters checks.
+ */
+#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define OSAL_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a system status word.
+ */
+typedef uint32_t syssts_t;
+
+/**
+ * @brief Type of a message.
+ */
+typedef int32_t msg_t;
+
+/**
+ * @brief Type of system time counter.
+ */
+typedef uint32_t systime_t;
+
+/**
+ * @brief Type of realtime counter.
+ */
+typedef uint32_t rtcnt_t;
+
+/**
+ * @brief Type of a thread reference.
+ */
+typedef void * thread_reference_t;
+
+/**
+ * @brief Type of an event flags object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+typedef struct event_source event_source_t;
+
+/**
+ * @brief Type of an event source callback.
+ * @note This type is not part of the OSAL API and is provided
+ * exclusively as an example and for convenience.
+ */
+typedef void (*eventcallback_t)(event_source_t *esp);
+
+/**
+ * @brief Type of an event flags mask.
+ */
+typedef uint32_t eventflags_t;
+
+/**
+ * @brief Events source object.
+ * @note The content of this structure is not part of the API and should
+ * not be relied upon. Implementers may define this structure in
+ * an entirely different way.
+ * @note Retrieval and clearing of the flags are not defined in this
+ * API and are implementation-dependent.
+ */
+struct event_source {
+ volatile eventflags_t flags; /**< @brief Stored event flags. */
+ eventcallback_t cb; /**< @brief Event source callback. */
+ void *param; /**< @brief User defined field. */
+};
+
+/**
+ * @brief Type of a mutex.
+ * @note If the OS does not support mutexes or there is no OS then them
+ * mechanism can be simulated.
+ */
+typedef uint32_t mutex_t;
+
+/**
+ * @brief Type of a thread queue.
+ * @details A thread queue is a queue of sleeping threads, queued threads
+ * can be dequeued one at time or all together.
+ * @note If the OSAL is implemented on a bare metal machine without RTOS
+ * then the queue can be implemented as a single thread reference.
+ */
+typedef struct {
+ thread_reference_t tr;
+} threads_queue_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name Debug related macros
+ * @{
+ */
+/**
+ * @brief Condition assertion.
+ * @details If the condition check fails then the OSAL panics with a
+ * message and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS
+ * switch is enabled.
+ * @note The remark string is not currently used except for putting a
+ * comment in the code about the assertion.
+ *
+ * @param[in] c the condition to be verified to be true
+ * @param[in] remark a remark string
+ *
+ * @api
+ */
+#define osalDbgAssert(c, remark) do { \
+ /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
+ if (OSAL_DBG_ENABLE_ASSERTS != FALSE) { \
+ if (!(c)) { \
+ /*lint -restore*/ \
+ osalSysHalt(__func__); \
+ } \
+ } \
+} while (false)
+
+
+/**
+ * @brief Function parameters check.
+ * @details If the condition check fails then the OSAL panics and halts.
+ * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch
+ * is enabled.
+ *
+ * @param[in] c the condition to be verified to be true
+ *
+ * @api
+ */
+#define osalDbgCheck(c) do { \
+ /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
+ if (OSAL_DBG_ENABLE_CHECKS != FALSE) { \
+ if (!(c)) { \
+ /*lint -restore*/ \
+ osalSysHalt(__func__); \
+ } \
+ } \
+} while (false)
+
+
+/**
+ * @brief I-Class state check.
+ * @note Implementation is optional.
+ */
+#define osalDbgCheckClassI()
+
+/**
+ * @brief S-Class state check.
+ * @note Implementation is optional.
+ */
+#define osalDbgCheckClassS()
+/** @} */
+
+/**
+ * @name IRQ service routines wrappers
+ * @{
+ */
+/**
+ * @brief Priority level verification macro.
+ */
+#define OSAL_IRQ_IS_VALID_PRIORITY(n) \
+ (((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS))
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers.
+ */
+#define OSAL_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers.
+ */
+#define OSAL_IRQ_EPILOGUE()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @details This macro hides the details of an ISR function declaration.
+ *
+ * @param[in] id a vector name as defined in @p vectors.s
+ */
+#define OSAL_IRQ_HANDLER(id) void id(void)
+/** @} */
+
+/**
+ * @name Time conversion utilities
+ * @{
+ */
+/**
+ * @brief Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec number of seconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_S2ST(sec) \
+ ((systime_t)((uint32_t)(sec) * (uint32_t)OSAL_ST_FREQUENCY))
+
+/**
+ * @brief Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec number of milliseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_MS2ST(msec) \
+ ((systime_t)((((((uint32_t)(msec)) * \
+ ((uint32_t)OSAL_ST_FREQUENCY)) - 1UL) / 1000UL) + 1UL))
+
+/**
+ * @brief Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec number of microseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_US2ST(usec) \
+ ((systime_t)((((((uint32_t)(usec)) * \
+ ((uint32_t)OSAL_ST_FREQUENCY)) - 1UL) / 1000000UL) + 1UL))
+/** @} */
+
+/**
+ * @name Time conversion utilities for the realtime counter
+ * @{
+ */
+/**
+ * @brief Seconds to realtime counter.
+ * @details Converts from seconds to realtime counter cycles.
+ * @note The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] sec number of seconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_S2RTC(freq, sec) ((freq) * (sec))
+
+/**
+ * @brief Milliseconds to realtime counter.
+ * @details Converts from milliseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next millisecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] msec number of milliseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec))
+
+/**
+ * @brief Microseconds to realtime counter.
+ * @details Converts from microseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next microsecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] usec number of microseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define OSAL_US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec))
+/** @} */
+
+/**
+ * @name Sleep macros using absolute time
+ * @{
+ */
+/**
+ * @brief Delays the invoking thread for the specified number of seconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] sec time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * milliseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] msec time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * microseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] usec time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+extern const char *osal_halt_msg;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void osalInit(void);
+ void osalSysHalt(const char *reason);
+ void osalSysPolledDelayX(rtcnt_t cycles);
+ void osalOsTimerHandlerI(void);
+ void osalOsRescheduleS(void);
+ systime_t osalOsGetSystemTimeX(void);
+ void osalThreadSleepS(systime_t time);
+ void osalThreadSleep(systime_t time);
+ msg_t osalThreadSuspendS(thread_reference_t *trp);
+ msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
+ void osalThreadResumeI(thread_reference_t *trp, msg_t msg);
+ void osalThreadResumeS(thread_reference_t *trp, msg_t msg);
+ msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout);
+ void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg);
+ void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg);
+ void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags);
+ void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags);
+ void osalEventSetCallback(event_source_t *esp,
+ eventcallback_t cb,
+ void *param);
+ void osalMutexLock(mutex_t *mp);
+ void osalMutexUnlock(mutex_t *mp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysDisable(void) {
+
+}
+
+/**
+ * @brief Enables interrupts globally.
+ *
+ * @special
+ */
+static inline void osalSysEnable(void) {
+
+}
+
+/**
+ * @brief Enters a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLock(void) {
+
+}
+
+/**
+ * @brief Leaves a critical zone from thread context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlock(void) {
+
+}
+
+/**
+ * @brief Enters a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLockFromISR(void) {
+
+}
+
+/**
+ * @brief Leaves a critical zone from ISR context.
+ * @note This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlockFromISR(void) {
+
+}
+
+/**
+ * @brief Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ * from any context. Because its flexibility it is less efficient
+ * than @p chSysLock() which is preferable when the calling context
+ * is known.
+ * @post The system is in a critical zone.
+ *
+ * @return The previous system status, the encoding of this
+ * status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+static inline syssts_t osalSysGetStatusAndLockX(void) {
+
+ return (syssts_t)0;
+}
+
+/**
+ * @brief Restores the specified execution status and leaves a critical zone.
+ * @note A call to @p chSchRescheduleS() is automatically performed
+ * if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts the system status to be restored.
+ *
+ * @xclass
+ */
+static inline void osalSysRestoreStatusX(syssts_t sts) {
+
+ (void)sts;
+}
+
+/**
+ * @brief Checks if the specified time is within the specified time window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ * @note This function can be called from any context.
+ *
+ * @param[in] time the time to be verified
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool osalOsIsTimeWithinX(systime_t time,
+ systime_t start,
+ systime_t end) {
+
+ return (bool)((time - start) < (end - start));
+}
+
+/**
+ * @brief Initializes a threads queue object.
+ *
+ * @param[out] tqp pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) {
+
+ osalDbgCheck(tqp != NULL);
+}
+
+/**
+ * @brief Initializes an event flags object.
+ *
+ * @param[out] esp pointer to the event flags object
+ *
+ * @init
+ */
+static inline void osalEventObjectInit(event_source_t *esp) {
+
+ osalDbgCheck(esp != NULL);
+
+ esp->flags = (eventflags_t)0;
+ esp->cb = NULL;
+ esp->param = NULL;
+}
+
+/**
+ * @brief Initializes s @p mutex_t object.
+ *
+ * @param[out] mp pointer to the @p mutex_t object
+ *
+ * @init
+ */
+static inline void osalMutexObjectInit(mutex_t *mp) {
+
+ osalDbgCheck(mp != NULL);
+
+ *mp = 0;
+}
+
+#endif /* OSAL_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.mk
new file mode 100644
index 0000000000..3cea5361ed
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/osal/osal.mk
@@ -0,0 +1,5 @@
+# OSAL files.
+OSALSRC += ${CHIBIOS}/os/hal/templates/osal/osal.c
+
+# Required include directories
+OSALINC += ${CHIBIOS}/os/hal/templates/osal
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/platform.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/platform.mk
index 1bd43182fc..9d5a95ceae 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/platform.mk
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/hal/templates/platform.mk
@@ -1,19 +1,89 @@
# List of all the template platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+PLATFORMSRC := ${CHIBIOS}/os/hal/templates/hal_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_st_lld.c
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_adc_lld.c
+endif
+ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_can_lld.c
+endif
+ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_dac_lld.c
+endif
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_ext_lld.c
+endif
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_gpt_lld.c
+endif
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_i2c_lld.c
+endif
+ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_i2s_lld.c
+endif
+ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_icu_lld.c
+endif
+ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_mac_lld.c
+endif
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_pal_lld.c
+endif
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_pwm_lld.c
+endif
+ifneq ($(findstring HAL_USE_QSPI TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_qspi_lld.c
+endif
+ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_rtc_lld.c
+endif
+ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_sdc_lld.c
+endif
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_serial_lld.c
+endif
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_spi_lld.c
+endif
+ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_uart_lld.c
+endif
+ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_usb_lld.c
+endif
+ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_wdg_lld.c
+endif
+else
PLATFORMSRC = ${CHIBIOS}/os/hal/templates/hal_lld.c \
- ${CHIBIOS}/os/hal/templates/adc_lld.c \
- ${CHIBIOS}/os/hal/templates/can_lld.c \
- ${CHIBIOS}/os/hal/templates/ext_lld.c \
- ${CHIBIOS}/os/hal/templates/gpt_lld.c \
- ${CHIBIOS}/os/hal/templates/i2c_lld.c \
- ${CHIBIOS}/os/hal/templates/icu_lld.c \
- ${CHIBIOS}/os/hal/templates/mac_lld.c \
- ${CHIBIOS}/os/hal/templates/pal_lld.c \
- ${CHIBIOS}/os/hal/templates/pwm_lld.c \
- ${CHIBIOS}/os/hal/templates/sdc_lld.c \
- ${CHIBIOS}/os/hal/templates/serial_lld.c \
- ${CHIBIOS}/os/hal/templates/spi_lld.c \
- ${CHIBIOS}/os/hal/templates/uart_lld.c \
- ${CHIBIOS}/os/hal/templates/usb_lld.c
+ ${CHIBIOS}/os/hal/templates/hal_adc_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_dac_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_ext_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_gpt_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_i2c_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_i2s_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_mac_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_qspi_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_rtc_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_sdc_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_st_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_uart_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_usb_lld.c \
+ ${CHIBIOS}/os/hal/templates/hal_wdg_lld.c
+endif
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/templates
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/ch.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/ch.h
deleted file mode 100644
index 77a30d1241..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/ch.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file ch.h
- * @brief ChibiOS/RT main include file.
- * @details This header includes all the required kernel headers so it is the
- * only kernel header you usually want to include in your application.
- *
- * @addtogroup kernel_info
- * @details Kernel related info.
- * @{
- */
-
-#ifndef _CH_H_
-#define _CH_H_
-
-/**
- * @brief ChibiOS/RT identification macro.
- */
-#define _CHIBIOS_RT_
-
-/**
- * @brief Kernel version string.
- */
-#define CH_KERNEL_VERSION "2.6.6"
-
-/**
- * @name Kernel version
- * @{
- */
-/**
- * @brief Kernel version major number.
- */
-#define CH_KERNEL_MAJOR 2
-
-/**
- * @brief Kernel version minor number.
- */
-#define CH_KERNEL_MINOR 6
-
-/**
- * @brief Kernel version patch number.
- */
-#define CH_KERNEL_PATCH 6
-/** @} */
-
-/**
- * @name Common constants
- */
-/**
- * @brief Generic 'false' boolean constant.
- */
-#if !defined(FALSE) || defined(__DOXYGEN__)
-#define FALSE 0
-#endif
-
-/**
- * @brief Generic 'true' boolean constant.
- */
-#if !defined(TRUE) || defined(__DOXYGEN__)
-#define TRUE (!FALSE)
-#endif
-
-/**
- * @brief Generic success constant.
- * @details This constant is functionally equivalent to @p FALSE but more
- * readable, it can be used as return value of all those functions
- * returning a @p bool_t as a status indicator.
- */
-#if !defined(CH_SUCCESS) || defined(__DOXYGEN__)
-#define CH_SUCCESS FALSE
-#endif
-
-/**
- * @brief Generic failure constant.
- * @details This constant is functionally equivalent to @p TRUE but more
- * readable, it can be used as return value of all those functions
- * returning a @p bool_t as a status indicator.
- */
-#if !defined(CH_FAILED) || defined(__DOXYGEN__)
-#define CH_FAILED TRUE
-#endif
-/** @} */
-
-#include "chconf.h"
-#include "chtypes.h"
-#include "chlists.h"
-#include "chcore.h"
-#include "chsys.h"
-#include "chvt.h"
-#include "chschd.h"
-#include "chsem.h"
-#include "chbsem.h"
-#include "chmtx.h"
-#include "chcond.h"
-#include "chevents.h"
-#include "chmsg.h"
-#include "chmboxes.h"
-#include "chmemcore.h"
-#include "chheap.h"
-#include "chmempools.h"
-#include "chthreads.h"
-#include "chdynamic.h"
-#include "chregistry.h"
-#include "chinline.h"
-#include "chqueues.h"
-#include "chstreams.h"
-#include "chfiles.h"
-#include "chdebug.h"
-
-#if !defined(__DOXYGEN__)
-extern WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE);
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _idle_thread(void *p);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CH_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chbsem.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chbsem.h
deleted file mode 100644
index 539d473ed5..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chbsem.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chbsem.h
- * @brief Binary semaphores structures and macros.
- *
- * @addtogroup binary_semaphores
- * @details Binary semaphores related APIs and services.
- *
- * Operation mode
- * Binary semaphores are implemented as a set of macros that use the
- * existing counting semaphores primitives. The difference between
- * counting and binary semaphores is that the counter of binary
- * semaphores is not allowed to grow above the value 1. Repeated
- * signal operation are ignored. A binary semaphore can thus have
- * only two defined states:
- * - Taken, when its counter has a value of zero or lower
- * than zero. A negative number represent the number of threads
- * queued on the binary semaphore.
- * - Not taken, when its counter has a value of one.
- * .
- * Binary semaphores are different from mutexes because there is no
- * the concept of ownership, a binary semaphore can be taken by a
- * thread and signaled by another thread or an interrupt handler,
- * mutexes can only be taken and released by the same thread. Another
- * difference is that binary semaphores, unlike mutexes, do not
- * implement the priority inheritance protocol.
- * In order to use the binary semaphores APIs the @p CH_USE_SEMAPHORES
- * option must be enabled in @p chconf.h.
- * @{
- */
-
-#ifndef _CHBSEM_H_
-#define _CHBSEM_H_
-
-#if CH_USE_SEMAPHORES || defined(__DOXYGEN__)
-
-/**
- * @extends Semaphore
- *
- * @brief Binary semaphore type.
- */
-typedef struct {
- Semaphore bs_sem;
-} BinarySemaphore;
-
-/**
- * @brief Data part of a static semaphore initializer.
- * @details This macro should be used when statically initializing a semaphore
- * that is part of a bigger structure.
- *
- * @param[in] name the name of the semaphore variable
- * @param[in] taken the semaphore initial state
- */
-#define _BSEMAPHORE_DATA(name, taken) \
- {_SEMAPHORE_DATA(name.bs_sem, ((taken) ? 0 : 1))}
-
-/**
- * @brief Static semaphore initializer.
- * @details Statically initialized semaphores require no explicit
- * initialization using @p chBSemInit().
- *
- * @param[in] name the name of the semaphore variable
- * @param[in] taken the semaphore initial state
- */
-#define BSEMAPHORE_DECL(name, taken) \
- BinarySemaphore name = _BSEMAPHORE_DATA(name, taken)
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Initializes a binary semaphore.
- *
- * @param[out] bsp pointer to a @p BinarySemaphore structure
- * @param[in] taken initial state of the binary semaphore:
- * - @a FALSE, the initial state is not taken.
- * - @a TRUE, the initial state is taken.
- * .
- *
- * @init
- */
-#define chBSemInit(bsp, taken) chSemInit(&(bsp)->bs_sem, (taken) ? 0 : 1)
-
-/**
- * @brief Wait operation on the binary semaphore.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- * @return A message specifying how the invoking thread has been
- * released from the semaphore.
- * @retval RDY_OK if the binary semaphore has been successfully taken.
- * @retval RDY_RESET if the binary semaphore has been reset using
- * @p bsemReset().
- *
- * @api
- */
-#define chBSemWait(bsp) chSemWait(&(bsp)->bs_sem)
-
-/**
- * @brief Wait operation on the binary semaphore.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- * @return A message specifying how the invoking thread has been
- * released from the semaphore.
- * @retval RDY_OK if the binary semaphore has been successfully taken.
- * @retval RDY_RESET if the binary semaphore has been reset using
- * @p bsemReset().
- *
- * @sclass
- */
-#define chBSemWaitS(bsp) chSemWaitS(&(bsp)->bs_sem)
-
-/**
- * @brief Wait operation on the binary semaphore.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return A message specifying how the invoking thread has been
- * released from the semaphore.
- * @retval RDY_OK if the binary semaphore has been successfully taken.
- * @retval RDY_RESET if the binary semaphore has been reset using
- * @p bsemReset().
- * @retval RDY_TIMEOUT if the binary semaphore has not been signaled or reset
- * within the specified timeout.
- *
- * @api
- */
-#define chBSemWaitTimeout(bsp, time) chSemWaitTimeout(&(bsp)->bs_sem, (time))
-
-/**
- * @brief Wait operation on the binary semaphore.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return A message specifying how the invoking thread has been
- * released from the semaphore.
- * @retval RDY_OK if the binary semaphore has been successfully taken.
- * @retval RDY_RESET if the binary semaphore has been reset using
- * @p bsemReset().
- * @retval RDY_TIMEOUT if the binary semaphore has not been signaled or reset
- * within the specified timeout.
- *
- * @sclass
- */
-#define chBSemWaitTimeoutS(bsp, time) chSemWaitTimeoutS(&(bsp)->bs_sem, (time))
-
-/**
- * @brief Reset operation on the binary semaphore.
- * @note The released threads can recognize they were waked up by a reset
- * rather than a signal because the @p bsemWait() will return
- * @p RDY_RESET instead of @p RDY_OK.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- * @param[in] taken new state of the binary semaphore
- * - @a FALSE, the new state is not taken.
- * - @a TRUE, the new state is taken.
- * .
- *
- * @api
- */
-#define chBSemReset(bsp, taken) chSemReset(&(bsp)->bs_sem, (taken) ? 0 : 1)
-
-/**
- * @brief Reset operation on the binary semaphore.
- * @note The released threads can recognize they were waked up by a reset
- * rather than a signal because the @p bsemWait() will return
- * @p RDY_RESET instead of @p RDY_OK.
- * @note This function does not reschedule.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- * @param[in] taken new state of the binary semaphore
- * - @a FALSE, the new state is not taken.
- * - @a TRUE, the new state is taken.
- * .
- *
- * @iclass
- */
-#define chBSemResetI(bsp, taken) chSemResetI(&(bsp)->bs_sem, (taken) ? 0 : 1)
-
-/**
- * @brief Performs a signal operation on a binary semaphore.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- *
- * @api
- */
-#define chBSemSignal(bsp) { \
- chSysLock(); \
- chBSemSignalI((bsp)); \
- chSchRescheduleS(); \
- chSysUnlock(); \
-}
-
-/**
- * @brief Performs a signal operation on a binary semaphore.
- * @note This function does not reschedule.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- *
- * @iclass
- */
-#define chBSemSignalI(bsp) { \
- if ((bsp)->bs_sem.s_cnt < 1) \
- chSemSignalI(&(bsp)->bs_sem); \
-}
-
-/**
- * @brief Returns the binary semaphore current state.
- *
- * @param[in] bsp pointer to a @p BinarySemaphore structure
- * @return The binary semaphore current state.
- * @retval FALSE if the binary semaphore is not taken.
- * @retval TRUE if the binary semaphore is taken.
- *
- * @iclass
- */
-#define chBSemGetStateI(bsp) ((bsp)->bs_sem.s_cnt > 0 ? FALSE : TRUE)
-/** @} */
-
-#endif /* CH_USE_SEMAPHORES */
-
-#endif /* _CHBSEM_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chcond.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chcond.h
deleted file mode 100644
index 5949b31187..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chcond.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-/*
- Concepts and parts of this file have been contributed by Leon Woestenberg.
- */
-
-/**
- * @file chcond.h
- * @brief Condition Variables macros and structures.
- *
- * @addtogroup condvars
- * @{
- */
-
-#ifndef _CHCOND_H_
-#define _CHCOND_H_
-
-#if CH_USE_CONDVARS || defined(__DOXYGEN__)
-
-/*
- * Module dependencies check.
- */
-#if !CH_USE_MUTEXES
-#error "CH_USE_CONDVARS requires CH_USE_MUTEXES"
-#endif
-
-/**
- * @brief CondVar structure.
- */
-typedef struct CondVar {
- ThreadsQueue c_queue; /**< @brief CondVar threads queue.*/
-} CondVar;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chCondInit(CondVar *cp);
- void chCondSignal(CondVar *cp);
- void chCondSignalI(CondVar *cp);
- void chCondBroadcast(CondVar *cp);
- void chCondBroadcastI(CondVar *cp);
- msg_t chCondWait(CondVar *cp);
- msg_t chCondWaitS(CondVar *cp);
-#if CH_USE_CONDVARS_TIMEOUT
- msg_t chCondWaitTimeout(CondVar *cp, systime_t time);
- msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @brief Data part of a static condition variable initializer.
- * @details This macro should be used when statically initializing a condition
- * variable that is part of a bigger structure.
- *
- * @param[in] name the name of the condition variable
- */
-#define _CONDVAR_DATA(name) {_THREADSQUEUE_DATA(name.c_queue)}
-
-/**
- * @brief Static condition variable initializer.
- * @details Statically initialized condition variables require no explicit
- * initialization using @p chCondInit().
- *
- * @param[in] name the name of the condition variable
- */
-#define CONDVAR_DECL(name) CondVar name = _CONDVAR_DATA(name)
-
-#endif /* CH_USE_CONDVARS */
-
-#endif /* _CHCOND_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chdebug.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chdebug.h
deleted file mode 100644
index 81daa04007..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chdebug.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chdebug.h
- * @brief Debug macros and structures.
- *
- * @addtogroup debug
- * @{
- */
-
-#ifndef _CHDEBUG_H_
-#define _CHDEBUG_H_
-
-#if CH_DBG_ENABLE_ASSERTS || CH_DBG_ENABLE_CHECKS || \
- CH_DBG_ENABLE_STACK_CHECK || CH_DBG_SYSTEM_STATE_CHECK
-#define CH_DBG_ENABLED TRUE
-#else
-#define CH_DBG_ENABLED FALSE
-#endif
-
-#define __QUOTE_THIS(p) #p
-
-/*===========================================================================*/
-/**
- * @name Debug related settings
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief Trace buffer entries.
- */
-#ifndef CH_TRACE_BUFFER_SIZE
-#define CH_TRACE_BUFFER_SIZE 64
-#endif
-
-/**
- * @brief Fill value for thread stack area in debug mode.
- */
-#ifndef CH_STACK_FILL_VALUE
-#define CH_STACK_FILL_VALUE 0x55
-#endif
-
-/**
- * @brief Fill value for thread area in debug mode.
- * @note The chosen default value is 0xFF in order to make evident which
- * thread fields were not initialized when inspecting the memory with
- * a debugger. A uninitialized field is not an error in itself but it
- * better to know it.
- */
-#ifndef CH_THREAD_FILL_VALUE
-#define CH_THREAD_FILL_VALUE 0xFF
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* System state checker related code and variables. */
-/*===========================================================================*/
-
-#if !CH_DBG_SYSTEM_STATE_CHECK
-#define dbg_enter_lock()
-#define dbg_leave_lock()
-#define dbg_check_disable()
-#define dbg_check_suspend()
-#define dbg_check_enable()
-#define dbg_check_lock()
-#define dbg_check_unlock()
-#define dbg_check_lock_from_isr()
-#define dbg_check_unlock_from_isr()
-#define dbg_check_enter_isr()
-#define dbg_check_leave_isr()
-#define chDbgCheckClassI()
-#define chDbgCheckClassS()
-#else
-#define dbg_enter_lock() (dbg_lock_cnt = 1)
-#define dbg_leave_lock() (dbg_lock_cnt = 0)
-#endif
-
-/*===========================================================================*/
-/* Trace related structures and macros. */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
-/**
- * @brief Trace buffer record.
- */
-typedef struct {
- systime_t se_time; /**< @brief Time of the switch event. */
- Thread *se_tp; /**< @brief Switched in thread. */
- void *se_wtobjp; /**< @brief Object where going to sleep.*/
- uint8_t se_state; /**< @brief Switched out thread state. */
-} ch_swc_event_t;
-
-/**
- * @brief Trace buffer header.
- */
-typedef struct {
- unsigned tb_size; /**< @brief Trace buffer size (entries).*/
- ch_swc_event_t *tb_ptr; /**< @brief Pointer to the buffer front.*/
- /** @brief Ring buffer.*/
- ch_swc_event_t tb_buffer[CH_TRACE_BUFFER_SIZE];
-} ch_trace_buffer_t;
-
-#if !defined(__DOXYGEN__)
-extern ch_trace_buffer_t dbg_trace_buffer;
-#endif
-
-#endif /* CH_DBG_ENABLE_TRACE */
-
-#if !CH_DBG_ENABLE_TRACE
-/* When the trace feature is disabled this function is replaced by an empty
- macro.*/
-#define dbg_trace(otp)
-#endif
-
-/*===========================================================================*/
-/* Parameters checking related macros. */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLE_CHECKS || defined(__DOXYGEN__)
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Function parameters check.
- * @details If the condition check fails then the kernel panics and halts.
- * @note The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch
- * is specified in @p chconf.h else the macro does nothing.
- *
- * @param[in] c the condition to be verified to be true
- * @param[in] func the undecorated function name
- *
- * @api
- */
-#if !defined(chDbgCheck)
-#define chDbgCheck(c, func) { \
- if (!(c)) \
- chDbgPanic(__QUOTE_THIS(func)"()"); \
-}
-#endif /* !defined(chDbgCheck) */
-/** @} */
-#else /* !CH_DBG_ENABLE_CHECKS */
-#define chDbgCheck(c, func) { \
- (void)(c), (void)__QUOTE_THIS(func)"()"; \
-}
-#endif /* !CH_DBG_ENABLE_CHECKS */
-
-/*===========================================================================*/
-/* Assertions related macros. */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLE_ASSERTS || defined(__DOXYGEN__)
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Condition assertion.
- * @details If the condition check fails then the kernel panics with the
- * specified message and halts.
- * @note The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch
- * is specified in @p chconf.h else the macro does nothing.
- * @note The convention for the message is the following:
- * @(), #@
- * @note The remark string is not currently used except for putting a
- * comment in the code about the assertion.
- *
- * @param[in] c the condition to be verified to be true
- * @param[in] m the text message
- * @param[in] r a remark string
- *
- * @api
- */
-#if !defined(chDbgAssert)
-#define chDbgAssert(c, m, r) { \
- if (!(c)) \
- chDbgPanic(m); \
-}
-#endif /* !defined(chDbgAssert) */
-/** @} */
-#else /* !CH_DBG_ENABLE_ASSERTS */
-#define chDbgAssert(c, m, r) {(void)(c);}
-#endif /* !CH_DBG_ENABLE_ASSERTS */
-
-/*===========================================================================*/
-/* Panic related macros. */
-/*===========================================================================*/
-
-#if !CH_DBG_ENABLED
-/* When the debug features are disabled this function is replaced by an empty
- macro.*/
-#define chDbgPanic(msg) {}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#if CH_DBG_SYSTEM_STATE_CHECK
- extern cnt_t dbg_isr_cnt;
- extern cnt_t dbg_lock_cnt;
- void dbg_check_disable(void);
- void dbg_check_suspend(void);
- void dbg_check_enable(void);
- void dbg_check_lock(void);
- void dbg_check_unlock(void);
- void dbg_check_lock_from_isr(void);
- void dbg_check_unlock_from_isr(void);
- void dbg_check_enter_isr(void);
- void dbg_check_leave_isr(void);
- void chDbgCheckClassI(void);
- void chDbgCheckClassS(void);
-#endif
-#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
- void _trace_init(void);
- void dbg_trace(Thread *otp);
-#endif
-#if CH_DBG_ENABLED
- extern const char *dbg_panic_msg;
- void chDbgPanic(const char *msg);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHDEBUG_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chdynamic.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chdynamic.h
deleted file mode 100644
index 1eeebe4893..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chdynamic.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chdynamic.h
- * @brief Dynamic threads macros and structures.
- *
- * @addtogroup dynamic_threads
- * @{
- */
-
-#ifndef _CHDYNAMIC_H_
-#define _CHDYNAMIC_H_
-
-#if CH_USE_DYNAMIC || defined(__DOXYGEN__)
-
-/*
- * Module dependencies check.
- */
-#if CH_USE_DYNAMIC && !CH_USE_WAITEXIT
-#error "CH_USE_DYNAMIC requires CH_USE_WAITEXIT"
-#endif
-#if CH_USE_DYNAMIC && !CH_USE_HEAP && !CH_USE_MEMPOOLS
-#error "CH_USE_DYNAMIC requires CH_USE_HEAP and/or CH_USE_MEMPOOLS"
-#endif
-
-/*
- * Dynamic threads APIs.
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
- Thread *chThdAddRef(Thread *tp);
- void chThdRelease(Thread *tp);
-#if CH_USE_HEAP
- Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size,
- tprio_t prio, tfunc_t pf, void *arg);
-#endif
-#if CH_USE_MEMPOOLS
- Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio,
- tfunc_t pf, void *arg);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_DYNAMIC */
-
-#endif /* _CHDYNAMIC_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chevents.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chevents.h
deleted file mode 100644
index 026351e6c5..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chevents.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-/*
- Concepts and parts of this file have been contributed by Scott (skute).
- */
-
-/**
- * @file chevents.h
- * @brief Events macros and structures.
- *
- * @addtogroup events
- * @{
- */
-
-#ifndef _CHEVENTS_H_
-#define _CHEVENTS_H_
-
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
-
-typedef struct EventListener EventListener;
-
-/**
- * @brief Event Listener structure.
- */
-struct EventListener {
- EventListener *el_next; /**< @brief Next Event Listener
- registered on the Event
- Source. */
- Thread *el_listener; /**< @brief Thread interested in the
- Event Source. */
- eventmask_t el_mask; /**< @brief Event flags mask associated
- by the thread to the Event
- Source. */
- flagsmask_t el_flags; /**< @brief Flags added to the listener
- by the event source. */
-};
-
-/**
- * @brief Event Source structure.
- */
-typedef struct EventSource {
- EventListener *es_next; /**< @brief First Event Listener
- registered on the Event
- Source. */
-} EventSource;
-
-/**
- * @brief Event Handler callback function.
- */
-typedef void (*evhandler_t)(eventid_t);
-
-/**
- * @brief Data part of a static event source initializer.
- * @details This macro should be used when statically initializing an event
- * source that is part of a bigger structure.
- * @param name the name of the event source variable
- */
-#define _EVENTSOURCE_DATA(name) {(void *)(&name)}
-
-/**
- * @brief Static event source initializer.
- * @details Statically initialized event sources require no explicit
- * initialization using @p chEvtInit().
- *
- * @param name the name of the event source variable
- */
-#define EVENTSOURCE_DECL(name) EventSource name = _EVENTSOURCE_DATA(name)
-
-/**
- * @brief All events allowed mask.
- */
-#define ALL_EVENTS ((eventmask_t)-1)
-
-/**
- * @brief Returns an event mask from an event identifier.
- */
-#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid)))
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Registers an Event Listener on an Event Source.
- * @note Multiple Event Listeners can use the same event identifier, the
- * listener will share the callback function.
- *
- * @param[in] esp pointer to the @p EventSource structure
- * @param[out] elp pointer to the @p EventListener structure
- * @param[in] eid numeric identifier assigned to the Event Listener. The
- * identifier is used as index for the event callback
- * function.
- * The value must range between zero and the size, in bit,
- * of the @p eventmask_t type minus one.
- *
- * @api
- */
-#define chEvtRegister(esp, elp, eid) \
- chEvtRegisterMask(esp, elp, EVENT_MASK(eid))
-
-/**
- * @brief Initializes an Event Source.
- * @note This function can be invoked before the kernel is initialized
- * because it just prepares a @p EventSource structure.
- *
- * @param[out] esp pointer to the @p EventSource structure
- *
- * @init
- */
-#define chEvtInit(esp) \
- ((esp)->es_next = (EventListener *)(void *)(esp))
-
-/**
- * @brief Verifies if there is at least one @p EventListener registered.
- *
- * @param[in] esp pointer to the @p EventSource structure
- *
- * @iclass
- */
-#define chEvtIsListeningI(esp) \
- ((void *)(esp) != (void *)(esp)->es_next)
-
-/**
- * @brief Signals all the Event Listeners registered on the specified Event
- * Source.
- *
- * @param[in] esp pointer to the @p EventSource structure
- *
- * @api
- */
-#define chEvtBroadcast(esp) chEvtBroadcastFlags(esp, 0)
-
-/**
- * @brief Signals all the Event Listeners registered on the specified Event
- * Source.
- * @post This function does not reschedule so a call to a rescheduling
- * function must be performed before unlocking the kernel. Note that
- * interrupt handlers always reschedule on exit so an explicit
- * reschedule must not be performed in ISRs.
- *
- * @param[in] esp pointer to the @p EventSource structure
- *
- * @iclass
- */
-#define chEvtBroadcastI(esp) chEvtBroadcastFlagsI(esp, 0)
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chEvtRegisterMask(EventSource *esp,
- EventListener *elp,
- eventmask_t mask);
- void chEvtUnregister(EventSource *esp, EventListener *elp);
- eventmask_t chEvtGetAndClearEvents(eventmask_t mask);
- eventmask_t chEvtAddEvents(eventmask_t mask);
- flagsmask_t chEvtGetAndClearFlags(EventListener *elp);
- flagsmask_t chEvtGetAndClearFlagsI(EventListener *elp);
- void chEvtSignal(Thread *tp, eventmask_t mask);
- void chEvtSignalI(Thread *tp, eventmask_t mask);
- void chEvtBroadcastFlags(EventSource *esp, flagsmask_t flags);
- void chEvtBroadcastFlagsI(EventSource *esp, flagsmask_t flags);
- void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask);
-#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT
- eventmask_t chEvtWaitOne(eventmask_t mask);
- eventmask_t chEvtWaitAny(eventmask_t mask);
- eventmask_t chEvtWaitAll(eventmask_t mask);
-#endif
-#if CH_USE_EVENTS_TIMEOUT
- eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time);
- eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time);
- eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#if !CH_OPTIMIZE_SPEED && CH_USE_EVENTS_TIMEOUT
-#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE)
-#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE)
-#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE)
-#endif
-
-#endif /* CH_USE_EVENTS */
-
-#endif /* _CHEVENTS_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chfiles.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chfiles.h
deleted file mode 100644
index cddcf27c93..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chfiles.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chfiles.h
- * @brief Data files.
- * @details This header defines abstract interfaces useful to access generic
- * data files in a standardized way.
- *
- * @addtogroup data_files
- * @details This module define an abstract interface for generic data files by
- * extending the @p BaseSequentialStream interface. Note that no code
- * is present, data files are just abstract interface-like structures,
- * you should look at the systems as to a set of abstract C++ classes
- * (even if written in C). This system has the advantage to make the
- * access to streams independent from the implementation logic.
- * The data files interface can be used as base class for high level
- * object types such as an API for a File System implementation.
- * @{
- */
-
-#ifndef _CHFILES_H_
-#define _CHFILES_H_
-
-/**
- * @brief No error return code.
- */
-#define FILE_OK 0
-
-/**
- * @brief Error code from the file stream methods.
- */
-#define FILE_ERROR 0xFFFFFFFFUL
-
-/**
- * @brief File offset type.
- */
-typedef uint32_t fileoffset_t;
-
-/**
- * @brief BaseFileStream specific methods.
- */
-#define _base_file_stream_methods \
- _base_sequential_stream_methods \
- /* File close method.*/ \
- uint32_t (*close)(void *instance); \
- /* Get last error code method.*/ \
- int (*geterror)(void *instance); \
- /* File get size method.*/ \
- fileoffset_t (*getsize)(void *instance); \
- /* File get current position method.*/ \
- fileoffset_t (*getposition)(void *instance); \
- /* File seek method.*/ \
- uint32_t (*lseek)(void *instance, fileoffset_t offset);
-
-/**
- * @brief @p BaseFileStream specific data.
- * @note It is empty because @p BaseFileStream is only an interface
- * without implementation.
- */
-#define _base_file_stream_data \
- _base_sequential_stream_data
-
-/**
- * @extends BaseSequentialStreamVMT
- *
- * @brief @p BaseFileStream virtual methods table.
- */
-struct BaseFileStreamVMT {
- _base_file_stream_methods
-};
-
-/**
- * @extends BaseSequentialStream
- *
- * @brief Base file stream class.
- * @details This class represents a generic file data stream.
- */
-typedef struct {
- /** @brief Virtual Methods Table.*/
- const struct BaseFileStreamVMT *vmt;
- _base_file_stream_data
-} BaseFileStream;
-
-/**
- * @name Macro Functions (BaseFileStream)
- * @{
- */
-/**
- * @brief Base file Stream close.
- * @details The function closes a file stream.
- *
- * @param[in] ip pointer to a @p BaseFileStream or derived class
- * @return The operation status.
- * @retval FILE_OK no error.
- * @retval FILE_ERROR operation failed.
- *
- * @api
- */
-#define chFileStreamClose(ip) ((ip)->vmt->close(ip))
-
-/**
- * @brief Returns an implementation dependent error code.
- *
- * @param[in] ip pointer to a @p BaseFileStream or derived class
- * @return Implementation dependent error code.
- *
- * @api
- */
-#define chFileStreamGetError(ip) ((ip)->vmt->geterror(ip))
-
-/**
- * @brief Returns the current file size.
- *
- * @param[in] ip pointer to a @p BaseFileStream or derived class
- * @return The file size.
- *
- * @api
- */
-#define chFileStreamGetSize(ip) ((ip)->vmt->getsize(ip))
-
-/**
- * @brief Returns the current file pointer position.
- *
- * @param[in] ip pointer to a @p BaseFileStream or derived class
- * @return The current position inside the file.
- *
- * @api
- */
-#define chFileStreamGetPosition(ip) ((ip)->vmt->getposition(ip))
-
-/**
- * @brief Moves the file current pointer to an absolute position.
- *
- * @param[in] ip pointer to a @p BaseFileStream or derived class
- * @param[in] offset new absolute position
- * @return The operation status.
- * @retval FILE_OK no error.
- * @retval FILE_ERROR operation failed.
- *
- * @api
- */
-#define chFileStreamSeek(ip, offset) ((ip)->vmt->lseek(ip, offset))
-/** @} */
-
-#endif /* _CHFILES_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chheap.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chheap.h
deleted file mode 100644
index 110b5aba10..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chheap.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chheap.h
- * @brief Heaps macros and structures.
- *
- * @addtogroup heaps
- * @{
- */
-
-#ifndef _CHHEAP_H_
-#define _CHHEAP_H_
-
-#if CH_USE_HEAP || defined(__DOXYGEN__)
-
-/*
- * Module dependencies check.
- */
-#if !CH_USE_MEMCORE && !CH_USE_MALLOC_HEAP
-#error "CH_USE_HEAP requires CH_USE_MEMCORE or CH_USE_MALLOC_HEAP"
-#endif
-
-#if !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "CH_USE_HEAP requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
-typedef struct memory_heap MemoryHeap;
-
-/**
- * @brief Memory heap block header.
- */
-union heap_header {
- stkalign_t align;
- struct {
- union {
- union heap_header *next; /**< @brief Next block in free list. */
- MemoryHeap *heap; /**< @brief Block owner heap. */
- } u; /**< @brief Overlapped fields. */
- size_t size; /**< @brief Size of the memory block. */
- } h;
-};
-
-/**
- * @brief Structure describing a memory heap.
- */
-struct memory_heap {
- memgetfunc_t h_provider; /**< @brief Memory blocks provider for
- this heap. */
- union heap_header h_free; /**< @brief Free blocks list header. */
-#if CH_USE_MUTEXES
- Mutex h_mtx; /**< @brief Heap access mutex. */
-#else
- Semaphore h_sem; /**< @brief Heap access semaphore. */
-#endif
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _heap_init(void);
-#if !CH_USE_MALLOC_HEAP
- void chHeapInit(MemoryHeap *heapp, void *buf, size_t size);
-#endif
- void *chHeapAlloc(MemoryHeap *heapp, size_t size);
- void chHeapFree(void *p);
- size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_HEAP */
-
-#endif /* _CHHEAP_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chinline.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chinline.h
deleted file mode 100644
index bd617672cf..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chinline.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chinline.h
- * @brief Kernel inlined functions.
- * @details In this file there are a set of inlined functions if the
- * @p CH_OPTIMIZE_SPEED is enabled.
- */
-
-#ifndef _CHINLINE_H_
-#define _CHINLINE_H_
-
-/* If the performance code path has been chosen then all the following
- functions are inlined into the various kernel modules.*/
-#if CH_OPTIMIZE_SPEED
-static INLINE void prio_insert(Thread *tp, ThreadsQueue *tqp) {
-
- Thread *cp = (Thread *)tqp;
- do {
- cp = cp->p_next;
- } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio));
- tp->p_next = cp;
- tp->p_prev = cp->p_prev;
- tp->p_prev->p_next = cp->p_prev = tp;
-}
-
-static INLINE void queue_insert(Thread *tp, ThreadsQueue *tqp) {
-
- tp->p_next = (Thread *)tqp;
- tp->p_prev = tqp->p_prev;
- tp->p_prev->p_next = tqp->p_prev = tp;
-}
-
-static INLINE Thread *fifo_remove(ThreadsQueue *tqp) {
- Thread *tp = tqp->p_next;
-
- (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp;
- return tp;
-}
-
-static INLINE Thread *lifo_remove(ThreadsQueue *tqp) {
- Thread *tp = tqp->p_prev;
-
- (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp;
- return tp;
-}
-
-static INLINE Thread *dequeue(Thread *tp) {
-
- tp->p_prev->p_next = tp->p_next;
- tp->p_next->p_prev = tp->p_prev;
- return tp;
-}
-
-static INLINE void list_insert(Thread *tp, ThreadsList *tlp) {
-
- tp->p_next = tlp->p_next;
- tlp->p_next = tp;
-}
-
-static INLINE Thread *list_remove(ThreadsList *tlp) {
-
- Thread *tp = tlp->p_next;
- tlp->p_next = tp->p_next;
- return tp;
-}
-#endif /* CH_OPTIMIZE_SPEED */
-
-#endif /* _CHINLINE_H_ */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chlists.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chlists.h
deleted file mode 100644
index 833a61e6e2..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chlists.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chlists.h
- * @brief Thread queues/lists macros and structures.
- * @note All the macros present in this module, while public, are not
- * an OS API and should not be directly used in the user applications
- * code.
- *
- * @addtogroup internals
- * @{
- */
-
-#ifndef _CHLISTS_H_
-#define _CHLISTS_H_
-
-typedef struct Thread Thread;
-
-/**
- * @brief Threads queue initialization.
- *
- * @notapi
- */
-#define queue_init(tqp) ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp));
-
-/**
- * @brief Threads list initialization.
- *
- * @notapi
- */
-#define list_init(tlp) ((tlp)->p_next = (Thread *)(tlp))
-
-/**
- * @brief Evaluates to @p TRUE if the specified threads queue or list is
- * empty.
- *
- * @notapi
- */
-#define isempty(p) ((p)->p_next == (Thread *)(p))
-
-/**
- * @brief Evaluates to @p TRUE if the specified threads queue or list is
- * not empty.
- *
- * @notapi
- */
-#define notempty(p) ((p)->p_next != (Thread *)(p))
-
-/**
- * @brief Data part of a static threads queue initializer.
- * @details This macro should be used when statically initializing a threads
- * queue that is part of a bigger structure.
- *
- * @param[in] name the name of the threads queue variable
- */
-#define _THREADSQUEUE_DATA(name) {(Thread *)&name, (Thread *)&name}
-
-/**
- * @brief Static threads queue initializer.
- * @details Statically initialized threads queues require no explicit
- * initialization using @p queue_init().
- *
- * @param[in] name the name of the threads queue variable
- */
-#define THREADSQUEUE_DECL(name) ThreadsQueue name = _THREADSQUEUE_DATA(name)
-
-/**
- * @extends ThreadsList
- *
- * @brief Generic threads bidirectional linked list header and element.
- */
-typedef struct {
- Thread *p_next; /**< First @p Thread in the queue, or
- @p ThreadQueue when empty. */
- Thread *p_prev; /**< Last @p Thread in the queue, or
- @p ThreadQueue when empty. */
-} ThreadsQueue;
-
-/**
- * @brief Generic threads single link list, it works like a stack.
- */
-typedef struct {
-
- Thread *p_next; /**< Last pushed @p Thread on the stack
- list, or pointer to itself if
- empty. */
-} ThreadsList;
-
-#if !CH_OPTIMIZE_SPEED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void prio_insert(Thread *tp, ThreadsQueue *tqp);
- void queue_insert(Thread *tp, ThreadsQueue *tqp);
- Thread *fifo_remove(ThreadsQueue *tqp);
- Thread *lifo_remove(ThreadsQueue *tqp);
- Thread *dequeue(Thread *tp);
- void list_insert(Thread *tp, ThreadsList *tlp);
- Thread *list_remove(ThreadsList *tlp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !CH_OPTIMIZE_SPEED */
-
-#endif /* _CHLISTS_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmboxes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmboxes.h
deleted file mode 100644
index 4245b12e37..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmboxes.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmboxes.h
- * @brief Mailboxes macros and structures.
- *
- * @addtogroup mailboxes
- * @{
- */
-
-#ifndef _CHMBOXES_H_
-#define _CHMBOXES_H_
-
-#if CH_USE_MAILBOXES || defined(__DOXYGEN__)
-
-/*
- * Module dependencies check.
- */
-#if !CH_USE_SEMAPHORES
-#error "CH_USE_MAILBOXES requires CH_USE_SEMAPHORES"
-#endif
-
-/**
- * @brief Structure representing a mailbox object.
- */
-typedef struct {
- msg_t *mb_buffer; /**< @brief Pointer to the mailbox
- buffer. */
- msg_t *mb_top; /**< @brief Pointer to the location
- after the buffer. */
- msg_t *mb_wrptr; /**< @brief Write pointer. */
- msg_t *mb_rdptr; /**< @brief Read pointer. */
- Semaphore mb_fullsem; /**< @brief Full counter
- @p Semaphore. */
- Semaphore mb_emptysem; /**< @brief Empty counter
- @p Semaphore. */
-} Mailbox;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n);
- void chMBReset(Mailbox *mbp);
- msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t timeout);
- msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t timeout);
- msg_t chMBPostI(Mailbox *mbp, msg_t msg);
- msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t timeout);
- msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t timeout);
- msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg);
- msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t timeout);
- msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t timeout);
- msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp);
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns the mailbox buffer size.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- *
- * @iclass
- */
-#define chMBSizeI(mbp) \
- ((mbp)->mb_top - (mbp)->mb_buffer)
-
-/**
- * @brief Returns the number of free message slots into a mailbox.
- * @note Can be invoked in any system state but if invoked out of a locked
- * state then the returned value may change after reading.
- * @note The returned value can be less than zero when there are waiting
- * threads on the internal semaphore.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @return The number of empty message slots.
- *
- * @iclass
- */
-#define chMBGetFreeCountI(mbp) chSemGetCounterI(&(mbp)->mb_emptysem)
-
-/**
- * @brief Returns the number of used message slots into a mailbox.
- * @note Can be invoked in any system state but if invoked out of a locked
- * state then the returned value may change after reading.
- * @note The returned value can be less than zero when there are waiting
- * threads on the internal semaphore.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @return The number of queued messages.
- *
- * @iclass
- */
-#define chMBGetUsedCountI(mbp) chSemGetCounterI(&(mbp)->mb_fullsem)
-
-/**
- * @brief Returns the next message in the queue without removing it.
- * @pre A message must be waiting in the queue for this function to work
- * or it would return garbage. The correct way to use this macro is
- * to use @p chMBGetFullCountI() and then use this macro, all within
- * a lock state.
- *
- * @iclass
- */
-#define chMBPeekI(mbp) (*(mbp)->mb_rdptr)
-/** @} */
-
-/**
- * @brief Data part of a static mailbox initializer.
- * @details This macro should be used when statically initializing a
- * mailbox that is part of a bigger structure.
- *
- * @param[in] name the name of the mailbox variable
- * @param[in] buffer pointer to the mailbox buffer area
- * @param[in] size size of the mailbox buffer area
- */
-#define _MAILBOX_DATA(name, buffer, size) { \
- (msg_t *)(buffer), \
- (msg_t *)(buffer) + size, \
- (msg_t *)(buffer), \
- (msg_t *)(buffer), \
- _SEMAPHORE_DATA(name.mb_fullsem, 0), \
- _SEMAPHORE_DATA(name.mb_emptysem, size), \
-}
-
-/**
- * @brief Static mailbox initializer.
- * @details Statically initialized mailboxes require no explicit
- * initialization using @p chMBInit().
- *
- * @param[in] name the name of the mailbox variable
- * @param[in] buffer pointer to the mailbox buffer area
- * @param[in] size size of the mailbox buffer area
- */
-#define MAILBOX_DECL(name, buffer, size) \
- Mailbox name = _MAILBOX_DATA(name, buffer, size)
-
-#endif /* CH_USE_MAILBOXES */
-
-#endif /* _CHMBOXES_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmemcore.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmemcore.h
deleted file mode 100644
index 66780fb5b6..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmemcore.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmemcore.h
- * @brief Core memory manager macros and structures.
- *
- * @addtogroup memcore
- * @{
- */
-
-#ifndef _CHMEMCORE_H_
-#define _CHMEMCORE_H_
-
-/**
- * @brief Memory get function.
- * @note This type must be assignment compatible with the @p chMemAlloc()
- * function.
- */
-typedef void *(*memgetfunc_t)(size_t size);
-
-/**
- * @name Alignment support macros
- */
-/**
- * @brief Alignment size constant.
- */
-#define MEM_ALIGN_SIZE sizeof(stkalign_t)
-
-/**
- * @brief Alignment mask constant.
- */
-#define MEM_ALIGN_MASK (MEM_ALIGN_SIZE - 1)
-
-/**
- * @brief Alignment helper macro.
- */
-#define MEM_ALIGN_PREV(p) ((size_t)(p) & ~MEM_ALIGN_MASK)
-
-/**
- * @brief Alignment helper macro.
- */
-#define MEM_ALIGN_NEXT(p) MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK)
-
-/**
- * @brief Returns whatever a pointer or memory size is aligned to
- * the type @p align_t.
- */
-#define MEM_IS_ALIGNED(p) (((size_t)(p) & MEM_ALIGN_MASK) == 0)
-/** @} */
-
-#if CH_USE_MEMCORE || defined(__DOXYGEN__)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _core_init(void);
- void *chCoreAlloc(size_t size);
- void *chCoreAllocI(size_t size);
- size_t chCoreStatus(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_MEMCORE */
-
-#endif /* _CHMEMCORE_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmempools.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmempools.h
deleted file mode 100644
index 0edc8d0ac2..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmempools.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmempools.h
- * @brief Memory Pools macros and structures.
- *
- * @addtogroup pools
- * @{
- */
-
-#ifndef _CHMEMPOOLS_H_
-#define _CHMEMPOOLS_H_
-
-#if CH_USE_MEMPOOLS || defined(__DOXYGEN__)
-
-/**
- * @brief Memory pool free object header.
- */
-struct pool_header {
- struct pool_header *ph_next; /**< @brief Pointer to the next pool
- header in the list. */
-};
-
-/**
- * @brief Memory pool descriptor.
- */
-typedef struct {
- struct pool_header *mp_next; /**< @brief Pointer to the header. */
- size_t mp_object_size; /**< @brief Memory pool objects
- size. */
- memgetfunc_t mp_provider; /**< @brief Memory blocks provider for
- this pool. */
-} MemoryPool;
-
-/**
- * @brief Data part of a static memory pool initializer.
- * @details This macro should be used when statically initializing a
- * memory pool that is part of a bigger structure.
- *
- * @param[in] name the name of the memory pool variable
- * @param[in] size size of the memory pool contained objects
- * @param[in] provider memory provider function for the memory pool
- */
-#define _MEMORYPOOL_DATA(name, size, provider) \
- {NULL, size, provider}
-
-/**
- * @brief Static memory pool initializer in hungry mode.
- * @details Statically initialized memory pools require no explicit
- * initialization using @p chPoolInit().
- *
- * @param[in] name the name of the memory pool variable
- * @param[in] size size of the memory pool contained objects
- * @param[in] provider memory provider function for the memory pool or @p NULL
- * if the pool is not allowed to grow automatically
- */
-#define MEMORYPOOL_DECL(name, size, provider) \
- MemoryPool name = _MEMORYPOOL_DATA(name, size, provider)
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Adds an object to a memory pool.
- * @pre The memory pool must be already been initialized.
- * @pre The added object must be of the right size for the specified
- * memory pool.
- * @pre The added object must be memory aligned to the size of
- * @p stkalign_t type.
- * @note This function is just an alias for @p chPoolFree() and has been
- * added for clarity.
- *
- * @param[in] mp pointer to a @p MemoryPool structure
- * @param[in] objp the pointer to the object to be added
- *
- * @api
- */
-#define chPoolAdd(mp, objp) chPoolFree(mp, objp)
-
-/**
- * @brief Adds an object to a memory pool.
- * @pre The memory pool must be already been initialized.
- * @pre The added object must be of the right size for the specified
- * memory pool.
- * @pre The added object must be memory aligned to the size of
- * @p stkalign_t type.
- * @note This function is just an alias for @p chPoolFree() and has been
- * added for clarity.
- *
- * @param[in] mp pointer to a @p MemoryPool structure
- * @param[in] objp the pointer to the object to be added
- *
- * @iclass
- */
-#define chPoolAddI(mp, objp) chPoolFreeI(mp, objp)
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider);
- void chPoolLoadArray(MemoryPool *mp, void *p, size_t n);
- void *chPoolAllocI(MemoryPool *mp);
- void *chPoolAlloc(MemoryPool *mp);
- void chPoolFreeI(MemoryPool *mp, void *objp);
- void chPoolFree(MemoryPool *mp, void *objp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_MEMPOOLS */
-
-#endif /* _CHMEMPOOLS_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmsg.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmsg.h
deleted file mode 100644
index 3e73db8fc2..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmsg.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmsg.h
- * @brief Messages macros and structures.
- *
- * @addtogroup messages
- * @{
- */
-
-#ifndef _CHMSG_H_
-#define _CHMSG_H_
-
-#if CH_USE_MESSAGES || defined(__DOXYGEN__)
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Evaluates to TRUE if the thread has pending messages.
- *
- * @iclass
- */
-#define chMsgIsPendingI(tp) \
- ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue)
-
-/**
- * @brief Returns the message carried by the specified thread.
- * @pre This function must be invoked immediately after exiting a call
- * to @p chMsgWait().
- *
- * @param[in] tp pointer to the thread
- * @return The message carried by the sender.
- *
- * @api
- */
-#define chMsgGet(tp) ((tp)->p_msg)
-
-/**
- * @brief Releases the thread waiting on top of the messages queue.
- * @pre Invoke this function only after a message has been received
- * using @p chMsgWait().
- *
- * @param[in] tp pointer to the thread
- * @param[in] msg message to be returned to the sender
- *
- * @sclass
- */
-#define chMsgReleaseS(tp, msg) chSchWakeupS(tp, msg)
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- msg_t chMsgSend(Thread *tp, msg_t msg);
- Thread * chMsgWait(void);
- void chMsgRelease(Thread *tp, msg_t msg);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_MESSAGES */
-
-#endif /* _CHMSG_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmtx.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmtx.h
deleted file mode 100644
index b4fcd97473..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chmtx.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmtx.h
- * @brief Mutexes macros and structures.
- *
- * @addtogroup mutexes
- * @{
- */
-
-#ifndef _CHMTX_H_
-#define _CHMTX_H_
-
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-
-/**
- * @brief Mutex structure.
- */
-typedef struct Mutex {
- ThreadsQueue m_queue; /**< @brief Queue of the threads sleeping
- on this Mutex. */
- Thread *m_owner; /**< @brief Owner @p Thread pointer or
- @p NULL. */
- struct Mutex *m_next; /**< @brief Next @p Mutex into an
- owner-list or @p NULL. */
-} Mutex;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chMtxInit(Mutex *mp);
- void chMtxLock(Mutex *mp);
- void chMtxLockS(Mutex *mp);
- bool_t chMtxTryLock(Mutex *mp);
- bool_t chMtxTryLockS(Mutex *mp);
- Mutex *chMtxUnlock(void);
- Mutex *chMtxUnlockS(void);
- void chMtxUnlockAll(void);
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @brief Data part of a static mutex initializer.
- * @details This macro should be used when statically initializing a mutex
- * that is part of a bigger structure.
- *
- * @param[in] name the name of the mutex variable
- */
-#define _MUTEX_DATA(name) {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL}
-
-/**
- * @brief Static mutex initializer.
- * @details Statically initialized mutexes require no explicit initialization
- * using @p chMtxInit().
- *
- * @param[in] name the name of the mutex variable
- */
-#define MUTEX_DECL(name) Mutex name = _MUTEX_DATA(name)
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns @p TRUE if the mutex queue contains at least a waiting
- * thread.
- *
- * @sclass
- */
-#define chMtxQueueNotEmptyS(mp) notempty(&(mp)->m_queue)
-/** @} */
-
-#endif /* CH_USE_MUTEXES */
-
-#endif /* _CHMTX_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chqueues.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chqueues.h
deleted file mode 100644
index b7ad17e2be..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chqueues.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chqueues.h
- * @brief I/O Queues macros and structures.
- *
- * @addtogroup io_queues
- * @{
- */
-
-#ifndef _CHQUEUES_H_
-#define _CHQUEUES_H_
-
-#if CH_USE_QUEUES || defined(__DOXYGEN__)
-
-/**
- * @name Queue functions returned status value
- * @{
- */
-#define Q_OK RDY_OK /**< @brief Operation successful. */
-#define Q_TIMEOUT RDY_TIMEOUT /**< @brief Timeout condition. */
-#define Q_RESET RDY_RESET /**< @brief Queue has been reset. */
-#define Q_EMPTY -3 /**< @brief Queue empty. */
-#define Q_FULL -4 /**< @brief Queue full, */
-/** @} */
-
-/**
- * @brief Type of a generic I/O queue structure.
- */
-typedef struct GenericQueue GenericQueue;
-
-/** @brief Queue notification callback type.*/
-typedef void (*qnotify_t)(GenericQueue *qp);
-
-/**
- * @brief Generic I/O queue structure.
- * @details This structure represents a generic Input or Output asymmetrical
- * queue. The queue is asymmetrical because one end is meant to be
- * accessed from a thread context, and thus can be blocking, the other
- * end is accessible from interrupt handlers or from within a kernel
- * lock zone (see I-Locked and S-Locked states in
- * @ref system_states) and is non-blocking.
- */
-struct GenericQueue {
- ThreadsQueue q_waiting; /**< @brief Queue of waiting threads. */
- size_t q_counter; /**< @brief Resources counter. */
- uint8_t *q_buffer; /**< @brief Pointer to the queue buffer.*/
- uint8_t *q_top; /**< @brief Pointer to the first location
- after the buffer. */
- uint8_t *q_wrptr; /**< @brief Write pointer. */
- uint8_t *q_rdptr; /**< @brief Read pointer. */
- qnotify_t q_notify; /**< @brief Data notification callback. */
- void *q_link; /**< @brief Application defined field. */
-};
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns the queue's buffer size.
- *
- * @param[in] qp pointer to a @p GenericQueue structure.
- * @return The buffer size.
- *
- * @iclass
- */
-#define chQSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer))
-
-/**
- * @brief Queue space.
- * @details Returns the used space if used on an input queue or the empty
- * space if used on an output queue.
- *
- * @param[in] qp pointer to a @p GenericQueue structure.
- * @return The buffer space.
- *
- * @iclass
- */
-#define chQSpaceI(qp) ((qp)->q_counter)
-
-/**
- * @brief Returns the queue application-defined link.
- * @note This function can be called in any context.
- *
- * @param[in] qp pointer to a @p GenericQueue structure.
- * @return The application-defined link.
- *
- * @special
- */
-#define chQGetLink(qp) ((qp)->q_link)
-/** @} */
-
-/**
- * @extends GenericQueue
- *
- * @brief Type of an input queue structure.
- * @details This structure represents a generic asymmetrical input queue.
- * Writing to the queue is non-blocking and can be performed from
- * interrupt handlers or from within a kernel lock zone (see
- * I-Locked and S-Locked states in @ref system_states).
- * Reading the queue can be a blocking operation and is supposed to
- * be performed by a system thread.
- */
-typedef GenericQueue InputQueue;
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns the filled space into an input queue.
- *
- * @param[in] iqp pointer to an @p InputQueue structure
- * @return The number of full bytes in the queue.
- * @retval 0 if the queue is empty.
- *
- * @iclass
- */
-#define chIQGetFullI(iqp) chQSpaceI(iqp)
-
-/**
- * @brief Returns the empty space into an input queue.
- *
- * @param[in] iqp pointer to an @p InputQueue structure
- * @return The number of empty bytes in the queue.
- * @retval 0 if the queue is full.
- *
- * @iclass
- */
-#define chIQGetEmptyI(iqp) (chQSizeI(iqp) - chQSpaceI(iqp))
-
-/**
- * @brief Evaluates to @p TRUE if the specified input queue is empty.
- *
- * @param[in] iqp pointer to an @p InputQueue structure.
- * @return The queue status.
- * @retval FALSE if the queue is not empty.
- * @retval TRUE if the queue is empty.
- *
- * @iclass
- */
-#define chIQIsEmptyI(iqp) ((bool_t)(chQSpaceI(iqp) <= 0))
-
-/**
- * @brief Evaluates to @p TRUE if the specified input queue is full.
- *
- * @param[in] iqp pointer to an @p InputQueue structure.
- * @return The queue status.
- * @retval FALSE if the queue is not full.
- * @retval TRUE if the queue is full.
- *
- * @iclass
- */
-#define chIQIsFullI(iqp) ((bool_t)(((iqp)->q_wrptr == (iqp)->q_rdptr) && \
- ((iqp)->q_counter != 0)))
-
-/**
- * @brief Input queue read.
- * @details This function reads a byte value from an input queue. If the queue
- * is empty then the calling thread is suspended until a byte arrives
- * in the queue.
- *
- * @param[in] iqp pointer to an @p InputQueue structure
- * @return A byte value from the queue.
- * @retval Q_RESET if the queue has been reset.
- *
- * @api
- */
-#define chIQGet(iqp) chIQGetTimeout(iqp, TIME_INFINITE)
-/** @} */
-
-/**
- * @brief Data part of a static input queue initializer.
- * @details This macro should be used when statically initializing an
- * input queue that is part of a bigger structure.
- *
- * @param[in] name the name of the input queue variable
- * @param[in] buffer pointer to the queue buffer area
- * @param[in] size size of the queue buffer area
- * @param[in] inotify input notification callback pointer
- * @param[in] link application defined pointer
- */
-#define _INPUTQUEUE_DATA(name, buffer, size, inotify, link) { \
- _THREADSQUEUE_DATA(name), \
- 0, \
- (uint8_t *)(buffer), \
- (uint8_t *)(buffer) + (size), \
- (uint8_t *)(buffer), \
- (uint8_t *)(buffer), \
- (inotify), \
- (link) \
-}
-
-/**
- * @brief Static input queue initializer.
- * @details Statically initialized input queues require no explicit
- * initialization using @p chIQInit().
- *
- * @param[in] name the name of the input queue variable
- * @param[in] buffer pointer to the queue buffer area
- * @param[in] size size of the queue buffer area
- * @param[in] inotify input notification callback pointer
- * @param[in] link application defined pointer
- */
-#define INPUTQUEUE_DECL(name, buffer, size, inotify, link) \
- InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link)
-
-/**
- * @extends GenericQueue
- *
- * @brief Type of an output queue structure.
- * @details This structure represents a generic asymmetrical output queue.
- * Reading from the queue is non-blocking and can be performed from
- * interrupt handlers or from within a kernel lock zone (see
- * I-Locked and S-Locked states in @ref system_states).
- * Writing the queue can be a blocking operation and is supposed to
- * be performed by a system thread.
- */
-typedef GenericQueue OutputQueue;
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns the filled space into an output queue.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure
- * @return The number of full bytes in the queue.
- * @retval 0 if the queue is empty.
- *
- * @iclass
- */
-#define chOQGetFullI(oqp) (chQSizeI(oqp) - chQSpaceI(oqp))
-
-/**
- * @brief Returns the empty space into an output queue.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure
- * @return The number of empty bytes in the queue.
- * @retval 0 if the queue is full.
- *
- * @iclass
- */
-#define chOQGetEmptyI(oqp) chQSpaceI(oqp)
-
-/**
- * @brief Evaluates to @p TRUE if the specified output queue is empty.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure.
- * @return The queue status.
- * @retval FALSE if the queue is not empty.
- * @retval TRUE if the queue is empty.
- *
- * @iclass
- */
-#define chOQIsEmptyI(oqp) ((bool_t)(((oqp)->q_wrptr == (oqp)->q_rdptr) && \
- ((oqp)->q_counter != 0)))
-
-/**
- * @brief Evaluates to @p TRUE if the specified output queue is full.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure.
- * @return The queue status.
- * @retval FALSE if the queue is not full.
- * @retval TRUE if the queue is full.
- *
- * @iclass
- */
-#define chOQIsFullI(oqp) ((bool_t)(chQSpaceI(oqp) <= 0))
-
-/**
- * @brief Output queue write.
- * @details This function writes a byte value to an output queue. If the queue
- * is full then the calling thread is suspended until there is space
- * in the queue.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure
- * @param[in] b the byte value to be written in the queue
- * @return The operation status.
- * @retval Q_OK if the operation succeeded.
- * @retval Q_RESET if the queue has been reset.
- *
- * @api
- */
-#define chOQPut(oqp, b) chOQPutTimeout(oqp, b, TIME_INFINITE)
- /** @} */
-
-/**
- * @brief Data part of a static output queue initializer.
- * @details This macro should be used when statically initializing an
- * output queue that is part of a bigger structure.
- *
- * @param[in] name the name of the output queue variable
- * @param[in] buffer pointer to the queue buffer area
- * @param[in] size size of the queue buffer area
- * @param[in] onotify output notification callback pointer
- * @param[in] link application defined pointer
- */
-#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) { \
- _THREADSQUEUE_DATA(name), \
- (size), \
- (uint8_t *)(buffer), \
- (uint8_t *)(buffer) + (size), \
- (uint8_t *)(buffer), \
- (uint8_t *)(buffer), \
- (onotify), \
- (link) \
-}
-
-/**
- * @brief Static output queue initializer.
- * @details Statically initialized output queues require no explicit
- * initialization using @p chOQInit().
- *
- * @param[in] name the name of the output queue variable
- * @param[in] buffer pointer to the queue buffer area
- * @param[in] size size of the queue buffer area
- * @param[in] onotify output notification callback pointer
- * @param[in] link application defined pointer
- */
-#define OUTPUTQUEUE_DECL(name, buffer, size, onotify, link) \
- OutputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy,
- void *link);
- void chIQResetI(InputQueue *iqp);
- msg_t chIQPutI(InputQueue *iqp, uint8_t b);
- msg_t chIQGetTimeout(InputQueue *iqp, systime_t time);
- size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp,
- size_t n, systime_t time);
-
- void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy,
- void *link);
- void chOQResetI(OutputQueue *oqp);
- msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time);
- msg_t chOQGetI(OutputQueue *oqp);
- size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp,
- size_t n, systime_t time);
-#ifdef __cplusplus
-}
-#endif
-#endif /* CH_USE_QUEUES */
-
-#endif /* _CHQUEUES_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chregistry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chregistry.h
deleted file mode 100644
index 0bd2fa760d..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chregistry.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chregistry.h
- * @brief Threads registry macros and structures.
- *
- * @addtogroup registry
- * @{
- */
-
-#ifndef _CHREGISTRY_H_
-#define _CHREGISTRY_H_
-
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-
-/**
- * @brief ChibiOS/RT memory signature record.
- */
-typedef struct {
- char ch_identifier[4]; /**< @brief Always set to "main". */
- uint8_t ch_zero; /**< @brief Must be zero. */
- uint8_t ch_size; /**< @brief Size of this structure. */
- uint16_t ch_version; /**< @brief Encoded ChibiOS/RT version. */
- uint8_t ch_ptrsize; /**< @brief Size of a pointer. */
- uint8_t ch_timesize; /**< @brief Size of a @p systime_t. */
- uint8_t ch_threadsize; /**< @brief Size of a @p Thread struct. */
- uint8_t cf_off_prio; /**< @brief Offset of @p p_prio field. */
- uint8_t cf_off_ctx; /**< @brief Offset of @p p_ctx field. */
- uint8_t cf_off_newer; /**< @brief Offset of @p p_newer field. */
- uint8_t cf_off_older; /**< @brief Offset of @p p_older field. */
- uint8_t cf_off_name; /**< @brief Offset of @p p_name field. */
- uint8_t cf_off_stklimit; /**< @brief Offset of @p p_stklimit
- field. */
- uint8_t cf_off_state; /**< @brief Offset of @p p_state field. */
- uint8_t cf_off_flags; /**< @brief Offset of @p p_flags field. */
- uint8_t cf_off_refs; /**< @brief Offset of @p p_refs field. */
- uint8_t cf_off_preempt; /**< @brief Offset of @p p_preempt
- field. */
- uint8_t cf_off_time; /**< @brief Offset of @p p_time field. */
-} chdebug_t;
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Sets the current thread name.
- * @pre This function only stores the pointer to the name if the option
- * @p CH_USE_REGISTRY is enabled else no action is performed.
- *
- * @param[in] p thread name as a zero terminated string
- *
- * @api
- */
-#define chRegSetThreadName(p) (currp->p_name = (p))
-
-/**
- * @brief Returns the name of the specified thread.
- * @pre This function only returns the pointer to the name if the option
- * @p CH_USE_REGISTRY is enabled else @p NULL is returned.
- *
- * @param[in] tp pointer to the thread
- *
- * @return Thread name as a zero terminated string.
- * @retval NULL if the thread name has not been set.
- */
-#define chRegGetThreadName(tp) ((tp)->p_name)
-/** @} */
-#else /* !CH_USE_REGISTRY */
-#define chRegSetThreadName(p)
-#define chRegGetThreadName(tp) NULL
-#endif /* !CH_USE_REGISTRY */
-
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-/**
- * @brief Removes a thread from the registry list.
- * @note This macro is not meant for use in application code.
- *
- * @param[in] tp thread to remove from the registry
- */
-#define REG_REMOVE(tp) { \
- (tp)->p_older->p_newer = (tp)->p_newer; \
- (tp)->p_newer->p_older = (tp)->p_older; \
-}
-
-/**
- * @brief Adds a thread to the registry list.
- * @note This macro is not meant for use in application code.
- *
- * @param[in] tp thread to add to the registry
- */
-#define REG_INSERT(tp) { \
- (tp)->p_newer = (Thread *)&rlist; \
- (tp)->p_older = rlist.r_older; \
- (tp)->p_older->p_newer = rlist.r_older = (tp); \
-}
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- extern ROMCONST chdebug_t ch_debug;
- Thread *chRegFirstThread(void);
- Thread *chRegNextThread(Thread *tp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_REGISTRY */
-
-#endif /* _CHREGISTRY_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chschd.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chschd.h
deleted file mode 100644
index 89a00f9eed..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chschd.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chschd.h
- * @brief Scheduler macros and structures.
- *
- * @addtogroup scheduler
- * @{
- */
-
-#ifndef _CHSCHD_H_
-#define _CHSCHD_H_
-
-/**
- * @name Wakeup status codes
- * @{
- */
-#define RDY_OK 0 /**< @brief Normal wakeup message. */
-#define RDY_TIMEOUT -1 /**< @brief Wakeup caused by a timeout
- condition. */
-#define RDY_RESET -2 /**< @brief Wakeup caused by a reset
- condition. */
-/** @} */
-
-/**
- * @name Priority constants
- * @{
- */
-#define NOPRIO 0 /**< @brief Ready list header priority. */
-#define IDLEPRIO 1 /**< @brief Idle thread priority. */
-#define LOWPRIO 2 /**< @brief Lowest user priority. */
-#define NORMALPRIO 64 /**< @brief Normal user priority. */
-#define HIGHPRIO 127 /**< @brief Highest user priority. */
-#define ABSPRIO 255 /**< @brief Greatest possible priority. */
-/** @} */
-
-/**
- * @name Special time constants
- * @{
- */
-/**
- * @brief Zero time specification for some functions with a timeout
- * specification.
- * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter,
- * see the specific function documentation.
- */
-#define TIME_IMMEDIATE ((systime_t)0)
-
-/**
- * @brief Infinite time specification for all functions with a timeout
- * specification.
- */
-#define TIME_INFINITE ((systime_t)-1)
-/** @} */
-
-/**
- * @brief Returns the priority of the first thread on the given ready list.
- *
- * @notapi
- */
-#define firstprio(rlp) ((rlp)->p_next->p_prio)
-
-/**
- * @extends ThreadsQueue
- *
- * @brief Ready list header.
- */
-#if !defined(PORT_OPTIMIZED_READYLIST_STRUCT) || defined(__DOXYGEN__)
-typedef struct {
- ThreadsQueue r_queue; /**< @brief Threads queue. */
- tprio_t r_prio; /**< @brief This field must be
- initialized to zero. */
- struct context r_ctx; /**< @brief Not used, present because
- offsets. */
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
- Thread *r_newer; /**< @brief Newer registry element. */
- Thread *r_older; /**< @brief Older registry element. */
-#endif
- /* End of the fields shared with the Thread structure.*/
- Thread *r_current; /**< @brief The currently running
- thread. */
-} ReadyList;
-#endif /* !defined(PORT_OPTIMIZED_READYLIST_STRUCT) */
-
-#if !defined(PORT_OPTIMIZED_RLIST_EXT) && !defined(__DOXYGEN__)
-extern ReadyList rlist;
-#endif /* !defined(PORT_OPTIMIZED_RLIST_EXT) */
-
-/**
- * @brief Current thread pointer access macro.
- * @note This macro is not meant to be used in the application code but
- * only from within the kernel, use the @p chThdSelf() API instead.
- * @note It is forbidden to use this macro in order to change the pointer
- * (currp = something), use @p setcurrp() instead.
- */
-#if !defined(PORT_OPTIMIZED_CURRP) || defined(__DOXYGEN__)
-#define currp rlist.r_current
-#endif /* !defined(PORT_OPTIMIZED_CURRP) */
-
-/**
- * @brief Current thread pointer change macro.
- * @note This macro is not meant to be used in the application code but
- * only from within the kernel.
- *
- * @notapi
- */
-#if !defined(PORT_OPTIMIZED_SETCURRP) || defined(__DOXYGEN__)
-#define setcurrp(tp) (currp = (tp))
-#endif /* !defined(PORT_OPTIMIZED_SETCURRP) */
-
-/*
- * Scheduler APIs.
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _scheduler_init(void);
-#if !defined(PORT_OPTIMIZED_READYI)
- Thread *chSchReadyI(Thread *tp);
-#endif
-#if !defined(PORT_OPTIMIZED_GOSLEEPS)
- void chSchGoSleepS(tstate_t newstate);
-#endif
-#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS)
- msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time);
-#endif
-#if !defined(PORT_OPTIMIZED_WAKEUPS)
- void chSchWakeupS(Thread *tp, msg_t msg);
-#endif
-#if !defined(PORT_OPTIMIZED_RESCHEDULES)
- void chSchRescheduleS(void);
-#endif
-#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED)
- bool_t chSchIsPreemptionRequired(void);
-#endif
-#if !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) || defined(__DOXYGEN__)
- void chSchDoRescheduleBehind(void);
-#endif
-#if !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) || defined(__DOXYGEN__)
- void chSchDoRescheduleAhead(void);
-#endif
-#if !defined(PORT_OPTIMIZED_DORESCHEDULE)
- void chSchDoReschedule(void);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Determines if the current thread must reschedule.
- * @details This function returns @p TRUE if there is a ready thread with
- * higher priority.
- *
- * @iclass
- */
-#if !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) || defined(__DOXYGEN__)
-#define chSchIsRescRequiredI() (firstprio(&rlist.r_queue) > currp->p_prio)
-#endif /* !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) */
-
-/**
- * @brief Determines if yielding is possible.
- * @details This function returns @p TRUE if there is a ready thread with
- * equal or higher priority.
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_CANYIELDS) || defined(__DOXYGEN__)
-#define chSchCanYieldS() (firstprio(&rlist.r_queue) >= currp->p_prio)
-#endif /* !defined(PORT_OPTIMIZED_CANYIELDS) */
-
-/**
- * @brief Yields the time slot.
- * @details Yields the CPU control to the next thread in the ready list with
- * equal or higher priority, if any.
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_DOYIELDS) || defined(__DOXYGEN__)
-#define chSchDoYieldS() { \
- if (chSchCanYieldS()) \
- chSchDoRescheduleBehind(); \
-}
-#endif /* !defined(PORT_OPTIMIZED_DOYIELDS) */
-
-/**
- * @brief Inline-able preemption code.
- * @details This is the common preemption code, this function must be invoked
- * exclusively from the port layer.
- *
- * @special
- */
-#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
-#define chSchPreemption() { \
- tprio_t p1 = firstprio(&rlist.r_queue); \
- tprio_t p2 = currp->p_prio; \
- if (currp->p_preempt) { \
- if (p1 > p2) \
- chSchDoRescheduleAhead(); \
- } \
- else { \
- if (p1 >= p2) \
- chSchDoRescheduleBehind(); \
- } \
-}
-#else /* CH_TIME_QUANTUM == 0 */
-#define chSchPreemption() { \
- if (p1 >= p2) \
- chSchDoRescheduleAhead(); \
-}
-#endif /* CH_TIME_QUANTUM == 0 */
-/** @} */
-
-#endif /* _CHSCHD_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chsem.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chsem.h
deleted file mode 100644
index d8de2c8cd8..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chsem.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chsem.h
- * @brief Semaphores macros and structures.
- *
- * @addtogroup semaphores
- * @{
- */
-
-#ifndef _CHSEM_H_
-#define _CHSEM_H_
-
-#if CH_USE_SEMAPHORES || defined(__DOXYGEN__)
-
-/**
- * @brief Semaphore structure.
- */
-typedef struct Semaphore {
- ThreadsQueue s_queue; /**< @brief Queue of the threads sleeping
- on this semaphore. */
- cnt_t s_cnt; /**< @brief The semaphore counter. */
-} Semaphore;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chSemInit(Semaphore *sp, cnt_t n);
- void chSemReset(Semaphore *sp, cnt_t n);
- void chSemResetI(Semaphore *sp, cnt_t n);
- msg_t chSemWait(Semaphore *sp);
- msg_t chSemWaitS(Semaphore *sp);
- msg_t chSemWaitTimeout(Semaphore *sp, systime_t time);
- msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time);
- void chSemSignal(Semaphore *sp);
- void chSemSignalI(Semaphore *sp);
- void chSemAddCounterI(Semaphore *sp, cnt_t n);
-#if CH_USE_SEMSW
- msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @brief Data part of a static semaphore initializer.
- * @details This macro should be used when statically initializing a semaphore
- * that is part of a bigger structure.
- *
- * @param[in] name the name of the semaphore variable
- * @param[in] n the counter initial value, this value must be
- * non-negative
- */
-#define _SEMAPHORE_DATA(name, n) {_THREADSQUEUE_DATA(name.s_queue), n}
-
-/**
- * @brief Static semaphore initializer.
- * @details Statically initialized semaphores require no explicit
- * initialization using @p chSemInit().
- *
- * @param[in] name the name of the semaphore variable
- * @param[in] n the counter initial value, this value must be
- * non-negative
- */
-#define SEMAPHORE_DECL(name, n) Semaphore name = _SEMAPHORE_DATA(name, n)
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Decreases the semaphore counter.
- * @details This macro can be used when the counter is known to be positive.
- *
- * @iclass
- */
-#define chSemFastWaitI(sp) ((sp)->s_cnt--)
-
-/**
- * @brief Increases the semaphore counter.
- * @details This macro can be used when the counter is known to be not
- * negative.
- *
- * @iclass
- */
-#define chSemFastSignalI(sp) ((sp)->s_cnt++)
-
-/**
- * @brief Returns the semaphore counter current value.
- *
- * @iclass
- */
-#define chSemGetCounterI(sp) ((sp)->s_cnt)
-/** @} */
-
-#endif /* CH_USE_SEMAPHORES */
-
-#endif /* _CHSEM_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chsys.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chsys.h
deleted file mode 100644
index e72a9a3ebe..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chsys.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chsys.h
- * @brief System related macros and structures.
- *
- * @addtogroup system
- * @{
- */
-
-#ifndef _CHSYS_H_
-#define _CHSYS_H_
-
-/**
- * @name Macro Functions
- * @{
- */
-#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__)
-/**
- * @brief Returns a pointer to the idle thread.
- * @pre In order to use this function the option @p CH_NO_IDLE_THREAD
- * must be disabled.
- * @note The reference counter of the idle thread is not incremented but
- * it is not strictly required being the idle thread a static
- * object.
- *
- * @return Pointer to the idle thread.
- *
- * @api
- */
-#define chSysGetIdleThread() (rlist.r_queue.p_prev)
-#endif
-
-/**
- * @brief Halts the system.
- * @details This function is invoked by the operating system when an
- * unrecoverable error is detected, for example because a programming
- * error in the application code that triggers an assertion while
- * in debug mode.
- * @note Can be invoked from any system state.
- *
- * @special
- */
-#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
-#define chSysHalt() port_halt()
-#else
-#define chSysHalt() { \
- SYSTEM_HALT_HOOK(); \
- port_halt(); \
-}
-#endif
-
-/**
- * @brief Performs a context switch.
- * @note Not a user function, it is meant to be invoked by the scheduler
- * itself or from within the port layer.
- *
- * @param[in] ntp the thread to be switched in
- * @param[in] otp the thread to be switched out
- *
- * @special
- */
-#define chSysSwitch(ntp, otp) { \
- dbg_trace(otp); \
- THREAD_CONTEXT_SWITCH_HOOK(ntp, otp); \
- port_switch(ntp, otp); \
-}
-
-/**
- * @brief Raises the system interrupt priority mask to the maximum level.
- * @details All the maskable interrupt sources are disabled regardless their
- * hardware priority.
- * @note Do not invoke this API from within a kernel lock.
- *
- * @special
- */
-#define chSysDisable() { \
- port_disable(); \
- dbg_check_disable(); \
-}
-
-/**
- * @brief Raises the system interrupt priority mask to system level.
- * @details The interrupt sources that should not be able to preempt the kernel
- * are disabled, interrupt sources with higher priority are still
- * enabled.
- * @note Do not invoke this API from within a kernel lock.
- * @note This API is no replacement for @p chSysLock(), the @p chSysLock()
- * could do more than just disable the interrupts.
- *
- * @special
- */
-#define chSysSuspend() { \
- port_suspend(); \
- dbg_check_suspend(); \
-}
-
-/**
- * @brief Lowers the system interrupt priority mask to user level.
- * @details All the interrupt sources are enabled.
- * @note Do not invoke this API from within a kernel lock.
- * @note This API is no replacement for @p chSysUnlock(), the
- * @p chSysUnlock() could do more than just enable the interrupts.
- *
- * @special
- */
-#define chSysEnable() { \
- dbg_check_enable(); \
- port_enable(); \
-}
-
-/**
- * @brief Enters the kernel lock mode.
- *
- * @special
- */
-#define chSysLock() { \
- port_lock(); \
- dbg_check_lock(); \
-}
-
-/**
- * @brief Leaves the kernel lock mode.
- *
- * @special
- */
-#define chSysUnlock() { \
- dbg_check_unlock(); \
- port_unlock(); \
-}
-
-/**
- * @brief Enters the kernel lock mode from within an interrupt handler.
- * @note This API may do nothing on some architectures, it is required
- * because on ports that support preemptable interrupt handlers
- * it is required to raise the interrupt mask to the same level of
- * the system mutual exclusion zone.
- * It is good practice to invoke this API before invoking any I-class
- * syscall from an interrupt handler.
- * @note This API must be invoked exclusively from interrupt handlers.
- *
- * @special
- */
-#define chSysLockFromIsr() { \
- port_lock_from_isr(); \
- dbg_check_lock_from_isr(); \
-}
-
-/**
- * @brief Leaves the kernel lock mode from within an interrupt handler.
- *
- * @note This API may do nothing on some architectures, it is required
- * because on ports that support preemptable interrupt handlers
- * it is required to raise the interrupt mask to the same level of
- * the system mutual exclusion zone.
- * It is good practice to invoke this API after invoking any I-class
- * syscall from an interrupt handler.
- * @note This API must be invoked exclusively from interrupt handlers.
- *
- * @special
- */
-#define chSysUnlockFromIsr() { \
- dbg_check_unlock_from_isr(); \
- port_unlock_from_isr(); \
-}
-/** @} */
-
-/**
- * @name ISRs abstraction macros
- */
-/**
- * @brief IRQ handler enter code.
- * @note Usually IRQ handlers functions are also declared naked.
- * @note On some architectures this macro can be empty.
- *
- * @special
- */
-#define CH_IRQ_PROLOGUE() \
- PORT_IRQ_PROLOGUE(); \
- dbg_check_enter_isr();
-
-/**
- * @brief IRQ handler exit code.
- * @note Usually IRQ handlers function are also declared naked.
- * @note This macro usually performs the final reschedule by using
- * @p chSchIsPreemptionRequired() and @p chSchDoReschedule().
- *
- * @special
- */
-#define CH_IRQ_EPILOGUE() \
- dbg_check_leave_isr(); \
- PORT_IRQ_EPILOGUE();
-
-/**
- * @brief Standard normal IRQ handler declaration.
- * @note @p id can be a function name or a vector number depending on the
- * port implementation.
- *
- * @special
- */
-#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id)
-/** @} */
-
-/**
- * @name Fast ISRs abstraction macros
- */
-/**
- * @brief Standard fast IRQ handler declaration.
- * @note @p id can be a function name or a vector number depending on the
- * port implementation.
- * @note Not all architectures support fast interrupts.
- *
- * @special
- */
-#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id)
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chSysInit(void);
- void chSysTimerHandlerI(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHSYS_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chthreads.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chthreads.h
deleted file mode 100644
index cc942bb53e..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chthreads.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chthreads.h
- * @brief Threads macros and structures.
- *
- * @addtogroup threads
- * @{
- */
-
-#ifndef _CHTHREADS_H_
-#define _CHTHREADS_H_
-
-/**
- * @name Thread states
- * @{
- */
-#define THD_STATE_READY 0 /**< @brief Waiting on the ready list. */
-#define THD_STATE_CURRENT 1 /**< @brief Currently running. */
-#define THD_STATE_SUSPENDED 2 /**< @brief Created in suspended state. */
-#define THD_STATE_WTSEM 3 /**< @brief Waiting on a semaphore. */
-#define THD_STATE_WTMTX 4 /**< @brief Waiting on a mutex. */
-#define THD_STATE_WTCOND 5 /**< @brief Waiting on a condition
- variable. */
-#define THD_STATE_SLEEPING 6 /**< @brief Waiting in @p chThdSleep()
- or @p chThdSleepUntil(). */
-#define THD_STATE_WTEXIT 7 /**< @brief Waiting in @p chThdWait(). */
-#define THD_STATE_WTOREVT 8 /**< @brief Waiting for an event. */
-#define THD_STATE_WTANDEVT 9 /**< @brief Waiting for several events. */
-#define THD_STATE_SNDMSGQ 10 /**< @brief Sending a message, in queue.*/
-#define THD_STATE_SNDMSG 11 /**< @brief Sent a message, waiting
- answer. */
-#define THD_STATE_WTMSG 12 /**< @brief Waiting for a message. */
-#define THD_STATE_WTQUEUE 13 /**< @brief Waiting on an I/O queue. */
-#define THD_STATE_FINAL 14 /**< @brief Thread terminated. */
-
-/**
- * @brief Thread states as array of strings.
- * @details Each element in an array initialized with this macro can be
- * indexed using the numeric thread state values.
- */
-#define THD_STATE_NAMES \
- "READY", "CURRENT", "SUSPENDED", "WTSEM", "WTMTX", "WTCOND", "SLEEPING", \
- "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "WTQUEUE", \
- "FINAL"
-/** @} */
-
-/**
- * @name Thread flags and attributes
- * @{
- */
-#define THD_MEM_MODE_MASK 3 /**< @brief Thread memory mode mask. */
-#define THD_MEM_MODE_STATIC 0 /**< @brief Static thread. */
-#define THD_MEM_MODE_HEAP 1 /**< @brief Thread allocated from a
- Memory Heap. */
-#define THD_MEM_MODE_MEMPOOL 2 /**< @brief Thread allocated from a
- Memory Pool. */
-#define THD_TERMINATE 4 /**< @brief Termination requested flag. */
-/** @} */
-
-/**
- * @extends ThreadsQueue
- *
- * @brief Structure representing a thread.
- * @note Not all the listed fields are always needed, by switching off some
- * not needed ChibiOS/RT subsystems it is possible to save RAM space
- * by shrinking the @p Thread structure.
- */
-struct Thread {
- Thread *p_next; /**< @brief Next in the list/queue. */
- /* End of the fields shared with the ThreadsList structure. */
- Thread *p_prev; /**< @brief Previous in the queue. */
- /* End of the fields shared with the ThreadsQueue structure. */
- tprio_t p_prio; /**< @brief Thread priority. */
- struct context p_ctx; /**< @brief Processor context. */
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
- Thread *p_newer; /**< @brief Newer registry element. */
- Thread *p_older; /**< @brief Older registry element. */
-#endif
- /* End of the fields shared with the ReadyList structure. */
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
- /**
- * @brief Thread name or @p NULL.
- */
- const char *p_name;
-#endif
-#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
- /**
- * @brief Thread stack boundary.
- */
- stkalign_t *p_stklimit;
-#endif
- /**
- * @brief Current thread state.
- */
- tstate_t p_state;
- /**
- * @brief Various thread flags.
- */
- tmode_t p_flags;
-#if CH_USE_DYNAMIC || defined(__DOXYGEN__)
- /**
- * @brief References to this thread.
- */
- trefs_t p_refs;
-#endif
- /**
- * @brief Number of ticks remaining to this thread.
- */
-#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
- tslices_t p_preempt;
-#endif
-#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__)
- /**
- * @brief Thread consumed time in ticks.
- * @note This field can overflow.
- */
- volatile systime_t p_time;
-#endif
- /**
- * @brief State-specific fields.
- * @note All the fields declared in this union are only valid in the
- * specified state or condition and are thus volatile.
- */
- union {
- /**
- * @brief Thread wakeup code.
- * @note This field contains the low level message sent to the thread
- * by the waking thread or interrupt handler. The value is valid
- * after exiting the @p chSchWakeupS() function.
- */
- msg_t rdymsg;
- /**
- * @brief Thread exit code.
- * @note The thread termination code is stored in this field in order
- * to be retrieved by the thread performing a @p chThdWait() on
- * this thread.
- */
- msg_t exitcode;
- /**
- * @brief Pointer to a generic "wait" object.
- * @note This field is used to get a generic pointer to a synchronization
- * object and is valid when the thread is in one of the wait
- * states.
- */
- void *wtobjp;
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
- /**
- * @brief Enabled events mask.
- * @note This field is only valid while the thread is in the
- * @p THD_STATE_WTOREVT or @p THD_STATE_WTANDEVT states.
- */
- eventmask_t ewmask;
-#endif
- } p_u;
-#if CH_USE_WAITEXIT || defined(__DOXYGEN__)
- /**
- * @brief Termination waiting list.
- */
- ThreadsList p_waiting;
-#endif
-#if CH_USE_MESSAGES || defined(__DOXYGEN__)
- /**
- * @brief Messages queue.
- */
- ThreadsQueue p_msgqueue;
- /**
- * @brief Thread message.
- */
- msg_t p_msg;
-#endif
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
- /**
- * @brief Pending events mask.
- */
- eventmask_t p_epending;
-#endif
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief List of the mutexes owned by this thread.
- * @note The list is terminated by a @p NULL in this field.
- */
- Mutex *p_mtxlist;
- /**
- * @brief Thread's own, non-inherited, priority.
- */
- tprio_t p_realprio;
-#endif
-#if (CH_USE_DYNAMIC && CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
- /**
- * @brief Memory Pool where the thread workspace is returned.
- */
- void *p_mpool;
-#endif
-#if defined(THREAD_EXT_FIELDS)
- /* Extra fields defined in chconf.h.*/
- THREAD_EXT_FIELDS
-#endif
-};
-
-/**
- * @brief Thread function.
- */
-typedef msg_t (*tfunc_t)(void *);
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns a pointer to the current @p Thread.
- * @note Can be invoked in any context.
- *
- * @special
- */
-#define chThdSelf() currp
-
-/**
- * @brief Returns the current thread priority.
- * @note Can be invoked in any context.
- *
- * @special
- */
-#define chThdGetPriority() (currp->p_prio)
-
-/**
- * @brief Returns the number of ticks consumed by the specified thread.
- * @note This function is only available when the
- * @p CH_DBG_THREADS_PROFILING configuration option is enabled.
- * @note Can be invoked in any context.
- *
- * @param[in] tp pointer to the thread
- *
- * @special
- */
-#define chThdGetTicks(tp) ((tp)->p_time)
-
-/**
- * @brief Returns the pointer to the @p Thread local storage area, if any.
- * @note Can be invoked in any context.
- *
- * @special
- */
-#define chThdLS() (void *)(currp + 1)
-
-/**
- * @brief Verifies if the specified thread is in the @p THD_STATE_FINAL state.
- * @note Can be invoked in any context.
- *
- * @param[in] tp pointer to the thread
- * @retval TRUE thread terminated.
- * @retval FALSE thread not terminated.
- *
- * @special
- */
-#define chThdTerminated(tp) ((tp)->p_state == THD_STATE_FINAL)
-
-/**
- * @brief Verifies if the current thread has a termination request pending.
- * @note Can be invoked in any context.
- *
- * @retval 0 termination request not pending.
- * @retval !0 termination request pending.
- *
- * @special
- */
-#define chThdShouldTerminate() (currp->p_flags & THD_TERMINATE)
-
-/**
- * @brief Resumes a thread created with @p chThdCreateI().
- *
- * @param[in] tp pointer to the thread
- *
- * @iclass
- */
-#define chThdResumeI(tp) chSchReadyI(tp)
-
-/**
- * @brief Suspends the invoking thread for the specified time.
- *
- * @param[in] time the delay in system ticks, the special values are
- * handled as follow:
- * - @a TIME_INFINITE the thread enters an infinite sleep
- * state.
- * - @a TIME_IMMEDIATE this value is not allowed.
- * .
- *
- * @sclass
- */
-#define chThdSleepS(time) chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time)
-
-/**
- * @brief Delays the invoking thread for the specified number of seconds.
- * @note The specified time is rounded up to a value allowed by the real
- * system tick clock.
- * @note The maximum specifiable value is implementation dependent.
- *
- * @param[in] sec time in seconds, must be different from zero
- *
- * @api
- */
-#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec))
-
-/**
- * @brief Delays the invoking thread for the specified number of
- * milliseconds.
- * @note The specified time is rounded up to a value allowed by the real
- * system tick clock.
- * @note The maximum specifiable value is implementation dependent.
- *
- * @param[in] msec time in milliseconds, must be different from zero
- *
- * @api
- */
-#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec))
-
-/**
- * @brief Delays the invoking thread for the specified number of
- * microseconds.
- * @note The specified time is rounded up to a value allowed by the real
- * system tick clock.
- * @note The maximum specifiable value is implementation dependent.
- *
- * @param[in] usec time in microseconds, must be different from zero
- *
- * @api
- */
-#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec))
-/** @} */
-
-/*
- * Threads APIs.
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
- Thread *_thread_init(Thread *tp, tprio_t prio);
-#if CH_DBG_FILL_THREADS
- void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v);
-#endif
- Thread *chThdCreateI(void *wsp, size_t size,
- tprio_t prio, tfunc_t pf, void *arg);
- Thread *chThdCreateStatic(void *wsp, size_t size,
- tprio_t prio, tfunc_t pf, void *arg);
- tprio_t chThdSetPriority(tprio_t newprio);
- Thread *chThdResume(Thread *tp);
- void chThdTerminate(Thread *tp);
- void chThdSleep(systime_t time);
- void chThdSleepUntil(systime_t time);
- void chThdYield(void);
- void chThdExit(msg_t msg);
- void chThdExitS(msg_t msg);
-#if CH_USE_WAITEXIT
- msg_t chThdWait(Thread *tp);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHTHREADS_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chvt.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chvt.h
deleted file mode 100644
index 38f15045c5..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/include/chvt.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chvt.h
- * @brief Time macros and structures.
- *
- * @addtogroup time
- * @{
- */
-
-#ifndef _CHVT_H_
-#define _CHVT_H_
-
-/**
- * @name Time conversion utilities
- * @{
- */
-/**
- * @brief Seconds to system ticks.
- * @details Converts from seconds to system ticks number.
- * @note The result is rounded upward to the next tick boundary.
- *
- * @param[in] sec number of seconds
- * @return The number of ticks.
- *
- * @api
- */
-#define S2ST(sec) \
- ((systime_t)((sec) * CH_FREQUENCY))
-
-/**
- * @brief Milliseconds to system ticks.
- * @details Converts from milliseconds to system ticks number.
- * @note The result is rounded upward to the next tick boundary.
- *
- * @param[in] msec number of milliseconds
- * @return The number of ticks.
- *
- * @api
- */
-#define MS2ST(msec) \
- ((systime_t)(((((uint32_t)(msec)) * ((uint32_t)CH_FREQUENCY) - 1UL) / \
- 1000UL) + 1UL))
-
-/**
- * @brief Microseconds to system ticks.
- * @details Converts from microseconds to system ticks number.
- * @note The result is rounded upward to the next tick boundary.
- *
- * @param[in] usec number of microseconds
- * @return The number of ticks.
- *
- * @api
- */
-#define US2ST(usec) \
- ((systime_t)(((((uint32_t)(usec)) * ((uint32_t)CH_FREQUENCY) - 1UL) / \
- 1000000UL) + 1UL))
-/** @} */
-
-/**
- * @brief Virtual Timer callback function.
- */
-typedef void (*vtfunc_t)(void *);
-
-/**
- * @brief Virtual Timer structure type.
- */
-typedef struct VirtualTimer VirtualTimer;
-
-/**
- * @extends VTList
- *
- * @brief Virtual Timer descriptor structure.
- */
-struct VirtualTimer {
- VirtualTimer *vt_next; /**< @brief Next timer in the delta
- list. */
- VirtualTimer *vt_prev; /**< @brief Previous timer in the delta
- list. */
- systime_t vt_time; /**< @brief Time delta before timeout. */
- vtfunc_t vt_func; /**< @brief Timer callback function
- pointer. */
- void *vt_par; /**< @brief Timer callback function
- parameter. */
-};
-
-/**
- * @brief Virtual timers list header.
- * @note The delta list is implemented as a double link bidirectional list
- * in order to make the unlink time constant, the reset of a virtual
- * timer is often used in the code.
- */
-typedef struct {
- VirtualTimer *vt_next; /**< @brief Next timer in the delta
- list. */
- VirtualTimer *vt_prev; /**< @brief Last timer in the delta
- list. */
- systime_t vt_time; /**< @brief Must be initialized to -1. */
- volatile systime_t vt_systime; /**< @brief System Time counter. */
-} VTList;
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Virtual timers ticker.
- * @note The system lock is released before entering the callback and
- * re-acquired immediately after. It is callback's responsibility
- * to acquire the lock if needed. This is done in order to reduce
- * interrupts jitter when many timers are in use.
- *
- * @iclass
- */
-#define chVTDoTickI() { \
- vtlist.vt_systime++; \
- if (&vtlist != (VTList *)vtlist.vt_next) { \
- VirtualTimer *vtp; \
- \
- --vtlist.vt_next->vt_time; \
- while (!(vtp = vtlist.vt_next)->vt_time) { \
- vtfunc_t fn = vtp->vt_func; \
- vtp->vt_func = (vtfunc_t)NULL; \
- vtp->vt_next->vt_prev = (void *)&vtlist; \
- (&vtlist)->vt_next = vtp->vt_next; \
- chSysUnlockFromIsr(); \
- fn(vtp->vt_par); \
- chSysLockFromIsr(); \
- } \
- } \
-}
-
-/**
- * @brief Returns @p TRUE if the specified timer is armed.
- *
- * @iclass
- */
-#define chVTIsArmedI(vtp) ((vtp)->vt_func != NULL)
-
-/**
- * @brief Enables a virtual timer.
- * @note The associated function is invoked from interrupt context.
- *
- * @param[out] vtp the @p VirtualTimer structure pointer
- * @param[in] time the number of ticks before the operation timeouts, the
- * special values are handled as follow:
- * - @a TIME_INFINITE is allowed but interpreted as a
- * normal time specification.
- * - @a TIME_IMMEDIATE this value is not allowed.
- * .
- * @param[in] vtfunc the timer callback function. After invoking the
- * callback the timer is disabled and the structure can
- * be disposed or reused.
- * @param[in] par a parameter that will be passed to the callback
- * function
- *
- * @api
- */
-#define chVTSet(vtp, time, vtfunc, par) { \
- chSysLock(); \
- chVTSetI(vtp, time, vtfunc, par); \
- chSysUnlock(); \
-}
-
-/**
- * @brief Disables a Virtual Timer.
- * @note The timer is first checked and disabled only if armed.
- *
- * @param[in] vtp the @p VirtualTimer structure pointer
- *
- * @api
- */
-#define chVTReset(vtp) { \
- chSysLock(); \
- if (chVTIsArmedI(vtp)) \
- chVTResetI(vtp); \
- chSysUnlock(); \
-}
-
-/**
- * @brief Current system time.
- * @details Returns the number of system ticks since the @p chSysInit()
- * invocation.
- * @note The counter can reach its maximum and then restart from zero.
- * @note This function is designed to work with the @p chThdSleepUntil().
- *
- * @return The system time in ticks.
- *
- * @api
- */
-#define chTimeNow() (vtlist.vt_systime)
-
-/**
- * @brief Returns the elapsed time since the specified start time.
- *
- * @param[in] start start time
- * @return The elapsed time.
- *
- * @api
- */
-#define chTimeElapsedSince(start) (chTimeNow() - (start))
-
-/**
- * @brief Checks if the current system time is within the specified time
- * window.
- * @note When start==end then the function returns always true because the
- * whole time range is specified.
- *
- * @param[in] start the start of the time window (inclusive)
- * @param[in] end the end of the time window (non inclusive)
- * @retval TRUE current time within the specified time window.
- * @retval FALSE current time not within the specified time window.
- *
- * @api
- */
-#define chTimeIsWithin(start, end) \
- (chTimeElapsedSince(start) < ((end) - (start)))
-/** @} */
-
-extern VTList vtlist;
-
-/*
- * Virtual Timers APIs.
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _vt_init(void);
- void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par);
- void chVTResetI(VirtualTimer *vtp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHVT_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/kernel.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/kernel.mk
deleted file mode 100644
index 1f9a046438..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/kernel.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-# List of all the ChibiOS/RT kernel files, there is no need to remove the files
-# from this list, you can disable parts of the kernel by editing chconf.h.
-KERNSRC = ${CHIBIOS}/os/kernel/src/chsys.c \
- ${CHIBIOS}/os/kernel/src/chdebug.c \
- ${CHIBIOS}/os/kernel/src/chlists.c \
- ${CHIBIOS}/os/kernel/src/chvt.c \
- ${CHIBIOS}/os/kernel/src/chschd.c \
- ${CHIBIOS}/os/kernel/src/chthreads.c \
- ${CHIBIOS}/os/kernel/src/chdynamic.c \
- ${CHIBIOS}/os/kernel/src/chregistry.c \
- ${CHIBIOS}/os/kernel/src/chsem.c \
- ${CHIBIOS}/os/kernel/src/chmtx.c \
- ${CHIBIOS}/os/kernel/src/chcond.c \
- ${CHIBIOS}/os/kernel/src/chevents.c \
- ${CHIBIOS}/os/kernel/src/chmsg.c \
- ${CHIBIOS}/os/kernel/src/chmboxes.c \
- ${CHIBIOS}/os/kernel/src/chqueues.c \
- ${CHIBIOS}/os/kernel/src/chmemcore.c \
- ${CHIBIOS}/os/kernel/src/chheap.c \
- ${CHIBIOS}/os/kernel/src/chmempools.c
-
-# Required include directories
-KERNINC = ${CHIBIOS}/os/kernel/include
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chdebug.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chdebug.c
deleted file mode 100644
index 3ba698abc8..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chdebug.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chdebug.c
- * @brief ChibiOS/RT Debug code.
- *
- * @addtogroup debug
- * @details Debug APIs and services:
- * - Runtime system state and call protocol check. The following
- * panic messages can be generated:
- * - SV#1, misplaced @p chSysDisable().
- * - SV#2, misplaced @p chSysSuspend()
- * - SV#3, misplaced @p chSysEnable().
- * - SV#4, misplaced @p chSysLock().
- * - SV#5, misplaced @p chSysUnlock().
- * - SV#6, misplaced @p chSysLockFromIsr().
- * - SV#7, misplaced @p chSysUnlockFromIsr().
- * - SV#8, misplaced @p CH_IRQ_PROLOGUE().
- * - SV#9, misplaced @p CH_IRQ_EPILOGUE().
- * - SV#10, misplaced I-class function.
- * - SV#11, misplaced S-class function.
- * .
- * - Trace buffer.
- * - Parameters check.
- * - Kernel assertions.
- * - Kernel panics.
- * .
- * @note Stack checks are not implemented in this module but in the port
- * layer in an architecture-dependent way.
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* System state checker related code and variables. */
-/*===========================================================================*/
-
-#if CH_DBG_SYSTEM_STATE_CHECK || defined(__DOXYGEN__)
-
-/**
- * @brief ISR nesting level.
- */
-cnt_t dbg_isr_cnt;
-
-/**
- * @brief Lock nesting level.
- */
-cnt_t dbg_lock_cnt;
-
-/**
- * @brief Guard code for @p chSysDisable().
- *
- * @notapi
- */
-void dbg_check_disable(void) {
-
- if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0))
- chDbgPanic("SV#1");
-}
-
-/**
- * @brief Guard code for @p chSysSuspend().
- *
- * @notapi
- */
-void dbg_check_suspend(void) {
-
- if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0))
- chDbgPanic("SV#2");
-}
-
-/**
- * @brief Guard code for @p chSysEnable().
- *
- * @notapi
- */
-void dbg_check_enable(void) {
-
- if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0))
- chDbgPanic("SV#3");
-}
-
-/**
- * @brief Guard code for @p chSysLock().
- *
- * @notapi
- */
-void dbg_check_lock(void) {
-
- if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0))
- chDbgPanic("SV#4");
- dbg_enter_lock();
-}
-
-/**
- * @brief Guard code for @p chSysUnlock().
- *
- * @notapi
- */
-void dbg_check_unlock(void) {
-
- if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0))
- chDbgPanic("SV#5");
- dbg_leave_lock();
-}
-
-/**
- * @brief Guard code for @p chSysLockFromIsr().
- *
- * @notapi
- */
-void dbg_check_lock_from_isr(void) {
-
- if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0))
- chDbgPanic("SV#6");
- dbg_enter_lock();
-}
-
-/**
- * @brief Guard code for @p chSysUnlockFromIsr().
- *
- * @notapi
- */
-void dbg_check_unlock_from_isr(void) {
-
- if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt <= 0))
- chDbgPanic("SV#7");
- dbg_leave_lock();
-}
-
-/**
- * @brief Guard code for @p CH_IRQ_PROLOGUE().
- *
- * @notapi
- */
-void dbg_check_enter_isr(void) {
-
- port_lock_from_isr();
- if ((dbg_isr_cnt < 0) || (dbg_lock_cnt != 0))
- chDbgPanic("SV#8");
- dbg_isr_cnt++;
- port_unlock_from_isr();
-}
-
-/**
- * @brief Guard code for @p CH_IRQ_EPILOGUE().
- *
- * @notapi
- */
-void dbg_check_leave_isr(void) {
-
- port_lock_from_isr();
- if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0))
- chDbgPanic("SV#9");
- dbg_isr_cnt--;
- port_unlock_from_isr();
-}
-
-/**
- * @brief I-class functions context check.
- * @details Verifies that the system is in an appropriate state for invoking
- * an I-class API function. A panic is generated if the state is
- * not compatible.
- *
- * @api
- */
-void chDbgCheckClassI(void) {
-
- if ((dbg_isr_cnt < 0) || (dbg_lock_cnt <= 0))
- chDbgPanic("SV#10");
-}
-
-/**
- * @brief S-class functions context check.
- * @details Verifies that the system is in an appropriate state for invoking
- * an S-class API function. A panic is generated if the state is
- * not compatible.
- *
- * @api
- */
-void chDbgCheckClassS(void) {
-
- if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0))
- chDbgPanic("SV#11");
-}
-
-#endif /* CH_DBG_SYSTEM_STATE_CHECK */
-
-/*===========================================================================*/
-/* Trace related code and variables. */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
-/**
- * @brief Public trace buffer.
- */
-ch_trace_buffer_t dbg_trace_buffer;
-
-/**
- * @brief Trace circular buffer subsystem initialization.
- * @note Internal use only.
- */
-void _trace_init(void) {
-
- dbg_trace_buffer.tb_size = CH_TRACE_BUFFER_SIZE;
- dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0];
-}
-
-/**
- * @brief Inserts in the circular debug trace buffer a context switch record.
- *
- * @param[in] otp the thread being switched out
- *
- * @notapi
- */
-void dbg_trace(Thread *otp) {
-
- dbg_trace_buffer.tb_ptr->se_time = chTimeNow();
- dbg_trace_buffer.tb_ptr->se_tp = currp;
- dbg_trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp;
- dbg_trace_buffer.tb_ptr->se_state = (uint8_t)otp->p_state;
- if (++dbg_trace_buffer.tb_ptr >=
- &dbg_trace_buffer.tb_buffer[CH_TRACE_BUFFER_SIZE])
- dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0];
-}
-#endif /* CH_DBG_ENABLE_TRACE */
-
-/*===========================================================================*/
-/* Panic related code and variables. */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLED || defined(__DOXYGEN__)
-/**
- * @brief Pointer to the panic message.
- * @details This pointer is meant to be accessed through the debugger, it is
- * written once and then the system is halted.
- */
-const char *dbg_panic_msg;
-
-/**
- * @brief Prints a panic message on the console and then halts the system.
- *
- * @param[in] msg the pointer to the panic message string
- */
-void chDbgPanic(const char *msg) {
-
- dbg_panic_msg = msg;
- chSysHalt();
-}
-#endif /* CH_DBG_ENABLED */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chdynamic.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chdynamic.c
deleted file mode 100644
index e664e78226..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chdynamic.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chdynamic.c
- * @brief Dynamic threads code.
- *
- * @addtogroup dynamic_threads
- * @details Dynamic threads related APIs and services.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_DYNAMIC || defined(__DOXYGEN__)
-
-/**
- * @brief Adds a reference to a thread object.
- * @pre The configuration option @p CH_USE_DYNAMIC must be enabled in order
- * to use this function.
- *
- * @param[in] tp pointer to the thread
- * @return The same thread pointer passed as parameter
- * representing the new reference.
- *
- * @api
- */
-Thread *chThdAddRef(Thread *tp) {
-
- chSysLock();
- chDbgAssert(tp->p_refs < 255, "chThdAddRef(), #1", "too many references");
- tp->p_refs++;
- chSysUnlock();
- return tp;
-}
-
-/**
- * @brief Releases a reference to a thread object.
- * @details If the references counter reaches zero and the thread
- * is in the @p THD_STATE_FINAL state then the thread's memory is
- * returned to the proper allocator.
- * @pre The configuration option @p CH_USE_DYNAMIC must be enabled in order
- * to use this function.
- * @note Static threads are not affected.
- *
- * @param[in] tp pointer to the thread
- *
- * @api
- */
-void chThdRelease(Thread *tp) {
- trefs_t refs;
-
- chSysLock();
- chDbgAssert(tp->p_refs > 0, "chThdRelease(), #1", "not referenced");
- refs = --tp->p_refs;
- chSysUnlock();
-
- /* If the references counter reaches zero and the thread is in its
- terminated state then the memory can be returned to the proper
- allocator. Of course static threads are not affected.*/
- if ((refs == 0) && (tp->p_state == THD_STATE_FINAL)) {
- switch (tp->p_flags & THD_MEM_MODE_MASK) {
-#if CH_USE_HEAP
- case THD_MEM_MODE_HEAP:
-#if CH_USE_REGISTRY
- REG_REMOVE(tp);
-#endif
- chHeapFree(tp);
- break;
-#endif
-#if CH_USE_MEMPOOLS
- case THD_MEM_MODE_MEMPOOL:
-#if CH_USE_REGISTRY
- REG_REMOVE(tp);
-#endif
- chPoolFree(tp->p_mpool, tp);
- break;
-#endif
- }
- }
-}
-
-#if CH_USE_HEAP || defined(__DOXYGEN__)
-/**
- * @brief Creates a new thread allocating the memory from the heap.
- * @pre The configuration options @p CH_USE_DYNAMIC and @p CH_USE_HEAP
- * must be enabled in order to use this function.
- * @note A thread can terminate by calling @p chThdExit() or by simply
- * returning from its main function.
- * @note The memory allocated for the thread is not released when the thread
- * terminates but when a @p chThdWait() is performed.
- *
- * @param[in] heapp heap from which allocate the memory or @p NULL for the
- * default heap
- * @param[in] size size of the working area to be allocated
- * @param[in] prio the priority level for the new thread
- * @param[in] pf the thread function
- * @param[in] arg an argument passed to the thread function. It can be
- * @p NULL.
- * @return The pointer to the @p Thread structure allocated for
- * the thread into the working space area.
- * @retval NULL if the memory cannot be allocated.
- *
- * @api
- */
-Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size,
- tprio_t prio, tfunc_t pf, void *arg) {
- void *wsp;
- Thread *tp;
-
- wsp = chHeapAlloc(heapp, size);
- if (wsp == NULL)
- return NULL;
-
-#if CH_DBG_FILL_THREADS
- _thread_memfill((uint8_t *)wsp,
- (uint8_t *)wsp + sizeof(Thread),
- CH_THREAD_FILL_VALUE);
- _thread_memfill((uint8_t *)wsp + sizeof(Thread),
- (uint8_t *)wsp + size,
- CH_STACK_FILL_VALUE);
-#endif
-
- chSysLock();
- tp = chThdCreateI(wsp, size, prio, pf, arg);
- tp->p_flags = THD_MEM_MODE_HEAP;
- chSchWakeupS(tp, RDY_OK);
- chSysUnlock();
- return tp;
-}
-#endif /* CH_USE_HEAP */
-
-#if CH_USE_MEMPOOLS || defined(__DOXYGEN__)
-/**
- * @brief Creates a new thread allocating the memory from the specified
- * memory pool.
- * @pre The configuration options @p CH_USE_DYNAMIC and @p CH_USE_MEMPOOLS
- * must be enabled in order to use this function.
- * @note A thread can terminate by calling @p chThdExit() or by simply
- * returning from its main function.
- * @note The memory allocated for the thread is not released when the thread
- * terminates but when a @p chThdWait() is performed.
- *
- * @param[in] mp pointer to the memory pool object
- * @param[in] prio the priority level for the new thread
- * @param[in] pf the thread function
- * @param[in] arg an argument passed to the thread function. It can be
- * @p NULL.
- * @return The pointer to the @p Thread structure allocated for
- * the thread into the working space area.
- * @retval NULL if the memory pool is empty.
- *
- * @api
- */
-Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio,
- tfunc_t pf, void *arg) {
- void *wsp;
- Thread *tp;
-
- chDbgCheck(mp != NULL, "chThdCreateFromMemoryPool");
-
- wsp = chPoolAlloc(mp);
- if (wsp == NULL)
- return NULL;
-
-#if CH_DBG_FILL_THREADS
- _thread_memfill((uint8_t *)wsp,
- (uint8_t *)wsp + sizeof(Thread),
- CH_THREAD_FILL_VALUE);
- _thread_memfill((uint8_t *)wsp + sizeof(Thread),
- (uint8_t *)wsp + mp->mp_object_size,
- CH_STACK_FILL_VALUE);
-#endif
-
- chSysLock();
- tp = chThdCreateI(wsp, mp->mp_object_size, prio, pf, arg);
- tp->p_flags = THD_MEM_MODE_MEMPOOL;
- tp->p_mpool = mp;
- chSchWakeupS(tp, RDY_OK);
- chSysUnlock();
- return tp;
-}
-#endif /* CH_USE_MEMPOOLS */
-
-#endif /* CH_USE_DYNAMIC */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chevents.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chevents.c
deleted file mode 100644
index c7d3a8c880..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chevents.c
+++ /dev/null
@@ -1,555 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-/*
- Concepts and parts of this file have been contributed by Scott (skute).
- */
-
-/**
- * @file chevents.c
- * @brief Events code.
- *
- * @addtogroup events
- * @details Event Flags, Event Sources and Event Listeners.
- * Operation mode
- * Each thread has a mask of pending event flags inside its @p Thread
- * structure.
- * Operations defined for event flags:
- * - Wait, the invoking thread goes to sleep until a certain
- * AND/OR combination of event flags becomes pending.
- * - Clear, a mask of event flags is cleared from the pending
- * events mask, the cleared event flags mask is returned (only the
- * flags that were actually pending and then cleared).
- * - Signal, an event mask is directly ORed to the mask of the
- * signaled thread.
- * - Broadcast, each thread registered on an Event Source is
- * signaled with the event flags specified in its Event Listener.
- * - Dispatch, an events mask is scanned and for each bit set
- * to one an associated handler function is invoked. Bit masks are
- * scanned from bit zero upward.
- * .
- * An Event Source is a special object that can be "broadcasted" by
- * a thread or an interrupt service routine. Broadcasting an Event
- * Source has the effect that all the threads registered on the
- * Event Source will be signaled with an events mask.
- * An unlimited number of Event Sources can exists in a system and
- * each thread can be listening on an unlimited number of
- * them.
- * @pre In order to use the Events APIs the @p CH_USE_EVENTS option must be
- * enabled in @p chconf.h.
- * @post Enabling events requires 1-4 (depending on the architecture)
- * extra bytes in the @p Thread structure.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
-/**
- * @brief Registers an Event Listener on an Event Source.
- * @details Once a thread has registered as listener on an event source it
- * will be notified of all events broadcasted there.
- * @note Multiple Event Listeners can specify the same bits to be ORed to
- * different threads.
- *
- * @param[in] esp pointer to the @p EventSource structure
- * @param[out] elp pointer to the @p EventListener structure
- * @param[in] mask the mask of event flags to be ORed to the thread when
- * the event source is broadcasted
- *
- * @api
- */
-void chEvtRegisterMask(EventSource *esp, EventListener *elp, eventmask_t mask) {
-
- chDbgCheck((esp != NULL) && (elp != NULL), "chEvtRegisterMask");
-
- chSysLock();
- elp->el_next = esp->es_next;
- esp->es_next = elp;
- elp->el_listener = currp;
- elp->el_mask = mask;
- elp->el_flags = 0;
- chSysUnlock();
-}
-
-/**
- * @brief Unregisters an Event Listener from its Event Source.
- * @note If the event listener is not registered on the specified event
- * source then the function does nothing.
- * @note For optimal performance it is better to perform the unregister
- * operations in inverse order of the register operations (elements
- * are found on top of the list).
- *
- * @param[in] esp pointer to the @p EventSource structure
- * @param[in] elp pointer to the @p EventListener structure
- *
- * @api
- */
-void chEvtUnregister(EventSource *esp, EventListener *elp) {
- EventListener *p;
-
- chDbgCheck((esp != NULL) && (elp != NULL), "chEvtUnregister");
-
- p = (EventListener *)esp;
- chSysLock();
- while (p->el_next != (EventListener *)esp) {
- if (p->el_next == elp) {
- p->el_next = elp->el_next;
- break;
- }
- p = p->el_next;
- }
- chSysUnlock();
-}
-
-/**
- * @brief Clears the pending events specified in the mask.
- *
- * @param[in] mask the events to be cleared
- * @return The pending events that were cleared.
- *
- * @api
- */
-eventmask_t chEvtGetAndClearEvents(eventmask_t mask) {
- eventmask_t m;
-
- chSysLock();
-
- m = currp->p_epending & mask;
- currp->p_epending &= ~mask;
-
- chSysUnlock();
- return m;
-}
-
-/**
- * @brief Adds (OR) a set of event flags on the current thread, this is
- * @b much faster than using @p chEvtBroadcast() or @p chEvtSignal().
- *
- * @param[in] mask the event flags to be added
- * @return The current pending events mask.
- *
- * @api
- */
-eventmask_t chEvtAddEvents(eventmask_t mask) {
-
- chSysLock();
-
- mask = (currp->p_epending |= mask);
-
- chSysUnlock();
- return mask;
-}
-
-/**
- * @brief Signals all the Event Listeners registered on the specified Event
- * Source.
- * @details This function variants ORs the specified event flags to all the
- * threads registered on the @p EventSource in addition to the event
- * flags specified by the threads themselves in the
- * @p EventListener objects.
- * @post This function does not reschedule so a call to a rescheduling
- * function must be performed before unlocking the kernel. Note that
- * interrupt handlers always reschedule on exit so an explicit
- * reschedule must not be performed in ISRs.
- *
- * @param[in] esp pointer to the @p EventSource structure
- * @param[in] flags the flags set to be added to the listener flags mask
- *
- * @iclass
- */
-void chEvtBroadcastFlagsI(EventSource *esp, flagsmask_t flags) {
- EventListener *elp;
-
- chDbgCheckClassI();
- chDbgCheck(esp != NULL, "chEvtBroadcastMaskI");
-
- elp = esp->es_next;
- while (elp != (EventListener *)esp) {
- elp->el_flags |= flags;
- chEvtSignalI(elp->el_listener, elp->el_mask);
- elp = elp->el_next;
- }
-}
-
-/**
- * @brief Returns the flags associated to an @p EventListener.
- * @details The flags are returned and the @p EventListener flags mask is
- * cleared.
- *
- * @param[in] elp pointer to the @p EventListener structure
- * @return The flags added to the listener by the associated
- * event source.
- *
- * @api
- */
-flagsmask_t chEvtGetAndClearFlags(EventListener *elp) {
- flagsmask_t flags;
-
- chSysLock();
-
- flags = elp->el_flags;
- elp->el_flags = 0;
-
- chSysUnlock();
- return flags;
-}
-
-/**
- * @brief Adds a set of event flags directly to specified @p Thread.
- *
- * @param[in] tp the thread to be signaled
- * @param[in] mask the event flags set to be ORed
- *
- * @api
- */
-void chEvtSignal(Thread *tp, eventmask_t mask) {
-
- chDbgCheck(tp != NULL, "chEvtSignal");
-
- chSysLock();
- chEvtSignalI(tp, mask);
- chSchRescheduleS();
- chSysUnlock();
-}
-
-/**
- * @brief Adds a set of event flags directly to specified @p Thread.
- * @post This function does not reschedule so a call to a rescheduling
- * function must be performed before unlocking the kernel. Note that
- * interrupt handlers always reschedule on exit so an explicit
- * reschedule must not be performed in ISRs.
- *
- * @param[in] tp the thread to be signaled
- * @param[in] mask the event flags set to be ORed
- *
- * @iclass
- */
-void chEvtSignalI(Thread *tp, eventmask_t mask) {
-
- chDbgCheckClassI();
- chDbgCheck(tp != NULL, "chEvtSignalI");
-
- tp->p_epending |= mask;
- /* Test on the AND/OR conditions wait states.*/
- if (((tp->p_state == THD_STATE_WTOREVT) &&
- ((tp->p_epending & tp->p_u.ewmask) != 0)) ||
- ((tp->p_state == THD_STATE_WTANDEVT) &&
- ((tp->p_epending & tp->p_u.ewmask) == tp->p_u.ewmask)))
- chSchReadyI(tp)->p_u.rdymsg = RDY_OK;
-}
-
-/**
- * @brief Signals all the Event Listeners registered on the specified Event
- * Source.
- * @details This function variants ORs the specified event flags to all the
- * threads registered on the @p EventSource in addition to the event
- * flags specified by the threads themselves in the
- * @p EventListener objects.
- *
- * @param[in] esp pointer to the @p EventSource structure
- * @param[in] flags the flags set to be added to the listener flags mask
- *
- * @api
- */
-void chEvtBroadcastFlags(EventSource *esp, flagsmask_t flags) {
-
- chSysLock();
- chEvtBroadcastFlagsI(esp, flags);
- chSchRescheduleS();
- chSysUnlock();
-}
-
-/**
- * @brief Returns the flags associated to an @p EventListener.
- * @details The flags are returned and the @p EventListener flags mask is
- * cleared.
- *
- * @param[in] elp pointer to the @p EventListener structure
- * @return The flags added to the listener by the associated
- * event source.
- *
- * @iclass
- */
-flagsmask_t chEvtGetAndClearFlagsI(EventListener *elp) {
- flagsmask_t flags;
-
- flags = elp->el_flags;
- elp->el_flags = 0;
-
- return flags;
-}
-
-/**
- * @brief Invokes the event handlers associated to an event flags mask.
- *
- * @param[in] mask mask of the event flags to be dispatched
- * @param[in] handlers an array of @p evhandler_t. The array must have size
- * equal to the number of bits in eventmask_t.
- *
- * @api
- */
-void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask) {
- eventid_t eid;
-
- chDbgCheck(handlers != NULL, "chEvtDispatch");
-
- eid = 0;
- while (mask) {
- if (mask & EVENT_MASK(eid)) {
- chDbgAssert(handlers[eid] != NULL,
- "chEvtDispatch(), #1",
- "null handler");
- mask &= ~EVENT_MASK(eid);
- handlers[eid](eid);
- }
- eid++;
- }
-}
-
-#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__)
-/**
- * @brief Waits for exactly one of the specified events.
- * @details The function waits for one event among those specified in
- * @p mask to become pending then the event is cleared and returned.
- * @note One and only one event is served in the function, the one with the
- * lowest event id. The function is meant to be invoked into a loop in
- * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have
- * an higher priority.
- *
- * @param[in] mask mask of the event flags that the function should wait
- * for, @p ALL_EVENTS enables all the events
- * @return The mask of the lowest id served and cleared event.
- *
- * @api
- */
-eventmask_t chEvtWaitOne(eventmask_t mask) {
- Thread *ctp = currp;
- eventmask_t m;
-
- chSysLock();
-
- if ((m = (ctp->p_epending & mask)) == 0) {
- ctp->p_u.ewmask = mask;
- chSchGoSleepS(THD_STATE_WTOREVT);
- m = ctp->p_epending & mask;
- }
- m &= -m;
- ctp->p_epending &= ~m;
-
- chSysUnlock();
- return m;
-}
-
-/**
- * @brief Waits for any of the specified events.
- * @details The function waits for any event among those specified in
- * @p mask to become pending then the events are cleared and returned.
- *
- * @param[in] mask mask of the event flags that the function should wait
- * for, @p ALL_EVENTS enables all the events
- * @return The mask of the served and cleared events.
- *
- * @api
- */
-eventmask_t chEvtWaitAny(eventmask_t mask) {
- Thread *ctp = currp;
- eventmask_t m;
-
- chSysLock();
-
- if ((m = (ctp->p_epending & mask)) == 0) {
- ctp->p_u.ewmask = mask;
- chSchGoSleepS(THD_STATE_WTOREVT);
- m = ctp->p_epending & mask;
- }
- ctp->p_epending &= ~m;
-
- chSysUnlock();
- return m;
-}
-
-/**
- * @brief Waits for all the specified events.
- * @details The function waits for all the events specified in @p mask to
- * become pending then the events are cleared and returned.
- *
- * @param[in] mask mask of the event flags that the function should wait
- * for, @p ALL_EVENTS requires all the events
- * @return The mask of the served and cleared events.
- *
- * @api
- */
-eventmask_t chEvtWaitAll(eventmask_t mask) {
- Thread *ctp = currp;
-
- chSysLock();
-
- if ((ctp->p_epending & mask) != mask) {
- ctp->p_u.ewmask = mask;
- chSchGoSleepS(THD_STATE_WTANDEVT);
- }
- ctp->p_epending &= ~mask;
-
- chSysUnlock();
- return mask;
-}
-#endif /* CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT */
-
-#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__)
-/**
- * @brief Waits for exactly one of the specified events.
- * @details The function waits for one event among those specified in
- * @p mask to become pending then the event is cleared and returned.
- * @note One and only one event is served in the function, the one with the
- * lowest event id. The function is meant to be invoked into a loop in
- * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have
- * an higher priority.
- *
- * @param[in] mask mask of the event flags that the function should wait
- * for, @p ALL_EVENTS enables all the events
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The mask of the lowest id served and cleared event.
- * @retval 0 if the operation has timed out.
- *
- * @api
- */
-eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time) {
- Thread *ctp = currp;
- eventmask_t m;
-
- chSysLock();
-
- if ((m = (ctp->p_epending & mask)) == 0) {
- if (TIME_IMMEDIATE == time) {
- chSysUnlock();
- return (eventmask_t)0;
- }
- ctp->p_u.ewmask = mask;
- if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) {
- chSysUnlock();
- return (eventmask_t)0;
- }
- m = ctp->p_epending & mask;
- }
- m &= -m;
- ctp->p_epending &= ~m;
-
- chSysUnlock();
- return m;
-}
-
-/**
- * @brief Waits for any of the specified events.
- * @details The function waits for any event among those specified in
- * @p mask to become pending then the events are cleared and
- * returned.
- *
- * @param[in] mask mask of the event flags that the function should wait
- * for, @p ALL_EVENTS enables all the events
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The mask of the served and cleared events.
- * @retval 0 if the operation has timed out.
- *
- * @api
- */
-eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time) {
- Thread *ctp = currp;
- eventmask_t m;
-
- chSysLock();
-
- if ((m = (ctp->p_epending & mask)) == 0) {
- if (TIME_IMMEDIATE == time) {
- chSysUnlock();
- return (eventmask_t)0;
- }
- ctp->p_u.ewmask = mask;
- if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) {
- chSysUnlock();
- return (eventmask_t)0;
- }
- m = ctp->p_epending & mask;
- }
- ctp->p_epending &= ~m;
-
- chSysUnlock();
- return m;
-}
-
-/**
- * @brief Waits for all the specified events.
- * @details The function waits for all the events specified in @p mask to
- * become pending then the events are cleared and returned.
- *
- * @param[in] mask mask of the event flags that the function should wait
- * for, @p ALL_EVENTS requires all the events
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The mask of the served and cleared events.
- * @retval 0 if the operation has timed out.
- *
- * @api
- */
-eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time) {
- Thread *ctp = currp;
-
- chSysLock();
-
- if ((ctp->p_epending & mask) != mask) {
- if (TIME_IMMEDIATE == time) {
- chSysUnlock();
- return (eventmask_t)0;
- }
- ctp->p_u.ewmask = mask;
- if (chSchGoSleepTimeoutS(THD_STATE_WTANDEVT, time) < RDY_OK) {
- chSysUnlock();
- return (eventmask_t)0;
- }
- }
- ctp->p_epending &= ~mask;
-
- chSysUnlock();
- return mask;
-}
-#endif /* CH_USE_EVENTS_TIMEOUT */
-
-#endif /* CH_USE_EVENTS */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chheap.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chheap.c
deleted file mode 100644
index d2b18e15ae..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chheap.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chheap.c
- * @brief Heaps code.
- *
- * @addtogroup heaps
- * @details Heap Allocator related APIs.
- * Operation mode
- * The heap allocator implements a first-fit strategy and its APIs
- * are functionally equivalent to the usual @p malloc() and @p free()
- * library functions. The main difference is that the OS heap APIs
- * are guaranteed to be thread safe.
- * By enabling the @p CH_USE_MALLOC_HEAP option the heap manager
- * will use the runtime-provided @p malloc() and @p free() as
- * back end for the heap APIs instead of the system provided
- * allocator.
- * @pre In order to use the heap APIs the @p CH_USE_HEAP option must
- * be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_HEAP || defined(__DOXYGEN__)
-
-#if !CH_USE_MALLOC_HEAP || defined(__DOXYGEN__)
-
-/*
- * Defaults on the best synchronization mechanism available.
- */
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-#define H_LOCK(h) chMtxLock(&(h)->h_mtx)
-#define H_UNLOCK(h) chMtxUnlock()
-#else
-#define H_LOCK(h) chSemWait(&(h)->h_sem)
-#define H_UNLOCK(h) chSemSignal(&(h)->h_sem)
-#endif
-
-/**
- * @brief Default heap descriptor.
- */
-static MemoryHeap default_heap;
-
-/**
- * @brief Initializes the default heap.
- *
- * @notapi
- */
-void _heap_init(void) {
- default_heap.h_provider = chCoreAlloc;
- default_heap.h_free.h.u.next = (union heap_header *)NULL;
- default_heap.h_free.h.size = 0;
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
- chMtxInit(&default_heap.h_mtx);
-#else
- chSemInit(&default_heap.h_sem, 1);
-#endif
-}
-
-/**
- * @brief Initializes a memory heap from a static memory area.
- * @pre Both the heap buffer base and the heap size must be aligned to
- * the @p stkalign_t type size.
- * @pre In order to use this function the option @p CH_USE_MALLOC_HEAP
- * must be disabled.
- *
- * @param[out] heapp pointer to the memory heap descriptor to be initialized
- * @param[in] buf heap buffer base
- * @param[in] size heap size
- *
- * @init
- */
-void chHeapInit(MemoryHeap *heapp, void *buf, size_t size) {
- union heap_header *hp;
-
- chDbgCheck(MEM_IS_ALIGNED(buf) && MEM_IS_ALIGNED(size), "chHeapInit");
-
- heapp->h_provider = (memgetfunc_t)NULL;
- heapp->h_free.h.u.next = hp = buf;
- heapp->h_free.h.size = 0;
- hp->h.u.next = NULL;
- hp->h.size = size - sizeof(union heap_header);
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
- chMtxInit(&heapp->h_mtx);
-#else
- chSemInit(&heapp->h_sem, 1);
-#endif
-}
-
-/**
- * @brief Allocates a block of memory from the heap by using the first-fit
- * algorithm.
- * @details The allocated block is guaranteed to be properly aligned for a
- * pointer data type (@p stkalign_t).
- *
- * @param[in] heapp pointer to a heap descriptor or @p NULL in order to
- * access the default heap.
- * @param[in] size the size of the block to be allocated. Note that the
- * allocated block may be a bit bigger than the requested
- * size for alignment and fragmentation reasons.
- * @return A pointer to the allocated block.
- * @retval NULL if the block cannot be allocated.
- *
- * @api
- */
-void *chHeapAlloc(MemoryHeap *heapp, size_t size) {
- union heap_header *qp, *hp, *fp;
-
- if (heapp == NULL)
- heapp = &default_heap;
-
- size = MEM_ALIGN_NEXT(size);
- qp = &heapp->h_free;
- H_LOCK(heapp);
-
- while (qp->h.u.next != NULL) {
- hp = qp->h.u.next;
- if (hp->h.size >= size) {
- if (hp->h.size < size + sizeof(union heap_header)) {
- /* Gets the whole block even if it is slightly bigger than the
- requested size because the fragment would be too small to be
- useful.*/
- qp->h.u.next = hp->h.u.next;
- }
- else {
- /* Block bigger enough, must split it.*/
- fp = (void *)((uint8_t *)(hp) + sizeof(union heap_header) + size);
- fp->h.u.next = hp->h.u.next;
- fp->h.size = hp->h.size - sizeof(union heap_header) - size;
- qp->h.u.next = fp;
- hp->h.size = size;
- }
- hp->h.u.heap = heapp;
-
- H_UNLOCK(heapp);
- return (void *)(hp + 1);
- }
- qp = hp;
- }
-
- H_UNLOCK(heapp);
-
- /* More memory is required, tries to get it from the associated provider
- else fails.*/
- if (heapp->h_provider) {
- hp = heapp->h_provider(size + sizeof(union heap_header));
- if (hp != NULL) {
- hp->h.u.heap = heapp;
- hp->h.size = size;
- hp++;
- return (void *)hp;
- }
- }
- return NULL;
-}
-
-#define LIMIT(p) (union heap_header *)((uint8_t *)(p) + \
- sizeof(union heap_header) + \
- (p)->h.size)
-
-/**
- * @brief Frees a previously allocated memory block.
- *
- * @param[in] p pointer to the memory block to be freed
- *
- * @api
- */
-void chHeapFree(void *p) {
- union heap_header *qp, *hp;
- MemoryHeap *heapp;
-
- chDbgCheck(p != NULL, "chHeapFree");
-
- hp = (union heap_header *)p - 1;
- heapp = hp->h.u.heap;
- qp = &heapp->h_free;
- H_LOCK(heapp);
-
- while (TRUE) {
- chDbgAssert((hp < qp) || (hp >= LIMIT(qp)),
- "chHeapFree(), #1",
- "within free block");
-
- if (((qp == &heapp->h_free) || (hp > qp)) &&
- ((qp->h.u.next == NULL) || (hp < qp->h.u.next))) {
- /* Insertion after qp.*/
- hp->h.u.next = qp->h.u.next;
- qp->h.u.next = hp;
- /* Verifies if the newly inserted block should be merged.*/
- if (LIMIT(hp) == hp->h.u.next) {
- /* Merge with the next block.*/
- hp->h.size += hp->h.u.next->h.size + sizeof(union heap_header);
- hp->h.u.next = hp->h.u.next->h.u.next;
- }
- if ((LIMIT(qp) == hp)) {
- /* Merge with the previous block.*/
- qp->h.size += hp->h.size + sizeof(union heap_header);
- qp->h.u.next = hp->h.u.next;
- }
- break;
- }
- qp = qp->h.u.next;
- }
-
- H_UNLOCK(heapp);
- return;
-}
-
-/**
- * @brief Reports the heap status.
- * @note This function is meant to be used in the test suite, it should
- * not be really useful for the application code.
- * @note This function is not implemented when the @p CH_USE_MALLOC_HEAP
- * configuration option is used (it always returns zero).
- *
- * @param[in] heapp pointer to a heap descriptor or @p NULL in order to
- * access the default heap.
- * @param[in] sizep pointer to a variable that will receive the total
- * fragmented free space
- * @return The number of fragments in the heap.
- *
- * @api
- */
-size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) {
- union heap_header *qp;
- size_t n, sz;
-
- if (heapp == NULL)
- heapp = &default_heap;
-
- H_LOCK(heapp);
-
- sz = 0;
- for (n = 0, qp = &heapp->h_free; qp->h.u.next; n++, qp = qp->h.u.next)
- sz += qp->h.u.next->h.size;
- if (sizep)
- *sizep = sz;
-
- H_UNLOCK(heapp);
- return n;
-}
-
-#else /* CH_USE_MALLOC_HEAP */
-
-#include
-
-#if CH_USE_MUTEXES
-#define H_LOCK() chMtxLock(&hmtx)
-#define H_UNLOCK() chMtxUnlock()
-static Mutex hmtx;
-#elif CH_USE_SEMAPHORES
-#define H_LOCK() chSemWait(&hsem)
-#define H_UNLOCK() chSemSignal(&hsem)
-static Semaphore hsem;
-#endif
-
-void _heap_init(void) {
-
-#if CH_USE_MUTEXES
- chMtxInit(&hmtx);
-#else
- chSemInit(&hsem, 1);
-#endif
-}
-
-void *chHeapAlloc(MemoryHeap *heapp, size_t size) {
- void *p;
-
- chDbgCheck(heapp == NULL, "chHeapAlloc");
-
- H_LOCK();
- p = malloc(size);
- H_UNLOCK();
- return p;
-}
-
-void chHeapFree(void *p) {
-
- chDbgCheck(p != NULL, "chHeapFree");
-
- H_LOCK();
- free(p);
- H_UNLOCK();
-}
-
-size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) {
-
- chDbgCheck(heapp == NULL, "chHeapStatus");
-
- if (sizep)
- *sizep = 0;
- return 0;
-}
-
-#endif /* CH_USE_MALLOC_HEAP */
-
-#endif /* CH_USE_HEAP */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chlists.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chlists.c
deleted file mode 100644
index 4139a80784..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chlists.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chlists.c
- * @brief Thread queues/lists code.
- *
- * @addtogroup internals
- * @details All the functions present in this module, while public, are not
- * OS APIs and should not be directly used in the user applications
- * code.
- * @{
- */
-#include "ch.h"
-
-#if !CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
-/**
- * @brief Inserts a thread into a priority ordered queue.
- * @note The insertion is done by scanning the list from the highest
- * priority toward the lowest.
- *
- * @param[in] tp the pointer to the thread to be inserted in the list
- * @param[in] tqp the pointer to the threads list header
- *
- * @notapi
- */
-void prio_insert(Thread *tp, ThreadsQueue *tqp) {
-
- /* cp iterates over the queue.*/
- Thread *cp = (Thread *)tqp;
- do {
- /* Iterate to next thread in queue.*/
- cp = cp->p_next;
- /* Not end of queue? and cp has equal or higher priority than tp?.*/
- } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio));
- /* Insertion on p_prev.*/
- tp->p_next = cp;
- tp->p_prev = cp->p_prev;
- tp->p_prev->p_next = cp->p_prev = tp;
-}
-
-/**
- * @brief Inserts a Thread into a queue.
- *
- * @param[in] tp the pointer to the thread to be inserted in the list
- * @param[in] tqp the pointer to the threads list header
- *
- * @notapi
- */
-void queue_insert(Thread *tp, ThreadsQueue *tqp) {
-
- tp->p_next = (Thread *)tqp;
- tp->p_prev = tqp->p_prev;
- tp->p_prev->p_next = tqp->p_prev = tp;
-}
-
-/**
- * @brief Removes the first-out Thread from a queue and returns it.
- * @note If the queue is priority ordered then this function returns the
- * thread with the highest priority.
- *
- * @param[in] tqp the pointer to the threads list header
- * @return The removed thread pointer.
- *
- * @notapi
- */
-Thread *fifo_remove(ThreadsQueue *tqp) {
- Thread *tp = tqp->p_next;
-
- (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp;
- return tp;
-}
-
-/**
- * @brief Removes the last-out Thread from a queue and returns it.
- * @note If the queue is priority ordered then this function returns the
- * thread with the lowest priority.
- *
- * @param[in] tqp the pointer to the threads list header
- * @return The removed thread pointer.
- *
- * @notapi
- */
-Thread *lifo_remove(ThreadsQueue *tqp) {
- Thread *tp = tqp->p_prev;
-
- (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp;
- return tp;
-}
-
-/**
- * @brief Removes a Thread from a queue and returns it.
- * @details The thread is removed from the queue regardless of its relative
- * position and regardless the used insertion method.
- *
- * @param[in] tp the pointer to the thread to be removed from the queue
- * @return The removed thread pointer.
- *
- * @notapi
- */
-Thread *dequeue(Thread *tp) {
-
- tp->p_prev->p_next = tp->p_next;
- tp->p_next->p_prev = tp->p_prev;
- return tp;
-}
-
-/**
- * @brief Pushes a Thread on top of a stack list.
- *
- * @param[in] tp the pointer to the thread to be inserted in the list
- * @param[in] tlp the pointer to the threads list header
- *
- * @notapi
- */
-void list_insert(Thread *tp, ThreadsList *tlp) {
-
- tp->p_next = tlp->p_next;
- tlp->p_next = tp;
-}
-
-/**
- * @brief Pops a Thread from the top of a stack list and returns it.
- * @pre The list must be non-empty before calling this function.
- *
- * @param[in] tlp the pointer to the threads list header
- * @return The removed thread pointer.
- *
- * @notapi
- */
-Thread *list_remove(ThreadsList *tlp) {
-
- Thread *tp = tlp->p_next;
- tlp->p_next = tp->p_next;
- return tp;
-}
-#endif /* CH_OPTIMIZE_SPEED */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmboxes.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmboxes.c
deleted file mode 100644
index 1e8855b614..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmboxes.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmboxes.c
- * @brief Mailboxes code.
- *
- * @addtogroup mailboxes
- * @details Asynchronous messages.
- * Operation mode
- * A mailbox is an asynchronous communication mechanism.
- * Operations defined for mailboxes:
- * - Post: Posts a message on the mailbox in FIFO order.
- * - Post Ahead: Posts a message on the mailbox with urgent
- * priority.
- * - Fetch: A message is fetched from the mailbox and removed
- * from the queue.
- * - Reset: The mailbox is emptied and all the stored messages
- * are lost.
- * .
- * A message is a variable of type msg_t that is guaranteed to have
- * the same size of and be compatible with (data) pointers (anyway an
- * explicit cast is needed).
- * If larger messages need to be exchanged then a pointer to a
- * structure can be posted in the mailbox but the posting side has
- * no predefined way to know when the message has been processed. A
- * possible approach is to allocate memory (from a memory pool for
- * example) from the posting side and free it on the fetching side.
- * Another approach is to set a "done" flag into the structure pointed
- * by the message.
- * @pre In order to use the mailboxes APIs the @p CH_USE_MAILBOXES option
- * must be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MAILBOXES || defined(__DOXYGEN__)
-/**
- * @brief Initializes a Mailbox object.
- *
- * @param[out] mbp the pointer to the Mailbox structure to be initialized
- * @param[in] buf pointer to the messages buffer as an array of @p msg_t
- * @param[in] n number of elements in the buffer array
- *
- * @init
- */
-void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n) {
-
- chDbgCheck((mbp != NULL) && (buf != NULL) && (n > 0), "chMBInit");
-
- mbp->mb_buffer = mbp->mb_wrptr = mbp->mb_rdptr = buf;
- mbp->mb_top = &buf[n];
- chSemInit(&mbp->mb_emptysem, n);
- chSemInit(&mbp->mb_fullsem, 0);
-}
-
-/**
- * @brief Resets a Mailbox object.
- * @details All the waiting threads are resumed with status @p RDY_RESET and
- * the queued messages are lost.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- *
- * @api
- */
-void chMBReset(Mailbox *mbp) {
-
- chDbgCheck(mbp != NULL, "chMBReset");
-
- chSysLock();
- mbp->mb_wrptr = mbp->mb_rdptr = mbp->mb_buffer;
- chSemResetI(&mbp->mb_emptysem, mbp->mb_top - mbp->mb_buffer);
- chSemResetI(&mbp->mb_fullsem, 0);
- chSchRescheduleS();
- chSysUnlock();
-}
-
-/**
- * @brief Posts a message into a mailbox.
- * @details The invoking thread waits until a empty slot in the mailbox becomes
- * available or the specified time runs out.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[in] msg the message to be posted on the mailbox
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
- *
- * @api
- */
-msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t time) {
- msg_t rdymsg;
-
- chSysLock();
- rdymsg = chMBPostS(mbp, msg, time);
- chSysUnlock();
- return rdymsg;
-}
-
-/**
- * @brief Posts a message into a mailbox.
- * @details The invoking thread waits until a empty slot in the mailbox becomes
- * available or the specified time runs out.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[in] msg the message to be posted on the mailbox
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
- *
- * @sclass
- */
-msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t time) {
- msg_t rdymsg;
-
- chDbgCheckClassS();
- chDbgCheck(mbp != NULL, "chMBPostS");
-
- rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time);
- if (rdymsg == RDY_OK) {
- *mbp->mb_wrptr++ = msg;
- if (mbp->mb_wrptr >= mbp->mb_top)
- mbp->mb_wrptr = mbp->mb_buffer;
- chSemSignalI(&mbp->mb_fullsem);
- chSchRescheduleS();
- }
- return rdymsg;
-}
-
-/**
- * @brief Posts a message into a mailbox.
- * @details This variant is non-blocking, the function returns a timeout
- * condition if the queue is full.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[in] msg the message to be posted on the mailbox
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be
- * posted.
- *
- * @iclass
- */
-msg_t chMBPostI(Mailbox *mbp, msg_t msg) {
-
- chDbgCheckClassI();
- chDbgCheck(mbp != NULL, "chMBPostI");
-
- if (chSemGetCounterI(&mbp->mb_emptysem) <= 0)
- return RDY_TIMEOUT;
- chSemFastWaitI(&mbp->mb_emptysem);
- *mbp->mb_wrptr++ = msg;
- if (mbp->mb_wrptr >= mbp->mb_top)
- mbp->mb_wrptr = mbp->mb_buffer;
- chSemSignalI(&mbp->mb_fullsem);
- return RDY_OK;
-}
-
-/**
- * @brief Posts an high priority message into a mailbox.
- * @details The invoking thread waits until a empty slot in the mailbox becomes
- * available or the specified time runs out.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[in] msg the message to be posted on the mailbox
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
- *
- * @api
- */
-msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t time) {
- msg_t rdymsg;
-
- chSysLock();
- rdymsg = chMBPostAheadS(mbp, msg, time);
- chSysUnlock();
- return rdymsg;
-}
-
-/**
- * @brief Posts an high priority message into a mailbox.
- * @details The invoking thread waits until a empty slot in the mailbox becomes
- * available or the specified time runs out.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[in] msg the message to be posted on the mailbox
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
- *
- * @sclass
- */
-msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t time) {
- msg_t rdymsg;
-
- chDbgCheckClassS();
- chDbgCheck(mbp != NULL, "chMBPostAheadS");
-
- rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time);
- if (rdymsg == RDY_OK) {
- if (--mbp->mb_rdptr < mbp->mb_buffer)
- mbp->mb_rdptr = mbp->mb_top - 1;
- *mbp->mb_rdptr = msg;
- chSemSignalI(&mbp->mb_fullsem);
- chSchRescheduleS();
- }
- return rdymsg;
-}
-
-/**
- * @brief Posts an high priority message into a mailbox.
- * @details This variant is non-blocking, the function returns a timeout
- * condition if the queue is full.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[in] msg the message to be posted on the mailbox
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be
- * posted.
- *
- * @iclass
- */
-msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg) {
-
- chDbgCheckClassI();
- chDbgCheck(mbp != NULL, "chMBPostAheadI");
-
- if (chSemGetCounterI(&mbp->mb_emptysem) <= 0)
- return RDY_TIMEOUT;
- chSemFastWaitI(&mbp->mb_emptysem);
- if (--mbp->mb_rdptr < mbp->mb_buffer)
- mbp->mb_rdptr = mbp->mb_top - 1;
- *mbp->mb_rdptr = msg;
- chSemSignalI(&mbp->mb_fullsem);
- return RDY_OK;
-}
-
-/**
- * @brief Retrieves a message from a mailbox.
- * @details The invoking thread waits until a message is posted in the mailbox
- * or the specified time runs out.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[out] msgp pointer to a message variable for the received message
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly fetched.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
- *
- * @api
- */
-msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t time) {
- msg_t rdymsg;
-
- chSysLock();
- rdymsg = chMBFetchS(mbp, msgp, time);
- chSysUnlock();
- return rdymsg;
-}
-
-/**
- * @brief Retrieves a message from a mailbox.
- * @details The invoking thread waits until a message is posted in the mailbox
- * or the specified time runs out.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[out] msgp pointer to a message variable for the received message
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly fetched.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
- *
- * @sclass
- */
-msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t time) {
- msg_t rdymsg;
-
- chDbgCheckClassS();
- chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchS");
-
- rdymsg = chSemWaitTimeoutS(&mbp->mb_fullsem, time);
- if (rdymsg == RDY_OK) {
- *msgp = *mbp->mb_rdptr++;
- if (mbp->mb_rdptr >= mbp->mb_top)
- mbp->mb_rdptr = mbp->mb_buffer;
- chSemSignalI(&mbp->mb_emptysem);
- chSchRescheduleS();
- }
- return rdymsg;
-}
-
-/**
- * @brief Retrieves a message from a mailbox.
- * @details This variant is non-blocking, the function returns a timeout
- * condition if the queue is empty.
- *
- * @param[in] mbp the pointer to an initialized Mailbox object
- * @param[out] msgp pointer to a message variable for the received message
- * @return The operation status.
- * @retval RDY_OK if a message has been correctly fetched.
- * @retval RDY_TIMEOUT if the mailbox is empty and a message cannot be
- * fetched.
- *
- * @iclass
- */
-msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp) {
-
- chDbgCheckClassI();
- chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchI");
-
- if (chSemGetCounterI(&mbp->mb_fullsem) <= 0)
- return RDY_TIMEOUT;
- chSemFastWaitI(&mbp->mb_fullsem);
- *msgp = *mbp->mb_rdptr++;
- if (mbp->mb_rdptr >= mbp->mb_top)
- mbp->mb_rdptr = mbp->mb_buffer;
- chSemSignalI(&mbp->mb_emptysem);
- return RDY_OK;
-}
-#endif /* CH_USE_MAILBOXES */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmemcore.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmemcore.c
deleted file mode 100644
index 9a744627c5..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmemcore.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmemcore.c
- * @brief Core memory manager code.
- *
- * @addtogroup memcore
- * @details Core Memory Manager related APIs and services.
- * Operation mode
- * The core memory manager is a simplified allocator that only
- * allows to allocate memory blocks without the possibility to
- * free them.
- * This allocator is meant as a memory blocks provider for the
- * other allocators such as:
- * - C-Runtime allocator (through a compiler specific adapter module).
- * - Heap allocator (see @ref heaps).
- * - Memory pools allocator (see @ref pools).
- * .
- * By having a centralized memory provider the various allocators
- * can coexist and share the main memory.
- * This allocator, alone, is also useful for very simple
- * applications that just require a simple way to get memory
- * blocks.
- * @pre In order to use the core memory manager APIs the @p CH_USE_MEMCORE
- * option must be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MEMCORE || defined(__DOXYGEN__)
-
-static uint8_t *nextmem;
-static uint8_t *endmem;
-
-/**
- * @brief Low level memory manager initialization.
- *
- * @notapi
- */
-void _core_init(void) {
-#if CH_MEMCORE_SIZE == 0
- extern uint8_t __heap_base__[];
- extern uint8_t __heap_end__[];
- nextmem = (uint8_t *)MEM_ALIGN_NEXT(__heap_base__);
- endmem = (uint8_t *)MEM_ALIGN_PREV(__heap_end__);
-#else
- static stkalign_t buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE];
- nextmem = (uint8_t *)&buffer[0];
- endmem = (uint8_t *)&buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE];
-#endif
-}
-
-/**
- * @brief Allocates a memory block.
- * @details The size of the returned block is aligned to the alignment
- * type so it is not possible to allocate less
- * than MEM_ALIGN_SIZE.
- *
- * @param[in] size the size of the block to be allocated
- * @return A pointer to the allocated memory block.
- * @retval NULL allocation failed, core memory exhausted.
- *
- * @api
- */
-void *chCoreAlloc(size_t size) {
- void *p;
-
- chSysLock();
- p = chCoreAllocI(size);
- chSysUnlock();
- return p;
-}
-
-/**
- * @brief Allocates a memory block.
- * @details The size of the returned block is aligned to the alignment
- * type so it is not possible to allocate less than
- * MEM_ALIGN_SIZE.
- *
- * @param[in] size the size of the block to be allocated.
- * @return A pointer to the allocated memory block.
- * @retval NULL allocation failed, core memory exhausted.
- *
- * @iclass
- */
-void *chCoreAllocI(size_t size) {
- void *p;
-
- chDbgCheckClassI();
-
- size = MEM_ALIGN_NEXT(size);
- if ((size_t)(endmem - nextmem) < size)
- return NULL;
- p = nextmem;
- nextmem += size;
- return p;
-}
-
-/**
- * @brief Core memory status.
- *
- * @return The size, in bytes, of the free core memory.
- *
- * @api
- */
-size_t chCoreStatus(void) {
-
- return (size_t)(endmem - nextmem);
-}
-#endif /* CH_USE_MEMCORE */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmempools.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmempools.c
deleted file mode 100644
index 842e20aa34..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmempools.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmempools.c
- * @brief Memory Pools code.
- *
- * @addtogroup pools
- * @details Memory Pools related APIs and services.
- * Operation mode
- * The Memory Pools APIs allow to allocate/free fixed size objects in
- * constant time and reliably without memory fragmentation
- * problems.
- * Memory Pools do not enforce any alignment constraint on the
- * contained object however the objects must be properly aligned
- * to contain a pointer to void.
- * @pre In order to use the memory pools APIs the @p CH_USE_MEMPOOLS option
- * must be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MEMPOOLS || defined(__DOXYGEN__)
-/**
- * @brief Initializes an empty memory pool.
- *
- * @param[out] mp pointer to a @p MemoryPool structure
- * @param[in] size the size of the objects contained in this memory pool,
- * the minimum accepted size is the size of a pointer to
- * void.
- * @param[in] provider memory provider function for the memory pool or
- * @p NULL if the pool is not allowed to grow
- * automatically
- *
- * @init
- */
-void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider) {
-
- chDbgCheck((mp != NULL) && (size >= sizeof(void *)), "chPoolInit");
-
- mp->mp_next = NULL;
- mp->mp_object_size = size;
- mp->mp_provider = provider;
-}
-
-/**
- * @brief Loads a memory pool with an array of static objects.
- * @pre The memory pool must be already been initialized.
- * @pre The array elements must be of the right size for the specified
- * memory pool.
- * @post The memory pool contains the elements of the input array.
- *
- * @param[in] mp pointer to a @p MemoryPool structure
- * @param[in] p pointer to the array first element
- * @param[in] n number of elements in the array
- *
- * @api
- */
-void chPoolLoadArray(MemoryPool *mp, void *p, size_t n) {
-
- chDbgCheck((mp != NULL) && (n != 0), "chPoolLoadArray");
-
- while (n) {
- chPoolAdd(mp, p);
- p = (void *)(((uint8_t *)p) + mp->mp_object_size);
- n--;
- }
-}
-
-/**
- * @brief Allocates an object from a memory pool.
- * @pre The memory pool must be already been initialized.
- *
- * @param[in] mp pointer to a @p MemoryPool structure
- * @return The pointer to the allocated object.
- * @retval NULL if pool is empty.
- *
- * @iclass
- */
-void *chPoolAllocI(MemoryPool *mp) {
- void *objp;
-
- chDbgCheckClassI();
- chDbgCheck(mp != NULL, "chPoolAllocI");
-
- if ((objp = mp->mp_next) != NULL)
- mp->mp_next = mp->mp_next->ph_next;
- else if (mp->mp_provider != NULL)
- objp = mp->mp_provider(mp->mp_object_size);
- return objp;
-}
-
-/**
- * @brief Allocates an object from a memory pool.
- * @pre The memory pool must be already been initialized.
- *
- * @param[in] mp pointer to a @p MemoryPool structure
- * @return The pointer to the allocated object.
- * @retval NULL if pool is empty.
- *
- * @api
- */
-void *chPoolAlloc(MemoryPool *mp) {
- void *objp;
-
- chSysLock();
- objp = chPoolAllocI(mp);
- chSysUnlock();
- return objp;
-}
-
-/**
- * @brief Releases an object into a memory pool.
- * @pre The memory pool must be already been initialized.
- * @pre The freed object must be of the right size for the specified
- * memory pool.
- * @pre The object must be properly aligned to contain a pointer to void.
- *
- * @param[in] mp pointer to a @p MemoryPool structure
- * @param[in] objp the pointer to the object to be released
- *
- * @iclass
- */
-void chPoolFreeI(MemoryPool *mp, void *objp) {
- struct pool_header *php = objp;
-
- chDbgCheckClassI();
- chDbgCheck((mp != NULL) && (objp != NULL), "chPoolFreeI");
-
- php->ph_next = mp->mp_next;
- mp->mp_next = php;
-}
-
-/**
- * @brief Releases an object into a memory pool.
- * @pre The memory pool must be already been initialized.
- * @pre The freed object must be of the right size for the specified
- * memory pool.
- * @pre The object must be properly aligned to contain a pointer to void.
- *
- * @param[in] mp pointer to a @p MemoryPool structure
- * @param[in] objp the pointer to the object to be released
- *
- * @api
- */
-void chPoolFree(MemoryPool *mp, void *objp) {
-
- chSysLock();
- chPoolFreeI(mp, objp);
- chSysUnlock();
-}
-
-#endif /* CH_USE_MEMPOOLS */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmtx.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmtx.c
deleted file mode 100644
index 1fac622e53..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmtx.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chmtx.c
- * @brief Mutexes code.
- *
- * @addtogroup mutexes
- * @details Mutexes related APIs and services.
- *
- * Operation mode
- * A mutex is a threads synchronization object that can be in two
- * distinct states:
- * - Not owned (unlocked).
- * - Owned by a thread (locked).
- * .
- * Operations defined for mutexes:
- * - Lock: The mutex is checked, if the mutex is not owned by
- * some other thread then it is associated to the locking thread
- * else the thread is queued on the mutex in a list ordered by
- * priority.
- * - Unlock: The mutex is released by the owner and the highest
- * priority thread waiting in the queue, if any, is resumed and made
- * owner of the mutex.
- * .
- * Constraints
- * In ChibiOS/RT the Unlock operations are always performed in
- * lock-reverse order. The unlock API does not even have a parameter,
- * the mutex to unlock is selected from an internal, per-thread, stack
- * of owned mutexes. This both improves the performance and is
- * required for an efficient implementation of the priority
- * inheritance mechanism.
- *
- * The priority inversion problem
- * The mutexes in ChibiOS/RT implements the full priority
- * inheritance mechanism in order handle the priority inversion
- * problem.
- * When a thread is queued on a mutex, any thread, directly or
- * indirectly, holding the mutex gains the same priority of the
- * waiting thread (if their priority was not already equal or higher).
- * The mechanism works with any number of nested mutexes and any
- * number of involved threads. The algorithm complexity (worst case)
- * is N with N equal to the number of nested mutexes.
- * @pre In order to use the mutex APIs the @p CH_USE_MUTEXES option
- * must be enabled in @p chconf.h.
- * @post Enabling mutexes requires 5-12 (depending on the architecture)
- * extra bytes in the @p Thread structure.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-
-/**
- * @brief Initializes s @p Mutex structure.
- *
- * @param[out] mp pointer to a @p Mutex structure
- *
- * @init
- */
-void chMtxInit(Mutex *mp) {
-
- chDbgCheck(mp != NULL, "chMtxInit");
-
- queue_init(&mp->m_queue);
- mp->m_owner = NULL;
-}
-
-/**
- * @brief Locks the specified mutex.
- * @post The mutex is locked and inserted in the per-thread stack of owned
- * mutexes.
- *
- * @param[in] mp pointer to the @p Mutex structure
- *
- * @api
- */
-void chMtxLock(Mutex *mp) {
-
- chSysLock();
-
- chMtxLockS(mp);
-
- chSysUnlock();
-}
-
-/**
- * @brief Locks the specified mutex.
- * @post The mutex is locked and inserted in the per-thread stack of owned
- * mutexes.
- *
- * @param[in] mp pointer to the @p Mutex structure
- *
- * @sclass
- */
-void chMtxLockS(Mutex *mp) {
- Thread *ctp = currp;
-
- chDbgCheckClassS();
- chDbgCheck(mp != NULL, "chMtxLockS");
-
- /* Is the mutex already locked? */
- if (mp->m_owner != NULL) {
- /* Priority inheritance protocol; explores the thread-mutex dependencies
- boosting the priority of all the affected threads to equal the priority
- of the running thread requesting the mutex.*/
- Thread *tp = mp->m_owner;
- /* Does the running thread have higher priority than the mutex
- owning thread? */
- while (tp->p_prio < ctp->p_prio) {
- /* Make priority of thread tp match the running thread's priority.*/
- tp->p_prio = ctp->p_prio;
- /* The following states need priority queues reordering.*/
- switch (tp->p_state) {
- case THD_STATE_WTMTX:
- /* Re-enqueues the mutex owner with its new priority.*/
- prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp);
- tp = ((Mutex *)tp->p_u.wtobjp)->m_owner;
- continue;
-#if CH_USE_CONDVARS | \
- (CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY) | \
- (CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY)
-#if CH_USE_CONDVARS
- case THD_STATE_WTCOND:
-#endif
-#if CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY
- case THD_STATE_WTSEM:
-#endif
-#if CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY
- case THD_STATE_SNDMSGQ:
-#endif
- /* Re-enqueues tp with its new priority on the queue.*/
- prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp);
- break;
-#endif
- case THD_STATE_READY:
-#if CH_DBG_ENABLE_ASSERTS
- /* Prevents an assertion in chSchReadyI().*/
- tp->p_state = THD_STATE_CURRENT;
-#endif
- /* Re-enqueues tp with its new priority on the ready list.*/
- chSchReadyI(dequeue(tp));
- break;
- }
- break;
- }
- /* Sleep on the mutex.*/
- prio_insert(ctp, &mp->m_queue);
- ctp->p_u.wtobjp = mp;
- chSchGoSleepS(THD_STATE_WTMTX);
- /* It is assumed that the thread performing the unlock operation assigns
- the mutex to this thread.*/
- chDbgAssert(mp->m_owner == ctp, "chMtxLockS(), #1", "not owner");
- chDbgAssert(ctp->p_mtxlist == mp, "chMtxLockS(), #2", "not owned");
- }
- else {
- /* It was not owned, inserted in the owned mutexes list.*/
- mp->m_owner = ctp;
- mp->m_next = ctp->p_mtxlist;
- ctp->p_mtxlist = mp;
- }
-}
-
-/**
- * @brief Tries to lock a mutex.
- * @details This function attempts to lock a mutex, if the mutex is already
- * locked by another thread then the function exits without waiting.
- * @post The mutex is locked and inserted in the per-thread stack of owned
- * mutexes.
- * @note This function does not have any overhead related to the
- * priority inheritance mechanism because it does not try to
- * enter a sleep state.
- *
- * @param[in] mp pointer to the @p Mutex structure
- * @return The operation status.
- * @retval TRUE if the mutex has been successfully acquired
- * @retval FALSE if the lock attempt failed.
- *
- * @api
- */
-bool_t chMtxTryLock(Mutex *mp) {
- bool_t b;
-
- chSysLock();
-
- b = chMtxTryLockS(mp);
-
- chSysUnlock();
- return b;
-}
-
-/**
- * @brief Tries to lock a mutex.
- * @details This function attempts to lock a mutex, if the mutex is already
- * taken by another thread then the function exits without waiting.
- * @post The mutex is locked and inserted in the per-thread stack of owned
- * mutexes.
- * @note This function does not have any overhead related to the
- * priority inheritance mechanism because it does not try to
- * enter a sleep state.
- *
- * @param[in] mp pointer to the @p Mutex structure
- * @return The operation status.
- * @retval TRUE if the mutex has been successfully acquired
- * @retval FALSE if the lock attempt failed.
- *
- * @sclass
- */
-bool_t chMtxTryLockS(Mutex *mp) {
-
- chDbgCheckClassS();
- chDbgCheck(mp != NULL, "chMtxTryLockS");
-
- if (mp->m_owner != NULL)
- return FALSE;
- mp->m_owner = currp;
- mp->m_next = currp->p_mtxlist;
- currp->p_mtxlist = mp;
- return TRUE;
-}
-
-/**
- * @brief Unlocks the next owned mutex in reverse lock order.
- * @pre The invoking thread must have at least one owned mutex.
- * @post The mutex is unlocked and removed from the per-thread stack of
- * owned mutexes.
- *
- * @return A pointer to the unlocked mutex.
- *
- * @api
- */
-Mutex *chMtxUnlock(void) {
- Thread *ctp = currp;
- Mutex *ump, *mp;
-
- chSysLock();
- chDbgAssert(ctp->p_mtxlist != NULL,
- "chMtxUnlock(), #1",
- "owned mutexes list empty");
- chDbgAssert(ctp->p_mtxlist->m_owner == ctp,
- "chMtxUnlock(), #2",
- "ownership failure");
- /* Removes the top Mutex from the Thread's owned mutexes list and marks it
- as not owned.*/
- ump = ctp->p_mtxlist;
- ctp->p_mtxlist = ump->m_next;
- /* If a thread is waiting on the mutex then the fun part begins.*/
- if (chMtxQueueNotEmptyS(ump)) {
- Thread *tp;
-
- /* Recalculates the optimal thread priority by scanning the owned
- mutexes list.*/
- tprio_t newprio = ctp->p_realprio;
- mp = ctp->p_mtxlist;
- while (mp != NULL) {
- /* If the highest priority thread waiting in the mutexes list has a
- greater priority than the current thread base priority then the final
- priority will have at least that priority.*/
- if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio))
- newprio = mp->m_queue.p_next->p_prio;
- mp = mp->m_next;
- }
- /* Assigns to the current thread the highest priority among all the
- waiting threads.*/
- ctp->p_prio = newprio;
- /* Awakens the highest priority thread waiting for the unlocked mutex and
- assigns the mutex to it.*/
- tp = fifo_remove(&ump->m_queue);
- ump->m_owner = tp;
- ump->m_next = tp->p_mtxlist;
- tp->p_mtxlist = ump;
- chSchWakeupS(tp, RDY_OK);
- }
- else
- ump->m_owner = NULL;
- chSysUnlock();
- return ump;
-}
-
-/**
- * @brief Unlocks the next owned mutex in reverse lock order.
- * @pre The invoking thread must have at least one owned mutex.
- * @post The mutex is unlocked and removed from the per-thread stack of
- * owned mutexes.
- * @post This function does not reschedule so a call to a rescheduling
- * function must be performed before unlocking the kernel.
- *
- * @return A pointer to the unlocked mutex.
- *
- * @sclass
- */
-Mutex *chMtxUnlockS(void) {
- Thread *ctp = currp;
- Mutex *ump, *mp;
-
- chDbgCheckClassS();
- chDbgAssert(ctp->p_mtxlist != NULL,
- "chMtxUnlockS(), #1",
- "owned mutexes list empty");
- chDbgAssert(ctp->p_mtxlist->m_owner == ctp,
- "chMtxUnlockS(), #2",
- "ownership failure");
-
- /* Removes the top Mutex from the owned mutexes list and marks it as not
- owned.*/
- ump = ctp->p_mtxlist;
- ctp->p_mtxlist = ump->m_next;
- /* If a thread is waiting on the mutex then the fun part begins.*/
- if (chMtxQueueNotEmptyS(ump)) {
- Thread *tp;
-
- /* Recalculates the optimal thread priority by scanning the owned
- mutexes list.*/
- tprio_t newprio = ctp->p_realprio;
- mp = ctp->p_mtxlist;
- while (mp != NULL) {
- /* If the highest priority thread waiting in the mutexes list has a
- greater priority than the current thread base priority then the final
- priority will have at least that priority.*/
- if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio))
- newprio = mp->m_queue.p_next->p_prio;
- mp = mp->m_next;
- }
- ctp->p_prio = newprio;
- /* Awakens the highest priority thread waiting for the unlocked mutex and
- assigns the mutex to it.*/
- tp = fifo_remove(&ump->m_queue);
- ump->m_owner = tp;
- ump->m_next = tp->p_mtxlist;
- tp->p_mtxlist = ump;
- chSchReadyI(tp);
- }
- else
- ump->m_owner = NULL;
- return ump;
-}
-
-/**
- * @brief Unlocks all the mutexes owned by the invoking thread.
- * @post The stack of owned mutexes is emptied and all the found
- * mutexes are unlocked.
- * @note This function is MUCH MORE efficient than releasing the
- * mutexes one by one and not just because the call overhead,
- * this function does not have any overhead related to the priority
- * inheritance mechanism.
- *
- * @api
- */
-void chMtxUnlockAll(void) {
- Thread *ctp = currp;
-
- chSysLock();
- if (ctp->p_mtxlist != NULL) {
- do {
- Mutex *ump = ctp->p_mtxlist;
- ctp->p_mtxlist = ump->m_next;
- if (chMtxQueueNotEmptyS(ump)) {
- Thread *tp = fifo_remove(&ump->m_queue);
- ump->m_owner = tp;
- ump->m_next = tp->p_mtxlist;
- tp->p_mtxlist = ump;
- chSchReadyI(tp);
- }
- else
- ump->m_owner = NULL;
- } while (ctp->p_mtxlist != NULL);
- ctp->p_prio = ctp->p_realprio;
- chSchRescheduleS();
- }
- chSysUnlock();
-}
-
-#endif /* CH_USE_MUTEXES */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chqueues.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chqueues.c
deleted file mode 100644
index e8a33cf753..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chqueues.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chqueues.c
- * @brief I/O Queues code.
- *
- * @addtogroup io_queues
- * @details ChibiOS/RT queues are mostly used in serial-like device drivers.
- * The device drivers are usually designed to have a lower side
- * (lower driver, it is usually an interrupt service routine) and an
- * upper side (upper driver, accessed by the application threads).
- * There are several kind of queues:
- * - Input queue, unidirectional queue where the writer is the
- * lower side and the reader is the upper side.
- * - Output queue, unidirectional queue where the writer is the
- * upper side and the reader is the lower side.
- * - Full duplex queue, bidirectional queue. Full duplex queues
- * are implemented by pairing an input queue and an output queue
- * together.
- * .
- * @pre In order to use the I/O queues the @p CH_USE_QUEUES option must
- * be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_QUEUES || defined(__DOXYGEN__)
-
-/**
- * @brief Puts the invoking thread into the queue's threads queue.
- *
- * @param[out] qp pointer to an @p GenericQueue structure
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return A message specifying how the invoking thread has been
- * released from threads queue.
- * @retval Q_OK is the normal exit, thread signaled.
- * @retval Q_RESET if the queue has been reset.
- * @retval Q_TIMEOUT if the queue operation timed out.
- */
-static msg_t qwait(GenericQueue *qp, systime_t time) {
-
- if (TIME_IMMEDIATE == time)
- return Q_TIMEOUT;
- currp->p_u.wtobjp = qp;
- queue_insert(currp, &qp->q_waiting);
- return chSchGoSleepTimeoutS(THD_STATE_WTQUEUE, time);
-}
-
-/**
- * @brief Initializes an input queue.
- * @details A Semaphore is internally initialized and works as a counter of
- * the bytes contained in the queue.
- * @note The callback is invoked from within the S-Locked system state,
- * see @ref system_states.
- *
- * @param[out] iqp pointer to an @p InputQueue structure
- * @param[in] bp pointer to a memory area allocated as queue buffer
- * @param[in] size size of the queue buffer
- * @param[in] infy pointer to a callback function that is invoked when
- * data is read from the queue. The value can be @p NULL.
- * @param[in] link application defined pointer
- *
- * @init
- */
-void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy,
- void *link) {
-
- queue_init(&iqp->q_waiting);
- iqp->q_counter = 0;
- iqp->q_buffer = iqp->q_rdptr = iqp->q_wrptr = bp;
- iqp->q_top = bp + size;
- iqp->q_notify = infy;
- iqp->q_link = link;
-}
-
-/**
- * @brief Resets an input queue.
- * @details All the data in the input queue is erased and lost, any waiting
- * thread is resumed with status @p Q_RESET.
- * @note A reset operation can be used by a low level driver in order to
- * obtain immediate attention from the high level layers.
- *
- * @param[in] iqp pointer to an @p InputQueue structure
- *
- * @iclass
- */
-void chIQResetI(InputQueue *iqp) {
-
- chDbgCheckClassI();
-
- iqp->q_rdptr = iqp->q_wrptr = iqp->q_buffer;
- iqp->q_counter = 0;
- while (notempty(&iqp->q_waiting))
- chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_RESET;
-}
-
-/**
- * @brief Input queue write.
- * @details A byte value is written into the low end of an input queue.
- *
- * @param[in] iqp pointer to an @p InputQueue structure
- * @param[in] b the byte value to be written in the queue
- * @return The operation status.
- * @retval Q_OK if the operation has been completed with success.
- * @retval Q_FULL if the queue is full and the operation cannot be
- * completed.
- *
- * @iclass
- */
-msg_t chIQPutI(InputQueue *iqp, uint8_t b) {
-
- chDbgCheckClassI();
-
- if (chIQIsFullI(iqp))
- return Q_FULL;
-
- iqp->q_counter++;
- *iqp->q_wrptr++ = b;
- if (iqp->q_wrptr >= iqp->q_top)
- iqp->q_wrptr = iqp->q_buffer;
-
- if (notempty(&iqp->q_waiting))
- chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
-
- return Q_OK;
-}
-
-/**
- * @brief Input queue read with timeout.
- * @details This function reads a byte value from an input queue. If the queue
- * is empty then the calling thread is suspended until a byte arrives
- * in the queue or a timeout occurs.
- * @note The callback is invoked before reading the character from the
- * buffer or before entering the state @p THD_STATE_WTQUEUE.
- *
- * @param[in] iqp pointer to an @p InputQueue structure
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return A byte value from the queue.
- * @retval Q_TIMEOUT if the specified time expired.
- * @retval Q_RESET if the queue has been reset.
- *
- * @api
- */
-msg_t chIQGetTimeout(InputQueue *iqp, systime_t time) {
- uint8_t b;
-
- chSysLock();
- if (iqp->q_notify)
- iqp->q_notify(iqp);
-
- while (chIQIsEmptyI(iqp)) {
- msg_t msg;
- if ((msg = qwait((GenericQueue *)iqp, time)) < Q_OK) {
- chSysUnlock();
- return msg;
- }
- }
-
- iqp->q_counter--;
- b = *iqp->q_rdptr++;
- if (iqp->q_rdptr >= iqp->q_top)
- iqp->q_rdptr = iqp->q_buffer;
-
- chSysUnlock();
- return b;
-}
-
-/**
- * @brief Input queue read with timeout.
- * @details The function reads data from an input queue into a buffer. The
- * operation completes when the specified amount of data has been
- * transferred or after the specified timeout or if the queue has
- * been reset.
- * @note The function is not atomic, if you need atomicity it is suggested
- * to use a semaphore or a mutex for mutual exclusion.
- * @note The callback is invoked before reading each character from the
- * buffer or before entering the state @p THD_STATE_WTQUEUE.
- *
- * @param[in] iqp pointer to an @p InputQueue structure
- * @param[out] bp pointer to the data buffer
- * @param[in] n the maximum amount of data to be transferred, the
- * value 0 is reserved
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The number of bytes effectively transferred.
- *
- * @api
- */
-size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp,
- size_t n, systime_t time) {
- qnotify_t nfy = iqp->q_notify;
- size_t r = 0;
-
- chDbgCheck(n > 0, "chIQReadTimeout");
-
- chSysLock();
- while (TRUE) {
- if (nfy)
- nfy(iqp);
-
- while (chIQIsEmptyI(iqp)) {
- if (qwait((GenericQueue *)iqp, time) != Q_OK) {
- chSysUnlock();
- return r;
- }
- }
-
- iqp->q_counter--;
- *bp++ = *iqp->q_rdptr++;
- if (iqp->q_rdptr >= iqp->q_top)
- iqp->q_rdptr = iqp->q_buffer;
-
- chSysUnlock(); /* Gives a preemption chance in a controlled point.*/
- r++;
- if (--n == 0)
- return r;
-
- chSysLock();
- }
-}
-
-/**
- * @brief Initializes an output queue.
- * @details A Semaphore is internally initialized and works as a counter of
- * the free bytes in the queue.
- * @note The callback is invoked from within the S-Locked system state,
- * see @ref system_states.
- *
- * @param[out] oqp pointer to an @p OutputQueue structure
- * @param[in] bp pointer to a memory area allocated as queue buffer
- * @param[in] size size of the queue buffer
- * @param[in] onfy pointer to a callback function that is invoked when
- * data is written to the queue. The value can be @p NULL.
- * @param[in] link application defined pointer
- *
- * @init
- */
-void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy,
- void *link) {
-
- queue_init(&oqp->q_waiting);
- oqp->q_counter = size;
- oqp->q_buffer = oqp->q_rdptr = oqp->q_wrptr = bp;
- oqp->q_top = bp + size;
- oqp->q_notify = onfy;
- oqp->q_link = link;
-}
-
-/**
- * @brief Resets an output queue.
- * @details All the data in the output queue is erased and lost, any waiting
- * thread is resumed with status @p Q_RESET.
- * @note A reset operation can be used by a low level driver in order to
- * obtain immediate attention from the high level layers.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure
- *
- * @iclass
- */
-void chOQResetI(OutputQueue *oqp) {
-
- chDbgCheckClassI();
-
- oqp->q_rdptr = oqp->q_wrptr = oqp->q_buffer;
- oqp->q_counter = chQSizeI(oqp);
- while (notempty(&oqp->q_waiting))
- chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_RESET;
-}
-
-/**
- * @brief Output queue write with timeout.
- * @details This function writes a byte value to an output queue. If the queue
- * is full then the calling thread is suspended until there is space
- * in the queue or a timeout occurs.
- * @note The callback is invoked after writing the character into the
- * buffer.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure
- * @param[in] b the byte value to be written in the queue
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval Q_OK if the operation succeeded.
- * @retval Q_TIMEOUT if the specified time expired.
- * @retval Q_RESET if the queue has been reset.
- *
- * @api
- */
-msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time) {
-
- chSysLock();
- while (chOQIsFullI(oqp)) {
- msg_t msg;
-
- if ((msg = qwait((GenericQueue *)oqp, time)) < Q_OK) {
- chSysUnlock();
- return msg;
- }
- }
-
- oqp->q_counter--;
- *oqp->q_wrptr++ = b;
- if (oqp->q_wrptr >= oqp->q_top)
- oqp->q_wrptr = oqp->q_buffer;
-
- if (oqp->q_notify)
- oqp->q_notify(oqp);
-
- chSysUnlock();
- return Q_OK;
-}
-
-/**
- * @brief Output queue read.
- * @details A byte value is read from the low end of an output queue.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure
- * @return The byte value from the queue.
- * @retval Q_EMPTY if the queue is empty.
- *
- * @iclass
- */
-msg_t chOQGetI(OutputQueue *oqp) {
- uint8_t b;
-
- chDbgCheckClassI();
-
- if (chOQIsEmptyI(oqp))
- return Q_EMPTY;
-
- oqp->q_counter++;
- b = *oqp->q_rdptr++;
- if (oqp->q_rdptr >= oqp->q_top)
- oqp->q_rdptr = oqp->q_buffer;
-
- if (notempty(&oqp->q_waiting))
- chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
-
- return b;
-}
-
-/**
- * @brief Output queue write with timeout.
- * @details The function writes data from a buffer to an output queue. The
- * operation completes when the specified amount of data has been
- * transferred or after the specified timeout or if the queue has
- * been reset.
- * @note The function is not atomic, if you need atomicity it is suggested
- * to use a semaphore or a mutex for mutual exclusion.
- * @note The callback is invoked after writing each character into the
- * buffer.
- *
- * @param[in] oqp pointer to an @p OutputQueue structure
- * @param[out] bp pointer to the data buffer
- * @param[in] n the maximum amount of data to be transferred, the
- * value 0 is reserved
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The number of bytes effectively transferred.
- *
- * @api
- */
-size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp,
- size_t n, systime_t time) {
- qnotify_t nfy = oqp->q_notify;
- size_t w = 0;
-
- chDbgCheck(n > 0, "chOQWriteTimeout");
-
- chSysLock();
- while (TRUE) {
- while (chOQIsFullI(oqp)) {
- if (qwait((GenericQueue *)oqp, time) != Q_OK) {
- chSysUnlock();
- return w;
- }
- }
- oqp->q_counter--;
- *oqp->q_wrptr++ = *bp++;
- if (oqp->q_wrptr >= oqp->q_top)
- oqp->q_wrptr = oqp->q_buffer;
-
- if (nfy)
- nfy(oqp);
-
- chSysUnlock(); /* Gives a preemption chance in a controlled point.*/
- w++;
- if (--n == 0)
- return w;
- chSysLock();
- }
-}
-#endif /* CH_USE_QUEUES */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chregistry.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chregistry.c
deleted file mode 100644
index 05818d95b4..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chregistry.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chregistry.c
- * @brief Threads registry code.
- *
- * @addtogroup registry
- * @details Threads Registry related APIs and services.
- *
- * Operation mode
- * The Threads Registry is a double linked list that holds all the
- * active threads in the system.
- * Operations defined for the registry:
- * - First, returns the first, in creation order, active thread
- * in the system.
- * - Next, returns the next, in creation order, active thread
- * in the system.
- * .
- * The registry is meant to be mainly a debug feature, for example,
- * using the registry a debugger can enumerate the active threads
- * in any given moment or the shell can print the active threads
- * and their state.
- * Another possible use is for centralized threads memory management,
- * terminating threads can pulse an event source and an event handler
- * can perform a scansion of the registry in order to recover the
- * memory.
- * @pre In order to use the threads registry the @p CH_USE_REGISTRY option
- * must be enabled in @p chconf.h.
- * @{
- */
-#include "ch.h"
-
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-
-#define _offsetof(st, m) \
- ((size_t)((char *)&((st *)0)->m - (char *)0))
-
-/*
- * OS signature in ROM plus debug-related information.
- */
-ROMCONST chdebug_t ch_debug = {
- "main",
- (uint8_t)0,
- (uint8_t)sizeof (chdebug_t),
- (uint16_t)((CH_KERNEL_MAJOR << 11) |
- (CH_KERNEL_MINOR << 6) |
- (CH_KERNEL_PATCH) << 0),
- (uint8_t)sizeof (void *),
- (uint8_t)sizeof (systime_t),
- (uint8_t)sizeof (Thread),
- (uint8_t)_offsetof(Thread, p_prio),
- (uint8_t)_offsetof(Thread, p_ctx),
- (uint8_t)_offsetof(Thread, p_newer),
- (uint8_t)_offsetof(Thread, p_older),
- (uint8_t)_offsetof(Thread, p_name),
-#if CH_DBG_ENABLE_STACK_CHECK
- (uint8_t)_offsetof(Thread, p_stklimit),
-#else
- (uint8_t)0,
-#endif
- (uint8_t)_offsetof(Thread, p_state),
- (uint8_t)_offsetof(Thread, p_flags),
-#if CH_USE_DYNAMIC
- (uint8_t)_offsetof(Thread, p_refs),
-#else
- (uint8_t)0,
-#endif
-#if CH_TIME_QUANTUM > 0
- (uint8_t)_offsetof(Thread, p_preempt),
-#else
- (uint8_t)0,
-#endif
-#if CH_DBG_THREADS_PROFILING
- (uint8_t)_offsetof(Thread, p_time)
-#else
- (uint8_t)0
-#endif
-};
-
-/**
- * @brief Returns the first thread in the system.
- * @details Returns the most ancient thread in the system, usually this is
- * the main thread unless it terminated. A reference is added to the
- * returned thread in order to make sure its status is not lost.
- * @note This function cannot return @p NULL because there is always at
- * least one thread in the system.
- *
- * @return A reference to the most ancient thread.
- *
- * @api
- */
-Thread *chRegFirstThread(void) {
- Thread *tp;
-
- chSysLock();
- tp = rlist.r_newer;
-#if CH_USE_DYNAMIC
- tp->p_refs++;
-#endif
- chSysUnlock();
- return tp;
-}
-
-/**
- * @brief Returns the thread next to the specified one.
- * @details The reference counter of the specified thread is decremented and
- * the reference counter of the returned thread is incremented.
- *
- * @param[in] tp pointer to the thread
- * @return A reference to the next thread.
- * @retval NULL if there is no next thread.
- *
- * @api
- */
-Thread *chRegNextThread(Thread *tp) {
- Thread *ntp;
-
- chSysLock();
- ntp = tp->p_newer;
- if (ntp == (Thread *)&rlist)
- ntp = NULL;
-#if CH_USE_DYNAMIC
- else {
- chDbgAssert(ntp->p_refs < 255, "chRegNextThread(), #1",
- "too many references");
- ntp->p_refs++;
- }
-#endif
- chSysUnlock();
-#if CH_USE_DYNAMIC
- chThdRelease(tp);
-#endif
- return ntp;
-}
-
-#endif /* CH_USE_REGISTRY */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chschd.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chschd.c
deleted file mode 100644
index a725f07ad1..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chschd.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chschd.c
- * @brief Scheduler code.
- *
- * @addtogroup scheduler
- * @details This module provides the default portable scheduler code,
- * scheduler functions can be individually captured by the port
- * layer in order to provide architecture optimized equivalents.
- * When a function is captured its default code is not built into
- * the OS image, the optimized version is included instead.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief Ready list header.
- */
-#if !defined(PORT_OPTIMIZED_RLIST_VAR) || defined(__DOXYGEN__)
-ReadyList rlist;
-#endif /* !defined(PORT_OPTIMIZED_RLIST_VAR) */
-
-/**
- * @brief Scheduler initialization.
- *
- * @notapi
- */
-void _scheduler_init(void) {
-
- queue_init(&rlist.r_queue);
- rlist.r_prio = NOPRIO;
-#if CH_USE_REGISTRY
- rlist.r_newer = rlist.r_older = (Thread *)&rlist;
-#endif
-}
-
-/**
- * @brief Inserts a thread in the Ready List.
- * @details The thread is positioned behind all threads with higher or equal
- * priority.
- * @pre The thread must not be already inserted in any list through its
- * @p p_next and @p p_prev or list corruption would occur.
- * @post This function does not reschedule so a call to a rescheduling
- * function must be performed before unlocking the kernel. Note that
- * interrupt handlers always reschedule on exit so an explicit
- * reschedule must not be performed in ISRs.
- *
- * @param[in] tp the thread to be made ready
- * @return The thread pointer.
- *
- * @iclass
- */
-#if !defined(PORT_OPTIMIZED_READYI) || defined(__DOXYGEN__)
-Thread *chSchReadyI(Thread *tp) {
- Thread *cp;
-
- chDbgCheckClassI();
-
- /* Integrity checks.*/
- chDbgAssert((tp->p_state != THD_STATE_READY) &&
- (tp->p_state != THD_STATE_FINAL),
- "chSchReadyI(), #1",
- "invalid state");
-
- tp->p_state = THD_STATE_READY;
- cp = (Thread *)&rlist.r_queue;
- do {
- cp = cp->p_next;
- } while (cp->p_prio >= tp->p_prio);
- /* Insertion on p_prev.*/
- tp->p_next = cp;
- tp->p_prev = cp->p_prev;
- tp->p_prev->p_next = cp->p_prev = tp;
- return tp;
-}
-#endif /* !defined(PORT_OPTIMIZED_READYI) */
-
-/**
- * @brief Puts the current thread to sleep into the specified state.
- * @details The thread goes into a sleeping state. The possible
- * @ref thread_states are defined into @p threads.h.
- *
- * @param[in] newstate the new thread state
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_GOSLEEPS) || defined(__DOXYGEN__)
-void chSchGoSleepS(tstate_t newstate) {
- Thread *otp;
-
- chDbgCheckClassS();
-
- (otp = currp)->p_state = newstate;
-#if CH_TIME_QUANTUM > 0
- /* The thread is renouncing its remaining time slices so it will have a new
- time quantum when it will wakeup.*/
- otp->p_preempt = CH_TIME_QUANTUM;
-#endif
- setcurrp(fifo_remove(&rlist.r_queue));
- currp->p_state = THD_STATE_CURRENT;
- chSysSwitch(currp, otp);
-}
-#endif /* !defined(PORT_OPTIMIZED_GOSLEEPS) */
-
-#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) || defined(__DOXYGEN__)
-/*
- * Timeout wakeup callback.
- */
-static void wakeup(void *p) {
- Thread *tp = (Thread *)p;
-
- chSysLockFromIsr();
- switch (tp->p_state) {
- case THD_STATE_READY:
- /* Handling the special case where the thread has been made ready by
- another thread with higher priority.*/
- chSysUnlockFromIsr();
- return;
-#if CH_USE_SEMAPHORES || CH_USE_QUEUES || \
- (CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT)
-#if CH_USE_SEMAPHORES
- case THD_STATE_WTSEM:
- chSemFastSignalI((Semaphore *)tp->p_u.wtobjp);
- /* Falls into, intentional. */
-#endif
-#if CH_USE_QUEUES
- case THD_STATE_WTQUEUE:
-#endif
-#if CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT
- case THD_STATE_WTCOND:
-#endif
- /* States requiring dequeuing.*/
- dequeue(tp);
-#endif
- }
- tp->p_u.rdymsg = RDY_TIMEOUT;
- chSchReadyI(tp);
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief Puts the current thread to sleep into the specified state with
- * timeout specification.
- * @details The thread goes into a sleeping state, if it is not awakened
- * explicitly within the specified timeout then it is forcibly
- * awakened with a @p RDY_TIMEOUT low level message. The possible
- * @ref thread_states are defined into @p threads.h.
- *
- * @param[in] newstate the new thread state
- * @param[in] time the number of ticks before the operation timeouts, the
- * special values are handled as follow:
- * - @a TIME_INFINITE the thread enters an infinite sleep
- * state, this is equivalent to invoking
- * @p chSchGoSleepS() but, of course, less efficient.
- * - @a TIME_IMMEDIATE this value is not allowed.
- * .
- * @return The wakeup message.
- * @retval RDY_TIMEOUT if a timeout occurs.
- *
- * @sclass
- */
-msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) {
-
- chDbgCheckClassS();
-
- if (TIME_INFINITE != time) {
- VirtualTimer vt;
-
- chVTSetI(&vt, time, wakeup, currp);
- chSchGoSleepS(newstate);
- if (chVTIsArmedI(&vt))
- chVTResetI(&vt);
- }
- else
- chSchGoSleepS(newstate);
- return currp->p_u.rdymsg;
-}
-#endif /* !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) */
-
-/**
- * @brief Wakes up a thread.
- * @details The thread is inserted into the ready list or immediately made
- * running depending on its relative priority compared to the current
- * thread.
- * @pre The thread must not be already inserted in any list through its
- * @p p_next and @p p_prev or list corruption would occur.
- * @note It is equivalent to a @p chSchReadyI() followed by a
- * @p chSchRescheduleS() but much more efficient.
- * @note The function assumes that the current thread has the highest
- * priority.
- *
- * @param[in] ntp the Thread to be made ready
- * @param[in] msg message to the awakened thread
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_WAKEUPS) || defined(__DOXYGEN__)
-void chSchWakeupS(Thread *ntp, msg_t msg) {
-
- chDbgCheckClassS();
-
- ntp->p_u.rdymsg = msg;
- /* If the waken thread has a not-greater priority than the current
- one then it is just inserted in the ready list else it made
- running immediately and the invoking thread goes in the ready
- list instead.*/
- if (ntp->p_prio <= currp->p_prio)
- chSchReadyI(ntp);
- else {
- Thread *otp = chSchReadyI(currp);
- setcurrp(ntp);
- ntp->p_state = THD_STATE_CURRENT;
- chSysSwitch(ntp, otp);
- }
-}
-#endif /* !defined(PORT_OPTIMIZED_WAKEUPS) */
-
-/**
- * @brief Performs a reschedule if a higher priority thread is runnable.
- * @details If a thread with a higher priority than the current thread is in
- * the ready list then make the higher priority thread running.
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_RESCHEDULES) || defined(__DOXYGEN__)
-void chSchRescheduleS(void) {
-
- chDbgCheckClassS();
-
- if (chSchIsRescRequiredI())
- chSchDoRescheduleAhead();
-}
-#endif /* !defined(PORT_OPTIMIZED_RESCHEDULES) */
-
-/**
- * @brief Evaluates if preemption is required.
- * @details The decision is taken by comparing the relative priorities and
- * depending on the state of the round robin timeout counter.
- * @note Not a user function, it is meant to be invoked by the scheduler
- * itself or from within the port layer.
- *
- * @retval TRUE if there is a thread that must go in running state
- * immediately.
- * @retval FALSE if preemption is not required.
- *
- * @special
- */
-#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) || defined(__DOXYGEN__)
-bool_t chSchIsPreemptionRequired(void) {
- tprio_t p1 = firstprio(&rlist.r_queue);
- tprio_t p2 = currp->p_prio;
-#if CH_TIME_QUANTUM > 0
- /* If the running thread has not reached its time quantum, reschedule only
- if the first thread on the ready queue has a higher priority.
- Otherwise, if the running thread has used up its time quantum, reschedule
- if the first thread on the ready queue has equal or higher priority.*/
- return currp->p_preempt ? p1 > p2 : p1 >= p2;
-#else
- /* If the round robin preemption feature is not enabled then performs a
- simpler comparison.*/
- return p1 > p2;
-#endif
-}
-#endif /* !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) */
-
-/**
- * @brief Switches to the first thread on the runnable queue.
- * @details The current thread is positioned in the ready list behind all
- * threads having the same priority. The thread regains its time
- * quantum.
- * @note Not a user function, it is meant to be invoked by the scheduler
- * itself or from within the port layer.
- *
- * @special
- */
-#if !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) || defined(__DOXYGEN__)
-void chSchDoRescheduleBehind(void) {
- Thread *otp;
-
- otp = currp;
- /* Picks the first thread from the ready queue and makes it current.*/
- setcurrp(fifo_remove(&rlist.r_queue));
- currp->p_state = THD_STATE_CURRENT;
-#if CH_TIME_QUANTUM > 0
- otp->p_preempt = CH_TIME_QUANTUM;
-#endif
- chSchReadyI(otp);
- chSysSwitch(currp, otp);
-}
-#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) */
-
-/**
- * @brief Switches to the first thread on the runnable queue.
- * @details The current thread is positioned in the ready list ahead of all
- * threads having the same priority.
- * @note Not a user function, it is meant to be invoked by the scheduler
- * itself or from within the port layer.
- *
- * @special
- */
-#if !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) || defined(__DOXYGEN__)
-void chSchDoRescheduleAhead(void) {
- Thread *otp, *cp;
-
- otp = currp;
- /* Picks the first thread from the ready queue and makes it current.*/
- setcurrp(fifo_remove(&rlist.r_queue));
- currp->p_state = THD_STATE_CURRENT;
-
- otp->p_state = THD_STATE_READY;
- cp = (Thread *)&rlist.r_queue;
- do {
- cp = cp->p_next;
- } while (cp->p_prio > otp->p_prio);
- /* Insertion on p_prev.*/
- otp->p_next = cp;
- otp->p_prev = cp->p_prev;
- otp->p_prev->p_next = cp->p_prev = otp;
-
- chSysSwitch(currp, otp);
-}
-#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) */
-
-/**
- * @brief Switches to the first thread on the runnable queue.
- * @details The current thread is positioned in the ready list behind or
- * ahead of all threads having the same priority depending on
- * if it used its whole time slice.
- * @note Not a user function, it is meant to be invoked by the scheduler
- * itself or from within the port layer.
- *
- * @special
- */
-#if !defined(PORT_OPTIMIZED_DORESCHEDULE) || defined(__DOXYGEN__)
-void chSchDoReschedule(void) {
-
-#if CH_TIME_QUANTUM > 0
- /* If CH_TIME_QUANTUM is enabled then there are two different scenarios to
- handle on preemption: time quantum elapsed or not.*/
- if (currp->p_preempt == 0) {
- /* The thread consumed its time quantum so it is enqueued behind threads
- with same priority level, however, it acquires a new time quantum.*/
- chSchDoRescheduleBehind();
- }
- else {
- /* The thread didn't consume all its time quantum so it is put ahead of
- threads with equal priority and does not acquire a new time quantum.*/
- chSchDoRescheduleAhead();
- }
-#else /* !(CH_TIME_QUANTUM > 0) */
- /* If the round-robin mechanism is disabled then the thread goes always
- ahead of its peers.*/
- chSchDoRescheduleAhead();
-#endif /* !(CH_TIME_QUANTUM > 0) */
-}
-#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULE) */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chsys.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chsys.c
deleted file mode 100644
index a91dddff55..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chsys.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chsys.c
- * @brief System related code.
- *
- * @addtogroup system
- * @details System related APIs and services:
- * - Initialization.
- * - Locks.
- * - Interrupt Handling.
- * - Power Management.
- * - Abnormal Termination.
- * .
- * @{
- */
-
-#include "ch.h"
-
-#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__)
-/**
- * @brief Idle thread working area.
- */
-WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE);
-
-/**
- * @brief This function implements the idle thread infinite loop.
- * @details The function puts the processor in the lowest power mode capable
- * to serve interrupts.
- * The priority is internally set to the minimum system value so
- * that this thread is executed only if there are no other ready
- * threads in the system.
- *
- * @param[in] p the thread parameter, unused in this scenario
- */
-void _idle_thread(void *p) {
-
- (void)p;
- chRegSetThreadName("idle");
- while (TRUE) {
- port_wait_for_interrupt();
- IDLE_LOOP_HOOK();
- }
-}
-#endif /* CH_NO_IDLE_THREAD */
-
-/**
- * @brief ChibiOS/RT initialization.
- * @details After executing this function the current instructions stream
- * becomes the main thread.
- * @pre Interrupts must be still disabled when @p chSysInit() is invoked
- * and are internally enabled.
- * @post The main thread is created with priority @p NORMALPRIO.
- * @note This function has special, architecture-dependent, requirements,
- * see the notes into the various port reference manuals.
- *
- * @special
- */
-void chSysInit(void) {
- static Thread mainthread;
-#if CH_DBG_ENABLE_STACK_CHECK
- extern stkalign_t __main_thread_stack_base__;
-#endif
-
- port_init();
- _scheduler_init();
- _vt_init();
-#if CH_USE_MEMCORE
- _core_init();
-#endif
-#if CH_USE_HEAP
- _heap_init();
-#endif
-#if CH_DBG_ENABLE_TRACE
- _trace_init();
-#endif
-
- /* Now this instructions flow becomes the main thread.*/
- setcurrp(_thread_init(&mainthread, NORMALPRIO));
- currp->p_state = THD_STATE_CURRENT;
-#if CH_DBG_ENABLE_STACK_CHECK
- /* This is a special case because the main thread Thread structure is not
- adjacent to its stack area.*/
- currp->p_stklimit = &__main_thread_stack_base__;
-#endif
- chSysEnable();
-
- /* Note, &ch_debug points to the string "main" if the registry is
- active, else the parameter is ignored.*/
- chRegSetThreadName((const char *)&ch_debug);
-
-#if !CH_NO_IDLE_THREAD
- /* This thread has the lowest priority in the system, its role is just to
- serve interrupts in its context while keeping the lowest energy saving
- mode compatible with the system status.*/
- chThdCreateStatic(_idle_thread_wa, sizeof(_idle_thread_wa), IDLEPRIO,
- (tfunc_t)_idle_thread, NULL);
-#endif
-}
-
-/**
- * @brief Handles time ticks for round robin preemption and timer increments.
- * @details Decrements the remaining time quantum of the running thread
- * and preempts it when the quantum is used up. Increments system
- * time and manages the timers.
- * @note The frequency of the timer determines the system tick granularity
- * and, together with the @p CH_TIME_QUANTUM macro, the round robin
- * interval.
- *
- * @iclass
- */
-void chSysTimerHandlerI(void) {
-
- chDbgCheckClassI();
-
-#if CH_TIME_QUANTUM > 0
- /* Running thread has not used up quantum yet? */
- if (currp->p_preempt > 0)
- /* Decrement remaining quantum.*/
- currp->p_preempt--;
-#endif
-#if CH_DBG_THREADS_PROFILING
- currp->p_time++;
-#endif
- chVTDoTickI();
-#if defined(SYSTEM_TICK_EVENT_HOOK)
- SYSTEM_TICK_EVENT_HOOK();
-#endif
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chthreads.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chthreads.c
deleted file mode 100644
index 57ae565667..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chthreads.c
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chthreads.c
- * @brief Threads code.
- *
- * @addtogroup threads
- * @details Threads related APIs and services.
- *
- * Operation mode
- * A thread is an abstraction of an independent instructions flow.
- * In ChibiOS/RT a thread is represented by a "C" function owning
- * a processor context, state informations and a dedicated stack
- * area. In this scenario static variables are shared among all
- * threads while automatic variables are local to the thread.
- * Operations defined for threads:
- * - Create, a thread is started on the specified thread
- * function. This operation is available in multiple variants,
- * both static and dynamic.
- * - Exit, a thread terminates by returning from its top
- * level function or invoking a specific API, the thread can
- * return a value that can be retrieved by other threads.
- * - Wait, a thread waits for the termination of another
- * thread and retrieves its return value.
- * - Resume, a thread created in suspended state is started.
- * - Sleep, the execution of a thread is suspended for the
- * specified amount of time or the specified future absolute time
- * is reached.
- * - SetPriority, a thread changes its own priority level.
- * - Yield, a thread voluntarily renounces to its time slot.
- * .
- * The threads subsystem is implicitly included in kernel however
- * some of its part may be excluded by disabling them in @p chconf.h,
- * see the @p CH_USE_WAITEXIT and @p CH_USE_DYNAMIC configuration
- * options.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief Initializes a thread structure.
- * @note This is an internal functions, do not use it in application code.
- *
- * @param[in] tp pointer to the thread
- * @param[in] prio the priority level for the new thread
- * @return The same thread pointer passed as parameter.
- *
- * @notapi
- */
-Thread *_thread_init(Thread *tp, tprio_t prio) {
-
- tp->p_prio = prio;
- tp->p_state = THD_STATE_SUSPENDED;
- tp->p_flags = THD_MEM_MODE_STATIC;
-#if CH_TIME_QUANTUM > 0
- tp->p_preempt = CH_TIME_QUANTUM;
-#endif
-#if CH_USE_MUTEXES
- tp->p_realprio = prio;
- tp->p_mtxlist = NULL;
-#endif
-#if CH_USE_EVENTS
- tp->p_epending = 0;
-#endif
-#if CH_DBG_THREADS_PROFILING
- tp->p_time = 0;
-#endif
-#if CH_USE_DYNAMIC
- tp->p_refs = 1;
-#endif
-#if CH_USE_REGISTRY
- tp->p_name = NULL;
- REG_INSERT(tp);
-#endif
-#if CH_USE_WAITEXIT
- list_init(&tp->p_waiting);
-#endif
-#if CH_USE_MESSAGES
- queue_init(&tp->p_msgqueue);
-#endif
-#if CH_DBG_ENABLE_STACK_CHECK
- tp->p_stklimit = (stkalign_t *)(tp + 1);
-#endif
-#if defined(THREAD_EXT_INIT_HOOK)
- THREAD_EXT_INIT_HOOK(tp);
-#endif
- return tp;
-}
-
-#if CH_DBG_FILL_THREADS || defined(__DOXYGEN__)
-/**
- * @brief Memory fill utility.
- *
- * @param[in] startp first address to fill
- * @param[in] endp last address to fill +1
- * @param[in] v filler value
- *
- * @notapi
- */
-void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) {
-
- while (startp < endp)
- *startp++ = v;
-}
-#endif /* CH_DBG_FILL_THREADS */
-
-/**
- * @brief Creates a new thread into a static memory area.
- * @details The new thread is initialized but not inserted in the ready list,
- * the initial state is @p THD_STATE_SUSPENDED.
- * @post The initialized thread can be subsequently started by invoking
- * @p chThdResume(), @p chThdResumeI() or @p chSchWakeupS()
- * depending on the execution context.
- * @note A thread can terminate by calling @p chThdExit() or by simply
- * returning from its main function.
- * @note Threads created using this function do not obey to the
- * @p CH_DBG_FILL_THREADS debug option because it would keep
- * the kernel locked for too much time.
- *
- * @param[out] wsp pointer to a working area dedicated to the thread stack
- * @param[in] size size of the working area
- * @param[in] prio the priority level for the new thread
- * @param[in] pf the thread function
- * @param[in] arg an argument passed to the thread function. It can be
- * @p NULL.
- * @return The pointer to the @p Thread structure allocated for
- * the thread into the working space area.
- *
- * @iclass
- */
-Thread *chThdCreateI(void *wsp, size_t size,
- tprio_t prio, tfunc_t pf, void *arg) {
- /* Thread structure is laid out in the lower part of the thread workspace.*/
- Thread *tp = wsp;
-
- chDbgCheckClassI();
-
- chDbgCheck((wsp != NULL) && (size >= THD_WA_SIZE(0)) &&
- (prio <= HIGHPRIO) && (pf != NULL),
- "chThdCreateI");
- SETUP_CONTEXT(wsp, size, pf, arg);
- return _thread_init(tp, prio);
-}
-
-/**
- * @brief Creates a new thread into a static memory area.
- * @note A thread can terminate by calling @p chThdExit() or by simply
- * returning from its main function.
- *
- * @param[out] wsp pointer to a working area dedicated to the thread stack
- * @param[in] size size of the working area
- * @param[in] prio the priority level for the new thread
- * @param[in] pf the thread function
- * @param[in] arg an argument passed to the thread function. It can be
- * @p NULL.
- * @return The pointer to the @p Thread structure allocated for
- * the thread into the working space area.
- *
- * @api
- */
-Thread *chThdCreateStatic(void *wsp, size_t size,
- tprio_t prio, tfunc_t pf, void *arg) {
- Thread *tp;
-
-#if CH_DBG_FILL_THREADS
- _thread_memfill((uint8_t *)wsp,
- (uint8_t *)wsp + sizeof(Thread),
- CH_THREAD_FILL_VALUE);
- _thread_memfill((uint8_t *)wsp + sizeof(Thread),
- (uint8_t *)wsp + size,
- CH_STACK_FILL_VALUE);
-#endif
- chSysLock();
- chSchWakeupS(tp = chThdCreateI(wsp, size, prio, pf, arg), RDY_OK);
- chSysUnlock();
- return tp;
-}
-
-/**
- * @brief Changes the running thread priority level then reschedules if
- * necessary.
- * @note The function returns the real thread priority regardless of the
- * current priority that could be higher than the real priority
- * because the priority inheritance mechanism.
- *
- * @param[in] newprio the new priority level of the running thread
- * @return The old priority level.
- *
- * @api
- */
-tprio_t chThdSetPriority(tprio_t newprio) {
- tprio_t oldprio;
-
- chDbgCheck(newprio <= HIGHPRIO, "chThdSetPriority");
-
- chSysLock();
-#if CH_USE_MUTEXES
- oldprio = currp->p_realprio;
- if ((currp->p_prio == currp->p_realprio) || (newprio > currp->p_prio))
- currp->p_prio = newprio;
- currp->p_realprio = newprio;
-#else
- oldprio = currp->p_prio;
- currp->p_prio = newprio;
-#endif
- chSchRescheduleS();
- chSysUnlock();
- return oldprio;
-}
-
-/**
- * @brief Resumes a suspended thread.
- * @pre The specified thread pointer must refer to an initialized thread
- * in the @p THD_STATE_SUSPENDED state.
- * @post The specified thread is immediately started or put in the ready
- * list depending on the relative priority levels.
- * @note Use this function to start threads created with @p chThdCreateI().
- *
- * @param[in] tp pointer to the thread
- * @return The pointer to the thread.
- *
- * @api
- */
-Thread *chThdResume(Thread *tp) {
-
- chSysLock();
- chDbgAssert(tp->p_state == THD_STATE_SUSPENDED,
- "chThdResume(), #1",
- "thread not in THD_STATE_SUSPENDED state");
- chSchWakeupS(tp, RDY_OK);
- chSysUnlock();
- return tp;
-}
-
-/**
- * @brief Requests a thread termination.
- * @pre The target thread must be written to invoke periodically
- * @p chThdShouldTerminate() and terminate cleanly if it returns
- * @p TRUE.
- * @post The specified thread will terminate after detecting the termination
- * condition.
- *
- * @param[in] tp pointer to the thread
- *
- * @api
- */
-void chThdTerminate(Thread *tp) {
-
- chSysLock();
- tp->p_flags |= THD_TERMINATE;
- chSysUnlock();
-}
-
-/**
- * @brief Suspends the invoking thread for the specified time.
- *
- * @param[in] time the delay in system ticks, the special values are
- * handled as follow:
- * - @a TIME_INFINITE the thread enters an infinite sleep
- * state.
- * - @a TIME_IMMEDIATE this value is not allowed.
- * .
- *
- * @api
- */
-void chThdSleep(systime_t time) {
-
- chDbgCheck(time != TIME_IMMEDIATE, "chThdSleep");
-
- chSysLock();
- chThdSleepS(time);
- chSysUnlock();
-}
-
-/**
- * @brief Suspends the invoking thread until the system time arrives to the
- * specified value.
- *
- * @param[in] time absolute system time
- *
- * @api
- */
-void chThdSleepUntil(systime_t time) {
-
- chSysLock();
- if ((time -= chTimeNow()) > 0)
- chThdSleepS(time);
- chSysUnlock();
-}
-
-/**
- * @brief Yields the time slot.
- * @details Yields the CPU control to the next thread in the ready list with
- * equal priority, if any.
- *
- * @api
- */
-void chThdYield(void) {
-
- chSysLock();
- chSchDoYieldS();
- chSysUnlock();
-}
-
-/**
- * @brief Terminates the current thread.
- * @details The thread goes in the @p THD_STATE_FINAL state holding the
- * specified exit status code, other threads can retrieve the
- * exit status code by invoking the function @p chThdWait().
- * @post Eventual code after this function will never be executed,
- * this function never returns. The compiler has no way to
- * know this so do not assume that the compiler would remove
- * the dead code.
- *
- * @param[in] msg thread exit code
- *
- * @api
- */
-void chThdExit(msg_t msg) {
-
- chSysLock();
- chThdExitS(msg);
- /* The thread never returns here.*/
-}
-
-/**
- * @brief Terminates the current thread.
- * @details The thread goes in the @p THD_STATE_FINAL state holding the
- * specified exit status code, other threads can retrieve the
- * exit status code by invoking the function @p chThdWait().
- * @post Eventual code after this function will never be executed,
- * this function never returns. The compiler has no way to
- * know this so do not assume that the compiler would remove
- * the dead code.
- *
- * @param[in] msg thread exit code
- *
- * @sclass
- */
-void chThdExitS(msg_t msg) {
- Thread *tp = currp;
-
- tp->p_u.exitcode = msg;
-#if defined(THREAD_EXT_EXIT_HOOK)
- THREAD_EXT_EXIT_HOOK(tp);
-#endif
-#if CH_USE_WAITEXIT
- while (notempty(&tp->p_waiting))
- chSchReadyI(list_remove(&tp->p_waiting));
-#endif
-#if CH_USE_REGISTRY
- /* Static threads are immediately removed from the registry because
- there is no memory to recover.*/
- if ((tp->p_flags & THD_MEM_MODE_MASK) == THD_MEM_MODE_STATIC)
- REG_REMOVE(tp);
-#endif
- chSchGoSleepS(THD_STATE_FINAL);
- /* The thread never returns here.*/
- chDbgAssert(FALSE, "chThdExitS(), #1", "zombies apocalypse");
-}
-
-#if CH_USE_WAITEXIT || defined(__DOXYGEN__)
-/**
- * @brief Blocks the execution of the invoking thread until the specified
- * thread terminates then the exit code is returned.
- * @details This function waits for the specified thread to terminate then
- * decrements its reference counter, if the counter reaches zero then
- * the thread working area is returned to the proper allocator.
- * The memory used by the exited thread is handled in different ways
- * depending on the API that spawned the thread:
- * - If the thread was spawned by @p chThdCreateStatic() or by
- * @p chThdCreateI() then nothing happens and the thread working
- * area is not released or modified in any way. This is the
- * default, totally static, behavior.
- * - If the thread was spawned by @p chThdCreateFromHeap() then
- * the working area is returned to the system heap.
- * - If the thread was spawned by @p chThdCreateFromMemoryPool()
- * then the working area is returned to the owning memory pool.
- * .
- * @pre The configuration option @p CH_USE_WAITEXIT must be enabled in
- * order to use this function.
- * @post Enabling @p chThdWait() requires 2-4 (depending on the
- * architecture) extra bytes in the @p Thread structure.
- * @post After invoking @p chThdWait() the thread pointer becomes invalid
- * and must not be used as parameter for further system calls.
- * @note If @p CH_USE_DYNAMIC is not specified this function just waits for
- * the thread termination, no memory allocators are involved.
- *
- * @param[in] tp pointer to the thread
- * @return The exit code from the terminated thread.
- *
- * @api
- */
-msg_t chThdWait(Thread *tp) {
- msg_t msg;
-
- chDbgCheck(tp != NULL, "chThdWait");
-
- chSysLock();
- chDbgAssert(tp != currp, "chThdWait(), #1", "waiting self");
-#if CH_USE_DYNAMIC
- chDbgAssert(tp->p_refs > 0, "chThdWait(), #2", "not referenced");
-#endif
- if (tp->p_state != THD_STATE_FINAL) {
- list_insert(currp, &tp->p_waiting);
- chSchGoSleepS(THD_STATE_WTEXIT);
- }
- msg = tp->p_u.exitcode;
- chSysUnlock();
-#if CH_USE_DYNAMIC
- chThdRelease(tp);
-#endif
- return msg;
-}
-#endif /* CH_USE_WAITEXIT */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chvt.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chvt.c
deleted file mode 100644
index c1c694560d..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chvt.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file chvt.c
- * @brief Time and Virtual Timers related code.
- *
- * @addtogroup time
- * @details Time and Virtual Timers related APIs and services.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief Virtual timers delta list header.
- */
-VTList vtlist;
-
-/**
- * @brief Virtual Timers initialization.
- * @note Internal use only.
- *
- * @notapi
- */
-void _vt_init(void) {
-
- vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist;
- vtlist.vt_time = (systime_t)-1;
- vtlist.vt_systime = 0;
-}
-
-/**
- * @brief Enables a virtual timer.
- * @note The associated function is invoked from interrupt context.
- *
- * @param[out] vtp the @p VirtualTimer structure pointer
- * @param[in] time the number of ticks before the operation timeouts, the
- * special values are handled as follow:
- * - @a TIME_INFINITE is allowed but interpreted as a
- * normal time specification.
- * - @a TIME_IMMEDIATE this value is not allowed.
- * .
- * @param[in] vtfunc the timer callback function. After invoking the
- * callback the timer is disabled and the structure can
- * be disposed or reused.
- * @param[in] par a parameter that will be passed to the callback
- * function
- *
- * @iclass
- */
-void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par) {
- VirtualTimer *p;
-
- chDbgCheckClassI();
- chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (time != TIME_IMMEDIATE),
- "chVTSetI");
-
- vtp->vt_par = par;
- vtp->vt_func = vtfunc;
- p = vtlist.vt_next;
- while (p->vt_time < time) {
- time -= p->vt_time;
- p = p->vt_next;
- }
-
- vtp->vt_prev = (vtp->vt_next = p)->vt_prev;
- vtp->vt_prev->vt_next = p->vt_prev = vtp;
- vtp->vt_time = time;
- if (p != (void *)&vtlist)
- p->vt_time -= time;
-}
-
-/**
- * @brief Disables a Virtual Timer.
- * @note The timer MUST be active when this function is invoked.
- *
- * @param[in] vtp the @p VirtualTimer structure pointer
- *
- * @iclass
- */
-void chVTResetI(VirtualTimer *vtp) {
-
- chDbgCheckClassI();
- chDbgCheck(vtp != NULL, "chVTResetI");
- chDbgAssert(vtp->vt_func != NULL,
- "chVTResetI(), #1",
- "timer not set or already triggered");
-
- if (vtp->vt_next != (void *)&vtlist)
- vtp->vt_next->vt_time += vtp->vt_time;
- vtp->vt_prev->vt_next = vtp->vt_next;
- vtp->vt_next->vt_prev = vtp->vt_prev;
- vtp->vt_func = (vtfunc_t)NULL;
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chcore.c b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chcore.c
deleted file mode 100644
index d4c31b3570..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chcore.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file templates/chcore.c
- * @brief Port related template code.
- * @details This file is a template of the system driver functions provided by
- * a port. Some of the following functions may be implemented as
- * macros in chcore.h if the implementer decides that there is an
- * advantage in doing so, for example because performance concerns.
- *
- * @addtogroup core
- * @details Non portable code templates.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief Port-related initialization code.
- * @note This function is usually empty.
- */
-void port_init(void) {
-}
-
-/**
- * @brief Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform more
- * actions.
- */
-void port_lock(void) {
-}
-
-/**
- * @brief Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform more
- * actions.
- */
-void port_unlock(void) {
-}
-
-/**
- * @brief Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- * interrupt handlers. The implementation is architecture dependent,
- * in its simplest form it is void.
- */
-void port_lock_from_isr(void) {
-}
-
-/**
- * @brief Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- * handlers. The implementation is architecture dependent, in its
- * simplest form it is void.
- */
-void port_unlock_from_isr(void) {
-}
-
-/**
- * @brief Disables all the interrupt sources.
- * @note Of course non-maskable interrupt sources are not included.
- */
-void port_disable(void) {
-}
-
-/**
- * @brief Disables the interrupt sources below kernel-level priority.
- * @note Interrupt sources above kernel level remains enabled.
- */
-void port_suspend(void) {
-}
-
-/**
- * @brief Enables all the interrupt sources.
- */
-void port_enable(void) {
-}
-
-/**
- * @brief Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- * The simplest implementation is an empty function or macro but this
- * would not take advantage of architecture-specific power saving
- * modes.
- */
-void port_wait_for_interrupt(void) {
-}
-
-/**
- * @brief Halts the system.
- * @details This function is invoked by the operating system when an
- * unrecoverable error is detected (for example because a programming
- * error in the application code that triggers an assertion while in
- * debug mode).
- */
-void port_halt(void) {
-
- port_disable();
- while (TRUE) {
- }
-}
-
-/**
- * @brief Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- * is responsible for the context switch between 2 threads.
- * @note The implementation of this code affects directly the context
- * switch performance so optimize here as much as you can.
- *
- * @param[in] ntp the thread to be switched in
- * @param[in] otp the thread to be switched out
- */
-void port_switch(Thread *ntp, Thread *otp) {
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chcore.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chcore.h
deleted file mode 100644
index 70d327ac4b..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chcore.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file templates/chcore.h
- * @brief Port related template macros and structures.
- * @details This file is a template of the system driver macros provided by
- * a port.
- *
- * @addtogroup core
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-/*===========================================================================*/
-/* Port constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters. */
-/*===========================================================================*/
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p PORT_INT_REQUIRED_STACK.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE 0
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK 0
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port exported info. */
-/*===========================================================================*/
-
-/**
- * @brief Unique macro for the implemented architecture.
- */
-#define CH_ARCHITECTURE_XXX
-
-/**
- * @brief Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME ""
-
-/**
- * @brief Name of the architecture variant (optional).
- */
-#define CH_ARCHITECTURE_VARIANT_NAME ""
-
-/**
- * @brief Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME "GCC"
-
-/**
- * @brief Port-specific information string.
- */
-#define CH_PORT_INFO ""
-
-/*===========================================================================*/
-/* Port implementation part. */
-/*===========================================================================*/
-
-/**
- * @brief Base type for stack and memory alignment.
- */
-typedef uint8_t stkalign_t;
-
-/**
- * @brief Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- * preemption-capable interrupt handler.
- */
-struct extctx {
-};
-
-/**
- * @brief System saved context.
- * @details This structure represents the inner stack frame during a context
- * switching.
- */
-struct intctx {
-};
-
-/**
- * @brief Platform dependent part of the @p Thread structure.
- * @details This structure usually contains just the saved stack pointer
- * defined as a pointer to a @p intctx structure.
- */
-struct context {
- struct intctx *sp;
-};
-
-/**
- * @brief Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
-}
-
-/**
- * @brief Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- sizeof(struct intctx) + \
- sizeof(struct extctx) + \
- (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- * aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- * enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- * enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE()
-
-/**
- * @brief IRQ handler function declaration.
- * @note @p id can be a function name or a vector number depending on the
- * port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief Fast IRQ handler function declaration.
- * @note @p id can be a function name or a vector number depending on the
- * port implementation.
- * @note Not all architectures support fast interrupts, in this case this
- * macro must be omitted.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void port_init(void);
- void port_lock(void);
- void port_unlock(void);
- void port_lock_from_isr(void);
- void port_unlock_from_isr(void);
- void port_disable(void);
- void port_suspend(void);
- void port_enable(void);
- void port_wait_for_interrupt(void);
- void port_halt(void);
- void port_switch(Thread *ntp, Thread *otp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chtypes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chtypes.h
deleted file mode 100644
index 21e904ac9f..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chtypes.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file templates/chtypes.h
- * @brief System types template.
- * @details The types defined in this file may change depending on the target
- * architecture. You may also try to optimize the size of the various
- * types in order to privilege size or performance, be careful in
- * doing so.
- *
- * @addtogroup types
- * @details System types and macros.
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#define __need_NULL
-#define __need_size_t
-#include
-
-#if !defined(_STDINT_H) && !defined(__STDINT_H_)
-#include
-#endif
-
-/**
- * @brief Boolean, recommended the fastest signed.
- */
-typedef int32_t bool_t;
-
-/**
- * @brief Thread mode flags, uint8_t is ok.
- */
-typedef uint8_t tmode_t;
-
-/**
- * @brief Thread state, uint8_t is ok.
- */
-typedef uint8_t tstate_t;
-
-/**
- * @brief Thread references counter, uint8_t is ok.
- */
-typedef uint8_t trefs_t;
-
-/**
- * @brief Priority, use the fastest unsigned type.
- */
-typedef uint32_t tprio_t;
-
-/**
- * @brief Message, use signed pointer equivalent.
- */
-typedef int32_t msg_t;
-
-/**
- * @brief Event Id, use fastest signed.
- */
-typedef int32_t eventid_t;
-
-/**
- * @brief Event Mask, recommended fastest unsigned.
- */
-typedef uint32_t eventmask_t;
-
-/**
- * @brief System Time, recommended fastest unsigned.
- */
-typedef uint32_t systime_t;
-
-/**
- * @brief Counter, recommended fastest signed.
- */
-typedef int32_t cnt_t;
-
-/**
- * @brief Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief ROM constant modifier.
- * @note This is required because some compilers require a custom keyword,
- * usually this macro is just set to "const" for the GCC compiler.
- * @note This macro is not used to place constants in different address
- * spaces (like AVR requires for example) because it is assumed that
- * a pointer to a ROMCONST constant is compatible with a pointer
- * to a normal variable. It is just like the "const" keyword but
- * requires that the constant is placed in ROM if the architecture
- * supports it.
- */
-#define ROMCONST const
-
-/**
- * @brief Packed structure modifier (within).
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief Packed structure modifier (before).
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief Packed structure modifier (after).
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/license/chcustomer.h b/flight/PiOS/Common/Libraries/ChibiOS/os/license/chcustomer.h
new file mode 100644
index 0000000000..bf51d0f490
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/license/chcustomer.h
@@ -0,0 +1,98 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chcustomer.h
+ * @brief Customer-related info.
+ *
+ * @addtogroup customer
+ * @{
+ */
+
+#ifndef CHCUSTOMER_H
+#define CHCUSTOMER_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Customer readable identifier.
+ */
+#define CH_CUSTOMER_ID_STRING "Santa, North Pole"
+
+/**
+ * @brief Customer code.
+ */
+#define CH_CUSTOMER_ID_CODE "xxxx-yyyy"
+
+/**
+ * @brief Current license.
+ * @note This setting is reserved to the copyright owner.
+ * @note Changing this setting invalidates the license.
+ * @note The license statement in the source headers is valid, applicable
+ * and binding regardless this setting.
+ */
+#define CH_LICENSE CH_LICENSE_GPL
+
+/**
+ * @name Licensed Products
+ * @{
+ */
+#define CH_CUSTOMER_LIC_RT TRUE
+#define CH_CUSTOMER_LIC_NIL TRUE
+#define CH_CUSTOMER_LIC_EX TRUE
+#define CH_CUSTOMER_LIC_PORT_CM0 TRUE
+#define CH_CUSTOMER_LIC_PORT_CM3 TRUE
+#define CH_CUSTOMER_LIC_PORT_CM4 TRUE
+#define CH_CUSTOMER_LIC_PORT_CM7 TRUE
+#define CH_CUSTOMER_LIC_PORT_ARM79 TRUE
+#define CH_CUSTOMER_LIC_PORT_E200Z0 TRUE
+#define CH_CUSTOMER_LIC_PORT_E200Z2 TRUE
+#define CH_CUSTOMER_LIC_PORT_E200Z3 TRUE
+#define CH_CUSTOMER_LIC_PORT_E200Z4 TRUE
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CHCUSTOMER_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/license/chlicense.h b/flight/PiOS/Common/Libraries/ChibiOS/os/license/chlicense.h
new file mode 100644
index 0000000000..3060bcae6b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/license/chlicense.h
@@ -0,0 +1,197 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chlicense.h
+ * @brief License Module macros and structures.
+ *
+ * @addtogroup license
+ * @{
+ */
+
+#ifndef CHLICENSE_H
+#define CHLICENSE_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Allowed Features Levels
+ * @{
+ */
+#define CH_FEATURES_BASIC 0
+#define CH_FEATURES_INTERMEDIATE 1
+#define CH_FEATURES_FULL 2
+/** @} */
+
+/**
+ * @name Deployment Options
+ */
+#define CH_DEPLOY_UNLIMITED -1
+#define CH_DEPLOY_NONE 0
+/** @} */
+
+/**
+ * @name Licensing Options
+ * @{
+ */
+#define CH_LICENSE_GPL 0
+#define CH_LICENSE_GPL_EXCEPTION 1
+#define CH_LICENSE_COMMERCIAL_FREE 2
+#define CH_LICENSE_COMMERCIAL_DEV_1000 3
+#define CH_LICENSE_COMMERCIAL_DEV_5000 4
+#define CH_LICENSE_COMMERCIAL_FULL 5
+#define CH_LICENSE_COMMERCIAL_RUNTIME 6
+#define CH_LICENSE_PARTNER 7
+/** @} */
+
+#include "chcustomer.h"
+#if CH_LICENSE == CH_LICENSE_PARTNER
+#include "chpartner.h"
+#endif
+#if CH_LICENSE == CH_LICENSE_COMMERCIAL_RUNTIME
+#include "chruntime.h"
+#endif
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if (CH_LICENSE == CH_LICENSE_GPL) || defined(__DOXYGEN__)
+/**
+ * @brief License identification string.
+ * @details This string identifies the license in a machine-readable
+ * format.
+ */
+#define CH_LICENSE_TYPE_STRING "GNU General Public License 3 (GPL3)"
+
+/**
+ * @brief Customer identification string.
+ * @details This information is only available for registered commercial users.
+ */
+#define CH_LICENSE_ID_STRING "N/A"
+
+/**
+ * @brief Customer code.
+ * @details This information is only available for registered commercial users.
+ */
+#define CH_LICENSE_ID_CODE "N/A"
+
+/**
+ * @brief Code modifiability restrictions.
+ * @details This setting defines if the source code is user-modifiable or not.
+ */
+#define CH_LICENSE_MODIFIABLE_CODE TRUE
+
+/**
+ * @brief Code functionality restrictions.
+ */
+#define CH_LICENSE_FEATURES CH_FEATURES_FULL
+
+/**
+ * @brief Code deploy restrictions.
+ * @details This is the per-core deploy limit allowed under the current
+ * license scheme.
+ */
+#define CH_LICENSE_MAX_DEPLOY CH_DEPLOY_UNLIMITED
+
+#elif CH_LICENSE == CH_LICENSE_GPL_EXCEPTION
+#define CH_LICENSE_TYPE_STRING "GNU General Public License 3 (GPL3) + Exception"
+#define CH_LICENSE_ID_STRING "N/A"
+#define CH_LICENSE_ID_CODE "N/A"
+#define CH_LICENSE_MODIFIABLE_CODE FALSE
+#define CH_LICENSE_FEATURES CH_FEATURES_BASIC
+#define CH_LICENSE_MAX_DEPLOY CH_DEPLOY_UNLIMITED
+
+#elif CH_LICENSE == CH_LICENSE_COMMERCIAL_FREE
+#define CH_LICENSE_TYPE_STRING "Zero Cost Registered License for 500 Cores"
+#define CH_LICENSE_ID_STRING "N/A"
+#define CH_LICENSE_ID_CODE "2017-0000"
+#define CH_LICENSE_MODIFIABLE_CODE FALSE
+#define CH_LICENSE_FEATURES CH_FEATURES_INTERMEDIATE
+#define CH_LICENSE_MAX_DEPLOY 500
+
+#elif CH_LICENSE == CH_LICENSE_COMMERCIAL_DEV_1000
+#define CH_LICENSE_TYPE_STRING "Developer Commercial License for 1000 Cores"
+#define CH_LICENSE_ID_STRING CH_CUSTOMER_ID_STRING
+#define CH_LICENSE_ID_CODE CH_CUSTOMER_ID_CODE
+#define CH_LICENSE_MODIFIABLE_CODE TRUE
+#define CH_LICENSE_FEATURES CH_FEATURES_FULL
+#define CH_LICENSE_DEPLOY_LIMIT 1000
+
+#elif CH_LICENSE == CH_LICENSE_COMMERCIAL_DEV_5000
+#define CH_LICENSE_TYPE_STRING "Developer Commercial License for 5000 Cores"
+#define CH_LICENSE_ID_STRING CH_CUSTOMER_ID_STRING
+#define CH_LICENSE_ID_CODE CH_CUSTOMER_ID_CODE
+#define CH_LICENSE_MODIFIABLE_CODE TRUE
+#define CH_LICENSE_FEATURES CH_FEATURES_FULL
+#define CH_LICENSE_DEPLOY_LIMIT 5000
+
+#elif CH_LICENSE == CH_LICENSE_COMMERCIAL_FULL
+#define CH_LICENSE_TYPE_STRING "Full Commercial License for Unlimited Deployment"
+#define CH_LICENSE_ID_STRING CH_CUSTOMER_ID_STRING
+#define CH_LICENSE_ID_CODE CH_CUSTOMER_ID_CODE
+#define CH_LICENSE_MODIFIABLE_CODE TRUE
+#define CH_LICENSE_FEATURES CH_FEATURES_FULL
+#define CH_LICENSE_MAX_DEPLOY CH_DEPLOY_UNLIMITED
+
+#elif CH_LICENSE == CH_LICENSE_COMMERCIAL_RUNTIME
+#define CH_LICENSE_TYPE_STRING "Runtime Commercial License"
+#define CH_LICENSE_ID_STRING CH_CUSTOMER_ID_STRING
+#define CH_LICENSE_ID_CODE CH_CUSTOMER_ID_CODE
+#define CH_LICENSE_MODIFIABLE_CODE TRUE
+#define CH_LICENSE_FEATURES CH_FEATURES_FULL
+#define CH_LICENSE_MAX_DEPLOY CH_RUNTIME_MAX_DEPLOY
+
+#elif CH_LICENSE == CH_LICENSE_PARTNER
+#define CH_LICENSE_TYPE_STRING "Partners Special Commercial License"
+#define CH_LICENSE_ID_STRING CH_CUSTOMER_ID_STRING
+#define CH_LICENSE_ID_CODE CH_CUSTOMER_ID_CODE
+#define CH_LICENSE_MODIFIABLE_CODE CH_PARTNER_MODIFIABLE_CODE
+#define CH_LICENSE_FEATURES CH_PARTNER_FEATURES
+#define CH_LICENSE_MAX_DEPLOY CH_PARTNER_MAX_DEPLOY
+
+#else
+#error "invalid licensing option"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CHLICENSE_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/license/chversion.h b/flight/PiOS/Common/Libraries/ChibiOS/os/license/chversion.h
new file mode 100644
index 0000000000..d45e264ccb
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/license/chversion.h
@@ -0,0 +1,101 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chversion.h
+ * @brief Version Module macros and structures.
+ *
+ * @addtogroup version
+ * @{
+ */
+
+#ifndef CHVERSION_H
+#define CHVERSION_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @brief ChibiOS product identification macro.
+ */
+#define _CHIBIOS_
+
+/**
+ * @brief Stable release flag.
+ */
+#define CH_VERSION_STABLE 1
+
+/**
+ * @name ChibiOS version identification
+ * @{
+ */
+/**
+ * @brief ChibiOS version string.
+ */
+#define CH_VERSION "17.6.3"
+
+/**
+ * @brief ChibiOS version release year.
+ */
+#define CH_VERSION_YEAR 17
+
+/**
+ * @brief ChibiOS version release month.
+ */
+#define CH_VERSION_MONTH 6
+
+/**
+ * @brief ChibiOS version patch number.
+ */
+#define CH_VERSION_PATCH 3
+
+/**
+ * @brief ChibiOS version nickname.
+ */
+#define CH_VERSION_NICKNAME "Vivace"
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CHVERSION_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h
deleted file mode 100644
index 7b76e135c6..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/STM32F1xx/cmparams.h
- * @brief ARM Cortex-M3 parameters for the STM32F1xx.
- *
- * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- * STM32F1xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief Cortex core model.
- */
-#define CORTEX_MODEL CORTEX_M3
-
-/**
- * @brief Systick unit presence.
- */
-#define CORTEX_HAS_ST TRUE
-
-/**
- * @brief Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU FALSE
-
-/**
- * @brief Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU FALSE
-
-/**
- * @brief Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS 4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld
deleted file mode 100644
index 01d516609b..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F100xB memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 128k
- ram : org = 0x20000000, len = 8k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld
deleted file mode 100644
index 0babc301bf..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F103xB memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 128k
- ram : org = 0x20000000, len = 20k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld
deleted file mode 100644
index f749234074..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F103xE memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 384k
- ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld
deleted file mode 100644
index 64b1297eb2..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F103xE memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 512k
- ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld
deleted file mode 100644
index c417d32dd9..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F103xG memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 1m
- ram : org = 0x20000000, len = 96k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld
deleted file mode 100644
index 0a427652ff..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F107xC memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 256k
- ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/port.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
deleted file mode 100644
index 51a2cf4a0d..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M3 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
- $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
- ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
- ${CHIBIOS}/os/ports/common/ARMCMx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx
-
-PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c
deleted file mode 100644
index 7570147034..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/STM32F1xx/vectors.c
- * @brief Interrupt vectors for the STM32F1xx family.
- *
- * @defgroup ARMCMx_STM32F1xx_VECTORS STM32F1xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32F1xx family.
- * One of the following macros must be defined on the
- * compiler command line or in a file named board.h:
- * - @p STM32F10X_LD
- * - @p STM32F10X_LD_VL
- * - @p STM32F10X_MD
- * - @p STM32F10X_MD_VL
- * - @p STM32F10X_HD
- * - @p STM32F10X_XL
- * - @p STM32F10X_CL
- * .
- * This is required in order to include a vectors table with
- * the correct length for the specified STM32 model.
- * @{
- */
-
-#include "ch.h"
-
-#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \
- !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \
- !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \
- !defined(STM32F10X_CL)
-#include "board.h"
-#endif
-
-#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
-#define NUM_VECTORS 46
-#elif defined(STM32F10X_HD) || defined(STM32F10X_XL)
-#define NUM_VECTORS 60
-#elif defined(STM32F10X_CL)
-#define NUM_VECTORS 68
-#else
-#define NUM_VECTORS 43
-#endif
-
-/**
- * @brief Type of an IRQ vector.
- */
-typedef void (*irq_vector_t)(void);
-
-/**
- * @brief Type of a structure representing the whole vectors table.
- */
-typedef struct {
- uint32_t *init_stack;
- irq_vector_t reset_vector;
- irq_vector_t nmi_vector;
- irq_vector_t hardfault_vector;
- irq_vector_t memmanage_vector;
- irq_vector_t busfault_vector;
- irq_vector_t usagefault_vector;
- irq_vector_t vector1c;
- irq_vector_t vector20;
- irq_vector_t vector24;
- irq_vector_t vector28;
- irq_vector_t svcall_vector;
- irq_vector_t debugmonitor_vector;
- irq_vector_t vector34;
- irq_vector_t pendsv_vector;
- irq_vector_t systick_vector;
- irq_vector_t vectors[NUM_VECTORS];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
- defined(STM32F10X_XL) || defined(STM32F10X_CL)
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-#endif
-#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-extern void Vector114(void);
-extern void Vector118(void);
-extern void Vector11C(void);
-extern void Vector120(void);
-extern void Vector124(void);
-extern void Vector128(void);
-extern void Vector12C(void);
-#endif
-#if defined(STM32F10X_CL)
-extern void Vector130(void);
-extern void Vector134(void);
-extern void Vector138(void);
-extern void Vector13C(void);
-extern void Vector140(void);
-extern void Vector144(void);
-extern void Vector148(void);
-extern void Vector14C(void);
-#endif
-#endif
-
-/**
- * @brief STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
- &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector,
- MemManageVector, BusFaultVector, UsageFaultVector, Vector1C,
- Vector20, Vector24, Vector28, SVCallVector,
- DebugMonitorVector, Vector34, PendSVVector, SysTickVector,
- {
- Vector40, Vector44, Vector48, Vector4C,
- Vector50, Vector54, Vector58, Vector5C,
- Vector60, Vector64, Vector68, Vector6C,
- Vector70, Vector74, Vector78, Vector7C,
- Vector80, Vector84, Vector88, Vector8C,
- Vector90, Vector94, Vector98, Vector9C,
- VectorA0, VectorA4, VectorA8, VectorAC,
- VectorB0, VectorB4, VectorB8, VectorBC,
- VectorC0, VectorC4, VectorC8, VectorCC,
- VectorD0, VectorD4, VectorD8, VectorDC,
- VectorE0, VectorE4, VectorE8,
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
- defined(STM32F10X_XL) || defined(STM32F10X_CL)
- VectorEC, VectorF0, VectorF4,
-#endif
-#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
- VectorF8, VectorFC, Vector100, Vector104,
- Vector108, Vector10C, Vector110, Vector114,
- Vector118, Vector11C, Vector120, Vector124,
- Vector128, Vector12C,
-#endif
-#if defined(STM32F10X_CL)
- Vector130, Vector134, Vector138, Vector13C,
- Vector140, Vector144, Vector148, Vector14C
-#endif
- }
-};
-
-/**
- * @brief Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- * This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
- while (TRUE)
- ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
- defined(STM32F10X_XL) || defined(STM32F10X_CL)
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-#endif
-#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
-#endif
-#if defined(STM32F10X_CL)
-void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
-#endif
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h
deleted file mode 100644
index 4b25454d85..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/STM32F3xx/cmparams.h
- * @brief ARM Cortex-M4 parameters for the STM32F3xx.
- *
- * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- * STM32F3xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief Cortex core model.
- */
-#define CORTEX_MODEL CORTEX_M4
-
-/**
- * @brief Systick unit presence.
- */
-#define CORTEX_HAS_ST TRUE
-
-/**
- * @brief Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU TRUE
-
-/**
- * @brief Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU TRUE
-
-/**
- * @brief Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS 4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld
deleted file mode 100644
index 69918c0086..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F303xC memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 256k
- ram : org = 0x20000000, len = 40k
- ccmram : org = 0x10000000, len = 8k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld
deleted file mode 100644
index 3d0c4d424c..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F373xC memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 256k
- ram : org = 0x20000000, len = 32k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/port.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/port.mk
deleted file mode 100644
index f8411004c0..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M4 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
- $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
- ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
- ${CHIBIOS}/os/ports/common/ARMCMx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F3xx
-
-PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F3xx/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c
deleted file mode 100644
index 6e02697c27..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/STM32F3xx/vectors.c
- * @brief Interrupt vectors for the STM32F3xx family.
- *
- * @defgroup ARMCMx_STM32F3xx_VECTORS STM32F3xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32F3xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief Type of an IRQ vector.
- */
-typedef void (*irq_vector_t)(void);
-
-/**
- * @brief Type of a structure representing the whole vectors table.
- */
-typedef struct {
- uint32_t *init_stack;
- irq_vector_t reset_vector;
- irq_vector_t nmi_vector;
- irq_vector_t hardfault_vector;
- irq_vector_t memmanage_vector;
- irq_vector_t busfault_vector;
- irq_vector_t usagefault_vector;
- irq_vector_t vector1c;
- irq_vector_t vector20;
- irq_vector_t vector24;
- irq_vector_t vector28;
- irq_vector_t svcall_vector;
- irq_vector_t debugmonitor_vector;
- irq_vector_t vector34;
- irq_vector_t pendsv_vector;
- irq_vector_t systick_vector;
- irq_vector_t vectors[82];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-extern void Vector114(void);
-extern void Vector118(void);
-extern void Vector11C(void);
-extern void Vector120(void);
-extern void Vector124(void);
-extern void Vector128(void);
-extern void Vector12C(void);
-extern void Vector130(void);
-extern void Vector134(void);
-extern void Vector138(void);
-extern void Vector13C(void);
-extern void Vector140(void);
-extern void Vector144(void);
-extern void Vector148(void);
-extern void Vector14C(void);
-extern void Vector150(void);
-extern void Vector154(void);
-extern void Vector158(void);
-extern void Vector15C(void);
-extern void Vector160(void);
-extern void Vector164(void);
-extern void Vector168(void);
-extern void Vector16C(void);
-extern void Vector170(void);
-extern void Vector174(void);
-extern void Vector178(void);
-extern void Vector17C(void);
-extern void Vector180(void);
-extern void Vector184(void);
-#endif
-
-/**
- * @brief STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
- &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector,
- MemManageVector, BusFaultVector, UsageFaultVector, Vector1C,
- Vector20, Vector24, Vector28, SVCallVector,
- DebugMonitorVector, Vector34, PendSVVector, SysTickVector,
- {
- Vector40, Vector44, Vector48, Vector4C,
- Vector50, Vector54, Vector58, Vector5C,
- Vector60, Vector64, Vector68, Vector6C,
- Vector70, Vector74, Vector78, Vector7C,
- Vector80, Vector84, Vector88, Vector8C,
- Vector90, Vector94, Vector98, Vector9C,
- VectorA0, VectorA4, VectorA8, VectorAC,
- VectorB0, VectorB4, VectorB8, VectorBC,
- VectorC0, VectorC4, VectorC8, VectorCC,
- VectorD0, VectorD4, VectorD8, VectorDC,
- VectorE0, VectorE4, VectorE8, VectorEC,
- VectorF0, VectorF4, VectorF8, VectorFC,
- Vector100, Vector104, Vector108, Vector10C,
- Vector110, Vector114, Vector118, Vector11C,
- Vector120, Vector124, Vector128, Vector12C,
- Vector130, Vector134, Vector138, Vector13C,
- Vector140, Vector144, Vector148, Vector14C,
- Vector150, Vector154, Vector158, Vector15C,
- Vector160, Vector164, Vector168, Vector16C,
- Vector170, Vector174, Vector178, Vector17C,
- Vector180, Vector184
- }
-};
-
-/**
- * @brief Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- * This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
- while (TRUE)
- ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h
deleted file mode 100644
index c3fdc417d1..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/STM32F4xx/cmparams.h
- * @brief ARM Cortex-M4 parameters for the STM32F4xx.
- *
- * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- * STM32F4xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief Cortex core model.
- */
-#define CORTEX_MODEL CORTEX_M4
-
-/**
- * @brief Systick unit presence.
- */
-#define CORTEX_HAS_ST TRUE
-
-/**
- * @brief Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU TRUE
-
-/**
- * @brief Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU TRUE
-
-/**
- * @brief Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS 4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld
deleted file mode 100644
index ea70d26e1a..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F401xC memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 256k
- ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xE.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xE.ld
deleted file mode 100644
index 78ecd199b6..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xE.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F401xE memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 512k
- ram : org = 0x20000000, len = 96k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld
deleted file mode 100644
index 37d63e92fe..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F405xG memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 1M
- ram : org = 0x20000000, len = 112k
- ethram : org = 0x2001C000, len = 16k
- ccmram : org = 0x10000000, len = 64k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld
deleted file mode 100644
index 0c657584ea..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F407xG memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 1M
- ram : org = 0x20000000, len = 112k
- ethram : org = 0x2001C000, len = 16k
- ccmram : org = 0x10000000, len = 64k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld
deleted file mode 100644
index 80cc60a5c6..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F407xG memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 1M
- ram : org = 0x20000000, len = 112k
- ethram : org = 0x2001C000, len = 16k
- ccmram : org = 0x10000000, len = 64k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ccmram
-
- .ccm (NOLOAD):
- {
- PROVIDE(_cmm_start = .);
- . = ALIGN(4);
- *(.ccm)
- . = ALIGN(4);
- *(.ccm.*)
- . = ALIGN(4);
- *(.bss.mainthread.*)
- . = ALIGN(4);
- *(.bss._idle_thread_wa)
- . = ALIGN(4);
- *(.bss.rlist)
- . = ALIGN(4);
- *(.bss.vtlist)
- . = ALIGN(4);
- *(.bss.endmem)
- . = ALIGN(4);
- *(.bss.nextmem)
- . = ALIGN(4);
- *(.bss.default_heap)
- . = ALIGN(4);
- PROVIDE(_cmm_end = .);
- } > ccmram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F429xI.ld b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F429xI.ld
deleted file mode 100644
index 669d59ab79..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F429xI.ld
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * ST32F429xI memory setup.
- */
-__main_stack_size__ = 0x0400;
-__process_stack_size__ = 0x0400;
-
-MEMORY
-{
- flash : org = 0x08000000, len = 2M
- ram : org = 0x20000000, len = 192k
- ccmram : org = 0x10000000, len = 64k
-}
-
-__ram_start__ = ORIGIN(ram);
-__ram_size__ = LENGTH(ram);
-__ram_end__ = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
- . = 0;
- _text = .;
-
- startup : ALIGN(16) SUBALIGN(16)
- {
- KEEP(*(vectors))
- } > flash
-
- constructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE(__init_array_end = .);
- } > flash
-
- destructors : ALIGN(4) SUBALIGN(4)
- {
- PROVIDE(__fini_array_start = .);
- KEEP(*(.fini_array))
- KEEP(*(SORT(.fini_array.*)))
- PROVIDE(__fini_array_end = .);
- } > flash
-
- .text : ALIGN(16) SUBALIGN(16)
- {
- *(.text.startup.*)
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- *(.glue_7t)
- *(.glue_7)
- *(.gcc*)
- } > flash
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > flash
-
- .ARM.exidx : {
- PROVIDE(__exidx_start = .);
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- PROVIDE(__exidx_end = .);
- } > flash
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
- } > flash
-
- .eh_frame : ONLY_IF_RO
- {
- *(.eh_frame)
- } > flash
-
- .textalign : ONLY_IF_RO
- {
- . = ALIGN(8);
- } > flash
-
- . = ALIGN(4);
- _etext = .;
- _textdata = _etext;
-
- .stacks :
- {
- . = ALIGN(8);
- __main_stack_base__ = .;
- . += __main_stack_size__;
- . = ALIGN(8);
- __main_stack_end__ = .;
- __process_stack_base__ = .;
- __main_thread_stack_base__ = .;
- . += __process_stack_size__;
- . = ALIGN(8);
- __process_stack_end__ = .;
- __main_thread_stack_end__ = .;
- } > ram
-
- .data :
- {
- . = ALIGN(4);
- PROVIDE(_data = .);
- *(.data)
- . = ALIGN(4);
- *(.data.*)
- . = ALIGN(4);
- *(.ramtext)
- . = ALIGN(4);
- PROVIDE(_edata = .);
- } > ram AT > flash
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE(_bss_start = .);
- *(.bss)
- . = ALIGN(4);
- *(.bss.*)
- . = ALIGN(4);
- *(COMMON)
- . = ALIGN(4);
- PROVIDE(_bss_end = .);
- } > ram
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/port.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
deleted file mode 100644
index 3fd6a41304..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M4 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
- $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
- ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
- ${CHIBIOS}/os/ports/common/ARMCMx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx
-
-PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx/ld
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c
deleted file mode 100644
index e3367f0995..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/STM32F4xx/vectors.c
- * @brief Interrupt vectors for the STM32F4xx family.
- *
- * @defgroup ARMCMx_STM32F4xx_VECTORS STM32F4xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32F4xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief Type of an IRQ vector.
- */
-typedef void (*irq_vector_t)(void);
-
-/**
- * @brief Type of a structure representing the whole vectors table.
- */
-typedef struct {
- uint32_t *init_stack;
- irq_vector_t reset_vector;
- irq_vector_t nmi_vector;
- irq_vector_t hardfault_vector;
- irq_vector_t memmanage_vector;
- irq_vector_t busfault_vector;
- irq_vector_t usagefault_vector;
- irq_vector_t vector1c;
- irq_vector_t vector20;
- irq_vector_t vector24;
- irq_vector_t vector28;
- irq_vector_t svcall_vector;
- irq_vector_t debugmonitor_vector;
- irq_vector_t vector34;
- irq_vector_t pendsv_vector;
- irq_vector_t systick_vector;
- irq_vector_t vectors[91];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-extern void Vector114(void);
-extern void Vector118(void);
-extern void Vector11C(void);
-extern void Vector120(void);
-extern void Vector124(void);
-extern void Vector128(void);
-extern void Vector12C(void);
-extern void Vector130(void);
-extern void Vector134(void);
-extern void Vector138(void);
-extern void Vector13C(void);
-extern void Vector140(void);
-extern void Vector144(void);
-extern void Vector148(void);
-extern void Vector14C(void);
-extern void Vector150(void);
-extern void Vector154(void);
-extern void Vector158(void);
-extern void Vector15C(void);
-extern void Vector160(void);
-extern void Vector164(void);
-extern void Vector168(void);
-extern void Vector16C(void);
-extern void Vector170(void);
-extern void Vector174(void);
-extern void Vector178(void);
-extern void Vector17C(void);
-extern void Vector180(void);
-extern void Vector184(void);
-extern void Vector188(void);
-extern void Vector18C(void);
-extern void Vector190(void);
-extern void Vector194(void);
-extern void Vector198(void);
-extern void Vector19C(void);
-extern void Vector1A0(void);
-extern void Vector1A4(void);
-extern void Vector1A8(void);
-#endif
-
-/**
- * @brief STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
- &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector,
- MemManageVector, BusFaultVector, UsageFaultVector, Vector1C,
- Vector20, Vector24, Vector28, SVCallVector,
- DebugMonitorVector, Vector34, PendSVVector, SysTickVector,
- {
- Vector40, Vector44, Vector48, Vector4C,
- Vector50, Vector54, Vector58, Vector5C,
- Vector60, Vector64, Vector68, Vector6C,
- Vector70, Vector74, Vector78, Vector7C,
- Vector80, Vector84, Vector88, Vector8C,
- Vector90, Vector94, Vector98, Vector9C,
- VectorA0, VectorA4, VectorA8, VectorAC,
- VectorB0, VectorB4, VectorB8, VectorBC,
- VectorC0, VectorC4, VectorC8, VectorCC,
- VectorD0, VectorD4, VectorD8, VectorDC,
- VectorE0, VectorE4, VectorE8, VectorEC,
- VectorF0, VectorF4, VectorF8, VectorFC,
- Vector100, Vector104, Vector108, Vector10C,
- Vector110, Vector114, Vector118, Vector11C,
- Vector120, Vector124, Vector128, Vector12C,
- Vector130, Vector134, Vector138, Vector13C,
- Vector140, Vector144, Vector148, Vector14C,
- Vector150, Vector154, Vector158, Vector15C,
- Vector160, Vector164, Vector168, Vector16C,
- Vector170, Vector174, Vector178, Vector17C,
- Vector180, Vector184, Vector188, Vector18C,
- Vector190, Vector194, Vector198, Vector19C,
- Vector1A0, Vector1A4, Vector1A8
- }
-};
-
-/**
- * @brief Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- * This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
- while (TRUE)
- ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector188(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector18C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector190(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector194(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector198(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector19C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore.c b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore.c
deleted file mode 100644
index b826d132b2..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/chcore.c
- * @brief ARM Cortex-Mx port code.
- *
- * @addtogroup ARMCMx_CORE
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief Halts the system.
- * @note The function is declared as a weak symbol, it is possible
- * to redefine it in your application code.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void port_halt(void) {
-
- port_disable();
- while (TRUE) {
- }
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v6m.c b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v6m.c
deleted file mode 100644
index 33bb8ab453..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v6m.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/chcore_v6m.c
- * @brief ARMv6-M architecture port code.
- *
- * @addtogroup ARMCMx_V6M_CORE
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* Port interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief System Timer vector.
- * @details This interrupt is used as system tick.
- * @note The timer must be initialized in the startup code.
- */
-CH_IRQ_HANDLER(SysTickVector) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
- chSysTimerHandlerI();
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-/**
- * @brief NMI vector.
- * @details The NMI vector is used for exception mode re-entering after a
- * context switch.
- */
-void NMIVector(void) {
- register struct extctx *ctxp;
-
- /* Discarding the current exception context and positioning the stack to
- point to the real one.*/
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
- ctxp++;
- asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
- port_unlock_from_isr();
-}
-#endif /* !CORTEX_ALTERNATE_SWITCH */
-
-#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-/**
- * @brief PendSV vector.
- * @details The PendSV vector is used for exception mode re-entering after a
- * context switch.
- */
-void PendSVVector(void) {
- register struct extctx *ctxp;
-
- /* Discarding the current exception context and positioning the stack to
- point to the real one.*/
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
- ctxp++;
- asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
-}
-#endif /* CORTEX_ALTERNATE_SWITCH */
-
-/*===========================================================================*/
-/* Port exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief IRQ epilogue code.
- *
- * @param[in] lr value of the @p LR register on ISR entry
- */
-void _port_irq_epilogue(regarm_t lr) {
-
- if (lr != (regarm_t)0xFFFFFFF1) {
- register struct extctx *ctxp;
-
- port_lock_from_isr();
- /* Adding an artificial exception return context, there is no need to
- populate it fully.*/
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
- ctxp--;
- asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
- ctxp->xpsr = (regarm_t)0x01000000;
-
- /* The exit sequence is different depending on if a preemption is
- required or not.*/
- if (chSchIsPreemptionRequired()) {
- /* Preemption is required we need to enforce a context switch.*/
- ctxp->pc = (void *)_port_switch_from_isr;
- }
- else {
- /* Preemption not required, we just need to exit the exception
- atomically.*/
- ctxp->pc = (void *)_port_exit_from_isr;
- }
-
- /* Note, returning without unlocking is intentional, this is done in
- order to keep the rest of the context switch atomic.*/
- }
-}
-
-/**
- * @brief Post-IRQ switch code.
- * @details The switch is performed in thread context then an NMI exception
- * is enforced in order to return to the exact point before the
- * preemption.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void _port_switch_from_isr(void) {
-
- dbg_check_lock();
- chSchDoReschedule();
- dbg_check_unlock();
- asm volatile ("_port_exit_from_isr:" : : : "memory");
-#if CORTEX_ALTERNATE_SWITCH
- SCB_ICSR = ICSR_PENDSVSET;
- port_unlock();
-#else
- SCB_ICSR = ICSR_NMIPENDSET;
-#endif
- /* The following loop should never be executed, the exception will kick in
- immediately.*/
- while (TRUE)
- ;
-}
-
-/**
- * @brief Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- * is responsible for the context switch between 2 threads.
- * @note The implementation of this code affects directly the context
- * switch performance so optimize here as much as you can.
- *
- * @param[in] ntp the thread to be switched in
- * @param[in] otp the thread to be switched out
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void _port_switch(Thread *ntp, Thread *otp) {
- register struct intctx *r13 asm ("r13");
-
- asm volatile ("push {r4, r5, r6, r7, lr} \n\t"
- "mov r4, r8 \n\t"
- "mov r5, r9 \n\t"
- "mov r6, r10 \n\t"
- "mov r7, r11 \n\t"
- "push {r4, r5, r6, r7}" : : : "memory");
-
- otp->p_ctx.r13 = r13;
- r13 = ntp->p_ctx.r13;
-
- asm volatile ("pop {r4, r5, r6, r7} \n\t"
- "mov r8, r4 \n\t"
- "mov r9, r5 \n\t"
- "mov r10, r6 \n\t"
- "mov r11, r7 \n\t"
- "pop {r4, r5, r6, r7, pc}" : : "r" (r13) : "memory");
-}
-
-/**
- * @brief Start a thread by invoking its work function.
- * @details If the work function returns @p chThdExit() is automatically
- * invoked.
- */
-void _port_thread_start(void) {
-
- chSysUnlock();
- asm volatile ("mov r0, r5 \n\t"
- "blx r4 \n\t"
- "bl chThdExit");
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v7m.c b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v7m.c
deleted file mode 100644
index c34ed96486..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v7m.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/chcore_v7m.c
- * @brief ARMv7-M architecture port code.
- *
- * @addtogroup ARMCMx_V7M_CORE
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* Port interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief System Timer vector.
- * @details This interrupt is used as system tick.
- * @note The timer must be initialized in the startup code.
- */
-CH_IRQ_HANDLER(SysTickVector) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
- chSysTimerHandlerI();
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief SVCall vector.
- * @details The SVCall vector is used for exception mode re-entering after a
- * context switch.
- * @note The SVCallVector vector is only used in advanced kernel mode.
- */
-void SVCallVector(void) {
- struct extctx *ctxp;
-
-#if CORTEX_USE_FPU
- /* Enforcing unstacking of the FP part of the context.*/
- SCB_FPCCR &= ~FPCCR_LSPACT;
-#endif
-
- /* Current PSP value.*/
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
-
- /* Discarding the current exception context and positioning the stack to
- point to the real one.*/
- ctxp++;
-
- /* Restoring real position of the original stack frame.*/
- asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
- port_unlock_from_isr();
-}
-#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
-
-#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief PendSV vector.
- * @details The PendSV vector is used for exception mode re-entering after a
- * context switch.
- * @note The PendSV vector is only used in compact kernel mode.
- */
-void PendSVVector(void) {
- struct extctx *ctxp;
-
-#if CORTEX_USE_FPU
- /* Enforcing unstacking of the FP part of the context.*/
- SCB_FPCCR &= ~FPCCR_LSPACT;
-#endif
-
- /* Current PSP value.*/
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
-
- /* Discarding the current exception context and positioning the stack to
- point to the real one.*/
- ctxp++;
-
- /* Restoring real position of the original stack frame.*/
- asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
-}
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/*===========================================================================*/
-/* Port exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Port-related initialization code.
- */
-void _port_init(void) {
-
- /* Initialization of the vector table and priority related settings.*/
- SCB_VTOR = CORTEX_VTOR_INIT;
- SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT);
-
- /* Initialization of the system vectors used by the port.*/
- nvicSetSystemHandlerPriority(HANDLER_SVCALL,
- CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
- nvicSetSystemHandlerPriority(HANDLER_PENDSV,
- CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
- nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
- CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
-}
-
-#if !CH_OPTIMIZE_SPEED
-void _port_lock(void) {
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
-}
-
-void _port_unlock(void) {
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
-}
-#endif
-
-/**
- * @brief Exception exit redirection to _port_switch_from_isr().
- */
-void _port_irq_epilogue(void) {
-
- port_lock_from_isr();
- if ((SCB_ICSR & ICSR_RETTOBASE) != 0) {
- struct extctx *ctxp;
-
-#if CORTEX_USE_FPU
- /* Enforcing a lazy FPU state save. Note, it goes in the original
- context because the FPCAR register has not been modified.*/
- asm volatile ("vmrs APSR_nzcv, FPSCR" : : : "memory");
-#endif
-
- /* Current PSP value.*/
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
-
- /* Adding an artificial exception return context, there is no need to
- populate it fully.*/
- ctxp--;
- ctxp->xpsr = (regarm_t)0x01000000;
-#if CORTEX_USE_FPU
- ctxp->fpscr = (regarm_t)SCB_FPDSCR;
-#endif
- asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
-
- /* The exit sequence is different depending on if a preemption is
- required or not.*/
- if (chSchIsPreemptionRequired()) {
- /* Preemption is required we need to enforce a context switch.*/
- ctxp->pc = (regarm_t)_port_switch_from_isr;
- }
- else {
- /* Preemption not required, we just need to exit the exception
- atomically.*/
- ctxp->pc = (regarm_t)_port_exit_from_isr;
- }
-
- /* Note, returning without unlocking is intentional, this is done in
- order to keep the rest of the context switch atomic.*/
- return;
- }
- port_unlock_from_isr();
-}
-
-/**
- * @brief Post-IRQ switch code.
- * @details Exception handlers return here for context switching.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void _port_switch_from_isr(void) {
-
- dbg_check_lock();
- chSchDoReschedule();
- dbg_check_unlock();
- asm volatile ("_port_exit_from_isr:" : : : "memory");
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
- asm volatile ("svc #0");
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
- SCB_ICSR = ICSR_PENDSVSET;
- port_unlock();
- while (TRUE)
- ;
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-}
-
-/**
- * @brief Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- * is responsible for the context switch between 2 threads.
- * @note The implementation of this code affects directly the context
- * switch performance so optimize here as much as you can.
- *
- * @param[in] ntp the thread to be switched in
- * @param[in] otp the thread to be switched out
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void _port_switch(Thread *ntp, Thread *otp) {
-
- asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"
- : : : "memory");
-#if CORTEX_USE_FPU
- asm volatile ("vpush {s16-s31}" : : : "memory");
-#endif
-
- asm volatile ("str sp, [%1, #12] \n\t"
- "ldr r4, [%0, #12] \n\t"
- "mov sp, r4" : : "r" (ntp), "r" (otp));
-
-#if CORTEX_USE_FPU
- asm volatile ("vpop {s16-s31}" : : : "memory");
-#endif
- asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}"
- : : : "memory");
-}
-
-/**
- * @brief Start a thread by invoking its work function.
- * @details If the work function returns @p chThdExit() is automatically
- * invoked.
- */
-void _port_thread_start(void) {
-
- chSysUnlock();
- asm volatile ("mov r0, r5 \n\t"
- "blx r4 \n\t"
- "bl chThdExit");
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v7m.h b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v7m.h
deleted file mode 100644
index e50161ad89..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chcore_v7m.h
+++ /dev/null
@@ -1,532 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/chcore_v7m.h
- * @brief ARMv7-M architecture port macros and structures.
- *
- * @addtogroup ARMCMx_V7M_CORE
- * @{
- */
-
-#ifndef _CHCORE_V7M_H_
-#define _CHCORE_V7M_H_
-
-/*===========================================================================*/
-/* Port constants. */
-/*===========================================================================*/
-
-/**
- * @brief Disabled value for BASEPRI register.
- */
-#define CORTEX_BASEPRI_DISABLED 0
-
-/*===========================================================================*/
-/* Port macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters. */
-/*===========================================================================*/
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p PORT_INT_REQUIRED_STACK.
- * @note In this port it is set to 16 because the idle thread does have
- * a stack frame when compiling without optimizations. You may
- * reduce this value to zero when compiling with optimizations.
- */
-#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
-#define PORT_IDLE_THREAD_STACK_SIZE 16
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * @note In this port this value is conservatively set to 64 because the
- * function @p chSchDoReschedule() can have a stack frame, especially
- * with compiler optimizations disabled. The value can be reduced
- * when compiler optimizations are enabled.
- */
-#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK 64
-#endif
-
-/**
- * @brief Enables the use of the WFI instruction in the idle thread loop.
- */
-#if !defined(CORTEX_ENABLE_WFI_IDLE)
-#define CORTEX_ENABLE_WFI_IDLE FALSE
-#endif
-
-/**
- * @brief SYSTICK handler priority.
- * @note The default SYSTICK handler priority is calculated as the priority
- * level in the middle of the numeric priorities range.
- */
-#if !defined(CORTEX_PRIORITY_SYSTICK)
-#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
-
-/**
- * @brief FPU support in context switch.
- * @details Activating this option activates the FPU support in the kernel.
- */
-#if !defined(CORTEX_USE_FPU)
-#define CORTEX_USE_FPU CORTEX_HAS_FPU
-#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
-/* This setting requires an FPU presence check in case it is externally
- redefined.*/
-#error "the selected core does not have an FPU"
-#endif
-
-/**
- * @brief Simplified priority handling flag.
- * @details Activating this option makes the Kernel work in compact mode.
- */
-#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
-#define CORTEX_SIMPLIFIED_PRIORITY FALSE
-#endif
-
-/**
- * @brief SVCALL handler priority.
- * @note The default SVCALL handler priority is defaulted to
- * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
- * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
- * priority level.
- */
-#if !defined(CORTEX_PRIORITY_SVCALL)
-#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
-#endif
-
-/**
- * @brief NVIC VTOR initialization expression.
- */
-#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
-#define CORTEX_VTOR_INIT 0x00000000
-#endif
-
-/**
- * @brief NVIC PRIGROUP initialization expression.
- * @details The default assigns all available priority bits as preemption
- * priority with no sub-priority.
- */
-#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
-#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters. */
-/*===========================================================================*/
-
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief Maximum usable priority for normal ISRs.
- */
-#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
-
-/**
- * @brief BASEPRI level within kernel lock.
- * @note In compact kernel mode this constant value is enforced to zero.
- */
-#define CORTEX_BASEPRI_KERNEL \
- CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY)
-#else
-
-#define CORTEX_MAX_KERNEL_PRIORITY 1
-#define CORTEX_BASEPRI_KERNEL 0
-#endif
-
-/**
- * @brief PendSV priority level.
- * @note This priority is enforced to be equal to
- * @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
- * highest priority that cannot preempt the kernel.
- */
-#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY
-
-/*===========================================================================*/
-/* Port exported info. */
-/*===========================================================================*/
-
-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
-/**
- * @brief Macro defining the specific ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM_v7M
-
-/**
- * @brief Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME "ARMv7-M"
-
-/**
- * @brief Name of the architecture variant.
- */
-#define CH_CORE_VARIANT_NAME "Cortex-M3"
-
-#elif (CORTEX_MODEL == CORTEX_M4)
-#define CH_ARCHITECTURE_ARM_v7ME
-#define CH_ARCHITECTURE_NAME "ARMv7-ME"
-#if CORTEX_USE_FPU
-#define CH_CORE_VARIANT_NAME "Cortex-M4F"
-#else
-#define CH_CORE_VARIANT_NAME "Cortex-M4"
-#endif
-#endif
-
-/**
- * @brief Port-specific information string.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define CH_PORT_INFO "Advanced kernel mode"
-#else
-#define CH_PORT_INFO "Compact kernel mode"
-#endif
-
-/*===========================================================================*/
-/* Port implementation part. */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-/**
- * @brief Generic ARM register.
- */
-typedef void *regarm_t;
-
-/* The documentation of the following declarations is in chconf.h in order
- to not have duplicated structure names into the documentation.*/
-#if !defined(__DOXYGEN__)
-
-typedef uint64_t stkalign_t __attribute__ ((aligned (8)));
-
-struct extctx {
- regarm_t r0;
- regarm_t r1;
- regarm_t r2;
- regarm_t r3;
- regarm_t r12;
- regarm_t lr_thd;
- regarm_t pc;
- regarm_t xpsr;
-#if CORTEX_USE_FPU
- regarm_t s0;
- regarm_t s1;
- regarm_t s2;
- regarm_t s3;
- regarm_t s4;
- regarm_t s5;
- regarm_t s6;
- regarm_t s7;
- regarm_t s8;
- regarm_t s9;
- regarm_t s10;
- regarm_t s11;
- regarm_t s12;
- regarm_t s13;
- regarm_t s14;
- regarm_t s15;
- regarm_t fpscr;
- regarm_t reserved;
-#endif /* CORTEX_USE_FPU */
-};
-
-struct intctx {
-#if CORTEX_USE_FPU
- regarm_t s16;
- regarm_t s17;
- regarm_t s18;
- regarm_t s19;
- regarm_t s20;
- regarm_t s21;
- regarm_t s22;
- regarm_t s23;
- regarm_t s24;
- regarm_t s25;
- regarm_t s26;
- regarm_t s27;
- regarm_t s28;
- regarm_t s29;
- regarm_t s30;
- regarm_t s31;
-#endif /* CORTEX_USE_FPU */
- regarm_t r4;
- regarm_t r5;
- regarm_t r6;
- regarm_t r7;
- regarm_t r8;
- regarm_t r9;
- regarm_t r10;
- regarm_t r11;
- regarm_t lr;
-};
-
-#endif /* !defined(__DOXYGEN__) */
-
-/**
- * @brief Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- * structure representing the stack pointer at context switch time.
- */
-struct context {
- struct intctx *r13;
-};
-
-/**
- * @brief Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = (void *)(pf); \
- tp->p_ctx.r13->r5 = (void *)(arg); \
- tp->p_ctx.r13->lr = (void *)(_port_thread_start); \
-}
-
-/**
- * @brief Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- sizeof(struct intctx) + \
- sizeof(struct extctx) + \
- (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- * aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- * enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- * enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
-
-/**
- * @brief IRQ handler function declaration.
- * @note @p id can be a function name or a vector number depending on the
- * port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief Fast IRQ handler function declaration.
- * @note @p id can be a function name or a vector number depending on the
- * port implementation.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief Port-related initialization code.
- */
-#define port_init() _port_init()
-
-/**
- * @brief Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- * more actions.
- * @note In this port this it raises the base priority to kernel level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
-#define port_lock() { \
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
-}
-#else /* !CH_OPTIMIZE_SPEED */
-#define port_lock() { \
- asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \
-}
-#endif /* !CH_OPTIMIZE_SPEED */
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_lock() asm volatile ("cpsid i" : : : "memory")
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- * more actions.
- * @note In this port this it lowers the base priority to user level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
-#define port_unlock() { \
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
-}
-#else /* !CH_OPTIMIZE_SPEED */
-#define port_unlock() { \
- asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \
-}
-#endif /* !CH_OPTIMIZE_SPEED */
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_unlock() asm volatile ("cpsie i" : : : "memory")
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- * interrupt handlers. The implementation is architecture dependent,
- * in its simplest form it is void.
- * @note Same as @p port_lock() in this port.
- */
-#define port_lock_from_isr() port_lock()
-
-/**
- * @brief Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- * handlers. The implementation is architecture dependent, in its
- * simplest form it is void.
- * @note Same as @p port_unlock() in this port.
- */
-#define port_unlock_from_isr() port_unlock()
-
-/**
- * @brief Disables all the interrupt sources.
- * @note Of course non-maskable interrupt sources are not included.
- * @note In this port it disables all the interrupt sources by raising
- * the priority mask to level 0.
- */
-#define port_disable() asm volatile ("cpsid i" : : : "memory")
-
-/**
- * @brief Disables the interrupt sources below kernel-level priority.
- * @note Interrupt sources above kernel level remains enabled.
- * @note In this port it raises/lowers the base priority to kernel level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_suspend() { \
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
- asm volatile ("msr BASEPRI, %0 \n\t" \
- "cpsie i" : : "r" (tmp) : "memory"); \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_suspend() asm volatile ("cpsid i" : : : "memory")
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief Enables all the interrupt sources.
- * @note In this port it lowers the base priority to user level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_enable() { \
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
- asm volatile ("msr BASEPRI, %0 \n\t" \
- "cpsie i" : : "r" (tmp) : "memory"); \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_enable() asm volatile ("cpsie i" : : : "memory")
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- * The simplest implementation is an empty function or macro but this
- * would not take advantage of architecture-specific power saving
- * modes.
- * @note Implemented as an inlined @p WFI instruction.
- */
-#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() { \
- asm volatile ("wfi" : : : "memory"); \
-}
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- * is responsible for the context switch between 2 threads.
- * @note The implementation of this code affects directly the context
- * switch performance so optimize here as much as you can.
- *
- * @param[in] ntp the thread to be switched in
- * @param[in] otp the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) { \
- register struct intctx *r13 asm ("r13"); \
- if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \
- chDbgPanic("stack overflow"); \
- _port_switch(ntp, otp); \
-}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void port_halt(void);
- void _port_init(void);
- void _port_irq_epilogue(void);
- void _port_switch_from_isr(void);
- void _port_exit_from_isr(void);
- void _port_switch(Thread *ntp, Thread *otp);
- void _port_thread_start(void);
-#if !CH_OPTIMIZE_SPEED
- void _port_lock(void);
- void _port_unlock(void);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_V7M_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chtypes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chtypes.h
deleted file mode 100644
index 4024cbd75b..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/chtypes.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file GCC/ARMCMx/chtypes.h
- * @brief ARM Cortex-Mx port system types.
- *
- * @addtogroup ARMCMx_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include
-#include
-#include
-
-typedef bool bool_t; /**< Fast boolean type. */
-typedef uint8_t tmode_t; /**< Thread flags. */
-typedef uint8_t tstate_t; /**< Thread state. */
-typedef uint8_t trefs_t; /**< Thread references counter. */
-typedef uint8_t tslices_t; /**< Thread time slices counter. */
-typedef uint32_t tprio_t; /**< Thread priority. */
-typedef int32_t msg_t; /**< Inter-thread message. */
-typedef int32_t eventid_t; /**< Event Id. */
-typedef uint32_t eventmask_t; /**< Event mask. */
-typedef uint32_t flagsmask_t; /**< Event flags. */
-typedef uint32_t systime_t; /**< System time. */
-typedef int32_t cnt_t; /**< Resources counter. */
-
-/**
- * @brief Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief ROM constant modifier.
- * @note It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief Packed structure modifier (within).
- * @note It uses the "packed" GCC attribute.
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief Packed structure modifier (before).
- * @note Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief Packed structure modifier (after).
- * @note Empty in this port.
- */
-#define PACK_STRUCT_END
-
-/**
- * @brief Packed variable specifier.
- */
-#define PACKED_VAR __attribute__((packed))
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/crt0.c b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/crt0.c
deleted file mode 100644
index b08a78641f..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/crt0.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file ARMCMx/crt0.c
- * @brief Generic ARMvx-M (Cortex-M0/M1/M3/M4) startup file for ChibiOS/RT.
- *
- * @addtogroup ARMCMx_STARTUP
- * @{
- */
-
-#include
-
-#if !defined(FALSE)
-#define FALSE 0
-#endif
-
-#if !defined(TRUE)
-#define TRUE (!FALSE)
-#endif
-
-#define SCB_CPACR *((uint32_t *)0xE000ED88U)
-#define SCB_FPCCR *((uint32_t *)0xE000EF34U)
-#define SCB_FPDSCR *((uint32_t *)0xE000EF3CU)
-#define FPCCR_ASPEN (0x1U << 31)
-#define FPCCR_LSPEN (0x1U << 30)
-
-typedef void (*funcp_t)(void);
-typedef funcp_t * funcpp_t;
-
-#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
-
-/*
- * Area fill code, it is a macro because here functions cannot be called
- * until stacks are initialized.
- */
-#define fill32(start, end, filler) { \
- uint32_t *p1 = start; \
- uint32_t *p2 = end; \
- while (p1 < p2) \
- *p1++ = filler; \
-}
-
-/*===========================================================================*/
-/**
- * @name Startup settings
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief Control special register initialization value.
- * @details The system is setup to run in privileged mode using the PSP
- * stack (dual stack mode).
- */
-#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
-#define CRT0_CONTROL_INIT 0x00000002
-#endif
-
-/**
- * @brief Stack segments initialization switch.
- */
-#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
-#define CRT0_STACKS_FILL_PATTERN 0x55555555
-#endif
-
-/**
- * @brief Stack segments initialization switch.
- */
-#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
-#define CRT0_INIT_STACKS TRUE
-#endif
-
-/**
- * @brief DATA segment initialization switch.
- */
-#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
-#define CRT0_INIT_DATA TRUE
-#endif
-
-/**
- * @brief BSS segment initialization switch.
- */
-#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
-#define CRT0_INIT_BSS TRUE
-#endif
-
-/**
- * @brief Constructors invocation switch.
- */
-#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
-#define CRT0_CALL_CONSTRUCTORS TRUE
-#endif
-
-/**
- * @brief Destructors invocation switch.
- */
-#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
-#define CRT0_CALL_DESTRUCTORS TRUE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name Symbols from the scatter file
- */
-/*===========================================================================*/
-
-/**
- * @brief Main stack lower boundary.
- * @details This symbol must be exported by the linker script and represents
- * the main stack lower boundary.
- */
-extern uint32_t __main_stack_base__;
-
-/**
- *
- * @brief Main stack initial position.
- * @details This symbol must be exported by the linker script and represents
- * the main stack initial position.
- */
-extern uint32_t __main_stack_end__;
-
-/**
- * @brief Process stack lower boundary.
- * @details This symbol must be exported by the linker script and represents
- * the process stack lower boundary.
- */
-extern uint32_t __process_stack_base__;
-
-/**
- * @brief Process stack initial position.
- * @details This symbol must be exported by the linker script and represents
- * the process stack initial position.
- */
-extern uint32_t __process_stack_end__;
-
-/**
- * @brief ROM image of the data segment start.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _textdata;
-
-/**
- * @brief Data segment start.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _data;
-
-/**
- * @brief Data segment end.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _edata;
-
-/**
- * @brief BSS segment start.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _bss_start;
-
-/**
- * @brief BSS segment end.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _bss_end;
-
-/**
- * @brief CCM BSS segment start.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _cmm_start;
-
-/**
- * @brief CCM BSS segment end.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _cmm_end;
-
-/**
- * @brief Constructors table start.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __init_array_start;
-
-/**
- * @brief Constructors table end.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __init_array_end;
-
-/**
- * @brief Destructors table start.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __fini_array_start;
-
-/**
- * @brief Destructors table end.
- * @pre The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __fini_array_end;
-
-/** @} */
-
-/**
- * @brief Application @p main() function.
- */
-extern void main(void);
-
-/**
- * @brief Early initialization.
- * @details This hook is invoked immediately after the stack initialization
- * and before the DATA and BSS segments initialization. The
- * default behavior is to do nothing.
- * @note This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void __early_init(void) {}
-
-/**
- * @brief Late initialization.
- * @details This hook is invoked after the DATA and BSS segments
- * initialization and before any static constructor. The
- * default behavior is to do nothing.
- * @note This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void __late_init(void) {}
-
-/**
- * @brief Default @p main() function exit handler.
- * @details This handler is invoked or the @p main() function exit. The
- * default behavior is to enter an infinite loop.
- * @note This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak, naked))
-#endif
-void _default_exit(void) {
- while (1)
- ;
-}
-
-/**
- * @brief Reset vector.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void ResetHandler(void) {
- uint32_t psp, reg;
-
- /* Process Stack initialization, it is allocated starting from the
- symbol __process_stack_end__ and its lower limit is the symbol
- __process_stack_base__.*/
- asm volatile ("cpsid i");
- psp = SYMVAL(__process_stack_end__);
- asm volatile ("msr PSP, %0" : : "r" (psp));
-
-#if CORTEX_USE_FPU
- /* Initializing the FPU context save in lazy mode.*/
- SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
-
- /* CP10 and CP11 set to full access.*/
- SCB_CPACR |= 0x00F00000;
-
- /* FPSCR and FPDSCR initially zero.*/
- reg = 0;
- asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory");
- SCB_FPDSCR = reg;
-
- /* CPU mode initialization, enforced FPCA bit.*/
- reg = CRT0_CONTROL_INIT | 4;
-#else
- /* CPU mode initialization.*/
- reg = CRT0_CONTROL_INIT;
-#endif
- asm volatile ("msr CONTROL, %0" : : "r" (reg));
- asm volatile ("isb");
-
-#if CRT0_INIT_STACKS
- /* Main and Process stacks initialization.*/
- fill32(&__main_stack_base__,
- &__main_stack_end__,
- CRT0_STACKS_FILL_PATTERN);
- fill32(&__process_stack_base__,
- &__process_stack_end__,
- CRT0_STACKS_FILL_PATTERN);
-#endif
-
- /* Early initialization hook invocation.*/
- __early_init();
-
-#if CRT0_INIT_DATA
- /* DATA segment initialization.*/
- {
- uint32_t *tp, *dp;
-
- tp = &_textdata;
- dp = &_data;
- while (dp < &_edata)
- *dp++ = *tp++;
- }
-#endif
-
-#if CRT0_INIT_BSS
- /* BSS segment initialization.*/
- fill32(&_bss_start, &_bss_end, 0);
-
- /* CCM-SRAM BSS initialization */
- fill32(&_cmm_start, &_cmm_end, 0);
-#endif
-
- /* Late initialization hook invocation.*/
- __late_init();
-
-#if CRT0_CALL_CONSTRUCTORS
- /* Constructors invocation.*/
- {
- funcpp_t fpp = &__init_array_start;
- while (fpp < &__init_array_end) {
- (*fpp)();
- fpp++;
- }
- }
-#endif
-
- /* Invoking application main() function.*/
- main();
-
-#if CRT0_CALL_DESTRUCTORS
- /* Destructors invocation.*/
- {
- funcpp_t fpp = &__fini_array_start;
- while (fpp < &__fini_array_end) {
- (*fpp)();
- fpp++;
- }
- }
-#endif
-
- /* Invoking the exit handler.*/
- _default_exit();
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/port.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/port.dox
deleted file mode 100644
index a411fc2941..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/GCC/ARMCMx/port.dox
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup ARMCMx ARM Cortex-Mx
- * @details ARM Cortex-Mx port for the GCC compiler.
- *
- * @section ARMCMx_INTRO Introduction
- * This port supports all the cores implementing the ARMv6-M and ARMv7-M
- * architectures.
- *
- * @section ARMCMx_MODES Kernel Modes
- * The Cortex-Mx port supports two distinct kernel modes:
- * - Advanced Kernel mode. In this mode the kernel only masks
- * interrupt sources with priorities below or equal to the
- * @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
- * the kernel critical sections and can be used for fast interrupts.
- * This mode is not available in the ARMv6-M architecture which does not
- * support priority masking.
- * - Compact Kernel mode. In this mode the kernel handles IRQ priorities
- * in a simplified way, all interrupt sources are disabled when the kernel
- * enters into a critical zone and re-enabled on exit. This is simple and
- * adequate for most applications, this mode results in a more compact and
- * faster kernel.
- * .
- * The selection of the mode is performed using the port configuration option
- * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
- * interrupts there are no other differences between the two modes. The
- * kernel API is exactly the same.
- *
- * @section ARMCMx_STATES_A System logical states in Compact Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
- * Kernel mode:
- * - Init. This state is represented by the startup code and the
- * initialization code before @p chSysInit() is executed. It has not a
- * special hardware state associated.
- * - Normal. This is the state the system has after executing
- * @p chSysInit(). In this state interrupts are enabled. The processor
- * is running in thread-privileged mode.
- * - Suspended. In this state the interrupt sources are globally
- * disabled. The processor is running in thread-privileged mode. In this
- * mode this state is not different from the Disabled state.
- * - Disabled. In this state the interrupt sources are globally
- * disabled. The processor is running in thread-privileged mode. In this
- * mode this state is not different from the Suspended state.
- * - Sleep. This state is entered with the execution of the specific
- * instruction @p wfi.
- * - S-Locked. In this state the interrupt sources are globally
- * disabled. The processor is running in thread-privileged mode.
- * - I-Locked. In this state the interrupt sources are globally
- * disabled. The processor is running in exception-privileged mode.
- * - Serving Regular Interrupt. In this state the interrupt sources are
- * not globally masked but only interrupts with higher priority can preempt
- * the current handler. The processor is running in exception-privileged
- * mode.
- * - Serving Fast Interrupt. Not implemented in compact kernel mode.
- * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific
- * asynchronous NMI vector and several synchronous fault vectors that can
- * be considered belonging to this category.
- * - Halted. Implemented as an infinite loop after globally masking all
- * the maskable interrupt sources. The ARM state is whatever the processor
- * was running when @p chSysHalt() was invoked.
- *
- * @section ARMCMx_STATES_B System logical states in Advanced Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the
- * Advanced Kernel mode:
- * - Init. This state is represented by the startup code and the
- * initialization code before @p chSysInit() is executed. It has not a
- * special hardware state associated.
- * - Normal. This is the state the system has after executing
- * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
- * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
- * processor is running in thread-privileged mode.
- * - Suspended. In this state the interrupt sources are not globally
- * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- * masking any interrupt source with lower or equal priority. The processor
- * is running in thread-privileged mode.
- * - Disabled. Interrupt sources are globally masked. The processor
- * is running in thread-privileged mode.
- * - Sleep. This state is entered with the execution of the specific
- * instruction @p wfi.
- * - S-Locked. In this state the interrupt sources are not globally
- * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- * masking any interrupt source with lower or equal priority. The processor
- * is running in thread-privileged mode.
- * - I-Locked. In this state the interrupt sources are not globally
- * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- * masking any interrupt source with lower or equal priority. The processor
- * is running in exception-privileged mode.
- * - Serving Regular Interrupt. In this state the interrupt sources are
- * not globally masked but only interrupts with higher priority can preempt
- * the current handler. The processor is running in exception-privileged
- * mode.
- * - Serving Fast Interrupt. Fast interrupts are defined as interrupt
- * sources having higher priority level than the kernel
- * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to
- * the I-Locked state because fast interrupts can preempt the kernel
- * critical zone.
- * This state is not implemented in the ARMv6-M implementation because
- * priority masking is not present in this architecture.
- * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific
- * asynchronous NMI vector and several synchronous fault vectors that can
- * be considered belonging to this category.
- * - Halted. Implemented as an infinite loop after globally masking all
- * the maskable interrupt sources. The ARM state is whatever the processor
- * was running when @p chSysHalt() was invoked.
- * .
- * @section ARMCMx_NOTES ARM Cortex-Mx/GCC port notes
- * The ARM Cortex-Mx port is organized as follow:
- * - The @p main() function is invoked in thread-privileged mode.
- * - Each thread has a private process stack, the system has a single main
- * stack where all the interrupts and exceptions are processed.
- * - The threads are started in thread-privileged mode.
- * - Interrupt nesting and the other advanced core/NVIC features are supported.
- * - The Cortex-Mx port is perfectly generic, support for more devices can be
- * easily added by adding a subdirectory under ./os/ports/GCC/ARMCMx
- * and giving it the name of the new device, then copy the files from another
- * device into the new directory and customize them for the new device.
- * .
- * @ingroup gcc
- */
-
-/**
- * @defgroup ARMCMx_CONF Configuration Options
- * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
- * by an interrupt handler between the @p extctx and @p intctx
- * structures.
- * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
- * thread. Usually there is no need to change this value unless inserting
- * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
- * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
- * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
- * @p wfi instruction from within the idle loop. This option is
- * defaulted to FALSE because it can create problems with some debuggers.
- * Setting this option to TRUE reduces the system power requirements.
- * .
- * @section ARMCMx_CONF_1 ARMv6-M specific options
- * The following options are specific for the ARMv6-M architecture:
- * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
- * exception instead of NMI as preemption handler.
- * .
- * @section ARMCMx_CONF_2 ARMv7-M specific options
- * The following options are specific for the ARMv6-M architecture:
- * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
- * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
- * mode.
- * .
- * @ingroup ARMCMx
- */
-
-/**
- * @defgroup ARMCMx_CORE Core Port Implementation
- * @details ARM Cortex-Mx specific port code, structures and macros.
- *
- * @ingroup ARMCMx
- */
-
-/**
- * @defgroup ARMCMx_V6M_CORE ARMv6-M Specific Implementation
- * @details ARMv6-M specific port code, structures and macros.
- *
- * @ingroup ARMCMx_CORE
- */
-
-/**
- * @defgroup ARMCMx_V7M_CORE ARMv7-M Specific Implementation
- * @details ARMv7-M specific port code, structures and macros.
- *
- * @ingroup ARMCMx_CORE
- */
-
-/**
- * @defgroup ARMCMx_STARTUP Startup Support
- * @details ChibiOS/RT provides its own generic startup file for the ARM
- * Cortex-Mx port.
- * Of course it is not mandatory to use it but care should be taken about the
- * startup phase details.
- *
- * @section ARMCMx_STARTUP_1 Startup Process
- * The startup process, as implemented, is the following:
- * -# Interrupts are masked globally.
- * -# The two stacks are initialized by assigning them the sizes defined in
- * the linker script (also known as scatter file).
- * -# The CPU state is switched to Privileged and the PSP stack is used.
- * -# An early initialization routine @p __early_init() is invoked, if the
- * symbol is not defined then an empty default routine is executed
- * (weak symbol).
- * -# DATA and BSS segments are initialized.
- * -# Constructors are invoked.
- * -# The @p main() function is invoked with no parameters.
- * -# Destructors are invoked.
- * -# A branch is performed to the weak symbol @p _default_exit(). The
- * default code is an endless empty loop.
- * .
- * @section ARMCMx_STARTUP_2 Expected linker symbols
- * The startup code starts at the symbol @p ResetHandler and expects the
- * following symbols to be defined in the linker script:
- * - @p __ram_end__, end of RAM.
- * - @p __main_stack_base__, main stack lower boundary.
- * - @p __main_stack_end__, main stack initial position.
- * - @p __process_stack_base__, process stack lower boundary.
- * - @p __process_stack_end__, process stack initial position.
- * - @p _textdata, address of the data segment source read only data.
- * - @p _data, start of the data segment.
- * - @p _edata, end of the data segment end location.
- * - @p _bss_start, start of the BSS.
- * - @p _bss_end, end of the BSS segment.
- * - @p __init_array_start, start of the constructors array.
- * - @p __init_array_end, end of the constructors array.
- * - @p __fini_array_start, start of the destructors array.
- * - @p __fini_array_end, end of the destructors array.
- * .
- * Additionally the kernel expects the following symbols:
- * - @p __main_thread_stack_base__, this symbol is required when the
- * stack checking is enabled (CH_DBG_ENABLE_STACK_CHECK==TRUE),
- * it is an alias of @p __process_stack_base__ in this port.
- * - @p __heap_base__ and @p __heap_end__, those symbols are required
- * if the memory core manager is enabled (CH_USE_MEMCORE==TRUE)
- * with a default core size set to zero (CH_MEMCORE_SIZE==0).
- * .
- * @ingroup ARMCMx
- */
-
-/**
- * @defgroup ARMCMx_SPECIFIC Specific Implementations
- * @details Platform-specific port code.
- *
- * @ingroup ARMCMx
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/nvic.c b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/nvic.c
deleted file mode 100644
index 15ef4a03ab..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/nvic.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file common/ARMCMx/nvic.c
- * @brief Cortex-Mx NVIC support code.
- *
- * @addtogroup COMMON_ARMCMx_NVIC
- * @{
- */
-
-#include "ch.h"
-#include "nvic.h"
-
-/**
- * @brief Sets the priority of an interrupt handler and enables it.
- * @note The parameters are not tested for correctness.
- *
- * @param[in] n the interrupt number
- * @param[in] prio the interrupt priority mask
- */
-void nvicEnableVector(uint32_t n, uint32_t prio) {
- unsigned sh = (n & 3) << 3;
-
- NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
- NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);
- NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
-}
-
-/**
- * @brief Disables an interrupt handler.
- * @note The parameters are not tested for correctness.
- *
- * @param[in] n the interrupt number
- */
-void nvicDisableVector(uint32_t n) {
- unsigned sh = (n & 3) << 3;
-
- NVIC_ICER(n >> 5) = 1 << (n & 0x1F);
- NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh);
-}
-
-/**
- * @brief Changes the priority of a system handler.
- * @note The parameters are not tested for correctness.
- *
- * @param[in] handler the system handler number
- * @param[in] prio the system handler priority mask
- */
-void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
- unsigned sh = (handler & 3) * 8;
-
- SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &
- ~(0xFF << sh)) | (prio << sh);
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/nvic.h b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/nvic.h
deleted file mode 100644
index 3419bc457b..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/nvic.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file common/ARMCMx/nvic.h
- * @brief Cortex-Mx NVIC support macros and structures.
- *
- * @addtogroup COMMON_ARMCMx_NVIC
- * @{
- */
-
-#ifndef _NVIC_H_
-#define _NVIC_H_
-
-/**
- * @name System vector numbers
- * @{
- */
-#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */
-#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */
-#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */
-#define HANDLER_RESERVED_3 3
-#define HANDLER_RESERVED_4 4
-#define HANDLER_RESERVED_5 5
-#define HANDLER_RESERVED_6 6
-#define HANDLER_SVCALL 7 /**< SVCALL vector id. */
-#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */
-#define HANDLER_RESERVED_9 9
-#define HANDLER_PENDSV 10 /**< PENDSV vector id. */
-#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */
-/** @} */
-
-typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */
-typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
-
-/**
- * @brief NVIC ITCR register.
- */
-#define NVIC_ITCR (*((IOREG32 *)0xE000E004U))
-
-/**
- * @brief Structure representing the SYSTICK I/O space.
- */
-typedef struct {
- IOREG32 CSR;
- IOREG32 RVR;
- IOREG32 CVR;
- IOREG32 CBVR;
-} CMx_ST;
-
-/**
- * @brief SYSTICK peripheral base address.
- */
-#define STBase ((CMx_ST *)0xE000E010U)
-#define ST_CSR (STBase->CSR)
-#define ST_RVR (STBase->RVR)
-#define ST_CVR (STBase->CVR)
-#define ST_CBVR (STBase->CBVR)
-
-#define CSR_ENABLE_MASK (0x1U << 0)
-#define ENABLE_OFF_BITS (0U << 0)
-#define ENABLE_ON_BITS (1U << 0)
-#define CSR_TICKINT_MASK (0x1U << 1)
-#define TICKINT_DISABLED_BITS (0U << 1)
-#define TICKINT_ENABLED_BITS (1U << 1)
-#define CSR_CLKSOURCE_MASK (0x1U << 2)
-#define CLKSOURCE_EXT_BITS (0U << 2)
-#define CLKSOURCE_CORE_BITS (1U << 2)
-#define CSR_COUNTFLAG_MASK (0x1U << 16)
-
-#define RVR_RELOAD_MASK (0xFFFFFFU << 0)
-
-#define CVR_CURRENT_MASK (0xFFFFFFU << 0)
-
-#define CBVR_TENMS_MASK (0xFFFFFFU << 0)
-#define CBVR_SKEW_MASK (0x1U << 30)
-#define CBVR_NOREF_MASK (0x1U << 31)
-
-/**
- * @brief Structure representing the NVIC I/O space.
- */
-typedef struct {
- IOREG32 ISER[8];
- IOREG32 unused1[24];
- IOREG32 ICER[8];
- IOREG32 unused2[24];
- IOREG32 ISPR[8];
- IOREG32 unused3[24];
- IOREG32 ICPR[8];
- IOREG32 unused4[24];
- IOREG32 IABR[8];
- IOREG32 unused5[56];
- IOREG32 IPR[60];
- IOREG32 unused6[644];
- IOREG32 STIR;
-} CMx_NVIC;
-
-/**
- * @brief NVIC peripheral base address.
- */
-#define NVICBase ((CMx_NVIC *)0xE000E100U)
-#define NVIC_ISER(n) (NVICBase->ISER[n])
-#define NVIC_ICER(n) (NVICBase->ICER[n])
-#define NVIC_ISPR(n) (NVICBase->ISPR[n])
-#define NVIC_ICPR(n) (NVICBase->ICPR[n])
-#define NVIC_IABR(n) (NVICBase->IABR[n])
-#define NVIC_IPR(n) (NVICBase->IPR[n])
-#define NVIC_STIR (NVICBase->STIR)
-
-/**
- * @brief Structure representing the System Control Block I/O space.
- */
-typedef struct {
- IOREG32 CPUID;
- IOREG32 ICSR;
- IOREG32 VTOR;
- IOREG32 AIRCR;
- IOREG32 SCR;
- IOREG32 CCR;
- IOREG32 SHPR[3];
- IOREG32 SHCSR;
- IOREG32 CFSR;
- IOREG32 HFSR;
- IOREG32 DFSR;
- IOREG32 MMFAR;
- IOREG32 BFAR;
- IOREG32 AFSR;
- IOREG32 PFR[2];
- IOREG32 DFR;
- IOREG32 ADR;
- IOREG32 MMFR[4];
- IOREG32 SAR[5];
- IOREG32 unused1[5];
- IOREG32 CPACR;
-} CMx_SCB;
-
-/**
- * @brief SCB peripheral base address.
- */
-#define SCBBase ((CMx_SCB *)0xE000ED00U)
-#define SCB_CPUID (SCBBase->CPUID)
-#define SCB_ICSR (SCBBase->ICSR)
-#define SCB_VTOR (SCBBase->VTOR)
-#define SCB_AIRCR (SCBBase->AIRCR)
-#define SCB_SCR (SCBBase->SCR)
-#define SCB_CCR (SCBBase->CCR)
-#define SCB_SHPR(n) (SCBBase->SHPR[n])
-#define SCB_SHCSR (SCBBase->SHCSR)
-#define SCB_CFSR (SCBBase->CFSR)
-#define SCB_HFSR (SCBBase->HFSR)
-#define SCB_DFSR (SCBBase->DFSR)
-#define SCB_MMFAR (SCBBase->MMFAR)
-#define SCB_BFAR (SCBBase->BFAR)
-#define SCB_AFSR (SCBBase->AFSR)
-#define SCB_PFR(n) (SCBBase->PFR[n])
-#define SCB_DFR (SCBBase->DFR)
-#define SCB_ADR (SCBBase->ADR)
-#define SCB_MMFR(n) (SCBBase->MMFR[n])
-#define SCB_SAR(n) (SCBBase->SAR[n])
-#define SCB_CPACR (SCBBase->CPACR)
-
-#define ICSR_VECTACTIVE_MASK (0x1FFU << 0)
-#define ICSR_RETTOBASE (0x1U << 11)
-#define ICSR_VECTPENDING_MASK (0x1FFU << 12)
-#define ICSR_ISRPENDING (0x1U << 22)
-#define ICSR_ISRPREEMPT (0x1U << 23)
-#define ICSR_PENDSTCLR (0x1U << 25)
-#define ICSR_PENDSTSET (0x1U << 26)
-#define ICSR_PENDSVCLR (0x1U << 27)
-#define ICSR_PENDSVSET (0x1U << 28)
-#define ICSR_NMIPENDSET (0x1U << 31)
-
-#define AIRCR_VECTKEY 0x05FA0000U
-#define AIRCR_PRIGROUP_MASK (0x7U << 8)
-#define AIRCR_PRIGROUP(n) ((n) << 8)
-
-/**
- * @brief Structure representing the FPU I/O space.
- */
-typedef struct {
- IOREG32 unused1[1];
- IOREG32 FPCCR;
- IOREG32 FPCAR;
- IOREG32 FPDSCR;
- IOREG32 MVFR0;
- IOREG32 MVFR1;
-} CMx_FPU;
-
-/**
- * @brief FPU peripheral base address.
- */
-#define FPUBase ((CMx_FPU *)0xE000EF30U)
-#define SCB_FPCCR (FPUBase->FPCCR)
-#define SCB_FPCAR (FPUBase->FPCAR)
-#define SCB_FPDSCR (FPUBase->FPDSCR)
-#define SCB_MVFR0 (FPUBase->MVFR0)
-#define SCB_MVFR1 (FPUBase->MVFR1)
-
-#define FPCCR_ASPEN (0x1U << 31)
-#define FPCCR_LSPEN (0x1U << 30)
-#define FPCCR_MONRDY (0x1U << 8)
-#define FPCCR_BFRDY (0x1U << 6)
-#define FPCCR_MMRDY (0x1U << 5)
-#define FPCCR_HFRDY (0x1U << 4)
-#define FPCCR_THREAD (0x1U << 3)
-#define FPCCR_USER (0x1U << 1)
-#define FPCCR_LSPACT (0x1U << 0)
-
-#define FPDSCR_AHP (0x1U << 26)
-#define FPDSCR_DN (0x1U << 25)
-#define FPDSCR_FZ (0x1U << 24)
-#define FPDSCR_RMODE(n) ((n##U) << 22)
-
-/**
- * @brief Structure representing the SCS I/O space.
- */
-typedef struct {
- IOREG32 DHCSR;
- IOREG32 DCRSR;
- IOREG32 DCRDR;
- IOREG32 DEMCR;
-} CMx_SCS;
-
-/**
- * @brief SCS peripheral base address.
- */
-#define SCSBase ((CMx_SCS *)0xE000EDF0U)
-#define SCS_DHCSR (SCSBase->DHCSR)
-#define SCS_DCRSR (SCSBase->DCRSR)
-#define SCS_DCRDR (SCSBase->DCRDR)
-#define SCS_DEMCR (SCSBase->DEMCR)
-
-#define SCS_DEMCR_TRCENA (0x1U << 24)
-
-/**
- * @brief Structure representing the DWT I/O space.
- */
-typedef struct {
- IOREG32 CTRL;
- IOREG32 CYCCNT;
- IOREG32 CPICNT;
- IOREG32 EXCCNT;
- IOREG32 SLEEPCNT;
- IOREG32 LSUCNT;
- IOREG32 FOLDCNT;
- IOREG32 PCSR;
-} CMx_DWT;
-
-/**
- * @brief DWT peripheral base address.
- */
-#define DWTBase ((CMx_DWT *)0xE0001000U)
-#define DWT_CTRL (DWTBase->CTRL)
-#define DWT_CYCCNT (DWTBase->CYCCNT)
-#define DWT_CPICNT (DWTBase->CPICNT)
-#define DWT_EXCCNT (DWTBase->EXCCNT)
-#define DWT_SLEEPCNT (DWTBase->SLEEPCNT)
-#define DWT_LSUCNT (DWTBase->LSUCNT)
-#define DWT_FOLDCNT (DWTBase->FOLDCNT)
-#define DWT_PCSR (DWTBase->PCSR)
-
-#define DWT_CTRL_CYCCNTENA (0x1U << 0)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void nvicEnableVector(uint32_t n, uint32_t prio);
- void nvicDisableVector(uint32_t n);
- void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NVIC_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/port.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/port.dox
deleted file mode 100644
index 2611a45c6b..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/common/ARMCMx/port.dox
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup COMMON_ARMCMx ARM Cortex-Mx Common Code
- * @ingroup port_common
- */
-
-/**
- * @defgroup COMMON_ARMCMx_NVIC NVIC Support
- * @details ARM Cortex-Mx NVIC support.
- *
- * @ingroup COMMON_ARMCMx
- */
-
- /** @} */
-
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/ports.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/ports/ports.dox
deleted file mode 100644
index 2b5d4d6709..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/ports/ports.dox
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
-*/
-
-/**
- * @defgroup ports Ports
- * This section describes the technical details of the various supported
- * ChibiOS/RT ports.
- */
-
-/**
- * @defgroup port_common Common Code
- * Code common to all compilers.
- *
- * @ingroup ports
- */
-
-/**
- * @defgroup gcc GCC Ports
- * Ports for the GCC compiler or derivatives.
- *
- * @ingroup ports
- */
-
-/**
- * @defgroup iar IAR Ports
- * Ports for the IAR compiler.
- *
- * @ingroup ports
- */
-
-/**
- * @defgroup rvct RVCT Ports
- * Ports for the RVCT compiler.
- *
- * @ingroup ports
- */
-
-/* *
- * @defgroup cosmic Cosmic Compiler Ports
- * Ports for the Compiler compiler.
- *
- * @ingroup ports
- */
-
-/* *
- * @defgroup raisonance Raisonance Compiler Ports
- * Ports for the Raisonance compiler.
- *
- * @ingroup ports
- */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/readme.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/readme.txt
new file mode 100644
index 0000000000..91827ecc93
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/readme.txt
@@ -0,0 +1,29 @@
+*****************************************************************************
+*** ChibiOS products directory organization ***
+*****************************************************************************
+
+--{root} - Distribution directory.
+ +--os/ - ChibiOS products, this directory.
+ | +--rt/ - ChibiOS/RT product.
+ | | +--include/ - RT kernel headers.
+ | | +--src/ - RT kernel sources.
+ | | +--templates/ - RT kernel port template files.
+ | | +--ports/ - RT kernel port files.
+ | | +--osal/ - RT kernel OSAL module for HAL interface.
+ | +--nil/ - ChibiOS/NIL product.
+ | | +--include/ - Nil kernel headers.
+ | | +--src/ - Nil kernel sources.
+ | | +--templates/ - Nil kernel port template files.
+ | | +--ports/ - Nil kernel port files.
+ | | +--osal/ - Nil kernel OSAL module for HAL interface.
+ | +--hal/ - ChibiOS/HAL product.
+ | | +--include/ - HAL high level headers.
+ | | +--src/ - HAL high level sources.
+ | | +--templates/ - HAL port template files.
+ | | +--ports/ - HAL port files (low level drivers implementations).
+ | | +--boards/ - HAL board files.
+ | +--common/ - Files used by multiple ChibiOS products.
+ | | +--ports - Common port files for various architectures and
+ | | compilers.
+ | +--various/ - Various portable support files.
+ | +--ext/ - Vendor files used by ChibiOS products.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/kernel.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/dox/rt.dox
similarity index 68%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/kernel/kernel.dox
rename to flight/PiOS/Common/Libraries/ChibiOS/os/rt/dox/rt.dox
index ee3a3a225a..ce83dd2c02 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/kernel.dox
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/dox/rt.dox
@@ -1,32 +1,24 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
- This file is part of ChibiOS/RT.
+ This file is part of ChibiOS.
- ChibiOS/RT is free software; you can redistribute it and/or modify
+ ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
- ChibiOS/RT is distributed in the hope that it will be useful,
+ ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
*/
/**
- * @defgroup kernel Kernel
+ * @defgroup kernel RT Kernel
* @details The kernel is the portable part of ChibiOS/RT, this section
* documents the various kernel subsystems.
*/
@@ -42,9 +34,7 @@
*/
/**
- * @defgroup types Types
- * @details The system types are defined into the port layer, please refer to
- * the core port implementation section.
+ * @defgroup checks License Checks
* @ingroup kernel
*/
@@ -117,8 +107,9 @@
*/
/**
- * @defgroup io_queues I/O Queues
- * @ingroup synchronization
+ * @defgroup mem Memory Alignment
+ * @details Memory Alignment services.
+ * @ingroup kernel
*/
/**
@@ -147,39 +138,33 @@
* @ingroup memory
*/
- /**
- * @defgroup streams Streams and Files
- * @details Stream and Files interfaces.
- * @ingroup kernel
- */
-
/**
- * @defgroup data_streams Abstract Sequential Streams
- * @ingroup streams
+ * @defgroup registry Registry
+ * @ingroup kernel
*/
/**
- * @defgroup data_files Abstract File Streams
- * @ingroup streams
+ * @defgroup debug Debug
+ * @ingroup kernel
*/
/**
- * @defgroup registry Registry
+ * @defgroup trace Trace
* @ingroup kernel
*/
/**
- * @defgroup debug Debug
+ * @defgroup time_measurement Time Measurement
* @ingroup kernel
*/
/**
- * @defgroup internals Internals
+ * @defgroup statistics Statistics
* @ingroup kernel
*/
/**
- * @defgroup core Port
+ * @defgroup core Port Layer
* @ingroup kernel
*/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/ch.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/ch.h
new file mode 100644
index 0000000000..c8f55ecd10
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/ch.h
@@ -0,0 +1,111 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file ch.h
+ * @brief ChibiOS/RT main include file.
+ * @details This header includes all the required kernel headers so it is the
+ * only kernel header you usually want to include in your application.
+ *
+ * @addtogroup kernel_info
+ * @details Kernel related info.
+ * @{
+ */
+
+#ifndef CH_H
+#define CH_H
+
+/**
+ * @brief ChibiOS/RT identification macro.
+ */
+#define _CHIBIOS_RT_
+
+/**
+ * @brief Stable release flag.
+ */
+#define CH_KERNEL_STABLE 1
+
+/**
+ * @name ChibiOS/RT version identification
+ * @{
+ */
+/**
+ * @brief Kernel version string.
+ */
+#define CH_KERNEL_VERSION "4.0.3"
+
+/**
+ * @brief Kernel version major number.
+ */
+#define CH_KERNEL_MAJOR 4
+
+/**
+ * @brief Kernel version minor number.
+ */
+#define CH_KERNEL_MINOR 0
+
+/**
+ * @brief Kernel version patch number.
+ */
+#define CH_KERNEL_PATCH 3
+/** @} */
+
+/* Core headers.*/
+#include "chtypes.h"
+#include "chconf.h"
+
+#if !defined(_CHIBIOS_RT_CONF_)
+#error "invalid configuration file"
+#endif
+
+#include "chlicense.h"
+#include "chchecks.h"
+#include "chsystypes.h"
+#include "chalign.h"
+#include "chcore.h"
+#include "chdebug.h"
+#include "chtrace.h"
+#include "chtm.h"
+#include "chstats.h"
+#include "chschd.h"
+#include "chsys.h"
+#include "chvt.h"
+#include "chthreads.h"
+
+/* Optional subsystems headers.*/
+#include "chregistry.h"
+#include "chsem.h"
+#include "chbsem.h"
+#include "chmtx.h"
+#include "chcond.h"
+#include "chevents.h"
+#include "chmsg.h"
+#include "chmboxes.h"
+#include "chmemcore.h"
+#include "chheap.h"
+#include "chmempools.h"
+#include "chdynamic.h"
+
+#if !defined(_CHIBIOS_RT_CONF_)
+#error "missing or wrong configuration file"
+#endif
+
+#endif /* CH_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chalign.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chalign.h
new file mode 100644
index 0000000000..fd64342117
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chalign.h
@@ -0,0 +1,119 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chalign.h
+ * @brief Memory alignment macros and structures.
+ *
+ * @addtogroup mem
+ * @{
+ */
+
+#ifndef CHALIGN_H
+#define CHALIGN_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name Memory alignment support macros
+ */
+/**
+ * @brief Alignment mask constant.
+ *
+ * @param[in] a alignment, must be a power of two
+ */
+#define MEM_ALIGN_MASK(a) ((size_t)(a) - 1U)
+
+/**
+ * @brief Aligns to the previous aligned memory address.
+ *
+ * @param[in] p variable to be aligned
+ * @param[in] a alignment, must be a power of two
+ */
+#define MEM_ALIGN_PREV(p, a) \
+ /*lint -save -e9033 [10.8] The cast is safe.*/ \
+ ((size_t)(p) & ~MEM_ALIGN_MASK(a)) \
+ /*lint -restore*/
+
+/**
+ * @brief Aligns to the next aligned memory address.
+ *
+ * @param[in] p variable to be aligned
+ * @param[in] a alignment, must be a power of two
+ */
+#define MEM_ALIGN_NEXT(p, a) \
+ /*lint -save -e9033 [10.8] The cast is safe.*/ \
+ MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK(a), (a)) \
+ /*lint -restore*/
+
+/**
+ * @brief Returns whatever a pointer or memory size is aligned.
+ *
+ * @param[in] p variable to be aligned
+ * @param[in] a alignment, must be a power of two
+ */
+#define MEM_IS_ALIGNED(p, a) (((size_t)(p) & MEM_ALIGN_MASK(a)) == 0U)
+
+/**
+ * @brief Returns whatever a constant is a valid alignment.
+ * @details Valid alignments are powers of two.
+ *
+ * @param[in] a alignment to be checked, must be a constant
+ */
+#define MEM_IS_VALID_ALIGNMENT(a) \
+ (((size_t)(a) != 0U) && (((size_t)(a) & ((size_t)(a) - 1U)) == 0U))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CHALIGN_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chchecks.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chchecks.h
new file mode 100644
index 0000000000..6e0415904f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chchecks.h
@@ -0,0 +1,111 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chchecks.h
+ * @brief Configuration checks macros and structures.
+ *
+ * @addtogroup checks
+ * @{
+ */
+
+#ifndef CHCHECKS_H
+#define CHCHECKS_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if CH_CUSTOMER_LIC_RT == FALSE
+#error "ChibiOS/RT not licensed"
+#endif
+
+#if (CH_LICENSE_FEATURES != CH_FEATURES_FULL) && \
+ (CH_LICENSE_FEATURES != CH_FEATURES_INTERMEDIATE) && \
+ (CH_LICENSE_FEATURES != CH_FEATURES_BASIC)
+#error "invalid CH_LICENSE_FEATURES setting"
+#endif
+
+/* Restrictions in basic and intermediate modes.*/
+#if (CH_LICENSE_FEATURES == CH_FEATURES_INTERMEDIATE) || \
+ (CH_LICENSE_FEATURES == CH_FEATURES_BASIC)
+
+/* System tick limited to 1000hz.*/
+#if CH_CFG_ST_FREQUENCY > 1000
+#undef CH_CFG_ST_FREQUENCY
+#define CH_CFG_ST_FREQUENCY 1000
+#endif
+
+/* Restricted subsystems.*/
+#undef CH_DBG_STATISTICS
+#undef CH_DBG_TRACE_MASK
+
+#define CH_DBG_STATISTICS FALSE
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
+
+#endif /* (CH_LICENSE_FEATURES == CH_FEATURES_INTERMEDIATE) ||
+ (CH_LICENSE_FEATURES == CH_FEATURES_BASIC) */
+
+/* Restrictions in basic mode.*/
+#if CH_LICENSE_FEATURES == CH_FEATURES_BASIC
+
+/* Tick-Less mode restricted.*/
+#undef CH_CFG_ST_TIMEDELTA
+#define CH_CFG_ST_TIMEDELTA 0
+
+/* Restricted subsystems.*/
+#undef CH_CFG_USE_TM
+#undef CH_CFG_USE_MUTEXES
+#undef CH_CFG_USE_CONDVARS
+#undef CH_CFG_USE_DYNAMIC
+
+#define CH_CFG_USE_TM FALSE
+#define CH_CFG_USE_MUTEXES FALSE
+#define CH_CFG_USE_CONDVARS FALSE
+#define CH_CFG_USE_DYNAMIC FALSE
+
+#endif /* CH_LICENSE_FEATURES == CH_FEATURES_BASIC */
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CHCHECKS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chcond.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chcond.h
new file mode 100644
index 0000000000..9c4ebb9b7b
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chcond.h
@@ -0,0 +1,116 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+/*
+ Concepts and parts of this file have been contributed by Leon Woestenberg.
+ */
+
+/**
+ * @file chcond.h
+ * @brief Condition Variables macros and structures.
+ *
+ * @addtogroup condvars
+ * @{
+ */
+
+#ifndef CHCOND_H
+#define CHCOND_H
+
+#if (CH_CFG_USE_CONDVARS == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if CH_CFG_USE_MUTEXES == FALSE
+#error "CH_CFG_USE_CONDVARS requires CH_CFG_USE_MUTEXES"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief condition_variable_t structure.
+ */
+typedef struct condition_variable {
+ threads_queue_t queue; /**< @brief Condition variable
+ threads queue. */
+} condition_variable_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Data part of a static condition variable initializer.
+ * @details This macro should be used when statically initializing a condition
+ * variable that is part of a bigger structure.
+ *
+ * @param[in] name the name of the condition variable
+ */
+#define _CONDVAR_DATA(name) {_THREADS_QUEUE_DATA(name.queue)}
+
+/**
+ * @brief Static condition variable initializer.
+ * @details Statically initialized condition variables require no explicit
+ * initialization using @p chCondInit().
+ *
+ * @param[in] name the name of the condition variable
+ */
+#define CONDVAR_DECL(name) condition_variable_t name = _CONDVAR_DATA(name)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chCondObjectInit(condition_variable_t *cp);
+ void chCondSignal(condition_variable_t *cp);
+ void chCondSignalI(condition_variable_t *cp);
+ void chCondBroadcast(condition_variable_t *cp);
+ void chCondBroadcastI(condition_variable_t *cp);
+ msg_t chCondWait(condition_variable_t *cp);
+ msg_t chCondWaitS(condition_variable_t *cp);
+#if CH_CFG_USE_CONDVARS_TIMEOUT == TRUE
+ msg_t chCondWaitTimeout(condition_variable_t *cp, systime_t time);
+ msg_t chCondWaitTimeoutS(condition_variable_t *cp, systime_t time);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_CONDVARS == TRUE */
+
+#endif /* CHCOND_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chdebug.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chdebug.h
new file mode 100644
index 0000000000..ce8a939b0c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chdebug.h
@@ -0,0 +1,169 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chdebug.h
+ * @brief Debug support macros and structures.
+ *
+ * @addtogroup debug
+ * @{
+ */
+
+#ifndef CHDEBUG_H
+#define CHDEBUG_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Debug related settings
+ * @{
+ */
+/**
+ * @brief Fill value for thread stack area in debug mode.
+ */
+#if !defined(CH_DBG_STACK_FILL_VALUE) || defined(__DOXYGEN__)
+#define CH_DBG_STACK_FILL_VALUE 0x55
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+#if CH_DBG_SYSTEM_STATE_CHECK == TRUE
+#define _dbg_enter_lock() (ch.dbg.lock_cnt = (cnt_t)1)
+#define _dbg_leave_lock() (ch.dbg.lock_cnt = (cnt_t)0)
+#endif
+
+/* When the state checker feature is disabled then the following functions
+ are replaced by an empty macro.*/
+#if CH_DBG_SYSTEM_STATE_CHECK == FALSE
+#define _dbg_enter_lock()
+#define _dbg_leave_lock()
+#define _dbg_check_disable()
+#define _dbg_check_suspend()
+#define _dbg_check_enable()
+#define _dbg_check_lock()
+#define _dbg_check_unlock()
+#define _dbg_check_lock_from_isr()
+#define _dbg_check_unlock_from_isr()
+#define _dbg_check_enter_isr()
+#define _dbg_check_leave_isr()
+#define chDbgCheckClassI()
+#define chDbgCheckClassS()
+#endif
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Function parameters check.
+ * @details If the condition check fails then the kernel panics and halts.
+ * @note The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch
+ * is specified in @p chconf.h else the macro does nothing.
+ *
+ * @param[in] c the condition to be verified to be true
+ *
+ * @api
+ */
+#if !defined(chDbgCheck)
+#define chDbgCheck(c) do { \
+ /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
+ if (CH_DBG_ENABLE_CHECKS != FALSE) { \
+ if (!(c)) { \
+ /*lint -restore*/ \
+ chSysHalt(__func__); \
+ } \
+ } \
+} while (false)
+#endif /* !defined(chDbgCheck) */
+
+/**
+ * @brief Condition assertion.
+ * @details If the condition check fails then the kernel panics with a
+ * message and halts.
+ * @note The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch
+ * is specified in @p chconf.h else the macro does nothing.
+ * @note The remark string is not currently used except for putting a
+ * comment in the code about the assertion.
+ *
+ * @param[in] c the condition to be verified to be true
+ * @param[in] r a remark string
+ *
+ * @api
+ */
+#if !defined(chDbgAssert)
+#define chDbgAssert(c, r) do { \
+ /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
+ if (CH_DBG_ENABLE_ASSERTS != FALSE) { \
+ if (!(c)) { \
+ /*lint -restore*/ \
+ chSysHalt(__func__); \
+ } \
+ } \
+} while (false)
+#endif /* !defined(chDbgAssert) */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK == TRUE
+ void _dbg_check_disable(void);
+ void _dbg_check_suspend(void);
+ void _dbg_check_enable(void);
+ void _dbg_check_lock(void);
+ void _dbg_check_unlock(void);
+ void _dbg_check_lock_from_isr(void);
+ void _dbg_check_unlock_from_isr(void);
+ void _dbg_check_enter_isr(void);
+ void _dbg_check_leave_isr(void);
+ void chDbgCheckClassI(void);
+ void chDbgCheckClassS(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CHDEBUG_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chdynamic.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chdynamic.h
new file mode 100644
index 0000000000..2d0a7024c7
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chdynamic.h
@@ -0,0 +1,99 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chdynamic.h
+ * @brief Dynamic threads macros and structures.
+ *
+ * @addtogroup dynamic_threads
+ * @{
+ */
+
+#ifndef CHDYNAMIC_H
+#define CHDYNAMIC_H
+
+#if (CH_CFG_USE_DYNAMIC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Module dependencies check.
+ */
+#if CH_CFG_USE_WAITEXIT == FALSE
+#error "CH_CFG_USE_DYNAMIC requires CH_CFG_USE_WAITEXIT"
+#endif
+
+#if CH_CFG_USE_REGISTRY == FALSE
+#error "CH_CFG_USE_DYNAMIC requires CH_CFG_USE_REGISTRY"
+#endif
+
+#if (CH_CFG_USE_HEAP == FALSE) && (CH_CFG_USE_MEMPOOLS == FALSE)
+#error "CH_CFG_USE_DYNAMIC requires CH_CFG_USE_HEAP and/or CH_CFG_USE_MEMPOOLS"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*
+ * Dynamic threads APIs.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if CH_CFG_USE_HEAP == TRUE
+ thread_t *chThdCreateFromHeap(memory_heap_t *heapp, size_t size,
+ const char *name, tprio_t prio,
+ tfunc_t pf, void *arg);
+#endif
+#if CH_CFG_USE_MEMPOOLS == TRUE
+ thread_t *chThdCreateFromMemoryPool(memory_pool_t *mp, const char *name,
+ tprio_t prio, tfunc_t pf, void *arg);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_DYNAMIC == TRUE */
+
+#endif /* CHDYNAMIC_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chevents.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chevents.h
new file mode 100644
index 0000000000..32896351a4
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chevents.h
@@ -0,0 +1,276 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+/*
+ Concepts and parts of this file have been contributed by Scott (skute).
+ */
+
+/**
+ * @file chevents.h
+ * @brief Events macros and structures.
+ *
+ * @addtogroup events
+ * @{
+ */
+
+#ifndef CHEVENTS_H
+#define CHEVENTS_H
+
+#if (CH_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+typedef struct event_listener event_listener_t;
+
+/**
+ * @brief Event Listener structure.
+ */
+struct event_listener {
+ event_listener_t *next; /**< @brief Next Event Listener
+ registered on the event
+ source. */
+ thread_t *listener; /**< @brief Thread interested in the
+ event source. */
+ eventmask_t events; /**< @brief Events to be set in
+ the listening thread. */
+ eventflags_t flags; /**< @brief Flags added to the listener
+ by the event source. */
+ eventflags_t wflags; /**< @brief Flags that this listener
+ interested in. */
+};
+
+/**
+ * @brief Event Source structure.
+ */
+typedef struct event_source {
+ event_listener_t *next; /**< @brief First Event Listener
+ registered on the Event
+ Source. */
+} event_source_t;
+
+/**
+ * @brief Event Handler callback function.
+ */
+typedef void (*evhandler_t)(eventid_t id);
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief All events allowed mask.
+ */
+#define ALL_EVENTS ((eventmask_t)-1)
+
+/**
+ * @brief Returns an event mask from an event identifier.
+ */
+#define EVENT_MASK(eid) ((eventmask_t)1 << (eventmask_t)(eid))
+
+/**
+ * @brief Data part of a static event source initializer.
+ * @details This macro should be used when statically initializing an event
+ * source that is part of a bigger structure.
+ * @param name the name of the event source variable
+ */
+#define _EVENTSOURCE_DATA(name) {(event_listener_t *)(&name)}
+
+/**
+ * @brief Static event source initializer.
+ * @details Statically initialized event sources require no explicit
+ * initialization using @p chEvtInit().
+ *
+ * @param name the name of the event source variable
+ */
+#define EVENTSOURCE_DECL(name) event_source_t name = _EVENTSOURCE_DATA(name)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chEvtRegisterMaskWithFlags(event_source_t *esp,
+ event_listener_t *elp,
+ eventmask_t events,
+ eventflags_t wflags);
+ void chEvtUnregister(event_source_t *esp, event_listener_t *elp);
+ eventmask_t chEvtGetAndClearEvents(eventmask_t events);
+ eventmask_t chEvtAddEvents(eventmask_t events);
+ eventflags_t chEvtGetAndClearFlags(event_listener_t *elp);
+ eventflags_t chEvtGetAndClearFlagsI(event_listener_t *elp);
+ void chEvtSignal(thread_t *tp, eventmask_t events);
+ void chEvtSignalI(thread_t *tp, eventmask_t events);
+ void chEvtBroadcastFlags(event_source_t *esp, eventflags_t flags);
+ void chEvtBroadcastFlagsI(event_source_t *esp, eventflags_t flags);
+ void chEvtDispatch(const evhandler_t *handlers, eventmask_t events);
+#if (CH_CFG_OPTIMIZE_SPEED == TRUE) || (CH_CFG_USE_EVENTS_TIMEOUT == FALSE)
+ eventmask_t chEvtWaitOne(eventmask_t events);
+ eventmask_t chEvtWaitAny(eventmask_t events);
+ eventmask_t chEvtWaitAll(eventmask_t events);
+#endif
+#if CH_CFG_USE_EVENTS_TIMEOUT == TRUE
+ eventmask_t chEvtWaitOneTimeout(eventmask_t events, systime_t time);
+ eventmask_t chEvtWaitAnyTimeout(eventmask_t events, systime_t time);
+ eventmask_t chEvtWaitAllTimeout(eventmask_t events, systime_t time);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#if (CH_CFG_OPTIMIZE_SPEED == FALSE) && (CH_CFG_USE_EVENTS_TIMEOUT == TRUE)
+#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE)
+#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE)
+#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE)
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes an Event Source.
+ * @note This function can be invoked before the kernel is initialized
+ * because it just prepares a @p event_source_t structure.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ *
+ * @init
+ */
+static inline void chEvtObjectInit(event_source_t *esp) {
+
+ esp->next = (event_listener_t *)esp;
+}
+
+/**
+ * @brief Registers an Event Listener on an Event Source.
+ * @details Once a thread has registered as listener on an event source it
+ * will be notified of all events broadcasted there.
+ * @note Multiple Event Listeners can specify the same bits to be ORed to
+ * different threads.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ * @param[out] elp pointer to the @p event_listener_t structure
+ * @param[in] events the mask of events to be ORed to the thread when
+ * the event source is broadcasted
+ *
+ * @api
+ */
+static inline void chEvtRegisterMask(event_source_t *esp,
+ event_listener_t *elp,
+ eventmask_t events) {
+
+ chEvtRegisterMaskWithFlags(esp, elp, events, (eventflags_t)-1);
+}
+
+/**
+ * @brief Registers an Event Listener on an Event Source.
+ * @note Multiple Event Listeners can use the same event identifier, the
+ * listener will share the callback function.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ * @param[out] elp pointer to the @p event_listener_t structure
+ * @param[in] event numeric identifier assigned to the Event Listener.
+ * The value must range between zero and the size, in bit,
+ * of the @p eventmask_t type minus one.
+ *
+ * @api
+ */
+static inline void chEvtRegister(event_source_t *esp,
+ event_listener_t *elp,
+ eventid_t event) {
+
+ chEvtRegisterMask(esp, elp, EVENT_MASK(event));
+}
+
+/**
+ * @brief Verifies if there is at least one @p event_listener_t registered.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ * @return The event source status.
+ *
+ * @iclass
+ */
+static inline bool chEvtIsListeningI(event_source_t *esp) {
+
+ return (bool)(esp != (event_source_t *)esp->next);
+}
+
+/**
+ * @brief Signals all the Event Listeners registered on the specified Event
+ * Source.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ *
+ * @api
+ */
+static inline void chEvtBroadcast(event_source_t *esp) {
+
+ chEvtBroadcastFlags(esp, (eventflags_t)0);
+}
+
+/**
+ * @brief Signals all the Event Listeners registered on the specified Event
+ * Source.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ *
+ * @iclass
+ */
+static inline void chEvtBroadcastI(event_source_t *esp) {
+
+ chEvtBroadcastFlagsI(esp, (eventflags_t)0);
+}
+
+/**
+ * @brief Returns the events mask.
+ * @details The pending events mask is returned but not altered in any way.
+ *
+ * @return The pending events mask.
+ *
+ * @api
+ */
+static inline eventmask_t chEvtGetEventsX(void) {
+
+ return currp->epending;
+}
+
+#endif /* CH_CFG_USE_EVENTS == TRUE */
+
+#endif /* CHEVENTS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chmsg.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chmsg.h
new file mode 100644
index 0000000000..0ea848342f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chmsg.h
@@ -0,0 +1,124 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmsg.h
+ * @brief Messages macros and structures.
+ *
+ * @addtogroup messages
+ * @{
+ */
+
+#ifndef CHMSG_H
+#define CHMSG_H
+
+#if (CH_CFG_USE_MESSAGES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ msg_t chMsgSend(thread_t *tp, msg_t msg);
+ thread_t * chMsgWait(void);
+ void chMsgRelease(thread_t *tp, msg_t msg);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/**
+ * @brief Evaluates to @p true if the thread has pending messages.
+ *
+ * @param[in] tp pointer to the thread
+ * @return The pending messages status.
+ *
+ * @iclass
+ */
+static inline bool chMsgIsPendingI(thread_t *tp) {
+
+ chDbgCheckClassI();
+
+ return (bool)(tp->msgqueue.next != (thread_t *)&tp->msgqueue);
+}
+
+/**
+ * @brief Returns the message carried by the specified thread.
+ * @pre This function must be invoked immediately after exiting a call
+ * to @p chMsgWait().
+ *
+ * @param[in] tp pointer to the thread
+ * @return The message carried by the sender.
+ *
+ * @api
+ */
+static inline msg_t chMsgGet(thread_t *tp) {
+
+ chDbgAssert(tp->state == CH_STATE_SNDMSG, "invalid state");
+
+ return tp->u.sentmsg;
+}
+
+/**
+ * @brief Releases the thread waiting on top of the messages queue.
+ * @pre Invoke this function only after a message has been received
+ * using @p chMsgWait().
+ *
+ * @param[in] tp pointer to the thread
+ * @param[in] msg message to be returned to the sender
+ *
+ * @sclass
+ */
+static inline void chMsgReleaseS(thread_t *tp, msg_t msg) {
+
+ chDbgCheckClassS();
+
+ chSchWakeupS(tp, msg);
+}
+
+#endif /* CH_CFG_USE_MESSAGES == TRUE */
+
+#endif /* CHMSG_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chmtx.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chmtx.h
new file mode 100644
index 0000000000..79394c18ca
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chmtx.h
@@ -0,0 +1,153 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmtx.h
+ * @brief Mutexes macros and structures.
+ *
+ * @addtogroup mutexes
+ * @{
+ */
+
+#ifndef CHMTX_H
+#define CHMTX_H
+
+#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a mutex structure.
+ */
+typedef struct ch_mutex mutex_t;
+
+/**
+ * @brief Mutex structure.
+ */
+struct ch_mutex {
+ threads_queue_t queue; /**< @brief Queue of the threads sleeping
+ on this mutex. */
+ thread_t *owner; /**< @brief Owner @p thread_t pointer or
+ @p NULL. */
+ mutex_t *next; /**< @brief Next @p mutex_t into an
+ owner-list or @p NULL. */
+#if (CH_CFG_USE_MUTEXES_RECURSIVE == TRUE) || defined(__DOXYGEN__)
+ cnt_t cnt; /**< @brief Mutex recursion counter. */
+#endif
+};
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Data part of a static mutex initializer.
+ * @details This macro should be used when statically initializing a mutex
+ * that is part of a bigger structure.
+ *
+ * @param[in] name the name of the mutex variable
+ */
+#if (CH_CFG_USE_MUTEXES_RECURSIVE == TRUE) || defined(__DOXYGEN__)
+#define _MUTEX_DATA(name) {_THREADS_QUEUE_DATA(name.queue), NULL, NULL, 0}
+#else
+#define _MUTEX_DATA(name) {_THREADS_QUEUE_DATA(name.queue), NULL, NULL}
+#endif
+
+/**
+ * @brief Static mutex initializer.
+ * @details Statically initialized mutexes require no explicit initialization
+ * using @p chMtxInit().
+ *
+ * @param[in] name the name of the mutex variable
+ */
+#define MUTEX_DECL(name) mutex_t name = _MUTEX_DATA(name)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chMtxObjectInit(mutex_t *mp);
+ void chMtxLock(mutex_t *mp);
+ void chMtxLockS(mutex_t *mp);
+ bool chMtxTryLock(mutex_t *mp);
+ bool chMtxTryLockS(mutex_t *mp);
+ void chMtxUnlock(mutex_t *mp);
+ void chMtxUnlockS(mutex_t *mp);
+ void chMtxUnlockAll(void);
+ void chMtxUnlockAllS(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns @p true if the mutex queue contains at least a waiting
+ * thread.
+ *
+ * @param[out] mp pointer to a @p mutex_t structure
+ * @return The mutex queue status.
+ *
+ * @deprecated
+ * @sclass
+ */
+static inline bool chMtxQueueNotEmptyS(mutex_t *mp) {
+
+ chDbgCheckClassS();
+
+ return queue_notempty(&mp->queue);
+}
+
+/**
+ * @brief Returns the next mutex in the mutexes stack of the current thread.
+ *
+ * @return A pointer to the next mutex in the stack.
+ * @retval NULL if the stack is empty.
+ *
+ * @sclass
+ */
+static inline mutex_t *chMtxGetNextMutexS(void) {
+
+ return chThdGetSelfX()->mtxlist;
+}
+
+#endif /* CH_CFG_USE_MUTEXES == TRUE */
+
+#endif /* CHMTX_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chregistry.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chregistry.h
new file mode 100644
index 0000000000..48953ae8a1
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chregistry.h
@@ -0,0 +1,185 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chregistry.h
+ * @brief Threads registry macros and structures.
+ *
+ * @addtogroup registry
+ * @{
+ */
+
+#ifndef CHREGISTRY_H
+#define CHREGISTRY_H
+
+#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ChibiOS/RT memory signature record.
+ */
+typedef struct {
+ char identifier[4]; /**< @brief Always set to "main". */
+ uint8_t zero; /**< @brief Must be zero. */
+ uint8_t size; /**< @brief Size of this structure. */
+ uint16_t version; /**< @brief Encoded ChibiOS/RT version. */
+ uint8_t ptrsize; /**< @brief Size of a pointer. */
+ uint8_t timesize; /**< @brief Size of a @p systime_t. */
+ uint8_t threadsize; /**< @brief Size of a @p thread_t. */
+ uint8_t off_prio; /**< @brief Offset of @p prio field. */
+ uint8_t off_ctx; /**< @brief Offset of @p ctx field. */
+ uint8_t off_newer; /**< @brief Offset of @p newer field. */
+ uint8_t off_older; /**< @brief Offset of @p older field. */
+ uint8_t off_name; /**< @brief Offset of @p name field. */
+ uint8_t off_stklimit; /**< @brief Offset of @p stklimit field.*/
+ uint8_t off_state; /**< @brief Offset of @p state field. */
+ uint8_t off_flags; /**< @brief Offset of @p flags field. */
+ uint8_t off_refs; /**< @brief Offset of @p refs field. */
+ uint8_t off_preempt; /**< @brief Offset of @p preempt field. */
+ uint8_t off_time; /**< @brief Offset of @p time field. */
+} chdebug_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Removes a thread from the registry list.
+ * @note This macro is not meant for use in application code.
+ *
+ * @param[in] tp thread to remove from the registry
+ */
+#define REG_REMOVE(tp) { \
+ (tp)->older->newer = (tp)->newer; \
+ (tp)->newer->older = (tp)->older; \
+}
+
+/**
+ * @brief Adds a thread to the registry list.
+ * @note This macro is not meant for use in application code.
+ *
+ * @param[in] tp thread to add to the registry
+ */
+#define REG_INSERT(tp) { \
+ (tp)->newer = (thread_t *)&ch.rlist; \
+ (tp)->older = ch.rlist.older; \
+ (tp)->older->newer = (tp); \
+ ch.rlist.older = (tp); \
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ extern ROMCONST chdebug_t ch_debug;
+ thread_t *chRegFirstThread(void);
+ thread_t *chRegNextThread(thread_t *tp);
+ thread_t *chRegFindThreadByName(const char *name);
+ thread_t *chRegFindThreadByPointer(thread_t *tp);
+ thread_t *chRegFindThreadByWorkingArea(stkalign_t *wa);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CH_CFG_USE_REGISTRY == TRUE */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Sets the current thread name.
+ * @pre This function only stores the pointer to the name if the option
+ * @p CH_CFG_USE_REGISTRY is enabled else no action is performed.
+ *
+ * @param[in] name thread name as a zero terminated string
+ *
+ * @api
+ */
+static inline void chRegSetThreadName(const char *name) {
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ ch.rlist.current->name = name;
+#else
+ (void)name;
+#endif
+}
+
+/**
+ * @brief Returns the name of the specified thread.
+ * @pre This function only returns the pointer to the name if the option
+ * @p CH_CFG_USE_REGISTRY is enabled else @p NULL is returned.
+ *
+ * @param[in] tp pointer to the thread
+ *
+ * @return Thread name as a zero terminated string.
+ * @retval NULL if the thread name has not been set.
+ *
+ */
+static inline const char *chRegGetThreadNameX(thread_t *tp) {
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ return tp->name;
+#else
+ (void)tp;
+ return NULL;
+#endif
+}
+
+/**
+ * @brief Changes the name of the specified thread.
+ * @pre This function only stores the pointer to the name if the option
+ * @p CH_CFG_USE_REGISTRY is enabled else no action is performed.
+ *
+ * @param[in] tp pointer to the thread
+ * @param[in] name thread name as a zero terminated string
+ *
+ * @xclass
+ */
+static inline void chRegSetThreadNameX(thread_t *tp, const char *name) {
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ tp->name = name;
+#else
+ (void)tp;
+ (void)name;
+#endif
+}
+
+#endif /* CHREGISTRY_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chschd.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chschd.h
new file mode 100644
index 0000000000..fbd455a46c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chschd.h
@@ -0,0 +1,727 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chschd.h
+ * @brief Scheduler macros and structures.
+ *
+ * @addtogroup scheduler
+ * @{
+ */
+
+#ifndef CHSCHD_H
+#define CHSCHD_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Wakeup status codes
+ * @{
+ */
+#define MSG_OK (msg_t)0 /**< @brief Normal wakeup message. */
+#define MSG_TIMEOUT (msg_t)-1 /**< @brief Wakeup caused by a timeout
+ condition. */
+#define MSG_RESET (msg_t)-2 /**< @brief Wakeup caused by a reset
+ condition. */
+/** @} */
+
+/**
+ * @name Priority constants
+ * @{
+ */
+#define NOPRIO (tprio_t)0 /**< @brief Ready list header
+ priority. */
+#define IDLEPRIO (tprio_t)1 /**< @brief Idle priority. */
+#define LOWPRIO (tprio_t)2 /**< @brief Lowest priority. */
+#define NORMALPRIO (tprio_t)128 /**< @brief Normal priority. */
+#define HIGHPRIO (tprio_t)255 /**< @brief Highest priority. */
+/** @} */
+
+/**
+ * @name Thread states
+ * @{
+ */
+#define CH_STATE_READY (tstate_t)0 /**< @brief Waiting on the
+ ready list. */
+#define CH_STATE_CURRENT (tstate_t)1 /**< @brief Currently running. */
+#define CH_STATE_WTSTART (tstate_t)2 /**< @brief Just created. */
+#define CH_STATE_SUSPENDED (tstate_t)3 /**< @brief Suspended state. */
+#define CH_STATE_QUEUED (tstate_t)4 /**< @brief On an I/O queue. */
+#define CH_STATE_WTSEM (tstate_t)5 /**< @brief On a semaphore. */
+#define CH_STATE_WTMTX (tstate_t)6 /**< @brief On a mutex. */
+#define CH_STATE_WTCOND (tstate_t)7 /**< @brief On a cond.variable.*/
+#define CH_STATE_SLEEPING (tstate_t)8 /**< @brief Sleeping. */
+#define CH_STATE_WTEXIT (tstate_t)9 /**< @brief Waiting a thread. */
+#define CH_STATE_WTOREVT (tstate_t)10 /**< @brief One event. */
+#define CH_STATE_WTANDEVT (tstate_t)11 /**< @brief Several events. */
+#define CH_STATE_SNDMSGQ (tstate_t)12 /**< @brief Sending a message,
+ in queue. */
+#define CH_STATE_SNDMSG (tstate_t)13 /**< @brief Sent a message,
+ waiting answer. */
+#define CH_STATE_WTMSG (tstate_t)14 /**< @brief Waiting for a
+ message. */
+#define CH_STATE_FINAL (tstate_t)15 /**< @brief Thread terminated. */
+
+/**
+ * @brief Thread states as array of strings.
+ * @details Each element in an array initialized with this macro can be
+ * indexed using the numeric thread state values.
+ */
+#define CH_STATE_NAMES \
+ "READY", "CURRENT", "WTSTART", "SUSPENDED", "QUEUED", "WTSEM", "WTMTX", \
+ "WTCOND", "SLEEPING", "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", \
+ "SNDMSG", "WTMSG", "FINAL"
+/** @} */
+
+/**
+ * @name Thread flags and attributes
+ * @{
+ */
+#define CH_FLAG_MODE_MASK (tmode_t)3U /**< @brief Thread memory mode
+ mask. */
+#define CH_FLAG_MODE_STATIC (tmode_t)0U /**< @brief Static thread. */
+#define CH_FLAG_MODE_HEAP (tmode_t)1U /**< @brief Thread allocated
+ from a Memory Heap. */
+#define CH_FLAG_MODE_MPOOL (tmode_t)2U /**< @brief Thread allocated
+ from a Memory Pool. */
+#define CH_FLAG_TERMINATE (tmode_t)4U /**< @brief Termination requested
+ flag. */
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(CH_CFG_IDLE_ENTER_HOOK)
+#error "CH_CFG_IDLE_ENTER_HOOK not defined in chconf.h"
+#endif
+
+#if !defined(CH_CFG_IDLE_LEAVE_HOOK)
+#error "CH_CFG_IDLE_LEAVE_HOOK not defined in chconf.h"
+#endif
+
+#if !defined(CH_CFG_IDLE_LOOP_HOOK)
+#error "CH_CFG_IDLE_LOOP_HOOK not defined in chconf.h"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Generic threads single link list, it works like a stack.
+ */
+struct ch_threads_list {
+ thread_t *next; /**< @brief Next in the list/queue. */
+};
+
+/**
+ * @brief Generic threads bidirectional linked list header and element.
+ */
+struct ch_threads_queue {
+ thread_t *next; /**< @brief Next in the list/queue. */
+ thread_t *prev; /**< @brief Previous in the queue. */
+};
+
+/**
+ * @brief Structure representing a thread.
+ * @note Not all the listed fields are always needed, by switching off some
+ * not needed ChibiOS/RT subsystems it is possible to save RAM space
+ * by shrinking this structure.
+ */
+struct ch_thread {
+ threads_queue_t queue; /**< @brief Threads queue header. */
+ tprio_t prio; /**< @brief Thread priority. */
+ struct port_context ctx; /**< @brief Processor context. */
+#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__)
+ thread_t *newer; /**< @brief Newer registry element. */
+ thread_t *older; /**< @brief Older registry element. */
+#endif
+ /* End of the fields shared with the ReadyList structure. */
+#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Thread name or @p NULL.
+ */
+ const char *name;
+#endif
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || (CH_CFG_USE_DYNAMIC == TRUE) || \
+ defined(__DOXYGEN__)
+ /**
+ * @brief Working area base address.
+ * @note This pointer is used for stack overflow checks and for
+ * dynamic threading.
+ */
+ stkalign_t *wabase;
+#endif
+ /**
+ * @brief Current thread state.
+ */
+ tstate_t state;
+ /**
+ * @brief Various thread flags.
+ */
+ tmode_t flags;
+#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief References to this thread.
+ */
+ trefs_t refs;
+#endif
+ /**
+ * @brief Number of ticks remaining to this thread.
+ */
+#if (CH_CFG_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
+ tslices_t preempt;
+#endif
+#if (CH_DBG_THREADS_PROFILING == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Thread consumed time in ticks.
+ * @note This field can overflow.
+ */
+ volatile systime_t time;
+#endif
+ /**
+ * @brief State-specific fields.
+ * @note All the fields declared in this union are only valid in the
+ * specified state or condition and are thus volatile.
+ */
+ union {
+ /**
+ * @brief Thread wakeup code.
+ * @note This field contains the low level message sent to the thread
+ * by the waking thread or interrupt handler. The value is valid
+ * after exiting the @p chSchWakeupS() function.
+ */
+ msg_t rdymsg;
+ /**
+ * @brief Thread exit code.
+ * @note The thread termination code is stored in this field in order
+ * to be retrieved by the thread performing a @p chThdWait() on
+ * this thread.
+ */
+ msg_t exitcode;
+ /**
+ * @brief Pointer to a generic "wait" object.
+ * @note This field is used to get a generic pointer to a synchronization
+ * object and is valid when the thread is in one of the wait
+ * states.
+ */
+ void *wtobjp;
+ /**
+ * @brief Pointer to a generic thread reference object.
+ * @note This field is used to get a pointer to a synchronization
+ * object and is valid when the thread is in @p CH_STATE_SUSPENDED
+ * state.
+ */
+ thread_reference_t *wttrp;
+#if (CH_CFG_USE_MESSAGES == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Thread sent message.
+ */
+ msg_t sentmsg;
+#endif
+#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Pointer to a generic semaphore object.
+ * @note This field is used to get a pointer to a synchronization
+ * object and is valid when the thread is in @p CH_STATE_WTSEM
+ * state.
+ */
+ struct ch_semaphore *wtsemp;
+#endif
+#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Pointer to a generic mutex object.
+ * @note This field is used to get a pointer to a synchronization
+ * object and is valid when the thread is in @p CH_STATE_WTMTX
+ * state.
+ */
+ struct ch_mutex *wtmtxp;
+#endif
+#if (CH_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Enabled events mask.
+ * @note This field is only valid while the thread is in the
+ * @p CH_STATE_WTOREVT or @p CH_STATE_WTANDEVT states.
+ */
+ eventmask_t ewmask;
+#endif
+ } u;
+#if (CH_CFG_USE_WAITEXIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Termination waiting list.
+ */
+ threads_list_t waiting;
+#endif
+#if (CH_CFG_USE_MESSAGES == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Messages queue.
+ */
+ threads_queue_t msgqueue;
+#endif
+#if (CH_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Pending events mask.
+ */
+ eventmask_t epending;
+#endif
+#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief List of the mutexes owned by this thread.
+ * @note The list is terminated by a @p NULL in this field.
+ */
+ struct ch_mutex *mtxlist;
+ /**
+ * @brief Thread's own, non-inherited, priority.
+ */
+ tprio_t realprio;
+#endif
+#if ((CH_CFG_USE_DYNAMIC == TRUE) && (CH_CFG_USE_MEMPOOLS == TRUE)) || \
+ defined(__DOXYGEN__)
+ /**
+ * @brief Memory Pool where the thread workspace is returned.
+ */
+ void *mpool;
+#endif
+#if (CH_DBG_STATISTICS == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Thread statistics.
+ */
+ time_measurement_t stats;
+#endif
+#if defined(CH_CFG_THREAD_EXTRA_FIELDS)
+ /* Extra fields defined in chconf.h.*/
+ CH_CFG_THREAD_EXTRA_FIELDS
+#endif
+};
+
+/**
+ * @extends virtual_timers_list_t
+ *
+ * @brief Virtual Timer descriptor structure.
+ */
+struct ch_virtual_timer {
+ virtual_timer_t *next; /**< @brief Next timer in the list. */
+ virtual_timer_t *prev; /**< @brief Previous timer in the list. */
+ systime_t delta; /**< @brief Time delta before timeout. */
+ vtfunc_t func; /**< @brief Timer callback function
+ pointer. */
+ void *par; /**< @brief Timer callback function
+ parameter. */
+};
+
+/**
+ * @brief Virtual timers list header.
+ * @note The timers list is implemented as a double link bidirectional list
+ * in order to make the unlink time constant, the reset of a virtual
+ * timer is often used in the code.
+ */
+struct ch_virtual_timers_list {
+ virtual_timer_t *next; /**< @brief Next timer in the delta
+ list. */
+ virtual_timer_t *prev; /**< @brief Last timer in the delta
+ list. */
+ systime_t delta; /**< @brief Must be initialized to -1. */
+#if (CH_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__)
+ volatile systime_t systime; /**< @brief System Time counter. */
+#endif
+#if (CH_CFG_ST_TIMEDELTA > 0) || defined(__DOXYGEN__)
+ /**
+ * @brief System time of the last tick event.
+ */
+ systime_t lasttime; /**< @brief System time of the last
+ tick event. */
+#endif
+};
+
+/**
+ * @extends threads_queue_t
+ */
+struct ch_ready_list {
+ threads_queue_t queue; /**< @brief Threads queue. */
+ tprio_t prio; /**< @brief This field must be
+ initialized to zero. */
+ struct port_context ctx; /**< @brief Not used, present because
+ offsets. */
+#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__)
+ thread_t *newer; /**< @brief Newer registry element. */
+ thread_t *older; /**< @brief Older registry element. */
+#endif
+ /* End of the fields shared with the thread_t structure.*/
+ thread_t *current; /**< @brief The currently running
+ thread. */
+};
+
+/**
+ * @brief System debug data structure.
+ */
+struct ch_system_debug {
+ /**
+ * @brief Pointer to the panic message.
+ * @details This pointer is meant to be accessed through the debugger, it is
+ * written once and then the system is halted.
+ * @note Accesses to this pointer must never be optimized out so the
+ * field itself is declared volatile.
+ */
+ const char * volatile panic_msg;
+#if (CH_DBG_SYSTEM_STATE_CHECK == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief ISR nesting level.
+ */
+ cnt_t isr_cnt;
+ /**
+ * @brief Lock nesting level.
+ */
+ cnt_t lock_cnt;
+#endif
+#if (CH_DBG_TRACE_MASK != CH_DBG_TRACE_MASK_DISABLED) || defined(__DOXYGEN__)
+ /**
+ * @brief Public trace buffer.
+ */
+ ch_trace_buffer_t trace_buffer;
+#endif
+};
+
+/**
+ * @brief System data structure.
+ * @note This structure contain all the data areas used by the OS except
+ * stacks.
+ */
+struct ch_system {
+ /**
+ * @brief Ready list header.
+ */
+ ready_list_t rlist;
+ /**
+ * @brief Virtual timers delta list header.
+ */
+ virtual_timers_list_t vtlist;
+ /**
+ * @brief System debug.
+ */
+ system_debug_t dbg;
+ /**
+ * @brief Main thread descriptor.
+ */
+ thread_t mainthread;
+#if (CH_CFG_USE_TM == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Time measurement calibration data.
+ */
+ tm_calibration_t tm;
+#endif
+#if (CH_DBG_STATISTICS == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Global kernel statistics.
+ */
+ kernel_stats_t kernel_stats;
+#endif
+};
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the priority of the first thread on the given ready list.
+ *
+ * @notapi
+ */
+#define firstprio(rlp) ((rlp)->next->prio)
+
+/**
+ * @brief Current thread pointer access macro.
+ * @note This macro is not meant to be used in the application code but
+ * only from within the kernel, use @p chThdGetSelfX() instead.
+ */
+#define currp ch.rlist.current
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern ch_system_t ch;
+#endif
+
+/*
+ * Scheduler APIs.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _scheduler_init(void);
+ thread_t *chSchReadyI(thread_t *tp);
+ thread_t *chSchReadyAheadI(thread_t *tp);
+ void chSchGoSleepS(tstate_t newstate);
+ msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time);
+ void chSchWakeupS(thread_t *ntp, msg_t msg);
+ void chSchRescheduleS(void);
+ bool chSchIsPreemptionRequired(void);
+ void chSchDoRescheduleBehind(void);
+ void chSchDoRescheduleAhead(void);
+ void chSchDoReschedule(void);
+#if CH_CFG_OPTIMIZE_SPEED == FALSE
+ void queue_prio_insert(thread_t *tp, threads_queue_t *tqp);
+ void queue_insert(thread_t *tp, threads_queue_t *tqp);
+ thread_t *queue_fifo_remove(threads_queue_t *tqp);
+ thread_t *queue_lifo_remove(threads_queue_t *tqp);
+ thread_t *queue_dequeue(thread_t *tp);
+ void list_insert(thread_t *tp, threads_list_t *tlp);
+ thread_t *list_remove(threads_list_t *tlp);
+#endif /* CH_CFG_OPTIMIZE_SPEED == FALSE */
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Threads list initialization.
+ *
+ * @param[in] tlp pointer to the threads list object
+ *
+ * @notapi
+ */
+static inline void list_init(threads_list_t *tlp) {
+
+ tlp->next = (thread_t *)tlp;
+}
+
+/**
+ * @brief Evaluates to @p true if the specified threads list is empty.
+ *
+ * @param[in] tlp pointer to the threads list object
+ * @return The status of the list.
+ *
+ * @notapi
+ */
+static inline bool list_isempty(threads_list_t *tlp) {
+
+ return (bool)(tlp->next == (thread_t *)tlp);
+}
+
+/**
+ * @brief Evaluates to @p true if the specified threads list is not empty.
+ *
+ * @param[in] tlp pointer to the threads list object
+ * @return The status of the list.
+ *
+ * @notapi
+ */
+static inline bool list_notempty(threads_list_t *tlp) {
+
+ return (bool)(tlp->next != (thread_t *)tlp);
+}
+
+/**
+ * @brief Threads queue initialization.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ *
+ * @notapi
+ */
+static inline void queue_init(threads_queue_t *tqp) {
+
+ tqp->next = (thread_t *)tqp;
+ tqp->prev = (thread_t *)tqp;
+}
+
+/**
+ * @brief Evaluates to @p true if the specified threads queue is empty.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @return The status of the queue.
+ *
+ * @notapi
+ */
+static inline bool queue_isempty(const threads_queue_t *tqp) {
+
+ return (bool)(tqp->next == (const thread_t *)tqp);
+}
+
+/**
+ * @brief Evaluates to @p true if the specified threads queue is not empty.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @return The status of the queue.
+ *
+ * @notapi
+ */
+static inline bool queue_notempty(const threads_queue_t *tqp) {
+
+ return (bool)(tqp->next != (const thread_t *)tqp);
+}
+
+/* If the performance code path has been chosen then all the following
+ functions are inlined into the various kernel modules.*/
+#if CH_CFG_OPTIMIZE_SPEED == TRUE
+static inline void list_insert(thread_t *tp, threads_list_t *tlp) {
+
+ tp->queue.next = tlp->next;
+ tlp->next = tp;
+}
+
+static inline thread_t *list_remove(threads_list_t *tlp) {
+
+ thread_t *tp = tlp->next;
+ tlp->next = tp->queue.next;
+
+ return tp;
+}
+
+static inline void queue_prio_insert(thread_t *tp, threads_queue_t *tqp) {
+
+ thread_t *cp = (thread_t *)tqp;
+ do {
+ cp = cp->queue.next;
+ } while ((cp != (thread_t *)tqp) && (cp->prio >= tp->prio));
+ tp->queue.next = cp;
+ tp->queue.prev = cp->queue.prev;
+ tp->queue.prev->queue.next = tp;
+ cp->queue.prev = tp;
+}
+
+static inline void queue_insert(thread_t *tp, threads_queue_t *tqp) {
+
+ tp->queue.next = (thread_t *)tqp;
+ tp->queue.prev = tqp->prev;
+ tp->queue.prev->queue.next = tp;
+ tqp->prev = tp;
+}
+
+static inline thread_t *queue_fifo_remove(threads_queue_t *tqp) {
+ thread_t *tp = tqp->next;
+
+ tqp->next = tp->queue.next;
+ tqp->next->queue.prev = (thread_t *)tqp;
+
+ return tp;
+}
+
+static inline thread_t *queue_lifo_remove(threads_queue_t *tqp) {
+ thread_t *tp = tqp->prev;
+
+ tqp->prev = tp->queue.prev;
+ tqp->prev->queue.next = (thread_t *)tqp;
+
+ return tp;
+}
+
+static inline thread_t *queue_dequeue(thread_t *tp) {
+
+ tp->queue.prev->queue.next = tp->queue.next;
+ tp->queue.next->queue.prev = tp->queue.prev;
+
+ return tp;
+}
+#endif /* CH_CFG_OPTIMIZE_SPEED == TRUE */
+
+/**
+ * @brief Determines if the current thread must reschedule.
+ * @details This function returns @p true if there is a ready thread with
+ * higher priority.
+ *
+ * @return The priorities situation.
+ * @retval false if rescheduling is not necessary.
+ * @retval true if there is a ready thread at higher priority.
+ *
+ * @iclass
+ */
+static inline bool chSchIsRescRequiredI(void) {
+
+ chDbgCheckClassI();
+
+ return firstprio(&ch.rlist.queue) > currp->prio;
+}
+
+/**
+ * @brief Determines if yielding is possible.
+ * @details This function returns @p true if there is a ready thread with
+ * equal or higher priority.
+ *
+ * @return The priorities situation.
+ * @retval false if yielding is not possible.
+ * @retval true if there is a ready thread at equal or higher priority.
+ *
+ * @sclass
+ */
+static inline bool chSchCanYieldS(void) {
+
+ chDbgCheckClassS();
+
+ return firstprio(&ch.rlist.queue) >= currp->prio;
+}
+
+/**
+ * @brief Yields the time slot.
+ * @details Yields the CPU control to the next thread in the ready list with
+ * equal or higher priority, if any.
+ *
+ * @sclass
+ */
+static inline void chSchDoYieldS(void) {
+
+ chDbgCheckClassS();
+
+ if (chSchCanYieldS()) {
+ chSchDoRescheduleBehind();
+ }
+}
+
+/**
+ * @brief Inline-able preemption code.
+ * @details This is the common preemption code, this function must be invoked
+ * exclusively from the port layer.
+ *
+ * @special
+ */
+static inline void chSchPreemption(void) {
+ tprio_t p1 = firstprio(&ch.rlist.queue);
+ tprio_t p2 = currp->prio;
+
+#if CH_CFG_TIME_QUANTUM > 0
+ if (currp->preempt > (tslices_t)0) {
+ if (p1 > p2) {
+ chSchDoRescheduleAhead();
+ }
+ }
+ else {
+ if (p1 >= p2) {
+ chSchDoRescheduleBehind();
+ }
+ }
+#else /* CH_CFG_TIME_QUANTUM == 0 */
+ if (p1 > p2) {
+ chSchDoRescheduleAhead();
+ }
+#endif /* CH_CFG_TIME_QUANTUM == 0 */
+}
+
+#endif /* CHSCHD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsem.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsem.h
new file mode 100644
index 0000000000..eb4b762a5e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsem.h
@@ -0,0 +1,160 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chsem.h
+ * @brief Semaphores macros and structures.
+ *
+ * @addtogroup semaphores
+ * @{
+ */
+
+#ifndef CHSEM_H
+#define CHSEM_H
+
+#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Semaphore structure.
+ */
+typedef struct ch_semaphore {
+ threads_queue_t queue; /**< @brief Queue of the threads sleeping
+ on this semaphore. */
+ cnt_t cnt; /**< @brief The semaphore counter. */
+} semaphore_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Data part of a static semaphore initializer.
+ * @details This macro should be used when statically initializing a semaphore
+ * that is part of a bigger structure.
+ *
+ * @param[in] name the name of the semaphore variable
+ * @param[in] n the counter initial value, this value must be
+ * non-negative
+ */
+#define _SEMAPHORE_DATA(name, n) {_THREADS_QUEUE_DATA(name.queue), n}
+
+/**
+ * @brief Static semaphore initializer.
+ * @details Statically initialized semaphores require no explicit
+ * initialization using @p chSemInit().
+ *
+ * @param[in] name the name of the semaphore variable
+ * @param[in] n the counter initial value, this value must be
+ * non-negative
+ */
+#define SEMAPHORE_DECL(name, n) semaphore_t name = _SEMAPHORE_DATA(name, n)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chSemObjectInit(semaphore_t *sp, cnt_t n);
+ void chSemReset(semaphore_t *sp, cnt_t n);
+ void chSemResetI(semaphore_t *sp, cnt_t n);
+ msg_t chSemWait(semaphore_t *sp);
+ msg_t chSemWaitS(semaphore_t *sp);
+ msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time);
+ msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time);
+ void chSemSignal(semaphore_t *sp);
+ void chSemSignalI(semaphore_t *sp);
+ void chSemAddCounterI(semaphore_t *sp, cnt_t n);
+ msg_t chSemSignalWait(semaphore_t *sps, semaphore_t *spw);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Decreases the semaphore counter.
+ * @details This macro can be used when the counter is known to be positive.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ *
+ * @iclass
+ */
+static inline void chSemFastWaitI(semaphore_t *sp) {
+
+ chDbgCheckClassI();
+
+ sp->cnt--;
+}
+
+/**
+ * @brief Increases the semaphore counter.
+ * @details This macro can be used when the counter is known to be not
+ * negative.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ *
+ * @iclass
+ */
+static inline void chSemFastSignalI(semaphore_t *sp) {
+
+ chDbgCheckClassI();
+
+ sp->cnt++;
+}
+
+/**
+ * @brief Returns the semaphore counter current value.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ * @return The semaphore counter value.
+ *
+ * @iclass
+ */
+static inline cnt_t chSemGetCounterI(semaphore_t *sp) {
+
+ chDbgCheckClassI();
+
+ return sp->cnt;
+}
+
+#endif /* CH_CFG_USE_SEMAPHORES == TRUE */
+
+#endif /* CHSEM_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chstats.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chstats.h
new file mode 100644
index 0000000000..3332c06fe9
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chstats.h
@@ -0,0 +1,105 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chstats.h
+ * @brief Statistics module macros and structures.
+ *
+ * @addtogroup statistics
+ * @{
+ */
+
+#ifndef CHSTATS_H
+#define CHSTATS_H
+
+#if (CH_DBG_STATISTICS == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+#if CH_CFG_USE_TM == FALSE
+#error "CH_DBG_STATISTICS requires CH_CFG_USE_TM"
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a kernel statistics structure.
+ */
+typedef struct {
+ ucnt_t n_irq; /**< @brief Number of IRQs. */
+ ucnt_t n_ctxswc; /**< @brief Number of context switches. */
+ time_measurement_t m_crit_thd; /**< @brief Measurement of threads
+ critical zones duration. */
+ time_measurement_t m_crit_isr; /**< @brief Measurement of ISRs critical
+ zones duration. */
+} kernel_stats_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _stats_init(void);
+ void _stats_increase_irq(void);
+ void _stats_ctxswc(thread_t *ntp, thread_t *otp);
+ void _stats_start_measure_crit_thd(void);
+ void _stats_stop_measure_crit_thd(void);
+ void _stats_start_measure_crit_isr(void);
+ void _stats_stop_measure_crit_isr(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#else /* CH_DBG_STATISTICS == FALSE */
+
+/* Stub functions for when the statistics module is disabled. */
+#define _stats_increase_irq()
+#define _stats_ctxswc(old, new)
+#define _stats_start_measure_crit_thd()
+#define _stats_stop_measure_crit_thd()
+#define _stats_start_measure_crit_isr()
+#define _stats_stop_measure_crit_isr()
+
+#endif /* CH_DBG_STATISTICS == FALSE */
+
+#endif /* CHSTATS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsys.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsys.h
new file mode 100644
index 0000000000..213d9b3461
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsys.h
@@ -0,0 +1,490 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chsys.h
+ * @brief System related macros and structures.
+ *
+ * @addtogroup system
+ * @{
+ */
+
+#ifndef CHSYS_H
+#define CHSYS_H
+
+/*lint -sem(chSysHalt, r_no)*/
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Masks of executable integrity checks.
+ * @{
+ */
+#define CH_INTEGRITY_RLIST 1U
+#define CH_INTEGRITY_VTLIST 2U
+#define CH_INTEGRITY_REGISTRY 4U
+#define CH_INTEGRITY_PORT 8U
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(CH_CFG_IRQ_PROLOGUE_HOOK)
+#error "CH_CFG_IRQ_PROLOGUE_HOOK not defined in chconf.h"
+#endif
+
+#if !defined(CH_CFG_IRQ_EPILOGUE_HOOK)
+#error "CH_CFG_IRQ_EPILOGUE_HOOK not defined in chconf.h"
+#endif
+
+#if !defined(CH_CFG_CONTEXT_SWITCH_HOOK)
+#error "CH_CFG_CONTEXT_SWITCH_HOOK not defined in chconf.h"
+#endif
+
+#if !defined(CH_CFG_SYSTEM_TICK_HOOK)
+#error "CH_CFG_SYSTEM_TICK_HOOK not defined in chconf.h"
+#endif
+
+#if !defined(CH_CFG_SYSTEM_HALT_HOOK)
+#error "CH_CFG_SYSTEM_HALT_HOOK not defined in chconf.h"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name ISRs abstraction macros
+ */
+/**
+ * @brief Priority level validation macro.
+ * @details This macro determines if the passed value is a valid priority
+ * level for the underlying architecture.
+ *
+ * @param[in] prio the priority level
+ * @return Priority range result.
+ * @retval false if the priority is invalid or if the architecture
+ * does not support priorities.
+ * @retval true if the priority is valid.
+ */
+#if defined(PORT_IRQ_IS_VALID_PRIORITY) || defined(__DOXYGEN__)
+#define CH_IRQ_IS_VALID_PRIORITY(prio) \
+ PORT_IRQ_IS_VALID_PRIORITY(prio)
+#else
+#define CH_IRQ_IS_VALID_PRIORITY(prio) false
+#endif
+
+/**
+ * @brief Priority level validation macro.
+ * @details This macro determines if the passed value is a valid priority
+ * level that cannot preempt the kernel critical zone.
+ *
+ * @param[in] prio the priority level
+ * @return Priority range result.
+ * @retval false if the priority is invalid or if the architecture
+ * does not support priorities.
+ * @retval true if the priority is valid.
+ */
+#if defined(PORT_IRQ_IS_VALID_KERNEL_PRIORITY) || defined(__DOXYGEN__)
+#define CH_IRQ_IS_VALID_KERNEL_PRIORITY(prio) \
+ PORT_IRQ_IS_VALID_KERNEL_PRIORITY(prio)
+#else
+#define CH_IRQ_IS_VALID_KERNEL_PRIORITY(prio) false
+#endif
+
+/**
+ * @brief IRQ handler enter code.
+ * @note Usually IRQ handlers functions are also declared naked.
+ * @note On some architectures this macro can be empty.
+ *
+ * @special
+ */
+#define CH_IRQ_PROLOGUE() \
+ PORT_IRQ_PROLOGUE(); \
+ CH_CFG_IRQ_PROLOGUE_HOOK(); \
+ _stats_increase_irq(); \
+ _trace_isr_enter(__func__); \
+ _dbg_check_enter_isr()
+
+/**
+ * @brief IRQ handler exit code.
+ * @note Usually IRQ handlers function are also declared naked.
+ * @note This macro usually performs the final reschedule by using
+ * @p chSchIsPreemptionRequired() and @p chSchDoReschedule().
+ *
+ * @special
+ */
+#define CH_IRQ_EPILOGUE() \
+ _dbg_check_leave_isr(); \
+ _trace_isr_leave(__func__); \
+ CH_CFG_IRQ_EPILOGUE_HOOK(); \
+ PORT_IRQ_EPILOGUE()
+
+/**
+ * @brief Standard normal IRQ handler declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ *
+ * @special
+ */
+#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name Fast ISRs abstraction macros
+ */
+/**
+ * @brief Standard fast IRQ handler declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ * @note Not all architectures support fast interrupts.
+ *
+ * @special
+ */
+#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name Time conversion utilities for the realtime counter
+ * @{
+ */
+/**
+ * @brief Seconds to realtime counter.
+ * @details Converts from seconds to realtime counter cycles.
+ * @note The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] sec number of seconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define S2RTC(freq, sec) ((freq) * (sec))
+
+/**
+ * @brief Milliseconds to realtime counter.
+ * @details Converts from milliseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next millisecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] msec number of milliseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec))
+
+/**
+ * @brief Microseconds to realtime counter.
+ * @details Converts from microseconds to realtime counter cycles.
+ * @note The result is rounded upward to the next microsecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] usec number of microseconds
+ * @return The number of cycles.
+ *
+ * @api
+ */
+#define US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec))
+
+/**
+ * @brief Realtime counter cycles to seconds.
+ * @details Converts from realtime counter cycles number to seconds.
+ * @note The result is rounded up to the next second boundary.
+ * @note The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] n number of cycles
+ * @return The number of seconds.
+ *
+ * @api
+ */
+#define RTC2S(freq, n) ((((n) - 1UL) / (freq)) + 1UL)
+
+/**
+ * @brief Realtime counter cycles to milliseconds.
+ * @details Converts from realtime counter cycles number to milliseconds.
+ * @note The result is rounded up to the next millisecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] n number of cycles
+ * @return The number of milliseconds.
+ *
+ * @api
+ */
+#define RTC2MS(freq, n) ((((n) - 1UL) / ((freq) / 1000UL)) + 1UL)
+
+/**
+ * @brief Realtime counter cycles to microseconds.
+ * @details Converts from realtime counter cycles number to microseconds.
+ * @note The result is rounded up to the next microsecond boundary.
+ * @note The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq clock frequency, in Hz, of the realtime counter
+ * @param[in] n number of cycles
+ * @return The number of microseconds.
+ *
+ * @api
+ */
+#define RTC2US(freq, n) ((((n) - 1UL) / ((freq) / 1000000UL)) + 1UL)
+/** @} */
+
+/**
+ * @brief Returns the current value of the system real time counter.
+ * @note This function is only available if the port layer supports the
+ * option @p PORT_SUPPORTS_RT.
+ *
+ * @return The value of the system realtime counter of
+ * type rtcnt_t.
+ *
+ * @xclass
+ */
+#if (PORT_SUPPORTS_RT == TRUE) || defined(__DOXYGEN__)
+#define chSysGetRealtimeCounterX() (rtcnt_t)port_rt_get_counter_value()
+#endif
+
+/**
+ * @brief Performs a context switch.
+ * @note Not a user function, it is meant to be invoked by the scheduler
+ * itself or from within the port layer.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ *
+ * @special
+ */
+#define chSysSwitch(ntp, otp) { \
+ \
+ _trace_switch(ntp, otp); \
+ _stats_ctxswc(ntp, otp); \
+ CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp); \
+ port_switch(ntp, otp); \
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern stkalign_t ch_idle_thread_wa[];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chSysInit(void);
+ void chSysHalt(const char *reason);
+ bool chSysIntegrityCheckI(unsigned testmask);
+ void chSysTimerHandlerI(void);
+ syssts_t chSysGetStatusAndLockX(void);
+ void chSysRestoreStatusX(syssts_t sts);
+#if PORT_SUPPORTS_RT == TRUE
+ bool chSysIsCounterWithinX(rtcnt_t cnt, rtcnt_t start, rtcnt_t end);
+ void chSysPolledDelayX(rtcnt_t cycles);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Raises the system interrupt priority mask to the maximum level.
+ * @details All the maskable interrupt sources are disabled regardless their
+ * hardware priority.
+ * @note Do not invoke this API from within a kernel lock.
+ *
+ * @special
+ */
+static inline void chSysDisable(void) {
+
+ port_disable();
+ _dbg_check_disable();
+}
+
+/**
+ * @brief Raises the system interrupt priority mask to system level.
+ * @details The interrupt sources that should not be able to preempt the kernel
+ * are disabled, interrupt sources with higher priority are still
+ * enabled.
+ * @note Do not invoke this API from within a kernel lock.
+ * @note This API is no replacement for @p chSysLock(), the @p chSysLock()
+ * could do more than just disable the interrupts.
+ *
+ * @special
+ */
+static inline void chSysSuspend(void) {
+
+ port_suspend();
+ _dbg_check_suspend();
+}
+
+/**
+ * @brief Lowers the system interrupt priority mask to user level.
+ * @details All the interrupt sources are enabled.
+ * @note Do not invoke this API from within a kernel lock.
+ * @note This API is no replacement for @p chSysUnlock(), the
+ * @p chSysUnlock() could do more than just enable the interrupts.
+ *
+ * @special
+ */
+static inline void chSysEnable(void) {
+
+ _dbg_check_enable();
+ port_enable();
+}
+
+/**
+ * @brief Enters the kernel lock state.
+ *
+ * @special
+ */
+static inline void chSysLock(void) {
+
+ port_lock();
+ _stats_start_measure_crit_thd();
+ _dbg_check_lock();
+}
+
+/**
+ * @brief Leaves the kernel lock state.
+ *
+ * @special
+ */
+static inline void chSysUnlock(void) {
+
+ _dbg_check_unlock();
+ _stats_stop_measure_crit_thd();
+
+ /* The following condition can be triggered by the use of i-class functions
+ in a critical section not followed by a chSchResceduleS(), this means
+ that the current thread has a lower priority than the next thread in
+ the ready list.*/
+ chDbgAssert((ch.rlist.queue.next == (thread_t *)&ch.rlist.queue) ||
+ (ch.rlist.current->prio >= ch.rlist.queue.next->prio),
+ "priority order violation");
+
+ port_unlock();
+}
+
+/**
+ * @brief Enters the kernel lock state from within an interrupt handler.
+ * @note This API may do nothing on some architectures, it is required
+ * because on ports that support preemptable interrupt handlers
+ * it is required to raise the interrupt mask to the same level of
+ * the system mutual exclusion zone.
+ * It is good practice to invoke this API before invoking any I-class
+ * syscall from an interrupt handler.
+ * @note This API must be invoked exclusively from interrupt handlers.
+ *
+ * @special
+ */
+static inline void chSysLockFromISR(void) {
+
+ port_lock_from_isr();
+ _stats_start_measure_crit_isr();
+ _dbg_check_lock_from_isr();
+}
+
+/**
+ * @brief Leaves the kernel lock state from within an interrupt handler.
+ *
+ * @note This API may do nothing on some architectures, it is required
+ * because on ports that support preemptable interrupt handlers
+ * it is required to raise the interrupt mask to the same level of
+ * the system mutual exclusion zone.
+ * It is good practice to invoke this API after invoking any I-class
+ * syscall from an interrupt handler.
+ * @note This API must be invoked exclusively from interrupt handlers.
+ *
+ * @special
+ */
+static inline void chSysUnlockFromISR(void) {
+
+ _dbg_check_unlock_from_isr();
+ _stats_stop_measure_crit_isr();
+ port_unlock_from_isr();
+}
+
+/**
+ * @brief Unconditionally enters the kernel lock state.
+ * @note Can be called without previous knowledge of the current lock state.
+ * The final state is "s-locked".
+ *
+ * @special
+ */
+static inline void chSysUnconditionalLock(void) {
+
+ if (port_irq_enabled(port_get_irq_status())) {
+ chSysLock();
+ }
+}
+
+/**
+ * @brief Unconditionally leaves the kernel lock state.
+ * @note Can be called without previous knowledge of the current lock state.
+ * The final state is "normal".
+ *
+ * @special
+ */
+static inline void chSysUnconditionalUnlock(void) {
+
+ if (!port_irq_enabled(port_get_irq_status())) {
+ chSysUnlock();
+ }
+}
+
+#if (CH_CFG_NO_IDLE_THREAD == FALSE) || defined(__DOXYGEN__)
+/**
+ * @brief Returns a pointer to the idle thread.
+ * @pre In order to use this function the option @p CH_CFG_NO_IDLE_THREAD
+ * must be disabled.
+ * @note The reference counter of the idle thread is not incremented but
+ * it is not strictly required being the idle thread a static
+ * object.
+ *
+ * @return Pointer to the idle thread.
+ *
+ * @xclass
+ */
+static inline thread_t *chSysGetIdleThreadX(void) {
+
+ return ch.rlist.queue.prev;
+}
+#endif /* CH_CFG_NO_IDLE_THREAD == FALSE */
+
+#endif /* CHSYS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsystypes.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsystypes.h
new file mode 100644
index 0000000000..a74e5c8b46
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chsystypes.h
@@ -0,0 +1,141 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chsystypes.h
+ * @brief System types header.
+ *
+ * @addtogroup scheduler
+ * @{
+ */
+
+#ifndef CHSYSTYPES_H
+#define CHSYSTYPES_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of system time.
+ */
+#if (CH_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#elif CH_CFG_ST_RESOLUTION == 16
+typedef uint16_t systime_t;
+#else
+#error "invalid CH_CFG_ST_RESOLUTION setting"
+#endif
+
+/**
+ * @extends threads_queue_t
+ *
+ * @brief Type of a thread structure.
+ */
+typedef struct ch_thread thread_t;
+
+/**
+ * @brief Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+
+/**
+ * @brief Type of a generic threads single link list, it works like a stack.
+ */
+typedef struct ch_threads_list threads_list_t;
+
+/**
+ * @extends threads_list_t
+ *
+ * @brief Type of a generic threads bidirectional linked list header and element.
+ */
+typedef struct ch_threads_queue threads_queue_t;
+
+/**
+ * @extends threads_queue_t
+ *
+ * @brief Type of a ready list header.
+ */
+typedef struct ch_ready_list ready_list_t;
+
+/**
+ * @brief Type of a Virtual Timer callback function.
+ */
+typedef void (*vtfunc_t)(void *p);
+
+/**
+ * @brief Type of a Virtual Timer structure.
+ */
+typedef struct ch_virtual_timer virtual_timer_t;
+
+/**
+ * @brief Type of virtual timers list header.
+ */
+typedef struct ch_virtual_timers_list virtual_timers_list_t;
+
+/**
+ * @brief Type of a system debug structure.
+ */
+typedef struct ch_system_debug system_debug_t;
+
+/**
+ * @brief Type of system data structure.
+ */
+typedef struct ch_system ch_system_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Utility to make the parameter a quoted string.
+ */
+#define __CH_STRINGIFY(a) #a
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CHSYSTYPES_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chthreads.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chthreads.h
new file mode 100644
index 0000000000..4487cdf264
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chthreads.h
@@ -0,0 +1,452 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chthreads.h
+ * @brief Threads module macros and structures.
+ *
+ * @addtogroup threads
+ * @{
+ */
+
+#ifndef CHTHREADS_H
+#define CHTHREADS_H
+
+/*lint -sem(chThdExit, r_no) -sem(chThdExitS, r_no)*/
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+#if !defined(CH_CFG_THREAD_EXTRA_FIELDS)
+#error "CH_CFG_THREAD_EXTRA_FIELDS not defined in chconf.h"
+#endif
+
+#if !defined(CH_CFG_THREAD_INIT_HOOK)
+#error "CH_CFG_THREAD_INIT_HOOK not defined in chconf.h"
+#endif
+
+#if !defined(CH_CFG_THREAD_EXIT_HOOK)
+#error "CH_CFG_THREAD_EXIT_HOOK not defined in chconf.h"
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Thread function.
+ */
+typedef void (*tfunc_t)(void *p);
+
+/**
+ * @brief Type of a thread descriptor.
+ */
+typedef struct {
+ /**
+ * @brief Thread name.
+ */
+ const char *name;
+ /**
+ * @brief Pointer to the working area base.
+ */
+ stkalign_t *wbase;
+ /**
+ * @brief End of the working area.
+ */
+ stkalign_t *wend;
+ /**
+ * @brief Thread priority.
+ */
+ tprio_t prio;
+ /**
+ * @brief Thread function pointer.
+ */
+ tfunc_t funcp;
+ /**
+ * @brief Thread argument.
+ */
+ void *arg;
+} thread_descriptor_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name Threads queues
+ */
+/**
+ * @brief Data part of a static threads queue object initializer.
+ * @details This macro should be used when statically initializing a threads
+ * queue that is part of a bigger structure.
+ *
+ * @param[in] name the name of the threads queue variable
+ */
+#define _THREADS_QUEUE_DATA(name) {(thread_t *)&name, (thread_t *)&name}
+
+/**
+ * @brief Static threads queue object initializer.
+ * @details Statically initialized threads queues require no explicit
+ * initialization using @p queue_init().
+ *
+ * @param[in] name the name of the threads queue variable
+ */
+#define _THREADS_QUEUE_DECL(name) \
+ threads_queue_t name = _THREADS_QUEUE_DATA(name)
+/** @} */
+
+/**
+ * @name Working Areas
+ */
+/**
+ * @brief Calculates the total Working Area size.
+ *
+ * @param[in] n the stack size to be assigned to the thread
+ * @return The total used memory in bytes.
+ *
+ * @api
+ */
+#define THD_WORKING_AREA_SIZE(n) \
+ MEM_ALIGN_NEXT(sizeof(thread_t) + PORT_WA_SIZE(n), PORT_STACK_ALIGN)
+
+/**
+ * @brief Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ * aligned as both position and size.
+ *
+ * @param[in] s the name to be assigned to the stack array
+ * @param[in] n the stack size to be assigned to the thread
+ *
+ * @api
+ */
+#define THD_WORKING_AREA(s, n) PORT_WORKING_AREA(s, n)
+
+/**
+ * @brief Base of a working area casted to the correct type.
+ *
+ * @param[in] s name of the working area
+ */
+#define THD_WORKING_AREA_BASE(s) ((stkalign_t *)(s))
+
+/**
+ * @brief End of a working area casted to the correct type.
+ *
+ * @param[in] s name of the working area
+ */
+#define THD_WORKING_AREA_END(s) (THD_WORKING_AREA_BASE(s) + \
+ (sizeof (s) / sizeof (stkalign_t)))
+/** @} */
+
+/**
+ * @name Threads abstraction macros
+ */
+/**
+ * @brief Thread declaration macro.
+ * @note Thread declarations should be performed using this macro because
+ * the port layer could define optimizations for thread functions.
+ */
+#define THD_FUNCTION(tname, arg) PORT_THD_FUNCTION(tname, arg)
+/** @} */
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Delays the invoking thread for the specified number of seconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] sec time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * milliseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] msec time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * microseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system tick clock.
+ * @note The maximum specifiable value is implementation dependent.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] usec time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ thread_t *_thread_init(thread_t *tp, const char *name, tprio_t prio);
+#if CH_DBG_FILL_THREADS == TRUE
+ void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v);
+#endif
+ thread_t *chThdCreateSuspendedI(const thread_descriptor_t *tdp);
+ thread_t *chThdCreateSuspended(const thread_descriptor_t *tdp);
+ thread_t *chThdCreateI(const thread_descriptor_t *tdp);
+ thread_t *chThdCreate(const thread_descriptor_t *tdp);
+ thread_t *chThdCreateStatic(void *wsp, size_t size,
+ tprio_t prio, tfunc_t pf, void *arg);
+ thread_t *chThdStart(thread_t *tp);
+#if CH_CFG_USE_REGISTRY == TRUE
+ thread_t *chThdAddRef(thread_t *tp);
+ void chThdRelease(thread_t *tp);
+#endif
+ void chThdExit(msg_t msg);
+ void chThdExitS(msg_t msg);
+#if CH_CFG_USE_WAITEXIT == TRUE
+ msg_t chThdWait(thread_t *tp);
+#endif
+ tprio_t chThdSetPriority(tprio_t newprio);
+ void chThdTerminate(thread_t *tp);
+ msg_t chThdSuspendS(thread_reference_t *trp);
+ msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
+ void chThdResumeI(thread_reference_t *trp, msg_t msg);
+ void chThdResumeS(thread_reference_t *trp, msg_t msg);
+ void chThdResume(thread_reference_t *trp, msg_t msg);
+ msg_t chThdEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout);
+ void chThdDequeueNextI(threads_queue_t *tqp, msg_t msg);
+ void chThdDequeueAllI(threads_queue_t *tqp, msg_t msg);
+ void chThdSleep(systime_t time);
+ void chThdSleepUntil(systime_t time);
+ systime_t chThdSleepUntilWindowed(systime_t prev, systime_t next);
+ void chThdYield(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+ /**
+ * @brief Returns a pointer to the current @p thread_t.
+ *
+ * @return A pointer to the current thread.
+ *
+ * @xclass
+ */
+static inline thread_t *chThdGetSelfX(void) {
+
+ return ch.rlist.current;
+}
+
+/**
+ * @brief Returns the current thread priority.
+ * @note Can be invoked in any context.
+ *
+ * @return The current thread priority.
+ *
+ * @xclass
+ */
+static inline tprio_t chThdGetPriorityX(void) {
+
+ return chThdGetSelfX()->prio;
+}
+
+/**
+ * @brief Returns the number of ticks consumed by the specified thread.
+ * @note This function is only available when the
+ * @p CH_DBG_THREADS_PROFILING configuration option is enabled.
+ *
+ * @param[in] tp pointer to the thread
+ * @return The number of consumed system ticks.
+ *
+ * @xclass
+ */
+#if (CH_DBG_THREADS_PROFILING == TRUE) || defined(__DOXYGEN__)
+static inline systime_t chThdGetTicksX(thread_t *tp) {
+
+ return tp->time;
+}
+#endif
+
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || (CH_CFG_USE_DYNAMIC == TRUE) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief Returns the working area base of the specified thread.
+ *
+ * @param[in] tp pointer to the thread
+ * @return The working area base pointer.
+ *
+ * @xclass
+ */
+static inline stkalign_t *chThdGetWorkingAreaX(thread_t *tp) {
+
+ return tp->wabase;
+}
+#endif /* CH_DBG_ENABLE_STACK_CHECK == TRUE */
+
+/**
+ * @brief Verifies if the specified thread is in the @p CH_STATE_FINAL state.
+ *
+ * @param[in] tp pointer to the thread
+ * @retval true thread terminated.
+ * @retval false thread not terminated.
+ *
+ * @xclass
+ */
+static inline bool chThdTerminatedX(thread_t *tp) {
+
+ return (bool)(tp->state == CH_STATE_FINAL);
+}
+
+/**
+ * @brief Verifies if the current thread has a termination request pending.
+ *
+ * @retval true termination request pending.
+ * @retval false termination request not pending.
+ *
+ * @xclass
+ */
+static inline bool chThdShouldTerminateX(void) {
+
+ return (bool)((chThdGetSelfX()->flags & CH_FLAG_TERMINATE) != (tmode_t)0);
+}
+
+/**
+ * @brief Resumes a thread created with @p chThdCreateI().
+ *
+ * @param[in] tp pointer to the thread
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ *
+ * @iclass
+ */
+static inline thread_t *chThdStartI(thread_t *tp) {
+
+ chDbgAssert(tp->state == CH_STATE_WTSTART, "wrong state");
+
+ return chSchReadyI(tp);
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @sclass
+ */
+static inline void chThdSleepS(systime_t time) {
+
+ chDbgCheck(time != TIME_IMMEDIATE);
+
+ (void) chSchGoSleepTimeoutS(CH_STATE_SLEEPING, time);
+}
+
+/**
+ * @brief Initializes a threads queue object.
+ *
+ * @param[out] tqp pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void chThdQueueObjectInit(threads_queue_t *tqp) {
+
+ queue_init(tqp);
+}
+
+/**
+ * @brief Evaluates to @p true if the specified queue is empty.
+ *
+ * @param[out] tqp pointer to the threads queue object
+ * @return The queue status.
+ * @retval false if the queue is not empty.
+ * @retval true if the queue is empty.
+ *
+ * @iclass
+ */
+static inline bool chThdQueueIsEmptyI(threads_queue_t *tqp) {
+
+ chDbgCheckClassI();
+
+ return queue_isempty(tqp);
+}
+
+/**
+ * @brief Dequeues and wakes up one thread from the threads queue object.
+ * @details Dequeues one thread from the queue without checking if the queue
+ * is empty.
+ * @pre The queue must contain at least an object.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+static inline void chThdDoDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+ thread_t *tp;
+
+ chDbgAssert(queue_notempty(tqp), "empty queue");
+
+ tp = queue_fifo_remove(tqp);
+
+ chDbgAssert(tp->state == CH_STATE_QUEUED, "invalid state");
+
+ tp->u.rdymsg = msg;
+ (void) chSchReadyI(tp);
+}
+
+#endif /* CHTHREADS_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chtm.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chtm.h
new file mode 100644
index 0000000000..471574991f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chtm.h
@@ -0,0 +1,109 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chtm.h
+ * @brief Time Measurement module macros and structures.
+ *
+ * @addtogroup time_measurement
+ * @{
+ */
+
+#ifndef CHTM_H
+#define CHTM_H
+
+#if (CH_CFG_USE_TM == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if PORT_SUPPORTS_RT == FALSE
+#error "CH_CFG_USE_TM requires PORT_SUPPORTS_RT"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a time measurement calibration data.
+ */
+typedef struct {
+ /**
+ * @brief Measurement calibration value.
+ */
+ rtcnt_t offset;
+} tm_calibration_t;
+
+/**
+ * @brief Type of a Time Measurement object.
+ * @note The maximum measurable time period depends on the implementation
+ * of the realtime counter and its clock frequency.
+ * @note The measurement is not 100% cycle-accurate, it can be in excess
+ * of few cycles depending on the compiler and target architecture.
+ * @note Interrupts can affect measurement if the measurement is performed
+ * with interrupts enabled.
+ */
+typedef struct {
+ rtcnt_t best; /**< @brief Best measurement. */
+ rtcnt_t worst; /**< @brief Worst measurement. */
+ rtcnt_t last; /**< @brief Last measurement. */
+ ucnt_t n; /**< @brief Number of measurements. */
+ rttime_t cumulative; /**< @brief Cumulative measurement. */
+} time_measurement_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _tm_init(void);
+ void chTMObjectInit(time_measurement_t *tmp);
+ NOINLINE void chTMStartMeasurementX(time_measurement_t *tmp);
+ NOINLINE void chTMStopMeasurementX(time_measurement_t *tmp);
+ NOINLINE void chTMChainMeasurementToX(time_measurement_t *tmp1,
+ time_measurement_t *tmp2);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_TM == TRUE */
+
+#endif /* CHTM_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chtrace.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chtrace.h
new file mode 100644
index 0000000000..1efafaa26f
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chtrace.h
@@ -0,0 +1,260 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chtrace.h
+ * @brief Tracer macros and structures.
+ *
+ * @addtogroup trace
+ * @{
+ */
+
+#ifndef CHTRACE_H
+#define CHTRACE_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Trace record types
+ * @{
+ */
+#define CH_TRACE_TYPE_UNUSED 0U
+#define CH_TRACE_TYPE_SWITCH 1U
+#define CH_TRACE_TYPE_ISR_ENTER 2U
+#define CH_TRACE_TYPE_ISR_LEAVE 3U
+#define CH_TRACE_TYPE_HALT 4U
+#define CH_TRACE_TYPE_USER 5U
+/** @} */
+
+/**
+ * @name Events to trace
+ * @{
+ */
+#define CH_DBG_TRACE_MASK_DISABLED 255U
+#define CH_DBG_TRACE_MASK_NONE 0U
+#define CH_DBG_TRACE_MASK_SWITCH 1U
+#define CH_DBG_TRACE_MASK_ISR 2U
+#define CH_DBG_TRACE_MASK_HALT 4U
+#define CH_DBG_TRACE_MASK_USER 8U
+#define CH_DBG_TRACE_MASK_SLOW (CH_DBG_TRACE_MASK_SWITCH | \
+ CH_DBG_TRACE_MASK_HALT | \
+ CH_DBG_TRACE_MASK_USER)
+#define CH_DBG_TRACE_MASK_ALL (CH_DBG_TRACE_MASK_SWITCH | \
+ CH_DBG_TRACE_MASK_ISR | \
+ CH_DBG_TRACE_MASK_HALT | \
+ CH_DBG_TRACE_MASK_USER)
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Debug related settings
+ * @{
+ */
+/**
+ * @brief Trace buffer entries.
+ */
+#if !defined(CH_DBG_TRACE_MASK) || defined(__DOXYGEN__)
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
+#endif
+
+/**
+ * @brief Trace buffer entries.
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#if !defined(CH_DBG_TRACE_BUFFER_SIZE) || defined(__DOXYGEN__)
+#define CH_DBG_TRACE_BUFFER_SIZE 128
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(CH_CFG_TRACE_HOOK)
+#error "CH_CFG_TRACE_HOOK not defined in chconf.h"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+#if (CH_DBG_TRACE_MASK != CH_DBG_TRACE_MASK_DISABLED) || defined(__DOXYGEN__)
+/*lint -save -e46 [6.1] An uint32_t is required.*/
+/**
+ * @brief Trace buffer record.
+ */
+typedef struct {
+ /**
+ * @brief Record type.
+ */
+ uint32_t type:3;
+ /**
+ * @brief Switched out thread state.
+ */
+ uint32_t state:5;
+ /**
+ * @brief Accurate time stamp.
+ * @note This field only available if the post supports
+ * @p PORT_SUPPORTS_RT else it is set to zero.
+ */
+ uint32_t rtstamp:24;
+ /**
+ * @brief System time stamp of the switch event.
+ */
+ systime_t time;
+ union {
+ /**
+ * @brief Structure representing a context switch.
+ */
+ struct {
+ /**
+ * @brief Switched in thread.
+ */
+ thread_t *ntp;
+ /**
+ * @brief Object where going to sleep.
+ */
+ void *wtobjp;
+ } sw;
+ /**
+ * @brief Structure representing an ISR enter.
+ */
+ struct {
+ /**
+ * @brief ISR function name taken using @p __func__.
+ */
+ const char *name;
+ } isr;
+ /**
+ * @brief Structure representing an halt.
+ */
+ struct {
+ /**
+ * @brief Halt error string.
+ */
+ const char *reason;
+ } halt;
+ /**
+ * @brief User trace structure.
+ */
+ struct {
+ /**
+ * @brief Trace user parameter 1.
+ */
+ void *up1;
+ /**
+ * @brief Trace user parameter 2.
+ */
+ void *up2;
+ } user;
+ } u;
+} ch_trace_event_t;
+/*lint -restore*/
+
+/**
+ * @brief Trace buffer header.
+ */
+typedef struct {
+ /**
+ * @brief Suspended trace sources mask.
+ */
+ uint16_t suspended;
+ /**
+ * @brief Trace buffer size (entries).
+ */
+ uint16_t size;
+ /**
+ * @brief Pointer to the buffer front.
+ */
+ ch_trace_event_t *ptr;
+ /**
+ * @brief Ring buffer.
+ */
+ ch_trace_event_t buffer[CH_DBG_TRACE_BUFFER_SIZE];
+} ch_trace_buffer_t;
+#endif /* CH_DBG_TRACE_MASK != CH_DBG_TRACE_MASK_DISABLED */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/* When a trace feature is disabled the associated functions are replaced by
+ an empty macro. Note that the macros can be externally redefined in
+ order to interface 3rd parties tracing tools.*/
+#if CH_DBG_TRACE_MASK == CH_DBG_TRACE_MASK_DISABLED
+#if !defined(_trace_init)
+#define _trace_init()
+#endif
+#if !defined(_trace_switch)
+#define _trace_switch(ntp, otp)
+#endif
+#if !defined(_trace_isr_enter)
+#define _trace_isr_enter(isr)
+#endif
+#if !defined(_trace_isr_leave)
+#define _trace_isr_leave(isr)
+#endif
+#if !defined(_trace_halt)
+#define _trace_halt(reason)
+#endif
+#if !defined(chDbgWriteTraceI)
+#define chDbgWriteTraceI(up1, up2)
+#endif
+#if !defined(chDbgWriteTrace)
+#define chDbgWriteTrace(up1, up2)
+#endif
+#endif /* CH_DBG_TRACE_MASK == CH_DBG_TRACE_MASK_DISABLED */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if (CH_DBG_TRACE_MASK != CH_DBG_TRACE_MASK_DISABLED) || defined(__DOXYGEN__)
+ void _trace_init(void);
+ void _trace_switch(thread_t *ntp, thread_t *otp);
+ void _trace_isr_enter(const char *isr);
+ void _trace_isr_leave(const char *isr);
+ void _trace_halt(const char *reason);
+ void chDbgWriteTraceI(void *up1, void *up2);
+ void chDbgWriteTrace(void *up1, void *up2);
+ void chDbgSuspendTraceI(uint16_t mask);
+ void chDbgSuspendTrace(uint16_t mask);
+ void chDbgResumeTraceI(uint16_t mask);
+ void chDbgResumeTrace(uint16_t mask);
+#endif /* CH_DBG_TRACE_MASK != CH_DBG_TRACE_MASK_DISABLED */
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CHTRACE_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chvt.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chvt.h
new file mode 100644
index 0000000000..3c14b74c43
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/include/chvt.h
@@ -0,0 +1,755 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chvt.h
+ * @brief Time and Virtual Timers module macros and structures.
+ *
+ * @addtogroup time
+ * @{
+ */
+
+#ifndef CHVT_H
+#define CHVT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Special time constants
+ * @{
+ */
+/**
+ * @brief Zero time specification for some functions with a timeout
+ * specification.
+ * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter,
+ * see the specific function documentation.
+ */
+#define TIME_IMMEDIATE ((systime_t)0)
+
+/**
+ * @brief Infinite time specification for all functions with a timeout
+ * specification.
+ * @note Not all functions accept @p TIME_INFINITE as timeout parameter,
+ * see the specific function documentation.
+ */
+#define TIME_INFINITE ((systime_t)-1)
+
+/**
+ * @brief Maximum time constant.
+ */
+#define TIME_MAXIMUM ((systime_t)-2)
+/** @} */
+
+/**
+ * @brief Maximum unsigned integer.
+ */
+#define __UINT_MAX ((unsigned int)-1)
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if (CH_CFG_ST_RESOLUTION != 16) && (CH_CFG_ST_RESOLUTION != 32)
+#error "invalid CH_CFG_ST_RESOLUTION specified, must be 16 or 32"
+#endif
+
+#if CH_CFG_ST_FREQUENCY <= 0
+#error "invalid CH_CFG_ST_FREQUENCY specified, must be greater than zero"
+#endif
+
+#if (CH_CFG_ST_TIMEDELTA < 0) || (CH_CFG_ST_TIMEDELTA == 1)
+#error "invalid CH_CFG_ST_TIMEDELTA specified, must " \
+ "be zero or greater than one"
+#endif
+
+#if (CH_CFG_ST_TIMEDELTA > 0) && (CH_CFG_TIME_QUANTUM > 0)
+#error "CH_CFG_TIME_QUANTUM not supported in tickless mode"
+#endif
+
+#if (CH_CFG_ST_TIMEDELTA > 0) && (CH_DBG_THREADS_PROFILING == TRUE)
+#error "CH_DBG_THREADS_PROFILING not supported in tickless mode"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name Fast time conversion utilities
+ * @{
+ */
+/**
+ * @brief Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] sec number of seconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define S2ST(sec) \
+ ((systime_t)((uint32_t)(sec) * (uint32_t)CH_CFG_ST_FREQUENCY))
+
+/**
+ * @brief Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] msec number of milliseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define MS2ST(msec) \
+ ((systime_t)(((((uint32_t)(msec)) * \
+ ((uint32_t)CH_CFG_ST_FREQUENCY)) + 999UL) / 1000UL))
+
+/**
+ * @brief Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] usec number of microseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define US2ST(usec) \
+ ((systime_t)(((((uint32_t)(usec)) * \
+ ((uint32_t)CH_CFG_ST_FREQUENCY)) + 999999UL) / 1000000UL))
+
+/**
+ * @brief System ticks to seconds.
+ * @details Converts from system ticks number to seconds.
+ * @note The result is rounded up to the next second boundary.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] n number of system ticks
+ * @return The number of seconds.
+ *
+ * @api
+ */
+#define ST2S(n) (((n) + CH_CFG_ST_FREQUENCY - 1UL) / CH_CFG_ST_FREQUENCY)
+
+/**
+ * @brief System ticks to milliseconds.
+ * @details Converts from system ticks number to milliseconds.
+ * @note The result is rounded up to the next millisecond boundary.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] n number of system ticks
+ * @return The number of milliseconds.
+ *
+ * @api
+ */
+#define ST2MS(n) (((n) * 1000UL + CH_CFG_ST_FREQUENCY - 1UL) / \
+ CH_CFG_ST_FREQUENCY)
+
+/**
+ * @brief System ticks to microseconds.
+ * @details Converts from system ticks number to microseconds.
+ * @note The result is rounded up to the next microsecond boundary.
+ * @note Use of this macro for large values is not secure because
+ * integer overflows, make sure your value can be correctly
+ * converted.
+ *
+ * @param[in] n number of system ticks
+ * @return The number of microseconds.
+ *
+ * @api
+ */
+#define ST2US(n) (((n) * 1000000UL + CH_CFG_ST_FREQUENCY - 1UL) / \
+ CH_CFG_ST_FREQUENCY)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*
+ * Virtual Timers APIs.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _vt_init(void);
+ void chVTDoSetI(virtual_timer_t *vtp, systime_t delay,
+ vtfunc_t vtfunc, void *par);
+ void chVTDoResetI(virtual_timer_t *vtp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @name Secure time conversion utilities
+ * @{
+ */
+/**
+ * @brief Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ * @note This function uses a 64 bits internal representation,
+ * use with non-constant parameters can lead to inefficient
+ * code because 64 bits arithmetic would be used at runtime.
+ *
+ * @param[in] sec number of seconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+static inline systime_t LL_S2ST(unsigned int sec) {
+ uint64_t ticks = (uint64_t)sec * (uint64_t)CH_CFG_ST_FREQUENCY;
+
+ chDbgAssert(ticks <= (uint64_t)TIME_MAXIMUM, "conversion overflow");
+
+ return (systime_t)ticks;
+}
+
+/**
+ * @brief Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ * @note This function uses a 64 bits internal representation,
+ * use with non-constant parameters can lead to inefficient
+ * code because 64 bits arithmetic would be used at runtime.
+ *
+ * @param[in] msec number of milliseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+static inline systime_t LL_MS2ST(unsigned int msec) {
+ uint64_t ticks = (((uint64_t)msec * (uint64_t)CH_CFG_ST_FREQUENCY) + 999ULL)
+ / 1000ULL;
+
+ chDbgAssert(ticks <= (uint64_t)TIME_MAXIMUM, "conversion overflow");
+
+ return (systime_t)ticks;
+}
+
+/**
+ * @brief Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ * @note This function uses a 64 bits internal representation,
+ * use with non-constant parameters can lead to inefficient
+ * code because 64 bits arithmetic would be used at runtime.
+ *
+ * @param[in] usec number of microseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+static inline systime_t LL_US2ST(unsigned int usec) {
+ uint64_t ticks = (((uint64_t)usec * (uint64_t)CH_CFG_ST_FREQUENCY) + 999999ULL)
+ / 1000000ULL;
+
+ chDbgAssert(ticks <= (uint64_t)TIME_MAXIMUM, "conversion overflow");
+
+ return (systime_t)ticks;
+}
+
+/**
+ * @brief System ticks to seconds.
+ * @details Converts from system ticks number to seconds.
+ * @note The result is rounded up to the next second boundary.
+ * @note This function uses a 64 bits internal representation,
+ * use with non-constant parameters can lead to inefficient
+ * code because 64 bits arithmetic would be used at runtime.
+ *
+ * @param[in] n number of system ticks
+ * @return The number of seconds.
+ *
+ * @api
+ */
+static inline unsigned int LL_ST2S(systime_t n) {
+ uint64_t sec = ((uint64_t)n + (uint64_t)CH_CFG_ST_FREQUENCY - 1ULL)
+ / (uint64_t)CH_CFG_ST_FREQUENCY;
+
+ chDbgAssert(sec < (uint64_t)__UINT_MAX, "conversion overflow");
+
+ return (unsigned int)sec;
+}
+
+/**
+ * @brief System ticks to milliseconds.
+ * @details Converts from system ticks number to milliseconds.
+ * @note The result is rounded up to the next millisecond boundary.
+ * @note This function uses a 64 bits internal representation,
+ * use with non-constant parameters can lead to inefficient
+ * code because 64 bits arithmetic would be used at runtime.
+ *
+ * @param[in] n number of system ticks
+ * @return The number of milliseconds.
+ *
+ * @api
+ */
+static inline unsigned int LL_ST2MS(systime_t n) {
+ uint64_t msec = (((uint64_t)n * 1000ULL) + (uint64_t)CH_CFG_ST_FREQUENCY - 1ULL)
+ / (uint64_t)CH_CFG_ST_FREQUENCY;
+
+ chDbgAssert(msec < (uint64_t)__UINT_MAX, "conversion overflow");
+
+ return (unsigned int)msec;
+}
+
+/**
+ * @brief System ticks to microseconds.
+ * @details Converts from system ticks number to microseconds.
+ * @note The result is rounded up to the next microsecond boundary.
+ * @note This function uses a 64 bits internal representation,
+ * use with non-constant parameters can lead to inefficient
+ * code because 64 bits arithmetic would be used at runtime.
+ *
+ * @param[in] n number of system ticks
+ * @return The number of microseconds.
+ *
+ * @api
+ */
+static inline unsigned int LL_ST2US(systime_t n) {
+ uint64_t usec = (((uint64_t)n * 1000000ULL) + (uint64_t)CH_CFG_ST_FREQUENCY - 1ULL)
+ / (uint64_t)CH_CFG_ST_FREQUENCY;
+
+ chDbgAssert(usec < (uint64_t)__UINT_MAX, "conversion overflow");
+
+ return (unsigned int)usec;
+}
+/** @} */
+
+/**
+ * @brief Initializes a @p virtual_timer_t object.
+ * @note Initializing a timer object is not strictly required because
+ * the function @p chVTSetI() initializes the object too. This
+ * function is only useful if you need to perform a @p chVTIsArmed()
+ * check before calling @p chVTSetI().
+ *
+ * @param[out] vtp the @p virtual_timer_t structure pointer
+ *
+ * @init
+ */
+static inline void chVTObjectInit(virtual_timer_t *vtp) {
+
+ vtp->func = NULL;
+}
+
+/**
+ * @brief Current system time.
+ * @details Returns the number of system ticks since the @p chSysInit()
+ * invocation.
+ * @note The counter can reach its maximum and then restart from zero.
+ * @note This function can be called from any context but its atomicity
+ * is not guaranteed on architectures whose word size is less than
+ * @p systime_t size.
+ *
+ * @return The system time in ticks.
+ *
+ * @xclass
+ */
+static inline systime_t chVTGetSystemTimeX(void) {
+
+#if CH_CFG_ST_TIMEDELTA == 0
+ return ch.vtlist.systime;
+#else /* CH_CFG_ST_TIMEDELTA > 0 */
+ return port_timer_get_time();
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+}
+
+/**
+ * @brief Current system time.
+ * @details Returns the number of system ticks since the @p chSysInit()
+ * invocation.
+ * @note The counter can reach its maximum and then restart from zero.
+ *
+ * @return The system time in ticks.
+ *
+ * @api
+ */
+static inline systime_t chVTGetSystemTime(void) {
+ systime_t systime;
+
+ chSysLock();
+ systime = chVTGetSystemTimeX();
+ chSysUnlock();
+
+ return systime;
+}
+
+/**
+ * @brief Returns the elapsed time since the specified start time.
+ *
+ * @param[in] start start time
+ * @return The elapsed time.
+ *
+ * @xclass
+ */
+static inline systime_t chVTTimeElapsedSinceX(systime_t start) {
+
+ return chVTGetSystemTimeX() - start;
+}
+
+/**
+ * @brief Checks if the specified time is within the specified time window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ * @note This function can be called from any context.
+ *
+ * @param[in] time the time to be verified
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool chVTIsTimeWithinX(systime_t time,
+ systime_t start,
+ systime_t end) {
+
+ return (bool)((systime_t)(time - start) < (systime_t)(end - start));
+}
+
+/**
+ * @brief Checks if the current system time is within the specified time
+ * window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ *
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool chVTIsSystemTimeWithinX(systime_t start, systime_t end) {
+
+ return chVTIsTimeWithinX(chVTGetSystemTimeX(), start, end);
+}
+
+/**
+ * @brief Checks if the current system time is within the specified time
+ * window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ *
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @api
+ */
+static inline bool chVTIsSystemTimeWithin(systime_t start, systime_t end) {
+
+ return chVTIsTimeWithinX(chVTGetSystemTime(), start, end);
+}
+
+/**
+ * @brief Returns the time interval until the next timer event.
+ * @note The return value is not perfectly accurate and can report values
+ * in excess of @p CH_CFG_ST_TIMEDELTA ticks.
+ * @note The interval returned by this function is only meaningful if
+ * more timers are not added to the list until the returned time.
+ *
+ * @param[out] timep pointer to a variable that will contain the time
+ * interval until the next timer elapses. This pointer
+ * can be @p NULL if the information is not required.
+ * @return The time, in ticks, until next time event.
+ * @retval false if the timers list is empty.
+ * @retval true if the timers list contains at least one timer.
+ *
+ * @iclass
+ */
+static inline bool chVTGetTimersStateI(systime_t *timep) {
+
+ chDbgCheckClassI();
+
+ if (&ch.vtlist == (virtual_timers_list_t *)ch.vtlist.next) {
+ return false;
+ }
+
+ if (timep != NULL) {
+#if CH_CFG_ST_TIMEDELTA == 0
+ *timep = ch.vtlist.next->delta;
+#else
+ *timep = ch.vtlist.lasttime + ch.vtlist.next->delta +
+ CH_CFG_ST_TIMEDELTA - chVTGetSystemTimeX();
+#endif
+ }
+
+ return true;
+}
+
+/**
+ * @brief Returns @p true if the specified timer is armed.
+ * @pre The timer must have been initialized using @p chVTObjectInit()
+ * or @p chVTDoSetI().
+ *
+ * @param[in] vtp the @p virtual_timer_t structure pointer
+ * @return true if the timer is armed.
+ *
+ * @iclass
+ */
+static inline bool chVTIsArmedI(virtual_timer_t *vtp) {
+
+ chDbgCheckClassI();
+
+ return (bool)(vtp->func != NULL);
+}
+
+/**
+ * @brief Returns @p true if the specified timer is armed.
+ * @pre The timer must have been initialized using @p chVTObjectInit()
+ * or @p chVTDoSetI().
+ *
+ * @param[in] vtp the @p virtual_timer_t structure pointer
+ * @return true if the timer is armed.
+ *
+ * @api
+ */
+static inline bool chVTIsArmed(virtual_timer_t *vtp) {
+ bool b;
+
+ chSysLock();
+ b = chVTIsArmedI(vtp);
+ chSysUnlock();
+
+ return b;
+}
+
+/**
+ * @brief Disables a Virtual Timer.
+ * @note The timer is first checked and disabled only if armed.
+ * @pre The timer must have been initialized using @p chVTObjectInit()
+ * or @p chVTDoSetI().
+ *
+ * @param[in] vtp the @p virtual_timer_t structure pointer
+ *
+ * @iclass
+ */
+static inline void chVTResetI(virtual_timer_t *vtp) {
+
+ if (chVTIsArmedI(vtp)) {
+ chVTDoResetI(vtp);
+ }
+}
+
+/**
+ * @brief Disables a Virtual Timer.
+ * @note The timer is first checked and disabled only if armed.
+ * @pre The timer must have been initialized using @p chVTObjectInit()
+ * or @p chVTDoSetI().
+ *
+ * @param[in] vtp the @p virtual_timer_t structure pointer
+ *
+ * @api
+ */
+static inline void chVTReset(virtual_timer_t *vtp) {
+
+ chSysLock();
+ chVTResetI(vtp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Enables a virtual timer.
+ * @details If the virtual timer was already enabled then it is re-enabled
+ * using the new parameters.
+ * @pre The timer must have been initialized using @p chVTObjectInit()
+ * or @p chVTDoSetI().
+ *
+ * @param[in] vtp the @p virtual_timer_t structure pointer
+ * @param[in] delay the number of ticks before the operation timeouts, the
+ * special values are handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ * @param[in] vtfunc the timer callback function. After invoking the
+ * callback the timer is disabled and the structure can
+ * be disposed or reused.
+ * @param[in] par a parameter that will be passed to the callback
+ * function
+ *
+ * @iclass
+ */
+static inline void chVTSetI(virtual_timer_t *vtp, systime_t delay,
+ vtfunc_t vtfunc, void *par) {
+
+ chVTResetI(vtp);
+ chVTDoSetI(vtp, delay, vtfunc, par);
+}
+
+/**
+ * @brief Enables a virtual timer.
+ * @details If the virtual timer was already enabled then it is re-enabled
+ * using the new parameters.
+ * @pre The timer must have been initialized using @p chVTObjectInit()
+ * or @p chVTDoSetI().
+ *
+ * @param[in] vtp the @p virtual_timer_t structure pointer
+ * @param[in] delay the number of ticks before the operation timeouts, the
+ * special values are handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ * @param[in] vtfunc the timer callback function. After invoking the
+ * callback the timer is disabled and the structure can
+ * be disposed or reused.
+ * @param[in] par a parameter that will be passed to the callback
+ * function
+ *
+ * @api
+ */
+static inline void chVTSet(virtual_timer_t *vtp, systime_t delay,
+ vtfunc_t vtfunc, void *par) {
+
+ chSysLock();
+ chVTSetI(vtp, delay, vtfunc, par);
+ chSysUnlock();
+}
+
+/**
+ * @brief Virtual timers ticker.
+ * @note The system lock is released before entering the callback and
+ * re-acquired immediately after. It is callback's responsibility
+ * to acquire the lock if needed. This is done in order to reduce
+ * interrupts jitter when many timers are in use.
+ *
+ * @iclass
+ */
+static inline void chVTDoTickI(void) {
+
+ chDbgCheckClassI();
+
+#if CH_CFG_ST_TIMEDELTA == 0
+ ch.vtlist.systime++;
+ if (&ch.vtlist != (virtual_timers_list_t *)ch.vtlist.next) {
+ /* The list is not empty, processing elements on top.*/
+ --ch.vtlist.next->delta;
+ while (ch.vtlist.next->delta == (systime_t)0) {
+ virtual_timer_t *vtp;
+ vtfunc_t fn;
+
+ vtp = ch.vtlist.next;
+ fn = vtp->func;
+ vtp->func = NULL;
+ vtp->next->prev = (virtual_timer_t *)&ch.vtlist;
+ ch.vtlist.next = vtp->next;
+ chSysUnlockFromISR();
+ fn(vtp->par);
+ chSysLockFromISR();
+ }
+ }
+#else /* CH_CFG_ST_TIMEDELTA > 0 */
+ virtual_timer_t *vtp;
+ systime_t now, delta;
+
+ /* First timer to be processed.*/
+ vtp = ch.vtlist.next;
+ now = chVTGetSystemTimeX();
+
+ /* All timers within the time window are triggered and removed,
+ note that the loop is stopped by the timers header having
+ "ch.vtlist.vt_delta == (systime_t)-1" which is greater than
+ all deltas.*/
+ while (vtp->delta <= (systime_t)(now - ch.vtlist.lasttime)) {
+ vtfunc_t fn;
+
+ /* The "last time" becomes this timer's expiration time.*/
+ ch.vtlist.lasttime += vtp->delta;
+
+ vtp->next->prev = (virtual_timer_t *)&ch.vtlist;
+ ch.vtlist.next = vtp->next;
+ fn = vtp->func;
+ vtp->func = NULL;
+
+ /* if the list becomes empty then the timer is stopped.*/
+ if (ch.vtlist.next == (virtual_timer_t *)&ch.vtlist) {
+ port_timer_stop_alarm();
+ }
+
+ /* Leaving the system critical zone in order to execute the callback
+ and in order to give a preemption chance to higher priority
+ interrupts.*/
+ chSysUnlockFromISR();
+
+ /* The callback is invoked outside the kernel critical zone.*/
+ fn(vtp->par);
+
+ /* Re-entering the critical zone in order to continue the exploration
+ of the list.*/
+ chSysLockFromISR();
+
+ /* Next element in the list, the current time could have advanced so
+ recalculating the time window.*/
+ vtp = ch.vtlist.next;
+ now = chVTGetSystemTimeX();
+ }
+
+ /* if the list is empty, nothing else to do.*/
+ if (ch.vtlist.next == (virtual_timer_t *)&ch.vtlist) {
+ return;
+ }
+
+ /* Recalculating the next alarm time.*/
+ delta = ch.vtlist.lasttime + vtp->delta - now;
+ if (delta < (systime_t)CH_CFG_ST_TIMEDELTA) {
+ delta = (systime_t)CH_CFG_ST_TIMEDELTA;
+ }
+ port_timer_set_alarm(now + delta);
+
+ chDbgAssert((chVTGetSystemTimeX() - ch.vtlist.lasttime) <=
+ (now + delta - ch.vtlist.lasttime),
+ "exceeding delta");
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+}
+
+#endif /* CHVT_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/rt.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/rt.mk
new file mode 100644
index 0000000000..5ebe4079cf
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/rt.mk
@@ -0,0 +1,75 @@
+# List of all the ChibiOS/RT kernel files, there is no need to remove the files
+# from this list, you can disable parts of the kernel by editing chconf.h.
+ifeq ($(USE_SMART_BUILD),yes)
+CHCONF := $(strip $(shell cat chconf.h | egrep -e "\#define"))
+
+KERNSRC := $(CHIBIOS)/os/rt/src/chsys.c \
+ $(CHIBIOS)/os/rt/src/chdebug.c \
+ $(CHIBIOS)/os/rt/src/chtrace.c \
+ $(CHIBIOS)/os/rt/src/chvt.c \
+ $(CHIBIOS)/os/rt/src/chschd.c \
+ $(CHIBIOS)/os/rt/src/chthreads.c
+ifneq ($(findstring CH_CFG_USE_TM TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chtm.c
+endif
+ifneq ($(findstring CH_DBG_STATISTICS TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chstats.c
+endif
+ifneq ($(findstring CH_CFG_USE_REGISTRY TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chregistry.c
+endif
+ifneq ($(findstring CH_CFG_USE_SEMAPHORES TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chsem.c
+endif
+ifneq ($(findstring CH_CFG_USE_MUTEXES TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chmtx.c
+endif
+ifneq ($(findstring CH_CFG_USE_CONDVARS TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chcond.c
+endif
+ifneq ($(findstring CH_CFG_USE_EVENTS TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chevents.c
+endif
+ifneq ($(findstring CH_CFG_USE_MESSAGES TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chmsg.c
+endif
+ifneq ($(findstring CH_CFG_USE_DYNAMIC TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/rt/src/chdynamic.c
+endif
+ifneq ($(findstring CH_CFG_USE_MAILBOXES TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/common/oslib/src/chmboxes.c
+endif
+ifneq ($(findstring CH_CFG_USE_MEMCORE TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/common/oslib/src/chmemcore.c
+endif
+ifneq ($(findstring CH_CFG_USE_HEAP TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/common/oslib/src/chheap.c
+endif
+ifneq ($(findstring CH_CFG_USE_MEMPOOLS TRUE,$(CHCONF)),)
+KERNSRC += $(CHIBIOS)/os/common/oslib/src/chmempools.c
+endif
+else
+KERNSRC := $(CHIBIOS)/os/rt/src/chsys.c \
+ $(CHIBIOS)/os/rt/src/chdebug.c \
+ $(CHIBIOS)/os/rt/src/chtrace.c \
+ $(CHIBIOS)/os/rt/src/chvt.c \
+ $(CHIBIOS)/os/rt/src/chschd.c \
+ $(CHIBIOS)/os/rt/src/chthreads.c \
+ $(CHIBIOS)/os/rt/src/chtm.c \
+ $(CHIBIOS)/os/rt/src/chstats.c \
+ $(CHIBIOS)/os/rt/src/chregistry.c \
+ $(CHIBIOS)/os/rt/src/chsem.c \
+ $(CHIBIOS)/os/rt/src/chmtx.c \
+ $(CHIBIOS)/os/rt/src/chcond.c \
+ $(CHIBIOS)/os/rt/src/chevents.c \
+ $(CHIBIOS)/os/rt/src/chmsg.c \
+ $(CHIBIOS)/os/rt/src/chdynamic.c \
+ $(CHIBIOS)/os/common/oslib/src/chmboxes.c \
+ $(CHIBIOS)/os/common/oslib/src/chmemcore.c \
+ $(CHIBIOS)/os/common/oslib/src/chheap.c \
+ $(CHIBIOS)/os/common/oslib/src/chmempools.c
+endif
+
+# Required include directories
+KERNINC := $(CHIBIOS)/os/rt/include \
+ $(CHIBIOS)/os/common/oslib/include
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chcond.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chcond.c
similarity index 50%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chcond.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chcond.c
index a8128c07e4..558d5a0793 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chcond.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chcond.c
@@ -1,28 +1,20 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
- This file is part of ChibiOS/RT.
+ This file is part of ChibiOS.
- ChibiOS/RT is free software; you can redistribute it and/or modify
+ ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
- ChibiOS/RT is distributed in the hope that it will be useful,
+ ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
*/
/*
Concepts and parts of this file have been contributed by Leon Woestenberg.
@@ -32,51 +24,76 @@
* @file chcond.c
* @brief Condition Variables code.
*
- * @addtogroup condvars Condition Variables
+ * @addtogroup condvars
* @details This module implements the Condition Variables mechanism. Condition
- * variables are an extensions to the Mutex subsystem and cannot
+ * variables are an extensions to the mutex subsystem and cannot
* work alone.
* Operation mode
* The condition variable is a synchronization object meant to be
- * used inside a zone protected by a @p Mutex. Mutexes and CondVars
- * together can implement a Monitor construct.
- * @pre In order to use the condition variable APIs the @p CH_USE_CONDVARS
+ * used inside a zone protected by a mutex. Mutexes and condition
+ * variables together can implement a Monitor construct.
+ * @pre In order to use the condition variable APIs the @p CH_CFG_USE_CONDVARS
* option must be enabled in @p chconf.h.
* @{
*/
#include "ch.h"
-#if (CH_USE_CONDVARS && CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#if (CH_CFG_USE_CONDVARS == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
/**
- * @brief Initializes s @p CondVar structure.
+ * @brief Initializes s @p condition_variable_t structure.
*
- * @param[out] cp pointer to a @p CondVar structure
+ * @param[out] cp pointer to a @p condition_variable_t structure
*
* @init
*/
-void chCondInit(CondVar *cp) {
+void chCondObjectInit(condition_variable_t *cp) {
- chDbgCheck(cp != NULL, "chCondInit");
+ chDbgCheck(cp != NULL);
- queue_init(&cp->c_queue);
+ queue_init(&cp->queue);
}
/**
* @brief Signals one thread that is waiting on the condition variable.
*
- * @param[in] cp pointer to the @p CondVar structure
+ * @param[in] cp pointer to the @p condition_variable_t structure
*
* @api
*/
-void chCondSignal(CondVar *cp) {
+void chCondSignal(condition_variable_t *cp) {
- chDbgCheck(cp != NULL, "chCondSignal");
+ chDbgCheck(cp != NULL);
chSysLock();
- if (notempty(&cp->c_queue))
- chSchWakeupS(fifo_remove(&cp->c_queue), RDY_OK);
+ if (queue_notempty(&cp->queue)) {
+ chSchWakeupS(queue_fifo_remove(&cp->queue), MSG_OK);
+ }
chSysUnlock();
}
@@ -87,27 +104,30 @@ void chCondSignal(CondVar *cp) {
* interrupt handlers always reschedule on exit so an explicit
* reschedule must not be performed in ISRs.
*
- * @param[in] cp pointer to the @p CondVar structure
+ * @param[in] cp pointer to the @p condition_variable_t structure
*
* @iclass
*/
-void chCondSignalI(CondVar *cp) {
+void chCondSignalI(condition_variable_t *cp) {
chDbgCheckClassI();
- chDbgCheck(cp != NULL, "chCondSignalI");
+ chDbgCheck(cp != NULL);
- if (notempty(&cp->c_queue))
- chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_OK;
+ if (queue_notempty(&cp->queue)) {
+ thread_t *tp = queue_fifo_remove(&cp->queue);
+ tp->u.rdymsg = MSG_OK;
+ (void) chSchReadyI(tp);
+ }
}
/**
* @brief Signals all threads that are waiting on the condition variable.
*
- * @param[in] cp pointer to the @p CondVar structure
+ * @param[in] cp pointer to the @p condition_variable_t structure
*
* @api
*/
-void chCondBroadcast(CondVar *cp) {
+void chCondBroadcast(condition_variable_t *cp) {
chSysLock();
chCondBroadcastI(cp);
@@ -122,20 +142,21 @@ void chCondBroadcast(CondVar *cp) {
* interrupt handlers always reschedule on exit so an explicit
* reschedule must not be performed in ISRs.
*
- * @param[in] cp pointer to the @p CondVar structure
+ * @param[in] cp pointer to the @p condition_variable_t structure
*
* @iclass
*/
-void chCondBroadcastI(CondVar *cp) {
+void chCondBroadcastI(condition_variable_t *cp) {
chDbgCheckClassI();
- chDbgCheck(cp != NULL, "chCondBroadcastI");
+ chDbgCheck(cp != NULL);
- /* Empties the condition variable queue and inserts all the Threads into the
- ready list in FIFO order. The wakeup message is set to @p RDY_RESET in
+ /* Empties the condition variable queue and inserts all the threads into the
+ ready list in FIFO order. The wakeup message is set to @p MSG_RESET in
order to make a chCondBroadcast() detectable from a chCondSignal().*/
- while (cp->c_queue.p_next != (void *)&cp->c_queue)
- chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_RESET;
+ while (queue_notempty(&cp->queue)) {
+ chSchReadyI(queue_fifo_remove(&cp->queue))->u.rdymsg = MSG_RESET;
+ }
}
/**
@@ -145,17 +166,17 @@ void chCondBroadcastI(CondVar *cp) {
* is performed atomically.
* @pre The invoking thread must have at least one owned mutex.
*
- * @param[in] cp pointer to the @p CondVar structure
+ * @param[in] cp pointer to the @p condition_variable_t structure
* @return A message specifying how the invoking thread has been
* released from the condition variable.
- * @retval RDY_OK if the condvar has been signaled using
+ * @retval MSG_OK if the condition variable has been signaled using
* @p chCondSignal().
- * @retval RDY_RESET if the condvar has been signaled using
+ * @retval MSG_RESET if the condition variable has been signaled using
* @p chCondBroadcast().
*
* @api
*/
-msg_t chCondWait(CondVar *cp) {
+msg_t chCondWait(condition_variable_t *cp) {
msg_t msg;
chSysLock();
@@ -171,49 +192,53 @@ msg_t chCondWait(CondVar *cp) {
* is performed atomically.
* @pre The invoking thread must have at least one owned mutex.
*
- * @param[in] cp pointer to the @p CondVar structure
+ * @param[in] cp pointer to the @p condition_variable_t structure
* @return A message specifying how the invoking thread has been
* released from the condition variable.
- * @retval RDY_OK if the condvar has been signaled using
+ * @retval MSG_OK if the condition variable has been signaled using
* @p chCondSignal().
- * @retval RDY_RESET if the condvar has been signaled using
+ * @retval MSG_RESET if the condition variable has been signaled using
* @p chCondBroadcast().
*
* @sclass
*/
-msg_t chCondWaitS(CondVar *cp) {
- Thread *ctp = currp;
- Mutex *mp;
+msg_t chCondWaitS(condition_variable_t *cp) {
+ thread_t *ctp = currp;
+ mutex_t *mp;
msg_t msg;
chDbgCheckClassS();
- chDbgCheck(cp != NULL, "chCondWaitS");
- chDbgAssert(ctp->p_mtxlist != NULL,
- "chCondWaitS(), #1",
- "not owning a mutex");
-
- mp = chMtxUnlockS();
- ctp->p_u.wtobjp = cp;
- prio_insert(ctp, &cp->c_queue);
- chSchGoSleepS(THD_STATE_WTCOND);
- msg = ctp->p_u.rdymsg;
+ chDbgCheck(cp != NULL);
+ chDbgAssert(ctp->mtxlist != NULL, "not owning a mutex");
+
+ /* Getting "current" mutex and releasing it.*/
+ mp = chMtxGetNextMutexS();
+ chMtxUnlockS(mp);
+
+ /* Start waiting on the condition variable, on exit the mutex is taken
+ again.*/
+ ctp->u.wtobjp = cp;
+ queue_prio_insert(ctp, &cp->queue);
+ chSchGoSleepS(CH_STATE_WTCOND);
+ msg = ctp->u.rdymsg;
chMtxLockS(mp);
+
return msg;
}
-#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__)
+#if (CH_CFG_USE_CONDVARS_TIMEOUT == TRUE) || defined(__DOXYGEN__)
/**
* @brief Waits on the condition variable releasing the mutex lock.
* @details Releases the currently owned mutex, waits on the condition
* variable, and finally acquires the mutex again. All the sequence
* is performed atomically.
* @pre The invoking thread must have at least one owned mutex.
- * @pre The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled
+ * @pre The configuration option @p CH_CFG_USE_CONDVARS_TIMEOUT must be enabled
* in order to use this function.
* @post Exiting the function because a timeout does not re-acquire the
* mutex, the mutex ownership is lost.
*
- * @param[in] cp pointer to the @p CondVar structure
+ * @param[in] cp pointer to the @p condition_variable_t structure
* @param[in] time the number of ticks before the operation timeouts, the
* special values are handled as follow:
* - @a TIME_INFINITE no timeout.
@@ -221,21 +246,22 @@ msg_t chCondWaitS(CondVar *cp) {
* .
* @return A message specifying how the invoking thread has been
* released from the condition variable.
- * @retval RDY_OK if the condvar has been signaled using
+ * @retval MSG_OK if the condition variable has been signaled using
* @p chCondSignal().
- * @retval RDY_RESET if the condvar has been signaled using
+ * @retval MSG_RESET if the condition variable has been signaled using
* @p chCondBroadcast().
- * @retval RDY_TIMEOUT if the condvar has not been signaled within the
- * specified timeout.
+ * @retval MSG_TIMEOUT if the condition variable has not been signaled within
+ * the specified timeout.
*
* @api
*/
-msg_t chCondWaitTimeout(CondVar *cp, systime_t time) {
+msg_t chCondWaitTimeout(condition_variable_t *cp, systime_t time) {
msg_t msg;
chSysLock();
msg = chCondWaitTimeoutS(cp, time);
chSysUnlock();
+
return msg;
}
@@ -245,12 +271,12 @@ msg_t chCondWaitTimeout(CondVar *cp, systime_t time) {
* variable, and finally acquires the mutex again. All the sequence
* is performed atomically.
* @pre The invoking thread must have at least one owned mutex.
- * @pre The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled
+ * @pre The configuration option @p CH_CFG_USE_CONDVARS_TIMEOUT must be enabled
* in order to use this function.
* @post Exiting the function because a timeout does not re-acquire the
* mutex, the mutex ownership is lost.
*
- * @param[in] cp pointer to the @p CondVar structure
+ * @param[in] cp pointer to the @p condition_variable_t structure
* @param[in] time the number of ticks before the operation timeouts, the
* special values are handled as follow:
* - @a TIME_INFINITE no timeout.
@@ -258,35 +284,40 @@ msg_t chCondWaitTimeout(CondVar *cp, systime_t time) {
* .
* @return A message specifying how the invoking thread has been
* released from the condition variable.
- * @retval RDY_OK if the condvar has been signaled using
+ * @retval MSG_OK if the condition variable has been signaled using
* @p chCondSignal().
- * @retval RDY_RESET if the condvar has been signaled using
+ * @retval MSG_RESET if the condition variable has been signaled using
* @p chCondBroadcast().
- * @retval RDY_TIMEOUT if the condvar has not been signaled within the
- * specified timeout.
+ * @retval MSG_TIMEOUT if the condition variable has not been signaled within
+ * the specified timeout.
*
* @sclass
*/
-msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time) {
- Mutex *mp;
+msg_t chCondWaitTimeoutS(condition_variable_t *cp, systime_t time) {
+ mutex_t *mp;
msg_t msg;
chDbgCheckClassS();
- chDbgCheck((cp != NULL) && (time != TIME_IMMEDIATE), "chCondWaitTimeoutS");
- chDbgAssert(currp->p_mtxlist != NULL,
- "chCondWaitTimeoutS(), #1",
- "not owning a mutex");
-
- mp = chMtxUnlockS();
- currp->p_u.wtobjp = cp;
- prio_insert(currp, &cp->c_queue);
- msg = chSchGoSleepTimeoutS(THD_STATE_WTCOND, time);
- if (msg != RDY_TIMEOUT)
+ chDbgCheck((cp != NULL) && (time != TIME_IMMEDIATE));
+ chDbgAssert(currp->mtxlist != NULL, "not owning a mutex");
+
+ /* Getting "current" mutex and releasing it.*/
+ mp = chMtxGetNextMutexS();
+ chMtxUnlockS(mp);
+
+ /* Start waiting on the condition variable, on exit the mutex is taken
+ again.*/
+ currp->u.wtobjp = cp;
+ queue_prio_insert(currp, &cp->queue);
+ msg = chSchGoSleepTimeoutS(CH_STATE_WTCOND, time);
+ if (msg != MSG_TIMEOUT) {
chMtxLockS(mp);
+ }
+
return msg;
}
-#endif /* CH_USE_CONDVARS_TIMEOUT */
+#endif /* CH_CFG_USE_CONDVARS_TIMEOUT == TRUE */
-#endif /* CH_USE_CONDVARS && CH_USE_MUTEXES */
+#endif /* CH_CFG_USE_CONDVARS == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chdebug.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chdebug.c
new file mode 100644
index 0000000000..c80537cb0e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chdebug.c
@@ -0,0 +1,259 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chdebug.c
+ * @brief Debug support code.
+ *
+ * @addtogroup debug
+ * @details Debug APIs and services:
+ * - Runtime system state and call protocol check. The following
+ * panic messages can be generated:
+ * - SV#1, misplaced @p chSysDisable().
+ * - Called from an ISR.
+ * - Called from a critical zone.
+ * .
+ * - SV#2, misplaced @p chSysSuspend()
+ * - Called from an ISR.
+ * - Called from a critical zone.
+ * .
+ * - SV#3, misplaced @p chSysEnable().
+ * - Called from an ISR.
+ * - Called from a critical zone.
+ * .
+ * - SV#4, misplaced @p chSysLock().
+ * - Called from an ISR.
+ * - Called from a critical zone.
+ * .
+ * - SV#5, misplaced @p chSysUnlock().
+ * - Called from an ISR.
+ * - Not called from a critical zone.
+ * .
+ * - SV#6, misplaced @p chSysLockFromISR().
+ * - Not called from an ISR.
+ * - Called from a critical zone.
+ * .
+ * - SV#7, misplaced @p chSysUnlockFromISR().
+ * - Not called from an ISR.
+ * - Not called from a critical zone.
+ * .
+ * - SV#8, misplaced @p CH_IRQ_PROLOGUE().
+ * - Not called at ISR begin.
+ * - Called from a critical zone.
+ * .
+ * - SV#9, misplaced @p CH_IRQ_EPILOGUE().
+ * - @p CH_IRQ_PROLOGUE() missing.
+ * - Not called at ISR end.
+ * - Called from a critical zone.
+ * .
+ * - SV#10, misplaced I-class function.
+ * - I-class function not called from within a critical zone.
+ * .
+ * - SV#11, misplaced S-class function.
+ * - S-class function not called from within a critical zone.
+ * - Called from an ISR.
+ * .
+ * - Trace buffer.
+ * - Parameters check.
+ * - Kernel assertions.
+ * - Kernel panics.
+ * .
+ * @note Stack checks are not implemented in this module but in the port
+ * layer in an architecture-dependent way.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+#if (CH_DBG_SYSTEM_STATE_CHECK == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Guard code for @p chSysDisable().
+ *
+ * @notapi
+ */
+void _dbg_check_disable(void) {
+
+ if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) {
+ chSysHalt("SV#1");
+ }
+}
+
+/**
+ * @brief Guard code for @p chSysSuspend().
+ *
+ * @notapi
+ */
+void _dbg_check_suspend(void) {
+
+ if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) {
+ chSysHalt("SV#2");
+ }
+}
+
+/**
+ * @brief Guard code for @p chSysEnable().
+ *
+ * @notapi
+ */
+void _dbg_check_enable(void) {
+
+ if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) {
+ chSysHalt("SV#3");
+ }
+}
+
+/**
+ * @brief Guard code for @p chSysLock().
+ *
+ * @notapi
+ */
+void _dbg_check_lock(void) {
+
+ if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) {
+ chSysHalt("SV#4");
+ }
+ _dbg_enter_lock();
+}
+
+/**
+ * @brief Guard code for @p chSysUnlock().
+ *
+ * @notapi
+ */
+void _dbg_check_unlock(void) {
+
+ if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt <= (cnt_t)0)) {
+ chSysHalt("SV#5");
+ }
+ _dbg_leave_lock();
+}
+
+/**
+ * @brief Guard code for @p chSysLockFromIsr().
+ *
+ * @notapi
+ */
+void _dbg_check_lock_from_isr(void) {
+
+ if ((ch.dbg.isr_cnt <= (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) {
+ chSysHalt("SV#6");
+ }
+ _dbg_enter_lock();
+}
+
+/**
+ * @brief Guard code for @p chSysUnlockFromIsr().
+ *
+ * @notapi
+ */
+void _dbg_check_unlock_from_isr(void) {
+
+ if ((ch.dbg.isr_cnt <= (cnt_t)0) || (ch.dbg.lock_cnt <= (cnt_t)0)) {
+ chSysHalt("SV#7");
+ }
+ _dbg_leave_lock();
+}
+
+/**
+ * @brief Guard code for @p CH_IRQ_PROLOGUE().
+ *
+ * @notapi
+ */
+void _dbg_check_enter_isr(void) {
+
+ port_lock_from_isr();
+ if ((ch.dbg.isr_cnt < (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) {
+ chSysHalt("SV#8");
+ }
+ ch.dbg.isr_cnt++;
+ port_unlock_from_isr();
+}
+
+/**
+ * @brief Guard code for @p CH_IRQ_EPILOGUE().
+ *
+ * @notapi
+ */
+void _dbg_check_leave_isr(void) {
+
+ port_lock_from_isr();
+ if ((ch.dbg.isr_cnt <= (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) {
+ chSysHalt("SV#9");
+ }
+ ch.dbg.isr_cnt--;
+ port_unlock_from_isr();
+}
+
+/**
+ * @brief I-class functions context check.
+ * @details Verifies that the system is in an appropriate state for invoking
+ * an I-class API function. A panic is generated if the state is
+ * not compatible.
+ *
+ * @api
+ */
+void chDbgCheckClassI(void) {
+
+ if ((ch.dbg.isr_cnt < (cnt_t)0) || (ch.dbg.lock_cnt <= (cnt_t)0)) {
+ chSysHalt("SV#10");
+ }
+}
+
+/**
+ * @brief S-class functions context check.
+ * @details Verifies that the system is in an appropriate state for invoking
+ * an S-class API function. A panic is generated if the state is
+ * not compatible.
+ *
+ * @api
+ */
+void chDbgCheckClassS(void) {
+
+ if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt <= (cnt_t)0)) {
+ chSysHalt("SV#11");
+ }
+}
+
+#endif /* CH_DBG_SYSTEM_STATE_CHECK == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chdynamic.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chdynamic.c
new file mode 100644
index 0000000000..c9ae11b134
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chdynamic.c
@@ -0,0 +1,185 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chdynamic.c
+ * @brief Dynamic threads code.
+ *
+ * @addtogroup dynamic_threads
+ * @details Dynamic threads related APIs and services.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_CFG_USE_DYNAMIC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+#if (CH_CFG_USE_HEAP == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Creates a new thread allocating the memory from the heap.
+ * @pre The configuration options @p CH_CFG_USE_DYNAMIC and
+ * @p CH_CFG_USE_HEAP must be enabled in order to use this function.
+ * @note A thread can terminate by calling @p chThdExit() or by simply
+ * returning from its main function.
+ * @note The memory allocated for the thread is not released automatically,
+ * it is responsibility of the creator thread to call @p chThdWait()
+ * and then release the allocated memory.
+ *
+ * @param[in] heapp heap from which allocate the memory or @p NULL for the
+ * default heap
+ * @param[in] size size of the working area to be allocated
+ * @param[in] name thread name
+ * @param[in] prio the priority level for the new thread
+ * @param[in] pf the thread function
+ * @param[in] arg an argument passed to the thread function. It can be
+ * @p NULL.
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ * @retval NULL if the memory cannot be allocated.
+ *
+ * @api
+ */
+thread_t *chThdCreateFromHeap(memory_heap_t *heapp, size_t size,
+ const char *name, tprio_t prio,
+ tfunc_t pf, void *arg) {
+ thread_t *tp;
+ void *wsp;
+
+ wsp = chHeapAllocAligned(heapp, size, PORT_WORKING_AREA_ALIGN);
+ if (wsp == NULL) {
+ return NULL;
+ }
+
+ thread_descriptor_t td = {
+ name,
+ wsp,
+ (stkalign_t *)((uint8_t *)wsp + size),
+ prio,
+ pf,
+ arg
+ };
+
+#if CH_DBG_FILL_THREADS == TRUE
+ _thread_memfill((uint8_t *)wsp,
+ (uint8_t *)wsp + size,
+ CH_DBG_STACK_FILL_VALUE);
+#endif
+
+ chSysLock();
+ tp = chThdCreateSuspendedI(&td);
+ tp->flags = CH_FLAG_MODE_HEAP;
+ chSchWakeupS(tp, MSG_OK);
+ chSysUnlock();
+
+ return tp;
+}
+#endif /* CH_CFG_USE_HEAP == TRUE */
+
+#if (CH_CFG_USE_MEMPOOLS == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Creates a new thread allocating the memory from the specified
+ * memory pool.
+ * @pre The configuration options @p CH_CFG_USE_DYNAMIC and
+ * @p CH_CFG_USE_MEMPOOLS must be enabled in order to use this
+ * function.
+ * @pre The pool must be initialized to contain only objects with
+ * alignment @p PORT_WORKING_AREA_ALIGN.
+ * @note A thread can terminate by calling @p chThdExit() or by simply
+ * returning from its main function.
+ * @note The memory allocated for the thread is not released automatically,
+ * it is responsibility of the creator thread to call @p chThdWait()
+ * and then release the allocated memory.
+ *
+ * @param[in] mp pointer to the memory pool object
+ * @param[in] name thread name
+ * @param[in] prio the priority level for the new thread
+ * @param[in] pf the thread function
+ * @param[in] arg an argument passed to the thread function. It can be
+ * @p NULL.
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ * @retval NULL if the memory pool is empty.
+ *
+ * @api
+ */
+thread_t *chThdCreateFromMemoryPool(memory_pool_t *mp, const char *name,
+ tprio_t prio, tfunc_t pf, void *arg) {
+ thread_t *tp;
+ void *wsp;
+
+ chDbgCheck(mp != NULL);
+
+ wsp = chPoolAlloc(mp);
+ if (wsp == NULL) {
+ return NULL;
+ }
+
+ thread_descriptor_t td = {
+ name,
+ wsp,
+ (stkalign_t *)((uint8_t *)wsp + mp->object_size),
+ prio,
+ pf,
+ arg
+ };
+
+#if CH_DBG_FILL_THREADS == TRUE
+ _thread_memfill((uint8_t *)wsp,
+ (uint8_t *)wsp + mp->object_size,
+ CH_DBG_STACK_FILL_VALUE);
+#endif
+
+ chSysLock();
+ tp = chThdCreateSuspendedI(&td);
+ tp->flags = CH_FLAG_MODE_MPOOL;
+ tp->mpool = mp;
+ chSchWakeupS(tp, MSG_OK);
+ chSysUnlock();
+
+ return tp;
+}
+#endif /* CH_CFG_USE_MEMPOOLS == TRUE */
+
+#endif /* CH_CFG_USE_DYNAMIC == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chevents.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chevents.c
new file mode 100644
index 0000000000..b974ccb677
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chevents.c
@@ -0,0 +1,587 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+/*
+ Concepts and parts of this file have been contributed by Scott (skute).
+ */
+
+/**
+ * @file chevents.c
+ * @brief Events code.
+ *
+ * @addtogroup events
+ * @details Event Flags, Event Sources and Event Listeners.
+ * Operation mode
+ * Each thread has a mask of pending events inside its
+ * @p thread_t structure.
+ * Operations defined for events:
+ * - Wait, the invoking thread goes to sleep until a certain
+ * AND/OR combination of events become pending.
+ * - Clear, a mask of events is cleared from the pending
+ * events, the cleared events mask is returned (only the
+ * events that were actually pending and then cleared).
+ * - Signal, an events mask is directly ORed to the mask of the
+ * signaled thread.
+ * - Broadcast, each thread registered on an Event Source is
+ * signaled with the events specified in its Event Listener.
+ * - Dispatch, an events mask is scanned and for each bit set
+ * to one an associated handler function is invoked. Bit masks are
+ * scanned from bit zero upward.
+ * .
+ * An Event Source is a special object that can be "broadcasted" by
+ * a thread or an interrupt service routine. Broadcasting an Event
+ * Source has the effect that all the threads registered on the
+ * Event Source will be signaled with an events mask.
+ * An unlimited number of Event Sources can exists in a system and
+ * each thread can be listening on an unlimited number of
+ * them.
+ * @pre In order to use the Events APIs the @p CH_CFG_USE_EVENTS option must be
+ * enabled in @p chconf.h.
+ * @post Enabling events requires 1-4 (depending on the architecture)
+ * extra bytes in the @p thread_t structure.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Registers an Event Listener on an Event Source.
+ * @details Once a thread has registered as listener on an event source it
+ * will be notified of all events broadcasted there.
+ * @note Multiple Event Listeners can specify the same bits to be ORed to
+ * different threads.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ * @param[in] elp pointer to the @p event_listener_t structure
+ * @param[in] events events to be ORed to the thread when
+ * the event source is broadcasted
+ * @param[in] wflags mask of flags the listening thread is interested in
+ *
+ * @api
+ */
+void chEvtRegisterMaskWithFlags(event_source_t *esp,
+ event_listener_t *elp,
+ eventmask_t events,
+ eventflags_t wflags) {
+
+ chDbgCheck((esp != NULL) && (elp != NULL));
+
+ chSysLock();
+ elp->next = esp->next;
+ esp->next = elp;
+ elp->listener = currp;
+ elp->events = events;
+ elp->flags = (eventflags_t)0;
+ elp->wflags = wflags;
+ chSysUnlock();
+}
+
+/**
+ * @brief Unregisters an Event Listener from its Event Source.
+ * @note If the event listener is not registered on the specified event
+ * source then the function does nothing.
+ * @note For optimal performance it is better to perform the unregister
+ * operations in inverse order of the register operations (elements
+ * are found on top of the list).
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ * @param[in] elp pointer to the @p event_listener_t structure
+ *
+ * @api
+ */
+void chEvtUnregister(event_source_t *esp, event_listener_t *elp) {
+ event_listener_t *p;
+
+ chDbgCheck((esp != NULL) && (elp != NULL));
+
+ /*lint -save -e9087 -e740 [11.3, 1.3] Cast required by list handling.*/
+ p = (event_listener_t *)esp;
+ /*lint -restore*/
+ chSysLock();
+ /*lint -save -e9087 -e740 [11.3, 1.3] Cast required by list handling.*/
+ while (p->next != (event_listener_t *)esp) {
+ /*lint -restore*/
+ if (p->next == elp) {
+ p->next = elp->next;
+ break;
+ }
+ p = p->next;
+ }
+ chSysUnlock();
+}
+
+/**
+ * @brief Clears the pending events specified in the events mask.
+ *
+ * @param[in] events the events to be cleared
+ * @return The mask of pending events that were cleared.
+ *
+ * @api
+ */
+eventmask_t chEvtGetAndClearEvents(eventmask_t events) {
+ eventmask_t m;
+
+ chSysLock();
+ m = currp->epending & events;
+ currp->epending &= ~events;
+ chSysUnlock();
+
+ return m;
+}
+
+/**
+ * @brief Adds (OR) a set of events to the current thread, this is
+ * @b much faster than using @p chEvtBroadcast() or @p chEvtSignal().
+ *
+ * @param[in] events the events to be added
+ * @return The mask of currently pending events.
+ *
+ * @api
+ */
+eventmask_t chEvtAddEvents(eventmask_t events) {
+
+ chSysLock();
+ currp->epending |= events;
+ events = currp->epending;
+ chSysUnlock();
+
+ return events;
+}
+
+/**
+ * @brief Signals all the Event Listeners registered on the specified Event
+ * Source.
+ * @details This function variants ORs the specified event flags to all the
+ * threads registered on the @p event_source_t in addition to the
+ * event flags specified by the threads themselves in the
+ * @p event_listener_t objects.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ * @param[in] flags the flags set to be added to the listener flags mask
+ *
+ * @iclass
+ */
+void chEvtBroadcastFlagsI(event_source_t *esp, eventflags_t flags) {
+ event_listener_t *elp;
+
+ chDbgCheckClassI();
+ chDbgCheck(esp != NULL);
+
+ elp = esp->next;
+ /*lint -save -e9087 -e740 [11.3, 1.3] Cast required by list handling.*/
+ while (elp != (event_listener_t *)esp) {
+ /*lint -restore*/
+ elp->flags |= flags;
+ /* When flags == 0 the thread will always be signaled because the
+ source does not emit any flag.*/
+ if ((flags == (eventflags_t)0) ||
+ ((elp->flags & elp->wflags) != (eventflags_t)0)) {
+ chEvtSignalI(elp->listener, elp->events);
+ }
+ elp = elp->next;
+ }
+}
+
+/**
+ * @brief Returns the flags associated to an @p event_listener_t.
+ * @details The flags are returned and the @p event_listener_t flags mask is
+ * cleared.
+ *
+ * @param[in] elp pointer to the @p event_listener_t structure
+ * @return The flags added to the listener by the associated
+ * event source.
+ *
+ * @api
+ */
+eventflags_t chEvtGetAndClearFlags(event_listener_t *elp) {
+ eventflags_t flags;
+
+ chSysLock();
+ flags = elp->flags;
+ elp->flags = (eventflags_t)0;
+ chSysUnlock();
+
+ return flags;
+}
+
+/**
+ * @brief Adds a set of event flags directly to the specified @p thread_t.
+ *
+ * @param[in] tp the thread to be signaled
+ * @param[in] events the events set to be ORed
+ *
+ * @api
+ */
+void chEvtSignal(thread_t *tp, eventmask_t events) {
+
+ chDbgCheck(tp != NULL);
+
+ chSysLock();
+ chEvtSignalI(tp, events);
+ chSchRescheduleS();
+ chSysUnlock();
+}
+
+/**
+ * @brief Adds a set of event flags directly to the specified @p thread_t.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] tp the thread to be signaled
+ * @param[in] events the events set to be ORed
+ *
+ * @iclass
+ */
+void chEvtSignalI(thread_t *tp, eventmask_t events) {
+
+ chDbgCheckClassI();
+ chDbgCheck(tp != NULL);
+
+ tp->epending |= events;
+ /* Test on the AND/OR conditions wait states.*/
+ if (((tp->state == CH_STATE_WTOREVT) &&
+ ((tp->epending & tp->u.ewmask) != (eventmask_t)0)) ||
+ ((tp->state == CH_STATE_WTANDEVT) &&
+ ((tp->epending & tp->u.ewmask) == tp->u.ewmask))) {
+ tp->u.rdymsg = MSG_OK;
+ (void) chSchReadyI(tp);
+ }
+}
+
+/**
+ * @brief Signals all the Event Listeners registered on the specified Event
+ * Source.
+ * @details This function variants ORs the specified event flags to all the
+ * threads registered on the @p event_source_t in addition to the
+ * event flags specified by the threads themselves in the
+ * @p event_listener_t objects.
+ *
+ * @param[in] esp pointer to the @p event_source_t structure
+ * @param[in] flags the flags set to be added to the listener flags mask
+ *
+ * @api
+ */
+void chEvtBroadcastFlags(event_source_t *esp, eventflags_t flags) {
+
+ chSysLock();
+ chEvtBroadcastFlagsI(esp, flags);
+ chSchRescheduleS();
+ chSysUnlock();
+}
+
+/**
+ * @brief Returns the flags associated to an @p event_listener_t.
+ * @details The flags are returned and the @p event_listener_t flags mask is
+ * cleared.
+ *
+ * @param[in] elp pointer to the @p event_listener_t structure
+ * @return The flags added to the listener by the associated
+ * event source.
+ *
+ * @iclass
+ */
+eventflags_t chEvtGetAndClearFlagsI(event_listener_t *elp) {
+ eventflags_t flags;
+
+ flags = elp->flags;
+ elp->flags = (eventflags_t)0;
+
+ return flags;
+}
+
+/**
+ * @brief Invokes the event handlers associated to an event flags mask.
+ *
+ * @param[in] events mask of events to be dispatched
+ * @param[in] handlers an array of @p evhandler_t. The array must have size
+ * equal to the number of bits in eventmask_t.
+ *
+ * @api
+ */
+void chEvtDispatch(const evhandler_t *handlers, eventmask_t events) {
+ eventid_t eid;
+
+ chDbgCheck(handlers != NULL);
+
+ eid = (eventid_t)0;
+ while (events != (eventmask_t)0) {
+ if ((events & EVENT_MASK(eid)) != (eventmask_t)0) {
+ chDbgAssert(handlers[eid] != NULL, "null handler");
+ events &= ~EVENT_MASK(eid);
+ handlers[eid](eid);
+ }
+ eid++;
+ }
+}
+
+#if (CH_CFG_OPTIMIZE_SPEED == TRUE) || \
+ (CH_CFG_USE_EVENTS_TIMEOUT == FALSE) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief Waits for exactly one of the specified events.
+ * @details The function waits for one event among those specified in
+ * @p events to become pending then the event is cleared and returned.
+ * @note One and only one event is served in the function, the one with the
+ * lowest event id. The function is meant to be invoked into a loop in
+ * order to serve all the pending events.
+ * This means that Event Listeners with a lower event identifier have
+ * an higher priority.
+ *
+ * @param[in] events events that the function should wait
+ * for, @p ALL_EVENTS enables all the events
+ * @return The mask of the lowest event id served and cleared.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitOne(eventmask_t events) {
+ thread_t *ctp = currp;
+ eventmask_t m;
+
+ chSysLock();
+ m = ctp->epending & events;
+ if (m == (eventmask_t)0) {
+ ctp->u.ewmask = events;
+ chSchGoSleepS(CH_STATE_WTOREVT);
+ m = ctp->epending & events;
+ }
+ m ^= m & (m - (eventmask_t)1);
+ ctp->epending &= ~m;
+ chSysUnlock();
+
+ return m;
+}
+
+/**
+ * @brief Waits for any of the specified events.
+ * @details The function waits for any event among those specified in
+ * @p events to become pending then the events are cleared and
+ * returned.
+ *
+ * @param[in] events events that the function should wait
+ * for, @p ALL_EVENTS enables all the events
+ * @return The mask of the served and cleared events.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAny(eventmask_t events) {
+ thread_t *ctp = currp;
+ eventmask_t m;
+
+ chSysLock();
+ m = ctp->epending & events;
+ if (m == (eventmask_t)0) {
+ ctp->u.ewmask = events;
+ chSchGoSleepS(CH_STATE_WTOREVT);
+ m = ctp->epending & events;
+ }
+ ctp->epending &= ~m;
+ chSysUnlock();
+
+ return m;
+}
+
+/**
+ * @brief Waits for all the specified events.
+ * @details The function waits for all the events specified in @p events to
+ * become pending then the events are cleared and returned.
+ *
+ * @param[in] events events that the function should wait
+ * for, @p ALL_EVENTS requires all the events
+ * @return The mask of the served and cleared events.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAll(eventmask_t events) {
+ thread_t *ctp = currp;
+
+ chSysLock();
+ if ((ctp->epending & events) != events) {
+ ctp->u.ewmask = events;
+ chSchGoSleepS(CH_STATE_WTANDEVT);
+ }
+ ctp->epending &= ~events;
+ chSysUnlock();
+
+ return events;
+}
+#endif /* CH_CFG_OPTIMIZE_SPEED || !CH_CFG_USE_EVENTS_TIMEOUT */
+
+#if (CH_CFG_USE_EVENTS_TIMEOUT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Waits for exactly one of the specified events.
+ * @details The function waits for one event among those specified in
+ * @p events to become pending then the event is cleared and returned.
+ * @note One and only one event is served in the function, the one with the
+ * lowest event id. The function is meant to be invoked into a loop
+ * in order to serve all the pending events.
+ * This means that Event Listeners with a lower event identifier have
+ * an higher priority.
+ *
+ * @param[in] events events that the function should wait
+ * for, @p ALL_EVENTS enables all the events
+ * @param[in] time the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The mask of the lowest event id served and cleared.
+ * @retval 0 if the operation has timed out.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitOneTimeout(eventmask_t events, systime_t time) {
+ thread_t *ctp = currp;
+ eventmask_t m;
+
+ chSysLock();
+ m = ctp->epending & events;
+ if (m == (eventmask_t)0) {
+ if (TIME_IMMEDIATE == time) {
+ chSysUnlock();
+ return (eventmask_t)0;
+ }
+ ctp->u.ewmask = events;
+ if (chSchGoSleepTimeoutS(CH_STATE_WTOREVT, time) < MSG_OK) {
+ chSysUnlock();
+ return (eventmask_t)0;
+ }
+ m = ctp->epending & events;
+ }
+ m ^= m & (m - (eventmask_t)1);
+ ctp->epending &= ~m;
+ chSysUnlock();
+
+ return m;
+}
+
+/**
+ * @brief Waits for any of the specified events.
+ * @details The function waits for any event among those specified in
+ * @p events to become pending then the events are cleared and
+ * returned.
+ *
+ * @param[in] events events that the function should wait
+ * for, @p ALL_EVENTS enables all the events
+ * @param[in] time the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The mask of the served and cleared events.
+ * @retval 0 if the operation has timed out.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAnyTimeout(eventmask_t events, systime_t time) {
+ thread_t *ctp = currp;
+ eventmask_t m;
+
+ chSysLock();
+ m = ctp->epending & events;
+ if (m == (eventmask_t)0) {
+ if (TIME_IMMEDIATE == time) {
+ chSysUnlock();
+ return (eventmask_t)0;
+ }
+ ctp->u.ewmask = events;
+ if (chSchGoSleepTimeoutS(CH_STATE_WTOREVT, time) < MSG_OK) {
+ chSysUnlock();
+ return (eventmask_t)0;
+ }
+ m = ctp->epending & events;
+ }
+ ctp->epending &= ~m;
+ chSysUnlock();
+
+ return m;
+}
+
+/**
+ * @brief Waits for all the specified events.
+ * @details The function waits for all the events specified in @p events to
+ * become pending then the events are cleared and returned.
+ *
+ * @param[in] events events that the function should wait
+ * for, @p ALL_EVENTS requires all the events
+ * @param[in] time the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The mask of the served and cleared events.
+ * @retval 0 if the operation has timed out.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAllTimeout(eventmask_t events, systime_t time) {
+ thread_t *ctp = currp;
+
+ chSysLock();
+ if ((ctp->epending & events) != events) {
+ if (TIME_IMMEDIATE == time) {
+ chSysUnlock();
+ return (eventmask_t)0;
+ }
+ ctp->u.ewmask = events;
+ if (chSchGoSleepTimeoutS(CH_STATE_WTANDEVT, time) < MSG_OK) {
+ chSysUnlock();
+ return (eventmask_t)0;
+ }
+ }
+ ctp->epending &= ~events;
+ chSysUnlock();
+
+ return events;
+}
+#endif /* CH_CFG_USE_EVENTS_TIMEOUT == TRUE */
+
+#endif /* CH_CFG_USE_EVENTS == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmsg.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chmsg.c
similarity index 56%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmsg.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chmsg.c
index e18c09633c..455541e7e7 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chmsg.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chmsg.c
@@ -1,28 +1,20 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
- This file is part of ChibiOS/RT.
+ This file is part of ChibiOS.
- ChibiOS/RT is free software; you can redistribute it and/or modify
+ ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
- ChibiOS/RT is distributed in the hope that it will be useful,
+ ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
*/
/**
@@ -43,24 +35,44 @@
* architectures function pointers can be larger that @p msg_t.
* Messages are usually processed in FIFO order but it is possible to
* process them in priority order by enabling the
- * @p CH_USE_MESSAGES_PRIORITY option in @p chconf.h.
- * @pre In order to use the message APIs the @p CH_USE_MESSAGES option
+ * @p CH_CFG_USE_MESSAGES_PRIORITY option in @p chconf.h.
+ * @pre In order to use the message APIs the @p CH_CFG_USE_MESSAGES option
* must be enabled in @p chconf.h.
* @post Enabling messages requires 6-12 (depending on the architecture)
- * extra bytes in the @p Thread structure.
+ * extra bytes in the @p thread_t structure.
* @{
*/
#include "ch.h"
-#if CH_USE_MESSAGES || defined(__DOXYGEN__)
+#if (CH_CFG_USE_MESSAGES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
-#if CH_USE_MESSAGES_PRIORITY
-#define msg_insert(tp, qp) prio_insert(tp, qp)
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+#if CH_CFG_USE_MESSAGES_PRIORITY == TRUE
+#define msg_insert(tp, qp) queue_prio_insert(tp, qp)
#else
#define msg_insert(tp, qp) queue_insert(tp, qp)
#endif
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
/**
* @brief Sends a message to the specified thread.
* @details The sender is stopped until the receiver executes a
@@ -72,20 +84,21 @@
*
* @api
*/
-msg_t chMsgSend(Thread *tp, msg_t msg) {
- Thread *ctp = currp;
+msg_t chMsgSend(thread_t *tp, msg_t msg) {
+ thread_t *ctp = currp;
- chDbgCheck(tp != NULL, "chMsgSend");
+ chDbgCheck(tp != NULL);
chSysLock();
- ctp->p_msg = msg;
- ctp->p_u.wtobjp = &tp->p_msgqueue;
- msg_insert(ctp, &tp->p_msgqueue);
- if (tp->p_state == THD_STATE_WTMSG)
- chSchReadyI(tp);
- chSchGoSleepS(THD_STATE_SNDMSGQ);
- msg = ctp->p_u.rdymsg;
+ ctp->u.sentmsg = msg;
+ msg_insert(ctp, &tp->msgqueue);
+ if (tp->state == CH_STATE_WTMSG) {
+ (void) chSchReadyI(tp);
+ }
+ chSchGoSleepS(CH_STATE_SNDMSGQ);
+ msg = ctp->u.rdymsg;
chSysUnlock();
+
return msg;
}
@@ -103,15 +116,17 @@ msg_t chMsgSend(Thread *tp, msg_t msg) {
*
* @api
*/
-Thread *chMsgWait(void) {
- Thread *tp;
+thread_t *chMsgWait(void) {
+ thread_t *tp;
chSysLock();
- if (!chMsgIsPendingI(currp))
- chSchGoSleepS(THD_STATE_WTMSG);
- tp = fifo_remove(&currp->p_msgqueue);
- tp->p_state = THD_STATE_SNDMSG;
+ if (!chMsgIsPendingI(currp)) {
+ chSchGoSleepS(CH_STATE_WTMSG);
+ }
+ tp = queue_fifo_remove(&currp->msgqueue);
+ tp->state = CH_STATE_SNDMSG;
chSysUnlock();
+
return tp;
}
@@ -125,15 +140,14 @@ Thread *chMsgWait(void) {
*
* @api
*/
-void chMsgRelease(Thread *tp, msg_t msg) {
+void chMsgRelease(thread_t *tp, msg_t msg) {
chSysLock();
- chDbgAssert(tp->p_state == THD_STATE_SNDMSG,
- "chMsgRelease(), #1", "invalid state");
+ chDbgAssert(tp->state == CH_STATE_SNDMSG, "invalid state");
chMsgReleaseS(tp, msg);
chSysUnlock();
}
-#endif /* CH_USE_MESSAGES */
+#endif /* CH_CFG_USE_MESSAGES == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chmtx.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chmtx.c
new file mode 100644
index 0000000000..add646c7ce
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chmtx.c
@@ -0,0 +1,557 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chmtx.c
+ * @brief Mutexes code.
+ *
+ * @addtogroup mutexes
+ * @details Mutexes related APIs and services.
+ * Operation mode
+ * A mutex is a threads synchronization object that can be in two
+ * distinct states:
+ * - Not owned (unlocked).
+ * - Owned by a thread (locked).
+ * .
+ * Operations defined for mutexes:
+ * - Lock: The mutex is checked, if the mutex is not owned by
+ * some other thread then it is associated to the locking thread
+ * else the thread is queued on the mutex in a list ordered by
+ * priority.
+ * - Unlock: The mutex is released by the owner and the highest
+ * priority thread waiting in the queue, if any, is resumed and made
+ * owner of the mutex.
+ * .
+ * Constraints
+ * In ChibiOS/RT the Unlock operations must always be performed
+ * in lock-reverse order. This restriction both improves the
+ * performance and is required for an efficient implementation
+ * of the priority inheritance mechanism.
+ * Operating under this restriction also ensures that deadlocks
+ * are no possible.
+ *
+ * Recursive mode
+ * By default mutexes are not recursive, this mean that it is not
+ * possible to take a mutex already owned by the same thread.
+ * It is possible to enable the recursive behavior by enabling the
+ * option @p CH_CFG_USE_MUTEXES_RECURSIVE.
+ *
+ * The priority inversion problem
+ * The mutexes in ChibiOS/RT implements the full priority
+ * inheritance mechanism in order handle the priority inversion
+ * problem.
+ * When a thread is queued on a mutex, any thread, directly or
+ * indirectly, holding the mutex gains the same priority of the
+ * waiting thread (if their priority was not already equal or higher).
+ * The mechanism works with any number of nested mutexes and any
+ * number of involved threads. The algorithm complexity (worst case)
+ * is N with N equal to the number of nested mutexes.
+ * @pre In order to use the mutex APIs the @p CH_CFG_USE_MUTEXES option
+ * must be enabled in @p chconf.h.
+ * @post Enabling mutexes requires 5-12 (depending on the architecture)
+ * extra bytes in the @p thread_t structure.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes s @p mutex_t structure.
+ *
+ * @param[out] mp pointer to a @p mutex_t structure
+ *
+ * @init
+ */
+void chMtxObjectInit(mutex_t *mp) {
+
+ chDbgCheck(mp != NULL);
+
+ queue_init(&mp->queue);
+ mp->owner = NULL;
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ mp->cnt = (cnt_t)0;
+#endif
+}
+
+/**
+ * @brief Locks the specified mutex.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ *
+ * @param[in] mp pointer to the @p mutex_t structure
+ *
+ * @api
+ */
+void chMtxLock(mutex_t *mp) {
+
+ chSysLock();
+ chMtxLockS(mp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Locks the specified mutex.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ *
+ * @param[in] mp pointer to the @p mutex_t structure
+ *
+ * @sclass
+ */
+void chMtxLockS(mutex_t *mp) {
+ thread_t *ctp = currp;
+
+ chDbgCheckClassS();
+ chDbgCheck(mp != NULL);
+
+ /* Is the mutex already locked? */
+ if (mp->owner != NULL) {
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+
+ chDbgAssert(mp->cnt >= (cnt_t)1, "counter is not positive");
+
+ /* If the mutex is already owned by this thread, the counter is increased
+ and there is no need of more actions.*/
+ if (mp->owner == ctp) {
+ mp->cnt++;
+ }
+ else {
+#endif
+ /* Priority inheritance protocol; explores the thread-mutex dependencies
+ boosting the priority of all the affected threads to equal the
+ priority of the running thread requesting the mutex.*/
+ thread_t *tp = mp->owner;
+
+ /* Does the running thread have higher priority than the mutex
+ owning thread? */
+ while (tp->prio < ctp->prio) {
+ /* Make priority of thread tp match the running thread's priority.*/
+ tp->prio = ctp->prio;
+
+ /* The following states need priority queues reordering.*/
+ switch (tp->state) {
+ case CH_STATE_WTMTX:
+ /* Re-enqueues the mutex owner with its new priority.*/
+ queue_prio_insert(queue_dequeue(tp), &tp->u.wtmtxp->queue);
+ tp = tp->u.wtmtxp->owner;
+ /*lint -e{9042} [16.1] Continues the while.*/
+ continue;
+#if (CH_CFG_USE_CONDVARS == TRUE) || \
+ ((CH_CFG_USE_SEMAPHORES == TRUE) && \
+ (CH_CFG_USE_SEMAPHORES_PRIORITY == TRUE)) || \
+ ((CH_CFG_USE_MESSAGES == TRUE) && \
+ (CH_CFG_USE_MESSAGES_PRIORITY == TRUE))
+#if CH_CFG_USE_CONDVARS == TRUE
+ case CH_STATE_WTCOND:
+#endif
+#if (CH_CFG_USE_SEMAPHORES == TRUE) && \
+ (CH_CFG_USE_SEMAPHORES_PRIORITY == TRUE)
+ case CH_STATE_WTSEM:
+#endif
+#if (CH_CFG_USE_MESSAGES == TRUE) && (CH_CFG_USE_MESSAGES_PRIORITY == TRUE)
+ case CH_STATE_SNDMSGQ:
+#endif
+ /* Re-enqueues tp with its new priority on the queue.*/
+ queue_prio_insert(queue_dequeue(tp), &tp->u.wtmtxp->queue);
+ break;
+#endif
+ case CH_STATE_READY:
+#if CH_DBG_ENABLE_ASSERTS == TRUE
+ /* Prevents an assertion in chSchReadyI().*/
+ tp->state = CH_STATE_CURRENT;
+#endif
+ /* Re-enqueues tp with its new priority on the ready list.*/
+ (void) chSchReadyI(queue_dequeue(tp));
+ break;
+ default:
+ /* Nothing to do for other states.*/
+ break;
+ }
+ break;
+ }
+
+ /* Sleep on the mutex.*/
+ queue_prio_insert(ctp, &mp->queue);
+ ctp->u.wtmtxp = mp;
+ chSchGoSleepS(CH_STATE_WTMTX);
+
+ /* It is assumed that the thread performing the unlock operation assigns
+ the mutex to this thread.*/
+ chDbgAssert(mp->owner == ctp, "not owner");
+ chDbgAssert(ctp->mtxlist == mp, "not owned");
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ chDbgAssert(mp->cnt == (cnt_t)1, "counter is not one");
+ }
+#endif
+ }
+ else {
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ chDbgAssert(mp->cnt == (cnt_t)0, "counter is not zero");
+
+ mp->cnt++;
+#endif
+ /* It was not owned, inserted in the owned mutexes list.*/
+ mp->owner = ctp;
+ mp->next = ctp->mtxlist;
+ ctp->mtxlist = mp;
+ }
+}
+
+/**
+ * @brief Tries to lock a mutex.
+ * @details This function attempts to lock a mutex, if the mutex is already
+ * locked by another thread then the function exits without waiting.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ * @note This function does not have any overhead related to the
+ * priority inheritance mechanism because it does not try to
+ * enter a sleep state.
+ *
+ * @param[in] mp pointer to the @p mutex_t structure
+ * @return The operation status.
+ * @retval true if the mutex has been successfully acquired
+ * @retval false if the lock attempt failed.
+ *
+ * @api
+ */
+bool chMtxTryLock(mutex_t *mp) {
+ bool b;
+
+ chSysLock();
+ b = chMtxTryLockS(mp);
+ chSysUnlock();
+
+ return b;
+}
+
+/**
+ * @brief Tries to lock a mutex.
+ * @details This function attempts to lock a mutex, if the mutex is already
+ * taken by another thread then the function exits without waiting.
+ * @post The mutex is locked and inserted in the per-thread stack of owned
+ * mutexes.
+ * @note This function does not have any overhead related to the
+ * priority inheritance mechanism because it does not try to
+ * enter a sleep state.
+ *
+ * @param[in] mp pointer to the @p mutex_t structure
+ * @return The operation status.
+ * @retval true if the mutex has been successfully acquired
+ * @retval false if the lock attempt failed.
+ *
+ * @sclass
+ */
+bool chMtxTryLockS(mutex_t *mp) {
+
+ chDbgCheckClassS();
+ chDbgCheck(mp != NULL);
+
+ if (mp->owner != NULL) {
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+
+ chDbgAssert(mp->cnt >= (cnt_t)1, "counter is not positive");
+
+ if (mp->owner == currp) {
+ mp->cnt++;
+ return true;
+ }
+#endif
+ return false;
+ }
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+
+ chDbgAssert(mp->cnt == (cnt_t)0, "counter is not zero");
+
+ mp->cnt++;
+#endif
+ mp->owner = currp;
+ mp->next = currp->mtxlist;
+ currp->mtxlist = mp;
+ return true;
+}
+
+/**
+ * @brief Unlocks the specified mutex.
+ * @note Mutexes must be unlocked in reverse lock order. Violating this
+ * rules will result in a panic if assertions are enabled.
+ * @pre The invoking thread must have at least one owned mutex.
+ * @post The mutex is unlocked and removed from the per-thread stack of
+ * owned mutexes.
+ *
+ * @param[in] mp pointer to the @p mutex_t structure
+ *
+ * @api
+ */
+void chMtxUnlock(mutex_t *mp) {
+ thread_t *ctp = currp;
+ mutex_t *lmp;
+
+ chDbgCheck(mp != NULL);
+
+ chSysLock();
+
+ chDbgAssert(ctp->mtxlist != NULL, "owned mutexes list empty");
+ chDbgAssert(ctp->mtxlist->owner == ctp, "ownership failure");
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ chDbgAssert(mp->cnt >= (cnt_t)1, "counter is not positive");
+
+ if (--mp->cnt == (cnt_t)0) {
+#endif
+
+ chDbgAssert(ctp->mtxlist == mp, "not next in list");
+
+ /* Removes the top mutex from the thread's owned mutexes list and marks
+ it as not owned. Note, it is assumed to be the same mutex passed as
+ parameter of this function.*/
+ ctp->mtxlist = mp->next;
+
+ /* If a thread is waiting on the mutex then the fun part begins.*/
+ if (chMtxQueueNotEmptyS(mp)) {
+ thread_t *tp;
+
+ /* Recalculates the optimal thread priority by scanning the owned
+ mutexes list.*/
+ tprio_t newprio = ctp->realprio;
+ lmp = ctp->mtxlist;
+ while (lmp != NULL) {
+ /* If the highest priority thread waiting in the mutexes list has a
+ greater priority than the current thread base priority then the
+ final priority will have at least that priority.*/
+ if (chMtxQueueNotEmptyS(lmp) &&
+ (lmp->queue.next->prio > newprio)) {
+ newprio = lmp->queue.next->prio;
+ }
+ lmp = lmp->next;
+ }
+
+ /* Assigns to the current thread the highest priority among all the
+ waiting threads.*/
+ ctp->prio = newprio;
+
+ /* Awakens the highest priority thread waiting for the unlocked mutex and
+ assigns the mutex to it.*/
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ mp->cnt = (cnt_t)1;
+#endif
+ tp = queue_fifo_remove(&mp->queue);
+ mp->owner = tp;
+ mp->next = tp->mtxlist;
+ tp->mtxlist = mp;
+
+ /* Note, not using chSchWakeupS() becuase that function expects the
+ current thread to have the higher or equal priority than the ones
+ in the ready list. This is not necessarily true here because we
+ just changed priority.*/
+ (void) chSchReadyI(tp);
+ chSchRescheduleS();
+ }
+ else {
+ mp->owner = NULL;
+ }
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ }
+#endif
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Unlocks the specified mutex.
+ * @note Mutexes must be unlocked in reverse lock order. Violating this
+ * rules will result in a panic if assertions are enabled.
+ * @pre The invoking thread must have at least one owned mutex.
+ * @post The mutex is unlocked and removed from the per-thread stack of
+ * owned mutexes.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel.
+ *
+ * @param[in] mp pointer to the @p mutex_t structure
+ *
+ * @sclass
+ */
+void chMtxUnlockS(mutex_t *mp) {
+ thread_t *ctp = currp;
+ mutex_t *lmp;
+
+ chDbgCheckClassS();
+ chDbgCheck(mp != NULL);
+
+ chDbgAssert(ctp->mtxlist != NULL, "owned mutexes list empty");
+ chDbgAssert(ctp->mtxlist->owner == ctp, "ownership failure");
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ chDbgAssert(mp->cnt >= (cnt_t)1, "counter is not positive");
+
+ if (--mp->cnt == (cnt_t)0) {
+#endif
+
+ chDbgAssert(ctp->mtxlist == mp, "not next in list");
+
+ /* Removes the top mutex from the thread's owned mutexes list and marks
+ it as not owned. Note, it is assumed to be the same mutex passed as
+ parameter of this function.*/
+ ctp->mtxlist = mp->next;
+
+ /* If a thread is waiting on the mutex then the fun part begins.*/
+ if (chMtxQueueNotEmptyS(mp)) {
+ thread_t *tp;
+
+ /* Recalculates the optimal thread priority by scanning the owned
+ mutexes list.*/
+ tprio_t newprio = ctp->realprio;
+ lmp = ctp->mtxlist;
+ while (lmp != NULL) {
+ /* If the highest priority thread waiting in the mutexes list has a
+ greater priority than the current thread base priority then the
+ final priority will have at least that priority.*/
+ if (chMtxQueueNotEmptyS(lmp) &&
+ (lmp->queue.next->prio > newprio)) {
+ newprio = lmp->queue.next->prio;
+ }
+ lmp = lmp->next;
+ }
+
+ /* Assigns to the current thread the highest priority among all the
+ waiting threads.*/
+ ctp->prio = newprio;
+
+ /* Awakens the highest priority thread waiting for the unlocked mutex and
+ assigns the mutex to it.*/
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ mp->cnt = (cnt_t)1;
+#endif
+ tp = queue_fifo_remove(&mp->queue);
+ mp->owner = tp;
+ mp->next = tp->mtxlist;
+ tp->mtxlist = mp;
+ (void) chSchReadyI(tp);
+ }
+ else {
+ mp->owner = NULL;
+ }
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ }
+#endif
+}
+
+/**
+ * @brief Unlocks all mutexes owned by the invoking thread.
+ * @post The stack of owned mutexes is emptied and all the found
+ * mutexes are unlocked.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel.
+ * @note This function is MUCH MORE efficient than releasing the
+ * mutexes one by one and not just because the call overhead,
+ * this function does not have any overhead related to the priority
+ * inheritance mechanism.
+ *
+ * @sclass
+ */
+void chMtxUnlockAllS(void) {
+ thread_t *ctp = currp;
+
+ while (ctp->mtxlist != NULL) {
+ mutex_t *mp = ctp->mtxlist;
+ ctp->mtxlist = mp->next;
+ if (chMtxQueueNotEmptyS(mp)) {
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ mp->cnt = (cnt_t)1;
+#endif
+ thread_t *tp = queue_fifo_remove(&mp->queue);
+ mp->owner = tp;
+ mp->next = tp->mtxlist;
+ tp->mtxlist = mp;
+ (void) chSchReadyI(tp);
+ }
+ else {
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ mp->cnt = (cnt_t)0;
+#endif
+ mp->owner = NULL;
+ }
+ }
+ ctp->prio = ctp->realprio;
+}
+
+/**
+ * @brief Unlocks all mutexes owned by the invoking thread.
+ * @post The stack of owned mutexes is emptied and all the found
+ * mutexes are unlocked.
+ * @note This function is MUCH MORE efficient than releasing the
+ * mutexes one by one and not just because the call overhead,
+ * this function does not have any overhead related to the priority
+ * inheritance mechanism.
+ *
+ * @api
+ */
+void chMtxUnlockAll(void) {
+ thread_t *ctp = currp;
+
+ chSysLock();
+ if (ctp->mtxlist != NULL) {
+ do {
+ mutex_t *mp = ctp->mtxlist;
+ ctp->mtxlist = mp->next;
+ if (chMtxQueueNotEmptyS(mp)) {
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ mp->cnt = (cnt_t)1;
+#endif
+ thread_t *tp = queue_fifo_remove(&mp->queue);
+ mp->owner = tp;
+ mp->next = tp->mtxlist;
+ tp->mtxlist = mp;
+ (void) chSchReadyI(tp);
+ }
+ else {
+#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE
+ mp->cnt = (cnt_t)0;
+#endif
+ mp->owner = NULL;
+ }
+ } while (ctp->mtxlist != NULL);
+ ctp->prio = ctp->realprio;
+ chSchRescheduleS();
+ }
+ chSysUnlock();
+}
+
+#endif /* CH_CFG_USE_MUTEXES == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chregistry.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chregistry.c
new file mode 100644
index 0000000000..4ac2ae42cb
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chregistry.c
@@ -0,0 +1,268 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chregistry.c
+ * @brief Threads registry code.
+ *
+ * @addtogroup registry
+ * @details Threads Registry related APIs and services.
+ * Operation mode
+ * The Threads Registry is a double linked list that holds all the
+ * active threads in the system.
+ * Operations defined for the registry:
+ * - First, returns the first, in creation order, active thread
+ * in the system.
+ * - Next, returns the next, in creation order, active thread
+ * in the system.
+ * .
+ * The registry is meant to be mainly a debug feature, for example,
+ * using the registry a debugger can enumerate the active threads
+ * in any given moment or the shell can print the active threads
+ * and their state.
+ * Another possible use is for centralized threads memory management,
+ * terminating threads can pulse an event source and an event handler
+ * can perform a scansion of the registry in order to recover the
+ * memory.
+ * @pre In order to use the threads registry the @p CH_CFG_USE_REGISTRY
+ * option must be enabled in @p chconf.h.
+ * @{
+ */
+
+#include
+
+#include "ch.h"
+
+#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+#define _offsetof(st, m) \
+ /*lint -save -e9005 -e9033 -e413 [11.8, 10.8 1.3] Normal pointers
+ arithmetic, it is safe.*/ \
+ ((size_t)((char *)&((st *)0)->m - (char *)0)) \
+ /*lint -restore*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/*
+ * OS signature in ROM plus debug-related information.
+ */
+ROMCONST chdebug_t ch_debug = {
+ {'m', 'a', 'i', 'n'},
+ (uint8_t)0,
+ (uint8_t)sizeof (chdebug_t),
+ (uint16_t)(((unsigned)CH_KERNEL_MAJOR << 11U) |
+ ((unsigned)CH_KERNEL_MINOR << 6U) |
+ ((unsigned)CH_KERNEL_PATCH << 0U)),
+ (uint8_t)sizeof (void *),
+ (uint8_t)sizeof (systime_t),
+ (uint8_t)sizeof (thread_t),
+ (uint8_t)_offsetof(thread_t, prio),
+ (uint8_t)_offsetof(thread_t, ctx),
+ (uint8_t)_offsetof(thread_t, newer),
+ (uint8_t)_offsetof(thread_t, older),
+ (uint8_t)_offsetof(thread_t, name),
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || (CH_CFG_USE_DYNAMIC == TRUE)
+ (uint8_t)_offsetof(thread_t, wabase),
+#else
+ (uint8_t)0,
+#endif
+ (uint8_t)_offsetof(thread_t, state),
+ (uint8_t)_offsetof(thread_t, flags),
+#if CH_CFG_USE_DYNAMIC == TRUE
+ (uint8_t)_offsetof(thread_t, refs),
+#else
+ (uint8_t)0,
+#endif
+#if CH_CFG_TIME_QUANTUM > 0
+ (uint8_t)_offsetof(thread_t, preempt),
+#else
+ (uint8_t)0,
+#endif
+#if CH_DBG_THREADS_PROFILING == TRUE
+ (uint8_t)_offsetof(thread_t, time)
+#else
+ (uint8_t)0
+#endif
+};
+
+/**
+ * @brief Returns the first thread in the system.
+ * @details Returns the most ancient thread in the system, usually this is
+ * the main thread unless it terminated. A reference is added to the
+ * returned thread in order to make sure its status is not lost.
+ * @note This function cannot return @p NULL because there is always at
+ * least one thread in the system.
+ *
+ * @return A reference to the most ancient thread.
+ *
+ * @api
+ */
+thread_t *chRegFirstThread(void) {
+ thread_t *tp;
+
+ chSysLock();
+ tp = ch.rlist.newer;
+#if CH_CFG_USE_DYNAMIC == TRUE
+ tp->refs++;
+#endif
+ chSysUnlock();
+
+ return tp;
+}
+
+/**
+ * @brief Returns the thread next to the specified one.
+ * @details The reference counter of the specified thread is decremented and
+ * the reference counter of the returned thread is incremented.
+ *
+ * @param[in] tp pointer to the thread
+ * @return A reference to the next thread.
+ * @retval NULL if there is no next thread.
+ *
+ * @api
+ */
+thread_t *chRegNextThread(thread_t *tp) {
+ thread_t *ntp;
+
+ chSysLock();
+ ntp = tp->newer;
+ /*lint -save -e9087 -e740 [11.3, 1.3] Cast required by list handling.*/
+ if (ntp == (thread_t *)&ch.rlist) {
+ /*lint -restore*/
+ ntp = NULL;
+ }
+#if CH_CFG_USE_DYNAMIC == TRUE
+ else {
+ chDbgAssert(ntp->refs < (trefs_t)255, "too many references");
+ ntp->refs++;
+ }
+#endif
+ chSysUnlock();
+#if CH_CFG_USE_DYNAMIC == TRUE
+ chThdRelease(tp);
+#endif
+
+ return ntp;
+}
+
+/**
+ * @brief Retrieves a thread pointer by name.
+ * @note The reference counter of the found thread is increased by one so
+ * it cannot be disposed incidentally after the pointer has been
+ * returned.
+ *
+ * @param[in] name the thread name
+ * @return A pointer to the found thread.
+ * @retval NULL if a matching thread has not been found.
+ *
+ * @api
+ */
+thread_t *chRegFindThreadByName(const char *name) {
+ thread_t *ctp;
+
+ /* Scanning registry.*/
+ ctp = chRegFirstThread();
+ do {
+ if (strcmp(chRegGetThreadNameX(ctp), name) == 0) {
+ return ctp;
+ }
+ ctp = chRegNextThread(ctp);
+ } while (ctp != NULL);
+
+ return NULL;
+}
+
+/**
+ * @brief Confirms that a pointer is a valid thread pointer.
+ * @note The reference counter of the found thread is increased by one so
+ * it cannot be disposed incidentally after the pointer has been
+ * returned.
+ *
+ * @param[in] tp pointer to the thread
+ * @return A pointer to the found thread.
+ * @retval NULL if a matching thread has not been found.
+ *
+ * @api
+ */
+thread_t *chRegFindThreadByPointer(thread_t *tp) {
+ thread_t *ctp;
+
+ /* Scanning registry.*/
+ ctp = chRegFirstThread();
+ do {
+ if (ctp == tp) {
+ return ctp;
+ }
+ ctp = chRegNextThread(ctp);
+ } while (ctp != NULL);
+
+ return NULL;
+}
+
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || (CH_CFG_USE_DYNAMIC == TRUE) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief Confirms that a working area is being used by some active thread.
+ * @note The reference counter of the found thread is increased by one so
+ * it cannot be disposed incidentally after the pointer has been
+ * returned.
+ *
+ * @param[in] wa pointer to a static working area
+ * @return A pointer to the found thread.
+ * @retval NULL if a matching thread has not been found.
+ *
+ * @api
+ */
+thread_t *chRegFindThreadByWorkingArea(stkalign_t *wa) {
+ thread_t *ctp;
+
+ /* Scanning registry.*/
+ ctp = chRegFirstThread();
+ do {
+ if (chThdGetWorkingAreaX(ctp) == wa) {
+ return ctp;
+ }
+ ctp = chRegNextThread(ctp);
+ } while (ctp != NULL);
+
+ return NULL;
+}
+#endif
+
+#endif /* CH_CFG_USE_REGISTRY == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chschd.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chschd.c
new file mode 100644
index 0000000000..21e4ca4d9a
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chschd.c
@@ -0,0 +1,605 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chschd.c
+ * @brief Scheduler code.
+ *
+ * @addtogroup scheduler
+ * @details This module provides the default portable scheduler code.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief System data structures.
+ */
+ch_system_t ch;
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Scheduler initialization.
+ *
+ * @notapi
+ */
+void _scheduler_init(void) {
+
+ queue_init(&ch.rlist.queue);
+ ch.rlist.prio = NOPRIO;
+#if CH_CFG_USE_REGISTRY == TRUE
+ ch.rlist.newer = (thread_t *)&ch.rlist;
+ ch.rlist.older = (thread_t *)&ch.rlist;
+#endif
+}
+
+#if (CH_CFG_OPTIMIZE_SPEED == FALSE) || defined(__DOXYGEN__)
+/**
+ * @brief Inserts a thread into a priority ordered queue.
+ * @note The insertion is done by scanning the list from the highest
+ * priority toward the lowest.
+ *
+ * @param[in] tp the pointer to the thread to be inserted in the list
+ * @param[in] tqp the pointer to the threads list header
+ *
+ * @notapi
+ */
+void queue_prio_insert(thread_t *tp, threads_queue_t *tqp) {
+
+ thread_t *cp = (thread_t *)tqp;
+ do {
+ cp = cp->queue.next;
+ } while ((cp != (thread_t *)tqp) && (cp->prio >= tp->prio));
+ tp->queue.next = cp;
+ tp->queue.prev = cp->queue.prev;
+ tp->queue.prev->queue.next = tp;
+ cp->queue.prev = tp;
+}
+
+/**
+ * @brief Inserts a thread into a queue.
+ *
+ * @param[in] tp the pointer to the thread to be inserted in the list
+ * @param[in] tqp the pointer to the threads list header
+ *
+ * @notapi
+ */
+void queue_insert(thread_t *tp, threads_queue_t *tqp) {
+
+ tp->queue.next = (thread_t *)tqp;
+ tp->queue.prev = tqp->prev;
+ tp->queue.prev->queue.next = tp;
+ tqp->prev = tp;
+}
+
+/**
+ * @brief Removes the first-out thread from a queue and returns it.
+ * @note If the queue is priority ordered then this function returns the
+ * thread with the highest priority.
+ *
+ * @param[in] tqp the pointer to the threads list header
+ * @return The removed thread pointer.
+ *
+ * @notapi
+ */
+thread_t *queue_fifo_remove(threads_queue_t *tqp) {
+ thread_t *tp = tqp->next;
+
+ tqp->next = tp->queue.next;
+ tqp->next->queue.prev = (thread_t *)tqp;
+
+ return tp;
+}
+
+/**
+ * @brief Removes the last-out thread from a queue and returns it.
+ * @note If the queue is priority ordered then this function returns the
+ * thread with the lowest priority.
+ *
+ * @param[in] tqp the pointer to the threads list header
+ * @return The removed thread pointer.
+ *
+ * @notapi
+ */
+thread_t *queue_lifo_remove(threads_queue_t *tqp) {
+ thread_t *tp = tqp->prev;
+
+ tqp->prev = tp->queue.prev;
+ tqp->prev->queue.next = (thread_t *)tqp;
+
+ return tp;
+}
+
+/**
+ * @brief Removes a thread from a queue and returns it.
+ * @details The thread is removed from the queue regardless of its relative
+ * position and regardless the used insertion method.
+ *
+ * @param[in] tp the pointer to the thread to be removed from the queue
+ * @return The removed thread pointer.
+ *
+ * @notapi
+ */
+thread_t *queue_dequeue(thread_t *tp) {
+
+ tp->queue.prev->queue.next = tp->queue.next;
+ tp->queue.next->queue.prev = tp->queue.prev;
+
+ return tp;
+}
+
+/**
+ * @brief Pushes a thread_t on top of a stack list.
+ *
+ * @param[in] tp the pointer to the thread to be inserted in the list
+ * @param[in] tlp the pointer to the threads list header
+ *
+ * @notapi
+ */
+void list_insert(thread_t *tp, threads_list_t *tlp) {
+
+ tp->queue.next = tlp->next;
+ tlp->next = tp;
+}
+
+/**
+ * @brief Pops a thread from the top of a stack list and returns it.
+ * @pre The list must be non-empty before calling this function.
+ *
+ * @param[in] tlp the pointer to the threads list header
+ * @return The removed thread pointer.
+ *
+ * @notapi
+ */
+thread_t *list_remove(threads_list_t *tlp) {
+
+ thread_t *tp = tlp->next;
+ tlp->next = tp->queue.next;
+
+ return tp;
+}
+#endif /* CH_CFG_OPTIMIZE_SPEED */
+
+/**
+ * @brief Inserts a thread in the Ready List placing it behind its peers.
+ * @details The thread is positioned behind all threads with higher or equal
+ * priority.
+ * @pre The thread must not be already inserted in any list through its
+ * @p next and @p prev or list corruption would occur.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] tp the thread to be made ready
+ * @return The thread pointer.
+ *
+ * @iclass
+ */
+thread_t *chSchReadyI(thread_t *tp) {
+ thread_t *cp;
+
+ chDbgCheckClassI();
+ chDbgCheck(tp != NULL);
+ chDbgAssert((tp->state != CH_STATE_READY) &&
+ (tp->state != CH_STATE_FINAL),
+ "invalid state");
+
+ tp->state = CH_STATE_READY;
+ cp = (thread_t *)&ch.rlist.queue;
+ do {
+ cp = cp->queue.next;
+ } while (cp->prio >= tp->prio);
+ /* Insertion on prev.*/
+ tp->queue.next = cp;
+ tp->queue.prev = cp->queue.prev;
+ tp->queue.prev->queue.next = tp;
+ cp->queue.prev = tp;
+
+ return tp;
+}
+
+/**
+ * @brief Inserts a thread in the Ready List placing it ahead its peers.
+ * @details The thread is positioned ahead all threads with higher or equal
+ * priority.
+ * @pre The thread must not be already inserted in any list through its
+ * @p next and @p prev or list corruption would occur.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] tp the thread to be made ready
+ * @return The thread pointer.
+ *
+ * @iclass
+ */
+thread_t *chSchReadyAheadI(thread_t *tp) {
+ thread_t *cp;
+
+ chDbgCheckClassI();
+ chDbgCheck(tp != NULL);
+ chDbgAssert((tp->state != CH_STATE_READY) &&
+ (tp->state != CH_STATE_FINAL),
+ "invalid state");
+
+ tp->state = CH_STATE_READY;
+ cp = (thread_t *)&ch.rlist.queue;
+ do {
+ cp = cp->queue.next;
+ } while (cp->prio > tp->prio);
+ /* Insertion on prev.*/
+ tp->queue.next = cp;
+ tp->queue.prev = cp->queue.prev;
+ tp->queue.prev->queue.next = tp;
+ cp->queue.prev = tp;
+
+ return tp;
+}
+
+/**
+ * @brief Puts the current thread to sleep into the specified state.
+ * @details The thread goes into a sleeping state. The possible
+ * @ref thread_states are defined into @p threads.h.
+ *
+ * @param[in] newstate the new thread state
+ *
+ * @sclass
+ */
+void chSchGoSleepS(tstate_t newstate) {
+ thread_t *otp = currp;
+
+ chDbgCheckClassS();
+
+ /* New state.*/
+ otp->state = newstate;
+
+#if CH_CFG_TIME_QUANTUM > 0
+ /* The thread is renouncing its remaining time slices so it will have a new
+ time quantum when it will wakeup.*/
+ otp->preempt = (tslices_t)CH_CFG_TIME_QUANTUM;
+#endif
+
+ /* Next thread in ready list becomes current.*/
+ currp = queue_fifo_remove(&ch.rlist.queue);
+ currp->state = CH_STATE_CURRENT;
+
+ /* Handling idle-enter hook.*/
+ if (currp->prio == IDLEPRIO) {
+ CH_CFG_IDLE_ENTER_HOOK();
+ }
+
+ /* Swap operation as tail call.*/
+ chSysSwitch(currp, otp);
+}
+
+/*
+ * Timeout wakeup callback.
+ */
+static void wakeup(void *p) {
+ thread_t *tp = (thread_t *)p;
+
+ chSysLockFromISR();
+ switch (tp->state) {
+ case CH_STATE_READY:
+ /* Handling the special case where the thread has been made ready by
+ another thread with higher priority.*/
+ chSysUnlockFromISR();
+ return;
+ case CH_STATE_SUSPENDED:
+ *tp->u.wttrp = NULL;
+ break;
+#if CH_CFG_USE_SEMAPHORES == TRUE
+ case CH_STATE_WTSEM:
+ chSemFastSignalI(tp->u.wtsemp);
+ /* Falls into, intentional. */
+#endif
+#if (CH_CFG_USE_CONDVARS == TRUE) && (CH_CFG_USE_CONDVARS_TIMEOUT == TRUE)
+ case CH_STATE_WTCOND:
+#endif
+ case CH_STATE_QUEUED:
+ /* States requiring dequeuing.*/
+ (void) queue_dequeue(tp);
+ break;
+ default:
+ /* Any other state, nothing to do.*/
+ break;
+ }
+ tp->u.rdymsg = MSG_TIMEOUT;
+ (void) chSchReadyI(tp);
+ chSysUnlockFromISR();
+}
+
+/**
+ * @brief Puts the current thread to sleep into the specified state with
+ * timeout specification.
+ * @details The thread goes into a sleeping state, if it is not awakened
+ * explicitly within the specified timeout then it is forcibly
+ * awakened with a @p MSG_TIMEOUT low level message. The possible
+ * @ref thread_states are defined into @p threads.h.
+ *
+ * @param[in] newstate the new thread state
+ * @param[in] time the number of ticks before the operation timeouts, the
+ * special values are handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state, this is equivalent to invoking
+ * @p chSchGoSleepS() but, of course, less efficient.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ * @return The wakeup message.
+ * @retval MSG_TIMEOUT if a timeout occurs.
+ *
+ * @sclass
+ */
+msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) {
+
+ chDbgCheckClassS();
+
+ if (TIME_INFINITE != time) {
+ virtual_timer_t vt;
+
+ chVTDoSetI(&vt, time, wakeup, currp);
+ chSchGoSleepS(newstate);
+ if (chVTIsArmedI(&vt)) {
+ chVTDoResetI(&vt);
+ }
+ }
+ else {
+ chSchGoSleepS(newstate);
+ }
+
+ return currp->u.rdymsg;
+}
+
+/**
+ * @brief Wakes up a thread.
+ * @details The thread is inserted into the ready list or immediately made
+ * running depending on its relative priority compared to the current
+ * thread.
+ * @pre The thread must not be already inserted in any list through its
+ * @p next and @p prev or list corruption would occur.
+ * @note It is equivalent to a @p chSchReadyI() followed by a
+ * @p chSchRescheduleS() but much more efficient.
+ * @note The function assumes that the current thread has the highest
+ * priority.
+ *
+ * @param[in] ntp the thread to be made ready
+ * @param[in] msg the wakeup message
+ *
+ * @sclass
+ */
+void chSchWakeupS(thread_t *ntp, msg_t msg) {
+ thread_t *otp = currp;
+
+ chDbgCheckClassS();
+
+ chDbgAssert((ch.rlist.queue.next == (thread_t *)&ch.rlist.queue) ||
+ (ch.rlist.current->prio >= ch.rlist.queue.next->prio),
+ "priority order violation");
+
+ /* Storing the message to be retrieved by the target thread when it will
+ restart execution.*/
+ ntp->u.rdymsg = msg;
+
+ /* If the waken thread has a not-greater priority than the current
+ one then it is just inserted in the ready list else it made
+ running immediately and the invoking thread goes in the ready
+ list instead.*/
+ if (ntp->prio <= otp->prio) {
+ (void) chSchReadyI(ntp);
+ }
+ else {
+ otp = chSchReadyI(otp);
+
+ /* Handling idle-leave hook.*/
+ if (otp->prio == IDLEPRIO) {
+ CH_CFG_IDLE_LEAVE_HOOK();
+ }
+
+ /* The extracted thread is marked as current.*/
+ currp = ntp;
+ ntp->state = CH_STATE_CURRENT;
+
+ /* Swap operation as tail call.*/
+ chSysSwitch(ntp, otp);
+ }
+}
+
+/**
+ * @brief Performs a reschedule if a higher priority thread is runnable.
+ * @details If a thread with a higher priority than the current thread is in
+ * the ready list then make the higher priority thread running.
+ *
+ * @sclass
+ */
+void chSchRescheduleS(void) {
+
+ chDbgCheckClassS();
+
+ if (chSchIsRescRequiredI()) {
+ chSchDoRescheduleAhead();
+ }
+}
+
+/**
+ * @brief Evaluates if preemption is required.
+ * @details The decision is taken by comparing the relative priorities and
+ * depending on the state of the round robin timeout counter.
+ * @note Not a user function, it is meant to be invoked by the scheduler
+ * itself or from within the port layer.
+ *
+ * @retval true if there is a thread that must go in running state
+ * immediately.
+ * @retval false if preemption is not required.
+ *
+ * @special
+ */
+bool chSchIsPreemptionRequired(void) {
+ tprio_t p1 = firstprio(&ch.rlist.queue);
+ tprio_t p2 = currp->prio;
+
+#if CH_CFG_TIME_QUANTUM > 0
+ /* If the running thread has not reached its time quantum, reschedule only
+ if the first thread on the ready queue has a higher priority.
+ Otherwise, if the running thread has used up its time quantum, reschedule
+ if the first thread on the ready queue has equal or higher priority.*/
+ return (currp->preempt > (tslices_t)0) ? (p1 > p2) : (p1 >= p2);
+#else
+ /* If the round robin preemption feature is not enabled then performs a
+ simpler comparison.*/
+ return p1 > p2;
+#endif
+}
+
+/**
+ * @brief Switches to the first thread on the runnable queue.
+ * @details The current thread is positioned in the ready list behind all
+ * threads having the same priority. The thread regains its time
+ * quantum.
+ * @note Not a user function, it is meant to be invoked by the scheduler
+ * itself.
+ *
+ * @special
+ */
+void chSchDoRescheduleBehind(void) {
+ thread_t *otp = currp;
+
+ /* Picks the first thread from the ready queue and makes it current.*/
+ currp = queue_fifo_remove(&ch.rlist.queue);
+ currp->state = CH_STATE_CURRENT;
+
+ /* Handling idle-leave hook.*/
+ if (otp->prio == IDLEPRIO) {
+ CH_CFG_IDLE_LEAVE_HOOK();
+ }
+
+#if CH_CFG_TIME_QUANTUM > 0
+ /* It went behind peers so it gets a new time quantum.*/
+ otp->preempt = (tslices_t)CH_CFG_TIME_QUANTUM;
+#endif
+
+ /* Placing in ready list behind peers.*/
+ otp = chSchReadyI(otp);
+
+ /* Swap operation as tail call.*/
+ chSysSwitch(currp, otp);
+}
+
+/**
+ * @brief Switches to the first thread on the runnable queue.
+ * @details The current thread is positioned in the ready list ahead of all
+ * threads having the same priority.
+ * @note Not a user function, it is meant to be invoked by the scheduler
+ * itself.
+ *
+ * @special
+ */
+void chSchDoRescheduleAhead(void) {
+ thread_t *otp = currp;
+
+ /* Picks the first thread from the ready queue and makes it current.*/
+ currp = queue_fifo_remove(&ch.rlist.queue);
+ currp->state = CH_STATE_CURRENT;
+
+ /* Handling idle-leave hook.*/
+ if (otp->prio == IDLEPRIO) {
+ CH_CFG_IDLE_LEAVE_HOOK();
+ }
+
+ /* Placing in ready list ahead of peers.*/
+ otp = chSchReadyAheadI(otp);
+
+ /* Swap operation as tail call.*/
+ chSysSwitch(currp, otp);
+}
+
+/**
+ * @brief Switches to the first thread on the runnable queue.
+ * @details The current thread is positioned in the ready list behind or
+ * ahead of all threads having the same priority depending on
+ * if it used its whole time slice.
+ * @note Not a user function, it is meant to be invoked by the scheduler
+ * itself or from within the port layer.
+ *
+ * @special
+ */
+void chSchDoReschedule(void) {
+ thread_t *otp = currp;
+
+ /* Picks the first thread from the ready queue and makes it current.*/
+ currp = queue_fifo_remove(&ch.rlist.queue);
+ currp->state = CH_STATE_CURRENT;
+
+ /* Handling idle-leave hook.*/
+ if (otp->prio == IDLEPRIO) {
+ CH_CFG_IDLE_LEAVE_HOOK();
+ }
+
+#if CH_CFG_TIME_QUANTUM > 0
+ /* If CH_CFG_TIME_QUANTUM is enabled then there are two different scenarios
+ to handle on preemption: time quantum elapsed or not.*/
+ if (currp->preempt == (tslices_t)0) {
+
+ /* The thread consumed its time quantum so it is enqueued behind threads
+ with same priority level, however, it acquires a new time quantum.*/
+ otp = chSchReadyI(otp);
+
+ /* The thread being swapped out receives a new time quantum.*/
+ otp->preempt = (tslices_t)CH_CFG_TIME_QUANTUM;
+ }
+ else {
+ /* The thread didn't consume all its time quantum so it is put ahead of
+ threads with equal priority and does not acquire a new time quantum.*/
+ otp = chSchReadyAheadI(otp);
+ }
+#else /* !(CH_CFG_TIME_QUANTUM > 0) */
+ /* If the round-robin mechanism is disabled then the thread goes always
+ ahead of its peers.*/
+ otp = chSchReadyAheadI(otp);
+#endif /* !(CH_CFG_TIME_QUANTUM > 0) */
+
+ /* Swap operation as tail call.*/
+ chSysSwitch(currp, otp);
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chsem.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chsem.c
similarity index 55%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chsem.c
rename to flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chsem.c
index 19408bf0b8..5091d60784 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/src/chsem.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chsem.c
@@ -1,28 +1,20 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
- This file is part of ChibiOS/RT.
+ This file is part of ChibiOS.
- ChibiOS/RT is free software; you can redistribute it and/or modify
+ ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
- ChibiOS/RT is distributed in the hope that it will be useful,
+ ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
*/
/**
@@ -31,7 +23,6 @@
*
* @addtogroup semaphores
* @details Semaphores related APIs and services.
- *
* Operation mode
* Semaphores are a flexible synchronization primitive, ChibiOS/RT
* implements semaphores in their "counting semaphores" variant as
@@ -58,37 +49,57 @@
* also have other uses, queues guards and counters for example.
* Semaphores usually use a FIFO queuing strategy but it is possible
* to make them order threads by priority by enabling
- * @p CH_USE_SEMAPHORES_PRIORITY in @p chconf.h.
- * @pre In order to use the semaphore APIs the @p CH_USE_SEMAPHORES
+ * @p CH_CFG_USE_SEMAPHORES_PRIORITY in @p chconf.h.
+ * @pre In order to use the semaphore APIs the @p CH_CFG_USE_SEMAPHORES
* option must be enabled in @p chconf.h.
* @{
*/
#include "ch.h"
-#if CH_USE_SEMAPHORES || defined(__DOXYGEN__)
+#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
-#if CH_USE_SEMAPHORES_PRIORITY
-#define sem_insert(tp, qp) prio_insert(tp, qp)
+#if CH_CFG_USE_SEMAPHORES_PRIORITY == TRUE
+#define sem_insert(tp, qp) queue_prio_insert(tp, qp)
#else
#define sem_insert(tp, qp) queue_insert(tp, qp)
#endif
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
/**
* @brief Initializes a semaphore with the specified counter value.
*
- * @param[out] sp pointer to a @p Semaphore structure
+ * @param[out] sp pointer to a @p semaphore_t structure
* @param[in] n initial value of the semaphore counter. Must be
* non-negative.
*
* @init
*/
-void chSemInit(Semaphore *sp, cnt_t n) {
+void chSemObjectInit(semaphore_t *sp, cnt_t n) {
- chDbgCheck((sp != NULL) && (n >= 0), "chSemInit");
+ chDbgCheck((sp != NULL) && (n >= (cnt_t)0));
- queue_init(&sp->s_queue);
- sp->s_cnt = n;
+ queue_init(&sp->queue);
+ sp->cnt = n;
}
/**
@@ -98,15 +109,15 @@ void chSemInit(Semaphore *sp, cnt_t n) {
* to the specified, non negative, value.
* @note The released threads can recognize they were waked up by a reset
* rather than a signal because the @p chSemWait() will return
- * @p RDY_RESET instead of @p RDY_OK.
+ * @p MSG_RESET instead of @p MSG_OK.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
* @param[in] n the new value of the semaphore counter. The value must
* be non-negative.
*
* @api
*/
-void chSemReset(Semaphore *sp, cnt_t n) {
+void chSemReset(semaphore_t *sp, cnt_t n) {
chSysLock();
chSemResetI(sp, n);
@@ -125,85 +136,87 @@ void chSemReset(Semaphore *sp, cnt_t n) {
* reschedule must not be performed in ISRs.
* @note The released threads can recognize they were waked up by a reset
* rather than a signal because the @p chSemWait() will return
- * @p RDY_RESET instead of @p RDY_OK.
+ * @p MSG_RESET instead of @p MSG_OK.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
* @param[in] n the new value of the semaphore counter. The value must
* be non-negative.
*
* @iclass
*/
-void chSemResetI(Semaphore *sp, cnt_t n) {
+void chSemResetI(semaphore_t *sp, cnt_t n) {
cnt_t cnt;
chDbgCheckClassI();
- chDbgCheck((sp != NULL) && (n >= 0), "chSemResetI");
- chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
- ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
- "chSemResetI(), #1",
+ chDbgCheck((sp != NULL) && (n >= (cnt_t)0));
+ chDbgAssert(((sp->cnt >= (cnt_t)0) && queue_isempty(&sp->queue)) ||
+ ((sp->cnt < (cnt_t)0) && queue_notempty(&sp->queue)),
"inconsistent semaphore");
- cnt = sp->s_cnt;
- sp->s_cnt = n;
- while (++cnt <= 0)
- chSchReadyI(lifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_RESET;
+ cnt = sp->cnt;
+ sp->cnt = n;
+ while (++cnt <= (cnt_t)0) {
+ chSchReadyI(queue_lifo_remove(&sp->queue))->u.rdymsg = MSG_RESET;
+ }
}
/**
* @brief Performs a wait operation on a semaphore.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
* @return A message specifying how the invoking thread has been
* released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or the
+ * @retval MSG_OK if the thread has not stopped on the semaphore or the
* semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using @p chSemReset().
+ * @retval MSG_RESET if the semaphore has been reset using @p chSemReset().
*
* @api
*/
-msg_t chSemWait(Semaphore *sp) {
+msg_t chSemWait(semaphore_t *sp) {
msg_t msg;
chSysLock();
msg = chSemWaitS(sp);
chSysUnlock();
+
return msg;
}
/**
* @brief Performs a wait operation on a semaphore.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
* @return A message specifying how the invoking thread has been
* released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or the
+ * @retval MSG_OK if the thread has not stopped on the semaphore or the
* semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using @p chSemReset().
+ * @retval MSG_RESET if the semaphore has been reset using @p chSemReset().
*
* @sclass
*/
-msg_t chSemWaitS(Semaphore *sp) {
+msg_t chSemWaitS(semaphore_t *sp) {
chDbgCheckClassS();
- chDbgCheck(sp != NULL, "chSemWaitS");
- chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
- ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
- "chSemWaitS(), #1",
+ chDbgCheck(sp != NULL);
+ chDbgAssert(((sp->cnt >= (cnt_t)0) && queue_isempty(&sp->queue)) ||
+ ((sp->cnt < (cnt_t)0) && queue_notempty(&sp->queue)),
"inconsistent semaphore");
- if (--sp->s_cnt < 0) {
- currp->p_u.wtobjp = sp;
- sem_insert(currp, &sp->s_queue);
- chSchGoSleepS(THD_STATE_WTSEM);
- return currp->p_u.rdymsg;
+ if (--sp->cnt < (cnt_t)0) {
+ currp->u.wtsemp = sp;
+ sem_insert(currp, &sp->queue);
+ chSchGoSleepS(CH_STATE_WTSEM);
+
+ return currp->u.rdymsg;
}
- return RDY_OK;
+
+ return MSG_OK;
}
/**
* @brief Performs a wait operation on a semaphore with timeout specification.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
* @param[in] time the number of ticks before the operation timeouts,
* the following special values are allowed:
* - @a TIME_IMMEDIATE immediate timeout.
@@ -211,27 +224,28 @@ msg_t chSemWaitS(Semaphore *sp) {
* .
* @return A message specifying how the invoking thread has been
* released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or the
+ * @retval MSG_OK if the thread has not stopped on the semaphore or the
* semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using @p chSemReset().
- * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset within
+ * @retval MSG_RESET if the semaphore has been reset using @p chSemReset().
+ * @retval MSG_TIMEOUT if the semaphore has not been signaled or reset within
* the specified timeout.
*
* @api
*/
-msg_t chSemWaitTimeout(Semaphore *sp, systime_t time) {
+msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time) {
msg_t msg;
chSysLock();
msg = chSemWaitTimeoutS(sp, time);
chSysUnlock();
+
return msg;
}
/**
* @brief Performs a wait operation on a semaphore with timeout specification.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
* @param[in] time the number of ticks before the operation timeouts,
* the following special values are allowed:
* - @a TIME_IMMEDIATE immediate timeout.
@@ -239,53 +253,55 @@ msg_t chSemWaitTimeout(Semaphore *sp, systime_t time) {
* .
* @return A message specifying how the invoking thread has been
* released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or the
+ * @retval MSG_OK if the thread has not stopped on the semaphore or the
* semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using @p chSemReset().
- * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset within
+ * @retval MSG_RESET if the semaphore has been reset using @p chSemReset().
+ * @retval MSG_TIMEOUT if the semaphore has not been signaled or reset within
* the specified timeout.
*
* @sclass
*/
-msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time) {
+msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time) {
chDbgCheckClassS();
- chDbgCheck(sp != NULL, "chSemWaitTimeoutS");
- chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
- ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
- "chSemWaitTimeoutS(), #1",
+ chDbgCheck(sp != NULL);
+ chDbgAssert(((sp->cnt >= (cnt_t)0) && queue_isempty(&sp->queue)) ||
+ ((sp->cnt < (cnt_t)0) && queue_notempty(&sp->queue)),
"inconsistent semaphore");
- if (--sp->s_cnt < 0) {
+ if (--sp->cnt < (cnt_t)0) {
if (TIME_IMMEDIATE == time) {
- sp->s_cnt++;
- return RDY_TIMEOUT;
+ sp->cnt++;
+
+ return MSG_TIMEOUT;
}
- currp->p_u.wtobjp = sp;
- sem_insert(currp, &sp->s_queue);
- return chSchGoSleepTimeoutS(THD_STATE_WTSEM, time);
+ currp->u.wtsemp = sp;
+ sem_insert(currp, &sp->queue);
+
+ return chSchGoSleepTimeoutS(CH_STATE_WTSEM, time);
}
- return RDY_OK;
+
+ return MSG_OK;
}
/**
* @brief Performs a signal operation on a semaphore.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
*
* @api
*/
-void chSemSignal(Semaphore *sp) {
+void chSemSignal(semaphore_t *sp) {
- chDbgCheck(sp != NULL, "chSemSignal");
- chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
- ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
- "chSemSignal(), #1",
- "inconsistent semaphore");
+ chDbgCheck(sp != NULL);
chSysLock();
- if (++sp->s_cnt <= 0)
- chSchWakeupS(fifo_remove(&sp->s_queue), RDY_OK);
+ chDbgAssert(((sp->cnt >= (cnt_t)0) && queue_isempty(&sp->queue)) ||
+ ((sp->cnt < (cnt_t)0) && queue_notempty(&sp->queue)),
+ "inconsistent semaphore");
+ if (++sp->cnt <= (cnt_t)0) {
+ chSchWakeupS(queue_fifo_remove(&sp->queue), MSG_OK);
+ }
chSysUnlock();
}
@@ -296,25 +312,24 @@ void chSemSignal(Semaphore *sp) {
* interrupt handlers always reschedule on exit so an explicit
* reschedule must not be performed in ISRs.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
*
* @iclass
*/
-void chSemSignalI(Semaphore *sp) {
+void chSemSignalI(semaphore_t *sp) {
chDbgCheckClassI();
- chDbgCheck(sp != NULL, "chSemSignalI");
- chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
- ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
- "chSemSignalI(), #1",
+ chDbgCheck(sp != NULL);
+ chDbgAssert(((sp->cnt >= (cnt_t)0) && queue_isempty(&sp->queue)) ||
+ ((sp->cnt < (cnt_t)0) && queue_notempty(&sp->queue)),
"inconsistent semaphore");
- if (++sp->s_cnt <= 0) {
+ if (++sp->cnt <= (cnt_t)0) {
/* Note, it is done this way in order to allow a tail call on
chSchReadyI().*/
- Thread *tp = fifo_remove(&sp->s_queue);
- tp->p_u.rdymsg = RDY_OK;
- chSchReadyI(tp);
+ thread_t *tp = queue_fifo_remove(&sp->queue);
+ tp->u.rdymsg = MSG_OK;
+ (void) chSchReadyI(tp);
}
}
@@ -325,76 +340,72 @@ void chSemSignalI(Semaphore *sp) {
* interrupt handlers always reschedule on exit so an explicit
* reschedule must not be performed in ISRs.
*
- * @param[in] sp pointer to a @p Semaphore structure
+ * @param[in] sp pointer to a @p semaphore_t structure
* @param[in] n value to be added to the semaphore counter. The value
* must be positive.
*
* @iclass
*/
-void chSemAddCounterI(Semaphore *sp, cnt_t n) {
+void chSemAddCounterI(semaphore_t *sp, cnt_t n) {
chDbgCheckClassI();
- chDbgCheck((sp != NULL) && (n > 0), "chSemAddCounterI");
- chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
- ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
- "chSemAddCounterI(), #1",
+ chDbgCheck((sp != NULL) && (n > (cnt_t)0));
+ chDbgAssert(((sp->cnt >= (cnt_t)0) && queue_isempty(&sp->queue)) ||
+ ((sp->cnt < (cnt_t)0) && queue_notempty(&sp->queue)),
"inconsistent semaphore");
- while (n > 0) {
- if (++sp->s_cnt <= 0)
- chSchReadyI(fifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_OK;
+ while (n > (cnt_t)0) {
+ if (++sp->cnt <= (cnt_t)0) {
+ chSchReadyI(queue_fifo_remove(&sp->queue))->u.rdymsg = MSG_OK;
+ }
n--;
}
}
-#if CH_USE_SEMSW || defined(__DOXYGEN__)
/**
* @brief Performs atomic signal and wait operations on two semaphores.
- * @pre The configuration option @p CH_USE_SEMSW must be enabled in order
- * to use this function.
*
- * @param[in] sps pointer to a @p Semaphore structure to be signaled
- * @param[in] spw pointer to a @p Semaphore structure to wait on
+ * @param[in] sps pointer to a @p semaphore_t structure to be signaled
+ * @param[in] spw pointer to a @p semaphore_t structure to wait on
* @return A message specifying how the invoking thread has been
* released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or the
+ * @retval MSG_OK if the thread has not stopped on the semaphore or the
* semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using @p chSemReset().
+ * @retval MSG_RESET if the semaphore has been reset using @p chSemReset().
*
* @api
*/
-msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw) {
+msg_t chSemSignalWait(semaphore_t *sps, semaphore_t *spw) {
msg_t msg;
- chDbgCheck((sps != NULL) && (spw != NULL), "chSemSignalWait");
- chDbgAssert(((sps->s_cnt >= 0) && isempty(&sps->s_queue)) ||
- ((sps->s_cnt < 0) && notempty(&sps->s_queue)),
- "chSemSignalWait(), #1",
- "inconsistent semaphore");
- chDbgAssert(((spw->s_cnt >= 0) && isempty(&spw->s_queue)) ||
- ((spw->s_cnt < 0) && notempty(&spw->s_queue)),
- "chSemSignalWait(), #2",
- "inconsistent semaphore");
+ chDbgCheck((sps != NULL) && (spw != NULL));
chSysLock();
- if (++sps->s_cnt <= 0)
- chSchReadyI(fifo_remove(&sps->s_queue))->p_u.rdymsg = RDY_OK;
- if (--spw->s_cnt < 0) {
- Thread *ctp = currp;
- sem_insert(ctp, &spw->s_queue);
- ctp->p_u.wtobjp = spw;
- chSchGoSleepS(THD_STATE_WTSEM);
- msg = ctp->p_u.rdymsg;
+ chDbgAssert(((sps->cnt >= (cnt_t)0) && queue_isempty(&sps->queue)) ||
+ ((sps->cnt < (cnt_t)0) && queue_notempty(&sps->queue)),
+ "inconsistent semaphore");
+ chDbgAssert(((spw->cnt >= (cnt_t)0) && queue_isempty(&spw->queue)) ||
+ ((spw->cnt < (cnt_t)0) && queue_notempty(&spw->queue)),
+ "inconsistent semaphore");
+ if (++sps->cnt <= (cnt_t)0) {
+ chSchReadyI(queue_fifo_remove(&sps->queue))->u.rdymsg = MSG_OK;
+ }
+ if (--spw->cnt < (cnt_t)0) {
+ thread_t *ctp = currp;
+ sem_insert(ctp, &spw->queue);
+ ctp->u.wtsemp = spw;
+ chSchGoSleepS(CH_STATE_WTSEM);
+ msg = ctp->u.rdymsg;
}
else {
chSchRescheduleS();
- msg = RDY_OK;
+ msg = MSG_OK;
}
chSysUnlock();
+
return msg;
}
-#endif /* CH_USE_SEMSW */
-#endif /* CH_USE_SEMAPHORES */
+#endif /* CH_CFG_USE_SEMAPHORES == TRUE */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chstats.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chstats.c
new file mode 100644
index 0000000000..0c01a858a8
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chstats.c
@@ -0,0 +1,126 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chstats.c
+ * @brief Statistics module code.
+ *
+ * @addtogroup statistics
+ * @details Statistics services.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_DBG_STATISTICS == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the statistics module.
+ *
+ * @init
+ */
+void _stats_init(void) {
+
+ ch.kernel_stats.n_irq = (ucnt_t)0;
+ ch.kernel_stats.n_ctxswc = (ucnt_t)0;
+ chTMObjectInit(&ch.kernel_stats.m_crit_thd);
+ chTMObjectInit(&ch.kernel_stats.m_crit_isr);
+}
+
+/**
+ * @brief Increases the IRQ counter.
+ */
+void _stats_increase_irq(void) {
+
+ port_lock_from_isr();
+ ch.kernel_stats.n_irq++;
+ port_unlock_from_isr();
+}
+
+/**
+ * @brief Updates context switch related statistics.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+void _stats_ctxswc(thread_t *ntp, thread_t *otp) {
+
+ ch.kernel_stats.n_ctxswc++;
+ chTMChainMeasurementToX(&otp->stats, &ntp->stats);
+}
+
+/**
+ * @brief Starts the measurement of a thread critical zone.
+ */
+void _stats_start_measure_crit_thd(void) {
+
+ chTMStartMeasurementX(&ch.kernel_stats.m_crit_thd);
+}
+
+/**
+ * @brief Stops the measurement of a thread critical zone.
+ */
+void _stats_stop_measure_crit_thd(void) {
+
+ chTMStopMeasurementX(&ch.kernel_stats.m_crit_thd);
+}
+
+/**
+ * @brief Starts the measurement of an ISR critical zone.
+ */
+void _stats_start_measure_crit_isr(void) {
+
+ chTMStartMeasurementX(&ch.kernel_stats.m_crit_isr);
+}
+
+/**
+ * @brief Stops the measurement of an ISR critical zone.
+ */
+void _stats_stop_measure_crit_isr(void) {
+
+ chTMStopMeasurementX(&ch.kernel_stats.m_crit_isr);
+}
+
+#endif /* CH_DBG_STATISTICS == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chsys.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chsys.c
new file mode 100644
index 0000000000..d2b75ddaad
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chsys.c
@@ -0,0 +1,446 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chsys.c
+ * @brief System related code.
+ *
+ * @addtogroup system
+ * @details System related APIs and services:
+ * - Initialization.
+ * - Locks.
+ * - Interrupt Handling.
+ * - Power Management.
+ * - Abnormal Termination.
+ * - Realtime counter.
+ * .
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+#if (CH_CFG_NO_IDLE_THREAD == FALSE) || defined(__DOXYGEN__)
+/**
+ * @brief Idle thread working area.
+ */
+THD_WORKING_AREA(ch_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE);
+#endif
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+#if (CH_CFG_NO_IDLE_THREAD == FALSE) || defined(__DOXYGEN__)
+/**
+ * @brief This function implements the idle thread infinite loop.
+ * @details The function puts the processor in the lowest power mode capable
+ * to serve interrupts.
+ * The priority is internally set to the minimum system value so
+ * that this thread is executed only if there are no other ready
+ * threads in the system.
+ *
+ * @param[in] p the thread parameter, unused in this scenario
+ */
+static void _idle_thread(void *p) {
+
+ (void)p;
+
+ while (true) {
+ /*lint -save -e522 [2.2] Apparently no side effects because it contains
+ an asm instruction.*/
+ port_wait_for_interrupt();
+ /*lint -restore*/
+ CH_CFG_IDLE_LOOP_HOOK();
+ }
+}
+#endif /* CH_CFG_NO_IDLE_THREAD == FALSE */
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief ChibiOS/RT initialization.
+ * @details After executing this function the current instructions stream
+ * becomes the main thread.
+ * @pre Interrupts must disabled before invoking this function.
+ * @post The main thread is created with priority @p NORMALPRIO and
+ * interrupts are enabled.
+ *
+ * @special
+ */
+void chSysInit(void) {
+
+ _scheduler_init();
+ _vt_init();
+ _trace_init();
+
+#if CH_DBG_SYSTEM_STATE_CHECK == TRUE
+ ch.dbg.isr_cnt = (cnt_t)0;
+ ch.dbg.lock_cnt = (cnt_t)0;
+#endif
+#if CH_CFG_USE_TM == TRUE
+ _tm_init();
+#endif
+#if CH_CFG_USE_MEMCORE == TRUE
+ _core_init();
+#endif
+#if CH_CFG_USE_HEAP == TRUE
+ _heap_init();
+#endif
+#if CH_DBG_STATISTICS == TRUE
+ _stats_init();
+#endif
+
+#if CH_CFG_NO_IDLE_THREAD == FALSE
+ /* Now this instructions flow becomes the main thread.*/
+#if CH_CFG_USE_REGISTRY == TRUE
+ currp = _thread_init(&ch.mainthread, (const char *)&ch_debug, NORMALPRIO);
+#else
+ currp = _thread_init(&ch.mainthread, "main", NORMALPRIO);
+#endif
+#else
+ /* Now this instructions flow becomes the idle thread.*/
+ currp = _thread_init(&ch.mainthread, "idle", IDLEPRIO);
+#endif
+
+#if CH_DBG_ENABLE_STACK_CHECK == TRUE
+ {
+ /* Setting up the base address of the static main thread stack, the
+ symbol must be provided externally.*/
+ extern stkalign_t __main_thread_stack_base__;
+ currp->wabase = &__main_thread_stack_base__;
+ }
+#elif CH_CFG_USE_DYNAMIC == TRUE
+ currp->wabase = NULL;
+#endif
+
+ /* Setting up the caller as current thread.*/
+ currp->state = CH_STATE_CURRENT;
+
+ /* Port layer initialization last because it depend on some of the
+ initializations performed before.*/
+ port_init();
+
+#if CH_DBG_STATISTICS == TRUE
+ /* Starting measurement for this thread.*/
+ chTMStartMeasurementX(&currp->stats);
+#endif
+
+ /* It is alive now.*/
+ chSysEnable();
+
+#if CH_CFG_NO_IDLE_THREAD == FALSE
+ {
+ static const thread_descriptor_t idle_descriptor = {
+ "idle",
+ THD_WORKING_AREA_BASE(ch_idle_thread_wa),
+ THD_WORKING_AREA_END(ch_idle_thread_wa),
+ IDLEPRIO,
+ _idle_thread,
+ NULL
+ };
+
+ /* This thread has the lowest priority in the system, its role is just to
+ serve interrupts in its context while keeping the lowest energy saving
+ mode compatible with the system status.*/
+ (void) chThdCreate(&idle_descriptor);
+ }
+#endif
+}
+
+/**
+ * @brief Halts the system.
+ * @details This function is invoked by the operating system when an
+ * unrecoverable error is detected, for example because a programming
+ * error in the application code that triggers an assertion while
+ * in debug mode.
+ * @note Can be invoked from any system state.
+ *
+ * @param[in] reason pointer to an error string
+ *
+ * @special
+ */
+void chSysHalt(const char *reason) {
+
+ port_disable();
+
+ /* Logging the event.*/
+ _trace_halt(reason);
+
+ /* Pointing to the passed message.*/
+ ch.dbg.panic_msg = reason;
+
+ /* Halt hook code, usually empty.*/
+ CH_CFG_SYSTEM_HALT_HOOK(reason);
+
+ /* Harmless infinite loop.*/
+ while (true) {
+ }
+}
+
+/**
+ * @brief System integrity check.
+ * @details Performs an integrity check of the important ChibiOS/RT data
+ * structures.
+ * @note The appropriate action in case of failure is to halt the system
+ * before releasing the critical zone.
+ * @note If the system is corrupted then one possible outcome of this
+ * function is an exception caused by @p NULL or corrupted pointers
+ * in list elements. Exception vectors must be monitored as well.
+ * @note This function is not used internally, it is up to the
+ * application to define if and where to perform system
+ * checking.
+ * @note Performing all tests at once can be a slow operation and can
+ * degrade the system response time. It is suggested to execute
+ * one test at time and release the critical zone in between tests.
+ *
+ * @param[in] testmask Each bit in this mask is associated to a test to be
+ * performed.
+ * @return The test result.
+ * @retval false The test succeeded.
+ * @retval true Test failed.
+ *
+ * @iclass
+ */
+bool chSysIntegrityCheckI(unsigned testmask) {
+ cnt_t n;
+
+ chDbgCheckClassI();
+
+ /* Ready List integrity check.*/
+ if ((testmask & CH_INTEGRITY_RLIST) != 0U) {
+ thread_t *tp;
+
+ /* Scanning the ready list forward.*/
+ n = (cnt_t)0;
+ tp = ch.rlist.queue.next;
+ while (tp != (thread_t *)&ch.rlist.queue) {
+ n++;
+ tp = tp->queue.next;
+ }
+
+ /* Scanning the ready list backward.*/
+ tp = ch.rlist.queue.prev;
+ while (tp != (thread_t *)&ch.rlist.queue) {
+ n--;
+ tp = tp->queue.prev;
+ }
+
+ /* The number of elements must match.*/
+ if (n != (cnt_t)0) {
+ return true;
+ }
+ }
+
+ /* Timers list integrity check.*/
+ if ((testmask & CH_INTEGRITY_VTLIST) != 0U) {
+ virtual_timer_t * vtp;
+
+ /* Scanning the timers list forward.*/
+ n = (cnt_t)0;
+ vtp = ch.vtlist.next;
+ while (vtp != (virtual_timer_t *)&ch.vtlist) {
+ n++;
+ vtp = vtp->next;
+ }
+
+ /* Scanning the timers list backward.*/
+ vtp = ch.vtlist.prev;
+ while (vtp != (virtual_timer_t *)&ch.vtlist) {
+ n--;
+ vtp = vtp->prev;
+ }
+
+ /* The number of elements must match.*/
+ if (n != (cnt_t)0) {
+ return true;
+ }
+ }
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ if ((testmask & CH_INTEGRITY_REGISTRY) != 0U) {
+ thread_t *tp;
+
+ /* Scanning the ready list forward.*/
+ n = (cnt_t)0;
+ tp = ch.rlist.newer;
+ while (tp != (thread_t *)&ch.rlist) {
+ n++;
+ tp = tp->newer;
+ }
+
+ /* Scanning the ready list backward.*/
+ tp = ch.rlist.older;
+ while (tp != (thread_t *)&ch.rlist) {
+ n--;
+ tp = tp->older;
+ }
+
+ /* The number of elements must match.*/
+ if (n != (cnt_t)0) {
+ return true;
+ }
+ }
+#endif /* CH_CFG_USE_REGISTRY == TRUE */
+
+#if defined(PORT_INTEGRITY_CHECK)
+ if ((testmask & CH_INTEGRITY_PORT) != 0U) {
+ PORT_INTEGRITY_CHECK();
+ }
+#endif
+
+ return false;
+}
+
+/**
+ * @brief Handles time ticks for round robin preemption and timer increments.
+ * @details Decrements the remaining time quantum of the running thread
+ * and preempts it when the quantum is used up. Increments system
+ * time and manages the timers.
+ * @note The frequency of the timer determines the system tick granularity
+ * and, together with the @p CH_CFG_TIME_QUANTUM macro, the round robin
+ * interval.
+ *
+ * @iclass
+ */
+void chSysTimerHandlerI(void) {
+
+ chDbgCheckClassI();
+
+#if CH_CFG_TIME_QUANTUM > 0
+ /* Running thread has not used up quantum yet? */
+ if (currp->preempt > (tslices_t)0) {
+ /* Decrement remaining quantum.*/
+ currp->preempt--;
+ }
+#endif
+#if CH_DBG_THREADS_PROFILING == TRUE
+ currp->time++;
+#endif
+ chVTDoTickI();
+ CH_CFG_SYSTEM_TICK_HOOK();
+}
+
+/**
+ * @brief Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ * from any context. Because its flexibility it is less efficient
+ * than @p chSysLock() which is preferable when the calling context
+ * is known.
+ * @post The system is in a critical zone.
+ *
+ * @return The previous system status, the encoding of this
+ * status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+syssts_t chSysGetStatusAndLockX(void) {
+
+ syssts_t sts = port_get_irq_status();
+ if (port_irq_enabled(sts)) {
+ if (port_is_isr_context()) {
+ chSysLockFromISR();
+ }
+ else {
+ chSysLock();
+ }
+ }
+ return sts;
+}
+
+/**
+ * @brief Restores the specified execution status and leaves a critical zone.
+ * @note A call to @p chSchRescheduleS() is automatically performed
+ * if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts the system status to be restored.
+ *
+ * @xclass
+ */
+void chSysRestoreStatusX(syssts_t sts) {
+
+ if (port_irq_enabled(sts)) {
+ if (port_is_isr_context()) {
+ chSysUnlockFromISR();
+ }
+ else {
+ chSchRescheduleS();
+ chSysUnlock();
+ }
+ }
+}
+
+#if (PORT_SUPPORTS_RT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Realtime window test.
+ * @details This function verifies if the current realtime counter value
+ * lies within the specified range or not. The test takes care
+ * of the realtime counter wrapping to zero on overflow.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ * @note This function is only available if the port layer supports the
+ * option @p PORT_SUPPORTS_RT.
+ *
+ * @param[in] cnt the counter value to be tested
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+bool chSysIsCounterWithinX(rtcnt_t cnt, rtcnt_t start, rtcnt_t end) {
+
+ return (bool)((cnt - start) < (end - start));
+}
+
+/**
+ * @brief Polled delay.
+ * @note The real delay is always few cycles in excess of the specified
+ * value.
+ * @note This function is only available if the port layer supports the
+ * option @p PORT_SUPPORTS_RT.
+ *
+ * @param[in] cycles number of cycles
+ *
+ * @xclass
+ */
+void chSysPolledDelayX(rtcnt_t cycles) {
+ rtcnt_t start = chSysGetRealtimeCounterX();
+ rtcnt_t end = start + cycles;
+
+ while (chSysIsCounterWithinX(chSysGetRealtimeCounterX(), start, end)) {
+ }
+}
+#endif /* PORT_SUPPORTS_RT == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chthreads.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chthreads.c
new file mode 100644
index 0000000000..9fb7761448
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chthreads.c
@@ -0,0 +1,903 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chthreads.c
+ * @brief Threads code.
+ *
+ * @addtogroup threads
+ * @details Threads related APIs and services.
+ * Operation mode
+ * A thread is an abstraction of an independent instructions flow.
+ * In ChibiOS/RT a thread is represented by a "C" function owning
+ * a processor context, state informations and a dedicated stack
+ * area. In this scenario static variables are shared among all
+ * threads while automatic variables are local to the thread.
+ * Operations defined for threads:
+ * - Create, a thread is started on the specified thread
+ * function. This operation is available in multiple variants,
+ * both static and dynamic.
+ * - Exit, a thread terminates by returning from its top
+ * level function or invoking a specific API, the thread can
+ * return a value that can be retrieved by other threads.
+ * - Wait, a thread waits for the termination of another
+ * thread and retrieves its return value.
+ * - Resume, a thread created in suspended state is started.
+ * - Sleep, the execution of a thread is suspended for the
+ * specified amount of time or the specified future absolute time
+ * is reached.
+ * - SetPriority, a thread changes its own priority level.
+ * - Yield, a thread voluntarily renounces to its time slot.
+ * .
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes a thread structure.
+ * @note This is an internal functions, do not use it in application code.
+ *
+ * @param[in] tp pointer to the thread
+ * @param[in] name thread name
+ * @param[in] prio the priority level for the new thread
+ * @return The same thread pointer passed as parameter.
+ *
+ * @notapi
+ */
+thread_t *_thread_init(thread_t *tp, const char *name, tprio_t prio) {
+
+ tp->prio = prio;
+ tp->state = CH_STATE_WTSTART;
+ tp->flags = CH_FLAG_MODE_STATIC;
+#if CH_CFG_TIME_QUANTUM > 0
+ tp->preempt = (tslices_t)CH_CFG_TIME_QUANTUM;
+#endif
+#if CH_CFG_USE_MUTEXES == TRUE
+ tp->realprio = prio;
+ tp->mtxlist = NULL;
+#endif
+#if CH_CFG_USE_EVENTS == TRUE
+ tp->epending = (eventmask_t)0;
+#endif
+#if CH_DBG_THREADS_PROFILING == TRUE
+ tp->time = (systime_t)0;
+#endif
+#if CH_CFG_USE_REGISTRY == TRUE
+ tp->refs = (trefs_t)1;
+ tp->name = name;
+ REG_INSERT(tp);
+#else
+ (void)name;
+#endif
+#if CH_CFG_USE_WAITEXIT == TRUE
+ list_init(&tp->waiting);
+#endif
+#if CH_CFG_USE_MESSAGES == TRUE
+ queue_init(&tp->msgqueue);
+#endif
+#if CH_DBG_STATISTICS == TRUE
+ chTMObjectInit(&tp->stats);
+#endif
+ CH_CFG_THREAD_INIT_HOOK(tp);
+ return tp;
+}
+
+#if (CH_DBG_FILL_THREADS == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Memory fill utility.
+ *
+ * @param[in] startp first address to fill
+ * @param[in] endp last address to fill +1
+ * @param[in] v filler value
+ *
+ * @notapi
+ */
+void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) {
+
+ while (startp < endp) {
+ *startp++ = v;
+ }
+}
+#endif /* CH_DBG_FILL_THREADS */
+
+/**
+ * @brief Creates a new thread into a static memory area.
+ * @details The new thread is initialized but not inserted in the ready list,
+ * the initial state is @p CH_STATE_WTSTART.
+ * @post The created thread has a reference counter set to one, it is
+ * caller responsibility to call @p chThdRelease() or @p chthdWait()
+ * in order to release the reference. The thread persists in the
+ * registry until its reference counter reaches zero.
+ * @post The initialized thread can be subsequently started by invoking
+ * @p chThdStart(), @p chThdStartI() or @p chSchWakeupS()
+ * depending on the execution context.
+ * @note A thread can terminate by calling @p chThdExit() or by simply
+ * returning from its main function.
+ * @note Threads created using this function do not obey to the
+ * @p CH_DBG_FILL_THREADS debug option because it would keep
+ * the kernel locked for too much time.
+ *
+ * @param[out] tdp pointer to the thread descriptor
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ *
+ * @iclass
+ */
+thread_t *chThdCreateSuspendedI(const thread_descriptor_t *tdp) {
+ thread_t *tp;
+
+ chDbgCheckClassI();
+ chDbgCheck(tdp != NULL);
+ chDbgCheck(MEM_IS_ALIGNED(tdp->wbase, PORT_WORKING_AREA_ALIGN) &&
+ MEM_IS_ALIGNED(tdp->wend, PORT_STACK_ALIGN) &&
+ (tdp->wend > tdp->wbase) &&
+ (((size_t)tdp->wend - (size_t)tdp->wbase) >= THD_WORKING_AREA_SIZE(0)));
+ chDbgCheck((tdp->prio <= HIGHPRIO) && (tdp->funcp != NULL));
+
+ /* The thread structure is laid out in the upper part of the thread
+ workspace. The thread position structure is aligned to the required
+ stack alignment because it represents the stack top.*/
+ tp = (thread_t *)((uint8_t *)tdp->wend -
+ MEM_ALIGN_NEXT(sizeof (thread_t), PORT_STACK_ALIGN));
+
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || (CH_CFG_USE_DYNAMIC == TRUE)
+ /* Stack boundary.*/
+ tp->wabase = tdp->wbase;
+#endif
+
+ /* Setting up the port-dependent part of the working area.*/
+ PORT_SETUP_CONTEXT(tp, tdp->wbase, tp, tdp->funcp, tdp->arg);
+
+ /* The driver object is initialized but not started.*/
+ return _thread_init(tp, tdp->name, tdp->prio);
+}
+
+/**
+ * @brief Creates a new thread into a static memory area.
+ * @details The new thread is initialized but not inserted in the ready list,
+ * the initial state is @p CH_STATE_WTSTART.
+ * @post The created thread has a reference counter set to one, it is
+ * caller responsibility to call @p chThdRelease() or @p chthdWait()
+ * in order to release the reference. The thread persists in the
+ * registry until its reference counter reaches zero.
+ * @post The initialized thread can be subsequently started by invoking
+ * @p chThdStart(), @p chThdStartI() or @p chSchWakeupS()
+ * depending on the execution context.
+ * @note A thread can terminate by calling @p chThdExit() or by simply
+ * returning from its main function.
+ *
+ * @param[out] tdp pointer to the thread descriptor
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ *
+ * @api
+ */
+thread_t *chThdCreateSuspended(const thread_descriptor_t *tdp) {
+ thread_t *tp;
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ chDbgAssert(chRegFindThreadByWorkingArea(tdp->wbase) == NULL,
+ "working area in use");
+#endif
+
+#if CH_DBG_FILL_THREADS == TRUE
+ _thread_memfill((uint8_t *)tdp->wbase,
+ (uint8_t *)tdp->wend,
+ CH_DBG_STACK_FILL_VALUE);
+#endif
+
+ chSysLock();
+ tp = chThdCreateSuspendedI(tdp);
+ chSysUnlock();
+
+ return tp;
+}
+
+/**
+ * @brief Creates a new thread into a static memory area.
+ * @details The new thread is initialized and make ready to execute.
+ * @post The created thread has a reference counter set to one, it is
+ * caller responsibility to call @p chThdRelease() or @p chthdWait()
+ * in order to release the reference. The thread persists in the
+ * registry until its reference counter reaches zero.
+ * @post The initialized thread can be subsequently started by invoking
+ * @p chThdStart(), @p chThdStartI() or @p chSchWakeupS()
+ * depending on the execution context.
+ * @note A thread can terminate by calling @p chThdExit() or by simply
+ * returning from its main function.
+ * @note Threads created using this function do not obey to the
+ * @p CH_DBG_FILL_THREADS debug option because it would keep
+ * the kernel locked for too much time.
+ *
+ * @param[out] tdp pointer to the thread descriptor
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ *
+ * @iclass
+ */
+thread_t *chThdCreateI(const thread_descriptor_t *tdp) {
+
+ return chSchReadyI(chThdCreateSuspendedI(tdp));
+}
+
+/**
+ * @brief Creates a new thread into a static memory area.
+ * @details The new thread is initialized and make ready to execute.
+ * @post The created thread has a reference counter set to one, it is
+ * caller responsibility to call @p chThdRelease() or @p chthdWait()
+ * in order to release the reference. The thread persists in the
+ * registry until its reference counter reaches zero.
+ * @note A thread can terminate by calling @p chThdExit() or by simply
+ * returning from its main function.
+ *
+ * @param[out] tdp pointer to the thread descriptor
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ *
+ * @iclass
+ */
+thread_t *chThdCreate(const thread_descriptor_t *tdp) {
+ thread_t *tp;
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ chDbgAssert(chRegFindThreadByWorkingArea(tdp->wbase) == NULL,
+ "working area in use");
+#endif
+
+#if CH_DBG_FILL_THREADS == TRUE
+ _thread_memfill((uint8_t *)tdp->wbase,
+ (uint8_t *)tdp->wend,
+ CH_DBG_STACK_FILL_VALUE);
+#endif
+
+ chSysLock();
+ tp = chThdCreateSuspendedI(tdp);
+ chSchWakeupS(tp, MSG_OK);
+ chSysUnlock();
+
+ return tp;
+}
+
+/**
+ * @brief Creates a new thread into a static memory area.
+ * @post The created thread has a reference counter set to one, it is
+ * caller responsibility to call @p chThdRelease() or @p chthdWait()
+ * in order to release the reference. The thread persists in the
+ * registry until its reference counter reaches zero.
+ * @note A thread can terminate by calling @p chThdExit() or by simply
+ * returning from its main function.
+ *
+ * @param[out] wsp pointer to a working area dedicated to the thread stack
+ * @param[in] size size of the working area
+ * @param[in] prio the priority level for the new thread
+ * @param[in] pf the thread function
+ * @param[in] arg an argument passed to the thread function. It can be
+ * @p NULL.
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ *
+ * @api
+ */
+thread_t *chThdCreateStatic(void *wsp, size_t size,
+ tprio_t prio, tfunc_t pf, void *arg) {
+ thread_t *tp;
+
+ chDbgCheck((wsp != NULL) &&
+ MEM_IS_ALIGNED(wsp, PORT_WORKING_AREA_ALIGN) &&
+ (size >= THD_WORKING_AREA_SIZE(0)) &&
+ MEM_IS_ALIGNED(size, PORT_STACK_ALIGN) &&
+ (prio <= HIGHPRIO) && (pf != NULL));
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ chDbgAssert(chRegFindThreadByWorkingArea(wsp) == NULL,
+ "working area in use");
+#endif
+
+#if CH_DBG_FILL_THREADS == TRUE
+ _thread_memfill((uint8_t *)wsp,
+ (uint8_t *)wsp + size,
+ CH_DBG_STACK_FILL_VALUE);
+#endif
+
+ chSysLock();
+
+ /* The thread structure is laid out in the upper part of the thread
+ workspace. The thread position structure is aligned to the required
+ stack alignment because it represents the stack top.*/
+ tp = (thread_t *)((uint8_t *)wsp + size -
+ MEM_ALIGN_NEXT(sizeof (thread_t), PORT_STACK_ALIGN));
+
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || (CH_CFG_USE_DYNAMIC == TRUE)
+ /* Stack boundary.*/
+ tp->wabase = (stkalign_t *)wsp;
+#endif
+
+ /* Setting up the port-dependent part of the working area.*/
+ PORT_SETUP_CONTEXT(tp, wsp, tp, pf, arg);
+
+ tp = _thread_init(tp, "noname", prio);
+
+ /* Starting the thread immediately.*/
+ chSchWakeupS(tp, MSG_OK);
+ chSysUnlock();
+
+ return tp;
+}
+
+/**
+ * @brief Resumes a thread created with @p chThdCreateI().
+ *
+ * @param[in] tp pointer to the thread
+ * @return The pointer to the @p thread_t structure allocated for
+ * the thread into the working space area.
+ *
+ * @api
+ */
+thread_t *chThdStart(thread_t *tp) {
+
+ chSysLock();
+ chDbgAssert(tp->state == CH_STATE_WTSTART, "wrong state");
+ chSchWakeupS(tp, MSG_OK);
+ chSysUnlock();
+
+ return tp;
+}
+
+#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Adds a reference to a thread object.
+ * @pre The configuration option @p CH_CFG_USE_DYNAMIC must be enabled in
+ * order to use this function.
+ *
+ * @param[in] tp pointer to the thread
+ * @return The same thread pointer passed as parameter
+ * representing the new reference.
+ *
+ * @api
+ */
+thread_t *chThdAddRef(thread_t *tp) {
+
+ chSysLock();
+ chDbgAssert(tp->refs < (trefs_t)255, "too many references");
+ tp->refs++;
+ chSysUnlock();
+
+ return tp;
+}
+
+/**
+ * @brief Releases a reference to a thread object.
+ * @details If the references counter reaches zero and the thread
+ * is in the @p CH_STATE_FINAL state then the thread's memory is
+ * returned to the proper allocator and the thread is removed
+ * from the registry.
+ * Threads whose counter reaches zero and are still active become
+ * "detached" and will be removed from registry on termination.
+ * @pre The configuration option @p CH_CFG_USE_DYNAMIC must be enabled in
+ * order to use this function.
+ * @note Static threads are not affected.
+ *
+ * @param[in] tp pointer to the thread
+ *
+ * @api
+ */
+void chThdRelease(thread_t *tp) {
+
+ chSysLock();
+ chDbgAssert(tp->refs > (trefs_t)0, "not referenced");
+ tp->refs--;
+
+ /* If the references counter reaches zero and the thread is in its
+ terminated state then the memory can be returned to the proper
+ allocator.*/
+ if ((tp->refs == (trefs_t)0) && (tp->state == CH_STATE_FINAL)) {
+ REG_REMOVE(tp);
+ chSysUnlock();
+
+#if CH_CFG_USE_DYNAMIC == TRUE
+ switch (tp->flags & CH_FLAG_MODE_MASK) {
+#if CH_CFG_USE_HEAP == TRUE
+ case CH_FLAG_MODE_HEAP:
+ chHeapFree(chThdGetWorkingAreaX(tp));
+ break;
+#endif
+#if CH_CFG_USE_MEMPOOLS == TRUE
+ case CH_FLAG_MODE_MPOOL:
+ chPoolFree(tp->mpool, chThdGetWorkingAreaX(tp));
+ break;
+#endif
+ default:
+ /* Nothing else to do for static threads.*/
+ break;
+ }
+#endif /* CH_CFG_USE_DYNAMIC == TRUE */
+ return;
+ }
+ chSysUnlock();
+}
+#endif /* CH_CFG_USE_REGISTRY == TRUE */
+
+/**
+ * @brief Terminates the current thread.
+ * @details The thread goes in the @p CH_STATE_FINAL state holding the
+ * specified exit status code, other threads can retrieve the
+ * exit status code by invoking the function @p chThdWait().
+ * @post Eventual code after this function will never be executed,
+ * this function never returns. The compiler has no way to
+ * know this so do not assume that the compiler would remove
+ * the dead code.
+ *
+ * @param[in] msg thread exit code
+ *
+ * @api
+ */
+void chThdExit(msg_t msg) {
+
+ chSysLock();
+ chThdExitS(msg);
+ /* The thread never returns here.*/
+}
+
+/**
+ * @brief Terminates the current thread.
+ * @details The thread goes in the @p CH_STATE_FINAL state holding the
+ * specified exit status code, other threads can retrieve the
+ * exit status code by invoking the function @p chThdWait().
+ * @post Exiting a non-static thread that does not have references
+ * (detached) causes the thread to remain in the registry.
+ * It can only be removed by performing a registry scan operation.
+ * @post Eventual code after this function will never be executed,
+ * this function never returns. The compiler has no way to
+ * know this so do not assume that the compiler would remove
+ * the dead code.
+ *
+ * @param[in] msg thread exit code
+ *
+ * @sclass
+ */
+void chThdExitS(msg_t msg) {
+ thread_t *tp = currp;
+
+ /* Storing exit message.*/
+ tp->u.exitcode = msg;
+
+ /* Exit handler hook.*/
+ CH_CFG_THREAD_EXIT_HOOK(tp);
+
+#if CH_CFG_USE_WAITEXIT == TRUE
+ /* Waking up any waiting thread.*/
+ while (list_notempty(&tp->waiting)) {
+ (void) chSchReadyI(list_remove(&tp->waiting));
+ }
+#endif
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ /* Static threads with no references are immediately removed from the
+ registry because there is no memory to recover.*/
+#if CH_CFG_USE_DYNAMIC == TRUE
+ if ((tp->refs == (trefs_t)0) &&
+ ((tp->flags & CH_FLAG_MODE_MASK) == CH_FLAG_MODE_STATIC)) {
+ REG_REMOVE(tp);
+ }
+#else
+ if (tp->refs == (trefs_t)0) {
+ REG_REMOVE(tp);
+ }
+#endif
+#endif
+
+ /* Going into final state.*/
+ chSchGoSleepS(CH_STATE_FINAL);
+
+ /* The thread never returns here.*/
+ chDbgAssert(false, "zombies apocalypse");
+}
+
+#if (CH_CFG_USE_WAITEXIT == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Blocks the execution of the invoking thread until the specified
+ * thread terminates then the exit code is returned.
+ * @details This function waits for the specified thread to terminate then
+ * decrements its reference counter, if the counter reaches zero then
+ * the thread working area is returned to the proper allocator and
+ * the thread is removed from registry.
+ * @pre The configuration option @p CH_CFG_USE_WAITEXIT must be enabled in
+ * order to use this function.
+ * @post Enabling @p chThdWait() requires 2-4 (depending on the
+ * architecture) extra bytes in the @p thread_t structure.
+ * @note If @p CH_CFG_USE_DYNAMIC is not specified this function just waits
+ * for the thread termination, no memory allocators are involved.
+ *
+ * @param[in] tp pointer to the thread
+ * @return The exit code from the terminated thread.
+ *
+ * @api
+ */
+msg_t chThdWait(thread_t *tp) {
+ msg_t msg;
+
+ chDbgCheck(tp != NULL);
+
+ chSysLock();
+ chDbgAssert(tp != currp, "waiting self");
+#if CH_CFG_USE_REGISTRY == TRUE
+ chDbgAssert(tp->refs > (trefs_t)0, "no references");
+#endif
+
+ if (tp->state != CH_STATE_FINAL) {
+ list_insert(currp, &tp->waiting);
+ chSchGoSleepS(CH_STATE_WTEXIT);
+ }
+ msg = tp->u.exitcode;
+ chSysUnlock();
+
+#if CH_CFG_USE_REGISTRY == TRUE
+ /* Releasing a reference to the thread.*/
+ chThdRelease(tp);
+#endif
+
+ return msg;
+}
+#endif /* CH_CFG_USE_WAITEXIT */
+
+/**
+ * @brief Changes the running thread priority level then reschedules if
+ * necessary.
+ * @note The function returns the real thread priority regardless of the
+ * current priority that could be higher than the real priority
+ * because the priority inheritance mechanism.
+ *
+ * @param[in] newprio the new priority level of the running thread
+ * @return The old priority level.
+ *
+ * @api
+ */
+tprio_t chThdSetPriority(tprio_t newprio) {
+ tprio_t oldprio;
+
+ chDbgCheck(newprio <= HIGHPRIO);
+
+ chSysLock();
+#if CH_CFG_USE_MUTEXES == TRUE
+ oldprio = currp->realprio;
+ if ((currp->prio == currp->realprio) || (newprio > currp->prio)) {
+ currp->prio = newprio;
+ }
+ currp->realprio = newprio;
+#else
+ oldprio = currp->prio;
+ currp->prio = newprio;
+#endif
+ chSchRescheduleS();
+ chSysUnlock();
+
+ return oldprio;
+}
+
+/**
+ * @brief Requests a thread termination.
+ * @pre The target thread must be written to invoke periodically
+ * @p chThdShouldTerminate() and terminate cleanly if it returns
+ * @p true.
+ * @post The specified thread will terminate after detecting the termination
+ * condition.
+ *
+ * @param[in] tp pointer to the thread
+ *
+ * @api
+ */
+void chThdTerminate(thread_t *tp) {
+
+ chSysLock();
+ tp->flags |= CH_FLAG_TERMINATE;
+ chSysUnlock();
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ *
+ * @api
+ */
+void chThdSleep(systime_t time) {
+
+ chSysLock();
+ chThdSleepS(time);
+ chSysUnlock();
+}
+
+/**
+ * @brief Suspends the invoking thread until the system time arrives to the
+ * specified value.
+ * @note The function has no concept of "past", all specifiable times
+ * are in the future, this means that if you call this function
+ * exceeding your calculated intervals then the function will
+ * return in a far future time, not immediately.
+ * @see chThdSleepUntilWindowed()
+ *
+ * @param[in] time absolute system time
+ *
+ * @api
+ */
+void chThdSleepUntil(systime_t time) {
+
+ chSysLock();
+ time -= chVTGetSystemTimeX();
+ if (time > (systime_t)0) {
+ chThdSleepS(time);
+ }
+ chSysUnlock();
+}
+
+/**
+ * @brief Suspends the invoking thread until the system time arrives to the
+ * specified value.
+ * @note The system time is assumed to be between @p prev and @p time
+ * else the call is assumed to have been called outside the
+ * allowed time interval, in this case no sleep is performed.
+ * @see chThdSleepUntil()
+ *
+ * @param[in] prev absolute system time of the previous deadline
+ * @param[in] next absolute system time of the next deadline
+ * @return the @p next parameter
+ *
+ * @api
+ */
+systime_t chThdSleepUntilWindowed(systime_t prev, systime_t next) {
+ systime_t time;
+
+ chSysLock();
+ time = chVTGetSystemTimeX();
+ if (chVTIsTimeWithinX(time, prev, next)) {
+ chThdSleepS(next - time);
+ }
+ chSysUnlock();
+
+ return next;
+}
+
+/**
+ * @brief Yields the time slot.
+ * @details Yields the CPU control to the next thread in the ready list with
+ * equal priority, if any.
+ *
+ * @api
+ */
+void chThdYield(void) {
+
+ chSysLock();
+ chSchDoYieldS();
+ chSysUnlock();
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @return The wake up message.
+ *
+ * @sclass
+ */
+msg_t chThdSuspendS(thread_reference_t *trp) {
+ thread_t *tp = chThdGetSelfX();
+
+ chDbgAssert(*trp == NULL, "not NULL");
+
+ *trp = tp;
+ tp->u.wttrp = trp;
+ chSchGoSleepS(CH_STATE_SUSPENDED);
+
+ return chThdGetSelfX()->u.rdymsg;
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The wake up message.
+ * @retval MSG_TIMEOUT if the operation timed out.
+ *
+ * @sclass
+ */
+msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) {
+ thread_t *tp = chThdGetSelfX();
+
+ chDbgAssert(*trp == NULL, "not NULL");
+
+ if (TIME_IMMEDIATE == timeout) {
+ return MSG_TIMEOUT;
+ }
+
+ *trp = tp;
+ tp->u.wttrp = trp;
+
+ return chSchGoSleepTimeoutS(CH_STATE_SUSPENDED, timeout);
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must not reschedule because it can be called from
+ * ISR context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void chThdResumeI(thread_reference_t *trp, msg_t msg) {
+
+ if (*trp != NULL) {
+ thread_t *tp = *trp;
+
+ chDbgAssert(tp->state == CH_STATE_SUSPENDED, "not CH_STATE_SUSPENDED");
+
+ *trp = NULL;
+ tp->u.rdymsg = msg;
+ (void) chSchReadyI(tp);
+ }
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void chThdResumeS(thread_reference_t *trp, msg_t msg) {
+
+ if (*trp != NULL) {
+ thread_t *tp = *trp;
+
+ chDbgAssert(tp->state == CH_STATE_SUSPENDED, "not CH_STATE_SUSPENDED");
+
+ *trp = NULL;
+ chSchWakeupS(tp, msg);
+ }
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @api
+ */
+void chThdResume(thread_reference_t *trp, msg_t msg) {
+
+ chSysLock();
+ chThdResumeS(trp, msg);
+ chSysUnlock();
+}
+
+/**
+ * @brief Enqueues the caller thread on a threads queue object.
+ * @details The caller thread is enqueued and put to sleep until it is
+ * dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] timeout the timeout in system ticks, the special values are
+ * handled as follow:
+ * - @a TIME_INFINITE the thread enters an infinite sleep
+ * state.
+ * - @a TIME_IMMEDIATE the thread is not enqueued and
+ * the function returns @p MSG_TIMEOUT as if a timeout
+ * occurred.
+ * .
+ * @return The message from @p osalQueueWakeupOneI() or
+ * @p osalQueueWakeupAllI() functions.
+ * @retval MSG_TIMEOUT if the thread has not been dequeued within the
+ * specified timeout or if the function has been
+ * invoked with @p TIME_IMMEDIATE as timeout
+ * specification.
+ *
+ * @sclass
+ */
+msg_t chThdEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) {
+
+ if (TIME_IMMEDIATE == timeout) {
+ return MSG_TIMEOUT;
+ }
+
+ queue_insert(currp, tqp);
+
+ return chSchGoSleepTimeoutS(CH_STATE_QUEUED, timeout);
+}
+
+/**
+ * @brief Dequeues and wakes up one thread from the threads queue object,
+ * if any.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void chThdDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+
+ if (queue_notempty(tqp)) {
+ chThdDoDequeueNextI(tqp, msg);
+ }
+}
+
+/**
+ * @brief Dequeues and wakes up all threads from the threads queue object.
+ *
+ * @param[in] tqp pointer to the threads queue object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void chThdDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+
+ while (queue_notempty(tqp)) {
+ chThdDoDequeueNextI(tqp, msg);
+ }
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chtm.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chtm.c
new file mode 100644
index 0000000000..b4e002e83e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chtm.c
@@ -0,0 +1,156 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chtm.c
+ * @brief Time Measurement module code.
+ *
+ * @addtogroup time_measurement
+ * @details Time Measurement APIs and services.
+ * @{
+ */
+
+#include "ch.h"
+
+#if (CH_CFG_USE_TM == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+static inline void tm_stop(time_measurement_t *tmp,
+ rtcnt_t now,
+ rtcnt_t offset) {
+
+ tmp->n++;
+ tmp->last = (now - tmp->last) - offset;
+ tmp->cumulative += (rttime_t)tmp->last;
+ if (tmp->last > tmp->worst) {
+ tmp->worst = tmp->last;
+ }
+ if (tmp->last < tmp->best) {
+ tmp->best = tmp->last;
+ }
+}
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the time measurement unit.
+ *
+ * @init
+ */
+void _tm_init(void) {
+ time_measurement_t tm;
+
+ /* Time Measurement subsystem calibration, it does a null measurement
+ and calculates the call overhead which is subtracted to real
+ measurements.*/
+ ch.tm.offset = (rtcnt_t)0;
+ chTMObjectInit(&tm);
+ chTMStartMeasurementX(&tm);
+ chTMStopMeasurementX(&tm);
+ ch.tm.offset = tm.last;
+}
+
+/**
+ * @brief Initializes a @p TimeMeasurement object.
+ *
+ * @param[out] tmp pointer to a @p TimeMeasurement structure
+ *
+ * @init
+ */
+void chTMObjectInit(time_measurement_t *tmp) {
+
+ tmp->best = (rtcnt_t)-1;
+ tmp->worst = (rtcnt_t)0;
+ tmp->last = (rtcnt_t)0;
+ tmp->n = (ucnt_t)0;
+ tmp->cumulative = (rttime_t)0;
+}
+
+/**
+ * @brief Starts a measurement.
+ * @pre The @p time_measurement_t structure must be initialized.
+ *
+ * @param[in,out] tmp pointer to a @p TimeMeasurement structure
+ *
+ * @xclass
+ */
+NOINLINE void chTMStartMeasurementX(time_measurement_t *tmp) {
+
+ tmp->last = chSysGetRealtimeCounterX();
+}
+
+/**
+ * @brief Stops a measurement.
+ * @pre The @p time_measurement_t structure must be initialized.
+ *
+ * @param[in,out] tmp pointer to a @p time_measurement_t structure
+ *
+ * @xclass
+ */
+NOINLINE void chTMStopMeasurementX(time_measurement_t *tmp) {
+
+ tm_stop(tmp, chSysGetRealtimeCounterX(), ch.tm.offset);
+}
+
+/**
+ * @brief Stops a measurement and chains to the next one using the same time
+ * stamp.
+ *
+ * @param[in,out] tmp1 pointer to the @p time_measurement_t structure to be
+ * stopped
+ * @param[in,out] tmp2 pointer to the @p time_measurement_t structure to be
+ * started
+ *
+ *
+ * @xclass
+ */
+NOINLINE void chTMChainMeasurementToX(time_measurement_t *tmp1,
+ time_measurement_t *tmp2) {
+
+ /* Starts new measurement.*/
+ tmp2->last = chSysGetRealtimeCounterX();
+
+ /* Stops previous measurement using the same time stamp.*/
+ tm_stop(tmp1, tmp2->last, (rtcnt_t)0);
+}
+
+#endif /* CH_CFG_USE_TM == TRUE */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chtrace.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chtrace.c
new file mode 100644
index 0000000000..9daab4d54e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chtrace.c
@@ -0,0 +1,265 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chtrace.c
+ * @brief Tracer code.
+ *
+ * @addtogroup trace
+ * @details System events tracing service.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+#if (CH_DBG_TRACE_MASK != CH_DBG_TRACE_MASK_DISABLED) || defined(__DOXYGEN__)
+/**
+ * @brief Writes a time stamp and increases the trace buffer pointer.
+ *
+ * @notapi
+ */
+static NOINLINE void trace_next(void) {
+
+ ch.dbg.trace_buffer.ptr->time = chVTGetSystemTimeX();
+#if PORT_SUPPORTS_RT == TRUE
+ ch.dbg.trace_buffer.ptr->rtstamp = chSysGetRealtimeCounterX();
+#else
+ ch.dbg.trace_buffer.ptr->rtstamp = (rtcnt_t)0;
+#endif
+
+ /* Trace hook, useful in order to interface debug tools.*/
+ CH_CFG_TRACE_HOOK(ch.dbg.trace_buffer.ptr);
+
+ if (++ch.dbg.trace_buffer.ptr >=
+ &ch.dbg.trace_buffer.buffer[CH_DBG_TRACE_BUFFER_SIZE]) {
+ ch.dbg.trace_buffer.ptr = &ch.dbg.trace_buffer.buffer[0];
+ }
+}
+#endif
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+#if (CH_DBG_TRACE_MASK != CH_DBG_TRACE_MASK_DISABLED) || defined(__DOXYGEN__)
+/**
+ * @brief Trace circular buffer subsystem initialization.
+ * @note Internal use only.
+ */
+void _trace_init(void) {
+ unsigned i;
+
+ ch.dbg.trace_buffer.suspended = (uint16_t)~CH_DBG_TRACE_MASK;
+ ch.dbg.trace_buffer.size = CH_DBG_TRACE_BUFFER_SIZE;
+ ch.dbg.trace_buffer.ptr = &ch.dbg.trace_buffer.buffer[0];
+ for (i = 0U; i < (unsigned)CH_DBG_TRACE_BUFFER_SIZE; i++) {
+ ch.dbg.trace_buffer.buffer[i].type = CH_TRACE_TYPE_UNUSED;
+ }
+}
+
+/**
+ * @brief Inserts in the circular debug trace buffer a context switch record.
+ *
+ * @param[in] ntp the thread being switched in
+ * @param[in] otp the thread being switched out
+ *
+ * @notapi
+ */
+void _trace_switch(thread_t *ntp, thread_t *otp) {
+
+ (void)ntp;
+
+ if ((ch.dbg.trace_buffer.suspended & CH_DBG_TRACE_MASK_SWITCH) == 0U) {
+ ch.dbg.trace_buffer.ptr->type = CH_TRACE_TYPE_SWITCH;
+ ch.dbg.trace_buffer.ptr->state = (uint8_t)otp->state;
+ ch.dbg.trace_buffer.ptr->u.sw.ntp = currp;
+ ch.dbg.trace_buffer.ptr->u.sw.wtobjp = otp->u.wtobjp;
+ trace_next();
+ }
+}
+
+/**
+ * @brief Inserts in the circular debug trace buffer an ISR-enter record.
+ *
+ * @param[in] isr name of the isr
+ *
+ * @notapi
+ */
+void _trace_isr_enter(const char *isr) {
+
+ if ((ch.dbg.trace_buffer.suspended & CH_DBG_TRACE_MASK_ISR) == 0U) {
+ port_lock_from_isr();
+ ch.dbg.trace_buffer.ptr->type = CH_TRACE_TYPE_ISR_ENTER;
+ ch.dbg.trace_buffer.ptr->state = 0U;
+ ch.dbg.trace_buffer.ptr->u.isr.name = isr;
+ trace_next();
+ port_unlock_from_isr();
+ }
+}
+
+/**
+ * @brief Inserts in the circular debug trace buffer an ISR-leave record.
+ *
+ * @param[in] isr name of the isr
+ *
+ * @notapi
+ */
+void _trace_isr_leave(const char *isr) {
+
+ if ((ch.dbg.trace_buffer.suspended & CH_DBG_TRACE_MASK_ISR) == 0U) {
+ port_lock_from_isr();
+ ch.dbg.trace_buffer.ptr->type = CH_TRACE_TYPE_ISR_LEAVE;
+ ch.dbg.trace_buffer.ptr->state = 0U;
+ ch.dbg.trace_buffer.ptr->u.isr.name = isr;
+ trace_next();
+ port_unlock_from_isr();
+ }
+}
+
+/**
+ * @brief Inserts in the circular debug trace buffer an halt record.
+ *
+ * @param[in] reason the halt error string
+ *
+ * @notapi
+ */
+void _trace_halt(const char *reason) {
+
+ if ((ch.dbg.trace_buffer.suspended & CH_DBG_TRACE_MASK_HALT) == 0U) {
+ ch.dbg.trace_buffer.ptr->type = CH_TRACE_TYPE_HALT;
+ ch.dbg.trace_buffer.ptr->state = 0;
+ ch.dbg.trace_buffer.ptr->u.halt.reason = reason;
+ trace_next();
+ }
+}
+
+/**
+ * @brief Adds an user trace record to the trace buffer.
+ *
+ * @param[in] up1 user parameter 1
+ * @param[in] up2 user parameter 2
+ *
+ * @iclass
+ */
+void chDbgWriteTraceI(void *up1, void *up2) {
+
+ chDbgCheckClassI();
+
+ if ((ch.dbg.trace_buffer.suspended & CH_DBG_TRACE_MASK_USER) == 0U) {
+ ch.dbg.trace_buffer.ptr->type = CH_TRACE_TYPE_USER;
+ ch.dbg.trace_buffer.ptr->state = 0;
+ ch.dbg.trace_buffer.ptr->u.user.up1 = up1;
+ ch.dbg.trace_buffer.ptr->u.user.up2 = up2;
+ trace_next();
+ }
+}
+
+/**
+ * @brief Adds an user trace record to the trace buffer.
+ *
+ * @param[in] up1 user parameter 1
+ * @param[in] up2 user parameter 2
+ *
+ * @api
+ */
+void chDbgWriteTrace(void *up1, void *up2) {
+
+ chSysLock();
+ chDbgWriteTraceI(up1, up2);
+ chSysUnlock();
+}
+
+/**
+ * @brief Suspends one or more trace events.
+ *
+ * @param[in] mask mask of the trace events to be suspended
+ *
+ * @iclass
+ */
+void chDbgSuspendTraceI(uint16_t mask) {
+
+ chDbgCheckClassI();
+
+ ch.dbg.trace_buffer.suspended |= mask;
+}
+
+/**
+ * @brief Suspends one or more trace events.
+ *
+ * @param[in] mask mask of the trace events to be suspended
+ *
+ * @api
+ */
+void chDbgSuspendTrace(uint16_t mask) {
+
+ chSysLock();
+ chDbgSuspendTraceI(mask);
+ chSysUnlock();
+}
+
+/**
+ * @brief Resumes one or more trace events.
+ *
+ * @param[in] mask mask of the trace events to be resumed
+ *
+ * @iclass
+ */
+void chDbgResumeTraceI(uint16_t mask) {
+
+ chDbgCheckClassI();
+
+ ch.dbg.trace_buffer.suspended &= ~mask;
+}
+
+/**
+ * @brief Resumes one or more trace events.
+ *
+ * @param[in] mask mask of the trace events to be resumed
+ *
+ * @api
+ */
+void chDbgResumeTrace(uint16_t mask) {
+
+ chSysLock();
+ chDbgResumeTraceI(mask);
+ chSysUnlock();
+}
+#endif /* CH_DBG_TRACE_MASK != CH_DBG_TRACE_MASK_DISABLED */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chvt.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chvt.c
new file mode 100644
index 0000000000..d1d9a735ed
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/src/chvt.c
@@ -0,0 +1,275 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chvt.c
+ * @brief Time and Virtual Timers module code.
+ *
+ * @addtogroup time
+ * @details Time and Virtual Timers related APIs and services.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Virtual Timers initialization.
+ * @note Internal use only.
+ *
+ * @notapi
+ */
+void _vt_init(void) {
+
+ ch.vtlist.next = (virtual_timer_t *)&ch.vtlist;
+ ch.vtlist.prev = (virtual_timer_t *)&ch.vtlist;
+ ch.vtlist.delta = (systime_t)-1;
+#if CH_CFG_ST_TIMEDELTA == 0
+ ch.vtlist.systime = (systime_t)0;
+#else /* CH_CFG_ST_TIMEDELTA > 0 */
+ ch.vtlist.lasttime = (systime_t)0;
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+}
+
+/**
+ * @brief Enables a virtual timer.
+ * @details The timer is enabled and programmed to trigger after the delay
+ * specified as parameter.
+ * @pre The timer must not be already armed before calling this function.
+ * @note The callback function is invoked from interrupt context.
+ *
+ * @param[out] vtp the @p virtual_timer_t structure pointer
+ * @param[in] delay the number of ticks before the operation timeouts, the
+ * special values are handled as follow:
+ * - @a TIME_INFINITE is allowed but interpreted as a
+ * normal time specification.
+ * - @a TIME_IMMEDIATE this value is not allowed.
+ * .
+ * @param[in] vtfunc the timer callback function. After invoking the
+ * callback the timer is disabled and the structure can
+ * be disposed or reused.
+ * @param[in] par a parameter that will be passed to the callback
+ * function
+ *
+ * @iclass
+ */
+void chVTDoSetI(virtual_timer_t *vtp, systime_t delay,
+ vtfunc_t vtfunc, void *par) {
+ virtual_timer_t *p;
+ systime_t delta;
+
+ chDbgCheckClassI();
+ chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (delay != TIME_IMMEDIATE));
+
+ vtp->par = par;
+ vtp->func = vtfunc;
+
+#if CH_CFG_ST_TIMEDELTA > 0
+ {
+ systime_t now = chVTGetSystemTimeX();
+
+ /* If the requested delay is lower than the minimum safe delta then it
+ is raised to the minimum safe value.*/
+ if (delay < (systime_t)CH_CFG_ST_TIMEDELTA) {
+ delay = (systime_t)CH_CFG_ST_TIMEDELTA;
+ }
+
+ /* Special case where the timers list is empty.*/
+ if (&ch.vtlist == (virtual_timers_list_t *)ch.vtlist.next) {
+
+ /* The delta list is empty, the current time becomes the new
+ delta list base time, the timer is inserted.*/
+ ch.vtlist.lasttime = now;
+ ch.vtlist.next = vtp;
+ ch.vtlist.prev = vtp;
+ vtp->next = (virtual_timer_t *)&ch.vtlist;
+ vtp->prev = (virtual_timer_t *)&ch.vtlist;
+ vtp->delta = delay;
+
+ /* Being the first element in the list the alarm timer is started.*/
+ port_timer_start_alarm(ch.vtlist.lasttime + delay);
+
+ return;
+ }
+
+ /* Pointer to the first element in the delta list, which is non-empty.*/
+ p = ch.vtlist.next;
+
+ /* Delay as delta from 'lasttime'. Note, it can overflow and the value
+ becomes lower than 'now'.*/
+ delta = now - ch.vtlist.lasttime + delay;
+
+ if (delta < now - ch.vtlist.lasttime) {
+ /* Scenario where a very large delay excedeed the numeric range, it
+ requires a special handling. We need to skip the first element and
+ adjust the delta to wrap back in the previous numeric range.*/
+ delta -= p->delta;
+ p = p->next;
+ }
+ else if (delta < p->delta) {
+ /* A small delay that will become the first element in the delta list
+ and next deadline.*/
+ port_timer_set_alarm(ch.vtlist.lasttime + delta);
+ }
+ }
+#else /* CH_CFG_ST_TIMEDELTA == 0 */
+ /* Delta is initially equal to the specified delay.*/
+ delta = delay;
+
+ /* Pointer to the first element in the delta list.*/
+ p = ch.vtlist.next;
+#endif /* CH_CFG_ST_TIMEDELTA == 0 */
+
+ /* The delta list is scanned in order to find the correct position for
+ this timer. */
+ while (p->delta < delta) {
+ /* Debug assert if the timer is already in the list.*/
+ chDbgAssert(p != vtp, "timer already armed");
+
+ delta -= p->delta;
+ p = p->next;
+ }
+
+ /* The timer is inserted in the delta list.*/
+ vtp->next = p;
+ vtp->prev = vtp->next->prev;
+ vtp->prev->next = vtp;
+ p->prev = vtp;
+ vtp->delta = delta;
+
+ /* Calculate new delta for the following entry.*/
+ p->delta -= delta;
+
+ /* Special case when the timer is in last position in the list, the
+ value in the header must be restored.*/
+ ch.vtlist.delta = (systime_t)-1;
+}
+
+/**
+ * @brief Disables a Virtual Timer.
+ * @pre The timer must be in armed state before calling this function.
+ *
+ * @param[in] vtp the @p virtual_timer_t structure pointer
+ *
+ * @iclass
+ */
+void chVTDoResetI(virtual_timer_t *vtp) {
+
+ chDbgCheckClassI();
+ chDbgCheck(vtp != NULL);
+ chDbgAssert(vtp->func != NULL, "timer not set or already triggered");
+
+#if CH_CFG_ST_TIMEDELTA == 0
+
+ /* The delta of the timer is added to the next timer.*/
+ vtp->next->delta += vtp->delta;
+
+ /* Removing the element from the delta list.*/
+ vtp->prev->next = vtp->next;
+ vtp->next->prev = vtp->prev;
+ vtp->func = NULL;
+
+ /* The above code changes the value in the header when the removed element
+ is the last of the list, restoring it.*/
+ ch.vtlist.delta = (systime_t)-1;
+#else /* CH_CFG_ST_TIMEDELTA > 0 */
+ systime_t nowdelta, delta;
+
+ /* If the timer is not the first of the list then it is simply unlinked
+ else the operation is more complex.*/
+ if (ch.vtlist.next != vtp) {
+ /* Removing the element from the delta list.*/
+ vtp->prev->next = vtp->next;
+ vtp->next->prev = vtp->prev;
+ vtp->func = NULL;
+
+ /* Adding delta to the next element, if it is not the last one.*/
+ if (&ch.vtlist != (virtual_timers_list_t *)vtp->next)
+ vtp->next->delta += vtp->delta;
+
+ return;
+ }
+
+ /* Removing the first timer from the list.*/
+ ch.vtlist.next = vtp->next;
+ ch.vtlist.next->prev = (virtual_timer_t *)&ch.vtlist;
+ vtp->func = NULL;
+
+ /* If the list become empty then the alarm timer is stopped and done.*/
+ if (&ch.vtlist == (virtual_timers_list_t *)ch.vtlist.next) {
+ port_timer_stop_alarm();
+
+ return;
+ }
+
+ /* The delta of the removed timer is added to the new first timer.*/
+ ch.vtlist.next->delta += vtp->delta;
+
+ /* If the new first timer has a delta of zero then the alarm is not
+ modified, the already programmed alarm will serve it.*/
+/* if (ch.vtlist.next->delta == 0) {
+ return;
+ }*/
+
+ /* Distance in ticks between the last alarm event and current time.*/
+ nowdelta = chVTGetSystemTimeX() - ch.vtlist.lasttime;
+
+ /* If the current time surpassed the time of the next element in list
+ then the event interrupt is already pending, just return.*/
+ if (nowdelta >= ch.vtlist.next->delta) {
+ return;
+ }
+
+ /* Distance from the next scheduled event and now.*/
+ delta = ch.vtlist.next->delta - nowdelta;
+
+ /* Making sure to not schedule an event closer than CH_CFG_ST_TIMEDELTA
+ ticks from now.*/
+ if (delta < (systime_t)CH_CFG_ST_TIMEDELTA) {
+ delta = (systime_t)CH_CFG_ST_TIMEDELTA;
+ }
+
+ port_timer_set_alarm(ch.vtlist.lasttime + nowdelta + delta);
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chconf.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/chconf.h
similarity index 54%
rename from flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chconf.h
rename to flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/chconf.h
index 2db88f229b..12ee7e1fb5 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/kernel/templates/chconf.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/chconf.h
@@ -1,28 +1,17 @@
/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
- This file is part of ChibiOS/RT.
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
@@ -36,24 +25,49 @@
* @{
*/
-#ifndef _CHCONF_H_
-#define _CHCONF_H_
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_RT_CONF_
/*===========================================================================*/
/**
- * @name Kernel parameters and options
+ * @name System timers settings
* @{
*/
/*===========================================================================*/
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
-#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
-#define CH_FREQUENCY 1000
-#endif
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
/**
* @brief Round robin interval.
@@ -62,13 +76,12 @@
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
- *
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
*/
-#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
-#define CH_TIME_QUANTUM 20
-#endif
+#define CH_CFG_TIME_QUANTUM 0
/**
* @brief Managed RAM size.
@@ -79,28 +92,18 @@
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
- * @note Requires @p CH_USE_MEMCORE.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
*/
-#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
-#define CH_MEMCORE_SIZE 0
-#endif
+#define CH_CFG_MEMCORE_SIZE 0
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
- * does not spawn the idle thread automatically. The application has
- * then the responsibility to do one of the following:
- * - Spawn a custom idle thread at priority @p IDLEPRIO.
- * - Change the main() thread priority to @p IDLEPRIO then enter
- * an endless loop. In this scenario the @p main() thread acts as
- * the idle thread.
- * .
- * @note Unless an idle thread is spawned the @p main() thread must not
- * enter a sleep state.
- */
-#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
-#define CH_NO_IDLE_THREAD FALSE
-#endif
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
/** @} */
@@ -119,9 +122,7 @@
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
-#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
-#define CH_OPTIMIZE_SPEED TRUE
-#endif
+#define CH_CFG_OPTIMIZE_SPEED TRUE
/** @} */
@@ -132,15 +133,22 @@
*/
/*===========================================================================*/
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
-#define CH_USE_REGISTRY TRUE
-#endif
+#define CH_CFG_USE_REGISTRY TRUE
/**
* @brief Threads synchronization APIs.
@@ -149,9 +157,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
-#define CH_USE_WAITEXIT TRUE
-#endif
+#define CH_CFG_USE_WAITEXIT TRUE
/**
* @brief Semaphores APIs.
@@ -159,43 +165,36 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
-#define CH_USE_SEMAPHORES TRUE
-#endif
+#define CH_CFG_USE_SEMAPHORES TRUE
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
- * @note The default is @p FALSE. Enable this if you have special requirements.
- * @note Requires @p CH_USE_SEMAPHORES.
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
-#define CH_USE_SEMAPHORES_PRIORITY FALSE
-#endif
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
/**
- * @brief Atomic semaphore API.
- * @details If enabled then the semaphores the @p chSemSignalWait() API
- * is included in the kernel.
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
-#define CH_USE_SEMSW TRUE
-#endif
+#define CH_CFG_USE_MUTEXES TRUE
/**
- * @brief Mutexes APIs.
- * @details If enabled then the mutexes APIs are included in the kernel.
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
*
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
*/
-#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
-#define CH_USE_MUTEXES TRUE
-#endif
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
/**
* @brief Conditional Variables APIs.
@@ -203,11 +202,9 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_MUTEXES.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
*/
-#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
-#define CH_USE_CONDVARS TRUE
-#endif
+#define CH_CFG_USE_CONDVARS TRUE
/**
* @brief Conditional Variables APIs with timeout.
@@ -215,11 +212,9 @@
* specification are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_CONDVARS.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
*/
-#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
-#define CH_USE_CONDVARS_TIMEOUT TRUE
-#endif
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
/**
* @brief Events Flags APIs.
@@ -227,9 +222,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
-#define CH_USE_EVENTS TRUE
-#endif
+#define CH_CFG_USE_EVENTS TRUE
/**
* @brief Events Flags APIs with timeout.
@@ -237,11 +230,9 @@
* are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_EVENTS.
+ * @note Requires @p CH_CFG_USE_EVENTS.
*/
-#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
-#define CH_USE_EVENTS_TIMEOUT TRUE
-#endif
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
/**
* @brief Synchronous Messages APIs.
@@ -250,21 +241,18 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
-#define CH_USE_MESSAGES TRUE
-#endif
+#define CH_CFG_USE_MESSAGES TRUE
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
- * @note The default is @p FALSE. Enable this if you have special requirements.
- * @note Requires @p CH_USE_MESSAGES.
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
*/
-#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
-#define CH_USE_MESSAGES_PRIORITY FALSE
-#endif
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
/**
* @brief Mailboxes APIs.
@@ -272,21 +260,9 @@
* included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_SEMAPHORES.
- */
-#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
-#define CH_USE_MAILBOXES TRUE
-#endif
-
-/**
- * @brief I/O Queues APIs.
- * @details If enabled then the I/O queues APIs are included in the kernel.
- *
- * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
-#define CH_USE_QUEUES TRUE
-#endif
+#define CH_CFG_USE_MAILBOXES TRUE
/**
* @brief Core Memory Manager APIs.
@@ -295,9 +271,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
-#define CH_USE_MEMCORE TRUE
-#endif
+#define CH_CFG_USE_MEMCORE TRUE
/**
* @brief Heap Allocator APIs.
@@ -305,27 +279,11 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
- * @p CH_USE_SEMAPHORES.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
-#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
-#define CH_USE_HEAP TRUE
-#endif
-
-/**
- * @brief C-runtime allocator.
- * @details If enabled the the heap allocator APIs just wrap the C-runtime
- * @p malloc() and @p free() functions.
- *
- * @note The default is @p FALSE.
- * @note Requires @p CH_USE_HEAP.
- * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
- * appropriate documentation.
- */
-#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
-#define CH_USE_MALLOC_HEAP FALSE
-#endif
+#define CH_CFG_USE_HEAP TRUE
/**
* @brief Memory Pools Allocator APIs.
@@ -334,9 +292,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
-#define CH_USE_MEMPOOLS TRUE
-#endif
+#define CH_CFG_USE_MEMPOOLS TRUE
/**
* @brief Dynamic Threads APIs.
@@ -344,12 +300,10 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_WAITEXIT.
- * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
-#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
-#define CH_USE_DYNAMIC TRUE
-#endif
+#define CH_CFG_USE_DYNAMIC TRUE
/** @} */
@@ -360,6 +314,13 @@
*/
/*===========================================================================*/
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
@@ -367,9 +328,7 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
-#endif
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
/**
* @brief Debug option, parameters checks.
@@ -378,9 +337,7 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS FALSE
-#endif
+#define CH_DBG_ENABLE_CHECKS TRUE
/**
* @brief Debug option, consistency checks.
@@ -390,20 +347,22 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS FALSE
-#endif
+#define CH_DBG_ENABLE_ASSERTS TRUE
/**
* @brief Debug option, trace buffer.
- * @details If enabled then the context switch circular trace buffer is
- * activated.
+ * @details If enabled then the trace buffer is activated.
*
- * @note The default is @p FALSE.
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
-#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE FALSE
-#endif
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL
+
+/**
+ * @brief Trace buffer entries.
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#define CH_DBG_TRACE_BUFFER_SIZE 128
/**
* @brief Debug option, stack checks.
@@ -415,9 +374,7 @@
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
-#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
-#endif
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
/**
* @brief Debug option, stacks initialization.
@@ -427,22 +384,18 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS FALSE
-#endif
+#define CH_DBG_FILL_THREADS TRUE
/**
* @brief Debug option, threads profiling.
- * @details If enabled then a field is added to the @p Thread structure that
+ * @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
- * @note The default is @p TRUE.
- * @note This debug option is defaulted to TRUE because it is required by
- * some test cases into the test suite.
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
*/
-#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
-#define CH_DBG_THREADS_PROFILING TRUE
-#endif
+#define CH_DBG_THREADS_PROFILING FALSE
/** @} */
@@ -455,12 +408,10 @@
/**
* @brief Threads descriptor structure extension.
- * @details User fields added to the end of the @p Thread structure.
+ * @details User fields added to the end of the @p thread_t structure.
*/
-#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
-#define THREAD_EXT_FIELDS \
+#define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/
-#endif
/**
* @brief Threads initialization hook.
@@ -469,67 +420,94 @@
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
-#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
-#define THREAD_EXT_INIT_HOOK(tp) { \
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
-#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
- *
- * @note It is inserted into lock zone.
- * @note It is also invoked when the threads simply return in order to
- * terminate.
*/
-#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
-#define THREAD_EXT_EXIT_HOOK(tp) { \
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
-#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
-#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
-#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
- /* System halt code here.*/ \
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+ /* Idle-enter code here.*/ \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+ /* Idle-leave code here.*/ \
}
-#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
-#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
-#define IDLE_LOOP_HOOK() { \
+#define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
-#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
-#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
-#define SYSTEM_TICK_EVENT_HOOK() { \
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
-#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
-#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
-#define SYSTEM_HALT_HOOK() { \
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
-#endif
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
/** @} */
@@ -537,6 +515,6 @@
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
-#endif /* _CHCONF_H_ */
+#endif /* CHCONF_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/meta/module.c b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/meta/module.c
new file mode 100644
index 0000000000..c07ea1c073
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/meta/module.c
@@ -0,0 +1,80 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chXxx.c
+ * @brief XXX module code.
+ *
+ * @addtogroup XXX
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_XXX || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief XXX Module initialization.
+ * @note This function is implicitly invoked on system initialization,
+ * there is no need to explicitly initialize the module.
+ *
+ * @notapi
+ */
+void _xxx_init(void) {
+
+}
+
+/**
+ * @brief Initializes a @p xxx_t object.
+ *
+ * @param[out] xxxp pointer to the @p xxx_t object
+ *
+ * @init
+ */
+void chXxxObjectInit(xxx_t *xxxp) {
+
+}
+
+#endif /* CH_CFG_USE_XXX */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/meta/module.h b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/meta/module.h
new file mode 100644
index 0000000000..eee1bd1714
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/rt/templates/meta/module.h
@@ -0,0 +1,76 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file chXxx.h
+ * @brief XXX Module macros and structures.
+ *
+ * @addtogroup XXX
+ * @{
+ */
+
+#ifndef CHXXX_H
+#define CHXXX_H
+
+#include "ch.h"
+
+#if CH_CFG_USE_XXX || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chXxxInit(void);
+ void chXxxObjectInit(xxx_t *xxxp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_XXX */
+
+#endif /* CHXXX_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/chprintf.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/chprintf.h
deleted file mode 100644
index 44c48b929a..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/chprintf.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file chprintf.h
- * @brief Mini printf-like functionality.
- *
- * @addtogroup chprintf
- * @{
- */
-
-#ifndef _CHPRINTF_H_
-#define _CHPRINTF_H_
-
-#include
-
-/**
- * @brief Float type support.
- */
-#if !defined(CHPRINTF_USE_FLOAT) || defined(__DOXYGEN__)
-#define CHPRINTF_USE_FLOAT FALSE
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap);
- int chsnprintf(char *str, size_t size, const char *fmt, ...);
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @brief System formatted output function.
- * @details This function implements a minimal @p printf() like functionality
- * with output on a @p BaseSequentialStream.
- * The general parameters format is: %[-][width|*][.precision|*][l|L]p.
- * The following parameter types (p) are supported:
- * - x hexadecimal integer.
- * - X hexadecimal long.
- * - o octal integer.
- * - O octal long.
- * - d decimal signed integer.
- * - D decimal signed long.
- * - u decimal unsigned integer.
- * - U decimal unsigned long.
- * - c character.
- * - s string.
- * .
- *
- * @param[in] chp pointer to a @p BaseSequentialStream implementing object
- * @param[in] fmt formatting string
- *
- * @api
- */
-static INLINE void chprintf(BaseSequentialStream *chp, const char *fmt, ...) {
- va_list ap;
-
- va_start(ap, fmt);
- chvprintf(chp, fmt, ap);
- va_end(ap);
-}
-
-#endif /* _CHPRINTF_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/chrtclib.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/chrtclib.c
deleted file mode 100644
index 509ddde6e1..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/chrtclib.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file chrtclib.c
- * @brief RTC time conversion utilities code.
- *
- * @addtogroup chrtclib
- * @{
- */
-
-#include
-
-#include "ch.h"
-#include "hal.h"
-
-#include "chrtclib.h"
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-#if (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) || \
- defined(STM32F30X) || defined(STM32F37X) || \
- defined(STM32F1XX) || defined(STM32F10X_MD) || defined(STM32F10X_LD) || \
- defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(STM32F0XX) || \
- defined(LPC122X) || defined(__DOXYGEN__))
-#if STM32_RTC_IS_CALENDAR
-/**
- * @brief Converts from STM32 BCD to canonicalized time format.
- *
- * @param[out] timp pointer to a @p tm structure as defined in time.h
- * @param[in] timespec pointer to a @p RTCTime structure
- *
- * @notapi
- */
-static void stm32_rtc_bcd2tm(struct tm *timp, RTCTime *timespec) {
- uint32_t tv_time = timespec->tv_time;
- uint32_t tv_date = timespec->tv_date;
-
-#if CH_DBG_ENABLE_CHECKS
- timp->tm_isdst = 0;
- timp->tm_wday = 0;
- timp->tm_mday = 0;
- timp->tm_yday = 0;
- timp->tm_mon = 0;
- timp->tm_year = 0;
- timp->tm_sec = 0;
- timp->tm_min = 0;
- timp->tm_hour = 0;
-#endif
-
- timp->tm_isdst = -1;
-
- timp->tm_wday = (tv_date & RTC_DR_WDU) >> RTC_DR_WDU_OFFSET;
- if (timp->tm_wday == 7)
- timp->tm_wday = 0;
-
- timp->tm_mday = (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET;
- timp->tm_mday += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10;
-
- timp->tm_mon = (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET;
- timp->tm_mon += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10;
- timp->tm_mon -= 1;
-
- timp->tm_year = (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET;
- timp->tm_year += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10;
- timp->tm_year += 2000 - 1900;
-
- timp->tm_sec = (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET;
- timp->tm_sec += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10;
-
- timp->tm_min = (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET;
- timp->tm_min += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10;
-
- timp->tm_hour = (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET;
- timp->tm_hour += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10;
- timp->tm_hour += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET);
-}
-
-/**
- * @brief Converts from canonicalized to STM32 BCD time format.
- *
- * @param[in] timp pointer to a @p tm structure as defined in time.h
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @notapi
- */
-static void stm32_rtc_tm2bcd(struct tm *timp, RTCTime *timespec) {
- uint32_t v = 0;
-
- timespec->tv_date = 0;
- timespec->tv_time = 0;
-
- v = timp->tm_year - 100;
- timespec->tv_date |= ((v / 10) << RTC_DR_YT_OFFSET) & RTC_DR_YT;
- timespec->tv_date |= (v % 10) << RTC_DR_YU_OFFSET;
-
- if (timp->tm_wday == 0)
- v = 7;
- else
- v = timp->tm_wday;
- timespec->tv_date |= (v << RTC_DR_WDU_OFFSET) & RTC_DR_WDU;
-
- v = timp->tm_mon + 1;
- timespec->tv_date |= ((v / 10) << RTC_DR_MT_OFFSET) & RTC_DR_MT;
- timespec->tv_date |= (v % 10) << RTC_DR_MU_OFFSET;
-
- v = timp->tm_mday;
- timespec->tv_date |= ((v / 10) << RTC_DR_DT_OFFSET) & RTC_DR_DT;
- timespec->tv_date |= (v % 10) << RTC_DR_DU_OFFSET;
-
- v = timp->tm_hour;
- timespec->tv_time |= ((v / 10) << RTC_TR_HT_OFFSET) & RTC_TR_HT;
- timespec->tv_time |= (v % 10) << RTC_TR_HU_OFFSET;
-
- v = timp->tm_min;
- timespec->tv_time |= ((v / 10) << RTC_TR_MNT_OFFSET) & RTC_TR_MNT;
- timespec->tv_time |= (v % 10) << RTC_TR_MNU_OFFSET;
-
- v = timp->tm_sec;
- timespec->tv_time |= ((v / 10) << RTC_TR_ST_OFFSET) & RTC_TR_ST;
- timespec->tv_time |= (v % 10) << RTC_TR_SU_OFFSET;
-}
-
-/**
- * @brief Gets raw time from RTC and converts it to canonicalized format.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[out] timp pointer to a @p tm structure as defined in time.h
- *
- * @api
- */
-void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) {
-#if STM32_RTC_HAS_SUBSECONDS
- RTCTime timespec = {0,0,FALSE,0};
-#else
- RTCTime timespec = {0,0,FALSE};
-#endif
-
- rtcGetTime(rtcp, ×pec);
- stm32_rtc_bcd2tm(timp, ×pec);
-}
-
-/**
- * @brief Sets RTC time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[out] timp pointer to a @p tm structure as defined in time.h
- *
- * @api
- */
-void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) {
-#if STM32_RTC_HAS_SUBSECONDS
- RTCTime timespec = {0,0,FALSE,0};
-#else
- RTCTime timespec = {0,0,FALSE};
-#endif
-
- stm32_rtc_tm2bcd(timp, ×pec);
- rtcSetTime(rtcp, ×pec);
-}
-
-/**
- * @brief Gets raw time from RTC and converts it to unix format.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @return Unix time value in seconds.
- *
- * @api
- */
-time_t rtcGetTimeUnixSec(RTCDriver *rtcp) {
-#if STM32_RTC_HAS_SUBSECONDS
- RTCTime timespec = {0,0,FALSE,0};
-#else
- RTCTime timespec = {0,0,FALSE};
-#endif
- struct tm timp;
-
- rtcGetTime(rtcp, ×pec);
- stm32_rtc_bcd2tm(&timp, ×pec);
-
- return mktime(&timp);
-}
-
-/**
- * @brief Sets RTC time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] tv_sec time specification
- * @return Unix time value in seconds.
- *
- * @api
- */
-void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec) {
-#if STM32_RTC_HAS_SUBSECONDS
- RTCTime timespec = {0,0,FALSE,0};
-#else
- RTCTime timespec = {0,0,FALSE};
-#endif
- struct tm timp;
-
- localtime_r(&tv_sec, &timp);
- stm32_rtc_tm2bcd(&timp, ×pec);
- rtcSetTime(rtcp, ×pec);
-}
-
-/**
- * @brief Gets raw time from RTC and converts it to unix format.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @return Unix time value in microseconds.
- *
- * @api
- */
-uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp) {
-#if STM32_RTC_HAS_SUBSECONDS
- uint64_t result = 0;
- RTCTime timespec = {0,0,FALSE,0};
- struct tm timp;
-
- rtcGetTime(rtcp, ×pec);
- stm32_rtc_bcd2tm(&timp, ×pec);
-
- result = (uint64_t)mktime(&timp) * 1000000;
- return result + timespec.tv_msec * 1000;
-#else
- return (uint64_t)rtcGetTimeUnixSec(rtcp) * 1000000;
-#endif
-}
-
-#else /* STM32_RTC_IS_CALENDAR */
-/**
- * @brief Gets raw time from RTC and converts it to canonicalized format.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[out] timp pointer to a @p tm structure as defined in time.h
- *
- * @api
- */
-void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) {
- RTCTime timespec = {0};
-
- rtcGetTime(rtcp, ×pec);
- localtime_r((time_t *)&(timespec.tv_sec), timp);
-}
-
-/**
- * @brief Sets RTC time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[out] timp pointer to a @p tm structure as defined in time.h
- *
- * @api
- */
-void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) {
- RTCTime timespec = {0};
-
- timespec.tv_sec = mktime(timp);
-#if !defined(LPC122X)
- timespec.tv_msec = 0;
-#endif
- rtcSetTime(rtcp, ×pec);
-}
-
-/**
- * @brief Gets raw time from RTC and converts it to unix format.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @return Unix time value in seconds.
- *
- * @api
- */
-time_t rtcGetTimeUnixSec(RTCDriver *rtcp) {
- RTCTime timespec = {0};
-
- rtcGetTime(rtcp, ×pec);
- return timespec.tv_sec;
-}
-
-/**
- * @brief Sets RTC time.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] tv_sec time specification
- * @return Unix time value in seconds.
- *
- * @api
- */
-void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec) {
- RTCTime timespec = {0};
-
- timespec.tv_sec = tv_sec;
-#if !defined(LPC122X)
- timespec.tv_msec = 0;
-#endif
- rtcSetTime(rtcp, ×pec);
-}
-
-/**
- * @brief Gets raw time from RTC and converts it to unix format.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @return Unix time value in microseconds.
- *
- * @api
- */
-uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp) {
-#if STM32_RTC_HAS_SUBSECONDS
- uint64_t result = 0;
- RTCTime timespec = {0,0};
-
- rtcGetTime(rtcp, ×pec);
- result = (uint64_t)timespec.tv_sec * 1000000;
- return result + timespec.tv_msec * 1000;
-#else
- return (uint64_t)rtcGetTimeUnixSec(rtcp) * 1000000;
-#endif
-}
-
-/**
- * @brief Get current time in format suitable for usage in FatFS.
- *
- * @param[in] rtcp pointer to RTC driver structure
- * @return FAT time value.
- *
- * @api
- */
-uint32_t rtcGetTimeFatFromCounter(RTCDriver *rtcp) {
- uint32_t fattime;
- struct tm timp;
-
- rtcGetTimeTm(rtcp, &timp);
-
- fattime = (timp.tm_sec) >> 1;
- fattime |= (timp.tm_min) << 5;
- fattime |= (timp.tm_hour) << 11;
- fattime |= (timp.tm_mday) << 16;
- fattime |= (timp.tm_mon + 1) << 21;
- fattime |= (timp.tm_year - 80) << 25;
-
- return fattime;
-}
-#endif /* STM32_RTC_IS_CALENDAR */
-#endif /* (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) || defined(STM32F1XX)) */
-
-#endif /* HAL_USE_RTC */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/chrtclib.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/chrtclib.h
deleted file mode 100644
index 7761110416..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/chrtclib.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file chrtclib.h
- * @brief RTC time conversion utilities header.
- *
- * @addtogroup chrtclib
- * @{
- */
-
-#ifndef CHRTCLIB_H_
-#define CHRTCLIB_H_
-
-#include
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#if !STM32_RTC_IS_CALENDAR
- uint32_t rtcGetTimeFat(RTCDriver *rtcp);
-#endif
- void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp);
- void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp);
- time_t rtcGetTimeUnixSec(RTCDriver *rtcp);
- uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp);
- void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_RTC */
-
-#endif /* CHRTCLIB_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/ch.cpp b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/ch.cpp
index 56e1b49d1d..7a33bdd2f6 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/ch.cpp
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/ch.cpp
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,65 +25,10 @@
namespace chibios_rt {
- /*------------------------------------------------------------------------*
- * chibios_rt::System *
- *------------------------------------------------------------------------*/
- void System::init(void) {
-
- chSysInit();
- }
-
- void System::lock(void) {
-
- chSysLock();
- }
-
- void System::unlock(void) {
-
- chSysUnlock();
- }
-
- void System::lockFromIsr(void) {
-
- chSysLockFromIsr();
- }
-
- void System::unlockFromIsr(void) {
-
- chSysUnlockFromIsr();
- }
-
- systime_t System::getTime(void) {
-
- return chTimeNow();
- }
-
- bool System::isTimeWithin(systime_t start, systime_t end) {
-
- return (bool)chTimeIsWithin(start, end);
- }
-
- /*------------------------------------------------------------------------*
- * chibios_rt::Core *
- *------------------------------------------------------------------------*/
- void *Core::alloc(size_t size) {
-
- return chCoreAlloc(size);
- }
-
- void *Core::allocI(size_t size) {
-
- return chCoreAllocI(size);
- }
-
- size_t Core::getStatus(void) {
-
- return chCoreStatus();
- }
-
/*------------------------------------------------------------------------*
* chibios_rt::Timer *
*------------------------------------------------------------------------*/
+
void Timer::setI(systime_t time, vtfunc_t vtfunc, void *par) {
chVTSetI(&timer_ref, time, vtfunc, par);
@@ -92,109 +37,71 @@ namespace chibios_rt {
void Timer::resetI() {
if (chVTIsArmedI(&timer_ref))
- chVTResetI(&timer_ref);
+ chVTDoResetI(&timer_ref);
}
bool Timer::isArmedI(void) {
- return (bool)chVTIsArmedI(&timer_ref);
+ return chVTIsArmedI(&timer_ref);
}
/*------------------------------------------------------------------------*
- * chibios_rt::ThreadReference *
+ * chibios_rt::ThreadStayPoint *
*------------------------------------------------------------------------*/
- void ThreadReference::stop(void) {
+ msg_t ThreadStayPoint::suspendS(void) {
- chDbgPanic("invoked unimplemented method stop()");
+ return chThdSuspendS(&thread_ref);
}
- msg_t ThreadReference::suspend(void) {
- msg_t msg;
-
- chSysLock();
+ msg_t ThreadStayPoint::suspendS(systime_t timeout) {
- chDbgAssert(thread_ref != NULL,
- "ThreadReference, #1",
- "already referenced");
-
- thread_ref = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- msg = thread_ref->p_u.rdymsg;
-
- chSysUnlock();
- return msg;
+ return chThdSuspendTimeoutS(&thread_ref, timeout);
}
- msg_t ThreadReference::suspendS(void) {
+ void ThreadStayPoint::resumeI(msg_t msg) {
- chDbgAssert(thread_ref == NULL,
- "ThreadReference, #2",
- "already referenced");
-
- thread_ref = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- return thread_ref->p_u.rdymsg;
+ chThdResumeI(&thread_ref, msg);
}
- void ThreadReference::resume(msg_t msg) {
-
- chSysLock()
+ void ThreadStayPoint::resumeS(msg_t msg) {
- chDbgAssert(thread_ref != NULL,
- "ThreadReference, #3",
- "not referenced");
-
- if (thread_ref) {
- Thread *tp = thread_ref;
- thread_ref = NULL;
- chSchWakeupS(tp, msg);
- }
-
- chSysUnlock();
+ chThdResumeS(&thread_ref, msg);
}
- void ThreadReference::resumeI(msg_t msg) {
+ /*------------------------------------------------------------------------*
+ * chibios_rt::ThreadReference *
+ *------------------------------------------------------------------------*/
- chDbgAssert(thread_ref != NULL,
- "ThreadReference, #4",
- "not referenced");
+ void ThreadReference::stop(void) {
- if (thread_ref) {
- Thread *tp = thread_ref;
- thread_ref = NULL;
- tp->p_msg = msg;
- chSchReadyI(tp);
- }
+ chSysHalt("invoked unimplemented method stop()");
}
void ThreadReference::requestTerminate(void) {
chDbgAssert(thread_ref != NULL,
- "ThreadReference, #5",
"not referenced");
chThdTerminate(thread_ref);
}
-#if CH_USE_WAITEXIT
+#if CH_CFG_USE_WAITEXIT
msg_t ThreadReference::wait(void) {
chDbgAssert(thread_ref != NULL,
- "ThreadReference, #6",
"not referenced");
msg_t msg = chThdWait(thread_ref);
thread_ref = NULL;
return msg;
}
-#endif /* CH_USE_WAITEXIT */
+#endif /* CH_CFG_USE_WAITEXIT */
-#if CH_USE_MESSAGES
+#if CH_CFG_USE_MESSAGES
msg_t ThreadReference::sendMessage(msg_t msg) {
chDbgAssert(thread_ref != NULL,
- "ThreadReference, #7",
"not referenced");
return chMsgSend(thread_ref, msg);
@@ -203,16 +110,14 @@ namespace chibios_rt {
bool ThreadReference::isPendingMessage(void) {
chDbgAssert(thread_ref != NULL,
- "ThreadReference, #7",
"not referenced");
- return (bool)chMsgIsPendingI(thread_ref);
+ return chMsgIsPendingI(thread_ref);
}
msg_t ThreadReference::getMessage(void) {
chDbgAssert(thread_ref != NULL,
- "ThreadReference, #8",
"not referenced");
return chMsgGet(thread_ref);
@@ -221,18 +126,16 @@ namespace chibios_rt {
void ThreadReference::releaseMessage(msg_t msg) {
chDbgAssert(thread_ref != NULL,
- "ThreadReference, #9",
"not referenced");
chMsgRelease(thread_ref, msg);
}
-#endif /* CH_USE_MESSAGES */
+#endif /* CH_CFG_USE_MESSAGES */
-#if CH_USE_EVENTS
+#if CH_CFG_USE_EVENTS
void ThreadReference::signalEvents(eventmask_t mask) {
chDbgAssert(thread_ref != NULL,
- "ThreadReference, #10",
"not referenced");
chEvtSignal(thread_ref, mask);
@@ -241,15 +144,14 @@ namespace chibios_rt {
void ThreadReference::signalEventsI(eventmask_t mask) {
chDbgAssert(thread_ref != NULL,
- "ThreadReference, #11",
"not referenced");
chEvtSignalI(thread_ref, mask);
}
-#endif /* CH_USE_EVENTS */
+#endif /* CH_CFG_USE_EVENTS */
-#if CH_USE_DYNAMIC
-#endif /* CH_USE_DYNAMIC */
+#if CH_CFG_USE_DYNAMIC
+#endif /* CH_CFG_USE_DYNAMIC */
/*------------------------------------------------------------------------*
* chibios_rt::BaseThread *
@@ -258,9 +160,8 @@ namespace chibios_rt {
}
- msg_t BaseThread::main(void) {
+ void BaseThread::main(void) {
- return 0;
}
ThreadReference BaseThread::start(tprio_t prio) {
@@ -268,11 +169,11 @@ namespace chibios_rt {
(void)prio;
return *this;
- };
+ }
- msg_t _thd_start(void *arg) {
+ void _thd_start(void *arg) {
- return ((BaseThread *)arg)->main();
+ ((BaseThread *)arg)->main();
}
void BaseThread::setName(const char *tname) {
@@ -297,7 +198,7 @@ namespace chibios_rt {
bool BaseThread::shouldTerminate(void) {
- return (bool)chThdShouldTerminate();
+ return chThdShouldTerminateX();
}
void BaseThread::sleep(systime_t interval){
@@ -315,15 +216,15 @@ namespace chibios_rt {
chThdYield();
}
-#if CH_USE_MESSAGES
+#if CH_CFG_USE_MESSAGES
ThreadReference BaseThread::waitMessage(void) {
ThreadReference tr(chMsgWait());
return tr;
}
-#endif /* CH_USE_MESSAGES */
+#endif /* CH_CFG_USE_MESSAGES */
-#if CH_USE_EVENTS
+#if CH_CFG_USE_EVENTS
eventmask_t BaseThread::getAndClearEvents(eventmask_t mask) {
return chEvtGetAndClearEvents(mask);
@@ -349,7 +250,7 @@ namespace chibios_rt {
return chEvtWaitAll(ewmask);
}
-#if CH_USE_EVENTS_TIMEOUT
+#if CH_CFG_USE_EVENTS_TIMEOUT
eventmask_t BaseThread::waitOneEventTimeout(eventmask_t ewmask,
systime_t time) {
@@ -367,39 +268,39 @@ namespace chibios_rt {
return chEvtWaitAllTimeout(ewmask, time);
}
-#endif /* CH_USE_EVENTS_TIMEOUT */
+#endif /* CH_CFG_USE_EVENTS_TIMEOUT */
void BaseThread::dispatchEvents(const evhandler_t handlers[],
eventmask_t mask) {
chEvtDispatch(handlers, mask);
}
-#endif /* CH_USE_EVENTS */
+#endif /* CH_CFG_USE_EVENTS */
-#if CH_USE_MUTEXES
- void BaseThread::unlockMutex(void) {
+#if CH_CFG_USE_MUTEXES
+ void BaseThread::unlockMutex(Mutex *mp) {
- chMtxUnlock();
+ chMtxUnlock(&mp->mutex);
}
- void BaseThread::unlockMutexS(void) {
+ void BaseThread::unlockMutexS(Mutex *mp) {
- chMtxUnlockS();
+ chMtxUnlockS(&mp->mutex);
}
void BaseThread::unlockAllMutexes(void) {
chMtxUnlockAll();
}
-#endif /* CH_USE_MUTEXES */
+#endif /* CH_CFG_USE_MUTEXES */
-#if CH_USE_SEMAPHORES
+#if CH_CFG_USE_SEMAPHORES
/*------------------------------------------------------------------------*
* chibios_rt::CounterSemaphore *
*------------------------------------------------------------------------*/
CounterSemaphore::CounterSemaphore(cnt_t n) {
- chSemInit(&sem, n);
+ chSemObjectInit(&sem, n);
}
void CounterSemaphore::reset(cnt_t n) {
@@ -422,12 +323,12 @@ namespace chibios_rt {
return chSemWaitS(&sem);
}
- msg_t CounterSemaphore::waitTimeout(systime_t time) {
+ msg_t CounterSemaphore::wait(systime_t time) {
return chSemWaitTimeout(&sem, time);
}
- msg_t CounterSemaphore::waitTimeoutS(systime_t time) {
+ msg_t CounterSemaphore::waitS(systime_t time) {
return chSemWaitTimeoutS(&sem, time);
}
@@ -452,20 +353,18 @@ namespace chibios_rt {
return chSemGetCounterI(&sem);
}
-#if CH_USE_SEMSW
msg_t CounterSemaphore::signalWait(CounterSemaphore *ssem,
CounterSemaphore *wsem) {
return chSemSignalWait(&ssem->sem, &wsem->sem);
}
-#endif /* CH_USE_SEMSW */
/*------------------------------------------------------------------------*
* chibios_rt::BinarySemaphore *
*------------------------------------------------------------------------*/
BinarySemaphore::BinarySemaphore(bool taken) {
- chBSemInit(&bsem, (bool_t)taken);
+ chBSemObjectInit(&bsem, taken);
}
msg_t BinarySemaphore::wait(void) {
@@ -478,24 +377,24 @@ namespace chibios_rt {
return chBSemWaitS(&bsem);
}
- msg_t BinarySemaphore::waitTimeout(systime_t time) {
+ msg_t BinarySemaphore::wait(systime_t time) {
return chBSemWaitTimeout(&bsem, time);
}
- msg_t BinarySemaphore::waitTimeoutS(systime_t time) {
+ msg_t BinarySemaphore::waitS(systime_t time) {
return chBSemWaitTimeoutS(&bsem, time);
}
void BinarySemaphore::reset(bool taken) {
- chBSemReset(&bsem, (bool_t)taken);
+ chBSemReset(&bsem, taken);
}
void BinarySemaphore::resetI(bool taken) {
- chBSemResetI(&bsem, (bool_t)taken);
+ chBSemResetI(&bsem, taken);
}
void BinarySemaphore::signal(void) {
@@ -512,15 +411,15 @@ namespace chibios_rt {
return (bool)chBSemGetStateI(&bsem);
}
-#endif /* CH_USE_SEMAPHORES */
+#endif /* CH_CFG_USE_SEMAPHORES */
-#if CH_USE_MUTEXES
+#if CH_CFG_USE_MUTEXES
/*------------------------------------------------------------------------*
* chibios_rt::Mutex *
*------------------------------------------------------------------------*/
Mutex::Mutex(void) {
- chMtxInit(&mutex);
+ chMtxObjectInit(&mutex);
}
bool Mutex::tryLock(void) {
@@ -543,13 +442,23 @@ namespace chibios_rt {
chMtxLockS(&mutex);
}
-#if CH_USE_CONDVARS
+ void Mutex::unlock(void) {
+
+ chMtxUnlock(&mutex);
+ }
+
+ void Mutex::unlockS(void) {
+
+ chMtxUnlockS(&mutex);
+ }
+
+#if CH_CFG_USE_CONDVARS
/*------------------------------------------------------------------------*
* chibios_rt::CondVar *
*------------------------------------------------------------------------*/
CondVar::CondVar(void) {
- chCondInit(&condvar);
+ chCondObjectInit(&condvar);
}
void CondVar::signal(void) {
@@ -582,25 +491,25 @@ namespace chibios_rt {
return chCondWaitS(&condvar);
}
-#if CH_USE_CONDVARS_TIMEOUT
- msg_t CondVar::waitTimeout(systime_t time) {
+#if CH_CFG_USE_CONDVARS_TIMEOUT
+ msg_t CondVar::wait(systime_t time) {
return chCondWaitTimeout(&condvar, time);
}
-#endif /* CH_USE_CONDVARS_TIMEOUT */
-#endif /* CH_USE_CONDVARS */
-#endif /* CH_USE_MUTEXES */
+#endif /* CH_CFG_USE_CONDVARS_TIMEOUT */
+#endif /* CH_CFG_USE_CONDVARS */
+#endif /* CH_CFG_USE_MUTEXES */
-#if CH_USE_EVENTS
+#if CH_CFG_USE_EVENTS
/*------------------------------------------------------------------------*
* chibios_rt::EvtListener *
*------------------------------------------------------------------------*/
- flagsmask_t EvtListener::getAndClearFlags(void) {
+ eventflags_t EvtListener::getAndClearFlags(void) {
return chEvtGetAndClearFlags(&ev_listener);
}
- flagsmask_t EvtListener::getAndClearFlagsI(void) {
+ eventflags_t EvtListener::getAndClearFlagsI(void) {
return chEvtGetAndClearFlagsI(&ev_listener);
}
@@ -610,7 +519,7 @@ namespace chibios_rt {
*------------------------------------------------------------------------*/
EvtSource::EvtSource(void) {
- chEvtInit(&ev_source);
+ chEvtObjectInit(&ev_source);
}
void EvtSource::registerOne(chibios_rt::EvtListener *elp,
@@ -630,208 +539,29 @@ namespace chibios_rt {
chEvtUnregister(&ev_source, &elp->ev_listener);
}
- void EvtSource::broadcastFlags(flagsmask_t flags) {
+ void EvtSource::broadcastFlags(eventflags_t flags) {
chEvtBroadcastFlags(&ev_source, flags);
}
- void EvtSource::broadcastFlagsI(flagsmask_t flags) {
+ void EvtSource::broadcastFlagsI(eventflags_t flags) {
chEvtBroadcastFlagsI(&ev_source, flags);
}
-#endif /* CH_USE_EVENTS */
-
-#if CH_USE_QUEUES
- /*------------------------------------------------------------------------*
- * chibios_rt::InQueue *
- *------------------------------------------------------------------------*/
- InQueue::InQueue(uint8_t *bp, size_t size, qnotify_t infy, void *link) {
-
- chIQInit(&iq, bp, size, infy, link);
- }
-
- size_t InQueue::getFullI(void) {
-
- return chIQGetFullI(&iq);
- }
-
- size_t InQueue::getEmptyI(void) {
-
- return chIQGetEmptyI(&iq);
- }
-
- bool InQueue::isEmptyI(void) {
-
- return (bool)chIQIsEmptyI(&iq);
- }
-
- bool InQueue::isFullI(void) {
-
- return (bool)chIQIsFullI(&iq);
- }
-
- void InQueue::resetI(void) {
-
- chIQResetI(&iq);
- }
-
- msg_t InQueue::putI(uint8_t b) {
-
- return chIQPutI(&iq, b);
- }
-
- msg_t InQueue::get() {
-
- return chIQGet(&iq);
- }
-
- msg_t InQueue::getTimeout(systime_t time) {
-
- return chIQGetTimeout(&iq, time);
- }
-
- size_t InQueue::readTimeout(uint8_t *bp, size_t n, systime_t time) {
-
- return chIQReadTimeout(&iq, bp, n, time);
- }
-
- /*------------------------------------------------------------------------*
- * chibios_rt::OutQueue *
- *------------------------------------------------------------------------*/
- OutQueue::OutQueue(uint8_t *bp, size_t size, qnotify_t onfy, void *link) {
-
- chOQInit(&oq, bp, size, onfy, link);
- }
-
- size_t OutQueue::getFullI(void) {
-
- return chOQGetFullI(&oq);
- }
-
- size_t OutQueue::getEmptyI(void) {
-
- return chOQGetEmptyI(&oq);
- }
-
- bool OutQueue::isEmptyI(void) {
-
- return (bool)chOQIsEmptyI(&oq);
- }
-
- bool OutQueue::isFullI(void) {
-
- return (bool)chOQIsFullI(&oq);
- }
-
- void OutQueue::resetI(void) {
-
- chOQResetI(&oq);
- }
-
- msg_t OutQueue::put(uint8_t b) {
-
- return chOQPut(&oq, b);
- }
-
- msg_t OutQueue::putTimeout(uint8_t b, systime_t time) {
-
- return chOQPutTimeout(&oq, b, time);
- }
-
- msg_t OutQueue::getI(void) {
-
- return chOQGetI(&oq);
- }
-
- size_t OutQueue::writeTimeout(const uint8_t *bp, size_t n,
- systime_t time) {
-
- return chOQWriteTimeout(&oq, bp, n, time);
- }
-#endif /* CH_USE_QUEUES */
-
-#if CH_USE_MAILBOXES
- /*------------------------------------------------------------------------*
- * chibios_rt::Mailbox *
- *------------------------------------------------------------------------*/
- Mailbox::Mailbox(msg_t *buf, cnt_t n) {
-
- chMBInit(&mb, buf, n);
- }
-
- void Mailbox::reset(void) {
-
- chMBReset(&mb);
- }
-
- msg_t Mailbox::post(msg_t msg, systime_t time) {
-
- return chMBPost(&mb, msg, time);
- }
-
- msg_t Mailbox::postS(msg_t msg, systime_t time) {
-
- return chMBPostS(&mb, msg, time);
- }
-
- msg_t Mailbox::postI(msg_t msg) {
-
- return chMBPostI(&mb, msg);
- }
-
- msg_t Mailbox::postAhead(msg_t msg, systime_t time) {
-
- return chMBPostAhead(&mb, msg, time);
- }
-
- msg_t Mailbox::postAheadS(msg_t msg, systime_t time) {
-
- return chMBPostAheadS(&mb, msg, time);
- }
-
- msg_t Mailbox::postAheadI(msg_t msg) {
-
- return chMBPostAheadI(&mb, msg);
- }
-
- msg_t Mailbox::fetch(msg_t *msgp, systime_t time) {
-
- return chMBFetch(&mb, msgp, time);
- }
-
- msg_t Mailbox::fetchS(msg_t *msgp, systime_t time) {
-
- return chMBFetchS(&mb, msgp, time);
- }
-
- msg_t Mailbox::fetchI(msg_t *msgp) {
-
- return chMBFetchI(&mb, msgp);
- }
-
- cnt_t Mailbox::getFreeCountI(void) {
-
- return chMBGetFreeCountI(&mb);
- }
-
- cnt_t Mailbox::getUsedCountI(void) {
-
- return chMBGetUsedCountI(&mb);
- }
-#endif /* CH_USE_MAILBOXES */
+#endif /* CH_CFG_USE_EVENTS */
-#if CH_USE_MEMPOOLS
+#if CH_CFG_USE_MEMPOOLS
/*------------------------------------------------------------------------*
* chibios_rt::MemoryPool *
*------------------------------------------------------------------------*/
MemoryPool::MemoryPool(size_t size, memgetfunc_t provider) {
- chPoolInit(&pool, size, provider);
+ chPoolObjectInit(&pool, size, provider);
}
MemoryPool::MemoryPool(size_t size, memgetfunc_t provider, void* p, size_t n) {
- chPoolInit(&pool, size, provider);
+ chPoolObjectInit(&pool, size, provider);
chPoolLoadArray(&pool, p, n);
}
@@ -860,7 +590,7 @@ namespace chibios_rt {
chPoolFreeI(&pool, objp);
}
-#endif /* CH_USE_MEMPOOLS */
+#endif /* CH_CFG_USE_MEMPOOLS */
}
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/ch.hpp b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/ch.hpp
index df4a802e34..cb62201f4e 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/ch.hpp
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/ch.hpp
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -28,10 +28,13 @@
#define _CH_HPP_
/**
- * @brief ChibiOS kernel-related classes and interfaces.
+ * @brief ChibiOS-RT kernel-related classes and interfaces.
*/
namespace chibios_rt {
+ /* Forward declarations */
+ class Mutex;
+
/*------------------------------------------------------------------------*
* chibios_rt::System *
*------------------------------------------------------------------------*/
@@ -52,21 +55,76 @@ namespace chibios_rt {
*
* @special
*/
- static void init(void);
+ static inline void init(void) {
+
+ chSysInit();
+ }
+
+ /**
+ * @brief Halts the system.
+ * @details This function is invoked by the operating system when an
+ * unrecoverable error is detected, for example because a programming
+ * error in the application code that triggers an assertion while
+ * in debug mode.
+ * @note Can be invoked from any system state.
+ *
+ * @param[in] reason pointer to an error string
+ *
+ * @special
+ */
+ static inline void halt(const char *reason) {
+
+ chSysHalt(reason);
+ }
+
+ /**
+ * @brief System integrity check.
+ * @details Performs an integrity check of the important ChibiOS/RT data
+ * structures.
+ * @note The appropriate action in case of failure is to halt the system
+ * before releasing the critical zone.
+ * @note If the system is corrupted then one possible outcome of this
+ * function is an exception caused by @p NULL or corrupted pointers
+ * in list elements. Exception vectors must be monitored as well.
+ * @note This function is not used internally, it is up to the
+ * application to define if and where to perform system
+ * checking.
+ * @note Performing all tests at once can be a slow operation and can
+ * degrade the system response time. It is suggested to execute
+ * one test at time and release the critical zone in between tests.
+ *
+ * @param[in] testmask Each bit in this mask is associated to a test to be
+ * performed.
+ * @return The test result.
+ * @retval false The test succeeded.
+ * @retval true Test failed.
+ *
+ * @iclass
+ */
+ static inline bool integrityCheckI(unsigned int testmask) {
+
+ return chSysIntegrityCheckI(testmask);
+ }
/**
* @brief Enters the kernel lock mode.
*
* @special
*/
- static void lock(void);
+ static inline void lock(void) {
+
+ chSysLock();
+ }
/**
* @brief Leaves the kernel lock mode.
*
* @special
*/
- static void unlock(void);
+ static inline void unlock(void) {
+
+ chSysUnlock();
+ }
/**
* @brief Enters the kernel lock mode from within an interrupt handler.
@@ -80,7 +138,10 @@ namespace chibios_rt {
*
* @special
*/
- static void lockFromIsr(void);
+ static inline void lockFromIsr(void) {
+
+ chSysLockFromISR();
+ }
/**
* @brief Leaves the kernel lock mode from within an interrupt handler.
@@ -95,8 +156,10 @@ namespace chibios_rt {
*
* @special
*/
- static void unlockFromIsr(void);
+ static inline void unlockFromIsr(void) {
+ chSysUnlockFromISR();
+ }
/**
* @brief Returns the system time as system ticks.
@@ -106,7 +169,23 @@ namespace chibios_rt {
*
* @api
*/
- static systime_t getTime(void);
+ static inline systime_t getTime(void) {
+
+ return chVTGetSystemTime();
+ }
+
+ /**
+ * @brief Returns the system time as system ticks.
+ * @note The system tick time interval is implementation dependent.
+ *
+ * @return The system time.
+ *
+ * @xclass
+ */
+ static inline systime_t getTimeX(void) {
+
+ return chVTGetSystemTimeX();
+ }
/**
* @brief Checks if the current system time is within the specified time
@@ -121,11 +200,15 @@ namespace chibios_rt {
*
* @api
*/
- static bool isTimeWithin(systime_t start, systime_t end);
+ static inline bool isSystemTimeWithin(systime_t start, systime_t end) {
+
+ return chVTIsSystemTimeWithin(start, end);
+ }
};
+#if CH_CFG_USE_MEMCORE || defined(__DOXYGEN__)
/*------------------------------------------------------------------------*
- * chibios_rt::System *
+ * chibios_rt::Core *
*------------------------------------------------------------------------*/
/**
* @brief Class encapsulating the base system functionalities.
@@ -145,7 +228,10 @@ namespace chibios_rt {
*
* @api
*/
- static void *alloc(size_t size);
+ static inline void *alloc(size_t size) {
+
+ return chCoreAlloc(size);
+ }
/**
* @brief Allocates a memory block.
@@ -159,17 +245,24 @@ namespace chibios_rt {
*
* @iclass
*/
- static void *allocI(size_t size);
+ static inline void *allocI(size_t size) {
+
+ return chCoreAllocI(size);
+ }
/**
* @brief Core memory status.
*
* @return The size, in bytes, of the free core memory.
*
- * @api
+ * @xclass
*/
- static size_t getStatus(void);
+ static inline size_t getStatusX(void) {
+
+ return chCoreGetStatusX();
+ }
};
+#endif /* CH_CFG_USE_MEMCORE */
/*------------------------------------------------------------------------*
* chibios_rt::Timer *
@@ -182,7 +275,7 @@ namespace chibios_rt {
/**
* @brief Embedded @p VirtualTimer structure.
*/
- ::VirtualTimer timer_ref;
+ ::virtual_timer_t timer_ref;
/**
* @brief Enables a virtual timer.
@@ -202,14 +295,14 @@ namespace chibios_rt {
*
* @iclass
*/
- void setI(systime_t time, vtfunc_t vtfunc, void *par);
+ inline void setI(systime_t time, vtfunc_t vtfunc, void *par);
/**
* @brief Resets the timer, if armed.
*
* @iclass
*/
- void resetI();
+ inline void resetI();
/**
* @brief Returns the timer status.
@@ -219,44 +312,22 @@ namespace chibios_rt {
*
* @iclass
*/
- bool isArmedI(void);
+ inline bool isArmedI(void);
};
/*------------------------------------------------------------------------*
- * chibios_rt::ThreadReference *
+ * chibios_rt::ThreadStayPoint *
*------------------------------------------------------------------------*/
/**
- * @brief Thread reference class.
- * @details This class encapsulates a reference to a system thread. All
- * operations involving another thread are performed through
- * an object of this type.
+ * @brief Thread suspension point class.
+ * @details This class encapsulates a reference to a suspended thread.
*/
- class ThreadReference {
+ class ThreadStayPoint {
public:
/**
* @brief Pointer to the system thread.
*/
- ::Thread *thread_ref;
-
- /**
- * @brief Thread reference constructor.
- *
- * @param[in] tp the target thread. This parameter can be
- * @p NULL if the thread is not known at
- * creation time.
- *
- * @init
- */
- ThreadReference(Thread *tp) : thread_ref(tp) {
-
- };
-
- /**
- * @brief Stops the thread.
- * @note The implementation is left to descendant classes and is
- * optional.
- */
- virtual void stop(void);
+ ::thread_reference_t thread_ref;
/**
* @brief Suspends the current thread on the reference.
@@ -266,39 +337,89 @@ namespace chibios_rt {
*
* @return The incoming message.
*
- * @api
+ * @sclass
*/
- msg_t suspend(void);
+ inline msg_t suspendS(void);
/**
- * @brief Suspends the current thread on the reference.
+ * @brief Suspends the current thread on the reference with timeout.
* @details The suspended thread becomes the referenced thread. It is
* possible to use this method only if the thread reference
* was set to @p NULL.
*
- * @return The incoming message.
+ *
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return A message specifying how the invoking thread has
+ * been released from the semaphore.
+ * @retval MSG_OK if the binary semaphore has been successfully
+ * taken.
+ * @retval MSG_RESET if the binary semaphore has been reset using
+ * @p bsemReset().
+ * @retval MSG_TIMEOUT if the binary semaphore has not been signaled
+ * or reset within the specified timeout.
*
* @sclass
*/
- msg_t suspendS(void);
+ inline msg_t suspendS(systime_t timeout);
/**
* @brief Resumes the currently referenced thread, if any.
*
* @param[in] msg the wakeup message
*
- * @api
+ * @iclass
*/
- void resume(msg_t msg);
+ inline void resumeI(msg_t msg);
/**
* @brief Resumes the currently referenced thread, if any.
*
* @param[in] msg the wakeup message
*
- * @iclass
+ * @sclass
+ */
+ inline void resumeS(msg_t msg);
+ };
+
+ /*------------------------------------------------------------------------*
+ * chibios_rt::ThreadReference *
+ *------------------------------------------------------------------------*/
+ /**
+ * @brief Thread reference class.
+ * @details This class encapsulates a reference to a system thread. All
+ * operations involving another thread are performed through
+ * an object of this type.
+ */
+ class ThreadReference {
+ public:
+ /**
+ * @brief Pointer to the system thread.
*/
- void resumeI(msg_t msg);
+ ::thread_t *thread_ref;
+
+ /**
+ * @brief Thread reference constructor.
+ *
+ * @param[in] tp the target thread. This parameter can be
+ * @p NULL if the thread is not known at
+ * creation time.
+ *
+ * @init
+ */
+ ThreadReference(thread_t *tp) : thread_ref(tp) {
+
+ };
+
+ /**
+ * @brief Stops the thread.
+ * @note The implementation is left to descendant classes and is
+ * optional.
+ */
+ virtual void stop(void);
/**
* @brief Requests a thread termination.
@@ -312,7 +433,7 @@ namespace chibios_rt {
*/
void requestTerminate(void);
-#if CH_USE_WAITEXIT || defined(__DOXYGEN__)
+#if CH_CFG_USE_WAITEXIT || defined(__DOXYGEN__)
/**
* @brief Blocks the execution of the invoking thread until the specified
* thread terminates then the exit code is returned.
@@ -346,9 +467,9 @@ namespace chibios_rt {
* @api
*/
msg_t wait(void);
-#endif /* CH_USE_WAITEXIT */
+#endif /* CH_CFG_USE_WAITEXIT */
-#if CH_USE_MESSAGES || defined(__DOXYGEN__)
+#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__)
/**
* @brief Sends a message to the thread and returns the answer.
*
@@ -386,9 +507,9 @@ namespace chibios_rt {
* @api
*/
void releaseMessage(msg_t msg);
-#endif /* CH_USE_MESSAGES */
+#endif /* CH_CFG_USE_MESSAGES */
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
/**
* @brief Adds a set of event flags directly to specified @p Thread.
*
@@ -406,10 +527,10 @@ namespace chibios_rt {
* @iclass
*/
void signalEventsI(eventmask_t mask);
-#endif /* CH_USE_EVENTS */
+#endif /* CH_CFG_USE_EVENTS */
-#if CH_USE_DYNAMIC || defined(__DOXYGEN__)
-#endif /* CH_USE_DYNAMIC */
+#if CH_CFG_USE_DYNAMIC || defined(__DOXYGEN__)
+#endif /* CH_CFG_USE_DYNAMIC */
};
/*------------------------------------------------------------------------*
@@ -435,7 +556,7 @@ namespace chibios_rt {
*
* @api
*/
- virtual msg_t main(void);
+ virtual void main(void);
/**
* @brief Creates and starts a system thread.
@@ -550,7 +671,7 @@ namespace chibios_rt {
*/
static void yield(void);
-#if CH_USE_MESSAGES || defined(__DOXYGEN__)
+#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__)
/**
* @brief Waits for a message.
*
@@ -559,9 +680,9 @@ namespace chibios_rt {
* @api
*/
static ThreadReference waitMessage(void);
-#endif /* CH_USE_MESSAGES */
+#endif /* CH_CFG_USE_MESSAGES */
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
/**
* @brief Clears the pending events specified in the mask.
*
@@ -630,7 +751,7 @@ namespace chibios_rt {
*/
static eventmask_t waitAllEvents(eventmask_t ewmask);
-#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__)
+#if CH_CFG_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__)
/**
* @brief Waits for a single event.
* @details A pending event among those specified in @p ewmask is selected,
@@ -689,7 +810,7 @@ namespace chibios_rt {
*/
static eventmask_t waitAllEventsTimeout(eventmask_t ewmask,
systime_t time);
-#endif /* CH_USE_EVENTS_TIMEOUT */
+#endif /* CH_CFG_USE_EVENTS_TIMEOUT */
/**
* @brief Invokes the event handlers associated to an event flags mask.
@@ -702,9 +823,9 @@ namespace chibios_rt {
*/
static void dispatchEvents(const evhandler_t handlers[],
eventmask_t mask);
-#endif /* CH_USE_EVENTS */
+#endif /* CH_CFG_USE_EVENTS */
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Unlocks the next owned mutex in reverse lock order.
* @pre The invoking thread must have at least one owned mutex.
@@ -715,7 +836,7 @@ namespace chibios_rt {
*
* @api
*/
- static void unlockMutex(void);
+ static void unlockMutex(Mutex *mp);
/**
* @brief Unlocks the next owned mutex in reverse lock order.
@@ -729,7 +850,7 @@ namespace chibios_rt {
*
* @sclass
*/
- static void unlockMutexS(void);
+ static void unlockMutexS(Mutex *mp);
/**
* @brief Unlocks all the mutexes owned by the invoking thread.
@@ -743,7 +864,7 @@ namespace chibios_rt {
* @api
*/
static void unlockAllMutexes(void);
-#endif /* CH_USE_MUTEXES */
+#endif /* CH_CFG_USE_MUTEXES */
};
/*------------------------------------------------------------------------*
@@ -758,7 +879,7 @@ namespace chibios_rt {
template
class BaseStaticThread : public BaseThread {
protected:
- WORKING_AREA(wa, N);
+ THD_WORKING_AREA(wa, N);
public:
/**
@@ -782,14 +903,14 @@ namespace chibios_rt {
* @api
*/
virtual ThreadReference start(tprio_t prio) {
- msg_t _thd_start(void *arg);
+ void _thd_start(void *arg);
thread_ref = chThdCreateStatic(wa, sizeof(wa), prio, _thd_start, this);
return *this;
}
};
-#if CH_USE_SEMAPHORES || defined(__DOXYGEN__)
+#if CH_CFG_USE_SEMAPHORES || defined(__DOXYGEN__)
/*------------------------------------------------------------------------*
* chibios_rt::CounterSemaphore *
*------------------------------------------------------------------------*/
@@ -801,7 +922,7 @@ namespace chibios_rt {
/**
* @brief Embedded @p ::Semaphore structure.
*/
- ::Semaphore sem;
+ ::semaphore_t sem;
/**
* @brief CounterSemaphore constructor.
@@ -821,7 +942,7 @@ namespace chibios_rt {
* set to the specified, non negative, value.
* @note The released threads can recognize they were waked up by a
* reset rather than a signal because the @p chSemWait() will
- * return @p RDY_RESET instead of @p RDY_OK.
+ * return @p MSG_RESET instead of @p MSG_OK.
*
* @param[in] n the new value of the semaphore counter. The value
* must be non-negative.
@@ -841,7 +962,7 @@ namespace chibios_rt {
* explicit reschedule must not be performed in ISRs.
* @note The released threads can recognize they were waked up by a
* reset rather than a signal because the @p chSemWait() will
- * return @p RDY_RESET instead of @p RDY_OK.
+ * return @p MSG_RESET instead of @p MSG_OK.
*
* @param[in] n the new value of the semaphore counter. The value
* must be non-negative.
@@ -855,9 +976,9 @@ namespace chibios_rt {
*
* @return A message specifying how the invoking thread has
* been released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or
+ * @retval MSG_OK if the thread has not stopped on the semaphore or
* the semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using
+ * @retval MSG_RESET if the semaphore has been reset using
* @p chSemReset().
*
* @api
@@ -869,9 +990,9 @@ namespace chibios_rt {
*
* @return A message specifying how the invoking thread has
* been released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or
+ * @retval MSG_OK if the thread has not stopped on the semaphore or
* the semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using
+ * @retval MSG_RESET if the semaphore has been reset using
* @p chSemReset().
*
* @sclass
@@ -889,16 +1010,16 @@ namespace chibios_rt {
* .
* @return A message specifying how the invoking thread has
* been released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or
+ * @retval MSG_OK if the thread has not stopped on the semaphore or
* the semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using
+ * @retval MSG_RESET if the semaphore has been reset using
* @p chSemReset().
- * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset
+ * @retval MSG_TIMEOUT if the semaphore has not been signaled or reset
* within the specified timeout.
*
* @api
*/
- msg_t waitTimeout(systime_t time);
+ msg_t wait(systime_t time);
/**
* @brief Performs a wait operation on a semaphore with timeout
@@ -911,16 +1032,16 @@ namespace chibios_rt {
* .
* @return A message specifying how the invoking thread has
* been released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore or
+ * @retval MSG_OK if the thread has not stopped on the semaphore or
* the semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using
+ * @retval MSG_RESET if the semaphore has been reset using
* @p chSemReset().
- * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset
+ * @retval MSG_TIMEOUT if the semaphore has not been signaled or reset
* within the specified timeout.
*
* @sclass
*/
- msg_t waitTimeoutS(systime_t time);
+ msg_t waitS(systime_t time);
/**
* @brief Performs a signal operation on a semaphore.
@@ -963,7 +1084,6 @@ namespace chibios_rt {
*/
cnt_t getCounterI(void);
-#if CH_USE_SEMSW || defined(__DOXYGEN__)
/**
* @brief Atomic signal and wait operations.
*
@@ -971,16 +1091,15 @@ namespace chibios_rt {
* @param[in] wsem @p Semaphore object to wait on
* @return A message specifying how the invoking thread
* has been released from the semaphore.
- * @retval RDY_OK if the thread has not stopped on the semaphore
+ * @retval MSG_OK if the thread has not stopped on the semaphore
* or the semaphore has been signaled.
- * @retval RDY_RESET if the semaphore has been reset using
+ * @retval MSG_RESET if the semaphore has been reset using
* @p chSemReset().
*
* @api
*/
static msg_t signalWait(CounterSemaphore *ssem,
CounterSemaphore *wsem);
-#endif /* CH_USE_SEMSW */
};
/*------------------------------------------------------------------------*
* chibios_rt::BinarySemaphore *
@@ -993,7 +1112,7 @@ namespace chibios_rt {
/**
* @brief Embedded @p ::Semaphore structure.
*/
- ::BinarySemaphore bsem;
+ ::binary_semaphore_t bsem;
/**
* @brief BinarySemaphore constructor.
@@ -1013,9 +1132,9 @@ namespace chibios_rt {
*
* @return A message specifying how the invoking thread has
* been released from the semaphore.
- * @retval RDY_OK if the binary semaphore has been successfully
+ * @retval MSG_OK if the binary semaphore has been successfully
* taken.
- * @retval RDY_RESET if the binary semaphore has been reset using
+ * @retval MSG_RESET if the binary semaphore has been reset using
* @p bsemReset().
*
* @api
@@ -1027,9 +1146,9 @@ namespace chibios_rt {
*
* @return A message specifying how the invoking thread has
* been released from the semaphore.
- * @retval RDY_OK if the binary semaphore has been successfully
+ * @retval MSG_OK if the binary semaphore has been successfully
* taken.
- * @retval RDY_RESET if the binary semaphore has been reset using
+ * @retval MSG_RESET if the binary semaphore has been reset using
* @p bsemReset().
*
* @sclass
@@ -1046,16 +1165,16 @@ namespace chibios_rt {
* .
* @return A message specifying how the invoking thread has
* been released from the semaphore.
- * @retval RDY_OK if the binary semaphore has been successfully
+ * @retval MSG_OK if the binary semaphore has been successfully
* taken.
- * @retval RDY_RESET if the binary semaphore has been reset using
+ * @retval MSG_RESET if the binary semaphore has been reset using
* @p bsemReset().
- * @retval RDY_TIMEOUT if the binary semaphore has not been signaled
+ * @retval MSG_TIMEOUT if the binary semaphore has not been signaled
* or reset within the specified timeout.
*
* @api
*/
- msg_t waitTimeout(systime_t time);
+ msg_t wait(systime_t time);
/**
* @brief Wait operation on the binary semaphore.
@@ -1067,22 +1186,22 @@ namespace chibios_rt {
* .
* @return A message specifying how the invoking thread has
* been released from the semaphore.
- * @retval RDY_OK if the binary semaphore has been successfully
+ * @retval MSG_OK if the binary semaphore has been successfully
* taken.
- * @retval RDY_RESET if the binary semaphore has been reset using
+ * @retval MSG_RESET if the binary semaphore has been reset using
* @p bsemReset().
- * @retval RDY_TIMEOUT if the binary semaphore has not been signaled
+ * @retval MSG_TIMEOUT if the binary semaphore has not been signaled
* or reset within the specified timeout.
*
* @sclass
*/
- msg_t waitTimeoutS(systime_t time);
+ msg_t waitS(systime_t time);
/**
* @brief Reset operation on the binary semaphore.
* @note The released threads can recognize they were waked up by a
* reset rather than a signal because the @p bsemWait() will
- * return @p RDY_RESET instead of @p RDY_OK.
+ * return @p MSG_RESET instead of @p MSG_OK.
*
* @param[in] taken new state of the binary semaphore
* - @a FALSE, the new state is not taken.
@@ -1097,7 +1216,7 @@ namespace chibios_rt {
* @brief Reset operation on the binary semaphore.
* @note The released threads can recognize they were waked up by a
* reset rather than a signal because the @p bsemWait() will
- * return @p RDY_RESET instead of @p RDY_OK.
+ * return @p MSG_RESET instead of @p MSG_OK.
* @note This function does not reschedule.
*
* @param[in] taken new state of the binary semaphore
@@ -1135,9 +1254,9 @@ namespace chibios_rt {
*/
bool getStateI(void);
};
-#endif /* CH_USE_SEMAPHORES */
+#endif /* CH_CFG_USE_SEMAPHORES */
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
/*------------------------------------------------------------------------*
* chibios_rt::Mutex *
*------------------------------------------------------------------------*/
@@ -1149,7 +1268,7 @@ namespace chibios_rt {
/**
* @brief Embedded @p ::Mutex structure.
*/
- ::Mutex mutex;
+ ::mutex_t mutex;
/**
* @brief Mutex object constructor.
@@ -1214,9 +1333,31 @@ namespace chibios_rt {
* @sclass
*/
void lockS(void);
+
+ /**
+ * @brief Unlocks the next owned mutex in reverse lock order.
+ * @pre The invoking thread must have at least one owned mutex.
+ * @post The mutex is unlocked and removed from the per-thread stack of
+ * owned mutexes.
+ *
+ * @api
+ */
+ void unlock(void);
+
+ /**
+ * @brief Unlocks the next owned mutex in reverse lock order.
+ * @pre The invoking thread must have at least one owned mutex.
+ * @post The mutex is unlocked and removed from the per-thread stack of
+ * owned mutexes.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel.
+ *
+ * @sclass
+ */
+ void unlockS(void);
};
-#if CH_USE_CONDVARS || defined(__DOXYGEN__)
+#if CH_CFG_USE_CONDVARS || defined(__DOXYGEN__)
/*------------------------------------------------------------------------*
* chibios_rt::CondVar *
*------------------------------------------------------------------------*/
@@ -1228,7 +1369,7 @@ namespace chibios_rt {
/**
* @brief Embedded @p ::CondVar structure.
*/
- ::CondVar condvar;
+ ::condition_variable_t condvar;
/**
* @brief CondVar object constructor.
@@ -1283,9 +1424,9 @@ namespace chibios_rt {
*
* @return A message specifying how the invoking thread has
* been released from the condition variable.
- * @retval RDY_OK if the condvar has been signaled using
+ * @retval MSG_OK if the condvar has been signaled using
* @p chCondSignal().
- * @retval RDY_RESET if the condvar has been signaled using
+ * @retval MSG_RESET if the condvar has been signaled using
* @p chCondBroadcast().
*
* @api
@@ -1301,37 +1442,37 @@ namespace chibios_rt {
*
* @return A message specifying how the invoking thread has
* been released from the condition variable.
- * @retval RDY_OK if the condvar has been signaled using
+ * @retval MSG_OK if the condvar has been signaled using
* @p chCondSignal().
- * @retval RDY_RESET if the condvar has been signaled using
+ * @retval MSG_RESET if the condvar has been signaled using
* @p chCondBroadcast().
*
* @sclass
*/
msg_t waitS(void);
-#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__)
+#if CH_CFG_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__)
/**
* @brief Waits on the CondVar while releasing the controlling mutex.
*
* @param[in] time the number of ticks before the operation fails
* @return The wakep mode.
- * @retval RDY_OK if the condvar was signaled using
+ * @retval MSG_OK if the condvar was signaled using
* @p chCondSignal().
- * @retval RDY_RESET if the condvar was signaled using
+ * @retval MSG_RESET if the condvar was signaled using
* @p chCondBroadcast().
- * @retval RDY_TIMEOUT if the condvar was not signaled within the
+ * @retval MSG_TIMEOUT if the condvar was not signaled within the
* specified timeout.
*
* @api
*/
- msg_t waitTimeout(systime_t time);
-#endif /* CH_USE_CONDVARS_TIMEOUT */
+ msg_t wait(systime_t time);
+#endif /* CH_CFG_USE_CONDVARS_TIMEOUT */
};
-#endif /* CH_USE_CONDVARS */
-#endif /* CH_USE_MUTEXES */
+#endif /* CH_CFG_USE_CONDVARS */
+#endif /* CH_CFG_USE_MUTEXES */
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
/*------------------------------------------------------------------------*
* chibios_rt::EvtListener *
*------------------------------------------------------------------------*/
@@ -1343,7 +1484,7 @@ namespace chibios_rt {
/**
* @brief Embedded @p ::EventListener structure.
*/
- struct ::EventListener ev_listener;
+ ::event_listener_t ev_listener;
/**
* @brief Returns the pending flags from the listener and clears them.
@@ -1353,7 +1494,7 @@ namespace chibios_rt {
*
* @api
*/
- flagsmask_t getAndClearFlags(void);
+ eventflags_t getAndClearFlags(void);
/**
* @brief Returns the flags associated to an @p EventListener.
@@ -1365,7 +1506,7 @@ namespace chibios_rt {
*
* @iclass
*/
- flagsmask_t getAndClearFlagsI(void);
+ eventflags_t getAndClearFlagsI(void);
};
/*------------------------------------------------------------------------*
@@ -1379,7 +1520,7 @@ namespace chibios_rt {
/**
* @brief Embedded @p ::EventSource structure.
*/
- struct ::EventSource ev_source;
+ ::event_source_t ev_source;
/**
* @brief EvtSource object constructor.
@@ -1433,7 +1574,7 @@ namespace chibios_rt {
*
* @api
*/
- void broadcastFlags(flagsmask_t flags);
+ void broadcastFlags(eventflags_t flags);
/**
* @brief Broadcasts on an event source.
@@ -1445,389 +1586,27 @@ namespace chibios_rt {
*
* @iclass
*/
- void broadcastFlagsI(flagsmask_t flags);
+ void broadcastFlagsI(eventflags_t flags);
};
-#endif /* CH_USE_EVENTS */
+#endif /* CH_CFG_USE_EVENTS */
-#if CH_USE_QUEUES || defined(__DOXYGEN__)
+#if CH_CFG_USE_MAILBOXES || defined(__DOXYGEN__)
/*------------------------------------------------------------------------*
- * chibios_rt::InQueue *
- *------------------------------------------------------------------------*/
- /**
- * @brief Class encapsulating an input queue.
- */
- class InQueue {
- private:
- /**
- * @brief Embedded @p ::InputQueue structure.
- */
- ::InputQueue iq;
-
- public:
- /**
- * @brief InQueue constructor.
- *
- * @param[in] bp pointer to a memory area allocated as queue buffer
- * @param[in] size size of the queue buffer
- * @param[in] infy pointer to a callback function that is invoked when
- * data is read from the queue. The value can be
- * @p NULL.
- * @param[in] link application defined pointer
- *
- * @init
- */
- InQueue(uint8_t *bp, size_t size, qnotify_t infy, void *link);
-
- /**
- * @brief Returns the filled space into an input queue.
- *
- * @return The number of full bytes in the queue.
- * @retval 0 if the queue is empty.
- *
- * @iclass
- */
- size_t getFullI(void);
-
- /**
- * @brief Returns the empty space into an input queue.
- *
- * @return The number of empty bytes in the queue.
- * @retval 0 if the queue is full.
- *
- * @iclass
- */
- size_t getEmptyI(void);
-
- /**
- * @brief Evaluates to @p TRUE if the specified input queue is empty.
- *
- * @return The queue status.
- * @retval false if the queue is not empty.
- * @retval true if the queue is empty.
- *
- * @iclass
- */
- bool isEmptyI(void);
-
- /**
- * @brief Evaluates to @p TRUE if the specified input queue is full.
- *
- * @return The queue status.
- * @retval FALSE if the queue is not full.
- * @retval TRUE if the queue is full.
- *
- * @iclass
- */
- bool isFullI(void);
-
- /**
- * @brief Resets an input queue.
- * @details All the data in the input queue is erased and lost, any waiting
- * thread is resumed with status @p Q_RESET.
- * @note A reset operation can be used by a low level driver in order to
- * obtain immediate attention from the high level layers.
- * @iclass
- */
- void resetI(void);
-
- /**
- * @brief Input queue write.
- * @details A byte value is written into the low end of an input queue.
- *
- * @param[in] b the byte value to be written in the queue
- * @return The operation status.
- * @retval Q_OK if the operation has been completed with success.
- * @retval Q_FULL if the queue is full and the operation cannot be
- * completed.
- *
- * @iclass
- */
- msg_t putI(uint8_t b);
-
- /**
- * @brief Input queue read.
- * @details This function reads a byte value from an input queue. If the
- * queue is empty then the calling thread is suspended until a
- * byte arrives in the queue.
- *
- * @return A byte value from the queue.
- * @retval Q_RESET if the queue has been reset.
- *
- * @api
- */
- msg_t get();
-
- /**
- * @brief Input queue read with timeout.
- * @details This function reads a byte value from an input queue. If the
- * queue is empty then the calling thread is suspended until a
- * byte arrives in the queue or a timeout occurs.
- * @note The callback is invoked before reading the character from the
- * buffer or before entering the state @p THD_STATE_WTQUEUE.
- *
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return A byte value from the queue.
- * @retval Q_TIMEOUT if the specified time expired.
- * @retval Q_RESET if the queue has been reset.
- *
- * @api
- */
- msg_t getTimeout(systime_t time);
-
- /**
- * @brief Input queue read with timeout.
- * @details The function reads data from an input queue into a buffer. The
- * operation completes when the specified amount of data has been
- * transferred or after the specified timeout or if the queue has
- * been reset.
- * @note The function is not atomic, if you need atomicity it is
- * suggested to use a semaphore or a mutex for mutual exclusion.
- * @note The callback is invoked before reading each character from the
- * buffer or before entering the state @p THD_STATE_WTQUEUE.
- *
- * @param[out] bp pointer to the data buffer
- * @param[in] n the maximum amount of data to be transferred, the
- * value 0 is reserved
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The number of bytes effectively transferred.
- *
- * @api
- */
- size_t readTimeout(uint8_t *bp, size_t n, systime_t time);
- };
-
- /*------------------------------------------------------------------------*
- * chibios_rt::InQueueBuffer *
- *------------------------------------------------------------------------*/
- /**
- * @brief Template class encapsulating an input queue and its buffer.
- *
- * @param N size of the input queue
- */
- template
- class InQueueBuffer : public InQueue {
- private:
- uint8_t iq_buf[N];
-
- public:
- /**
- * @brief InQueueBuffer constructor.
- *
- * @param[in] infy input notify callback function
- * @param[in] link parameter to be passed to the callback
- *
- * @init
- */
- InQueueBuffer(qnotify_t infy, void *link) : InQueue(iq_buf, N,
- infy, link) {
- }
- };
-
- /*------------------------------------------------------------------------*
- * chibios_rt::OutQueue *
- *------------------------------------------------------------------------*/
- /**
- * @brief Class encapsulating an output queue.
- */
- class OutQueue {
- private:
- /**
- * @brief Embedded @p ::OutputQueue structure.
- */
- ::OutputQueue oq;
-
- public:
- /**
- * @brief OutQueue constructor.
- *
- * @param[in] bp pointer to a memory area allocated as queue buffer
- * @param[in] size size of the queue buffer
- * @param[in] onfy pointer to a callback function that is invoked when
- * data is written to the queue. The value can be
- * @p NULL.
- * @param[in] link application defined pointer
- *
- * @init
- */
- OutQueue(uint8_t *bp, size_t size, qnotify_t onfy, void *link);
-
- /**
- * @brief Returns the filled space into an output queue.
- *
- * @return The number of full bytes in the queue.
- * @retval 0 if the queue is empty.
- *
- * @iclass
- */
- size_t getFullI(void);
-
- /**
- * @brief Returns the empty space into an output queue.
- *
- * @return The number of empty bytes in the queue.
- * @retval 0 if the queue is full.
- *
- * @iclass
- */
- size_t getEmptyI(void);
-
- /**
- * @brief Evaluates to @p TRUE if the specified output queue is empty.
- *
- * @return The queue status.
- * @retval false if the queue is not empty.
- * @retval true if the queue is empty.
- *
- * @iclass
- */
- bool isEmptyI(void);
-
- /**
- * @brief Evaluates to @p TRUE if the specified output queue is full.
- *
- * @return The queue status.
- * @retval FALSE if the queue is not full.
- * @retval TRUE if the queue is full.
- *
- * @iclass
- */
- bool isFullI(void);
-
- /**
- * @brief Resets an output queue.
- * @details All the data in the output queue is erased and lost, any
- * waiting thread is resumed with status @p Q_RESET.
- * @note A reset operation can be used by a low level driver in order
- * to obtain immediate attention from the high level layers.
- *
- * @iclass
- */
- void resetI(void);
-
- /**
- * @brief Output queue write.
- * @details This function writes a byte value to an output queue. If the
- * queue is full then the calling thread is suspended until there
- * is space in the queue.
- *
- * @param[in] b the byte value to be written in the queue
- * @return The operation status.
- * @retval Q_OK if the operation succeeded.
- * @retval Q_RESET if the queue has been reset.
- *
- * @api
- */
- msg_t put(uint8_t b);
-
- /**
- * @brief Output queue write with timeout.
- * @details This function writes a byte value to an output queue. If the
- * queue is full then the calling thread is suspended until there
- * is space in the queue or a timeout occurs.
- * @note The callback is invoked after writing the character into the
- * buffer.
- *
- * @param[in] b the byte value to be written in the queue
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval Q_OK if the operation succeeded.
- * @retval Q_TIMEOUT if the specified time expired.
- * @retval Q_RESET if the queue has been reset.
- *
- * @api
- */
- msg_t putTimeout(uint8_t b, systime_t time);
-
- /**
- * @brief Output queue read.
- * @details A byte value is read from the low end of an output queue.
- *
- * @return The byte value from the queue.
- * @retval Q_EMPTY if the queue is empty.
- *
- * @iclass
- */
- msg_t getI(void);
-
- /**
- * @brief Output queue write with timeout.
- * @details The function writes data from a buffer to an output queue. The
- * operation completes when the specified amount of data has been
- * transferred or after the specified timeout or if the queue has
- * been reset.
- * @note The function is not atomic, if you need atomicity it is
- * suggested to use a semaphore or a mutex for mutual exclusion.
- * @note The callback is invoked after writing each character into the
- * buffer.
- *
- * @param[out] bp pointer to the data buffer
- * @param[in] n the maximum amount of data to be transferred, the
- * value 0 is reserved
- * @param[in] time the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The number of bytes effectively transferred.
- *
- * @api
- */
- size_t writeTimeout(const uint8_t *bp, size_t n, systime_t time);
-};
-
- /*------------------------------------------------------------------------*
- * chibios_rt::OutQueueBuffer *
+ * chibios_rt::Mailbox *
*------------------------------------------------------------------------*/
/**
- * @brief Template class encapsulating an output queue and its buffer.
+ * @brief Base mailbox class.
*
- * @param N size of the output queue
+ * @param T type of objects that mailbox able to handle
*/
- template
- class OutQueueBuffer : public OutQueue {
- private:
- uint8_t oq_buf[N];
-
+ template
+ class MailboxBase {
public:
- /**
- * @brief OutQueueBuffer constructor.
- *
- * @param[in] onfy output notify callback function
- * @param[in] link parameter to be passed to the callback
- *
- * @init
- */
- OutQueueBuffer(qnotify_t onfy, void *link) : OutQueue(oq_buf, N,
- onfy, link) {
- }
- };
-#endif /* CH_USE_QUEUES */
-#if CH_USE_MAILBOXES || defined(__DOXYGEN__)
- /*------------------------------------------------------------------------*
- * chibios_rt::Mailbox *
- *------------------------------------------------------------------------*/
- /**
- * @brief Class encapsulating a mailbox.
- */
- class Mailbox {
- public:
/**
* @brief Embedded @p ::Mailbox structure.
*/
- ::Mailbox mb;
+ ::mailbox_t mb;
/**
* @brief Mailbox constructor.
@@ -1839,16 +1618,22 @@ namespace chibios_rt {
*
* @init
*/
- Mailbox(msg_t *buf, cnt_t n);
+ MailboxBase(msg_t *buf, cnt_t n) {
+
+ chMBObjectInit(&mb, buf, n);
+ }
/**
* @brief Resets a Mailbox object.
- * @details All the waiting threads are resumed with status @p RDY_RESET
+ * @details All the waiting threads are resumed with status @p MSG_RESET
* and the queued messages are lost.
*
* @api
*/
- void reset(void);
+ void reset(void) {
+
+ chMBReset(&mb);
+ }
/**
* @brief Posts a message into a mailbox.
@@ -1862,13 +1647,16 @@ namespace chibios_rt {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT if the operation has timed out.
*
* @api
*/
- msg_t post(msg_t msg, systime_t time);
+ msg_t post(T msg, systime_t time) {
+
+ return chMBPost(&mb, reinterpret_cast(msg), time);
+ }
/**
* @brief Posts a message into a mailbox.
@@ -1882,13 +1670,16 @@ namespace chibios_rt {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT if the operation has timed out.
*
* @sclass
*/
- msg_t postS(msg_t msg, systime_t time);
+ msg_t postS(T msg, systime_t time) {
+
+ return chMBPostS(&mb, reinterpret_cast(msg), time);
+ }
/**
* @brief Posts a message into a mailbox.
@@ -1897,13 +1688,16 @@ namespace chibios_rt {
*
* @param[in] msg the message to be posted on the mailbox
* @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_TIMEOUT if the mailbox is full and the message cannot be
* posted.
*
* @iclass
*/
- msg_t postI(msg_t msg);
+ msg_t postI(T msg) {
+
+ return chMBPostI(&mb, reinterpret_cast(msg));
+ }
/**
* @brief Posts an high priority message into a mailbox.
@@ -1917,13 +1711,16 @@ namespace chibios_rt {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT if the operation has timed out.
*
* @api
*/
- msg_t postAhead(msg_t msg, systime_t time);
+ msg_t postAhead(T msg, systime_t time) {
+
+ return chMBPostAhead(&mb, reinterpret_cast(msg), time);
+ }
/**
* @brief Posts an high priority message into a mailbox.
@@ -1937,13 +1734,16 @@ namespace chibios_rt {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_RESET if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT if the operation has timed out.
*
* @sclass
*/
- msg_t postAheadS(msg_t msg, systime_t time);
+ msg_t postAheadS(T msg, systime_t time) {
+
+ return chMBPostAheadS(&mb, reinterpret_cast(msg), time);
+ }
/**
* @brief Posts an high priority message into a mailbox.
@@ -1952,13 +1752,16 @@ namespace chibios_rt {
*
* @param[in] msg the message to be posted on the mailbox
* @return The operation status.
- * @retval RDY_OK if a message has been correctly posted.
- * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be
+ * @retval MSG_OK if a message has been correctly posted.
+ * @retval MSG_TIMEOUT if the mailbox is full and the message cannot be
* posted.
*
* @iclass
*/
- msg_t postAheadI(msg_t msg);
+ msg_t postAheadI(T msg) {
+
+ return chMBPostAheadI(&mb, reinterpret_cast(msg));
+ }
/**
* @brief Retrieves a message from a mailbox.
@@ -1972,13 +1775,16 @@ namespace chibios_rt {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if a message has been correctly fetched.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
+ * @retval MSG_OK if a message has been correctly fetched.
+ * @retval MSG_RESET if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT if the operation has timed out.
*
* @api
*/
- msg_t fetch(msg_t *msgp, systime_t time);
+ msg_t fetch(T *msgp, systime_t time) {
+
+ return chMBFetch(&mb, reinterpret_cast(msgp), time);
+ }
/**
* @brief Retrieves a message from a mailbox.
@@ -1992,13 +1798,16 @@ namespace chibios_rt {
* - @a TIME_INFINITE no timeout.
* .
* @return The operation status.
- * @retval RDY_OK if a message has been correctly fetched.
- * @retval RDY_RESET if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT if the operation has timed out.
+ * @retval MSG_OK if a message has been correctly fetched.
+ * @retval MSG_RESET if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT if the operation has timed out.
*
* @sclass
*/
- msg_t fetchS(msg_t *msgp, systime_t time);
+ msg_t fetchS(T *msgp, systime_t time) {
+
+ return chMBFetchS(&mb, reinterpret_cast(msgp), time);
+ }
/**
* @brief Retrieves a message from a mailbox.
@@ -2008,13 +1817,16 @@ namespace chibios_rt {
* @param[out] msgp pointer to a message variable for the received
* message
* @return The operation status.
- * @retval RDY_OK if a message has been correctly fetched.
- * @retval RDY_TIMEOUT if the mailbox is empty and a message cannot be
+ * @retval MSG_OK if a message has been correctly fetched.
+ * @retval MSG_TIMEOUT if the mailbox is empty and a message cannot be
* fetched.
*
* @iclass
*/
- msg_t fetchI(msg_t *msgp);
+ msg_t fetchI(T *msgp) {
+
+ return chMBFetchI(&mb, reinterpret_cast(msgp));
+ }
/**
* @brief Returns the number of free message slots into a mailbox.
@@ -2027,7 +1839,10 @@ namespace chibios_rt {
*
* @iclass
*/
- cnt_t getFreeCountI(void);
+ cnt_t getFreeCountI(void) {
+
+ return chMBGetFreeCountI(&mb);
+ }
/**
* @brief Returns the number of used message slots into a mailbox.
@@ -2040,35 +1855,38 @@ namespace chibios_rt {
*
* @iclass
*/
- cnt_t getUsedCountI(void);
+ cnt_t getUsedCountI(void) {
+
+ return chMBGetUsedCountI(&mb);
+ }
};
/*------------------------------------------------------------------------*
- * chibios_rt::MailboxBuffer *
+ * chibios_rt::Mailbox *
*------------------------------------------------------------------------*/
/**
- * @brief Template class encapsulating a mailbox and its messages buffer.
+ * @brief Template class encapsulating a mailbox and its messages buffer.
*
- * @param N size of the mailbox
+ * @param N length of the mailbox buffer
*/
- template
- class MailboxBuffer : public Mailbox {
+ template
+ class Mailbox : public MailboxBase {
private:
msg_t mb_buf[N];
public:
/**
- * @brief BufferMailbox constructor.
+ * @brief Mailbox constructor.
*
* @init
*/
- MailboxBuffer(void) : Mailbox(mb_buf,
- (cnt_t)(sizeof mb_buf / sizeof (msg_t))) {
+ Mailbox(void) :
+ MailboxBase(mb_buf, (cnt_t)(sizeof mb_buf / sizeof (msg_t))) {
}
};
-#endif /* CH_USE_MAILBOXES */
+#endif /* CH_CFG_USE_MAILBOXES */
-#if CH_USE_MEMPOOLS || defined(__DOXYGEN__)
+#if CH_CFG_USE_MEMPOOLS || defined(__DOXYGEN__)
/*------------------------------------------------------------------------*
* chibios_rt::MemoryPool *
*------------------------------------------------------------------------*/
@@ -2080,7 +1898,7 @@ namespace chibios_rt {
/**
* @brief Embedded @p ::MemoryPool structure.
*/
- ::MemoryPool pool;
+ ::memory_pool_t pool;
/**
* @brief MemoryPool constructor.
@@ -2207,7 +2025,7 @@ namespace chibios_rt {
loadArray(pool_buf, N);
}
};
-#endif /* CH_USE_MEMPOOLS */
+#endif /* CH_CFG_USE_MEMPOOLS */
/*------------------------------------------------------------------------*
* chibios_rt::BaseSequentialStreamInterface *
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/chcpp.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/chcpp.mk
new file mode 100644
index 0000000000..8e38cde8b5
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/chcpp.mk
@@ -0,0 +1,5 @@
+# C++ wrapper files.
+CHCPPSRC = $(CHIBIOS)/os/various/cpp_wrappers/ch.cpp \
+ $(CHIBIOS)/os/various/cpp_wrappers/syscalls_cpp.cpp
+
+CHCPPINC = $(CHIBIOS)/os/various/cpp_wrappers
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/kernel.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/kernel.mk
deleted file mode 100644
index 049da2d371..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/kernel.mk
+++ /dev/null
@@ -1,4 +0,0 @@
-# C++ wrapper files.
-CHCPPSRC = ${CHIBIOS}/os/various/cpp_wrappers/ch.cpp
-
-CHCPPINC = ${CHIBIOS}/os/various/cpp_wrappers
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/syscalls_cpp.cpp b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/syscalls_cpp.cpp
new file mode 100644
index 0000000000..486461a766
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/syscalls_cpp.cpp
@@ -0,0 +1,41 @@
+#include
+#include
+
+#include "osal.h"
+
+#include "syscalls_cpp.hpp"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _exit(int status){
+ (void) status;
+ osalSysHalt("Unrealized");
+ while(TRUE){}
+}
+
+pid_t _getpid(void){
+ return 1;
+}
+
+#undef errno
+extern int errno;
+int _kill(int pid, int sig) {
+ (void)pid;
+ (void)sig;
+ errno = EINVAL;
+ return -1;
+}
+
+void _open_r(void){
+ return;
+}
+
+void __cxa_pure_virtual() {
+ osalSysHalt("Pure virtual function call.");
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/syscalls_cpp.hpp b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/syscalls_cpp.hpp
new file mode 100644
index 0000000000..cd78a9c5d6
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/cpp_wrappers/syscalls_cpp.hpp
@@ -0,0 +1,13 @@
+#ifndef SYSCALLS_CPP_HPP_
+#define SYSCALLS_CPP_HPP_
+
+/* The ABI requires a 32-bit type.*/
+typedef int __guard;
+
+int __cxa_guard_acquire(__guard *);
+void __cxa_guard_release (__guard *);
+void __cxa_guard_abort (__guard *);
+
+void *__dso_handle = NULL;
+
+#endif /* SYSCALLS_CPP_HPP_ */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.c
index 0e7f6eecc1..8db74c1c86 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,7 +22,6 @@
* @{
*/
-#include "ch.h"
#include "hal.h"
#include "lis302dl.h"
@@ -81,7 +80,7 @@ void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) {
default:
/* Reserved register must not be written, according to the datasheet
this could permanently damage the device.*/
- chDbgAssert(FALSE, "lis302dlWriteRegister(), #1", "reserved register");
+ osalDbgAssert(FALSE, "reserved register");
case LIS302DL_WHO_AM_I:
case LIS302DL_HP_FILTER_RESET:
case LIS302DL_STATUS_REG:
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.dox
index fc83535a04..b0a979104c 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.dox
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.dox
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.h
index efa11f549a..df5d430237 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/accel/lis302dl.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,8 +22,8 @@
* @{
*/
-#ifndef _LIS302DL_H_
-#define _LIS302DL_H_
+#ifndef LIS302DL_H
+#define LIS302DL_H
/*===========================================================================*/
/* Driver constants. */
@@ -88,6 +88,6 @@ extern "C" {
}
#endif
-#endif /* _LIS302DL_H_ */
+#endif /* LIS302DL_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/lcd/lcd3310.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/lcd/lcd3310.c
new file mode 100644
index 0000000000..1c3b8398b4
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/lcd/lcd3310.c
@@ -0,0 +1,310 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file lcd3310.c
+ * @brief Nokia 3310 LCD interface module through SPI code.
+ *
+ * @addtogroup lcd3310
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+#include "lcd3310.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+const uint8_t Fonts8x5 [][LCD3310_FONT_X_SIZE] =
+{
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, /* space */
+ { 0x00, 0x00, 0x2f, 0x00, 0x00 }, /* ! */
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, /* " */
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, /* # */
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, /* $ */
+ { 0xc4, 0xc8, 0x10, 0x26, 0x46 }, /* % */
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, /* & */
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, /* ' */
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, /* ( */
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, /* ) */
+ { 0x14, 0x08, 0x3E, 0x08, 0x14 }, /* * */
+ { 0x08, 0x08, 0x3E, 0x08, 0x08 }, /* + */
+ { 0x00, 0x00, 0x50, 0x30, 0x00 }, /* , */
+ { 0x10, 0x10, 0x10, 0x10, 0x10 }, /* - */
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, /* . */
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, /* / */
+ { 0x3E, 0x51, 0x49, 0x45, 0x3E }, /* 0 */
+ { 0x00, 0x42, 0x7F, 0x40, 0x00 }, /* 1 */
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, /* 2 */
+ { 0x21, 0x41, 0x45, 0x4B, 0x31 }, /* 3 */
+ { 0x18, 0x14, 0x12, 0x7F, 0x10 }, /* 4 */
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, /* 5 */
+ { 0x3C, 0x4A, 0x49, 0x49, 0x30 }, /* 6 */
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, /* 7 */
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, /* 8 */
+ { 0x06, 0x49, 0x49, 0x29, 0x1E }, /* 9 */
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, /* : */
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, /* ; */
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, /* < */
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, /* = */
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, /* > */
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, /* ? */
+ { 0x32, 0x49, 0x59, 0x51, 0x3E }, /* @ */
+ { 0x7E, 0x11, 0x11, 0x11, 0x7E }, /* A */
+ { 0x7F, 0x49, 0x49, 0x49, 0x36 }, /* B */
+ { 0x3E, 0x41, 0x41, 0x41, 0x22 }, /* C */
+ { 0x7F, 0x41, 0x41, 0x22, 0x1C }, /* D */
+ { 0x7F, 0x49, 0x49, 0x49, 0x41 }, /* E */
+ { 0x7F, 0x09, 0x09, 0x09, 0x01 }, /* F */
+ { 0x3E, 0x41, 0x49, 0x49, 0x7A }, /* G */
+ { 0x7F, 0x08, 0x08, 0x08, 0x7F }, /* H */
+ { 0x00, 0x41, 0x7F, 0x41, 0x00 }, /* I */
+ { 0x20, 0x40, 0x41, 0x3F, 0x01 }, /* J */
+ { 0x7F, 0x08, 0x14, 0x22, 0x41 }, /* K */
+ { 0x7F, 0x40, 0x40, 0x40, 0x40 }, /* L */
+ { 0x7F, 0x02, 0x0C, 0x02, 0x7F }, /* M */
+ { 0x7F, 0x04, 0x08, 0x10, 0x7F }, /* N */
+ { 0x3E, 0x41, 0x41, 0x41, 0x3E }, /* O */
+ { 0x7F, 0x09, 0x09, 0x09, 0x06 }, /* P */
+ { 0x3E, 0x41, 0x51, 0x21, 0x5E }, /* Q */
+ { 0x7F, 0x09, 0x19, 0x29, 0x46 }, /* R */
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, /* S */
+ { 0x01, 0x01, 0x7F, 0x01, 0x01 }, /* T */
+ { 0x3F, 0x40, 0x40, 0x40, 0x3F }, /* U */
+ { 0x1F, 0x20, 0x40, 0x20, 0x1F }, /* V */
+ { 0x3F, 0x40, 0x38, 0x40, 0x3F }, /* W */
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, /* X */
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, /* Y */
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, /* Z */
+ { 0x00, 0x7F, 0x41, 0x41, 0x00 }, /* [ */
+ { 0x55, 0x2A, 0x55, 0x2A, 0x55 }, /* \ */
+ { 0x00, 0x41, 0x41, 0x7F, 0x00 }, /* ] */
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, /* ^ */
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, /* _ */
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, /* ' */
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, /* a */
+ { 0x7F, 0x48, 0x44, 0x44, 0x38 }, /* b */
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, /* c */
+ { 0x38, 0x44, 0x44, 0x48, 0x7F }, /* d */
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, /* e */
+ { 0x08, 0x7E, 0x09, 0x01, 0x02 }, /* f */
+ { 0x0C, 0x52, 0x52, 0x52, 0x3E }, /* g */
+ { 0x7F, 0x08, 0x04, 0x04, 0x78 }, /* h */
+ { 0x00, 0x44, 0x7D, 0x40, 0x00 }, /* i */
+ { 0x20, 0x40, 0x44, 0x3D, 0x00 }, /* j */
+ { 0x7F, 0x10, 0x28, 0x44, 0x00 }, /* k */
+ { 0x00, 0x41, 0x7F, 0x40, 0x00 }, /* l */
+ { 0x7C, 0x04, 0x18, 0x04, 0x78 }, /* m */
+ { 0x7C, 0x08, 0x04, 0x04, 0x78 }, /* n */
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, /* o */
+ { 0x7C, 0x14, 0x14, 0x14, 0x08 }, /* p */
+ { 0x08, 0x14, 0x14, 0x18, 0x7C }, /* q */
+ { 0x7C, 0x08, 0x04, 0x04, 0x08 }, /* r */
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, /* s */
+ { 0x04, 0x3F, 0x44, 0x40, 0x20 }, /* t */
+ { 0x3C, 0x40, 0x40, 0x20, 0x7C }, /* u */
+ { 0x1C, 0x20, 0x40, 0x20, 0x1C }, /* v */
+ { 0x3C, 0x40, 0x30, 0x40, 0x3C }, /* w */
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, /* x */
+ { 0x0C, 0x50, 0x50, 0x50, 0x3C }, /* y */
+ { 0x44, 0x64, 0x54, 0x4C, 0x44 }, /* z */
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, /* { */
+ { 0x00, 0x00, 0x7F, 0x00, 0x00 }, /* | */
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, /* } */
+};
+
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief LCD driver initialization.
+ * @pre The SPI interface must be initialized and the driver started.
+ *
+ * @param[in] spip pointer to the SPI interface
+ *
+ */
+void lcd3310Init(SPIDriver *spip) {
+
+ /* Reset LCD */
+ palClearPad(LCD3310_RES_PORT, LCD3310_RES_PIN);
+ chThdSleepMilliseconds(15);
+ palSetPad(LCD3310_RES_PORT, LCD3310_RES_PIN);
+ chThdSleepMilliseconds(15);
+
+ /* Send configuration commands to LCD */
+ lcd3310WriteByte(spip, 0x21, LCD3310_SEND_CMD); /* LCD extended commands */
+ lcd3310WriteByte(spip, 0xC8, LCD3310_SEND_CMD); /* Set LCD Vop (Contrast) */
+ lcd3310WriteByte(spip, 0x05, LCD3310_SEND_CMD); /* Set start line S6 to 1 TLS8204 */
+ lcd3310WriteByte(spip, 0x40, LCD3310_SEND_CMD); /* Set start line S[5:0] to 0x00 TLS8204 */
+ lcd3310WriteByte(spip, 0x12, LCD3310_SEND_CMD); /* LCD bias mode 1:68. */
+ lcd3310WriteByte(spip, 0x20, LCD3310_SEND_CMD); /* LCD standard Commands, horizontal addressing mode. */
+ lcd3310WriteByte(spip, 0x08, LCD3310_SEND_CMD); /* LCD blank */
+ lcd3310WriteByte(spip, 0x0C, LCD3310_SEND_CMD); /* LCD in normal mode. */
+
+ lcd3310Clear(spip); /* Clear LCD */
+}
+
+/**
+ * @brief Write byte to LCD driver.
+ * @pre The LCD driver must be initialized.
+ *
+ * @param[in] spip pointer to the SPI interface
+ * @param[in] data data to write
+ * @param[in] cd select between command or data
+ */
+void lcd3310WriteByte(SPIDriver *spip, uint8_t data, uint8_t cd) {
+
+ spiSelect(spip);
+
+ if(cd == LCD3310_SEND_DATA) {
+ palSetPad(LCD3310_DC_PORT, LCD3310_DC_PIN);
+ }
+ else {
+ palClearPad(LCD3310_DC_PORT, LCD3310_DC_PIN);
+ }
+
+ spiSend(spip, 1, &data); // change to normal spi send
+ spiUnselect(spip);
+}
+
+/**
+ * @brief Clear LCD
+ * @pre The LCD driver must be initialized.
+ *
+ * @param[in] spip pointer to the SPI interface
+ */
+void lcd3310Clear(SPIDriver *spip) { // ok
+
+ uint32_t i, j;
+
+ for (i = 0; i < LCD3310_Y_RES/LCD3310_FONT_Y_SIZE; i++) {
+ lcd3310SetPosXY(spip, 0, i);
+ for (j = 0; j < LCD3310_X_RES; j++)
+ lcd3310WriteByte(spip, 0x00, LCD3310_SEND_DATA);
+ }
+
+}
+
+/**
+ * @brief Set position
+ * @pre The LCD driver must be initialized.
+ *
+ * @param[in] spip pointer to the SPI interface
+ * @param[in] x column address in LCD DDRAM, 0 to 83
+ * @param[in] y page address in LCD DDRAM, 0 to 5
+ */
+void lcd3310SetPosXY(SPIDriver *spip, uint8_t x, uint8_t y) {
+
+ if (y > LCD3310_Y_RES/LCD3310_FONT_Y_SIZE) return;
+ if (x > LCD3310_X_RES) return;
+
+ lcd3310WriteByte(spip, 0x80 | x, LCD3310_SEND_CMD); /* Set x position */
+ lcd3310WriteByte(spip, 0x40 | y, LCD3310_SEND_CMD); /* Set y position */
+
+}
+
+/**
+ * @brief Write char
+ * @pre The LCD driver must be initialized.
+ *
+ * @param[in] spip pointer to the SPI interface
+ * @param[in] ch char
+ */
+void lcd3310WriteChar(SPIDriver *spip, uint8_t ch) {
+
+ uint8_t i;
+
+ for ( i = 0; i < LCD3310_FONT_X_SIZE; i++ ){
+ lcd3310WriteByte(spip, Fonts8x5[ch - 32][i], LCD3310_SEND_DATA);
+ }
+
+}
+
+/**
+ * @brief Set LCD contrast.
+ * @pre The LCD driver must be initialized.
+ *
+ * @param[in] spip pointer to the SPI interface
+ * @param[in] contrast LCD contrast value
+ */
+void lcd3310Contrast (SPIDriver *spip, uint8_t contrast) {
+
+ lcd3310WriteByte(spip, 0x21, LCD3310_SEND_CMD); /* LCD Extended Commands */
+ lcd3310WriteByte(spip, 0x80 | contrast, LCD3310_SEND_CMD); /* Set LCD Vop (Contrast) */
+ lcd3310WriteByte(spip, 0x20, LCD3310_SEND_CMD); /* LCD Standard Commands, horizontal addressing mode */
+}
+
+
+/**
+ * @brief Write text
+ * @pre The LCD driver must be initialized.
+ *
+ * @param[in] spip pointer to the SPI interface
+ * @param[in] strp pointer to text
+ */
+void lcd3310WriteText(SPIDriver *spip, const uint8_t * strp) {
+
+ while ( *strp ) {
+ lcd3310WriteChar(spip, *strp);
+ strp++;
+ }
+}
+
+/**
+ * @brief Rotate text
+ * @pre The LCD driver must be initialized.
+ *
+ * @param[in] spip pointer to the SPI interface
+ * @param[in] strp pointer to text
+ * @param[in] offset text offset
+ */
+void lcd3310RotateText(SPIDriver *spip, const uint8_t * strp, uint8_t offset) {
+
+ uint8_t i;
+ uint8_t n;
+ uint8_t m;
+
+ for(n = 0; strp[n] != '\0'; n++); /* Count number of char */
+
+ if (offset >= n)
+ return;
+
+ for (i = 0; i < LCD3310_X_RES/LCD3310_FONT_X_SIZE; i++) {
+ m = i + offset;
+ if ( m < n)
+ lcd3310WriteChar(spip, strp[m]);
+ else
+ lcd3310WriteChar(spip, strp[m - n]);
+ }
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/lcd/lcd3310.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/lcd/lcd3310.h
new file mode 100644
index 0000000000..00dbadb47e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/devices_lib/lcd/lcd3310.h
@@ -0,0 +1,94 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file lcd3310.h
+ * @brief Nokia 3310 LCD interface module through SPI code.
+ *
+ * @addtogroup lcd3310
+ * @{
+ */
+
+#ifndef LCD3310_H
+#define LCD3310_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define LCD3310_X_RES 84
+#define LCD3310_Y_RES 48
+
+#define LCD3310_FONT_X_SIZE 5
+#define LCD3310_FONT_Y_SIZE 8
+
+#define LCD3310_SEND_CMD 0
+#define LCD3310_SEND_DATA 1
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(LCD3310_RES_PIN)
+#error "LCD3310_RES_PIN not defined!!!"
+#endif
+
+#if !defined(LCD3310_RES_PORT)
+#error "LCD3310_RES_PORT not defined!!!"
+#endif
+
+#if !defined(LCD3310_DC_PIN)
+#error "LCD3310_DC_PIN not defined!!!"
+#endif
+
+#if!defined(LCD3310_DC_PORT)
+#error "LCD3310_DC_PORT not defined!!!"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void lcd3310Init(SPIDriver *spip);
+ void lcd3310WriteByte(SPIDriver *spip, uint8_t data, uint8_t cd);
+ void lcd3310Contrast(SPIDriver *spip, uint8_t contrast);
+ void lcd3310Clear(SPIDriver *spip);
+ void lcd3310SetPosXY(SPIDriver *spip, uint8_t x, uint8_t y);
+ void lcd3310WriteChar (SPIDriver *spip, uint8_t ch);
+ void lcd3310WriteText(SPIDriver *spip, const uint8_t * strp);
+ void lcd3310RotateText(SPIDriver *spip, const uint8_t * strp, uint8_t offset);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LCD3310_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/evtimer.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/evtimer.c
index 9686229887..b32335f0ad 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/evtimer.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/evtimer.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,40 +25,61 @@
#include "ch.h"
#include "evtimer.h"
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
static void tmrcb(void *p) {
- EvTimer *etp = p;
+ event_timer_t *etp = p;
- chSysLockFromIsr();
+ chSysLockFromISR();
chEvtBroadcastI(&etp->et_es);
- chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp);
- chSysUnlockFromIsr();
+ chVTDoSetI(&etp->et_vt, etp->et_interval, tmrcb, etp);
+ chSysUnlockFromISR();
}
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
/**
- * @brief Starts the timer
- * @details If the timer was already running then the function has no effect.
+ * @brief Initializes an @p event_timer_t structure.
*
- * @param etp pointer to an initialized @p EvTimer structure.
+ * @param[out] etp the @p event_timer_t structure to be initialized
+ * @param[in] time the interval in system ticks
*/
-void evtStart(EvTimer *etp) {
-
- chSysLock();
+void evtObjectInit(event_timer_t *etp, systime_t time) {
- if (!chVTIsArmedI(&etp->et_vt))
- chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp);
-
- chSysUnlock();
+ chEvtObjectInit(&etp->et_es);
+ chVTObjectInit(&etp->et_vt);
+ etp->et_interval = time;
}
/**
- * @brief Stops the timer.
- * @details If the timer was already stopped then the function has no effect.
+ * @brief Starts the timer
+ * @details If the timer was already running then the function has no effect.
*
- * @param etp pointer to an initialized @p EvTimer structure.
+ * @param[in] etp pointer to an initialized @p event_timer_t structure.
*/
-void evtStop(EvTimer *etp) {
+void evtStart(event_timer_t *etp) {
- chVTReset(&etp->et_vt);
+ chVTSet(&etp->et_vt, etp->et_interval, tmrcb, etp);
}
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/evtimer.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/evtimer.h
index cd16898401..6bef2a48d2 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/evtimer.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/evtimer.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,47 +22,73 @@
* @{
*/
-#ifndef _EVTIMER_H_
-#define _EVTIMER_H_
+#ifndef EVTIMER_H
+#define EVTIMER_H
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
/*
* Module dependencies check.
*/
-#if !CH_USE_EVENTS
-#error "Event Timers require CH_USE_EVENTS"
+#if !CH_CFG_USE_EVENTS
+#error "Event Timers require CH_CFG_USE_EVENTS"
#endif
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
/**
- * @brief Event timer structure.
+ * @brief Type of a event timer structure.
*/
typedef struct {
- VirtualTimer et_vt;
- EventSource et_es;
- systime_t et_interval;
-} EvTimer;
+ virtual_timer_t et_vt;
+ event_source_t et_es;
+ systime_t et_interval;
+} event_timer_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
- void evtStart(EvTimer *etp);
- void evtStop(EvTimer *etp);
+ void evtObjectInit(event_timer_t *etp, systime_t time);
+ void evtStart(event_timer_t *etp);
#ifdef __cplusplus
}
#endif
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
/**
- * @brief Initializes an @p EvTimer structure.
+ * @brief Stops the timer.
+ * @details If the timer was already stopped then the function has no effect.
*
- * @param etp the EvTimer structure to be initialized
- * @param time the interval in system ticks
+ * @param[in] etp pointer to an initialized @p event_timer_t structure.
*/
-#define evtInit(etp, time) { \
- chEvtInit(&(etp)->et_es); \
- (etp)->et_vt.vt_func = NULL; \
- (etp)->et_interval = (time); \
+static inline void vevtStop(event_timer_t *etp) {
+
+ chVTReset(&etp->et_vt);
}
-#endif /* _EVTIMER_H_ */
+#endif /* EVTIMER_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs.mk
index b703dd2689..e406bae851 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs.mk
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs.mk
@@ -1,7 +1,7 @@
# FATFS files.
-FATFSSRC = ${CHIBIOS}/os/various/fatfs_bindings/fatfs_diskio.c \
- ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \
- ${CHIBIOS}/ext/fatfs/src/ff.c \
- ${CHIBIOS}/ext/fatfs/src/option/ccsbcs.c
+FATFSSRC = $(CHIBIOS)/os/various/fatfs_bindings/fatfs_diskio.c \
+ $(CHIBIOS)/os/various/fatfs_bindings/fatfs_syscall.c \
+ $(CHIBIOS)/ext/fatfs/src/ff.c \
+ $(CHIBIOS)/ext/fatfs/src/ffunicode.c
-FATFSINC = ${CHIBIOS}/ext/fatfs/src
+FATFSINC = $(CHIBIOS)/ext/fatfs/src
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs_diskio.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs_diskio.c
index 80727dc9fa..7fe5d155f3 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs_diskio.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs_diskio.c
@@ -5,7 +5,6 @@
/* disk I/O modules and attach it to FatFs module with common interface. */
/*-----------------------------------------------------------------------*/
-#include "ch.h"
#include "hal.h"
#include "ffconf.h"
#include "diskio.h"
@@ -23,7 +22,6 @@ extern SDCDriver SDCD1;
#endif
#if HAL_USE_RTC
-#include "chrtclib.h"
extern RTCDriver RTCD1;
#endif
@@ -39,12 +37,12 @@ extern RTCDriver RTCD1;
/* Inidialize a Drive */
DSTATUS disk_initialize (
- BYTE drv /* Physical drive nmuber (0..) */
+ BYTE pdrv /* Physical drive number (0..) */
)
{
DSTATUS stat;
- switch (drv) {
+ switch (pdrv) {
#if HAL_USE_MMC_SPI
case MMC:
stat = 0;
@@ -65,7 +63,7 @@ DSTATUS disk_initialize (
return stat;
#endif
}
- return STA_NODISK;
+ return STA_NOINIT;
}
@@ -74,12 +72,12 @@ DSTATUS disk_initialize (
/* Return Disk Status */
DSTATUS disk_status (
- BYTE drv /* Physical drive nmuber (0..) */
+ BYTE pdrv /* Physical drive number (0..) */
)
{
DSTATUS stat;
- switch (drv) {
+ switch (pdrv) {
#if HAL_USE_MMC_SPI
case MMC:
stat = 0;
@@ -100,7 +98,7 @@ DSTATUS disk_status (
return stat;
#endif
}
- return STA_NODISK;
+ return STA_NOINIT;
}
@@ -109,13 +107,13 @@ DSTATUS disk_status (
/* Read Sector(s) */
DRESULT disk_read (
- BYTE drv, /* Physical drive nmuber (0..) */
- BYTE *buff, /* Data buffer to store read data */
- DWORD sector, /* Sector address (LBA) */
- BYTE count /* Number of sectors to read (1..255) */
+ BYTE pdrv, /* Physical drive number (0..) */
+ BYTE *buff, /* Data buffer to store read data */
+ DWORD sector, /* Sector address (LBA) */
+ UINT count /* Number of sectors to read (1..255) */
)
{
- switch (drv) {
+ switch (pdrv) {
#if HAL_USE_MMC_SPI
case MMC:
if (blkGetDriverState(&MMCD1) != BLK_READY)
@@ -148,15 +146,15 @@ DRESULT disk_read (
/*-----------------------------------------------------------------------*/
/* Write Sector(s) */
-#if _READONLY == 0
+#if !FF_FS_READONLY
DRESULT disk_write (
- BYTE drv, /* Physical drive nmuber (0..) */
- const BYTE *buff, /* Data to be written */
- DWORD sector, /* Sector address (LBA) */
- BYTE count /* Number of sectors to write (1..255) */
+ BYTE pdrv, /* Physical drive number (0..) */
+ const BYTE *buff, /* Data to be written */
+ DWORD sector, /* Sector address (LBA) */
+ UINT count /* Number of sectors to write (1..255) */
)
{
- switch (drv) {
+ switch (pdrv) {
#if HAL_USE_MMC_SPI
case MMC:
if (blkGetDriverState(&MMCD1) != BLK_READY)
@@ -185,7 +183,7 @@ DRESULT disk_write (
}
return RES_PARERR;
}
-#endif /* _READONLY */
+#endif /* _FS_READONLY */
@@ -193,22 +191,26 @@ DRESULT disk_write (
/* Miscellaneous Functions */
DRESULT disk_ioctl (
- BYTE drv, /* Physical drive nmuber (0..) */
- BYTE ctrl, /* Control code */
+ BYTE pdrv, /* Physical drive number (0..) */
+ BYTE cmd, /* Control code */
void *buff /* Buffer to send/receive control data */
)
{
- switch (drv) {
+ (void)buff;
+
+ switch (pdrv) {
#if HAL_USE_MMC_SPI
case MMC:
- switch (ctrl) {
+ switch (cmd) {
case CTRL_SYNC:
return RES_OK;
+#if FF_MAX_SS > FF_MIN_SS
case GET_SECTOR_SIZE:
*((WORD *)buff) = MMCSD_BLOCK_SIZE;
return RES_OK;
-#if _USE_ERASE
- case CTRL_ERASE_SECTOR:
+#endif
+#if FF_USE_TRIM
+ case CTRL_TRIM:
mmcErase(&MMCD1, *((DWORD *)buff), *((DWORD *)buff + 1));
return RES_OK;
#endif
@@ -217,20 +219,22 @@ DRESULT disk_ioctl (
}
#else
case SDC:
- switch (ctrl) {
+ switch (cmd) {
case CTRL_SYNC:
return RES_OK;
case GET_SECTOR_COUNT:
*((DWORD *)buff) = mmcsdGetCardCapacity(&SDCD1);
return RES_OK;
+#if FF_MAX_SS > FF_MIN_SS
case GET_SECTOR_SIZE:
*((WORD *)buff) = MMCSD_BLOCK_SIZE;
return RES_OK;
+#endif
case GET_BLOCK_SIZE:
*((DWORD *)buff) = 256; /* 512b blocks in one erase block */
return RES_OK;
-#if _USE_ERASE
- case CTRL_ERASE_SECTOR:
+#if FF_USE_TRIM
+ case CTRL_TRIM:
sdcErase(&SDCD1, *((DWORD *)buff), *((DWORD *)buff + 1));
return RES_OK;
#endif
@@ -244,11 +248,11 @@ DRESULT disk_ioctl (
DWORD get_fattime(void) {
#if HAL_USE_RTC
- return rtcGetTimeFat(&RTCD1);
+ RTCDateTime timespec;
+
+ rtcGetTime(&RTCD1, ×pec);
+ return rtcConvertDateTimeToFAT(×pec);
#else
return ((uint32_t)0 | (1 << 16)) | (1 << 21); /* wrong but valid time */
#endif
}
-
-
-
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs_syscall.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs_syscall.c
index c4e35bf0ae..43ff9d9fb8 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs_syscall.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/fatfs_syscall.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,33 +15,33 @@
*/
/*------------------------------------------------------------------------*/
-/* Sample code of OS dependent controls for FatFs R0.08b */
-/* (C)ChaN, 2011 */
+/* Sample code of OS dependent controls for FatFs */
+/* (C)ChaN, 2014 */
/*------------------------------------------------------------------------*/
-#include "ch.h"
+#include "hal.h"
#include "ff.h"
-#if _FS_REENTRANT
+#if FF_FS_REENTRANT
/*------------------------------------------------------------------------*/
/* Static array of Synchronization Objects */
/*------------------------------------------------------------------------*/
-static Semaphore ff_sem[_VOLUMES];
+static semaphore_t ff_sem[FF_VOLUMES];
/*------------------------------------------------------------------------*/
/* Create a Synchronization Object */
/*------------------------------------------------------------------------*/
-int ff_cre_syncobj(BYTE vol, _SYNC_t *sobj) {
+int ff_cre_syncobj(BYTE vol, FF_SYNC_t *sobj) {
*sobj = &ff_sem[vol];
- chSemInit(*sobj, 1);
+ chSemObjectInit(*sobj, 1);
return TRUE;
}
/*------------------------------------------------------------------------*/
/* Delete a Synchronization Object */
/*------------------------------------------------------------------------*/
-int ff_del_syncobj(_SYNC_t sobj) {
+int ff_del_syncobj(FF_SYNC_t sobj) {
chSemReset(sobj, 0);
return TRUE;
@@ -50,22 +50,22 @@ int ff_del_syncobj(_SYNC_t sobj) {
/*------------------------------------------------------------------------*/
/* Request Grant to Access the Volume */
/*------------------------------------------------------------------------*/
-int ff_req_grant(_SYNC_t sobj) {
+int ff_req_grant(FF_SYNC_t sobj) {
- msg_t msg = chSemWaitTimeout(sobj, (systime_t)_FS_TIMEOUT);
- return msg == RDY_OK;
+ msg_t msg = chSemWaitTimeout(sobj, (systime_t)FF_FS_TIMEOUT);
+ return msg == MSG_OK;
}
/*------------------------------------------------------------------------*/
/* Release Grant to Access the Volume */
/*------------------------------------------------------------------------*/
-void ff_rel_grant(_SYNC_t sobj) {
+void ff_rel_grant(FF_SYNC_t sobj) {
chSemSignal(sobj);
}
#endif /* _FS_REENTRANT */
-#if _USE_LFN == 3 /* LFN with a working buffer on the heap */
+#if FF_USE_LFN == 3 /* LFN with a working buffer on the heap */
/*------------------------------------------------------------------------*/
/* Allocate a memory block */
/*------------------------------------------------------------------------*/
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/readme.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/readme.txt
index ef546e5aee..7f57b8acec 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/readme.txt
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/fatfs_bindings/readme.txt
@@ -1,6 +1,12 @@
This directory contains the ChibiOS/RT "official" bindings with the FatFS
library by ChaN: http://elm-chan.org
-In order to use FatFS within ChibiOS/RT project, unzip FatFS under
-./ext/fatfs then include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk
-in your makefile.
+In order to use FatFS within ChibiOS/RT project:
+1. unzip FatFS under ./ext/fatfs [See Note 2]
+2. include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk in your makefile.
+3. Add $(FATFSSRC) to $(CSRC)
+4. Add $(FATFSINC) to $(INCDIR)
+
+Note:
+1. These files modified for use with version 0.13 of fatfs.
+2. In the original distribution, the source directory is called 'source' rather than 'src'
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/cc.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/cc.h
index 8f85833187..cad7e9c4bd 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/cc.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/cc.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -51,7 +51,7 @@
#ifndef __CC_H__
#define __CC_H__
-#include
+#include
typedef uint8_t u8_t;
typedef int8_t s8_t;
@@ -61,12 +61,17 @@ typedef uint32_t u32_t;
typedef int32_t s32_t;
typedef uint32_t mem_ptr_t;
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+
#define LWIP_PLATFORM_DIAG(x)
#define LWIP_PLATFORM_ASSERT(x) { \
- chSysHalt(); \
+ osalSysHalt(x); \
}
+#ifndef BYTE_ORDER
#define BYTE_ORDER LITTLE_ENDIAN
+#endif
+
#define LWIP_PROVIDE_ERRNO
#endif /* __CC_H__ */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/perf.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/perf.h
index 541f51e163..7dad009c2a 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/perf.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/perf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/sys_arch.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/sys_arch.c
index 56336020ea..5f99550e45 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/sys_arch.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/sys_arch.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -50,7 +50,7 @@
// see http://lwip.wikia.com/wiki/Porting_for_an_OS for instructions
-#include "ch.h"
+#include "hal.h"
#include "lwip/opt.h"
#include "lwip/mem.h"
@@ -66,13 +66,13 @@ void sys_init(void) {
err_t sys_sem_new(sys_sem_t *sem, u8_t count) {
- *sem = chHeapAlloc(NULL, sizeof(Semaphore));
+ *sem = chHeapAlloc(NULL, sizeof(semaphore_t));
if (*sem == 0) {
SYS_STATS_INC(sem.err);
return ERR_MEM;
}
else {
- chSemInit(*sem, (cnt_t)count);
+ chSemObjectInit(*sem, (cnt_t)count);
SYS_STATS_INC_USED(sem);
return ERR_OK;
}
@@ -99,17 +99,18 @@ void sys_sem_signal_S(sys_sem_t *sem) {
}
u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) {
- systime_t time, tmo;
-
- chSysLock();
- tmo = timeout > 0 ? (systime_t)timeout : TIME_INFINITE;
- time = chTimeNow();
- if (chSemWaitTimeoutS(*sem, tmo) != RDY_OK)
- time = SYS_ARCH_TIMEOUT;
- else
- time = chTimeNow() - time;
- chSysUnlock();
- return time;
+ systime_t tmo, start, remaining;
+
+ osalSysLock();
+ tmo = timeout > 0 ? MS2ST((systime_t)timeout) : TIME_INFINITE;
+ start = osalOsGetSystemTimeX();
+ if (chSemWaitTimeoutS(*sem, tmo) != MSG_OK) {
+ osalSysUnlock();
+ return SYS_ARCH_TIMEOUT;
+ }
+ remaining = osalOsGetSystemTimeX() - start;
+ osalSysUnlock();
+ return (u32_t)ST2MS(remaining);
}
int sys_sem_valid(sys_sem_t *sem) {
@@ -124,21 +125,26 @@ void sys_sem_set_invalid(sys_sem_t *sem) {
err_t sys_mbox_new(sys_mbox_t *mbox, int size) {
- *mbox = chHeapAlloc(NULL, sizeof(Mailbox) + sizeof(msg_t) * size);
+ *mbox = chHeapAlloc(NULL, sizeof(mailbox_t) + sizeof(msg_t) * size);
if (*mbox == 0) {
SYS_STATS_INC(mbox.err);
return ERR_MEM;
}
else {
- chMBInit(*mbox, (void *)(((uint8_t *)*mbox) + sizeof(Mailbox)), size);
+ chMBObjectInit(*mbox, (void *)(((uint8_t *)*mbox) + sizeof(mailbox_t)), size);
SYS_STATS_INC(mbox.used);
return ERR_OK;
}
}
void sys_mbox_free(sys_mbox_t *mbox) {
+ cnt_t tmpcnt;
- if (chMBGetUsedCountI(*mbox) != 0) {
+ osalSysLock();
+ tmpcnt = chMBGetUsedCountI(*mbox);
+ osalSysUnlock();
+
+ if (tmpcnt != 0) {
// If there are messages still present in the mailbox when the mailbox
// is deallocated, it is an indication of a programming error in lwIP
// and the developer should be notified.
@@ -157,7 +163,7 @@ void sys_mbox_post(sys_mbox_t *mbox, void *msg) {
err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) {
- if (chMBPost(*mbox, (msg_t)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) {
+ if (chMBPost(*mbox, (msg_t)msg, TIME_IMMEDIATE) == MSG_TIMEOUT) {
SYS_STATS_INC(mbox.err);
return ERR_MEM;
}
@@ -165,22 +171,23 @@ err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) {
}
u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) {
- systime_t time, tmo;
-
- chSysLock();
- tmo = timeout > 0 ? (systime_t)timeout : TIME_INFINITE;
- time = chTimeNow();
- if (chMBFetchS(*mbox, (msg_t *)msg, tmo) != RDY_OK)
- time = SYS_ARCH_TIMEOUT;
- else
- time = chTimeNow() - time;
- chSysUnlock();
- return time;
+ systime_t tmo, start, remaining;
+
+ osalSysLock();
+ tmo = timeout > 0 ? MS2ST((systime_t)timeout) : TIME_INFINITE;
+ start = osalOsGetSystemTimeX();
+ if (chMBFetchS(*mbox, (msg_t *)msg, tmo) != MSG_OK) {
+ osalSysUnlock();
+ return SYS_ARCH_TIMEOUT;
+ }
+ remaining = osalOsGetSystemTimeX() - start;
+ osalSysUnlock();
+ return (u32_t)ST2MS(remaining);
}
u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) {
- if (chMBFetch(*mbox, (msg_t *)msg, TIME_IMMEDIATE) == RDY_TIMEOUT)
+ if (chMBFetch(*mbox, (msg_t *)msg, TIME_IMMEDIATE) == MSG_TIMEOUT)
return SYS_MBOX_EMPTY;
return 0;
}
@@ -197,39 +204,32 @@ void sys_mbox_set_invalid(sys_mbox_t *mbox) {
sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread,
void *arg, int stacksize, int prio) {
+ thread_t *tp;
- size_t wsz;
- void *wsp;
-
- (void)name;
- wsz = THD_WA_SIZE(stacksize);
- wsp = chCoreAlloc(wsz);
- if (wsp == NULL)
- return NULL;
- return (sys_thread_t)chThdCreateStatic(wsp, wsz, prio, (tfunc_t)thread, arg);
+ tp = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(stacksize),
+ name, prio, (tfunc_t)thread, arg);
+ return (sys_thread_t)tp;
}
sys_prot_t sys_arch_protect(void) {
- chSysLock();
- return 0;
+ return chSysGetStatusAndLockX();
}
void sys_arch_unprotect(sys_prot_t pval) {
- (void)pval;
- chSysUnlock();
+ osalSysRestoreStatusX((syssts_t)pval);
}
u32_t sys_now(void) {
-#if CH_FREQUENCY == 1000
- return (u32_t)chTimeNow();
-#elif (CH_FREQUENCY / 1000) >= 1 && (CH_FREQUENCY % 1000) == 0
- return ((u32_t)chTimeNow() - 1) / (CH_FREQUENCY / 1000) + 1;
-#elif (1000 / CH_FREQUENCY) >= 1 && (1000 % CH_FREQUENCY) == 0
- return ((u32_t)chTimeNow() - 1) * (1000 / CH_FREQUENCY) + 1;
+#if OSAL_ST_FREQUENCY == 1000
+ return (u32_t)osalOsGetSystemTimeX();
+#elif (OSAL_ST_FREQUENCY / 1000) >= 1 && (OSAL_ST_FREQUENCY % 1000) == 0
+ return ((u32_t)osalOsGetSystemTimeX() - 1) / (OSAL_ST_FREQUENCY / 1000) + 1;
+#elif (1000 / OSAL_ST_FREQUENCY) >= 1 && (1000 % OSAL_ST_FREQUENCY) == 0
+ return ((u32_t)osalOsGetSystemTimeX() - 1) * (1000 / OSAL_ST_FREQUENCY) + 1;
#else
- return (u32_t)(((u64_t)(chTimeNow() - 1) * 1000) / CH_FREQUENCY) + 1;
+ return (u32_t)(((u64_t)(osalOsGetSystemTimeX() - 1) * 1000) / OSAL_ST_FREQUENCY) + 1;
#endif
}
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/sys_arch.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/sys_arch.h
index 97ca10f93e..edcaf58284 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/sys_arch.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/arch/sys_arch.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -48,19 +48,19 @@
*
*/
-#include
+#include
#ifndef __SYS_ARCH_H__
#define __SYS_ARCH_H__
-typedef Semaphore * sys_sem_t;
-typedef Mailbox * sys_mbox_t;
-typedef Thread * sys_thread_t;
-typedef int sys_prot_t;
+typedef semaphore_t * sys_sem_t;
+typedef mailbox_t * sys_mbox_t;
+typedef thread_t * sys_thread_t;
+typedef syssts_t sys_prot_t;
-#define SYS_MBOX_NULL (Mailbox *)0
-#define SYS_THREAD_NULL (Thread *)0
-#define SYS_SEM_NULL (Semaphore *)0
+#define SYS_MBOX_NULL (mailbox_t *)0
+#define SYS_THREAD_NULL (thread_t *)0
+#define SYS_SEM_NULL (semaphore_t *)0
/* let sys.h use binary semaphores for mutexes */
#define LWIP_COMPAT_MUTEX 1
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwip.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwip.mk
index d6ea6716ad..b9b799d3b8 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwip.mk
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwip.mk
@@ -1,54 +1,54 @@
# List of the required lwIP files.
-LWIP = ${CHIBIOS}/ext/lwip
+LWIP = $(CHIBIOS)/ext/lwip
LWBINDSRC = \
$(CHIBIOS)/os/various/lwip_bindings/lwipthread.c \
$(CHIBIOS)/os/various/lwip_bindings/arch/sys_arch.c
LWNETIFSRC = \
- ${LWIP}/src/netif/etharp.c
+ $(LWIP)/src/netif/etharp.c
LWCORESRC = \
- ${LWIP}/src/core/dhcp.c \
- ${LWIP}/src/core/dns.c \
- ${LWIP}/src/core/init.c \
- ${LWIP}/src/core/mem.c \
- ${LWIP}/src/core/memp.c \
- ${LWIP}/src/core/netif.c \
- ${LWIP}/src/core/pbuf.c \
- ${LWIP}/src/core/raw.c \
- ${LWIP}/src/core/stats.c \
- ${LWIP}/src/core/sys.c \
- ${LWIP}/src/core/tcp.c \
- ${LWIP}/src/core/tcp_in.c \
- ${LWIP}/src/core/tcp_out.c \
- ${LWIP}/src/core/udp.c
+ $(LWIP)/src/core/dhcp.c \
+ $(LWIP)/src/core/dns.c \
+ $(LWIP)/src/core/init.c \
+ $(LWIP)/src/core/mem.c \
+ $(LWIP)/src/core/memp.c \
+ $(LWIP)/src/core/netif.c \
+ $(LWIP)/src/core/pbuf.c \
+ $(LWIP)/src/core/raw.c \
+ $(LWIP)/src/core/stats.c \
+ $(LWIP)/src/core/sys.c \
+ $(LWIP)/src/core/tcp.c \
+ $(LWIP)/src/core/tcp_in.c \
+ $(LWIP)/src/core/tcp_out.c \
+ $(LWIP)/src/core/udp.c
LWIPV4SRC = \
- ${LWIP}/src/core/ipv4/autoip.c \
- ${LWIP}/src/core/ipv4/icmp.c \
- ${LWIP}/src/core/ipv4/igmp.c \
- ${LWIP}/src/core/ipv4/inet.c \
- ${LWIP}/src/core/ipv4/inet_chksum.c \
- ${LWIP}/src/core/ipv4/ip.c \
- ${LWIP}/src/core/ipv4/ip_addr.c \
- ${LWIP}/src/core/ipv4/ip_frag.c \
- ${LWIP}/src/core/def.c \
- ${LWIP}/src/core/timers.c
+ $(LWIP)/src/core/ipv4/autoip.c \
+ $(LWIP)/src/core/ipv4/icmp.c \
+ $(LWIP)/src/core/ipv4/igmp.c \
+ $(LWIP)/src/core/ipv4/inet.c \
+ $(LWIP)/src/core/ipv4/inet_chksum.c \
+ $(LWIP)/src/core/ipv4/ip.c \
+ $(LWIP)/src/core/ipv4/ip_addr.c \
+ $(LWIP)/src/core/ipv4/ip_frag.c \
+ $(LWIP)/src/core/def.c \
+ $(LWIP)/src/core/timers.c
LWAPISRC = \
- ${LWIP}/src/api/api_lib.c \
- ${LWIP}/src/api/api_msg.c \
- ${LWIP}/src/api/err.c \
- ${LWIP}/src/api/netbuf.c \
- ${LWIP}/src/api/netdb.c \
- ${LWIP}/src/api/netifapi.c \
- ${LWIP}/src/api/sockets.c \
- ${LWIP}/src/api/tcpip.c
+ $(LWIP)/src/api/api_lib.c \
+ $(LWIP)/src/api/api_msg.c \
+ $(LWIP)/src/api/err.c \
+ $(LWIP)/src/api/netbuf.c \
+ $(LWIP)/src/api/netdb.c \
+ $(LWIP)/src/api/netifapi.c \
+ $(LWIP)/src/api/sockets.c \
+ $(LWIP)/src/api/tcpip.c
LWSRC = $(LWBINDSRC) $(LWNETIFSRC) $(LWCORESRC) $(LWIPV4SRC) $(LWAPISRC)
LWINC = \
$(CHIBIOS)/os/various/lwip_bindings \
- ${LWIP}/src/include \
- ${LWIP}/src/include/ipv4
+ $(LWIP)/src/include \
+ $(LWIP)/src/include/ipv4
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwipthread.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwipthread.c
index f70d44a9f7..72023595c5 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwipthread.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwipthread.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -55,7 +55,6 @@
* @{
*/
-#include "ch.h"
#include "hal.h"
#include "evtimer.h"
@@ -73,13 +72,22 @@
#include "netif/etharp.h"
#include "netif/ppp_oe.h"
+#if LWIP_DHCP
+#include
+#endif
+
#define PERIODIC_TIMER_ID 1
#define FRAME_RECEIVED_ID 2
-/**
+/*
+ * Suspension point for initialization procedure.
+ */
+thread_reference_t lwip_trp = NULL;
+
+/*
* Stack area for the LWIP-MAC thread.
*/
-WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE);
+static THD_WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE);
/*
* Initialization.
@@ -106,7 +114,7 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p) {
MACTransmitDescriptor td;
(void)netif;
- if (macWaitTransmitDescriptor(ÐD1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != RDY_OK)
+ if (macWaitTransmitDescriptor(ÐD1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != MSG_OK)
return ERR_TIMEOUT;
#if ETH_PAD_SIZE
@@ -136,7 +144,7 @@ static struct pbuf *low_level_input(struct netif *netif) {
u16_t len;
(void)netif;
- if (macWaitReceiveDescriptor(ÐD1, &rd, TIME_IMMEDIATE) == RDY_OK) {
+ if (macWaitReceiveDescriptor(ÐD1, &rd, TIME_IMMEDIATE) == MSG_OK) {
len = (u16_t)rd.size;
#if ETH_PAD_SIZE
@@ -211,9 +219,9 @@ static err_t ethernetif_init(struct netif *netif) {
* @param[in] p pointer to a @p lwipthread_opts structure or @p NULL
* @return The function does not return.
*/
-msg_t lwip_thread(void *p) {
- EvTimer evt;
- EventListener el0, el1;
+static THD_FUNCTION(lwip_thread, p) {
+ event_timer_t evt;
+ event_listener_t el0, el1;
struct ip_addr ip, gateway, netmask;
static struct netif thisif;
static const MACConfig mac_config = {thisif.hwaddr};
@@ -252,26 +260,35 @@ msg_t lwip_thread(void *p) {
netif_set_up(&thisif);
/* Setup event sources.*/
- evtInit(&evt, LWIP_LINK_POLL_INTERVAL);
+ evtObjectInit(&evt, LWIP_LINK_POLL_INTERVAL);
evtStart(&evt);
chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID);
chEvtRegisterMask(macGetReceiveEventSource(ÐD1), &el1, FRAME_RECEIVED_ID);
chEvtAddEvents(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID);
- /* Goes to the final priority after initialization.*/
+ /* Resumes the caller and goes to the final priority.*/
+ chThdResume(&lwip_trp, MSG_OK);
chThdSetPriority(LWIP_THREAD_PRIORITY);
- while (TRUE) {
+ while (true) {
eventmask_t mask = chEvtWaitAny(ALL_EVENTS);
if (mask & PERIODIC_TIMER_ID) {
- bool_t current_link_status = macPollLinkStatus(ÐD1);
+ bool current_link_status = macPollLinkStatus(ÐD1);
if (current_link_status != netif_is_link_up(&thisif)) {
- if (current_link_status)
+ if (current_link_status) {
tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up,
&thisif, 0);
- else
+#if LWIP_DHCP
+ dhcp_start(&thisif);
+#endif
+ }
+ else {
tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down,
&thisif, 0);
+#if LWIP_DHCP
+ dhcp_stop(&thisif);
+#endif
+ }
}
}
if (mask & FRAME_RECEIVED_ID) {
@@ -297,7 +314,27 @@ msg_t lwip_thread(void *p) {
}
}
}
- return 0;
+}
+
+/**
+ * @brief Initializes the lwIP subsystem.
+ * @note The function exits after the initialization is finished.
+ *
+ * @param[in] opts pointer to the configuration structure, if @p NULL
+ * then the static configuration is used.
+ */
+void lwipInit(const lwipthread_opts_t *opts) {
+
+ /* Creating the lwIP thread (it changes priority internally).*/
+ chThdCreateStatic(wa_lwip_thread, sizeof (wa_lwip_thread),
+ chThdGetPriorityX() - 1, lwip_thread, (void *)opts);
+
+ /* Waiting for the lwIP thread complete initialization. Note,
+ this thread reaches the thread reference object first because
+ the relative priorities.*/
+ chSysLock();
+ chThdSuspendS(&lwip_trp);
+ chSysUnlock();
}
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwipthread.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwipthread.h
index 91be445ce1..fd222f6f55 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwipthread.h
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/lwipthread.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -21,111 +21,141 @@
* @{
*/
-#ifndef _LWIPTHREAD_H_
-#define _LWIPTHREAD_H_
+#ifndef LWIPTHREAD_H
+#define LWIPTHREAD_H
#include
-/** @brief MAC thread priority.*/
+/**
+ * @brief lwIP thread priority.
+ */
#ifndef LWIP_THREAD_PRIORITY
#define LWIP_THREAD_PRIORITY LOWPRIO
#endif
-/** @brief MAC thread stack size. */
+/**
+ * @brief lwIP thread stack size.
+ */
#if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
-#define LWIP_THREAD_STACK_SIZE 512
+#define LWIP_THREAD_STACK_SIZE 576
#endif
-/** @brief Link poll interval. */
+/**
+ * @brief Link poll interval.
+ */
#if !defined(LWIP_LINK_POLL_INTERVAL) || defined(__DOXYGEN__)
#define LWIP_LINK_POLL_INTERVAL S2ST(5)
#endif
-/** @brief IP Address. */
+/**
+ * @brief IP Address.
+ */
#if !defined(LWIP_IPADDR) || defined(__DOXYGEN__)
-#define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 1, 20)
+#define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 1, 10)
#endif
-/** @brief IP Gateway. */
+/**
+ * @brief IP Gateway.
+ */
#if !defined(LWIP_GATEWAY) || defined(__DOXYGEN__)
#define LWIP_GATEWAY(p) IP4_ADDR(p, 192, 168, 1, 1)
#endif
-/** @brief IP netmask. */
+/**
+ * @brief IP netmask.
+ */
#if !defined(LWIP_NETMASK) || defined(__DOXYGEN__)
#define LWIP_NETMASK(p) IP4_ADDR(p, 255, 255, 255, 0)
#endif
-/** @brief Transmission timeout. */
+/**
+ * @brief Transmission timeout.
+ */
#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__)
#define LWIP_SEND_TIMEOUT 50
#endif
-/** @brief Link speed. */
+/**
+ * @brief Link speed.
+ */
#if !defined(LWIP_LINK_SPEED) || defined(__DOXYGEN__)
#define LWIP_LINK_SPEED 100000000
#endif
-/** @brief MAC Address byte 0. */
+/**
+ * @brief MAC Address byte 0.
+ */
#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__)
#define LWIP_ETHADDR_0 0xC2
#endif
-/** @brief MAC Address byte 1. */
+/**
+ * @brief MAC Address byte 1.
+ */
#if !defined(LWIP_ETHADDR_1) || defined(__DOXYGEN__)
#define LWIP_ETHADDR_1 0xAF
#endif
-/** @brief MAC Address byte 2. */
+/**
+ * @brief MAC Address byte 2.
+ */
#if !defined(LWIP_ETHADDR_2) || defined(__DOXYGEN__)
#define LWIP_ETHADDR_2 0x51
#endif
-/** @brief MAC Address byte 3. */
+/**
+ * @brief MAC Address byte 3.
+ */
#if !defined(LWIP_ETHADDR_3) || defined(__DOXYGEN__)
#define LWIP_ETHADDR_3 0x03
#endif
-/** @brief MAC Address byte 4. */
+/**
+ * @brief MAC Address byte 4.
+ */
#if !defined(LWIP_ETHADDR_4) || defined(__DOXYGEN__)
#define LWIP_ETHADDR_4 0xCF
#endif
-/** @brief MAC Address byte 5. */
+/**
+ * @brief MAC Address byte 5.
+ */
#if !defined(LWIP_ETHADDR_5) || defined(__DOXYGEN__)
#define LWIP_ETHADDR_5 0x46
#endif
-/** @brief Interface name byte 0. */
+/**
+ * @brief Interface name byte 0.
+ */
#if !defined(LWIP_IFNAME0) || defined(__DOXYGEN__)
#define LWIP_IFNAME0 'm'
#endif
-/** @brief Interface name byte 1. */
+/**
+ * @brief Interface name byte 1.
+ */
#if !defined(LWIP_IFNAME1) || defined(__DOXYGEN__)
#define LWIP_IFNAME1 's'
#endif
/**
- * @brief Runtime TCP/IP settings.
+ * @brief Runtime TCP/IP settings.
*/
-struct lwipthread_opts {
+typedef struct lwipthread_opts {
uint8_t *macaddress;
uint32_t address;
uint32_t netmask;
uint32_t gateway;
-};
-
-extern WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE);
+} lwipthread_opts_t;
#ifdef __cplusplus
extern "C" {
#endif
- msg_t lwip_thread(void *p);
+ void lwipInit(const lwipthread_opts_t *opts);
#ifdef __cplusplus
}
#endif
-#endif /* _LWIPTHREAD_H_ */
+#endif /* LWIPTHREAD_H */
/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/readme.txt b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/readme.txt
index 1b81b72b40..f2a88982a4 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/readme.txt
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/lwip_bindings/readme.txt
@@ -1,6 +1,6 @@
This directory contains the ChibiOS/RT "official" bindings with the lwIP
TCP/IP stack: http://savannah.nongnu.org/projects/lwip
-In order to use FatFS within ChibiOS/RT project, unzip FatFS under
+In order to use lwIP within ChibiOS/RT project, unzip lwIP under
./ext/lwip-1.4.0 then include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk
in your makefile.
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell.c
deleted file mode 100644
index 9717172eda..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file shell.c
- * @brief Simple CLI shell code.
- *
- * @addtogroup SHELL
- * @{
- */
-
-#include
-
-#include "ch.h"
-#include "hal.h"
-#include "shell.h"
-#include "chprintf.h"
-
-/**
- * @brief Shell termination event source.
- */
-EventSource shell_terminated;
-
-static char *_strtok(char *str, const char *delim, char **saveptr) {
- char *token;
- if (str)
- *saveptr = str;
- token = *saveptr;
-
- if (!token)
- return NULL;
-
- token += strspn(token, delim);
- *saveptr = strpbrk(token, delim);
- if (*saveptr)
- *(*saveptr)++ = '\0';
-
- return *token ? token : NULL;
-}
-
-static void usage(BaseSequentialStream *chp, char *p) {
-
- chprintf(chp, "Usage: %s\r\n", p);
-}
-
-static void list_commands(BaseSequentialStream *chp, const ShellCommand *scp) {
-
- while (scp->sc_name != NULL) {
- chprintf(chp, "%s ", scp->sc_name);
- scp++;
- }
-}
-
-static void cmd_info(BaseSequentialStream *chp, int argc, char *argv[]) {
-
- (void)argv;
- if (argc > 0) {
- usage(chp, "info");
- return;
- }
-
- chprintf(chp, "Kernel: %s\r\n", CH_KERNEL_VERSION);
-#ifdef CH_COMPILER_NAME
- chprintf(chp, "Compiler: %s\r\n", CH_COMPILER_NAME);
-#endif
- chprintf(chp, "Architecture: %s\r\n", CH_ARCHITECTURE_NAME);
-#ifdef CH_CORE_VARIANT_NAME
- chprintf(chp, "Core Variant: %s\r\n", CH_CORE_VARIANT_NAME);
-#endif
-#ifdef CH_PORT_INFO
- chprintf(chp, "Port Info: %s\r\n", CH_PORT_INFO);
-#endif
-#ifdef PLATFORM_NAME
- chprintf(chp, "Platform: %s\r\n", PLATFORM_NAME);
-#endif
-#ifdef BOARD_NAME
- chprintf(chp, "Board: %s\r\n", BOARD_NAME);
-#endif
-#ifdef __DATE__
-#ifdef __TIME__
- chprintf(chp, "Build time: %s%s%s\r\n", __DATE__, " - ", __TIME__);
-#endif
-#endif
-}
-
-static void cmd_systime(BaseSequentialStream *chp, int argc, char *argv[]) {
-
- (void)argv;
- if (argc > 0) {
- usage(chp, "systime");
- return;
- }
- chprintf(chp, "%lu\r\n", (unsigned long)chTimeNow());
-}
-
-/**
- * @brief Array of the default commands.
- */
-static ShellCommand local_commands[] = {
- {"info", cmd_info},
- {"systime", cmd_systime},
- {NULL, NULL}
-};
-
-static bool_t cmdexec(const ShellCommand *scp, BaseSequentialStream *chp,
- char *name, int argc, char *argv[]) {
-
- while (scp->sc_name != NULL) {
- if (strcasecmp(scp->sc_name, name) == 0) {
- scp->sc_function(chp, argc, argv);
- return FALSE;
- }
- scp++;
- }
- return TRUE;
-}
-
-/**
- * @brief Shell thread function.
- *
- * @param[in] p pointer to a @p BaseSequentialStream object
- * @return Termination reason.
- * @retval RDY_OK terminated by command.
- * @retval RDY_RESET terminated by reset condition on the I/O channel.
- *
- * @notapi
- */
-static msg_t shell_thread(void *p) {
- int n;
- BaseSequentialStream *chp = ((ShellConfig *)p)->sc_channel;
- const ShellCommand *scp = ((ShellConfig *)p)->sc_commands;
- char *lp, *cmd, *tokp, line[SHELL_MAX_LINE_LENGTH];
- char *args[SHELL_MAX_ARGUMENTS + 1];
-
- chRegSetThreadName("shell");
- chprintf(chp, "\r\nChibiOS/RT Shell\r\n");
- while (TRUE) {
- chprintf(chp, "ch> ");
- if (shellGetLine(chp, line, sizeof(line))) {
- chprintf(chp, "\r\nlogout");
- break;
- }
- lp = _strtok(line, " \t", &tokp);
- cmd = lp;
- n = 0;
- while ((lp = _strtok(NULL, " \t", &tokp)) != NULL) {
- if (n >= SHELL_MAX_ARGUMENTS) {
- chprintf(chp, "too many arguments\r\n");
- cmd = NULL;
- break;
- }
- args[n++] = lp;
- }
- args[n] = NULL;
- if (cmd != NULL) {
- if (strcasecmp(cmd, "exit") == 0) {
- if (n > 0) {
- usage(chp, "exit");
- continue;
- }
- break;
- }
- else if (strcasecmp(cmd, "help") == 0) {
- if (n > 0) {
- usage(chp, "help");
- continue;
- }
- chprintf(chp, "Commands: help exit ");
- list_commands(chp, local_commands);
- if (scp != NULL)
- list_commands(chp, scp);
- chprintf(chp, "\r\n");
- }
- else if (cmdexec(local_commands, chp, cmd, n, args) &&
- ((scp == NULL) || cmdexec(scp, chp, cmd, n, args))) {
- chprintf(chp, "%s", cmd);
- chprintf(chp, " ?\r\n");
- }
- }
- }
- shellExit(RDY_OK);
- /* Never executed, silencing a warning.*/
- return 0;
-}
-
-/**
- * @brief Shell manager initialization.
- *
- * @api
- */
-void shellInit(void) {
-
- chEvtInit(&shell_terminated);
-}
-
-/**
- * @brief Terminates the shell.
- * @note Must be invoked from the command handlers.
- * @note Does not return.
- *
- * @param[in] msg shell exit code
- *
- * @api
- */
-void shellExit(msg_t msg) {
-
- /* Atomically broadcasting the event source and terminating the thread,
- there is not a chSysUnlock() because the thread terminates upon return.*/
- chSysLock();
- chEvtBroadcastI(&shell_terminated);
- chThdExitS(msg);
-}
-
-/**
- * @brief Spawns a new shell.
- * @pre @p CH_USE_HEAP and @p CH_USE_DYNAMIC must be enabled.
- *
- * @param[in] scp pointer to a @p ShellConfig object
- * @param[in] size size of the shell working area to be allocated
- * @param[in] prio priority level for the new shell
- * @return A pointer to the shell thread.
- * @retval NULL thread creation failed because memory allocation.
- *
- * @api
- */
-#if CH_USE_HEAP && CH_USE_DYNAMIC
-Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) {
-
- return chThdCreateFromHeap(NULL, size, prio, shell_thread, (void *)scp);
-}
-#endif
-
-/**
- * @brief Create statically allocated shell thread.
- *
- * @param[in] scp pointer to a @p ShellConfig object
- * @param[in] wsp pointer to a working area dedicated to the shell thread stack
- * @param[in] size size of the shell working area
- * @param[in] prio priority level for the new shell
- * @return A pointer to the shell thread.
- *
- * @api
- */
-Thread *shellCreateStatic(const ShellConfig *scp, void *wsp,
- size_t size, tprio_t prio) {
-
- return chThdCreateStatic(wsp, size, prio, shell_thread, (void *)scp);
-}
-
-/**
- * @brief Reads a whole line from the input channel.
- *
- * @param[in] chp pointer to a @p BaseSequentialStream object
- * @param[in] line pointer to the line buffer
- * @param[in] size buffer maximum length
- * @return The operation status.
- * @retval TRUE the channel was reset or CTRL-D pressed.
- * @retval FALSE operation successful.
- *
- * @api
- */
-bool_t shellGetLine(BaseSequentialStream *chp, char *line, unsigned size) {
- char *p = line;
-
- while (TRUE) {
- char c;
-
- if (chSequentialStreamRead(chp, (uint8_t *)&c, 1) == 0)
- return TRUE;
- if (c == 4) {
- chprintf(chp, "^D");
- return TRUE;
- }
- if (c == 8) {
- if (p != line) {
- chSequentialStreamPut(chp, c);
- chSequentialStreamPut(chp, 0x20);
- chSequentialStreamPut(chp, c);
- p--;
- }
- continue;
- }
- if (c == '\r') {
- chprintf(chp, "\r\n");
- *p = 0;
- return FALSE;
- }
- if (c < 0x20)
- continue;
- if (p < line + size - 1) {
- chSequentialStreamPut(chp, c);
- *p++ = (char)c;
- }
- }
-}
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell.h
deleted file mode 100644
index e1699a18ba..0000000000
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file shell.h
- * @brief Simple CLI shell header.
- *
- * @addtogroup SHELL
- * @{
- */
-
-#ifndef _SHELL_H_
-#define _SHELL_H_
-
-/**
- * @brief Shell maximum input line length.
- */
-#if !defined(SHELL_MAX_LINE_LENGTH) || defined(__DOXYGEN__)
-#define SHELL_MAX_LINE_LENGTH 64
-#endif
-
-/**
- * @brief Shell maximum arguments per command.
- */
-#if !defined(SHELL_MAX_ARGUMENTS) || defined(__DOXYGEN__)
-#define SHELL_MAX_ARGUMENTS 4
-#endif
-
-/**
- * @brief Command handler function type.
- */
-typedef void (*shellcmd_t)(BaseSequentialStream *chp, int argc, char *argv[]);
-
-/**
- * @brief Custom command entry type.
- */
-typedef struct {
- const char *sc_name; /**< @brief Command name. */
- shellcmd_t sc_function; /**< @brief Command function. */
-} ShellCommand;
-
-/**
- * @brief Shell descriptor type.
- */
-typedef struct {
- BaseSequentialStream *sc_channel; /**< @brief I/O channel associated
- to the shell. */
- const ShellCommand *sc_commands; /**< @brief Shell extra commands
- table. */
-} ShellConfig;
-
-#if !defined(__DOXYGEN__)
-extern EventSource shell_terminated;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void shellInit(void);
- void shellExit(msg_t msg);
- Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio);
- Thread *shellCreateStatic(const ShellConfig *scp, void *wsp,
- size_t size, tprio_t prio);
- bool_t shellGetLine(BaseSequentialStream *chp, char *line, unsigned size);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SHELL_H_ */
-
-/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.c
new file mode 100644
index 0000000000..d5db0fd12c
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.c
@@ -0,0 +1,590 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file shell.c
+ * @brief Simple CLI shell code.
+ *
+ * @addtogroup SHELL
+ * @{
+ */
+
+#include
+
+#include "ch.h"
+#include "hal.h"
+#include "shell.h"
+#include "shell_cmd.h"
+#include "chprintf.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief Shell termination event source.
+ */
+event_source_t shell_terminated;
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+static char *parse_arguments(char *str, char **saveptr) {
+ char *p;
+
+ if (str != NULL)
+ *saveptr = str;
+
+ p = *saveptr;
+ if (!p) {
+ return NULL;
+ }
+
+ /* Skipping white space.*/
+ p += strspn(p, " \t");
+
+ if (*p == '"') {
+ /* If an argument starts with a double quote then its delimiter is another
+ quote.*/
+ p++;
+ *saveptr = strpbrk(p, "\"");
+ }
+ else {
+ /* The delimiter is white space.*/
+ *saveptr = strpbrk(p, " \t");
+ }
+
+ /* Replacing the delimiter with a zero.*/
+ if (*saveptr != NULL) {
+ *(*saveptr)++ = '\0';
+ }
+
+ return *p != '\0' ? p : NULL;
+}
+
+static void list_commands(BaseSequentialStream *chp, const ShellCommand *scp) {
+
+ while (scp->sc_name != NULL) {
+ chprintf(chp, "%s ", scp->sc_name);
+ scp++;
+ }
+}
+
+static bool cmdexec(const ShellCommand *scp, BaseSequentialStream *chp,
+ char *name, int argc, char *argv[]) {
+
+ while (scp->sc_name != NULL) {
+ if (strcmp(scp->sc_name, name) == 0) {
+ scp->sc_function(chp, argc, argv);
+ return false;
+ }
+ scp++;
+ }
+ return true;
+}
+
+#if (SHELL_USE_HISTORY == TRUE) || defined(__DOXYGEN__)
+static void del_histbuff_entry(ShellHistory *shp) {
+ int pos = shp->sh_beg + *(shp->sh_buffer + shp->sh_beg) + 1;
+
+ if (pos >= shp->sh_size)
+ pos -= shp->sh_size;
+
+ shp->sh_beg = pos;
+}
+
+static bool is_histbuff_space(ShellHistory *shp, int length) {
+
+ if (shp->sh_end >= shp->sh_beg) {
+ if (length < (shp->sh_size - (shp->sh_end - shp->sh_beg + 1)))
+ return true;
+ }
+ else {
+ if (length < (shp->sh_beg - shp->sh_end - 1))
+ return true;
+ }
+
+ return false;
+}
+
+static void save_history(ShellHistory *shp, char *line, int length) {
+
+ if (shp == NULL)
+ return;
+
+ if (length > shp->sh_size - 2)
+ return;
+
+ while ((*(line + length -1) == ' ') && (length > 0))
+ length--;
+
+ if (length <= 0)
+ return;
+
+ while (!is_histbuff_space(shp, length))
+ del_histbuff_entry(shp);
+
+ if (length < shp->sh_size - shp->sh_end - 1)
+ memcpy(shp->sh_buffer + shp->sh_end + 1, line, length);
+ else {
+ /*
+ * Since there isn't enough room left at the end of the buffer,
+ * split the line to save up to the end of the buffer and then
+ * wrap back to the beginning of the buffer.
+ */
+ int part_len = shp->sh_size - shp->sh_end - 1;
+ memcpy(shp->sh_buffer + shp->sh_end + 1, line, part_len);
+ memcpy(shp->sh_buffer, line + part_len, length - part_len);
+ }
+
+ /* Save the length of the current line and move the buffer end pointer */
+ *(shp->sh_buffer + shp->sh_end) = (char)length;
+ shp->sh_end += length + 1;
+ if (shp->sh_end >= shp->sh_size)
+ shp->sh_end -= shp->sh_size;
+ *(shp->sh_buffer + shp->sh_end) = 0;
+ shp->sh_cur = 0;
+}
+
+static int get_history(ShellHistory *shp, char *line, int dir) {
+ int count=0;
+
+ if (shp == NULL)
+ return -1;
+
+ /* Count the number of lines saved in the buffer */
+ int idx = shp->sh_beg;
+ while (idx != shp->sh_end) {
+ idx += *(shp->sh_buffer + idx) + 1;
+ if (idx >= shp->sh_size)
+ idx -= shp->sh_size;
+ count++;
+ }
+
+ if (dir == SHELL_HIST_DIR_FW) {
+ if (shp->sh_cur > 0)
+ shp->sh_cur -= 2;
+ else
+ return 0;
+ }
+
+ if (count >= shp->sh_cur) {
+ idx = shp->sh_beg;
+ int i = 0;
+ while (idx != shp->sh_end && shp->sh_cur != (count - i - 1)) {
+ idx += *(shp->sh_buffer + idx) + 1;
+ if (idx >= shp->sh_size)
+ idx -= shp->sh_size;
+ i++;
+ }
+
+ int length = *(shp->sh_buffer + idx);
+
+ if (length > 0) {
+ shp->sh_cur++;
+
+ memset(line, 0, SHELL_MAX_LINE_LENGTH);
+ if ((idx + length) < shp->sh_size) {
+ memcpy(line, (shp->sh_buffer + idx + 1), length);
+ }
+ else {
+ /*
+ * Since the saved line was split at the end of the buffer,
+ * get the line in two parts.
+ */
+ int part_len = shp->sh_size - idx - 1;
+ memcpy(line, shp->sh_buffer + idx + 1, part_len);
+ memcpy(line + part_len, shp->sh_buffer, length - part_len);
+ }
+ return length;
+ }
+ else if (dir == SHELL_HIST_DIR_FW) {
+ shp->sh_cur++;
+ return 0;
+ }
+ }
+ return -1;
+}
+#endif
+
+#if (SHELL_USE_COMPLETION == TRUE) || defined(__DOXYGEN__)
+static void get_completions(ShellConfig *scfg, char *line) {
+ const ShellCommand *lcp = shell_local_commands;
+ const ShellCommand *scp = scfg->sc_commands;
+ char **scmp = scfg->sc_completion;
+ char help_cmp[] = "help";
+
+ if (strstr(help_cmp, line) == help_cmp) {
+ *scmp++ = help_cmp;
+ }
+ while (lcp->sc_name != NULL) {
+ if (strstr(lcp->sc_name, line) == lcp->sc_name) {
+ *scmp++ = (char *)lcp->sc_name;
+ }
+ lcp++;
+ }
+ if (scp != NULL) {
+ while (scp->sc_name != NULL) {
+ if (strstr(scp->sc_name, line) == scp->sc_name) {
+ *scmp++ = (char *)scp->sc_name;
+ }
+ scp++;
+ }
+ }
+
+ *scmp = NULL;
+}
+
+static int process_completions(ShellConfig *scfg, char *line, int length, unsigned size) {
+ char **scmp = scfg->sc_completion;
+ char **cmp = scmp + 1;
+ char *c = line + length;
+ int clen = 0;
+
+ if (*scmp != NULL) {
+ if (*cmp == NULL) {
+ clen = strlen(*scmp);
+ int i = length;
+ while ((c < line + clen) && (c < line + size - 1))
+ *c++ = *(*scmp + i++);
+ if (c < line + size -1) {
+ *c = ' ';
+ clen++;
+ }
+ }
+ else {
+ while (*(*scmp + clen) != 0) {
+ while ((*(*scmp + clen) == *(*cmp + clen)) &&
+ (*(*cmp + clen) != 0) && (*cmp != NULL)) {
+ cmp++;
+ }
+ if (*cmp == NULL) {
+ if ((c < line + size - 1) && (clen >= length))
+ *c++ = *(*scmp + clen);
+ cmp = scmp + 1;
+ clen++;
+ }
+ else {
+ break;
+ }
+ }
+ }
+
+ *(line + clen) = 0;
+ }
+
+ return clen;
+}
+
+static void write_completions(ShellConfig *scfg, char *line, int pos) {
+ BaseSequentialStream *chp = scfg->sc_channel;
+ char **scmp = scfg->sc_completion;
+
+ if (*(scmp + 1) != NULL) {
+ chprintf(chp, SHELL_NEWLINE_STR);
+ while (*scmp != NULL)
+ chprintf(chp, " %s", *scmp++);
+ chprintf(chp, SHELL_NEWLINE_STR);
+
+ chprintf(chp, SHELL_PROMPT_STR);
+ chprintf(chp, "%s", line);
+ }
+ else {
+ chprintf(chp, "%s", line + pos);
+ }
+}
+#endif
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Shell thread function.
+ *
+ * @param[in] p pointer to a @p BaseSequentialStream object
+ */
+THD_FUNCTION(shellThread, p) {
+ int n;
+ ShellConfig *scfg = p;
+ BaseSequentialStream *chp = scfg->sc_channel;
+ const ShellCommand *scp = scfg->sc_commands;
+ char *lp, *cmd, *tokp, line[SHELL_MAX_LINE_LENGTH];
+ char *args[SHELL_MAX_ARGUMENTS + 1];
+
+#if SHELL_USE_HISTORY == TRUE
+ *(scfg->sc_histbuf) = 0;
+ ShellHistory hist = {
+ scfg->sc_histbuf,
+ scfg->sc_histsize,
+ 0,
+ 0,
+ 0
+ };
+ ShellHistory *shp = &hist;
+#else
+ ShellHistory *shp = NULL;
+#endif
+
+ chprintf(chp, SHELL_NEWLINE_STR);
+ chprintf(chp, "ChibiOS/RT Shell"SHELL_NEWLINE_STR);
+ while (true) {
+ chprintf(chp, SHELL_PROMPT_STR);
+ if (shellGetLine(scfg, line, sizeof(line), shp)) {
+#if (SHELL_CMD_EXIT_ENABLED == TRUE) && !defined(_CHIBIOS_NIL_)
+ chprintf(chp, SHELL_NEWLINE_STR);
+ chprintf(chp, "logout");
+ break;
+#else
+ /* Putting a delay in order to avoid an endless loop trying to read
+ an unavailable stream.*/
+ osalThreadSleepMilliseconds(100);
+#endif
+ }
+ lp = parse_arguments(line, &tokp);
+ cmd = lp;
+ n = 0;
+ while ((lp = parse_arguments(NULL, &tokp)) != NULL) {
+ if (n >= SHELL_MAX_ARGUMENTS) {
+ chprintf(chp, "too many arguments"SHELL_NEWLINE_STR);
+ cmd = NULL;
+ break;
+ }
+ args[n++] = lp;
+ }
+ args[n] = NULL;
+ if (cmd != NULL) {
+ if (strcmp(cmd, "help") == 0) {
+ if (n > 0) {
+ shellUsage(chp, "help");
+ continue;
+ }
+ chprintf(chp, "Commands: help ");
+ list_commands(chp, shell_local_commands);
+ if (scp != NULL)
+ list_commands(chp, scp);
+ chprintf(chp, SHELL_NEWLINE_STR);
+ }
+ else if (cmdexec(shell_local_commands, chp, cmd, n, args) &&
+ ((scp == NULL) || cmdexec(scp, chp, cmd, n, args))) {
+ chprintf(chp, "%s", cmd);
+ chprintf(chp, " ?"SHELL_NEWLINE_STR);
+ }
+ }
+ }
+ shellExit(MSG_OK);
+}
+
+/**
+ * @brief Shell manager initialization.
+ *
+ * @api
+ */
+void shellInit(void) {
+
+ chEvtObjectInit(&shell_terminated);
+}
+
+#if !defined(_CHIBIOS_NIL_) || defined(__DOXYGEN__)
+/**
+ * @brief Terminates the shell.
+ * @note Must be invoked from the command handlers.
+ * @note Does not return.
+ *
+ * @param[in] msg shell exit code
+ *
+ * @api
+ */
+void shellExit(msg_t msg) {
+
+ /* Atomically broadcasting the event source and terminating the thread,
+ there is not a chSysUnlock() because the thread terminates upon return.*/
+ chSysLock();
+ chEvtBroadcastI(&shell_terminated);
+ chThdExitS(msg);
+}
+#endif
+
+/**
+ * @brief Reads a whole line from the input channel.
+ * @note Input chars are echoed on the same stream object with the
+ * following exceptions:
+ * - DEL and BS are echoed as BS-SPACE-BS.
+ * - CR is echoed as CR-LF.
+ * - 0x4 is echoed as "^D".
+ * - Other values below 0x20 are not echoed.
+ * .
+ *
+ * @param[in] scfg pointer to a @p ShellConfig object
+ * @param[in] line pointer to the line buffer
+ * @param[in] size buffer maximum length
+ * @param[in] shp pointer to a @p ShellHistory object or NULL
+ * @return The operation status.
+ * @retval true the channel was reset or CTRL-D pressed.
+ * @retval false operation successful.
+ *
+ * @api
+ */
+bool shellGetLine(ShellConfig *scfg, char *line, unsigned size, ShellHistory *shp) {
+ char *p = line;
+ BaseSequentialStream *chp = scfg->sc_channel;
+#if SHELL_USE_ESC_SEQ == TRUE
+ bool escape = false;
+ bool bracket = false;
+#endif
+
+#if SHELL_USE_HISTORY != TRUE
+ (void) shp;
+#endif
+
+ while (true) {
+ char c;
+
+ if (streamRead(chp, (uint8_t *)&c, 1) == 0)
+ return true;
+#if SHELL_USE_ESC_SEQ == TRUE
+ if (c == 27) {
+ escape = true;
+ continue;
+ }
+ if (escape) {
+ escape = false;
+ if (c == '[') {
+ escape = true;
+ bracket = true;
+ continue;
+ }
+ if (bracket) {
+ bracket = false;
+#if SHELL_USE_HISTORY == TRUE
+ if (c == 'A') {
+ int len = get_history(shp, line, SHELL_HIST_DIR_BK);
+
+ if (len > 0) {
+ _shell_reset_cur(chp);
+ _shell_clr_line(chp);
+ chprintf(chp, "%s", line);
+ p = line + len;
+ }
+ continue;
+ }
+ if (c == 'B') {
+ int len = get_history(shp, line, SHELL_HIST_DIR_FW);
+
+ if (len == 0)
+ *line = 0;
+
+ if (len >= 0) {
+ _shell_reset_cur(chp);
+ _shell_clr_line(chp);
+ chprintf(chp, "%s", line);
+ p = line + len;
+ }
+ continue;
+ }
+#endif
+ }
+ continue;
+ }
+#endif
+#if (SHELL_CMD_EXIT_ENABLED == TRUE) && !defined(_CHIBIOS_NIL_)
+ if (c == 4) {
+ chprintf(chp, "^D");
+ return true;
+ }
+#endif
+ if ((c == 8) || (c == 127)) {
+ if (p != line) {
+ streamPut(chp, 0x08);
+ streamPut(chp, 0x20);
+ streamPut(chp, 0x08);
+ p--;
+ }
+ continue;
+ }
+ if (c == '\r') {
+ chprintf(chp, SHELL_NEWLINE_STR);
+#if SHELL_USE_HISTORY == TRUE
+ save_history(shp, line, p - line);
+#endif
+ *p = 0;
+ return false;
+ }
+#if SHELL_USE_COMPLETION == TRUE
+ if (c == '\t') {
+ if (p < line + size - 1) {
+ *p = 0;
+
+ get_completions(scfg, line);
+ int len = process_completions(scfg, line, p - line, size);
+ if (len > 0) {
+ write_completions(scfg, line, p - line);
+ p = line + len;
+ }
+ }
+ continue;
+ }
+#endif
+#if SHELL_USE_HISTORY == TRUE
+ if (c == 14) {
+ int len = get_history(shp, line, SHELL_HIST_DIR_FW);
+
+ if (len == 0)
+ *line = 0;
+
+ if (len >= 0) {
+ _shell_reset_cur(chp);
+ _shell_clr_line(chp);
+ chprintf(chp, "%s", line);
+ p = line + len;
+ }
+ continue;
+ }
+ if (c == 16) {
+ int len = get_history(shp, line, SHELL_HIST_DIR_BK);
+
+ if (len > 0) {
+ _shell_reset_cur(chp);
+ _shell_clr_line(chp);
+ chprintf(chp, "%s", line);
+ p = line + len;
+ }
+ continue;
+ }
+#endif
+ if (c < 0x20)
+ continue;
+ if (p < line + size - 1) {
+ streamPut(chp, c);
+ *p++ = (char)c;
+ }
+ }
+}
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.h
new file mode 100644
index 0000000000..5a454fa8aa
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.h
@@ -0,0 +1,227 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file shell.h
+ * @brief Simple CLI shell header.
+ *
+ * @addtogroup SHELL
+ * @{
+ */
+
+#ifndef SHELL_H
+#define SHELL_H
+
+#if defined(SHELL_CONFIG_FILE)
+#include "shellconf.h"
+#endif
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Shell History Constants
+ */
+#define SHELL_HIST_DIR_BK 0
+#define SHELL_HIST_DIR_FW 1
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Shell maximum input line length.
+ */
+#if !defined(SHELL_MAX_LINE_LENGTH) || defined(__DOXYGEN__)
+#define SHELL_MAX_LINE_LENGTH 64
+#endif
+
+/**
+ * @brief Shell maximum arguments per command.
+ */
+#if !defined(SHELL_MAX_ARGUMENTS) || defined(__DOXYGEN__)
+#define SHELL_MAX_ARGUMENTS 4
+#endif
+
+/**
+ * @brief Shell maximum command history.
+ */
+#if !defined(SHELL_MAX_HIST_BUFF) || defined(__DOXYGEN__)
+#define SHELL_MAX_HIST_BUFF 8 * SHELL_MAX_LINE_LENGTH
+#endif
+
+/**
+ * @brief Enable shell command history
+ */
+#if !defined(SHELL_USE_HISTORY) || defined(__DOXYGEN__)
+#define SHELL_USE_HISTORY FALSE
+#endif
+
+/**
+ * @brief Enable shell command completion
+ */
+#if !defined(SHELL_USE_COMPLETION) || defined(__DOXYGEN__)
+#define SHELL_USE_COMPLETION FALSE
+#endif
+
+/**
+ * @brief Shell Maximum Completions (Set to max commands with common prefix)
+ */
+#if !defined(SHELL_MAX_COMPLETIONS) || defined(__DOXYGEN__)
+#define SHELL_MAX_COMPLETIONS 8
+#endif
+
+/**
+ * @brief Enable shell escape sequence processing
+ */
+#if !defined(SHELL_USE_ESC_SEQ) || defined(__DOXYGEN__)
+#define SHELL_USE_ESC_SEQ FALSE
+#endif
+
+/**
+ * @brief Prompt string
+ */
+#if !defined(SHELL_PROMPT_STR) || defined(__DOXYGEN__)
+#define SHELL_PROMPT_STR "ch> "
+#endif
+
+/**
+ * @brief Newline string
+ */
+#if !defined(SHELL_NEWLINE_STR) || defined(__DOXYGEN__)
+#define SHELL_NEWLINE_STR "\r\n"
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Command handler function type.
+ */
+typedef void (*shellcmd_t)(BaseSequentialStream *chp, int argc, char *argv[]);
+
+/**
+ * @brief Custom command entry type.
+ */
+typedef struct {
+ const char *sc_name; /**< @brief Command name. */
+ shellcmd_t sc_function; /**< @brief Command function. */
+} ShellCommand;
+
+/**
+ * @brief Shell history type.
+ */
+typedef struct {
+ char *sh_buffer; /**< @brief Buffer to store command
+ history. */
+ const int sh_size; /**< @brief Shell history buffer
+ size. */
+ int sh_beg; /**< @brief Beginning command index
+ in buffer. */
+ int sh_end; /**< @brief Ending command index
+ in buffer. */
+ int sh_cur; /**< @brief Currently selected
+ command in buffer. */
+} ShellHistory;
+
+/**
+ * @brief Shell descriptor type.
+ */
+typedef struct {
+ BaseSequentialStream *sc_channel; /**< @brief I/O channel associated
+ to the shell. */
+ const ShellCommand *sc_commands; /**< @brief Shell extra commands
+ table. */
+#if (SHELL_USE_HISTORY == TRUE) || defined(__DOXYGEN__)
+ char *sc_histbuf; /**< @brief Shell command history
+ buffer. */
+ const int sc_histsize; /**< @brief Shell history buffer
+ size. */
+#endif
+#if (SHELL_USE_COMPLETION == TRUE) || defined(__DOXYGEN__)
+ char **sc_completion; /**< @brief Shell command completion
+ buffer. */
+#endif
+} ShellConfig;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Send escape codes to move cursor to the beginning of the line
+ *
+ * @param[in] stream pointer to a @p BaseSequentialStream object
+ *
+ * @notapi
+ */
+#define _shell_reset_cur(stream) chprintf(stream, "\033[%dD\033[%dC", \
+ SHELL_MAX_LINE_LENGTH + \
+ strlen(SHELL_PROMPT_STR) + 2, \
+ strlen(SHELL_PROMPT_STR))
+
+/**
+ * @brief Send escape codes to clear the rest of the line
+ *
+ * @param[in] stream pointer to a @p BaseSequentialStream object
+ *
+ * @notapi
+ */
+#define _shell_clr_line(stream) chprintf(stream, "\033[K")
+
+/**
+ * @brief Prints out usage message
+ *
+ * @param[in] stream pointer to a @p BaseSequentialStream object
+ * @param[in] message pointer to message string
+ *
+ * @api
+ */
+#define shellUsage(stream, message) \
+ chprintf(stream, "Usage: %s"SHELL_NEWLINE_STR, message)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern event_source_t shell_terminated;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void shellInit(void);
+ THD_FUNCTION(shellThread, p);
+ void shellExit(msg_t msg);
+ bool shellGetLine(ShellConfig *scfg, char *line, unsigned size, ShellHistory *shp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* SHELL_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.mk b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.mk
new file mode 100644
index 0000000000..46ced2a83e
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell.mk
@@ -0,0 +1,5 @@
+# RT Shell files.
+SHELLSRC = $(CHIBIOS)/os/various/shell/shell.c \
+ $(CHIBIOS)/os/various/shell/shell_cmd.c
+
+SHELLINC = $(CHIBIOS)/os/various/shell
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell_cmd.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell_cmd.c
new file mode 100644
index 0000000000..d4468579d3
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell_cmd.c
@@ -0,0 +1,225 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file shell_cmd.c
+ * @brief Simple CLI shell common commands code.
+ *
+ * @addtogroup SHELL
+ * @{
+ */
+
+#include
+
+#include "ch.h"
+#include "hal.h"
+#include "shell.h"
+#include "shell_cmd.h"
+#include "chprintf.h"
+
+#if (SHELL_CMD_TEST_ENABLED == TRUE) || defined(__DOXYGEN__)
+#include "ch_test.h"
+#endif
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+#if ((SHELL_CMD_EXIT_ENABLED == TRUE) && !defined(_CHIBIOS_NIL_)) || \
+ defined(__DOXYGEN__)
+static void cmd_exit(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ (void)argv;
+ if (argc > 0) {
+ shellUsage(chp, "exit");
+ return;
+ }
+
+ shellExit(MSG_OK);
+}
+#endif
+
+#if (SHELL_CMD_INFO_ENABLED == TRUE) || defined(__DOXYGEN__)
+static void cmd_info(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ (void)argv;
+ if (argc > 0) {
+ shellUsage(chp, "info");
+ return;
+ }
+
+ chprintf(chp, "Kernel: %s"SHELL_NEWLINE_STR, CH_KERNEL_VERSION);
+#ifdef PORT_COMPILER_NAME
+ chprintf(chp, "Compiler: %s"SHELL_NEWLINE_STR, PORT_COMPILER_NAME);
+#endif
+ chprintf(chp, "Architecture: %s"SHELL_NEWLINE_STR, PORT_ARCHITECTURE_NAME);
+#ifdef PORT_CORE_VARIANT_NAME
+ chprintf(chp, "Core Variant: %s"SHELL_NEWLINE_STR, PORT_CORE_VARIANT_NAME);
+#endif
+#ifdef PORT_INFO
+ chprintf(chp, "Port Info: %s"SHELL_NEWLINE_STR, PORT_INFO);
+#endif
+#ifdef PLATFORM_NAME
+ chprintf(chp, "Platform: %s"SHELL_NEWLINE_STR, PLATFORM_NAME);
+#endif
+#ifdef BOARD_NAME
+ chprintf(chp, "Board: %s"SHELL_NEWLINE_STR, BOARD_NAME);
+#endif
+#ifdef __DATE__
+#ifdef __TIME__
+ chprintf(chp, "Build time: %s%s%s"SHELL_NEWLINE_STR, __DATE__, " - ", __TIME__);
+#endif
+#endif
+}
+#endif
+
+#if (SHELL_CMD_ECHO_ENABLED == TRUE) || defined(__DOXYGEN__)
+static void cmd_echo(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ (void)argv;
+ if (argc != 1) {
+ shellUsage(chp, "echo \"message\"");
+ return;
+ }
+ chprintf(chp, "%s"SHELL_NEWLINE_STR, argv[0]);
+}
+#endif
+
+#if (SHELL_CMD_SYSTIME_ENABLED == TRUE) || defined(__DOXYGEN__)
+static void cmd_systime(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ (void)argv;
+ if (argc > 0) {
+ shellUsage(chp, "systime");
+ return;
+ }
+ chprintf(chp, "%lu"SHELL_NEWLINE_STR, (unsigned long)chVTGetSystemTime());
+}
+#endif
+
+#if (SHELL_CMD_MEM_ENABLED == TRUE) || defined(__DOXYGEN__)
+static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
+ size_t n, total, largest;
+
+ (void)argv;
+ if (argc > 0) {
+ shellUsage(chp, "mem");
+ return;
+ }
+ n = chHeapStatus(NULL, &total, &largest);
+ chprintf(chp, "core free memory : %u bytes"SHELL_NEWLINE_STR, chCoreGetStatusX());
+ chprintf(chp, "heap fragments : %u"SHELL_NEWLINE_STR, n);
+ chprintf(chp, "heap free total : %u bytes"SHELL_NEWLINE_STR, total);
+ chprintf(chp, "heap free largest: %u bytes"SHELL_NEWLINE_STR, largest);
+}
+#endif
+
+#if (SHELL_CMD_THREADS_ENABLED == TRUE) || defined(__DOXYGEN__)
+static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
+ static const char *states[] = {CH_STATE_NAMES};
+ thread_t *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ shellUsage(chp, "threads");
+ return;
+ }
+ chprintf(chp, "stklimit stack addr refs prio state name\r\n"SHELL_NEWLINE_STR);
+ tp = chRegFirstThread();
+ do {
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || (CH_CFG_USE_DYNAMIC == TRUE)
+ uint32_t stklimit = (uint32_t)tp->wabase;
+#else
+ uint32_t stklimit = 0U;
+#endif
+ chprintf(chp, "%08lx %08lx %08lx %4lu %4lu %9s %12s"SHELL_NEWLINE_STR,
+ stklimit, (uint32_t)tp->ctx.sp, (uint32_t)tp,
+ (uint32_t)tp->refs - 1, (uint32_t)tp->prio, states[tp->state],
+ tp->name == NULL ? "" : tp->name);
+ tp = chRegNextThread(tp);
+ } while (tp != NULL);
+}
+#endif
+
+#if (SHELL_CMD_TEST_ENABLED == TRUE) || defined(__DOXYGEN__)
+static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
+ thread_t *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ shellUsage(chp, "test");
+ return;
+ }
+ tp = chThdCreateFromHeap(NULL, SHELL_CMD_TEST_WA_SIZE,
+ "test", chThdGetPriorityX(),
+ (tfunc_t)test_execute, chp);
+ if (tp == NULL) {
+ chprintf(chp, "out of memory"SHELL_NEWLINE_STR);
+ return;
+ }
+ chThdWait(tp);
+}
+#endif
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Array of the default commands.
+ */
+const ShellCommand shell_local_commands[] = {
+#if (SHELL_CMD_EXIT_ENABLED == TRUE) && !defined(_CHIBIOS_NIL_)
+ {"exit", cmd_exit},
+#endif
+#if SHELL_CMD_INFO_ENABLED == TRUE
+ {"info", cmd_info},
+#endif
+#if SHELL_CMD_ECHO_ENABLED == TRUE
+ {"echo", cmd_echo},
+#endif
+#if SHELL_CMD_SYSTIME_ENABLED == TRUE
+ {"systime", cmd_systime},
+#endif
+#if SHELL_CMD_MEM_ENABLED == TRUE
+ {"mem", cmd_mem},
+#endif
+#if SHELL_CMD_THREADS_ENABLED == TRUE
+ {"threads", cmd_threads},
+#endif
+#if SHELL_CMD_TEST_ENABLED == TRUE
+ {"test", cmd_test},
+#endif
+ {NULL, NULL}
+};
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell_cmd.h b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell_cmd.h
new file mode 100644
index 0000000000..47d0d17a84
--- /dev/null
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/shell/shell_cmd.h
@@ -0,0 +1,114 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file shell_cmd.h
+ * @brief Simple CLI shell common commands header.
+ *
+ * @addtogroup SHELL
+ * @{
+ */
+
+#ifndef SHELLCMD_H
+#define SHELLCMD_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+#if !defined(SHELL_CMD_EXIT_ENABLED) || defined(__DOXYGEN__)
+#define SHELL_CMD_EXIT_ENABLED TRUE
+#endif
+
+#if !defined(SHELL_CMD_INFO_ENABLED) || defined(__DOXYGEN__)
+#define SHELL_CMD_INFO_ENABLED TRUE
+#endif
+
+#if !defined(SHELL_CMD_ECHO_ENABLED) || defined(__DOXYGEN__)
+#define SHELL_CMD_ECHO_ENABLED TRUE
+#endif
+
+#if !defined(SHELL_CMD_SYSTIME_ENABLED) || defined(__DOXYGEN__)
+#define SHELL_CMD_SYSTIME_ENABLED TRUE
+#endif
+
+#if !defined(SHELL_CMD_MEM_ENABLED) || defined(__DOXYGEN__)
+#define SHELL_CMD_MEM_ENABLED TRUE
+#endif
+
+#if !defined(SHELL_CMD_THREADS_ENABLED) || defined(__DOXYGEN__)
+#define SHELL_CMD_THREADS_ENABLED TRUE
+#endif
+
+#if !defined(SHELL_CMD_TEST_ENABLED) || defined(__DOXYGEN__)
+#define SHELL_CMD_TEST_ENABLED TRUE
+#endif
+
+#if !defined(SHELL_CMD_TEST_WA_SIZE) || defined(__DOXYGEN__)
+#define SHELL_CMD_TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if (SHELL_CMD_MEM_ENABLED == TRUE) && (CH_CFG_USE_MEMCORE == FALSE)
+#error "SHELL_CMD_MEM_ENABLED requires CH_CFG_USE_MEMCORE"
+#endif
+
+#if (SHELL_CMD_MEM_ENABLED == TRUE) && (CH_CFG_USE_HEAP == FALSE)
+#error "SHELL_CMD_MEM_ENABLED requires CH_CFG_USE_HEAP"
+#endif
+
+#if (SHELL_CMD_THREADS_ENABLED == TRUE) && (CH_CFG_USE_REGISTRY == FALSE)
+#error "SHELL_CMD_THREADS_ENABLED requires CH_CFG_USE_REGISTRY"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const ShellCommand shell_local_commands[];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* SHELLCMD_H */
+
+/** @} */
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/syscalls.c b/flight/PiOS/Common/Libraries/ChibiOS/os/various/syscalls.c
index 4c337c339a..a7d995fa78 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/syscalls.c
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/syscalls.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -65,13 +65,9 @@
#include "hal.h"
#endif
-#ifndef __errno_r
-#include
-#define __errno_r(reent) reent->_errno
-#endif
-
/***************************************************************************/
+__attribute__((used))
int _read_r(struct _reent *r, int file, char * ptr, int len)
{
(void)r;
@@ -93,6 +89,7 @@ int _read_r(struct _reent *r, int file, char * ptr, int len)
/***************************************************************************/
+__attribute__((used))
int _lseek_r(struct _reent *r, int file, int ptr, int dir)
{
(void)r;
@@ -105,6 +102,7 @@ int _lseek_r(struct _reent *r, int file, int ptr, int dir)
/***************************************************************************/
+__attribute__((used))
int _write_r(struct _reent *r, int file, char * ptr, int len)
{
(void)r;
@@ -122,6 +120,7 @@ int _write_r(struct _reent *r, int file, char * ptr, int len)
/***************************************************************************/
+__attribute__((used))
int _close_r(struct _reent *r, int file)
{
(void)r;
@@ -132,12 +131,13 @@ int _close_r(struct _reent *r, int file)
/***************************************************************************/
+__attribute__((used))
caddr_t _sbrk_r(struct _reent *r, int incr)
{
-#if CH_USE_MEMCORE
+#if CH_CFG_USE_MEMCORE
void *p;
- chDbgCheck(incr > 0, "_sbrk_r");
+ chDbgCheck(incr >= 0);
p = chCoreAlloc((size_t)incr);
if (p == NULL) {
@@ -154,6 +154,7 @@ caddr_t _sbrk_r(struct _reent *r, int incr)
/***************************************************************************/
+__attribute__((used))
int _fstat_r(struct _reent *r, int file, struct stat * st)
{
(void)r;
@@ -166,6 +167,7 @@ int _fstat_r(struct _reent *r, int file, struct stat * st)
/***************************************************************************/
+__attribute__((used))
int _isatty_r(struct _reent *r, int fd)
{
(void)r;
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/os/various/various.dox b/flight/PiOS/Common/Libraries/ChibiOS/os/various/various.dox
index 4c46eaecf7..f31d5b6522 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/os/various/various.dox
+++ b/flight/PiOS/Common/Libraries/ChibiOS/os/various/various.dox
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -70,14 +70,6 @@
* @ingroup various
*/
-/**
- * @defgroup chrtclib RTC time conversion utilities
- *
- * @brief RTC time conversion utilities.
- *
- * @ingroup various
- */
-
/**
* @defgroup chprintf System formatted print
*
diff --git a/flight/PiOS/Common/Libraries/ChibiOS/readme.txt b/flight/PiOS/Common/Libraries/ChibiOS/readme.txt
index 0835356071..0f91dddae4 100644
--- a/flight/PiOS/Common/Libraries/ChibiOS/readme.txt
+++ b/flight/PiOS/Common/Libraries/ChibiOS/readme.txt
@@ -2,1155 +2,169 @@
*** Files Organization ***
*****************************************************************************
---{root} - ChibiOS/RT directory.
- +--readme.txt - This file.
- +--documentation.html - Shortcut to the web documentation page.
- +--todo.txt - Current plan (development/unstable versions only).
- +--license.txt - GPL license text.
- +--exception.txt - GPL exception text (stable releases only).
- +--boards/ - Board support files.
- +--demos/ - Demo projects.
- +--docs/ - Documentation.
- | +--html/ - Local HTML documentation (after rebuild).
- | +--reports/ - Test reports.
- | +--src/ - Documentation source files (required for rebuild).
- | +--rsc/ - Documentation resource files (required for rebuild).
- | +--Doxyfile - Doxygen project file (required for rebuild).
- | +--index.html - Local documentation access (after rebuild).
- +--ext/ - External libraries, not part of ChibiOS/RT.
- +--os/ - ChibiOS/RT files.
- | +--hal/ - Hardware Abstraction Layer.
- | | +--include/ - HAL high level headers.
- | | +--src/ - HAL high level source.
- | | +--platforms/ - HAL low level drivers implementations.
- | | | +--AT91SAM7/ - Drivers for AT91SAM7 platform.
- | | | +--AVR/ - Drivers for AVR platform.
- | | | +--LPC11xx/ - Drivers for LPC11xx platform.
- | | | +--LPC13xx/ - Drivers for LPC13xx platform.
- | | | +--LPC214x/ - Drivers for LPC214x platform.
- | | | +--MSP430/ - Drivers for MSP430 platform.
- | | | +--SPC56x/ - Drivers for SPC56x/MPC563xx platforms.
- | | | +--STM32/ - Drivers for STM32 platform (common).
- | | | +--STM32F1xx/- Drivers for STM32F1xx platform.
- | | | +--STM32F2xx/- Drivers for STM32F2xx platform.
- | | | +--STM32F4xx/- Drivers for STM32F4xx platform.
- | | | +--STM32L1xx/- Drivers for STM32L1xx platform.
- | | | +--Posix/ - Drivers for x86 Linux/OSX simulator platform.
- | | | +--Win32/ - Drivers for x86 Win32 simulator platform.
- | | +--templates/ - Driver template files.
- | | +--meta/ - Driver meta templates.
- | +--ports/ - Port files for the various architectures.
- | | +--GCC/ - Ports for the GCC compiler.
- | | | +--ARM/ - Port files for ARM7 and ARM9 architectures.
- | | | +--ARMCMx/ - Port files for ARMCMx architectures (ARMv6/7-M).
- | | | +--PPC/ - Port files for PowerPC architecture.
- | | | +--AVR/ - Port files for AVR architecture.
- | | | +--MSP430/ - Port files for MSP430 architecture.
- | | | +--SIMIA32/ - Port files for SIMIA32 simulator architecture.
- | | +--IAR/ - Ports for the IAR compiler.
- | | | +--ARMCMx/ - Port files for ARMCMx architectures (ARMv6/7-M).
- | | +--RVCT/ - Ports for the Keil RVCT compiler.
- | | | +--ARMCMx/ - Port files for ARMCMx architectures (ARMv6/7-M).
- | +--kernel/ - Kernel portable files.
- | | +--include/ - Kernel headers.
- | | +--src/ - Kernel source.
- | | +--templates/ - Kernel port template files.
- | +--various/ - Various portable support files.
- +--test/ - Kernel test suite source code.
- | +--coverage/ - Code coverage project.
- +--testhal/ - HAL integration test demos.
- | +--LPC11xx/ - LPC11xx HAL demos.
- | +--LPC13xx/ - LPC11xx HAL demos.
- | +--STM32F1xx/ - STM32F1xx HAL demos.
- | +--STM32F4xx/ - STM32F4xx HAL demos (valid for STM32F2xx too).
- | +--STM32L1xx/ - STM32L1xx HAL demos.
- +--tools - Various tools.
- +--eclipse - Eclipse enhancements.
+--{root} - ChibiOS directory.
+ +--readme.txt - This file.
+ +--documentation.html - Shortcut to the web documentation page.
+ +--license.txt - GPL license text.
+ +--demos/ - Demo projects, one directory per platform.
+ +--docs/ - Documentation.
+ | +--common/ - Documentation common build resources.
+ | +--hal/ - Builders for HAL.
+ | | +--Doxyfile_* - Doxygen project files (required for rebuild).
+ | | +--html/ - Local HTML documentation (after rebuild).
+ | | +--reports/ - Test reports.
+ | | +--rsc/ - Documentation resource files (required for rebuild).
+ | | +--src/ - Documentation source files (required for rebuild).
+ | | +--Doxyfile_* - Doxygen project files (required for rebuild).
+ | | +--index.html - Local documentation access (after rebuild).
+ | +--nil/ - Builders for NIL.
+ | | +--Doxyfile_* - Doxygen project files (required for rebuild).
+ | | +--html/ - Local HTML documentation (after rebuild).
+ | | +--reports/ - Test reports.
+ | | +--rsc/ - Documentation resource files (required for rebuild).
+ | | +--src/ - Documentation source files (required for rebuild).
+ | | +--Doxyfile_* - Doxygen project files (required for rebuild).
+ | | +--index.html - Local documentation access (after rebuild).
+ | +--rt/ - Builders for RT.
+ | | +--html/ - Local HTML documentation (after rebuild).
+ | | +--reports/ - Test reports.
+ | | +--rsc/ - Documentation resource files (required for rebuild).
+ | | +--src/ - Documentation source files (required for rebuild).
+ | | +--Doxyfile_* - Doxygen project files (required for rebuild).
+ | | +--index.html - Local documentation access (after rebuild).
+ +--ext/ - External libraries, not part of ChibiOS/RT.
+ +--os/ - ChibiOS components.
+ | +--common/ - Shared OS modules.
+ | | +--abstractions/ - API emulator wrappers.
+ | | | +--cmsis_os/ - CMSIS OS emulation layer for RT (ARMCMx port only).
+ | | | +--nasa_osal/ - NASA Operating System Abstraction Layer for RT.
+ | | +--ext/ - Vendor files used by the OS.
+ | | +--oslib/ - RTOS modules usable by both RT and NIL.
+ | | +--ports/ - RTOS ports usable by both RT and NIL.
+ | | +--startup/ - Startup support for all compilers and platforms.
+ | +--ex/ - EX component.
+ | | +--dox/ - EX documentation resources.
+ | | +--Micron/ - EX complex drivers for Micron devices.
+ | | +--ST/ - EX complex drivers for STMicroelectronics devices.
+ | | +--subsystems/ - EX subsystems.
+ | | | +--mfs/ - EX Managed Flash Storage module.
+ | +--hal/ - HAL component.
+ | | +--boards/ - HAL board support files.
+ | | +--dox/ - HAL documentation resources.
+ | | +--include/ - HAL high level headers.
+ | | +--lib/ - HAL libraries.
+ | | | +--fallback/ - HAL fall back software drivers.
+ | | | +--peripherals/- HAL peripherals interfaces.
+ | | | +--streams/ - HAL streams.
+ | | +--osal/ - HAL OSAL implementations.
+ | | | +--lib/ - HAL OSAL common modules.
+ | | +--src/ - HAL high level source.
+ | | +--ports/ - HAL ports.
+ | | +--templates/ - HAL driver template files.
+ | | +--osal/ - HAL OSAL templates.
+ | +--nil/ - NIL RTOS component.
+ | | +--dox/ - NIL documentation resources.
+ | | +--include/ - NIL high level headers.
+ | | +--src/ - NIL high level source.
+ | | +--templates/ - NIL configuration template files.
+ | +--rt/ - RT RTOS component.
+ | | +--dox/ - RT documentation resources.
+ | | +--include/ - RT high level headers.
+ | | +--src/ - RT high level source.
+ | | +--templates/ - RT configuration template files.
+ | +--various/ - Various portable support files.
+ +--test/ - Kernel test suite source code.
+ | +--lib/ - Portable test engine.
+ | +--hal/ - HAL test suites.
+ | | +--testbuild/ - HAL build test and MISRA check.
+ | +--nil/ - NIL test suites.
+ | | +--testbuild/ - NIL build test and MISRA check.
+ | +--rt/ - RT test suites.
+ | | +--testbuild/ - RT build test and MISRA check.
+ | | +--coverage/ - RT code coverage project.
+ +--testhal/ - HAL integration test demos.
*****************************************************************************
-*** Releases ***
+*** Releases and Change Log ***
*****************************************************************************
-*** 2.6.6 ***
-- FIX: Fixed error in STM32F30x adc_lld_stop() (bug #535).
-- FIX: Fixed STM32 DIER register setting in PWM and ICU drivers (bug #534).
-- FIX: Fixed ARMCM4 FPU exception randomly triggered (bug #533).
-- FIX: Fixed control transfers larger than 127 bytes don't work (bug #531).
-- FIX: Fixed STM32F0xx ADC driver enforces continuous mode (bug #528).
- Note, this bug enforced a change, now the bit ADC_CFGR1_CONT must be
- manually specified in the cfgr1 field of the ADCConversionGroup
- structure when applicable.
-- FIX: Fixed STM32F30x ADC driver enforces continuous mode (bug #527).
- Note, this bug enforced a change, now the bit ADC_CFGR_CONT must be
- manually specified in the cfgr field of the ADCConversionGroup
- structure when applicable.
-- FIX: Fixed double clock mode for TIM1/TIM8 on STM32F30x fails (bug #525).
-- FIX: Fixed SDC initialization error with V1.1 cards (bug #523).
-- FIX: Fixed Race condition in STM32 SDC driver (bug #522).
-- FIX: Fixed failure to compile EXT driver on STM32F401 (bug #517).
-- FIX: Fixed wrong DMA channels for STM32L1 I2C1 unit (bug #516).
-- FIX: Fixed EXT driver compile error on STM32F030 (bug #514).
-
-*** 2.6.5 ***
-- FIX: Fixed race condition in Cortex-M4 port with FPU and fast interrupts
- (bug #513).
-- FIX: Fixed STM32F1xx warning in stm32_dma.c (bug #512).
-- FIX: Fixed invalid checks in canSTM32SetFilters() function (bug #511).
-- FIX: Fixed missing check when disabling STM32F1 shared DMA IRQs (bug #510).
-- FIX: Fixed STM32L1 Medium Density Plus RTC Subseconds (bug #509).
-- FIX: Fixed stm32 CCM .ld file needs NOLOAD (bug #506).
-- FIX: Fixed dereference possibly null pointer before checking for nulliness
- in STM32 RTCv2 driver (bug #505).
-- FIX: Fixed race condition in STM32 (F1, F2, F4, L1) serial driver
- implementation (bug #503).
-- FIX: Fixed missing make dependencies for asm files (bug #501).
-- FIX: STM32L1 Plus Clock and I2C (bug #495).
-- NEW: Added support for STMicroelectronics STEVAL-MKI121V1 also known as
- INEMO-M1 Discovery board. A simple demo application using USB has been
- added.
-- NEW: Added support for STMicroelectronics NUCLEO-F103RB board.
-- NEW: Added support for STMicroelectronics NUCLEO-F401RE board.
-- NEW: Added support for STMicroelectronics NUCLEO-F030R8 board.
-- NEW: Added support for STMicroelectronics NUCLEO-L152RE board (not tested
- because lack of support in OpenOCD).
-- CHANGE: Made mii_read() and mii_write() public in the STM32 MAC driver.
-
-*** 2.6.4 ***
-- FIX: Fixed insufficient ISR-reserved stack in ARMCMx port when
- optimizations are disabled (bug #494).
-- FIX: Fixed configuration descriptors larger than 127 bytes don't
- work (bug #373).
-- FIX: Fixed invalid cast in PWM_FRACTION_TO_WIDTH() macro (bug #487).
-- FIX: Fixed wrong STM32 TIM9 clock source in PWM and ICU drivers (bug #486).
-- FIX: Fixed MMC_SPI driver block_addresses is not initialized after
- reconnection (bug #485).
-- FIX: Fixed STM32L1 Plus Compilation Problems (bug #484).
-- FIX: Fixed OTG HS failure when WFI instruction is enabled (bug #482).
-- FIX: Fixed wrong STM32F4 TIM6 vector number symbol (bug #480).
-- FIX: Fixed problem in STM32 SDADC driver initialization (bug #479).
-- FIX: Fixed chThdShouldTerminate() documentation incorrect (bug #478).
-- FIX: Fixed spurious callback in STM32 EXT driver (bug #477).
-- FIX: Fixed several macro errors in STM32L1xx HAL driver (bug #476).
-- FIX: Fixed wrong STM32 RTCv2 alarms implementation (bug #475).
-- FIX: Fixed wrong ADC34 macros in STM32F30x HAL driver (bug #474).
-- FIX: Fixed wrong TIM1 and TIM8 macros in STM32F30x HAL driver (bug #473).
-- FIX: Fixed chprintf()/chSequentialStreamWrite() crash with size of 0
- or NULL (bug #472).
-- FIX: Fixed simulated IO message is corrupted in simulator (bug #468).
-- FIX: Fixed typo in STMxx demo makefiles (bug #466).
-- FIX: Fixed wrong multilib handling in ChibiOS buildsystem (bug #465).
-- NEW: Improved makefiles backported from the 3.0 branch, make sure to use
- Makefiles taken from this version in your projects.
-- CHANGE: Made optional the STM32 MAC DMABMR SR reset procedure.
-
-*** 2.6.3 ***
-- FIX: Fixed TM32 SDC driver clock activation issue (bug #464).
-- FIX: Fixed spurious callback in ICU driver (bug #461).
-- FIX: Fixed compile error in STM32F0xx ADC driver when STM32F0XX_LD devices
- are selected (bug #460).
-- FIX: Fixed race condition in STM32 SDC driver (bug #458).
-- FIX: Fixed race condition in STM32 OTG driver (bug #457).
-- FIX: Fixed switch to LAN8710A PHY for STM32-E407 boards (bug #456).
-- FIX: Fixed add PHY id of LAN8710A (bug #455).
-- FIX: Fixed memstreams.c missing from simulator makefiles (bug #454).
-- FIX: Fixed chprintf() does not compile in strict C90 mode (bug #453).
-- FIX: Fixed corrupted mcuconf.h file in ARMCM4-STM32F407-DISCOVERY demo
- (bug #452).
-
-*** 2.6.2 ***
-- FIX: Fixed wrong vector names for STM32Lxx.
-- FIX: Fixed wrong STM32_TIM_CCMR2_OCxM macros on STM32F30x (bug #449).
-- FIX: Fixed STM32F30x TIM1/TIM8 alternate clock source setting not
- recognized (bug #448).
-- FIX: Fixed wrong MCO2 check in STM32F4xx HAL driver (bug #447).
-- FIX: Fixed spurious half buffer callback in STM32 ADC drivers (bug #446).
-- FIX: Fixed callbacks changes to the ADC high level driver (bug #445).
-- FIX: Fixed wrong definition in STM32F37x ADC driver (bug #444).
-- FIX: Fixed wrong CORTEX_PRIORITY_PENDSV value (bug #443).
-- FIX: Fixed lost incoming characters in STM32 USARTv1 driver (bug #442).
-- FIX: Fixed STM32 OTG-FS wrong upper memory limit (bug #437).
-- FIX: Fixed race condition in STM32 DMA interrupt (bug #439).
-- FIX: Fixed timing issue in the STM32 OTGv1 USB driver (bug #436).
-- FIX: Fixed STM32L1 remove reset flag (bug #435).
-- FIX: Fixed unaligned data access in USB LLD (bug #434).
-- FIX: Fixed add RTC to STM32L1 (bug #433).
-- FIX: Fixed support 10-bit addresses in STM32 I2C driver (bug #432).
-- FIX: Fixed duplicate STM32_GPT_USE_TIM8 definition in some mcuconf.h files
- (bug #431).
-- FIX: Fixed possible unalignment in GCC Cortex-M scatter files (bug #430).
-- NEW: Added support for STM32F030xx/050xx/060xx devices.
-- NEW: Added BOARD_OTG_NOVBUSSENS board option for STM32 OTG.
-- NEW: Added SPI4/SPI5/SPI6 support to the STM32v1 SPIv1 low level driver.
-- NEW: Added chvprintf() and chsnprintf() functions to the chprintf module.
-- NEW: Added a new function shellExit() to the shell. It allows to exit the
- shell from any command handler.
-- NEW: Added support for STM32F401/STM32F42x/STM32F43x devices.
-- NEW: Improved time range check in the kernel, new API chTimeElapsedSince()
- introduced. The API chTimeIsWithin() is now a macro.
-- NEW: Added support for STM32F0xx platform in RTCv2 driver.
-- NEW: Improvements to the STM32F4xx backup domain initialization.
-- NEW: Added support for STM32F4xx backup RAM.
-- NEW: Added support of UART4 and UART5 (STM32F4xx and STM32F2xx platforms)
- (feature request #28).
-
-*** 2.6.1 ***
-- FIX: Fixed PAL driver documentation error (bug #427).
-- FIX: Fixed UART4 and 5 marked as not present in STM32F30x devices (bug #426).
-- FIX: Fixed warning in STM32 ICU/PWM drivers when used on STM32F3xx (bug
- #425).
-- FIX: Fixed conditional code error in STM32 PWM driver (bug #424).
-- FIX: Fixed error in Guards of pwm_lld.h from STM32 (bug #423).
-- FIX: Fixed wrong RTC macro names in STM32L1xx HAL (bug #422).
-- FIX: Fixed CodeSourcery personal version fails to build with undefined
- errno_r (bug #421).
-- FIX: Fixed FSMC reset on STM32F4xx (bug #420).
-- FIX: Fixed invalid directory links in the demo files (bug #419).
-- FIX: Fixed missing casts in time-conversion macros (bug #418).
-- FIX: Fixed PLL2 activation condition is wrong in STM32F107 HAL (bug #417).
-- NEW: Improvements to the STM32F4xx backup domain initialization.
-- NEW: Added initializer for the DIER register to the STM32 GPT, ICU and
- PWM drivers.
-- NEW: Added support for 32bits counters to the STM32 GPT driver.
-- NEW: Added port support for SCP560B64.
-- CHANGE: Moved the STM32 GPT, ICU and PWM low level drivers under
- ./os/hal/platform/STM32/TIMv1. Updated all the impacted project files.
-
-*** 2.6.0 ***
-- FIX: Fixed MS2ST() and US2ST() macros error (bug #415).
-- NEW: Added new pwmIsChannelEnabledI() API to the PWM driver, implemented
- in the STM32 driver.
-- NEW: Added support for timers 6, 7, 9, 11, 12, 14 to the STM32 GPT driver.
-- NEW: Added support for timer 9 to the STM32 PWM and ICU drivers.
-- NEW: Relicensed parts of the distribution tree under the Apache 2.0
- license in order to make specific parts of the code more accessible
- to the open source community and adopters.
-- NEW: Added ADC(EQADC), HAL, ICU, PAL, PWM, Serial drivers for SPC5xx
- platforms, tests to be added on the various sub-families.
-- NEW: Added support for SPC56ELxx, SPC560BCxx, SPC560Pxx, SPC560Mxx and
- SPC564Axx platforms.
-- NEW: Now the general documentation includes data extracted from the low
- level driver templates. Per-platform/architecture documents are no more
- required and will be replaced with technical articles and examples for
- each specific driver.
-- NEW: Added a build test project for low level device driver templates.
-- NEW: Enhanced CAN driver model, support for mailboxes has been added. STM32
- driver implementation upgraded.
-- NEW: Added ADC and PWM drivers for the AT91SAM7 platform, both donated
- by Andrew Hannam.
-- NEW: Added kernel support for the SAM4L, an Atmel Studio 6 demo for the
- SAM4L-EK board has been added.
-- NEW: CAN2 support for STM32 added.
-- NEW: Updated STM32L1xx header to the latest version.
-- NEW: Added an option to lwipthread to change the link status poll interval.
-- NEW: Added new C++ demo for the STM32F4-Discovery.
-- NEW: Updated C++ wrapper with a much more logical classes structure.
-- NEW: ADC driver implementation for the STM32F3xx, the driver supports also
- the dual-ADC mode allowing for a very high combined bandwidth.
-- NEW: Added zero-copy capability to the STM32 MAC driver (experimental and
- not tested yet).
-- NEW: Added an optional zero-copy mode API to the MAC driver model.
-- NEW: Added EXT driver to the STM32F3xx platform.
-- NEW: Improved the STM32 EXT driver to support more than 32 channels.
-- NEW: Added support for Olimex board STM32-LCD.
-- NEW: Support for STM32F30x and STM32F37x.
-- NEW: AT91SAM7A3 support.
-- NEW: Unified the STM32F4xx and STM32F2xx platform code. The STM32F2xx now is
- only supported as an STM32F4xx variant and not tested separately.
-- NEW: Updated STM32F1, F2, F4, L1 ADC drivers to allow HW triggering.
-- NEW: Added a new option STM32_ETH1_CHANGE_PHY_STATE to the STM32 MAC driver,
- this change is connected to bug 3570335.
-- NEW: Modified the CAN drivers to use the new event flags mechanism, the
- previous flags handling has been removed.
-- NEW: Modified serial and serial_usb drivers to use the new event flags
- mechanism, the previous flags handling in BaseAsynchronousChannel has
- been removed.
-- NEW: Improved the kernel events subsystem, now event sources can associate
- source-specific flags to the listener, the flags can then be retrieved
- using the new APIs chEvtGetAndClearFlags() and chEvtGetAndClearFlagsI().
- Some old APIs have been renamed to increase consistency of the module.
-- NEW: Added VLE support to the Power Architecture GCC port.
-- NEW: Reorganized the Power Architecture GCC port along the lines of the
- ARMCMx port, now it can support multiple core types.
-- NEW: Updated the Power Architecture rules.mk file to put object and listing
- files into a ./build directory like ARM ports already do.
-- NEW: Added Eclipse project files to most demos. The project are setup to
- have paths relative to a variable named CHIBIOS that must point to the
- ChibiOS/RT installation path. The variable must be defined under
- Window->Preferences->General->Workspace->Linked_Resources and must contain
- a path without the trailing slash character.
-- NEW: Added memory signature record to the registry in order to simplify
- the implementation of ad-hoc debuggers.
-- NEW: Small andjustment in chcore.h files under ./os/ports/GCC required by a
- difference in GCC 4.7.x.
-- NEW: Added another STM32F4-Discovery demo using the on-board MEMS, SPI
- and PWM. Removed MEMS handling from the old demo because code size limits
- on non-free compilers.
-- NEW: Added USART6 support to the STM32 UARTv1 driver, contributed by Erik
- van der Zalm.
-- NEW: Added demo for Arduino Mega, contributed by Fabio Utzig.
-- NEW: Added support for ATmega1280, contributed by Fabio Utzig.
-- NEW: Added I2C driver for AVR, contributed by Fabio Utzig.
-- NEW: Added FatFs demo for the Olimex STM32-P107 board.
-- NEW: Added support for the Olimex STM32-E407 board. Added an integrated
- demo including USB-CDC, lwIP with web server, FatFs and shell, all running
- together.
-- NEW: Added an experimental and unsupported STM8 port for the IAR compiler,
- contributed by "king2".
-- NEW: Reorganized the STM32 EXT driver to have a sub-platform specific
- part containing all the ISR related code, this has been necessary because
- the significant differences among the various sub-families.
-- NEW: Validated CAN driver on STM32F2/F4 (backported to 2.4.2).
-- NEW: USB implementation for STM32F105/F107/2xx/F4xx devices.
-- NEW: Improved SerialUSB driver using the new queued mode, much smaller
- than the previous driver.
-- NEW: Improved USB driver model supporting also queues for endpoint I/O,
- packet mode removed.
-- NEW: Added an application-defined field to I/O queues (a void pointer).
-- NEW: Added board files for Maple Mini STM32F103, contributed by Wagner
- Sartori Junior.
-- NEW: Added SSP1 capability to the LPC13xx SPI driver.
-- NEW: Updated vendor headers for LPC11xx and LPC13xx, the new headers
- support several new devices.
-- NEW: Demo for STM32F0-Discovery board.
-- NEW: Initial support for STM32F0xx devices, added a specific ADC driver.
- Validated EXT, GPT, ICU, PAL, PWM, Serial, SPI, UART drivers.
-- NEW: Added a common ancestor class to the SDC and MMC_SPI drivers. This
- allows to share code and definitions.
-- NEW: Modified the SDC driver to implement the new block devices abstract
- interface.
-- NEW: Added two new functions to the MMC_SPI driver: mmcSync() and
- mmcGetInfo(). Also implemented the new block devices abstract
- interface. Moved the configuration parameters from mmcObjectInit() to
- the configuration structure saving some RAM space. Updated demos.
-- NEW: Added an abstract interface for block devices in the HAL. This
- abstraction layer is meant to unify the access protocol to the SDC and
- MMC_SPI (and potentially others) device drivers.
-- NEW: Added an abstract interface for serial devices in the HAL. This
- interface is meant to replace the equivalent class already present in the
- kernel. access macros are similar except for the prefix, "chn" instead
- of "chIO".
-- NEW: Updated the MSP port to work with the latest MSPGCC compiler (4.6.3
- LTS 20120406 unpatched), now the old MSPGCC 3.2.3 is no more supported
- (backported to 2.4.1).
-- NEW: EXT driver improved, now it is possible to reprogram channels at
- runtime without necessarily specifying a new configuration.
- TODO: Update AT91SAM7 EXT driver.
-- NEW: Integrated FatFS 0.9, now the FatFS integration files are centralized
- under ./os/various/fatfs_bindings and shared among all demos. The FatFS
- file ffconf.h is now application-specific like all the other configuration
- files.
-- NEW: Added an new option CORTEX_PRIGROUP_INIT to the Cortex-Mx ports in
- order to make priority organization configurable, the default is to
- assign all the available priority bits to preemption priority with no
- sub-priorities.
-- NEW: Added a new function chPoolLoadArray() to the Memory Pools subsystem,
- it allows to load an entire array element's into a pool with a single
- operation.
-- NEW: Addes support for .S patch in the GCC ARM ports, by Ayman El-Khashab.
-- NEW: Added a switch to the STM32F4 Makefile files in order to enable or
- disable the FPU support in a single place.
-- NEW: Added float support (optional) to chprintf(), by Fabio Utzig.
-- NEW: Added overflow handling in the ICU driver (contributed by Xo).
-- NEW: Updated debug plugin 1.0.8 (backported to 2.4.0).
-- NEW: Added more accurate UBRR calculation in AVR serial driver (backported
- to 2.4.0).
-- NEW: Revision of the round-robin scheduling, now threads do not lose their
- time slice when preempted. Each thread has its own time slices counter.
- TODO: Seek optimizations.
-- NEW: Modified the Virtual Timers management, now the callback is invoked
- not in lock mode. This change reduces the interrupt jitter caused by
- multiple timers used at same time.
-- NEW: Added board files and demo for Olimex LPC-P1343 (contributed by
- Johnny Halfmoon).
-- NEW: Added handling of input 2 to the STM32 ICU driver (contributed by
- Fabio).
-- NEW: STM32 Ethernet driver completed. Added STM32F107 and STM32F407
- lwIP demos (backported to 2.4.1).
-- NEW: lwIP related code is not centralized into a single place, no need to
- duplicate the code in each application or demo (backported to 2.4.1).
-- CHANGE: Added two new methods to the BaseSequentialStream interface:
- chSequentialStreamPut() and chSequentialStreamGet().
-- CHANGE: Removed the chioch.h header from the kernel, now channels interface
- is exported by the HAL. Removed functions chPutWouldBlock() and
- chGetWouldBlock().
-- CHANGE: Removed macro chMsgGetS(), chMsgGet() is still available.
-- CHANGE: chprintf() now takes a BaseSequentialStream as parameter instead
- of a BaseChannel making it more generic.
-- CHANGE: Now the shell requires a BaseSequentialStream instead of a
- BaseChannel for communications making it more generic.
-- CHANGE: Kernel memory pools now do not check the alignment of the inserted
- objects, it is responsibility of the application to insert properly
- aligned objects.
-- CHANGE: The PORT_INT_REQUIRED_STACK parameter for the Cortex-Mx ports has
- been increased to 32 from 16 because the stack frame sizes are increased
- when compiling with optimizations disabled, which is common during
- debugging. In order to save RAM trim back this value when compiling with
- optimizations enabled (backported to 2.4.1).
-- CHANGE: Renamed Ethernet driver in AT91 HAL ETHD1 (backported to 2.4.1).
-- CHANGE: Macros icuGetWidthI() and icuGetPeriodI() renamed to icuGetWidth()
- and icuGetPeriod().
-- Various documentation fixes and improvements.
-
-*** 2.4.4 ***
-- FIX: Fixed wrong Keil project in ARMCM3-STM32F107 demo (bug #408).
-- FIX: Fixed wrong macro in PWM driver (bug #407).
-- FIX: Fixed USB driver possible deadlock under certain configurations (bug
- #406).
-- FIX: Fixed USB driver cannot be stopped (bug #405).
-- FIX: Fixed fixed I2C malfunction after fixing bug 3607518 (bug 3607549).
-- FIX: Fixed spurious interrupt disabling an STM32 DMA stream (bug 3607518).
-- FIX: Fixed start of any ADC disables VREF and VBAT (bug 3607467).
-- FIX: Fixed CAN_USE_SLEEP_MODE compilation problem (bug 3606616).
-- FIX: Fixed misplaced brace in icu_lld.c (bug 3605832).
-- FIX: Fixed bug prevents calling adcStartConversionI() within ISR (bug
- 3605053).
-- FIX: Fixed typo in platforms/STM32/can_lld.c (bug 3604657).
-- FIX: Fixed duplicated code in hal_lld.h (STM32F4xx) (bug 3602544).
-- FIX: Fixed compile errors in Posix-GCC demo (bug 3601621).
-- FIX: Fixed state checker error in MSP430 port (bug 3601460).
-- FIX: Fixed wrong assertion in UART driver (bug 3600789).
-- FIX: Fixed small bug in shell argument parsing code in shell_thread (bug
- 3599328).
-- FIX: Fixed wrong condition in checksum offload of STM32 MAC driver (bug
- 3598720).
-- FIX: Fixed error in STM32 MAC driver degrades performance (bug 3598719).
-- NEW: Updated STM32L1xx header to the latest version.
-
-*** 2.4.3 ***
-- FIX: Fixed warning in STM32 ICU driver using IAR compiler (bug 3598177).
-- FIX: Fixed typo in chOQGetEmptyI() macro (bug 3595910).
-- FIX: Fixed possible false detect of loaded prescaler in RTCv1 driver (bug
- 3595489).
-- FIX: Fixed unneeded RTC initialization when HAL_USE_RTC disabled
- (bug 3594620).
-- FIX: Fixed compilation issue with HAL_USE_RTC disabled (bug 3594083).
-- FIX: Fixed wasting of BKP registers in RTCv1 driver (bug 3594005).
-- FIX: Fixed potential problem with RTC_CRL_RSF bit (bug 3593972).
-- FIX: Fixed STM32F1x rtc_lld_init not functional (bug 3592817).
-- FIX: Fixed DMA reconfiguration problem in STM32 SPI driver (bug 3592809).
-- FIX: Fixed STM32 UART driver redundant initialization (bug 3592764).
-- FIX: Fixed wrong stack initializations in GCC STM32L1xx port files (bug
- 3591321).
-- FIX: Fixed different redefinition for __main_stack_end__ symbol (bug
- 3591317).
-- FIX: Fixed errors in STM32F0xx UART driver (bug 3589412).
-- FIX: Fixed MSP430 port_switch code for MSPGCC issue (bug 3587633).
-- FIX: Fixed workaround for errata in STM32F4-A devices (bug 3586425).
-- FIX: Fixed error in palWritePad() macro (bug 3586230).
-- FIX: Fixed missing ; in testmbox.c (bug 3585979).
-- FIX: Fixed STM32_P407: implement mmc_lld_is_card_inserted (bug 3581929).
-- FIX: Fixed double chSysInit() call in MSP430F1611 demo (bug 3581304).
-- FIX: Fixed bug in abstract file interface (bug 3579660).
-- FIX: Fixed various typos and wrong limits in the STM32F4/F2 HAL driver
- (bug 3578944).
-- FIX: Fixed ARM CMx crt0.c fails at low optimization levels (bug 3578927).
-- FIX: Fixed compilation issue in syscalls.c (bug 3576771).
-- FIX: Fixed superfluous pack #defines cause nasty warning (bug 3575662).
-- FIX: Fixed mac.c won't compile due to misplaced declarations (bug 3575657).
-- FIX: Fixed STM32F4 ADC prescaler incorrectly initialized (bug 3575297).
-- FIX: Fixed RCC_APB2ENR_IOPEEN undeclared on STM32F10X_LD_VL devices (bug
- 3575098).
-- FIX: Fixed optimization disable (-O0) breaks kernel in CortexM/RVCT (bug
- 3573123).
-- FIX: Fixed misplaced declarations in lwip_bindings sys_arch.c (bug 3571053).
-- FIX: Fixed FatFS won't compile with _FS_REENTRANT enabled (bug 3570135).
-- FIX: Fixed mmc_spi.c won't compile due to misplaced declaration (bug
- 3570035).
-- FIX: Fixed GPIO glitch during PAL initialization (bug 3569347).
-- FIX: Fixed STM32F1x rtc_lld_init glitches rtc on hard reset (bug 3567597).
-- FIX: Fixed STM8L, cosmic compiler: c_lreg not saved (bug 3566342).
-- FIX: Fixed anomaly in USB enumeration (bug 3565325).
-- FIX: Fixed problem with lwIP statistics (bug 3564134).
-- FIX: Fixed packed structures macros not functional in IAR and RVCT port
- (bug 3561279).
-- FIX: Fixed Problem in FatFs demos related to LFN (bug 3560980).
-- NEW: Added memory signature record to the registry in order to simplify
- the implementation of ad-hoc debuggers.
-- NEW: I2C workaround allowing to read single byte on all STM32 platforms
- except STM32F1xx.
-- NEW: Small adjustment in chcore.h files under ./os/ports/GCC required by a
- difference in GCC 4.7.x.
-
-*** 2.4.2 ***
-- FIX: Fixed problem in STM32 DMA1 stream1 IRQ handler (bug 3538468).
-- FIX: Fixed wrong priority assigned to TIM8 in STM32 ICU driver (bug 3536950).
-- FIX: Fixed TIM8 not working in STM32 GPT driver (bug 3536523).
-- FIX: Fixed timer overflow not working in STM32 ICU driver for TIM1/TIM8 (bug
- 3536522).
-- FIX: Fixed wrong DMA channels on USART2 in STM32F10X_MD_VL devices (bug
- 3536070).
-- FIX: Fixed issue with DMA channel init in STM32 ADC and SPI drivers (bug
- 3535938).
-- FIX: Fixed unreliable PHY initialization (bug 3534819).
-- FIX: Fixed wrong ADC callback buffer pointer in ADC driver (bug 3534767).
-- FIX: Fixed lwIP-related files missing from version 2.4.1 (bug 3533887).
-- FIX: Fixed problem with arm-v6m and state checker (bug 3532591).
-- FIX: Fixed wrong MAC divider setting in STM32 MAC driver (bug 3531290).
-- FIX: Fixed wrong MCO1 divider in STM32F2/F4 HAL (bug 3531289).
-- FIX: Fixed missing "break" in AVR PAL driver (bug 3530924).
-- FIX: Fixed timeout related race condition in STM32 I2C driver (bug 3530043).
-- FIX: Fixed wrong macro check in STM32 MAC driver (bug 3527179).
-- FIX: Fixed error in STM32L-Discovery board.h file (bug 3526918).
-- NEW: Validated CAN driver on STM32F2/F4.
-- Small fixes to the STM32F4 board files.
-- Various documentation fixes and improvements.
-
-*** 2.4.1 ***
-- FIX: Fixed inconsistent LPCxxx Internal RC oscillator names (bug 3524138).
-- FIX: Fixed wrong frequency limit checks vs VDD in STM32F2xx HAL (bug
- 3524094).
-- FIX: Fixed STM32 I2C1 wrong alternate TX DMA setting (bug 3524088).
-- FIX: Fixed three testhal builds fail (bug 3523322).
-- FIX: Fixed MAC driver functions with invalid name (bug 3522808).
-- FIX: Fixed code coverage crashes with Linux/gcc-4.4.5 (bug 3522301).
-- FIX: Fixed macro dmaWaitCompletion() fails to compile in STM32 HAL (bug
- 3519202).
-- FIX: Fixed ARM addresses generated in vectors table (bug 3519037).
-- FIX: Fixed missing serial driver functionality for SAM7S64, SAM7S128 and
- SAM7S512 (bug 3517648).
-- FIX: Fixed a few more spelling fixes (bug 3515531).
-- FIX: Fixed spurious ) char in STM32 serial_lld.h (bug 3514138).
-- FIX: Fixed problem with FPU initialization in GCC Cortex-M4 port (bug
- 3513897).
-- FIX: Spelling fixes (bug 3510812).
-- FIX: Fixed STM32 ICUD8 not functional because wrong initialization (bug
- 3508758).
-- FIX: Fixed chMBFetchI does not decrement mb_fullsem (bug 3504450).
-- FIX: Fixed STM32 PLLI2S initialization error (bug 3503490).
-- FIX: Fixed USART3 not working on STM32F2/F4 UART driver (bug 3496981).
-- FIX: Fixed stack misalignment on Posix-MacOSX (bug 3495487).
-- FIX: Fixed STM8S HSI clock initialization error (bug 3489727).
-- FIX: Fixed MMC over SPI driver performs an unnecessary SPI read (bug
- 3486930).
-- FIX: Fixed Realtime counter initialization in STM32 HALs (bug 3485500).
-- FIX: Fixed PPC port broken when CH_DBG_SYSTEM_STATE_CHECK is activated
- (bug 3485667).
-- FIX: Fixed missing PLL3 check in STM32F107 HAL (bug 3485278).
-- FIX: Fixed ADC maximum frequency limit in STM32F2/F4 ADC drivers (bug
- 3484947).
-- FIX: Fixed various minor documentation errors (bug 3484942).
-- NEW: STM32 Ethernet driver completed. Added STM32F107 and STM32F407
- lwIP demos.
-- NEW: lwIP related code is not centralized into a single place, no need to
- duplicate the code in each application or demo.
-- NEW: Updated the MSP port to work with the latest MSPGCC compiler (4.6.3
- LTS 20120406 unpatched), now the old MSPGCC 3.2.3 is no more supported.
-- CHANGE: The PORT_INT_REQUIRED_STACK parameter for the Cortex-Mx ports has
- been increased to 32 from 16 because the stack frame sizes are increased
- when compiling with optimizations disabled, which is common during
- debugging. In order to save RAM trim back this value when compiling with
- optimizations enabled.
-- CHANGE: Renamed Ethernet driver in AT91 HAL ETHD1.
-
-*** 2.4.0 ***
-- NEW: Implemented new makefile system for ARM GCC ports, now objects,
- listings and output files are generated into a "build" directory and not
- together with sources, also implemented a simplified output log mode.
- Now makefiles and load script files are requirements and trigger a
- rebuild if touched.
-- NEW: Improved Cortex-Mx port, now the Cortex-M4 are Cortex-M4F are also
- supported. Improved startup files.
-- NEW: Added a new hook THREAD_CONTEXT_SWITCH_HOOK() that allows to insert
- code just before a context switch. For example this hook could be used
- in oder to implement advanced power management schemes.
-- NEW: Improved Event Flags subsystems in the kernel.
-- NEW: Added a macro THD_STATE_NAMES to chthreads.h. This macro is an
- initializer for string arrays containing thread state names.
-- NEW: Added a new debug option CH_DBG_SYSTEM_STATE_CHECK that ensures the
- correct API call protocol. If an API is invoked out of the correct context
- then the kernel panics with a debug message.
-- NEW: Added the new CMSIS 2.1 headers, now CMSIS resides into a shared
- location: ./os/ports/common/ARMCMx/CMSIS. Old CMSIS files have been
- removed from the various platforms.
-- NEW: Removed all the ch.ld files from the ARMCMx demos, now the makefiles
- point to common ld files under the various ports. Less duplication and
- easier maintenance.
-- NEW: Improved stack checking and reorganized memory map for the Cortex-Mx
- demos. Now stacks are allocated at the start of the RAM, an overflow of the
- exception stack now triggers an exception (it could go unnoticed before).
- The process stack is organized to be checked on context switch like other
- threads. Now all threads have an explicit stack boundary pointer.
-- NEW: Now the port layer exports info regarding the compiler and the port
- options. The info are printed into the test reports. Date and time also
- added.
-- NEW: Added initialization of the NVIC VTOR register to all Cortex-Mx (v7M)
- ports. Also added a port option CORTEX_VTOR_INIT to enforce a different
- default value into the register.
-- NEW: Added "IRQ_STORM" test applications to those platforms supporting
- ISR preemption.
-- NEW: Added a chprintf() function to ./os/various, it can print on any
- BaseChannel interface.
-- NEW: Improved the mini shell, enhanced info command, optimizations and
- removed the shellPrint() and shellPrintLine() functions, now it uses
- chprintf() for output.
-- NEW: USB driver model and USB implementation for STM32F1xx and STM32L1xx.
-- NEW: USB CDC abstract driver.
-- NEW: New driver models EXT, GPT, I2C, ICU, RTC, SDC, TM.
-- NEW: Improved PWM and MAC driver models.
-- NEW: Added support for STM32L1xx, STM32F2xx and STM32F4xx.
-- NEW: Updated the STM32F1xx header file to the latest version 3.5.0 and fixed
- it in order to correct several bugs related to the XL family.
-- NEW: Added an unified registers file for STM32: stm32.h. This file includes
- the appropriate vendor files then adds its own additional definitions.
-- NEW: Added TIM8 support to the STM32 GPT, ICU and PWM drivers.
-- NEW: DMA sharing in the STM32 HAL.
-- NEW: ADC specific drivers for STM32L1xx, STM32F2xx and STM32F4xx.
-- NEW: EXT driver AT91SAM7x and STM32(all).
-- NEW: PAL driver for AVR.
-- NEW: GPT driver for LPC11xx, LPC13xx and STM32(all).
-- NEW: I2C driver for STM32(all).
-- NEW: ICU driver for STM32(all).
-- NEW: RTC driver for STM32F1xx.
-- NEW: SDC driver for STM32F1xx.
-- NEW: Added handling of USART6 to the STM32 serial driver.
-- NEW: Added demos for the ST STM32F4-Discovery and STM32L1-Discovery kits.
-- NEW: Updated AVR demos to use the new PAL driver.
-- NEW: Now an error is generated at compile time when trying to enable the
- options CH_DBG_ENABLE_STACK_CHECK on ports that do not support it.
-- NEW: Added a kernel-only Cortex-Mx demo as reference project for users not
- interested in the HAL but just want to use the ChibiOS/RT kernel.
- The demo is named ARMCM3-GENERIC-KERNEL and is defaulted to the STM32, in
- order to use it on other families or on the ARM Cortex-M0 just change the
- inclusion paths in the makefile.
-- NEW: Integrated new FatFs version 0.8b.
-- NEW: lwIP 1.4.0 has been integrated, this new version does not require
- custom hooks into the Thread structure and is thus much lighter.
-- CHANGE: Now the callback associated to input queues is invoked before
- reading each character. Previously it was invoked only before going
- to sleep into the THD_STATE_WTQUEUE state.
-- CHANGE: Removed the option CH_USE_NESTED_LOCK, lwIP no more requires it and
- it would have conflicted with CH_DBG_SYSTEM_STATE_CHECK which is far more
- useful.
-- CHANGE: Renamed the scheduler functions chSchIsRescRequiredExI() to
- chSchIsPreemptionRequired(), chSchDoRescheduleI() to chSchDoReschedule(),
- chSysSwitchI() to chSysSwitch(). All those functions were special cases
- and not regular I-class APIs.
-- CHANGE: Renamed the macros IDLE_THREAD_STACK_SIZE and INT_REQUIRED_STACK
- to PORT_IDLE_THREAD_STACK_SIZE and PORT_INT_REQUIRED_STACK for consistency.
-- CHANGE: Removed the "old" Cortex-M3 port from the code, the current port
- has no drawbacks and the old port is now just a maintenance cost.
-- CHANGE: Removed the CH_CURRP_REGISTER_CACHE option, it is GCC-specific so
- it does not belong to the kernel options. The feature will be eventually
- reimplemented as a port-specific option.
-- CHANGE: Renamed the demo ARMCM3-STM32F107-GCC in ARMCM3-STM32F107 and added
- IAR and Keil projects.
-- CHANGE: Now the ARMCM3-STM32F107 demo targets the board Olimex STM32-P107
- as default.
-- CHANGE: Removed all the prefixes from the structure/union field names
- in the HAL subsystem.
-- CHANGE: Updated the documentation to use Doxygen 1.7.4 which produces a much
- more readable output. Also modified the documentation layout to put functions
- and variables ahead of everything else in the group pages.
- Doxygen version below 1.7.4 cannot be used anymore because differences in
- templates. Note that now there are two Doxygen projects, one for generating
- the CHM file the other for plain HTML.
-
-*** 2.2.8 ***
-- NEW: Added new API chThdExitS() in order to allow atomic operations on
- thead exit.
-- FIX: Fixed Extra initialization in STM32 SPI driver (bug 3436127).
-- FIX: Fixed DMA priority setting error in STM32 UART driver (bug 3436125).
-- FIX: Fixed DMA priority setting error in STM32 SPI driver (bug 3436124).
-- FIX: Fixed broken support for UART5 in STM32 serial driver (bug 3434094).
-- FIX: Fixed misplaced chRegSetThreadName() in ARM7-AT91SAM7S-FATFS-GCC demo
- (bug 3411780).
-- FIX: Fixed missing UART5 definition in STM32 HAL (bug 3411774).
-- FIX: The function chThdExit() triggers an error on shell return when the
- system state checker is enabled (bug 3411207).
-- FIX: Some ARMCMx makefiles refer the file rules.mk in the ARM7 port (bug
- 3411180).
-
-*** 2.2.7 ***
-- INFO: GCC test runs performed with YAGARTO 4.6.0.
-- NEW: Added debug plugin for Eclipse under ./tools/eclipse.
-- NEW: The debug macros chDbgCheck() and chDbgAssert() now can be externally
- redefined. The macro chDbgCheck() no more includes the line number in the
- description because incompatibility with the Cosmic compiler.
-- NEW: Added a new functionality to the registry subsystem, now it is possible
- to associate a name to the threads using chRegSetThreadName. The main and
- idle threads have their name assigned by default.
-- FIX: Fixed wrong check on CH_DBG_ENABLE_STACK_CHECK setting (bug 3387671).
-- FIX: Fixed wrong APB1 frequency check (bug 3361039).
-- FIX: Fixed missing state in shell demos (bug 3351556).
-- CHANGE: Removed todo.txt file, it does not belong to the stable version.
-
-*** 2.2.6 ***
-- FIX: Fixed race condition in Cortex-Mx ports (bug 3317500).
-- FIX: Fixed wrong macro check in STM32 UART driver (bug 3311999).
-
-*** 2.2.5 ***
-- FIX: Fixed STM32F107 demo build failure (bug 3294998).
-- NEW: Reorganization of the Cortex-Mx ports in order to reduced code and
- comments duplication in the various headers (backported to 2.2.5).
-- NEW: Improved the ARMv7-M sub-port now there are two modes: Compact and
- Advanced.
- The advanced mode is equivalent to the previous versions, the compact mode
- is new and makes the kernel *much* smaller and generally faster but does
- not support fast interrupts.
-- NEW: Added to the ARMv6-M sub-port an option to use the PendSV exception
- instead of NMI for preemption.
-
-*** 2.2.4 ***
-- FIX: Fixed CodeBlocks demo broken (bug 3304718).
-- FIX: Fixed race condition in output queues (bug 3303908).
-- FIX: Fixed CH_USE_HEAP and CH_USE_MALLOC_HEAP conflict (bug 3303841).
-- FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420).
-- FIX: Fixed invalid BRR() macro in AVR serial driver (bug 3299306).
-- FIX: Fixed missing IRQ vectors amicable names for STM32 XL devices (bug
- 3298889).
-- FIX: Fixed wrong identifier in AVR serial driver (bug 3292084).
-- FIX: Fixed wrong macro check for STM32 XL devices (bug 3291898).
-- FIX: Fixed SPI driver restart in STM32 SPI driver implementation, also
- applied the same fix to the STM8S SPI driver (bug 3288758).
-- FIX: Fixed missing state transition in ADC driver (bug 3288149).
-- FIX: Fixed missing state transition in SPI driver (bug 3288112).
-- NEW: Added an option to the kernel to not spawn the Idle Thread from within
- chSysInit(), this way the application can spawn a custom idle thread or
- even use the main() thread as idle thread.
-- CHANGE: chiQGetFullI() and chOQGetFullI() become macros. The queues
- subsystem has been optimized and is no more dependent on semaphores.
- Note that the queues callbacks invocation policy has been slightly
- changed, see the documentation.
-
-*** 2.2.3 ***
-- FIX: Fixed insufficient idle thread stack in Cortex-M0-GCC port
- (bug 3226671).
-- FIX: Fixed stack checking in Cortex-M0-GCC port (bug 3226657).
-- FIX: Fixed wrong checks in PAL driver (bug 3224681).
-- FIX: Fixed wrong checks in I/O Queues (bug 3219197).
-- FIX: Fixed invalid assertion in adcConvert() (bug 3205410).
-- NEW: Implemented stack checking in the Cortex-Mx RVCT port.
-- NEW: Improved preemption implementation for the Cortex-M0, now it uses
- the NMI vector in order to restore the original context. The change makes
- IRQ handling faster and also saves some RAM/ROM space. The GCC port code
- now does not inline the epilogue code in each ISR saving significant ROM
- space for each interrupt handler in the system.
-
-*** 2.2.2 ***
-- FIX: Fixed race condition in CM0 ports, the fix also improves the
- ISR latency (bug 3193062).
-- FIX: Fixed Cortex-Mx linker scripts alignment of __heap_base__, the
- correct alignment is now enforced at runtime into core_init() in order
- to make the OS integration easier (bug 3191112).
-- FIX: Fixed error in function chCoreAllocI() function documentation (bug
- 3191107).
-- FIX: Fixed minor problem with memory pools (bug 3190512).
-- NEW: Added I-Class functions to the MailBoxes subsystem, now it is
- possible to use them as a transport layer between ISRs and Threads.
-- CHANGE: Swapped the numeric values of the TIME_IMMEDIATE and TIME_INFINITE
- constants. Fixed the relative documentation in various places.
-- Documentation related fixes.
-
-*** 2.2.1 ***
-- FIX: Stack overflow in CM0 ports when nearing interrupts saturation (bug
- 3187105).
-- FIX: Fixed missing e200z test report (bug 3182611).
-- FIX: Fixed error in _BSEMAPHORE_DATA macro (bug 3184139).
-- FIX: Error in MAC driver (bug 3179783).
-- FIX: Fixed wrong serial driver macros (bug 3173336).
-
-*** 2.2.0 ***
-- NEW: The Cortex-Mx port now also supports the IAR and Keil compilers.
-- NEW: Improvements to the Cortex-Mx port.
-- NEW: Improved ARM port supporting both ARM7 and ARM9.
-- NEW: Support for binary semaphores in the kernel.
-- NEW: Improved kernel hooks.
-- NEW: Extensive improvements to the STM32 platform support.
-- NEW: SPI drivers for the AT91SAM7x, LPC11xx, LPC13xx, LPC214x, STM8S,
- platforms.
-- NEW: Unified STM8 port for both the Cosmic and the Raisonance compilers.
-- NEW: Demos for the STM8S-Discovery, STM8L-Discovery, STM32VL-Discovery
- boards.
-- NEW: Improved almost all the existing device driver models in the HAL.
-- NEW: Added test/example applications for all the device drivers in the HAL.
-- NEW: Added support for the STM8L platform.
-- NEW: New UART unbuffered serial device driver model.
-- NEW: Greatly improved documentation.
-- NEW: Lots of other minor improvements and optimizations, see the change
- log of the 2.1.x development branch for details.
-
-*** 2.0.10 ***
-- FIX: Fixed missing lines from the STM32 PWM driver (bug 3154403).
-- FIX: Fixed error in chIOGetxxxxxEventSource() macros (bug 3153550).
-- FIX: Fixed switch condition error in STM32 PWM driver (bug 3152482).
-
-*** 2.0.9 ***
-- FIX: Fixed error in output queues static initializer (bug 3149141).
-- FIX: Fixed extra notifications in input queues (bug 3148525).
-- FIX: Fixed error in sdPutTimeout() macro (bug 3138763).
-- FIX: Fixed preprocessing crt0.s fail (bug 3132293).
-- Documentation related fixes.
-
-*** 2.0.8 ***
-- FIX: Fixed failed memory recovery by registry scan, improved the related
- test case (bug 3116888).
-- FIX: Fixed PWM channels going to ACTIVE state when the pulse width is
- set to zero in the STM32 PWM driver (bug 3114481).
-- FIX: Fixed PWM channels return to IDLE state in STM32 PWM driver (bug
- 3114467).
-- CHANGE: Bugs 3114467 and 3114481 have been fixed by backporting the 2.1.x
- PWM driver, there is a difference in the PWM callback parameters.
-
-*** 2.0.7 ***
-- FIX: Fixed typo in board name (bug 3113574).
-- FIX: Fixed defective event wait functions with timeout (bug 3113443).
-
-*** 2.0.6 ***
-- FIX: Fixed typo in memstreams.h (bug 3089567).
-- FIX: Fixed wrong macro check in LPC214x and AT91SAM7 serial drivers (bug
- 3088776).
-- FIX: Fixed non functioning option SPI_USE_MUTUAL_EXCLUSION=FALSE (bug
- 3084764).
-- FIX: Fixed wrong macro check in STM32 serial support (but 3078891).
-- FIX: Fixed lwIP demo not working (bug 3076354).
-- FIX: Fixed non functioning option CH_USE_NESTED_LOCKS (bug 3075544).
-- CHANGE: The API chThdInit() has been renamed to chThdCreateI().
-
-*** 2.0.5 ***
-- FIX: Incorrect AT91SAM7X initialization, thanks Leszek (bug 3075354).
-- FIX: Fixed race condition in function chSchGoSleepTimeoutS, thanks Bal�zs
- (bug 3074984).
-- FIX: Fixed race condition in threads creation (bug 3069854).
-- FIX: Fixed broken CH_DBG_ENABLE_STACK_CHECK option in legacy CM3 port (bug
- 3064274).
-- FIX: Fixed CAN_USE_SLEEP_MODE setting (bug 3064204).
-
-*** 2.0.4 ***
-- FIX: Fixed potential issue with GCC reorganizing instructions around "asm
- volatile" statements (bug 3058731).
-- FIX: Fixed reduced ARM7 performance with GCC 4.5.x (bug 3056866).
-
-*** 2.0.3 ***
-- Tests reports regenerated using GCC 4.5.1, small performance improvements
- in all benchmarks.
-- FIX: Fixed crash of the Posix simulator under Ubuntu 10.4 (bug 3055329).
-- FIX: Fixed incorrect PLL2 setting in STM32 HAL (bug 3044770).
-- FIX: Fixed wrong check on STM32_HCLK (bug 3044758).
-- FIX: Fixed wrong condition check in STM32 PWM driver (bug 3041414).
-- FIX: Corrupted IRQ stack in Cortex-Mx port (bug 3041117).
-- FIX: Fixed a documentation error regarding the ADC driver function
- adcStartConversion() (bug 3039890).
-- FIX: Fixed insufficient stack size for idle thread (bug 3033624).
-- FIX: Fixed misspelled word in some chioch.h and chstreams.h macros (bug
- 3031534).
-- FIX: Fixed wrong macro check in the STM32 SPI driver (bug 3028562).
-
-
-*** 2.0.2 ***
-- FIX: Fixed invalid context restore in MSP430 port (bug 3027975).
-- FIX: Fixed STM32 vectors file (bug 3026528).
-- FIX: Fixed race condition in STM32 SPI driver (bug 3025854).
-- FIX: Fixed H_LOCK and H_UNLOCK redefined with CH_USE_MALLOC_HEAP (bug
- 3025549).
-- FIX: Added option to enforce the stack alignment to 32 or 64 bits in the
- Cortex-Mx port (bug 3025133).
-- NEW: Added friendly interrupt vectors names to the STM32 HAL (change request
- 3023944).
-- CHANGE: Removed the option -mabi=apcs-gnu from all the Cortex-Mx demos. The
- option is not compatible with the 64 bits stack alignment now default in
- the Cortex-Mx port. Note that the 64 bits alignment has a cost both as
- performance and as space but it is the "standard".
-
-*** 2.0.1 ***
-- FIX: Fixed notification order in input queues (bug 3020708).
-- FIX: Fixed non functional CH_CURRP_REGISTER_CACHE option in the Cortex-M3
- port (bug 3020702).
-- FIX: Fixed non functional CH_DBG_ENABLE_STACK_CHECK option in the Cortex-M3
- caused by GCC 4.5.0, the fix also improves the context switch performance
- because GCC 4.5.0 apparently was generating useless instructions within the
- very critical context switch code (bug 3019738).
-- FIX: Fixed insufficient stack space assigned to the idle thread in
- Cortex-M3 port (bug 3019594).
-- FIX: Fixed missing check in chIQReadTimeout() and chIQWriteTimeout() (bug
- 3019158).
-- FIX: Fixed instability in Mutexes subsystem (bug 3019099).
-- NEW: Added timers clock macros to the STM32 clock tree HAL driver.
-
-*** 2.0.0 ***
-- NEW: Implemented the concept of thread references, this mechanism ensures
- that a dynamic thread's memory is not freed while some other thread still
- owns a reference to the thread. Static threads are not affected by the new
- mechanism. Two new APIs have been added: chThdAddRef() and chThdRelease().
-- NEW: Now more than one thread can be waiting in chThdWait() as long they
- own a reference.
-- NEW: Implemented a new threads registry subsystem, the registry allows to
- enumerate the active threads at runtime and/or from a debugger. This is
- a preparatory step for a dedicated ChibiOS/RT debugger.
-- NEW: New chCoreFree() API that returns the core memory left.
-- NEW: Added a PowerPC port and demo targeting the SPC563M/MPC563xM
- ST/Freescale automotive SOCs.
-- NEW: Added STM8 port and demo targeting the Raisonance REva board
- with STM8S208RB piggyback.
-- NEW: New unified ARM Cortex-Mx port, this port supports both the ARMv6M
- and ARMv7-M architectures (Cortex-M0/M1/M3/M4 so far). The new port also
- allow to easily add to new Cortex-M implementations by simply adding a
- parameters file (cmparams.h).
-- NEW: Improved clock initialization for the STM32, now it is possible to
- configure the clock using any clock source and any HSE frequency.
-- NEW: The STM32 clock tree parameters and checks are now calculated into
- a separate file in order to support multiple clock trees for different
- sub-families of the STM32 platform.
-- NEW: Added separated clock trees for the STM32 LD/MD/HD sub-family and
- the CL sub-family. Now the selection of the sub-family is done in the
- board.h file, there is no more the need to put -DSTM32F10X_xx into
- the makefile.
-- NEW: Added support for STM32/HD/CL UART4 and UART5, thanks Egon for the
- patch.
-- NEW: Embedded Artists LPCxpresso Base Board support files added.
-- NEW: LPC11xx support, drivers (Serial, PAL, HAL) and demo.
-- NEW: LPC13xx support, drivers (Serial, PAL, HAL), demo and reports.
-- NEW: The port layer now can "capture" the implementation of individual
- scheduler API functions in order to provide architecture-optimized
- versions. This is done because further scheduler optimizations are
- becoming increasingly pointless without considering architecture and
- compiler related constraints.
-- NEW: Updated the STM32 FW Library files to latest version 3.3.0.
-- NEW: AT91SAM7 HAL support for the DGBU UART peripheral, as SD3.
-- NEW: Added a demo for the AT91SAM7S256 and board files for the Olimex
- SAM7-P256. The demo has been contributed by Alexander Kozaruk.
-- NEW: Added core variant name macro in chcore.h and platform name in
- hal_lld.h, the info are printed in the test report and from the "info"
- shell command.
-- NEW: Added BOARD_NAME macro to the various board.h files.
-- NEW: Added a MemoryStream class under ./os/various.
-- NEW: Added Mac OS-X support for the simulator. The Linux simulator has
- been renamed to Posix simulator in order to include this change in a
- single project.
-- NEW: New articles, sections and various improvements to the documentation.
-- NEW: Added to the simulators shell demos two new commands: threads and mem,
- that show the currently active threads (using the new registry) and the
- memory allocators state.
-- NEW: New articles and guides in the documentation.
-- OPT: New Cortex-M3 port code, *huge* performance improvements in all the
- context switching related benchmarks (up to 18% depending on the benchmark).
- The new code does no more require the use of the PendSV vector that is
- thus available to the user, it also saves four RAM bytes for each thread
- in the system. The old code is still available as a fall back option while
- the new one is being hardened by peer review and time, the two ports are
- perfectly interchangeable.
-- OPT: Speed/size optimization to the events subsystem.
-- OPT: Speed/size optimization to the mutexes subsystem.
-- OPT: Speed/size optimization to the condvars subsystem.
-- OPT: Speed/size optimization to the synchronous messages subsystem.
-- OPT: Small size optimization in the semaphores subsystem.
-- OPT: Minor optimizations in the "compact" code path.
-- OPT: Optimization on the interface between scheduler and port layer, now
- the kernel is even smaller and the context switch performance improved
- quite a bit on all the supported architectures.
-- OPT: Simplified the implementation of chSchYieldS() and made it a macro.
- The previous implementation was probably overkill and took too much space
- even if a bit faster.
-- OPT: Internal optimization in the serial driver, it now is a bit smaller
- and uses less RAM (all architectures).
-
-*** 1.4.3 ***
-- FIX: Fixed centralized ARM makefile (bug 2992747).
-- FIX: Fixed write problems in MMC_SPI driver (bug 2991714).
-- FIX: Fixed wrong macro check in serial.h (bug 2989459).
-
-*** 1.4.2 ***
-- FIX: Fixed missing reschedule in chEvtSignal() (bug 2961208).
-- FIX: Removed C99-style variables declarations (bug 2964418).
-- Minor documentation fixes.
-
-*** 1.4.1 ***
-- FIX: Fixed wrong UART deinitialization sequence in LPC214x serial driver
- (bug 2953985).
-- FIX: Fixed wrong PINSEL2 offset into lpc214x.h (bug 2953981).
-- FIX: Fixed invalid UART-related macro in the LPC214x HAL (bug 2953195).
-- FIX: Wrong prototype in template file chcore.c (bug 2951529).
-- FIX: Fixed insufficient stack space for the idle thread in the ARMCM3 port
- when compiling without optimizations (bug 2946233).
-- FIX: Fixed wrong notes on function chThdResume() (bug 2943160).
-- FIX: Fixed missing dependencies check for CH_USE_DYNAMIC (bug 2942757).
-- FIX: Fixed swapped thread states descriptions (bug 2938445).
-- FIX_ Fixed C99-style variable declaration (bug 2938444).
-
-*** 1.4.0 ***
-- Full test cycle and test reports updated.
-- NEW: Reorganized and rationalized the distribution tree and the
- documentation.
-- NEW: Abstract Streams and I/O Channels mechanisms introduced.
-- NEW: Added a new core memory manager.
-- NEW: Improved Heap and Pools allocators.
-- NEW: The I/O queues code has been improved, now there are 2 separate
- structures: InputQueue and OutputQueue.
-- NEW: Added timeout specification to the I/O queues read/write primitives.
-- NEW: Static initializers macros introduced for most kernel objects.
-- NEW: Added new APIs chSchDoYieldS() and chThdYield().
-- NEW: Improved and simplified kernel configuration files.
-- MEW: Added new benchmarks and test cases.
-- NEW: Added more test cases in order to improve the test suite code coverage
- (it was 74% in version 1.2.0, it is now close to 100%).
-- NEW: Added a code coverage analysis application under ./tests/coverage.
-- NEW: Added the test suite documentation to the general documentation.
-- NEW: Linux x86 simulator demo added.
-- NEW: Improved the Cortex-M3 preemption code.
-- NEW: Added standard CMSIS 1.2.0 support to the Cortex-M3 port.
-- NEW: Added support for the ST firmware library to the STM32 port.
-- NEW: Added support for HD and CL STM32 devices.
-- NEW: Improvements to the AT91SAM7 support.
-- NEW: Improved makefiles and makefile fragments, now the paths are not fixed.
-- NEW: Unified the initialization of the various drivers from a single HAL
- driver. The single drivers can be enabled or disabled from a HAL
- configuration file halconf.h.
-- NEW: Hardware Abstraction Layer (HAL) with support for PAL, ADC, CAN, MAC,
- MMC/SD, PWM, Serial, SPI drivers. Added driver implementations to the
- various platforms.
-- NEW: Added support for uIP, lwIP, FatFS external libraries, added demos.
-- Many many other improvements and minor features.
-
-*** 1.2.4 ***
-- FIX: Fixed GCC 4.4.x aliasing warnings (bug 2846336).
-- FIX: Modified linker scripts for GCC 4.4.x (bug 2846302).
-- FIX: Fixed the CH_OPTIMIZE_SPEED option in the CM3 port (bug 2846278).
-- FIX: Fixed GCC 4.4.x related problems in CM3 port (bug 2846162).
-- FIX: Fixed LPC214x UART problem (bug 2841088).
-
-*** 1.2.3 ***
-- FIX: Fixed C99-style variable declarations (bug 2792919).
-- FIX: Fixed instance of obsolete CH_USE_TERMINATE option in the C++ wrapper
- (bug 2796065).
-- FIX: Insufficient stack allocated to the C++ LPC2148 demo (bug 2796069).
-- FIX: Fixed errors in events test case (bug 2796081).
-- CHANGE: Increased main stack size to 1KiB for all the ARMx demos, 2KiB for
- the C++ LPC2148 demo. This should make things easier for unexperienced
- users.
-
-*** 1.2.2 ***
-- FIX: Fixed macro in test.h (bug 2781176).
-- FIX: Fixed @file tag in sam7x_serial.c (bug 2788573).
-- FIX: Fixed sequence assertion in test.c (bug 2789377).
-- FIX: Fixed test_cpu_pulse() incorrect behavior (bug 2789383).
-- FIX: Fixed missing volatile modifier for p_time field in Thread structure
- (bug 2789501).
-- CHANGE: Made the option CH_DBG_THREADS_PROFILING default to TRUE because it
- is now required in order to execute the whole test suite. Note that this
- option is very light so there is no real overhead in the system.
-- Added a (harmless) workaround to the Cortex-M3 startup file in order to
- make the RIDE7 demo compile on an unmodified distribution.
-
-*** 1.2.1 ***
-- FIX: Fixed regression in MinGW demo (bug 2745153).
-- FIX: Fixed problem with the timeout constant TIME_IMMEDIATE (bug 2755170).
-- FIX: Fixed a problem in semaphores test case #2 (bug 2755195).
-- FIX: Removed unused list functions (bug 2755230).
-- FIX: Added the exception notes into the source headers (bug 2772129).
-- FIX: Added license notice to several files (bug 2772160).
-- FIX: Found new instances of the obsolete function chSysGetTime() in the
- C++ wrapper and in the WEB demo (bug 2772237).
-
-*** 1.2.0 ***
-- Full test cycle and test reports updated.
-- NEW: Better separation between the port code and the system APIs, now an
- architecture-specific "driver" contains all the port related code.
- Port functions/macros are no more directly exposed as APIs to the user code.
-- NEW: Added a configuration option to enable nested system locks/unlocks.
-- NEW: Improved the interrupt handlers related code. Now interrupts are
- handled in a very similar way in every architecture. See the "Concepts"
- section and the "Writing interrupt handlers under ChibiOS/RT" article in the
- documentation.
-- NEW: Added the chEvtSignal() and chEvtSignalI() APIs that allows direct
- thread signaling, much more efficient that chEvtBroadcast() when the target
- is a known single thread.
-- NEW: Added a configuration option that enables the priority enqueuing on
- semaphores. It is defaulted to off because usually semaphores are used for
- I/O related tasks without hard realtime requirements.
-- NEW: Now the all the options in chconf.h and the various driver headers
- can be overridden externally, as example from within the Makefile.
- The options are no mode a simple define but a define with an assigned
- TRUE/FALSE value within an #ifndef block.
-- NEW: Idle thread hook macro added to the configuration file.
-- NEW: Changed the ARM7 and Cortex-M3 startup files, now the action when
- the main() function returns can be overridden by redefining the symbol
- MainExitHandler.
-- NEW: Mailboxes (asynchronous messages) subsystem and test cases added.
-- NEW: Most APIs with a timeout specification now accept the constant
- TIME_IMMEDIATE (-1) that triggers an immediate timeout when trying to enter
- a sleep state.
-- NEW: Mode flexible debug configuration options, removed the old CH_USE_DEBUG
- and CH_USE_TRACE. Replaced with CH_DBG_ENABLE_CHECKS, SCH_DBG_ENABLE_ASSERTS,
- CH_DBG_ENABLE_TRACE and CH_DBG_FILL_THREADS.
-- NEW: Added a debug option CH_DBG_THREADS_PROFILING for threads profiling.
- A field into the Thread structure counts the consumed time. The information
- is not used into the kernel, it is meant for debugging.
-- NEW: Added a debug option CH_DBG_ENABLE_STACK_CHECK for stack overflow
- checking. The check is not performed in the kernel but in the port code.
- Currently only the ARM7 and ARMCM3 ports implements it.
-- NEW: Unified makefiles for ARM7, ARMCM3 MSP430 projects, the new makefiles
- share a common part making them easier to maintain. Also reorganized the
- demo-specific part of the makefile, now it is easier to configure and the
- option can be overridden from outside.
-- OPT: Improved ARM7 thumb port code, thanks to some GCC tricks involving
- registers usage now the kernel is much smaller, faster and most OS APIs
- use less RAM in stack frames (note, this is an ARM7 thumb mode specific
- optimization).
-- OPT: Small optimization to the Cortex-M3 thread startup code, improved thread
- related performance scores and smaller code.
-- OPT: Alternative, non-inlined and more compact, implementations for
- port_lock() and port_unlock() in the Cortex-M3 port when CH_OPTIMIZE_SPEED
- is FALSE.
-- OPT: Improved ready list and priority ordered lists code, some space saved,
- better context switch performance.
-- CHANGE: Now the API chThdSetPriority() returns the old priority instead
- of void.
-- CHANGE: Modified the signature of the chMsgSendWithEvent() API, it now uses
- a more efficient event signaling method.
-- CHANGE: Removed the field p_tid from the Thread structure and the related
- code, this improved the thread creation scores (~2%) and saves some RAM.
- The trace buffer field cse_tid is now populated with a simple hash of the
- thread pointer as thread identifier.
-- CHANGE: Renamed the macros chSysIRQEnter() and chSysIRQExit() in
- CH_IRQ_PROLOGUE() and CH_IRQ_EPILOGUE() in order to make very clear that
- those are not functions but inlined code. Also introduced a new macro
- CH_IRQ_HANDLER that should be used when declaring an interrupt handler.
-- CHANGE: Renamed several internal initialization functions by removing the
- "ch" prefix because could not be considered system APIs.
-- CHANGE: Changed the chSemFastWaitS() macro in chSemFastWaitI() and
- chSemGetCounter() in chSemGetCounterI().
-- Improved ARM7 and Cortex-M3 support, new configuration options.
-- Introduced the concept of interrupt classes, see the documentation.
-- Introduced the concept of system states, see the documentation.
-- Huge improvements to the documentation.
-- Articles and notes previously in the wiki now merged in the general
- documentation and updated, the wiki entries are obsolete and will be removed.
-- New application notes and articles added.
-- Added kernel size metrics to the test reports.
-- Removed the inclusion graph from the documentation because the little
- info they add and the size of all the images. It is possible to configure
- Doxygen to have them again (and more graph types).
-- Improvements to the test suite, added a new level of indirection that allows
- to make tests depend on the configuration options without have to put #ifs
- into the test main module. New benchmarks about semaphores and mutexes.
-- Modified the test thread function to return the global test result flag.
-- Removed testcond.c|h and moved the test cases into testmtx.c. Mutexes and
- condvars have to be tested together.
-- Added architecture diagram to the documentation.
-
-*** 1.0.2 ***
-- FIX: Fixed priority inheritance problem with condvars (bug 2674756).
-- FIX: Fixed a problem in time ranges (bug 2680425).
-- Replaced ./docs/index.html with a direct shortcut to the documentation.
-
-*** 1.0.1 ***
-- NEW: Added to the STM32 demo makefile an option to build ChibiOS/RT with the
- full STM32 FWLib 2.03.
- Note that, except for the compile option, the library is not used by the
- OS nor supported.
-- FIX: Fixed a problem into the STACK_ALIGN() macro.
-- FIX: Fixed a problem with a wrong declaration of the PLL structure in the
- file lpc214x.h.
-- FIX: Modified the default value for the STM32 HSI setup it was 1, it should
- be 0x10.
-- FIX: Removed an obsolete constant (P_SUSPENDED) from thread.h.
-- FIX: Removed unused field mp_grow in the MemoryPool structure.
-- FIX: Fixed wrong assertions in chThdWait() and chHeapFree().
-- FIX: Fixed a problem with some event APIs not showing in the documentation.
-
-*** 1.0.0 ***
-- License switch, added GPL exception, see exception.txt.
-- Full test cycle and test reports updated.
-- Renamed some occurrences of "Conditional Variable" in "Condition Variable" in
- the documentation.
-- FIX: Fixed some images in the documentation because problems when seen in
- Internet Explorer.
+*** 17.6.3 ***
+- NIL: Fixed core and Heap allocators not functional in NIL (bug #902).
+- HAL: Fixed function uartSendFullTimeout() failing on STM32 USARTv1 and
+ v2 drivers (bug #901).
+- HAL: Fixed broken I2C fallback driver (bug #900).
+- LIB: Fixed heap buffer alignment not enforced (bug #899).
+- LIB: Fixed call protocol violation in chCoreAlloc() (bug #896).
+- RT: Fixed trace Buffer activation bits state reversed in chconf.h
+ (bug #895).
+- BLD: Fixed USE_OPT not passed to assembler in rules.mk (bug #892).
+- HAL: Fixed IRQ sharing issue in STM32 DMAv1 driver (bug #891).
+- HAL: Fixed CHPRINTF_USE_FLOAT defaulted to TRUE (bug #890).
+- HAL: Fixed various STM32 registry problems (more instances)(bug #889).
+
+*** 17.6.2 ***
+- HAL: Fixed various STM32 registry problems (bug #889).
+- LIB: Fixed heap allocator returning unaligned blocks (bug #888).
+
+*** 17.6.1 ***
+- NEW: Integrated the latest FatFS 0.13 with patches.
+- NEW: Improved RT and NIL test suite to report version numbers and
+ configuration settings.
+- NEW: Added a test suite generator tool written in FTL.
+- NEW: Added to the HAL USB driver a new function usbWakeupHost() for
+ standby exit.
+- NEW: Added shared Eclipse debug configurations for OpenOCD under
+ ./tools/eclipse/debug. Now it is no more required to re-create
+ those each time a new workspace is created, just import the global
+ ChibiOS project in it. The configurations will appear under the
+ Eclipse Tools menu. It is required to create an OPENOCD environment
+ variable pointing to the OpenOCD executable. It will be done in
+ ChibiStudio 20 by default.
+- NIL: Fixed duplicated entries in NIL documentation (bug #887).
+- HAL: Fixed EXT low level driver bug on AVR port (bug #886).
+- HAL: Fixed USB GET_DESCRIPTOR not handled for Interface Recipients (bug #885).
+- RT: MAILBOX_DECL size parameter is actually a count (bug #884).
+- HAL: Fixed error in uartReceiveTimeout() and uartSendTimeout() (bug #883).
+- HAL: Fixed TIMx DBL field macro broken (bug #880).
+- HAL: Fixed STM32 SPI problem in spi_lld_start() (bug #879).
+- HAL: Fixed invalid STM32 CAN3 filters initialization (bug #878).
+- HAL: Fixed missing CAN definitions in STM32L432 registry entry (bug #877).
+- HAL: Fixed missing STM32_TIM_MAX_CHANNELS definition in STM32L0 registry
+ (bug #876).
+- HAL: Fixed STM32 OTGv1 driver fails on STM32L4 (bug #875).
+- HAL: Fixed wrong I2S and SAI freq divisor (bug #874).
+- HAL: Fixed wrong SAI1 and SAI2 clock selection (bug #873).
+- HAL: Fixed invalid number of DMA channels on STM32L011 (bug #872).
+- HAL: Fixed STM32 USARTv2 serial incorrect buffer size declarations
+ (bug #871).
+- HAL: Fixed bug in STM32L0xx port related to STM32L0x1 (bug #870).
+- HAL: Fixed board file configuration for STM32F3 Discovery REVC (bug #869).
+- HAL: Fixed wrong PPRE2 and LSI related macros in STM32L0 hal lld (bug #868).
+- HAL: Fixed wrong bit mask in STM32L0 hal lld (bug #866).
+- RT: Fixed misplaced assertion in semaphores code (bug #865).
+- RT: Fixed event cast cleanup for compilation warnings (bug #864).
+- HAL: Fixed STM32 USBv1 fails the state check when USB_USE_WAIT is TRUE
+ (bug #863).
+- HAL: Fixed incorrect OTG stepping in STM32F412 registry (bug #861).
+- HAL: Fixed missing DMA I2C3 streams in STM32F411 registry (bug #860).
+- HAL: Fixed missing Ethernet PHY in some STM32 Nucleo-144 board files (bug
+ #859).
+- VAR: Fixed priority issue in STM32 Nucleo-64 F401RE demo (bug #858).
+- VAR: Fixed STM32L053 Discovery demo which is unaligned to standard demos (bug
+ #857).
+- HAL: Fixed HSI48 which is not correctly enabled in STM32L0xx port (bug #856).
+- HAL: Fixed unaligned STM32F0xx mcuconf.h files (bug #855).
+- HAL: Fixed invalid handling of DST flag in STM32 RTCv2 (bug #854).
+- HAL: Fixed extra right parenthesis in STM32F4 registry (bug #853).
+- EX: Fixed documentation-related issues (bug #852).
+- HAL: Fixed documentation-related issues (bug #852).
+- HAL: Fixed wrong frame size code in STM32 USARTv2 UART driver (bug #851).
+- NIL: Fixed documentation-related issues (bug #850).
+- RT: Fixed documentation-related issues (bug #850).
+- RT: Fixed leftover chcustomer.h file (bug #849).
+- RT: Fixed invalid check in chchecks.h (bug #848).
+- HAL: Fixed STM32F070xB: USART invalid DMA channels (bug #847).
+- VAR: Fixed CMSIS_OS issue in timers (bug #846).
+
+*** 17.6.0 ***
+- First 17.6.0 release, see release note 17.6.0.
diff --git a/flight/PiOS/Common/pios_heap.c b/flight/PiOS/Common/pios_heap.c
index 2b40965f15..01ae1fc772 100644
--- a/flight/PiOS/Common/pios_heap.c
+++ b/flight/PiOS/Common/pios_heap.c
@@ -32,6 +32,12 @@
#include /* uintptr_t */
#include /* bool */
+#if defined(PIOS_INCLUDE_CHIBIOS)
+#if !defined(CH_CFG_USE_MEMCORE) || CH_CFG_USE_MEMCORE != TRUE
+#error "pios_heap: Need to use memcore with ChibiOS."
+#endif
+#endif
+
#define DEBUG_MALLOC_FAILURES 0
static volatile bool malloc_failed_flag = false;
static void malloc_failed_hook(void)
@@ -53,6 +59,8 @@ bool PIOS_heap_malloc_failed_p(void)
#include "pios_thread.h"
#endif
+#if !defined(PIOS_INCLUDE_CHIBIOS) || defined(PIOS_INCLUDE_FASTHEAP)
+
struct pios_heap {
const uintptr_t start_addr;
uintptr_t end_addr;
@@ -103,6 +111,10 @@ static size_t simple_get_free_bytes(struct pios_heap *heap)
return heap->end_addr - heap->free_addr;
}
+#endif
+
+#if !defined(PIOS_INCLUDE_CHIBIOS)
+
static void simple_extend_heap(struct pios_heap *heap, size_t bytes)
{
heap->end_addr += bytes;
@@ -119,12 +131,16 @@ static struct pios_heap pios_standard_heap = {
.end_addr = (const uintptr_t)&_eheap,
.free_addr = (uintptr_t)&_sheap,
};
-
+#endif
void * pvPortMalloc(size_t size) __attribute__((alias ("PIOS_malloc"), weak));
void * PIOS_malloc(size_t size)
{
+#if defined(PIOS_INCLUDE_CHIBIOS)
+ void *buf = chCoreAlloc(size);
+#else
void *buf = simple_malloc(&pios_standard_heap, size);
+#endif
if (buf == NULL)
malloc_failed_hook();
@@ -178,8 +194,10 @@ void PIOS_free(void * buf)
return simple_free(&pios_nodma_heap, buf);
#endif /* PIOS_INCLUDE_FASTHEAP */
+#if !defined(PIOS_INCLUDE_CHIBIOS)
if (is_ptr_in_heap_p(&pios_standard_heap, buf))
return simple_free(&pios_standard_heap, buf);
+#endif
}
size_t xPortGetFreeHeapSize(void) __attribute__((alias ("PIOS_heap_get_free_size")));
@@ -189,7 +207,11 @@ size_t PIOS_heap_get_free_size(void)
PIOS_Thread_Scheduler_Suspend();
#endif /* PIOS_INCLUDE_RTOS */
+#if defined(PIOS_INCLUDE_CHIBIOS)
+ size_t free_bytes = chCoreGetStatusX();
+#else
size_t free_bytes = simple_get_free_bytes(&pios_standard_heap);
+#endif
#if defined(PIOS_INCLUDE_RTOS)
PIOS_Thread_Scheduler_Resume();
@@ -236,7 +258,9 @@ void PIOS_heap_increase_size(size_t bytes)
PIOS_Thread_Scheduler_Suspend();
#endif /* PIOS_INCLUDE_RTOS */
+#if !defined(PIOS_INCLUDE_CHIBIOS)
simple_extend_heap(&pios_standard_heap, bytes);
+#endif
#if defined(PIOS_INCLUDE_RTOS)
PIOS_Thread_Scheduler_Resume();
diff --git a/flight/PiOS/Common/pios_mutex.c b/flight/PiOS/Common/pios_mutex.c
index 81cf95e3c4..bd15173a77 100644
--- a/flight/PiOS/Common/pios_mutex.c
+++ b/flight/PiOS/Common/pios_mutex.c
@@ -33,12 +33,12 @@
#if defined(PIOS_INCLUDE_CHIBIOS)
struct pios_mutex
{
- Mutex mtx;
+ mutex_t mtx;
};
struct pios_recursive_mutex
{
- Mutex mtx;
+ mutex_t mtx;
uint32_t count;
};
@@ -56,7 +56,7 @@ struct pios_mutex *PIOS_Mutex_Create(void)
if (mtx == NULL)
return NULL;
- chMtxInit(&mtx->mtx);
+ chMtxObjectInit(&mtx->mtx);
return mtx;
}
@@ -93,7 +93,8 @@ bool PIOS_Mutex_Unlock(struct pios_mutex *mtx)
{
PIOS_Assert(mtx != NULL);
- chMtxUnlock();
+ mutex_t *next = chMtxGetNextMutexS();
+ if (next) chMtxUnlock(next);
return true;
}
@@ -112,7 +113,7 @@ struct pios_recursive_mutex *PIOS_Recursive_Mutex_Create(void)
if (mtx == NULL)
return NULL;
- chMtxInit(&mtx->mtx);
+ chMtxObjectInit(&mtx->mtx);
mtx->count = 0;
return mtx;
@@ -134,7 +135,7 @@ bool PIOS_Recursive_Mutex_Lock(struct pios_recursive_mutex *mtx, uint32_t timeou
chSysLock();
- if (chThdSelf() != mtx->mtx.m_owner)
+ if (chThdGetSelfX() != mtx->mtx.owner)
chMtxLockS(&mtx->mtx);
++mtx->count;
@@ -161,8 +162,10 @@ bool PIOS_Recursive_Mutex_Unlock(struct pios_recursive_mutex *mtx)
--mtx->count;
- if (mtx->count == 0)
- chMtxUnlockS();
+ if (mtx->count == 0) {
+ mutex_t *next = chMtxGetNextMutexS();
+ if (next) chMtxUnlockS(next);
+ }
chSysUnlock();
diff --git a/flight/PiOS/Common/pios_queue.c b/flight/PiOS/Common/pios_queue.c
index 08008309a8..bd349f26a3 100644
--- a/flight/PiOS/Common/pios_queue.c
+++ b/flight/PiOS/Common/pios_queue.c
@@ -36,8 +36,8 @@
struct pios_queue
{
- Mailbox mb;
- MemoryPool mp;
+ mailbox_t mb;
+ memory_pool_t mp;
void *mpb;
};
@@ -64,12 +64,12 @@ struct pios_queue *PIOS_Queue_Create(size_t queue_length, size_t item_size)
PIOS_free(queuep);
return NULL;
}
- chPoolInit(&queuep->mp, item_size, NULL);
+ chPoolObjectInit(&queuep->mp, item_size, NULL);
chPoolLoadArray(&queuep->mp, queuep->mpb, queue_length + PIOS_QUEUE_MAX_WAITERS);
/* Create the mailbox. */
msg_t *mb_buf = PIOS_malloc_no_dma(sizeof(msg_t) * queue_length);
- chMBInit(&queuep->mb, mb_buf, queue_length);
+ chMBObjectInit(&queuep->mb, mb_buf, queue_length);
return queuep;
}
@@ -104,7 +104,7 @@ bool PIOS_Queue_Send(struct pios_queue *queuep, const void *itemp, uint32_t time
if (buf == NULL)
return false;
- memcpy(buf, itemp, queuep->mp.mp_object_size);
+ memcpy(buf, itemp, queuep->mp.object_size);
systime_t timeout;
if (timeout_ms == PIOS_QUEUE_TIMEOUT_MAX)
@@ -116,7 +116,7 @@ bool PIOS_Queue_Send(struct pios_queue *queuep, const void *itemp, uint32_t time
msg_t result = chMBPost(&queuep->mb, (msg_t)buf, timeout);
- if (result != RDY_OK)
+ if (result != MSG_OK)
{
chPoolFree(&queuep->mp, buf);
return false;
@@ -138,26 +138,26 @@ bool PIOS_Queue_Send(struct pios_queue *queuep, const void *itemp, uint32_t time
*/
bool PIOS_Queue_Send_FromISR(struct pios_queue *queuep, const void *itemp, bool *wokenp)
{
- chSysLockFromIsr();
+ chSysLockFromISR();
void *buf = chPoolAllocI(&queuep->mp);
if (buf == NULL)
{
- chSysUnlockFromIsr();
+ chSysUnlockFromISR();
return false;
}
- memcpy(buf, itemp, queuep->mp.mp_object_size);
+ memcpy(buf, itemp, queuep->mp.object_size);
msg_t result = chMBPostI(&queuep->mb, (msg_t)buf);
- if (result != RDY_OK)
+ if (result != MSG_OK)
{
chPoolFreeI(&queuep->mp, buf);
- chSysUnlockFromIsr();
+ chSysUnlockFromISR();
return false;
}
- chSysUnlockFromIsr();
+ chSysUnlockFromISR();
return true;
}
@@ -187,10 +187,10 @@ bool PIOS_Queue_Receive(struct pios_queue *queuep, void *itemp, uint32_t timeout
msg_t result = chMBFetch(&queuep->mb, &buf, timeout);
- if (result != RDY_OK)
+ if (result != MSG_OK)
return false;
- memcpy(itemp, (void*)buf, queuep->mp.mp_object_size);
+ memcpy(itemp, (void*)buf, queuep->mp.object_size);
chPoolFree(&queuep->mp, (void*)buf);
@@ -208,7 +208,7 @@ bool PIOS_Queue_Receive(struct pios_queue *queuep, void *itemp, uint32_t timeout
size_t PIOS_Queue_GetItemSize(struct pios_queue *queuep)
{
PIOS_Assert(queuep);
- return queuep->mp.mp_object_size;
+ return queuep->mp.object_size;
}
#endif /* defined(PIOS_INCLUDE_CHIBIOS) */
diff --git a/flight/PiOS/Common/pios_semaphore.c b/flight/PiOS/Common/pios_semaphore.c
index 4a8b7ef83f..d60203b320 100644
--- a/flight/PiOS/Common/pios_semaphore.c
+++ b/flight/PiOS/Common/pios_semaphore.c
@@ -29,7 +29,7 @@
struct pios_semaphore
{
#if defined(PIOS_INCLUDE_CHIBIOS)
- BinarySemaphore sema;
+ binary_semaphore_t sema;
#else
uint32_t sema_count;
#endif
@@ -54,7 +54,7 @@ struct pios_semaphore *PIOS_Semaphore_Create(void)
/*
* The initial state of a binary semaphore is "given".
*/
- chBSemInit(&sema->sema, false);
+ chBSemObjectInit(&sema->sema, false);
return sema;
}
@@ -74,11 +74,11 @@ bool PIOS_Semaphore_Take(struct pios_semaphore *sema, uint32_t timeout_ms)
PIOS_Assert(sema != NULL);
if (timeout_ms == PIOS_SEMAPHORE_TIMEOUT_MAX)
- return chBSemWait(&sema->sema) == RDY_OK;
+ return chBSemWait(&sema->sema) == MSG_OK;
else if (timeout_ms == 0)
- return chBSemWaitTimeout(&sema->sema, TIME_IMMEDIATE) == RDY_OK;
+ return chBSemWaitTimeout(&sema->sema, TIME_IMMEDIATE) == MSG_OK;
else
- return chBSemWaitTimeout(&sema->sema, MS2ST(timeout_ms)) == RDY_OK;
+ return chBSemWaitTimeout(&sema->sema, MS2ST(timeout_ms)) == MSG_OK;
}
/**
@@ -131,9 +131,9 @@ bool PIOS_Semaphore_Give_FromISR(struct pios_semaphore *sema, bool *woken)
PIOS_Assert(sema != NULL);
PIOS_Assert(woken != NULL);
- chSysLockFromIsr();
+ chSysLockFromISR();
chBSemSignalI(&sema->sema);
- chSysUnlockFromIsr();
+ chSysUnlockFromISR();
return true;
}
diff --git a/flight/PiOS/Common/pios_thread.c b/flight/PiOS/Common/pios_thread.c
index ce6d31e52c..e56de10ea1 100644
--- a/flight/PiOS/Common/pios_thread.c
+++ b/flight/PiOS/Common/pios_thread.c
@@ -30,14 +30,19 @@
#error "pios_thread.c requires PIOS_INCLUDE_CHIBIOS"
#endif
+#if !defined(CH_CFG_USE_MEMCORE) || CH_CFG_USE_MEMCORE != TRUE
+#error "pios_thread: Need to use memcore with ChibiOS."
+#endif
+
#if defined(PIOS_INCLUDE_CHIBIOS)
struct pios_thread
{
- Thread *threadp;
+ thread_t *threadp;
+ uint32_t *stack;
};
-#define CVT_MS2ST(msec) ((systime_t)(((((uint32_t)(msec)) * ((uint64_t)CH_FREQUENCY) - 1UL) / 1000UL) + 1UL))
-#define CVT_ST2MS(n) (((((n) - 1ULL) * 1000ULL) / ((uint64_t)CH_FREQUENCY)) + 1UL)
+#define CVT_MS2ST(msec) ((systime_t)(((((uint32_t)(msec)) * ((uint64_t)CH_CFG_ST_FREQUENCY) - 1UL) / 1000UL) + 1UL))
+#define CVT_ST2MS(n) (((((n) - 1ULL) * 1000ULL) / ((uint64_t)CH_CFG_ST_FREQUENCY)) + 1UL)
/**
* Compute size that is at rounded up to the nearest
@@ -49,26 +54,6 @@ static uint32_t ceil_size(uint32_t size)
size = size + (a - size % a);
return size;
}
-/**
- * ChibiOS stack expects alignment (both start and end)
- * to 8 byte boundaries. This makes sure to allocate enough
- * memory and return an address that has the requested size
- * or more with these constraints.
- */
-static uint8_t * align8_alloc(uint32_t size)
-{
- // round size up to at nearest multiple of 8 + 4 bytes to guarantee
- // sufficient size within. This is because PIOS_malloc only guarantees
- // uintptr_t alignment which is 4 bytes.
- size = size + sizeof(uintptr_t);
- uint8_t *wap = PIOS_malloc(size);
-
- // shift start point to nearest 8 byte boundary.
- uint32_t pad = ((uint32_t) wap) % sizeof(stkalign_t);
- wap = wap + pad;
-
- return wap;
-}
/**
* @brief Creates a handle for the current thread.
@@ -82,9 +67,12 @@ struct pios_thread *PIOS_Thread_WrapCurrentThread(const char *namep)
struct pios_thread *thread = PIOS_malloc_no_dma(sizeof(struct pios_thread));
if (thread) {
- thread->threadp = chThdSelf();
-#if CH_USE_REGISTRY
- thread->threadp->p_name = namep;
+ thread->threadp = chThdGetSelfX();
+
+ extern uint32_t __main_thread_stack_base__;
+ thread->stack = &__main_thread_stack_base__;
+#if CH_CFG_USE_REGISTRY
+ thread->threadp->name = namep;
#endif /* CH_USE_REGISTRY */
}
@@ -122,14 +110,14 @@ struct pios_thread *PIOS_Thread_Create(void (*fp)(void *), const char *namep, si
// Use special functions to ensure ChibiOS stack requirements
stack_bytes = ceil_size(stack_bytes);
- uint8_t *wap = align8_alloc(stack_bytes);
+ uint8_t *wap = chCoreAllocAligned(stack_bytes, PORT_STACK_ALIGN);
if (wap == NULL)
{
PIOS_free(thread);
return NULL;
}
- thread->threadp = chThdCreateStatic(wap, stack_bytes, prio, (msg_t (*)(void *))fp, argp);
+ thread->threadp = chThdCreateStatic(wap, stack_bytes, prio, (tfunc_t)fp, argp);
if (thread->threadp == NULL)
{
PIOS_free(thread);
@@ -137,14 +125,18 @@ struct pios_thread *PIOS_Thread_Create(void (*fp)(void *), const char *namep, si
return NULL;
}
-#if CH_USE_REGISTRY
- thread->threadp->p_name = namep;
-#endif /* CH_USE_REGISTRY */
+#if CH_CFG_USE_REGISTRY
+ thread->threadp->name = namep;
+#endif /* CH_CFG_USE_REGISTRY */
+
+ /* Newer ChibiOS versions store the thread struct at the bottom of the stack allocation
+ instead of the top. */
+ thread->stack = (uint32_t*)wap;
return thread;
}
-#if (CH_USE_WAITEXIT == TRUE)
+#if (CH_CFG_USE_WAITEXIT == TRUE)
/**
*
* @brief Destroys an instance of @p struct pios_thread.
@@ -166,7 +158,7 @@ void PIOS_Thread_Delete(struct pios_thread *threadp)
}
#else
#error "PIOS_Thread_Delete requires CH_USE_WAITEXIT to be defined TRUE"
-#endif /* (CH_USE_WAITEXIT == TRUE) */
+#endif /* (CH_CFG_USE_WAITEXIT == TRUE) */
/**
*
@@ -177,7 +169,7 @@ void PIOS_Thread_Delete(struct pios_thread *threadp)
*/
uint32_t PIOS_Thread_Systime(void)
{
- return (uint32_t)CVT_ST2MS(chTimeNow());
+ return (uint32_t)CVT_ST2MS(chVTGetSystemTime());
}
/**
@@ -214,7 +206,7 @@ void PIOS_Thread_Sleep_Until(uint32_t *previous_ms, uint32_t increment_ms)
chSysLock();
- systime_t now = chTimeNow();
+ systime_t now = chVTGetSystemTime();
systime_t sleep_time = future - now;
if (sleep_time > increment_st) {
@@ -241,7 +233,7 @@ void PIOS_Thread_Sleep_Until(uint32_t *previous_ms, uint32_t increment_ms)
bool PIOS_Thread_Period_Elapsed(const uint32_t prev_systime, const uint32_t increment_ms)
{
/* TODO: make PIOS_Thread_Systime return opaque type to avoid ms conversion */
- return CVT_MS2ST(increment_ms) <= chTimeElapsedSince(CVT_MS2ST(prev_systime));
+ return CVT_MS2ST(increment_ms) <= chVTTimeElapsedSinceX(CVT_MS2ST(prev_systime));
}
/**
@@ -255,13 +247,13 @@ bool PIOS_Thread_Period_Elapsed(const uint32_t prev_systime, const uint32_t incr
uint32_t PIOS_Thread_Get_Stack_Usage(struct pios_thread *threadp)
{
#if CH_DBG_FILL_THREADS
- uint32_t *stack = (uint32_t*)((size_t)threadp->threadp + sizeof(*threadp->threadp));
+ uint32_t *stack = threadp->stack;
uint32_t *stklimit = stack;
while (*stack ==
- ((CH_STACK_FILL_VALUE << 24) |
- (CH_STACK_FILL_VALUE << 16) |
- (CH_STACK_FILL_VALUE << 8) |
- (CH_STACK_FILL_VALUE << 0)))
+ ((CH_DBG_STACK_FILL_VALUE << 24) |
+ (CH_DBG_STACK_FILL_VALUE << 16) |
+ (CH_DBG_STACK_FILL_VALUE << 8) |
+ (CH_DBG_STACK_FILL_VALUE << 0)))
++stack;
return (stack - stklimit) * 4;
#else
diff --git a/flight/PiOS/STM32/inc/chconf.h b/flight/PiOS/STM32/inc/chconf.h
index 0c43bf8600..de68222d2e 100644
--- a/flight/PiOS/STM32/inc/chconf.h
+++ b/flight/PiOS/STM32/inc/chconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -29,24 +29,49 @@
* @{
*/
-#ifndef _CHCONF_H_
-#define _CHCONF_H_
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_RT_CONF_
/*===========================================================================*/
/**
- * @name Kernel parameters and options
+ * @name System timers settings
* @{
*/
/*===========================================================================*/
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
-#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
-#define CH_FREQUENCY 1000
-#endif
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
/**
* @brief Round robin interval.
@@ -55,13 +80,12 @@
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
- *
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
*/
-#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
-#define CH_TIME_QUANTUM 1
-#endif
+#define CH_CFG_TIME_QUANTUM 1
/**
* @brief Managed RAM size.
@@ -72,28 +96,18 @@
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
- * @note Requires @p CH_USE_MEMCORE.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
*/
-#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
-#define CH_MEMCORE_SIZE 0
-#endif
+#define CH_CFG_MEMCORE_SIZE 0
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
- * does not spawn the idle thread automatically. The application has
- * then the responsibility to do one of the following:
- * - Spawn a custom idle thread at priority @p IDLEPRIO.
- * - Change the main() thread priority to @p IDLEPRIO then enter
- * an endless loop. In this scenario the @p main() thread acts as
- * the idle thread.
- * .
- * @note Unless an idle thread is spawned the @p main() thread must not
- * enter a sleep state.
- */
-#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
-#define CH_NO_IDLE_THREAD FALSE
-#endif
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
/** @} */
@@ -112,9 +126,7 @@
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
-#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
-#define CH_OPTIMIZE_SPEED TRUE
-#endif
+#define CH_CFG_OPTIMIZE_SPEED TRUE
/** @} */
@@ -125,15 +137,22 @@
*/
/*===========================================================================*/
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
-#define CH_USE_REGISTRY TRUE
-#endif
+#define CH_CFG_USE_REGISTRY TRUE
/**
* @brief Threads synchronization APIs.
@@ -142,9 +161,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
-#define CH_USE_WAITEXIT TRUE
-#endif
+#define CH_CFG_USE_WAITEXIT TRUE
/**
* @brief Semaphores APIs.
@@ -152,43 +169,36 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
-#define CH_USE_SEMAPHORES TRUE
-#endif
+#define CH_CFG_USE_SEMAPHORES TRUE
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
- * @note The default is @p FALSE. Enable this if you have special requirements.
- * @note Requires @p CH_USE_SEMAPHORES.
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
-#define CH_USE_SEMAPHORES_PRIORITY FALSE
-#endif
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
/**
- * @brief Atomic semaphore API.
- * @details If enabled then the semaphores the @p chSemSignalWait() API
- * is included in the kernel.
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
-#define CH_USE_SEMSW TRUE
-#endif
+#define CH_CFG_USE_MUTEXES TRUE
/**
- * @brief Mutexes APIs.
- * @details If enabled then the mutexes APIs are included in the kernel.
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
*
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
*/
-#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
-#define CH_USE_MUTEXES TRUE
-#endif
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
/**
* @brief Conditional Variables APIs.
@@ -196,11 +206,9 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_MUTEXES.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
*/
-#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
-#define CH_USE_CONDVARS FALSE
-#endif
+#define CH_CFG_USE_CONDVARS FALSE
/**
* @brief Conditional Variables APIs with timeout.
@@ -208,11 +216,9 @@
* specification are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_CONDVARS.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
*/
-#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
-#define CH_USE_CONDVARS_TIMEOUT FALSE
-#endif
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
/**
* @brief Events Flags APIs.
@@ -220,9 +226,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
-#define CH_USE_EVENTS FALSE
-#endif
+#define CH_CFG_USE_EVENTS TRUE
/**
* @brief Events Flags APIs with timeout.
@@ -230,11 +234,9 @@
* are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_EVENTS.
+ * @note Requires @p CH_CFG_USE_EVENTS.
*/
-#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
-#define CH_USE_EVENTS_TIMEOUT FALSE
-#endif
+#define CH_CFG_USE_EVENTS_TIMEOUT FALSE
/**
* @brief Synchronous Messages APIs.
@@ -243,21 +245,18 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
-#define CH_USE_MESSAGES FALSE
-#endif
+#define CH_CFG_USE_MESSAGES FALSE
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
- * @note The default is @p FALSE. Enable this if you have special requirements.
- * @note Requires @p CH_USE_MESSAGES.
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
*/
-#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
-#define CH_USE_MESSAGES_PRIORITY FALSE
-#endif
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
/**
* @brief Mailboxes APIs.
@@ -265,21 +264,9 @@
* included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_SEMAPHORES.
- */
-#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
-#define CH_USE_MAILBOXES TRUE
-#endif
-
-/**
- * @brief I/O Queues APIs.
- * @details If enabled then the I/O queues APIs are included in the kernel.
- *
- * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
-#define CH_USE_QUEUES FALSE
-#endif
+#define CH_CFG_USE_MAILBOXES TRUE
/**
* @brief Core Memory Manager APIs.
@@ -288,9 +275,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
-#define CH_USE_MEMCORE FALSE
-#endif
+#define CH_CFG_USE_MEMCORE TRUE
/**
* @brief Heap Allocator APIs.
@@ -298,27 +283,11 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
- * @p CH_USE_SEMAPHORES.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
-#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
-#define CH_USE_HEAP FALSE
-#endif
-
-/**
- * @brief C-runtime allocator.
- * @details If enabled the the heap allocator APIs just wrap the C-runtime
- * @p malloc() and @p free() functions.
- *
- * @note The default is @p FALSE.
- * @note Requires @p CH_USE_HEAP.
- * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
- * appropriate documentation.
- */
-#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
-#define CH_USE_MALLOC_HEAP FALSE
-#endif
+#define CH_CFG_USE_HEAP FALSE
/**
* @brief Memory Pools Allocator APIs.
@@ -327,9 +296,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
-#define CH_USE_MEMPOOLS TRUE
-#endif
+#define CH_CFG_USE_MEMPOOLS TRUE
/**
* @brief Dynamic Threads APIs.
@@ -337,12 +304,10 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_WAITEXIT.
- * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
-#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
-#define CH_USE_DYNAMIC FALSE
-#endif
+#define CH_CFG_USE_DYNAMIC FALSE
/** @} */
@@ -353,6 +318,13 @@
*/
/*===========================================================================*/
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
@@ -360,9 +332,7 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
-#endif
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
/**
* @brief Debug option, parameters checks.
@@ -371,9 +341,7 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS FALSE
-#endif
+#define CH_DBG_ENABLE_CHECKS FALSE
/**
* @brief Debug option, consistency checks.
@@ -383,20 +351,22 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS FALSE
-#endif
+#define CH_DBG_ENABLE_ASSERTS FALSE
/**
* @brief Debug option, trace buffer.
- * @details If enabled then the context switch circular trace buffer is
- * activated.
+ * @details If enabled then the trace buffer is activated.
*
- * @note The default is @p FALSE.
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
-#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE FALSE
-#endif
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL
+
+/**
+ * @brief Trace buffer entries.
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#define CH_DBG_TRACE_BUFFER_SIZE 128
/**
* @brief Debug option, stack checks.
@@ -408,9 +378,7 @@
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
-#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
-#endif
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
/**
* @brief Debug option, stacks initialization.
@@ -420,22 +388,18 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS TRUE
-#endif
+#define CH_DBG_FILL_THREADS TRUE
/**
* @brief Debug option, threads profiling.
- * @details If enabled then a field is added to the @p Thread structure that
+ * @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
- * @note The default is @p TRUE.
- * @note This debug option is defaulted to TRUE because it is required by
- * some test cases into the test suite.
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
*/
-#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
-#define CH_DBG_THREADS_PROFILING FALSE
-#endif
+#define CH_DBG_THREADS_PROFILING TRUE
/** @} */
@@ -446,52 +410,22 @@
*/
/*===========================================================================*/
-#include
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This is an optional service that could not be implemented in
- * all HAL implementations.
- * @note This function can be called from any context.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @special
- */
+/*
+ Backwards compat for dRonin
+*/
+#define hal_lld_get_counter_value() DWT->CYCCNT
#define halGetCounterValue() hal_lld_get_counter_value()
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() DWT_CYCCNT
+// typedef uint32_t halrtcnt_t;
/**
* @brief Threads descriptor structure extension.
- * @details User fields added to the end of the @p Thread structure.
+ * @details User fields added to the end of the @p thread_t structure.
*/
-#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
-#define THREAD_EXT_FIELDS \
- halrtcnt_t ticks_switched_in; \
- halrtcnt_t ticks_total; \
- /* Add threads custom fields here.*/
-#endif
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ uint32_t ticks_switched_in; \
+ uint32_t ticks_total; \
+ /* Add threads custom fields here.*//* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
@@ -500,70 +434,99 @@ typedef uint32_t halrtcnt_t;
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
-#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
-#define THREAD_EXT_INIT_HOOK(tp) { \
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
-#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
- *
- * @note It is inserted into lock zone.
- * @note It is also invoked when the threads simply return in order to
- * terminate.
*/
-#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
-#define THREAD_EXT_EXIT_HOOK(tp) { \
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
-#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
-#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
-#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
ntp->ticks_switched_in = halGetCounterValue(); \
otp->ticks_total += ntp->ticks_switched_in - otp->ticks_switched_in; \
/* System halt code here.*/ \
}
-#endif
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+ /* Idle-enter code here.*/ \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+ /* Idle-leave code here.*/ \
+}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
-#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
-#define IDLE_LOOP_HOOK() { \
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
extern void vApplicationIdleHook(void); \
vApplicationIdleHook(); \
}
-#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
-#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
-#define SYSTEM_TICK_EVENT_HOOK() { \
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
-#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
-#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
-#define SYSTEM_HALT_HOOK() { \
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
-#endif
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
/** @} */
@@ -575,11 +538,6 @@ typedef uint32_t halrtcnt_t;
in the project options.*/
#define CORTEX_USE_FPU TRUE
-#endif /* _CHCONF_H_ */
-
-/** @} */
+#endif /* CHCONF_H */
-/**
- * @}
- * @}
- */
+/** @} */
\ No newline at end of file
diff --git a/flight/PiOS/STM32/inc/halconf.h b/flight/PiOS/STM32/inc/halconf.h
index 7e91b654d3..793c4ebaf3 100644
--- a/flight/PiOS/STM32/inc/halconf.h
+++ b/flight/PiOS/STM32/inc/halconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -28,18 +28,14 @@
* @{
*/
-#ifndef _HALCONF_H_
-#define _HALCONF_H_
+#ifndef HALCONF_H
+#define HALCONF_H
#include "mcuconf.h"
/**
- * @brief Enables the TM subsystem.
+ * @name Drivers enable switches
*/
-#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
-#define HAL_USE_TM FALSE
-#endif
-
/**
* @brief Enables the PAL subsystem.
*/
@@ -61,6 +57,13 @@
#define HAL_USE_CAN FALSE
#endif
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
/**
* @brief Enables the EXT subsystem.
*/
@@ -82,6 +85,13 @@
#define HAL_USE_I2C FALSE
#endif
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
/**
* @brief Enables the ICU subsystem.
*/
@@ -110,6 +120,13 @@
#define HAL_USE_PWM FALSE
#endif
+/**
+ * @brief Enables the QSPI subsystem.
+ */
+#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
+#define HAL_USE_QSPI FALSE
+#endif
+
/**
* @brief Enables the RTC subsystem.
*/
@@ -159,8 +176,19 @@
#define HAL_USE_USB FALSE
#endif
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+/** @} */
+
/*===========================================================================*/
-/* ADC driver related settings. */
+/**
+ * @name ADC driver related setting
+ * @{
+ */
/*===========================================================================*/
/**
@@ -178,9 +206,13 @@
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
+/** @} */
/*===========================================================================*/
-/* CAN driver related settings. */
+/**
+ * @name CAN driver related setting
+ * @{
+ */
/*===========================================================================*/
/**
@@ -189,9 +221,13 @@
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
+/** @} */
/*===========================================================================*/
-/* I2C driver related settings. */
+/**
+ * @name I2C driver related setting
+ * @{
+ */
/*===========================================================================*/
/**
@@ -200,16 +236,20 @@
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
+/** @} */
/*===========================================================================*/
-/* MAC driver related settings. */
+/**
+ * @name MAC driver related setting
+ * @{
+ */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
-#define MAC_USE_ZERO_COPY FALSE
+#define MAC_USE_ZERO_COPY TRUE
#endif
/**
@@ -218,9 +258,13 @@
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
+/** @} */
/*===========================================================================*/
-/* MMC_SPI driver related settings. */
+/**
+ * @name MMC_SPI driver related setting
+ * @{
+ */
/*===========================================================================*/
/**
@@ -234,9 +278,13 @@
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
+/** @} */
/*===========================================================================*/
-/* SDC driver related settings. */
+/**
+ * @name SDC driver related setting
+ * @{
+ */
/*===========================================================================*/
/**
@@ -253,7 +301,7 @@
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
-#define SDC_MMC_SUPPORT FALSE
+#define SDC_MMC_SUPPORT TRUE
#endif
/**
@@ -265,9 +313,13 @@
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
+/** @} */
/*===========================================================================*/
-/* SERIAL driver related settings. */
+/**
+ * @name SERIAL driver related setting
+ * @{
+ */
/*===========================================================================*/
/**
@@ -283,15 +335,46 @@
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
- * @note The default is 64 bytes for both the transmission and receive
+ * @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SERIAL_USB driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 256 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
+/** @} */
/*===========================================================================*/
-/* SPI driver related settings. */
+/**
+ * @name SPI driver related setting
+ * @{
+ */
/*===========================================================================*/
/**
@@ -309,12 +392,48 @@
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
+/** @} */
-#endif /* _HALCONF_H_ */
+/*===========================================================================*/
+/**
+ * @name UART driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT TRUE
+#endif
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION TRUE
+#endif
/** @} */
+/*===========================================================================*/
/**
- * @}
- * @}
+ * @name USB driver related setting
+ * @{
*/
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT TRUE
+#endif
+/** @} */
+
+#endif /* HALCONF_H */
+
+/** @} */
\ No newline at end of file
diff --git a/flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/stm32f1xx.h b/flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/stm32f1xx.h
new file mode 100644
index 0000000000..bec1c82449
--- /dev/null
+++ b/flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/stm32f1xx.h
@@ -0,0 +1,9 @@
+/*
+ Redirect for ChibiOS
+*/
+#ifndef STM32F1XX_H
+#define STM32F1XX_H
+
+#include "stm32f10x.h"
+
+#endif // STM32F1XX_H
\ No newline at end of file
diff --git a/flight/PiOS/STM32F10x/library_chibios.mk b/flight/PiOS/STM32F10x/library_chibios.mk
index c704ca5a4e..824e5cfb1a 100644
--- a/flight/PiOS/STM32F10x/library_chibios.mk
+++ b/flight/PiOS/STM32F10x/library_chibios.mk
@@ -12,6 +12,12 @@ PIOS_DEVLIB := $(dir $(lastword $(MAKEFILE_LIST)))
#
LINKER_SCRIPTS_APP = $(PIOS_DEVLIB)/sections_chibios.ld
+#
+# ChibiOS settings
+#
+CDEFS += -DCRT1_AREAS_NUMBER=0
+ADEFS += -DCRT0_INIT_RAM_AREAS=FALSE
+
#
# Compiler options implied by the F30x
#
@@ -54,19 +60,31 @@ SRC += $(wildcard $(USBDEVLIB)/src/*.c)
# ChibiOS
CHIBIOS := $(PIOSCOMMONLIB)/ChibiOS
-include $(PIOSCOMMONLIB)/ChibiOS/os/hal/platforms/STM32F1xx/platform.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/hal/hal.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/kernel/kernel.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/platform.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+
+include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+include $(CHIBIOS)/os/rt/rt.mk
SRC += $(PLATFORMSRC)
SRC += $(HALSRC)
SRC += $(PORTSRC)
SRC += $(KERNSRC)
+SRC += $(OSALSRC)
+SRC += $(STARTUPSRC)
+
+ASRC += $(PORTASM)
+ASRC += $(STARTUPASM)
EXTRAINCDIRS += $(PLATFORMINC)
EXTRAINCDIRS += $(HALINC)
EXTRAINCDIRS += $(PORTINC)
EXTRAINCDIRS += $(KERNINC)
+EXTRAINCDIRS += $(OSALINC)
+EXTRAINCDIRS += $(STARTUPINC)
+EXTRAINCDIRS += $(CHIBIOS)/os/license
+EXTRAINCDIRS += $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F1xx/
diff --git a/flight/PiOS/STM32F10x/mcuconf.h b/flight/PiOS/STM32F10x/mcuconf.h
index 41d6995239..d09460a91d 100644
--- a/flight/PiOS/STM32F10x/mcuconf.h
+++ b/flight/PiOS/STM32F10x/mcuconf.h
@@ -1,13 +1,46 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
#define STM32F103_MCUCONF
+/*
+ * HAL driver system settings.
+ */
#define STM32_NO_INIT TRUE
-#define STM32_PVD_ENABLE FALSE
-#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 9
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_ADCPRE STM32_ADCPRE_DIV4
+#define STM32_USB_CLOCK_REQUIRED TRUE
+#define STM32_USBPRE STM32_USBPRE_DIV1P5
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_RTCSEL STM32_RTCSEL_HSEDIV
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+
+#endif // MCUCONF_H
\ No newline at end of file
diff --git a/flight/PiOS/STM32F10x/sections_chibios.ld b/flight/PiOS/STM32F10x/sections_chibios.ld
index 53c6d6bd67..bdea99e299 100644
--- a/flight/PiOS/STM32F10x/sections_chibios.ld
+++ b/flight/PiOS/STM32F10x/sections_chibios.ld
@@ -29,17 +29,17 @@ __ram_start__ = ORIGIN(ram);
__ram_size__ = LENGTH(ram);
__ram_end__ = __ram_start__ + __ram_size__;
-ENTRY(ResetHandler)
+ENTRY(Reset_Handler)
SECTIONS
{
. = 0;
_text = .;
- startup : ALIGN(16) SUBALIGN(16)
+ .vectors : ALIGN(16) SUBALIGN(16)
{
PROVIDE (pios_isr_vector_table_base = .);
- KEEP(*(vectors))
+ KEEP(*(.vectors))
} > flash
constructors : ALIGN(4) SUBALIGN(4)
@@ -60,7 +60,6 @@ SECTIONS
.text : ALIGN(16) SUBALIGN(16)
{
- *(.text.startup.*)
*(.text)
*(.text.*)
*(.rodata)
@@ -143,9 +142,9 @@ SECTIONS
{
PROVIDE(_cmm_start = .);
. = ALIGN(4);
- *(.bss.mainthread.*)
+ *(.bss.ch)
. = ALIGN(4);
- *(.bss._idle_thread_wa)
+ *(.bss.ch_idle_thread_wa)
. = ALIGN(4);
*(.bss.rlist)
. = ALIGN(4);
@@ -164,6 +163,8 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE(_data = .);
+ _textdata_start = LOADADDR(.data);
+ _data_start = .;
*(.data)
. = ALIGN(4);
*(.data.*)
@@ -171,6 +172,7 @@ SECTIONS
*(.ramtext)
. = ALIGN(4);
PROVIDE(_edata = .);
+ _data_end = .;
} > ram AT > flash
.bss (NOLOAD) :
@@ -208,5 +210,5 @@ SECTIONS
PROVIDE(end = .);
_end = .;
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
+__heap_base__ = _sheap;
+__heap_end__ = _eheap;
diff --git a/flight/PiOS/STM32F30x/Libraries/CMSIS3/Device/ST/STM32F30x/Include/stm32f3xx.h b/flight/PiOS/STM32F30x/Libraries/CMSIS3/Device/ST/STM32F30x/Include/stm32f3xx.h
new file mode 100644
index 0000000000..c537c4b0cd
--- /dev/null
+++ b/flight/PiOS/STM32F30x/Libraries/CMSIS3/Device/ST/STM32F30x/Include/stm32f3xx.h
@@ -0,0 +1,9 @@
+/*
+ Redirect for ChibiOS.
+*/
+#ifndef STM32F3XX_H
+#define STM32F3XX_H
+
+#include "stm32f30x.h"
+
+#endif // STM32F3XX_H
diff --git a/flight/PiOS/STM32F30x/Libraries/ChibiOS/library.mk b/flight/PiOS/STM32F30x/Libraries/ChibiOS/library.mk
index da08498cd1..d1bd1ac5d5 100644
--- a/flight/PiOS/STM32F30x/Libraries/ChibiOS/library.mk
+++ b/flight/PiOS/STM32F30x/Libraries/ChibiOS/library.mk
@@ -8,18 +8,30 @@
# ChibiOS
CHIBIOS := $(PIOSCOMMONLIB)/ChibiOS
-include $(PIOSCOMMONLIB)/ChibiOS/os/hal/platforms/STM32F30x/platform.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/hal/hal.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/ports/GCC/ARMCMx/STM32F3xx/port.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/kernel/kernel.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+
+include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+include $(CHIBIOS)/os/rt/rt.mk
SRC += $(PLATFORMSRC)
SRC += $(HALSRC)
SRC += $(PORTSRC)
SRC += $(KERNSRC)
+SRC += $(OSALSRC)
+SRC += $(STARTUPSRC)
+
+ASRC += $(PORTASM)
+ASRC += $(STARTUPASM)
EXTRAINCDIRS += $(PLATFORMINC)
EXTRAINCDIRS += $(HALINC)
EXTRAINCDIRS += $(PORTINC)
EXTRAINCDIRS += $(KERNINC)
+EXTRAINCDIRS += $(OSALINC)
+EXTRAINCDIRS += $(STARTUPINC)
+EXTRAINCDIRS += $(CHIBIOS)/os/license
+EXTRAINCDIRS += $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F3xx/
diff --git a/flight/PiOS/STM32F30x/inc/mcuconf.h b/flight/PiOS/STM32F30x/inc/mcuconf.h
index 6a1a56a1d7..872cd7f8a7 100644
--- a/flight/PiOS/STM32F30x/inc/mcuconf.h
+++ b/flight/PiOS/STM32F30x/inc/mcuconf.h
@@ -39,7 +39,7 @@
* 0...3 Lowest...Highest.
*/
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
/*
* HAL driver system settings.
diff --git a/flight/PiOS/STM32F30x/library_chibios.mk b/flight/PiOS/STM32F30x/library_chibios.mk
index c3bfa8acc1..3137ae30c6 100644
--- a/flight/PiOS/STM32F30x/library_chibios.mk
+++ b/flight/PiOS/STM32F30x/library_chibios.mk
@@ -12,6 +12,12 @@ PIOS_DEVLIB := $(dir $(lastword $(MAKEFILE_LIST)))
#
LINKER_SCRIPTS_APP = $(PIOS_DEVLIB)/sections_chibios.ld
+#
+# ChibiOS settings
+#
+CDEFS += -DCRT1_AREAS_NUMBER=0
+ADEFS += -DCRT0_INIT_RAM_AREAS=FALSE
+
#
# Compiler options implied by the F30x
#
diff --git a/flight/PiOS/STM32F30x/pios_usb_hid_istr.c b/flight/PiOS/STM32F30x/pios_usb_hid_istr.c
index 14d2ad0206..ac1f9e4b48 100644
--- a/flight/PiOS/STM32F30x/pios_usb_hid_istr.c
+++ b/flight/PiOS/STM32F30x/pios_usb_hid_istr.c
@@ -46,7 +46,11 @@ EP1_OUT_Callback, EP2_OUT_Callback, EP3_OUT_Callback, EP4_OUT_Callback, EP5_OUT_
* Output :
* Return :
*******************************************************************************/
+#if STM32_HAS_USB
+void USB_LP_IRQHandler(void) //USB_Istr(void)
+#else
void USB_LP_CAN1_RX0_IRQHandler(void) //USB_Istr(void)
+#endif
{
PIOS_IRQ_Prologue();
diff --git a/flight/PiOS/STM32F30x/sections_chibios.ld b/flight/PiOS/STM32F30x/sections_chibios.ld
index e331e2d643..87370916a8 100644
--- a/flight/PiOS/STM32F30x/sections_chibios.ld
+++ b/flight/PiOS/STM32F30x/sections_chibios.ld
@@ -29,17 +29,17 @@ __ram_start__ = ORIGIN(ram);
__ram_size__ = LENGTH(ram);
__ram_end__ = __ram_start__ + __ram_size__;
-ENTRY(ResetHandler)
+ENTRY(Reset_Handler)
SECTIONS
{
. = 0;
_text = .;
- startup : ALIGN(16) SUBALIGN(16)
+ .vectors : ALIGN(16) SUBALIGN(16)
{
PROVIDE (pios_isr_vector_table_base = .);
- KEEP(*(vectors))
+ KEEP(*(.vectors))
} > flash
constructors : ALIGN(4) SUBALIGN(4)
@@ -60,7 +60,6 @@ SECTIONS
.text : ALIGN(16) SUBALIGN(16)
{
- *(.text.startup.*)
*(.text)
*(.text.*)
*(.rodata)
@@ -184,6 +183,8 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE(_data = .);
+ _textdata_start = LOADADDR(.data);
+ _data_start = .;
*(.data)
. = ALIGN(4);
*(.data.*)
@@ -191,6 +192,7 @@ SECTIONS
*(.ramtext)
. = ALIGN(4);
PROVIDE(_edata = .);
+ _data_end = .;
} > ram AT > flash
.bss (NOLOAD) :
@@ -228,5 +230,5 @@ SECTIONS
PROVIDE(end = .);
_end = .;
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
+__heap_base__ = _sheap;
+__heap_end__ = _eheap;
diff --git a/flight/PiOS/STM32F4xx/Libraries/ChibiOS/library.mk b/flight/PiOS/STM32F4xx/Libraries/ChibiOS/library.mk
index 0270ccdd35..22e9821438 100644
--- a/flight/PiOS/STM32F4xx/Libraries/ChibiOS/library.mk
+++ b/flight/PiOS/STM32F4xx/Libraries/ChibiOS/library.mk
@@ -8,18 +8,30 @@
# ChibiOS
CHIBIOS := $(PIOSCOMMONLIB)/ChibiOS
-include $(PIOSCOMMONLIB)/ChibiOS/os/hal/platforms/STM32F4xx/platform.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/hal/hal.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
-include $(PIOSCOMMONLIB)/ChibiOS/os/kernel/kernel.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+
+include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+include $(CHIBIOS)/os/rt/rt.mk
SRC += $(PLATFORMSRC)
SRC += $(HALSRC)
SRC += $(PORTSRC)
SRC += $(KERNSRC)
+SRC += $(OSALSRC)
+SRC += $(STARTUPSRC)
+
+ASRC += $(PORTASM)
+ASRC += $(STARTUPASM)
EXTRAINCDIRS += $(PLATFORMINC)
EXTRAINCDIRS += $(HALINC)
EXTRAINCDIRS += $(PORTINC)
EXTRAINCDIRS += $(KERNINC)
+EXTRAINCDIRS += $(OSALINC)
+EXTRAINCDIRS += $(STARTUPINC)
+EXTRAINCDIRS += $(CHIBIOS)/os/license
+EXTRAINCDIRS += $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F4xx/
diff --git a/flight/PiOS/STM32F4xx/library_chibios.mk b/flight/PiOS/STM32F4xx/library_chibios.mk
index 5e436e21b9..e324ee1e0d 100644
--- a/flight/PiOS/STM32F4xx/library_chibios.mk
+++ b/flight/PiOS/STM32F4xx/library_chibios.mk
@@ -10,7 +10,7 @@ PIOS_DEVLIB := $(dir $(lastword $(MAKEFILE_LIST)))
#
# Linker script depending on STM32 type
#
-ifneq "$(findstring STM32F40_41xxx,$(STM32_TYPE))" ""
+ifneq "$(findstring STM32F405xx,$(STM32_TYPE))" ""
LINKER_SCRIPTS_APP = $(PIOS_DEVLIB)/sections_chibios.ld
else ifneq "$(findstring STM32F446xx,$(STM32_TYPE))" ""
LINKER_SCRIPTS_APP = $(PIOS_DEVLIB)/sections_chibios_STM32F446xx.ld
@@ -18,6 +18,11 @@ else
$(error No linker script found for $(STM32_TYPE))
endif
+#
+# ChibiOS settings
+#
+CDEFS += -DCRT1_AREAS_NUMBER=0
+ADEFS += -DCRT0_INIT_RAM_AREAS=FALSE
#
# Compiler options implied by the F4xx
diff --git a/flight/PiOS/STM32F4xx/sections_chibios.ld b/flight/PiOS/STM32F4xx/sections_chibios.ld
index f264893303..8c8f5093eb 100644
--- a/flight/PiOS/STM32F4xx/sections_chibios.ld
+++ b/flight/PiOS/STM32F4xx/sections_chibios.ld
@@ -29,17 +29,17 @@ __ram_start__ = ORIGIN(ram);
__ram_size__ = LENGTH(ram);
__ram_end__ = __ram_start__ + __ram_size__;
-ENTRY(ResetHandler)
+ENTRY(Reset_Handler)
SECTIONS
{
. = 0;
_text = .;
- startup : ALIGN(16) SUBALIGN(16)
+ .vectors : ALIGN(16) SUBALIGN(16)
{
PROVIDE (pios_isr_vector_table_base = .);
- KEEP(*(vectors))
+ KEEP(*(.vectors))
} > flash
constructors : ALIGN(4) SUBALIGN(4)
@@ -60,7 +60,6 @@ SECTIONS
.text : ALIGN(16) SUBALIGN(16)
{
- *(.text.startup.*)
*(.text)
*(.text.*)
*(.rodata)
@@ -143,9 +142,9 @@ SECTIONS
{
PROVIDE(_cmm_start = .);
. = ALIGN(4);
- *(.bss.mainthread.*)
+ *(.bss.ch)
. = ALIGN(4);
- *(.bss._idle_thread_wa)
+ *(.bss.ch_idle_thread_wa)
. = ALIGN(4);
*(.bss.rlist)
. = ALIGN(4);
@@ -184,6 +183,8 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE(_data = .);
+ _textdata_start = LOADADDR(.data);
+ _data_start = .;
*(.data)
. = ALIGN(4);
*(.data.*)
@@ -191,6 +192,7 @@ SECTIONS
*(.ramtext)
. = ALIGN(4);
PROVIDE(_edata = .);
+ _data_end = .;
} > ram AT > flash
.bss (NOLOAD) :
@@ -228,5 +230,5 @@ SECTIONS
PROVIDE(end = .);
_end = .;
-__heap_base__ = _end;
-__heap_end__ = __ram_end__;
+__heap_base__ = _sheap;
+__heap_end__ = _eheap;
diff --git a/flight/PiOS/STM32F4xx/sections_chibios_STM32F446xx.ld b/flight/PiOS/STM32F4xx/sections_chibios_STM32F446xx.ld
index 9bb2b52b08..016c42bb8d 100644
--- a/flight/PiOS/STM32F4xx/sections_chibios_STM32F446xx.ld
+++ b/flight/PiOS/STM32F4xx/sections_chibios_STM32F446xx.ld
@@ -29,17 +29,17 @@ __ram_start__ = ORIGIN(ram);
__ram_size__ = LENGTH(ram);
__ram_end__ = __ram_start__ + __ram_size__;
-ENTRY(ResetHandler)
+ENTRY(Reset_Handler)
SECTIONS
{
. = 0;
_text = .;
- startup : ALIGN(16) SUBALIGN(16)
+ .vectors : ALIGN(16) SUBALIGN(16)
{
PROVIDE (pios_isr_vector_table_base = .);
- KEEP(*(vectors))
+ KEEP(*(.vectors))
} > flash
constructors : ALIGN(4) SUBALIGN(4)
@@ -60,7 +60,6 @@ SECTIONS
.text : ALIGN(16) SUBALIGN(16)
{
- *(.text.startup.*)
*(.text)
*(.text.*)
*(.rodata)
@@ -143,6 +142,8 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE(_data = .);
+ _textdata_start = LOADADDR(.data);
+ _data_start = .;
*(.data)
. = ALIGN(4);
*(.data.*)
@@ -150,6 +151,7 @@ SECTIONS
*(.ramtext)
. = ALIGN(4);
PROVIDE(_edata = .);
+ _data_end = .;
} > ram AT > flash
.bss (NOLOAD) :
@@ -187,7 +189,7 @@ SECTIONS
PROVIDE(end = .);
_end = .;
-__heap_base__ = _end;
+__heap_base__ = .;
__heap_end__ = __ram_end__;
/* confirmed that fill32 does the right thing when start == end.
diff --git a/flight/PiOS/inc/pios_thread.h b/flight/PiOS/inc/pios_thread.h
index ccd1a96876..048a76865e 100644
--- a/flight/PiOS/inc/pios_thread.h
+++ b/flight/PiOS/inc/pios_thread.h
@@ -47,7 +47,7 @@ enum pios_thread_prio_e
PIOS_THREAD_PRIO_HIGHEST = HIGHPRIO,
};
-#define PIOS_THREAD_STACK_SIZE_MIN THD_WA_SIZE(256 + PORT_INT_REQUIRED_STACK)
+#define PIOS_THREAD_STACK_SIZE_MIN THD_WORKING_AREA_SIZE(256 + PORT_INT_REQUIRED_STACK)
#else
diff --git a/flight/targets/aq32/fw/Makefile b/flight/targets/aq32/fw/Makefile
index 892f2f5f74..5f2af0ebdd 100644
--- a/flight/targets/aq32/fw/Makefile
+++ b/flight/targets/aq32/fw/Makefile
@@ -183,6 +183,9 @@ CDEFS += -DARM_MATH_ROUNDING
CDEFS += -D__FPU_PRESENT=1
CDEFS += -DUNALIGNED_SUPPORT_DISABLE
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
# Debugging format.
DEBUGF = dwarf-2
@@ -210,7 +213,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/bl/f4/Makefile b/flight/targets/bl/f4/Makefile
index 4fb84e47cd..d673f43334 100644
--- a/flight/targets/bl/f4/Makefile
+++ b/flight/targets/bl/f4/Makefile
@@ -70,7 +70,7 @@ SRC += pios_usbhook.c
SRC += startup.c
SRC += vectors_stm32f4xx.c
-ifneq "$(findstring STM32F40_41xxx,$(STM32_TYPE))" ""
+ifneq "$(findstring STM32F405xx,$(STM32_TYPE))" ""
LINKER_SCRIPTS_BL = $(PIOS_DEVLIB)/link_STM32F4xx_BL_memory.ld \
$(PIOS_DEVLIB)/link_STM32F4xx_sections.ld
else ifneq "$(findstring STM32F446xx,$(STM32_TYPE))" ""
@@ -139,6 +139,9 @@ ADEFS = -D__ASSEMBLY__
#
# Flags for C and C++ (arm-elf-gcc/arm-elf-g++)
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -gdwarf-2
CFLAGS += -Os -fconserve-stack
diff --git a/flight/targets/brain/fw/Makefile b/flight/targets/brain/fw/Makefile
index 621168a639..b6b71d9959 100644
--- a/flight/targets/brain/fw/Makefile
+++ b/flight/targets/brain/fw/Makefile
@@ -187,6 +187,9 @@ CDEFS += -DARM_MATH_ROUNDING
CDEFS += -D__FPU_PRESENT=1
CDEFS += -DUNALIGNED_SUPPORT_DISABLE
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
# Debugging format.
DEBUGF = dwarf-2
@@ -214,7 +217,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/brainre1/fw/Makefile b/flight/targets/brainre1/fw/Makefile
index 892e902b2d..2371ba311a 100644
--- a/flight/targets/brainre1/fw/Makefile
+++ b/flight/targets/brainre1/fw/Makefile
@@ -188,6 +188,9 @@ CDEFS += -DARM_MATH_ROUNDING
CDEFS += -D__FPU_PRESENT=1
CDEFS += -DUNALIGNED_SUPPORT_DISABLE
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
# Debugging format.
DEBUGF = dwarf-2
@@ -215,7 +218,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/bu/f4/Makefile b/flight/targets/bu/f4/Makefile
index 5be9e208bf..29f00b7f80 100644
--- a/flight/targets/bu/f4/Makefile
+++ b/flight/targets/bu/f4/Makefile
@@ -86,6 +86,9 @@ PAYLOAD_FILE = $(ROOT_DIR)/build/bl_$(BOARD_NAME)/bl_$(BOARD_NAME).bin
# Place project-specific -D (define) and/or
# -U options for C here.
CDEFS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CDEFS += -D$(STM32_SUBTYPE)
+endif
CDEFS += -DSYSCLK_FREQ=$(SYSCLK_FREQ)
CDEFS += -DMEM_SIZE=$(FW_BANK_SIZE)
CDEFS += -DUSE_$(BOARD)
@@ -155,7 +158,7 @@ LDFLAGS += -Wl,--warn-common
LDFLAGS += -Wl,--fatal-warnings
# Linker scripts
-ifneq "$(findstring STM32F40_41xxx,$(STM32_TYPE))" ""
+ifneq "$(findstring STM32F405xx,$(STM32_TYPE))" ""
LINKER_SCRIPTS_APP = $(PIOS_DEVLIB)/link_STM32F4xx_OP_memory.ld \
$(PIOS_DEVLIB)/link_STM32F4xx_sections.ld
else ifneq "$(findstring STM32F446xx,$(STM32_TYPE))" ""
diff --git a/flight/targets/dtfc/board-info/board_hw_defs.c b/flight/targets/dtfc/board-info/board_hw_defs.c
index 626230eae3..c52f12551d 100644
--- a/flight/targets/dtfc/board-info/board_hw_defs.c
+++ b/flight/targets/dtfc/board-info/board_hw_defs.c
@@ -793,7 +793,11 @@ static const struct pios_internal_adc_cfg internal_adc_cfg = {
static const struct pios_usb_cfg pios_usb_main_cfg = {
.irq = {
.init = {
+#if STM32_HAS_USB
+ .NVIC_IRQChannel = USB_LP_IRQn,
+#else
.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn,
+#endif
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
diff --git a/flight/targets/dtfc/fw/Makefile b/flight/targets/dtfc/fw/Makefile
index aea6f73c76..3888fcadfa 100644
--- a/flight/targets/dtfc/fw/Makefile
+++ b/flight/targets/dtfc/fw/Makefile
@@ -180,7 +180,10 @@ CDEFS += -DUNALIGNED_SUPPORT_DISABLE
# This is not the best place for these. Really should abstract out
# to the board file or something
-CFLAGS += -DSTM32F30X
+CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -DMEM_SIZE=$(FW_BANK_SIZE)
# Debugging format.
@@ -211,7 +214,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/lux/board-info/board_hw_defs.c b/flight/targets/lux/board-info/board_hw_defs.c
index 2fc19f96d7..b41467769c 100644
--- a/flight/targets/lux/board-info/board_hw_defs.c
+++ b/flight/targets/lux/board-info/board_hw_defs.c
@@ -810,7 +810,11 @@ static const struct pios_internal_adc_cfg internal_adc_cfg = {
static const struct pios_usb_cfg pios_usb_main_cfg = {
.irq = {
.init = {
+#if STM32_HAS_USB
+ .NVIC_IRQChannel = USB_LP_IRQn,
+#else
.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn,
+#endif
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
diff --git a/flight/targets/lux/fw/Makefile b/flight/targets/lux/fw/Makefile
index d7ce8b3a24..a392d31fb7 100644
--- a/flight/targets/lux/fw/Makefile
+++ b/flight/targets/lux/fw/Makefile
@@ -180,7 +180,10 @@ CDEFS += -DUNALIGNED_SUPPORT_DISABLE
# This is not the best place for these. Really should abstract out
# to the board file or something
-CFLAGS += -DSTM32F30X
+CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -DMEM_SIZE=$(FW_BANK_SIZE)
# Debugging format.
@@ -211,7 +214,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/omnibusf3/board-info/board_hw_defs.c b/flight/targets/omnibusf3/board-info/board_hw_defs.c
index 8f07df2a21..eb3abfa360 100644
--- a/flight/targets/omnibusf3/board-info/board_hw_defs.c
+++ b/flight/targets/omnibusf3/board-info/board_hw_defs.c
@@ -822,7 +822,11 @@ static const struct pios_internal_adc_cfg internal_adc1_cfg = {
static const struct pios_usb_cfg pios_usb_main_cfg = {
.irq = {
.init = {
+#if STM32_HAS_USB
+ .NVIC_IRQChannel = USB_LP_IRQn,
+#else
.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn,
+#endif
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
diff --git a/flight/targets/omnibusf3/fw/Makefile b/flight/targets/omnibusf3/fw/Makefile
index e4a0fdc096..507ef320fc 100644
--- a/flight/targets/omnibusf3/fw/Makefile
+++ b/flight/targets/omnibusf3/fw/Makefile
@@ -182,7 +182,10 @@ CDEFS += -DUNALIGNED_SUPPORT_DISABLE
# This is not the best place for these. Really should abstract out
# to the board file or something
-CFLAGS += -DSTM32F30X
+CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -DMEM_SIZE=$(FW_BANK_SIZE)
# Debugging format.
@@ -213,7 +216,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/pikoblx/board-info/board_hw_defs.c b/flight/targets/pikoblx/board-info/board_hw_defs.c
index faf18abe00..544002c5cf 100644
--- a/flight/targets/pikoblx/board-info/board_hw_defs.c
+++ b/flight/targets/pikoblx/board-info/board_hw_defs.c
@@ -889,7 +889,11 @@ static const struct pios_internal_adc_cfg internal_adc_cfg = {
static const struct pios_usb_cfg pios_usb_main_cfg = {
.irq = {
.init = {
+#if STM32_HAS_USB
+ .NVIC_IRQChannel = USB_LP_IRQn,
+#else
.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn,
+#endif
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
diff --git a/flight/targets/pikoblx/fw/Makefile b/flight/targets/pikoblx/fw/Makefile
index a328dbc4e1..49831f5ad2 100644
--- a/flight/targets/pikoblx/fw/Makefile
+++ b/flight/targets/pikoblx/fw/Makefile
@@ -184,7 +184,10 @@ CDEFS += -DUNALIGNED_SUPPORT_DISABLE
# This is not the best place for these. Really should abstract out
# to the board file or something
-CFLAGS += -DSTM32F30X
+CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -DMEM_SIZE=$(FW_BANK_SIZE)
# Debugging format.
@@ -215,7 +218,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/pipxtreme/board-info/cmsis_system.c b/flight/targets/pipxtreme/board-info/cmsis_system.c
index cb43469ff2..55022258db 100644
--- a/flight/targets/pipxtreme/board-info/cmsis_system.c
+++ b/flight/targets/pipxtreme/board-info/cmsis_system.c
@@ -67,6 +67,7 @@
*/
#include "stm32f10x.h"
+#include "pios_config.h"
/**
* @}
@@ -152,6 +153,10 @@
/*******************************************************************************
* Clock Definitions
*******************************************************************************/
+#if defined(PIOS_INCLUDE_CHIBIOS)
+ /* ChibiOS supplies and inits this via HAL. */
+ extern uint32_t SystemCoreClock;
+#else
#ifdef SYSCLK_FREQ_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_24MHz
@@ -167,6 +172,7 @@
#else /*!< HSI Selected as System Clock source */
uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
#endif
+#endif // defined(PIOS_INCLUDE_CHIBIOS)
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
diff --git a/flight/targets/pipxtreme/fw/Makefile b/flight/targets/pipxtreme/fw/Makefile
index 628dcddcf9..98a3861176 100644
--- a/flight/targets/pipxtreme/fw/Makefile
+++ b/flight/targets/pipxtreme/fw/Makefile
@@ -262,7 +262,7 @@ CDEFS += $(foreach MOD, $(notdir $(MODULES)), -DMODULE_$(MOD)_BUILTIN)
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/pipxtreme/fw/chconf.h b/flight/targets/pipxtreme/fw/chconf.h
index 06d947b98b..da9dc3532f 100644
--- a/flight/targets/pipxtreme/fw/chconf.h
+++ b/flight/targets/pipxtreme/fw/chconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,34 +15,63 @@
*/
/**
- * @file templates/chconf.h
- * @brief Configuration file template.
- * @details A copy of this file must be placed in each project directory, it
- * contains the application specific kernel settings.
+ * @addtogroup PIOS PIOS Core hardware abstraction layer
+ * @{
+ * @addtogroup ChibiOS ChibiOS Interface
+ * @{
+ *
+ * @file PiOS/inc/chconf.h
+ * @brief Configuration file
+ * @details Generic chconf.h file for flight targets
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
-#ifndef _CHCONF_H_
-#define _CHCONF_H_
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_RT_CONF_
/*===========================================================================*/
/**
- * @name Kernel parameters and options
+ * @name System timers settings
* @{
*/
/*===========================================================================*/
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
-#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
-#define CH_FREQUENCY 1000
-#endif
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
/**
* @brief Round robin interval.
@@ -51,13 +80,12 @@
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
- *
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
*/
-#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
-#define CH_TIME_QUANTUM 1
-#endif
+#define CH_CFG_TIME_QUANTUM 1
/**
* @brief Managed RAM size.
@@ -68,28 +96,18 @@
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
- * @note Requires @p CH_USE_MEMCORE.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
*/
-#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
-#define CH_MEMCORE_SIZE 0
-#endif
+#define CH_CFG_MEMCORE_SIZE 0
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
- * does not spawn the idle thread automatically. The application has
- * then the responsibility to do one of the following:
- * - Spawn a custom idle thread at priority @p IDLEPRIO.
- * - Change the main() thread priority to @p IDLEPRIO then enter
- * an endless loop. In this scenario the @p main() thread acts as
- * the idle thread.
- * .
- * @note Unless an idle thread is spawned the @p main() thread must not
- * enter a sleep state.
- */
-#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
-#define CH_NO_IDLE_THREAD FALSE
-#endif
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
/** @} */
@@ -108,9 +126,7 @@
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
-#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
-#define CH_OPTIMIZE_SPEED FALSE
-#endif
+#define CH_CFG_OPTIMIZE_SPEED FALSE
/** @} */
@@ -121,15 +137,22 @@
*/
/*===========================================================================*/
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
-#define CH_USE_REGISTRY TRUE
-#endif
+#define CH_CFG_USE_REGISTRY TRUE
/**
* @brief Threads synchronization APIs.
@@ -138,9 +161,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
-#define CH_USE_WAITEXIT TRUE
-#endif
+#define CH_CFG_USE_WAITEXIT TRUE
/**
* @brief Semaphores APIs.
@@ -148,43 +169,36 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
-#define CH_USE_SEMAPHORES TRUE
-#endif
+#define CH_CFG_USE_SEMAPHORES TRUE
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
- * @note The default is @p FALSE. Enable this if you have special requirements.
- * @note Requires @p CH_USE_SEMAPHORES.
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
-#define CH_USE_SEMAPHORES_PRIORITY FALSE
-#endif
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
/**
- * @brief Atomic semaphore API.
- * @details If enabled then the semaphores the @p chSemSignalWait() API
- * is included in the kernel.
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
-#define CH_USE_SEMSW TRUE
-#endif
+#define CH_CFG_USE_MUTEXES TRUE
/**
- * @brief Mutexes APIs.
- * @details If enabled then the mutexes APIs are included in the kernel.
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
*
- * @note The default is @p TRUE.
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
*/
-#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
-#define CH_USE_MUTEXES TRUE
-#endif
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
/**
* @brief Conditional Variables APIs.
@@ -192,11 +206,9 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_MUTEXES.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
*/
-#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
-#define CH_USE_CONDVARS FALSE
-#endif
+#define CH_CFG_USE_CONDVARS FALSE
/**
* @brief Conditional Variables APIs with timeout.
@@ -204,11 +216,9 @@
* specification are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_CONDVARS.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
*/
-#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
-#define CH_USE_CONDVARS_TIMEOUT FALSE
-#endif
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
/**
* @brief Events Flags APIs.
@@ -216,9 +226,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
-#define CH_USE_EVENTS FALSE
-#endif
+#define CH_CFG_USE_EVENTS TRUE
/**
* @brief Events Flags APIs with timeout.
@@ -226,11 +234,9 @@
* are included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_EVENTS.
+ * @note Requires @p CH_CFG_USE_EVENTS.
*/
-#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
-#define CH_USE_EVENTS_TIMEOUT FALSE
-#endif
+#define CH_CFG_USE_EVENTS_TIMEOUT FALSE
/**
* @brief Synchronous Messages APIs.
@@ -239,21 +245,18 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
-#define CH_USE_MESSAGES FALSE
-#endif
+#define CH_CFG_USE_MESSAGES FALSE
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
- * @note The default is @p FALSE. Enable this if you have special requirements.
- * @note Requires @p CH_USE_MESSAGES.
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
*/
-#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
-#define CH_USE_MESSAGES_PRIORITY FALSE
-#endif
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
/**
* @brief Mailboxes APIs.
@@ -261,21 +264,9 @@
* included in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_SEMAPHORES.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
-#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
-#define CH_USE_MAILBOXES TRUE
-#endif
-
-/**
- * @brief I/O Queues APIs.
- * @details If enabled then the I/O queues APIs are included in the kernel.
- *
- * @note The default is @p TRUE.
- */
-#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
-#define CH_USE_QUEUES FALSE
-#endif
+#define CH_CFG_USE_MAILBOXES TRUE
/**
* @brief Core Memory Manager APIs.
@@ -284,9 +275,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
-#define CH_USE_MEMCORE FALSE
-#endif
+#define CH_CFG_USE_MEMCORE TRUE
/**
* @brief Heap Allocator APIs.
@@ -294,27 +283,11 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
- * @p CH_USE_SEMAPHORES.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
-#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
-#define CH_USE_HEAP FALSE
-#endif
-
-/**
- * @brief C-runtime allocator.
- * @details If enabled the the heap allocator APIs just wrap the C-runtime
- * @p malloc() and @p free() functions.
- *
- * @note The default is @p FALSE.
- * @note Requires @p CH_USE_HEAP.
- * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
- * appropriate documentation.
- */
-#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
-#define CH_USE_MALLOC_HEAP FALSE
-#endif
+#define CH_CFG_USE_HEAP FALSE
/**
* @brief Memory Pools Allocator APIs.
@@ -323,9 +296,7 @@
*
* @note The default is @p TRUE.
*/
-#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
-#define CH_USE_MEMPOOLS TRUE
-#endif
+#define CH_CFG_USE_MEMPOOLS TRUE
/**
* @brief Dynamic Threads APIs.
@@ -333,12 +304,10 @@
* in the kernel.
*
* @note The default is @p TRUE.
- * @note Requires @p CH_USE_WAITEXIT.
- * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
-#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
-#define CH_USE_DYNAMIC FALSE
-#endif
+#define CH_CFG_USE_DYNAMIC FALSE
/** @} */
@@ -349,6 +318,13 @@
*/
/*===========================================================================*/
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
@@ -356,9 +332,7 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
-#endif
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
/**
* @brief Debug option, parameters checks.
@@ -367,9 +341,7 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS FALSE
-#endif
+#define CH_DBG_ENABLE_CHECKS FALSE
/**
* @brief Debug option, consistency checks.
@@ -379,20 +351,22 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS FALSE
-#endif
+#define CH_DBG_ENABLE_ASSERTS FALSE
/**
* @brief Debug option, trace buffer.
- * @details If enabled then the context switch circular trace buffer is
- * activated.
+ * @details If enabled then the trace buffer is activated.
*
- * @note The default is @p FALSE.
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL
+
+/**
+ * @brief Trace buffer entries.
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
*/
-#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE FALSE
-#endif
+#define CH_DBG_TRACE_BUFFER_SIZE 128
/**
* @brief Debug option, stack checks.
@@ -404,9 +378,7 @@
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
-#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
-#endif
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
/**
* @brief Debug option, stacks initialization.
@@ -416,22 +388,18 @@
*
* @note The default is @p FALSE.
*/
-#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS TRUE
-#endif
+#define CH_DBG_FILL_THREADS TRUE
/**
* @brief Debug option, threads profiling.
- * @details If enabled then a field is added to the @p Thread structure that
+ * @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
- * @note The default is @p TRUE.
- * @note This debug option is defaulted to TRUE because it is required by
- * some test cases into the test suite.
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
*/
-#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
-#define CH_DBG_THREADS_PROFILING FALSE
-#endif
+#define CH_DBG_THREADS_PROFILING TRUE
/** @} */
@@ -442,52 +410,22 @@
*/
/*===========================================================================*/
-#include
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This is an optional service that could not be implemented in
- * all HAL implementations.
- * @note This function can be called from any context.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @special
- */
+/*
+ Backwards compat for dRonin
+*/
#define halGetCounterValue() hal_lld_get_counter_value()
+#define hal_lld_get_counter_value() DWT->CYCCNT
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() DWT_CYCCNT
+// typedef uint32_t halrtcnt_t;
/**
* @brief Threads descriptor structure extension.
- * @details User fields added to the end of the @p Thread structure.
+ * @details User fields added to the end of the @p thread_t structure.
*/
-#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
-#define THREAD_EXT_FIELDS \
- halrtcnt_t ticks_switched_in; \
- halrtcnt_t ticks_total; \
- /* Add threads custom fields here.*/
-#endif
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ uint32_t ticks_switched_in; \
+ uint32_t ticks_total; \
+ /* Add threads custom fields here.*//* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
@@ -496,70 +434,99 @@ typedef uint32_t halrtcnt_t;
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
-#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
-#define THREAD_EXT_INIT_HOOK(tp) { \
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
-#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
- *
- * @note It is inserted into lock zone.
- * @note It is also invoked when the threads simply return in order to
- * terminate.
*/
-#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
-#define THREAD_EXT_EXIT_HOOK(tp) { \
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
-#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
-#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
-#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
ntp->ticks_switched_in = halGetCounterValue(); \
otp->ticks_total += ntp->ticks_switched_in - otp->ticks_switched_in; \
/* System halt code here.*/ \
}
-#endif
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+ /* Idle-enter code here.*/ \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+ /* Idle-leave code here.*/ \
+}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
-#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
-#define IDLE_LOOP_HOOK() { \
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
extern void vApplicationIdleHook(void); \
vApplicationIdleHook(); \
}
-#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
-#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
-#define SYSTEM_TICK_EVENT_HOOK() { \
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
-#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
-#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
-#define SYSTEM_HALT_HOOK() { \
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
-#endif
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
/** @} */
@@ -567,6 +534,6 @@ typedef uint32_t halrtcnt_t;
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
-#endif /* _CHCONF_H_ */
+#endif /* CHCONF_H */
-/** @} */
+/** @} */
\ No newline at end of file
diff --git a/flight/targets/playuavosd/fw/Makefile b/flight/targets/playuavosd/fw/Makefile
index b300f8b8f0..adf64f4c36 100644
--- a/flight/targets/playuavosd/fw/Makefile
+++ b/flight/targets/playuavosd/fw/Makefile
@@ -188,6 +188,9 @@ CDEFS += -DARM_MATH_ROUNDING
CDEFS += -D__FPU_PRESENT=1
CDEFS += -DUNALIGNED_SUPPORT_DISABLE
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
# Debugging format.
DEBUGF = dwarf-2
@@ -215,7 +218,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/quanton/fw/Makefile b/flight/targets/quanton/fw/Makefile
index 35ac1e5421..8c766eacac 100644
--- a/flight/targets/quanton/fw/Makefile
+++ b/flight/targets/quanton/fw/Makefile
@@ -186,6 +186,9 @@ CDEFS += -DARM_MATH_ROUNDING
CDEFS += -D__FPU_PRESENT=1
CDEFS += -DUNALIGNED_SUPPORT_DISABLE
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
# Debugging format.
DEBUGF = dwarf-2
@@ -214,7 +217,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/revolution/fw/Makefile b/flight/targets/revolution/fw/Makefile
index f1059b8cf3..3ed96af6db 100644
--- a/flight/targets/revolution/fw/Makefile
+++ b/flight/targets/revolution/fw/Makefile
@@ -222,6 +222,9 @@ CDEFS += -DUNALIGNED_SUPPORT_DISABLE
# This is not the best place for these. Really should abstract out
# to the board file or something
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -DMEM_SIZE=1024000000
# Output format. (can be ihex or binary or both)
@@ -254,7 +257,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/seppuku/fw/Makefile b/flight/targets/seppuku/fw/Makefile
index 6a2979b455..6f36998fbf 100644
--- a/flight/targets/seppuku/fw/Makefile
+++ b/flight/targets/seppuku/fw/Makefile
@@ -194,6 +194,9 @@ CDEFS += -DARM_MATH_ROUNDING
CDEFS += -D__FPU_PRESENT=1
CDEFS += -DUNALIGNED_SUPPORT_DISABLE
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
# Debugging format.
DEBUGF = dwarf-2
@@ -222,7 +225,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/sparky/board-info/board_hw_defs.c b/flight/targets/sparky/board-info/board_hw_defs.c
index 255a510f2f..ea1cc7c44c 100644
--- a/flight/targets/sparky/board-info/board_hw_defs.c
+++ b/flight/targets/sparky/board-info/board_hw_defs.c
@@ -1045,7 +1045,11 @@ static struct pios_internal_adc_cfg internal_adc_cfg = {
static const struct pios_usb_cfg pios_usb_main_cfg = {
.irq = {
.init = {
+#if STM32_HAS_USB
+ .NVIC_IRQChannel = USB_LP_IRQn,
+#else
.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn,
+#endif
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
diff --git a/flight/targets/sparky/fw/Makefile b/flight/targets/sparky/fw/Makefile
index 08c2675e28..57407b4c73 100644
--- a/flight/targets/sparky/fw/Makefile
+++ b/flight/targets/sparky/fw/Makefile
@@ -45,7 +45,7 @@ OPTMODULES += CameraStab
OPTMODULES += Autotune
OPTMODULES += TxPID
OPTMODULES += PathPlanner
-OPTMODULES += VtolPathFollower
+#OPTMODULES += VtolPathFollower
OPTMODULES += FixedWingPathFollower
OPTMODULES += UAVOMavlinkBridge
OPTMODULES += UAVOMSPBridge
@@ -58,7 +58,7 @@ OPTMODULES += UAVOFrSKYSensorHubBridge
OPTMODULES += UAVOFrSKYSPortBridge
OPTMODULES += Geofence
OPTMODULES += Logging
-OPTMODULES += Storm32Bgc
+#OPTMODULES += Storm32Bgc
OPTMODULES += UAVOCrossfireTelemetry
# Paths
@@ -184,7 +184,10 @@ CDEFS += -DUNALIGNED_SUPPORT_DISABLE
# This is not the best place for these. Really should abstract out
# to the board file or something
-CFLAGS += -DSTM32F30X
+CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -DMEM_SIZE=$(FW_BANK_SIZE)
# Debugging format.
@@ -215,7 +218,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/sparky2/fw/Makefile b/flight/targets/sparky2/fw/Makefile
index 3a27a2c51e..ff711a1f6d 100644
--- a/flight/targets/sparky2/fw/Makefile
+++ b/flight/targets/sparky2/fw/Makefile
@@ -219,6 +219,9 @@ CDEFS += -DUNALIGNED_SUPPORT_DISABLE
# This is not the best place for these. Really should abstract out
# to the board file or something
CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -DMEM_SIZE=1024000000
# Output format. (can be ihex or binary or both)
@@ -254,7 +257,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/flight/targets/sprf3e/board-info/board_hw_defs.c b/flight/targets/sprf3e/board-info/board_hw_defs.c
index 17ca33c4a6..1eeffc3147 100644
--- a/flight/targets/sprf3e/board-info/board_hw_defs.c
+++ b/flight/targets/sprf3e/board-info/board_hw_defs.c
@@ -900,7 +900,11 @@ static const struct pios_internal_adc_cfg internal_adc_cfg = {
static const struct pios_usb_cfg pios_usb_main_cfg = {
.irq = {
.init = {
+#if STM32_HAS_USB
+ .NVIC_IRQChannel = USB_LP_IRQn,
+#else
.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn,
+#endif
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
diff --git a/flight/targets/sprf3e/fw/Makefile b/flight/targets/sprf3e/fw/Makefile
index c4470b0078..c79f6c7130 100644
--- a/flight/targets/sprf3e/fw/Makefile
+++ b/flight/targets/sprf3e/fw/Makefile
@@ -168,8 +168,8 @@ endif
# common architecture-specific flags from the device-specific library makefile
CFLAGS += $(ARCHFLAGS)
-CFLAGS += -DDIAGNOSTICS
-CFLAGS += -DDIAG_TASKS
+#CFLAGS += -DDIAGNOSTICS
+#CFLAGS += -DDIAG_TASKS
# configure CMSIS DSP Library
CDEFS += -DARM_MATH_CM4
@@ -180,7 +180,10 @@ CDEFS += -DUNALIGNED_SUPPORT_DISABLE
# This is not the best place for these. Really should abstract out
# to the board file or something
-CFLAGS += -DSTM32F30X
+CFLAGS += -D$(STM32_TYPE)
+ifneq ($(STM32_SUBTYPE),)
+CFLAGS += -D$(STM32_SUBTYPE)
+endif
CFLAGS += -DMEM_SIZE=$(FW_BANK_SIZE)
# Debugging format.
@@ -211,7 +214,7 @@ CDEFS += ${BUILTIN_DEFS}
# Place project-specific -D and/or -U options for
# Assembler with preprocessor here.
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
-ADEFS = -D__ASSEMBLY__
+ADEFS += -D__ASSEMBLY__
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
diff --git a/make/firmware-arches.mk b/make/firmware-arches.mk
index 13352967fb..7bae541c9f 100644
--- a/make/firmware-arches.mk
+++ b/make/firmware-arches.mk
@@ -11,7 +11,8 @@ else ifneq "$(findstring STM32F40,$(CHIP))" ""
OPENOCD_JTAG_CONFIG ?= stlink-v2.cfg
OPENOCD_CONFIG := stm32f4x.cfg
MCU := cortex-m4
-STM32_TYPE := STM32F40_41xxx
+STM32_TYPE := STM32F405xx
+STM32_SUBTYPE := STM32F40_41xxx
ARCH_TYPES := STM32F4xx STM32
else ifneq "$(findstring STM32F30,$(CHIP))" ""
OPENOCD_JTAG_CONFIG ?= stlink-v2.cfg