RAM Organisation.md

Memory Array Structure

![[basic_memory_array.drawio.svg]] Generally we attempt to make the memory array as square as possible (word-lines $\approx$ bit-lines) to reduce [[Parasitic Capacitance]] of both groups of lines.

• This only allows for a single address & data bus supporting a single read/write port.

MultiPort Memory

Increasing bandwidth of read with multiple read ports.