Build an extern function using CAM module

[MarioPatetta]

Hello,

I'm trying to build an extern function that includes a Content Addressable Memory module. I would like to use the verilog and vhdl files available in P4-NetFPGA-live/lib/hw/xilinx/cores/cam_v1_1_0/hdl.

I've then copied those files inside my extern hdl directory and when I compile a .p4 file that instantiates that extern with the P4-SDNet compiler (step 4 of the workflow) everything runs smoothly. When I try to run the SDNet simulation though, I get the following errors:

ERROR: [VRFC 10-2063] Module <cam_top> not found while processing module instance <cam_top> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/ipv4_cam_lut_0_t.HDL/cam_wrapper.v:53]
ERROR: [VRFC 10-2063] Module <true_dp_bram> not found while processing module instance <ipv4_bram> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/ipv4_cam_lut_0_t.HDL/ipv4_cam_lut_0_t.v:168]
ERROR: [VRFC 10-2063] Module <TopPipe_lvl_1_t> not found while processing module instance <TopPipe_lvl_1> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:653]
ERROR: [VRFC 10-2063] Module <TopDeparser_t> not found while processing module instance <TopDeparser> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:685]
ERROR: [VRFC 10-2063] Module <S_BRIDGER_for_forward_tuple_in_request> not found while processing module instance <S_BRIDGER_for_forward_tuple_in_request> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:727]
ERROR: [VRFC 10-2063] Module <S_BRIDGER_for_ipv4_cam_lut_0_tuple_in_ipv4_cam_lut_input> not found while processing module instance <S_BRIDGER_for_ipv4_cam_lut_0_tuple_in_ipv4_cam_lut_input> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:741]
ERROR: [VRFC 10-2063] Module <S_PROTOCOL_ADAPTER_INGRESS> not found while processing module instance <S_PROTOCOL_ADAPTER_INGRESS> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:755]
ERROR: [VRFC 10-2063] Module <S_PROTOCOL_ADAPTER_EGRESS> not found while processing module instance <S_PROTOCOL_ADAPTER_EGRESS> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:778]
ERROR: [VRFC 10-2063] Module <S_SYNCER_for_TopParser> not found while processing module instance <S_SYNCER_for_TopParser> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:800]
ERROR: [VRFC 10-2063] Module <S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser> not found while processing module instance <S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:842]
ERROR: [VRFC 10-2063] Module <S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser> not found while processing module instance <S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:916]
ERROR: [VRFC 10-2063] Module <S_SYNCER_for_S_SYNCER_for_TopDeparser> not found while processing module instance <S_SYNCER_for_S_SYNCER_for_TopDeparser> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:1014]
ERROR: [VRFC 10-2063] Module <S_SYNCER_for_TopDeparser> not found while processing module instance <S_SYNCER_for_TopDeparser> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:1120]
ERROR: [VRFC 10-2063] Module <S_SYNCER_for__OUT_> not found while processing module instance <S_SYNCER_for__OUT_> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:1194]
ERROR: [VRFC 10-2063] Module <S_CONTROLLER_SimpleSumeSwitch> not found while processing module instance <S_CONTROL_SimpleSumeSwitch> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:1232]
ERROR: [VRFC 10-2063] Module <TB_System_Stim> not found while processing module instance <TB_System_Stim_i> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv:143]
ERROR: [VRFC 10-2063] Module <Check> not found while processing module instance <TB_System_Check_i> [/home/mario/mario_test/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects/cam_lut/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv:162]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

After a little debugging, I've realised that the problem seems to occur when the verilog file cam_wrapper.v instantiates a module described in cam_top.vhd, a vdhl file. I've tried substituting cam_top.vhd with a dummy verilog file just to test if that was the cause of the errors and in fact I got no errors afterwards.

It seems than that mixing verilog and vhdl is not possible in the context of externs description. Can somebody give me confirmation of this and/or any advices? In the mean time I will start translating .vhd files into .v ones.

Thanks in advance.