diff --git a/libpresifuzz_observers/Cargo.toml b/libpresifuzz_observers/Cargo.toml index 71bb39f..d68147d 100644 --- a/libpresifuzz_observers/Cargo.toml +++ b/libpresifuzz_observers/Cargo.toml @@ -45,3 +45,5 @@ lazy_static = "1.4.0" elf = "0.7.4" rand = "0.8.5" tempfile = "3.9.0" +flate2 = "1.0" +quick-xml = "0.32.0" diff --git a/libpresifuzz_observers/src/lib.rs b/libpresifuzz_observers/src/lib.rs index 5d09673..65da3ac 100644 --- a/libpresifuzz_observers/src/lib.rs +++ b/libpresifuzz_observers/src/lib.rs @@ -3,4 +3,5 @@ // SPDX-License-Identifier: Apache-2.0 pub mod verdi_observer; +pub mod verdi_xml_observer; diff --git a/libpresifuzz_observers/src/verdi_xml_observer.rs b/libpresifuzz_observers/src/verdi_xml_observer.rs new file mode 100644 index 0000000..76c6dfe --- /dev/null +++ b/libpresifuzz_observers/src/verdi_xml_observer.rs @@ -0,0 +1,408 @@ +// SPDX-FileCopyrightText: 2022 Intel Corporation +// +// SPDX-License-Identifier: Apache-2.0 + +use libafl::{ + executors::{ExitKind}, + observers::{MapObserver, Observer}, + observers::{DifferentialObserver, ObserversTuple}, + Error, + inputs::{UsesInput}, +}; + +use core::{ + slice::from_raw_parts, + fmt::Debug, + slice::IterMut, + slice::Iter, +}; +use serde::{Deserialize, Serialize}; +use libafl_bolts::{ + AsIter, AsIterMut, HasLen, Named, +}; + +use std::fs::File; +use std::io::prelude::*; +use flate2::bufread::GzDecoder; +use quick_xml::Reader; +use quick_xml::events::Event; + +extern crate fs_extra; +use std::{ + str, + hash::Hasher, +}; +use ahash::AHasher; + +#[derive(Copy, Clone, Serialize, Deserialize, Debug)] +pub enum VerdiCoverageMetric { + Line = 4, + Toggle = 5, + FSM = 6, + Condition = 7, + Branch = 8, + Assert = 9, +} + +/// A simple observer, just overlooking the runtime of the target. +#[derive(Clone, Serialize, Deserialize, Debug)] +#[allow(clippy::unsafe_derive_deserialize)] +pub struct VerdiXMLMapObserver +{ + name: String, + map: Vec, + vdb: String, + workdir: String, + metric: VerdiCoverageMetric, + filter: String +} + +impl VerdiXMLMapObserver +{ + /// Creates a new [`MapObserver`] + /// + /// # Note + /// Will get a pointer to the map and dereference it at any point in time. + /// The map must not move in memory! + #[must_use] + pub fn new(name: &'static str, vdb: &String, workdir: &str, metric: VerdiCoverageMetric, filter: &String) -> Self { + + Self { + name: name.to_string(), + map: Vec::::new(), + workdir: workdir.to_string(), + metric, + filter: filter.to_string(), + vdb: vdb.to_string() + } + } + + /// Gets cnt as usize + #[must_use] + pub fn cnt(&self) -> usize { + self.map.len() + } + + /// Gets map ptr + #[must_use] + pub fn my_map(&self) -> &[u32] { + self.map.as_slice() + } + +} + +impl Named for VerdiXMLMapObserver +{ + fn name(&self) -> &str { + &self.name + } +} + +impl HasLen for VerdiXMLMapObserver +{ + fn len(&self) -> usize { + self.map.len() + } +} + +impl MapObserver for VerdiXMLMapObserver +{ + type Entry = u32; + + #[inline] + fn initial(&self) -> u32 { + 0 + } + + #[inline] + fn get(&self, idx: usize) -> &u32 { + &self.map.as_slice()[idx] + } + + #[inline] + fn get_mut(&mut self, idx: usize) -> &mut u32 { + &mut self.map.as_mut_slice()[idx] + } + + /// Count the set bytes in the map + fn count_bytes(&self) -> u64 { + let initial = self.initial(); + let cnt = self.usable_count(); + let map = self.map.as_slice(); + let mut res = 0; + for x in map[0..cnt].iter() { + if *x != initial { + res += 1; + } + } + res + } + + fn usable_count(&self) -> usize { + self.map.as_slice().len() + } + + fn hash(&self) -> u64 { + + let slice = &self.map.as_slice(); + + let mut hasher = AHasher::new_with_keys(0, 0); + let ptr = slice.as_ptr() as *const u8; + let map_size = slice.len() / core::mem::size_of::(); + unsafe { + hasher.write(from_raw_parts(ptr, map_size)); + } + hasher.finish() + } + + /// Reset the map + #[inline] + fn reset_map(&mut self) -> Result<(), Error> { + // Normal memset, see https://rust.godbolt.org/z/Trs5hv + let initial = self.initial(); + let cnt = self.usable_count(); + let map = self.map.as_mut_slice(); + for x in map[0..cnt].iter_mut() { + *x = initial; + } + Ok(()) + } + + fn to_vec(&self) -> Vec { + self.map.as_slice().to_vec() + } + + /// Get the number of set entries with the specified indexes + fn how_many_set(&self, indexes: &[usize]) -> usize { + let initial = self.initial(); + let cnt = self.usable_count(); + let map = self.map.as_slice(); + let mut res = 0; + for i in indexes { + if *i < cnt && map[*i] != initial { + res += 1; + } + } + res + } +} + +impl Observer for VerdiXMLMapObserver +where + S: UsesInput, +{ + fn pre_exec(&mut self, _state: &mut S, _input: &S::Input) -> Result<(), Error> { + let initial = self.initial(); + let map = self.map.as_mut_slice(); + for x in map.iter_mut() { + *x = initial; + } + Ok(()) + } + + #[inline] + fn post_exec( + &mut self, + _state: &mut S, + _input: &S::Input, + _exit_kind: &ExitKind, + ) -> Result<(), Error> { + + // Path to the gzip-compressed XML file + let xml_file = match self.metric { + VerdiCoverageMetric::Toggle => "tgl.verilog.data.xml", + VerdiCoverageMetric::Line => "line.verilog.data.xml", + VerdiCoverageMetric::FSM => "fsm.verilog.data.xml", + VerdiCoverageMetric::Branch => "branch.verilog.data.xml", + VerdiCoverageMetric::Condition => "cond.verilog.data.xml", + VerdiCoverageMetric::Assert => "assert.verilog.data.xml", + }; + + let xml_file = format!("./{}/snps/coverage/db/testdata/test/{}", self.vdb, xml_file); + let xml_file_ = xml_file.clone(); + + // Open the gzip-compressed file + let mut coverage_file = File::open(xml_file).expect("Unable to open file xml coverage file"); + + let mut buffer = Vec::new(); + coverage_file.read_to_end(&mut buffer).expect("Unable to read the file tail the end"); + + let mut gz = GzDecoder::new(&buffer[..]); + let mut xml_str = String::new(); + gz.read_to_string(&mut xml_str).expect("Unable to unzip using GzDecoder"); + + // Create an XML reader + let mut xml_reader = Reader::from_str(&xml_str); + xml_reader.config_mut().trim_text(true); + + let mut concatenated_bits = String::new(); + + // Variables to hold the XML event state + // Iterate over the XML events + loop { + match xml_reader.read_event() { + Ok(Event::Start(ref e)) if e.name() == quick_xml::name::QName(b"instance_data") => { + 'attr_loop: for attr in e.attributes() { + match attr { + Ok(attr) => { + // stop if filter does not match + if attr.key == quick_xml::name::QName(b"name") && ! attr.unescape_value().unwrap().contains(self.filter.as_str()) { + + break 'attr_loop; + + } else if attr.key == quick_xml::name::QName(b"value") { + + let tmp_str = &attr.unescape_value().unwrap(); + println!("item of {} bits: {:?}", tmp_str.len(), tmp_str); + + concatenated_bits.push_str(tmp_str); + } + + } + Err(_) => {continue;}, + } + } + } + Ok(Event::Eof) => break, // Exit the loop when reaching the end of file + Err(e) => panic!("Error while parsing vdb xml files {} at position {}: {:?}", xml_file_, xml_reader.buffer_position(), e), + _ => (), // Ignore other events + } + } + + // we saved the bitmap in str format into concatenated_bits + // This consumes a bit of memory, but then it is easier to translate the String into a + // concatenated chain of bit: bitmap. + + let bit_len = concatenated_bits.len(); + let mut start = 0; + + while start < bit_len { + + // process 32bits chunks at max + let end = (start + 32).min(bit_len); + let bit_chunk = &concatenated_bits[start..end]; + + // translates str to u32 with radix 2 + let value = u32::from_str_radix(bit_chunk, 2).unwrap(); + + // Normally, only last chunk might be not 32bits aligned so we add padding with 0 + let value = if end - start < 32 { + value << (32 - (end - start)) + } else { + value + }; + + self.map.push(value); + start += 32; + } + + for value in &self.map { + println!("{:032b}", value); // Print the binary representation of each u32 value + } + + Ok(()) + } +} + +impl<'it> AsIter<'it> for VerdiXMLMapObserver +{ + type Item = u32; + type IntoIter = Iter<'it, u32>; + + fn as_iter(&'it self) -> Self::IntoIter { + let cnt = self.usable_count(); + self.map.as_slice()[..cnt].iter() + } +} + +impl<'it> AsIterMut<'it> for VerdiXMLMapObserver +{ + type Item = u32; + type IntoIter = IterMut<'it, u32>; + + fn as_iter_mut(&'it mut self) -> Self::IntoIter { + let cnt = self.usable_count(); + self.map.as_mut_slice()[..cnt].iter_mut() + } +} + +impl DifferentialObserver for VerdiXMLMapObserver +where + OTA: ObserversTuple, + OTB: ObserversTuple, + S: UsesInput, +{ + fn pre_observe_first(&mut self, _observers: &mut OTA) -> Result<(), Error> { + Ok(()) + } + + fn post_observe_first(&mut self, _observers: &mut OTA) -> Result<(), Error> { + Ok(()) + } + + fn pre_observe_second(&mut self, _observers: &mut OTB) -> Result<(), Error> { + Ok(()) + } + + fn post_observe_second(&mut self, _observers: &mut OTB) -> Result<(), Error> { + Ok(()) + } +} + + +// TODO: Re-enable this test using vdb from open source design +#[cfg(feature = "std")] +#[cfg(test)] +mod tests { + + extern crate fs_extra; + use libc::{c_uint, c_char, c_void}; + use nix::{sys::wait::waitpid,unistd::{fork, ForkResult}}; + use std::process; + use libafl_bolts::prelude::StdRand; + use libafl::prelude::BytesInput; + use libafl::executors::{ExitKind}; + use libafl_bolts::current_time; + use libafl::prelude::InMemoryCorpus; + use libafl::prelude::Testcase; + use libafl::prelude::ConstFeedback; + use crate::verdi_xml_observer::VerdiXMLMapObserver; + use crate::verdi_xml_observer::VerdiCoverageMetric; + use libafl::prelude::StdState; + use libafl::state::HasMaxSize; + use libafl::observers::Observer; + + #[test] + fn test_verdi_xml_observer() { + + let input = BytesInput::new(vec![1, 2, 3, 4]); + + let rand = StdRand::with_seed(current_time().as_nanos() as u64); + let corpus = InMemoryCorpus::::new(); + + let mut feedback = ConstFeedback::new(true); + let mut objective = ConstFeedback::new(false); + + + let mut verdi_observer = VerdiXMLMapObserver::new( + "verdi_map", + &String::from("test.vdb"), + "", + VerdiCoverageMetric::Toggle, + &"chiptop0".to_string() + ); + + let mut state = StdState::new( + rand, + corpus, + InMemoryCorpus::::new(), + &mut feedback, + &mut objective, + ) + .unwrap(); + state.set_max_size(1024); + + let _ = verdi_observer.post_exec(&mut state, &input, &ExitKind::Ok); + } +} + diff --git a/libpresifuzz_observers/test.vdb/.cmoptions b/libpresifuzz_observers/test.vdb/.cmoptions new file mode 100644 index 0000000..dbc1475 --- /dev/null +++ b/libpresifuzz_observers/test.vdb/.cmoptions @@ -0,0 +1,24 @@ +Instrument +cond 16643 +line 3 +fsm 65539 +tgl 8 +assign 0 +obc 0 +path 3 +branch 3 +Count 0 +Glitch -1 +cm_tglmda 0 +cm_tglstructarr 1 +cm_tglcount 0 +cm_tglunencryptedsignals 0 +cm_hier 0 +InstrSpecs 2 +TglUnpkdLimitVal -1 +IrisFlow -1 +scalene_no_dump_design 0 +cm_assert_hier 0 +cm_common_hier 0 +sdc 0 +CmHierOpt -1 \ No newline at end of file diff --git a/libpresifuzz_observers/test.vdb/.mode64 b/libpresifuzz_observers/test.vdb/.mode64 new file mode 100644 index 0000000..e69de29 diff --git a/libpresifuzz_observers/test.vdb/.vdb_version b/libpresifuzz_observers/test.vdb/.vdb_version new file mode 100644 index 0000000..efbe897 --- /dev/null +++ b/libpresifuzz_observers/test.vdb/.vdb_version @@ -0,0 +1 @@ +V-2023.12 \ No newline at end of file diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/.cm_totalPaths b/libpresifuzz_observers/test.vdb/snps/coverage/db/.cm_totalPaths new file mode 100644 index 0000000..00f7823 --- /dev/null +++ b/libpresifuzz_observers/test.vdb/snps/coverage/db/.cm_totalPaths @@ -0,0 +1 @@ +49957302 \ No newline at end of file diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/dve_debug.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/dve_debug.xml new file mode 100644 index 0000000..621135a Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/dve_debug.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/vcmArguments.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/vcmArguments.xml new file mode 100644 index 0000000..1413e08 Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/vcmArguments.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt b/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt new file mode 100644 index 0000000..e69de29 diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml new file mode 100644 index 0000000..5edca3d --- /dev/null +++ b/libpresifuzz_observers/test.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml @@ -0,0 +1,410 @@ + + + + + + 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+TestDriver.testHarness.chiptop0.system.mbus.fixer.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.mbus.fixer.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.mbus.picker.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.mbus.picker.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.mbus.picker.monitor_1.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.mbus.picker.monitor_1.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.mbus.coupler_to_memory_controller_port_named_axi4.tl2axi4.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.mbus.coupler_to_memory_controller_port_named_axi4.tl2axi4.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.ctrls.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.ctrls.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sourceA.io_a_q.ram_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sourceC.queue.ram_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sourceD.queue.ram_data_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sourceE.io_e_q.ram_sink_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkA.putbuffer.head_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkA.putbuffer.tail_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkA.putbuffer.next_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkA.putbuffer.data_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkC.c_q.ram_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkC.putbuffer.head_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkC.putbuffer.tail_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkC.putbuffer.next_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkC.putbuffer.data_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.sinkD.d_q.ram_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.requests.head_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.requests.tail_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.requests.next_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.l2.inclusive_cache_bank_sched.requests.data_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.InclusiveCache_inner_TLBuffer.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.InclusiveCache_inner_TLBuffer.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.coh_wrapper.cork.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.cork.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.coh_wrapper.cork.q.ram_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.cork.q_1.ram_ext00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.binder.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.coh_wrapper.binder.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.element_reset_domain_rockettile.tlMasterXbar.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.element_reset_domain_rockettile.tlMasterXbar.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.element_reset_domain_rockettile.tlMasterXbar.monitor_1.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.element_reset_domain_rockettile.tlMasterXbar.monitor_1.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.element_reset_domain_rockettile.frontend.btb.table_ext00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.element_reset_domain_rockettile.fpuOpt.regfile_ext00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.element_reset_domain_rockettile.core.rf_ext00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.element_reset_domain_rockettile.core.PlusArgTimeout.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.buffer.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.buffer.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.buffer.nodeOut_a_q.ram_ext00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.buffer.nodeIn_d_q.ram_ext00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.buffer.nodeIn_b_q.ram_ext00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.buffer.nodeOut_c_q.ram_ext00 +TestDriver.testHarness.chiptop0.system.tile_prci_domain.buffer.nodeOut_e_q.ram_sink_ext00 +TestDriver.testHarness.chiptop0.system.clint_domain.clint.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.clint_domain.clint.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.domain.plic.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.domain.plic.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.dmiXbar.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.dmiXbar.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.dmOuter.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.dmOuter.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.dmiBypass.bar.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.dmiBypass.bar.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.dmiBypass.error.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.dmiBypass.error.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.asource.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tlDM.dmOuter.asource.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tlDM.dmInner.dmInner.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tlDM.dmInner.dmInner.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.tlDM.dmInner.dmInner.monitor_1.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.tlDM.dmInner.dmInner.monitor_1.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.bootrom_domain.bootrom.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.bootrom_domain.bootrom.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.bank.ram.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.bank.ram.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.uartClockDomainWrapper.uart_0.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.uartClockDomainWrapper.uart_0.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.uartClockDomainWrapper.uart_0.txm.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.uartClockDomainWrapper.uart_0.txm.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.uartClockDomainWrapper.uart_0.txq.ram_ext00 +TestDriver.testHarness.chiptop0.system.uartClockDomainWrapper.uart_0.rxq.ram_ext00 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.xbar.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.xbar.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.clock_gater.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.clock_gater.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.fragmenter.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.fragmenter.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.reset_setter.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.reset_setter.monitor.plusarg_reader_100 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.fragmenter_1.monitor.plusarg_reader00 +TestDriver.testHarness.chiptop0.system.chipyard_prcictrl_domain.fragmenter_1.monitor.plusarg_reader_100 +TestDriver.testHarness.uart_sim_0_uartno0.txq.ram_ext00 +TestDriver.testHarness.uart_sim_0_uartno0.rxm.plusarg_reader00 +TestDriver.testHarness.uart_sim_0_uartno0.rxm.plusarg_reader_100 +TestDriver.testHarness.uart_sim_0_uartno0.rxq.ram_ext00 +TestDriver.testHarness.plusarg_reader00 +TestDriver.testHarness.jtag00 +TestDriver.testHarness.plusarg_reader_100 +TestDriver.testHarness.ram.serdesser.monitor.plusarg_reader00 +TestDriver.testHarness.ram.serdesser.monitor.plusarg_reader_100 +TestDriver.testHarness.ram.buffer.monitor.plusarg_reader00 +TestDriver.testHarness.ram.buffer.monitor.plusarg_reader_100 +TestDriver.testHarness.ram.buffer.nodeOut_a_q.ram_ext00 +TestDriver.testHarness.ram.buffer.nodeIn_d_q.ram_ext00 +UARTRx_TestHarness_UNIQUIFIED4390 +UARTTx_TestHarness_UNIQUIFIED4390 +UARTTx_TestHarness_UNIQUIFIED.plusarg_reader00 +UARTTx_TestHarness_UNIQUIFIED.plusarg_reader_100 +plusarg_reader_TestHarness_UNIQUIFIED00 diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/design/verilog.design.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/design/verilog.design.xml new file mode 100644 index 0000000..f59ca51 Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/design/verilog.design.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.exclude.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.exclude.xml new file mode 100644 index 0000000..871fb0a Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.exclude.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.info.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.info.xml new file mode 100644 index 0000000..1c0bb15 Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.info.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.shape.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.shape.xml new file mode 100644 index 0000000..04e2ea7 Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/branch.verilog.shape.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml new file mode 100644 index 0000000..871fb0a Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.info.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.info.xml new file mode 100644 index 0000000..3fb4608 Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.info.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.shape.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.shape.xml new file mode 100644 index 0000000..05094dc Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/cond.verilog.shape.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml new file mode 100644 index 0000000..529d7ca --- /dev/null +++ b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml @@ -0,0 +1,2 @@ + + diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt new file mode 100644 index 0000000..fa4798a --- /dev/null +++ b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt @@ -0,0 +1,208 @@ +// Synopsys, Inc. +// User: unknown +// Date: Mon Jun 3 15:15:00 2024 + +// ================================================================================================== +// This config file prototype is produced from the last run using the complete list of extracted fsms. +// Please note that by providing your own description of the module you are enforcing what will be +// extracted for that module. +// Copy this file to your source directory and edit it as described below, +// then pass the file to VCS using the -cm_fsmcfg command line option. +// FSMs will be extracted normally for any module not mentioned in this file +// ================================================================================================== +// 1. For every module that you want to specify yourself, use: +// MODULE==name +// ----------------------------------------------------- +// The following options are defining the behavior on the module level. +// ----------------------------------------------------- +// 1.1 You can control what fsms should be used within this module: +// FSMS=AUTO +// this means that you want VCS to automatically extract all +// detectable FSMs from this module. +// ----------------------------------------------------- +// FSMS=EXCLUDE +// this means that you want all fsms except the ones from the list that follows +// if the list is empty, all fsms will be extracted for this module +// ----------------------------------------------------- +// FSMS=RESTRICT +// this means that you want only the fsms from the list that follows +// if the list is empty, no fsms will be extracted for this module +// ----------------------------------------------------- +// If none of these options are specified, the program will assume FSMS=RESTRICT +// ----------------------------------------------------- +// 1.2 You can specify that the state with the minimal value should be used as a +// start state for all sequences in every fsm in the module. +// FSMS=START_STATE_DFLT +// For any particular fsm you can overwrite this behavior inside its description. +// ----------------------------------------------------- +// 2. Each fsm description in the list of fsms should be specified as follows: +// 2.1 provide the current state variable declaration: +// CURRENT= name of the current state variable +// ----------------------------------------------------- +// 2.2 if next state variable is different from the current state provide: +// NEXT= next state variable +// if you don't use NEXT=, the program will assume that CURRENT and NEXT are the same +// ----------------------------------------------------- +// 2.3 if you want to provide the restrictive the list of states, provide: +// STATES= s0,s1 etc. where s0 is either a name or a value of the state +// if you don't use STATES=, the program will assume that you want to use all states +// ----------------------------------------------------- +// 2.4 if you want to ignore some states, specify them in the following list: +// STATES_X= s0,s1, etc. +// ----------------------------------------------------- +// 2.5 if you want to mark, that some states should never be reached, specify them as a list: +// STATES_NEVER= s0,s1, etc. +// ----------------------------------------------------- +// 2.6 similar to the STATES, if you want to provide the restrictive the list of transitions, specify: +// TRANSITIONS= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.7 similar to the STATES_X, if you want to ignore some transitions, specify them in the following list: +// TRANSITIONS_X= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.8 similar to the STATES_NEVER,if you want to mark, that some transitions should never occur, +// specify them as a list: +// TRANSITIONS_NEVER= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.9 if you want to specify the start state use: +// START_STATE= s0 +// ----------------------------------------------------- +// Please note: +// - that a state in every list can be specified either by name or by value. +// - in specifying the transitions you can use * in order to refer to 'any' state. +// ================================================================================================== +// Uncomment and modify the following 2 line to override default FSM sequence limits for all FSMs in the design. +//SEQ_NUMBER_MAX=10000 +//SEQ_LENGTH_MAX=32 + +MODULE=TLAtomicAutomata_1 +CURRENT=cam_s_0_state +NEXT=cam_s_0_state +STATES='h0,'h1,'h2,'h3 +TRANSITIONS='h0->'h3, +'h1->'h0, +'h2->'h0, +'h2->'h1, +'h3->'h0 +MODULE=TLDebugModuleInner +CURRENT=ctrlStateReg +NEXT=ctrlStateReg +STATES='h0,'h1,'h2 +TRANSITIONS='h0->'h1, +'h1->'h0, +'h2->'h0, +'h2->'h1 +MODULE=PTW +CURRENT=state +NEXT=state +STATES='h0,'h1,'h2,'h3,'h4 +TRANSITIONS='h0->'h1, +'h1->'h0, +'h2->'h0, +'h2->'h1, +'h3->'h0, +'h3->'h1, +'h4->'h0, +'h4->'h1 +MODULE=MulDiv +CURRENT=state +NEXT=state +STATES='h0,'h1,'h2,'h3,'h5,'h6,'h7 +TRANSITIONS='h0->'h2, +'h1->'h0, +'h1->'h3, +'h2->'h0, +'h2->'h6, +'h3->'h0, +'h5->'h0, +'h5->'h7, +'h6->'h0, +'h7->'h0 +MODULE=TLB_1 +CURRENT=state +NEXT=state +STATES='h0,'h1,'h2,'h3 +TRANSITIONS='h0->'h1, +'h1->'h0, +'h2->'h0, +'h2->'h3, +'h3->'h0 +MODULE=TLAtomicAutomata +CURRENT=cam_s_0_state +NEXT=cam_s_0_state +STATES='h0,'h1,'h2,'h3 +TRANSITIONS='h0->'h3, +'h1->'h0, +'h2->'h0, +'h2->'h1, +'h3->'h0 +MODULE=TSIToTileLink +CURRENT=state +NEXT=state +STATES='h0,'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8 +TRANSITIONS='h0->'h1, +'h1->'h0, +'h1->'h2, +'h2->'h0, +'h2->'h3, +'h2->'h6, +'h3->'h0, +'h3->'h4, +'h4->'h0, +'h4->'h5, +'h5->'h0, +'h5->'h3, +'h6->'h0, +'h6->'h7, +'h7->'h0, +'h7->'h8, +'h8->'h0, +'h8->'h6 +MODULE=DCache +CURRENT=tlb_state +NEXT=tlb_state +STATES='h0,'h1,'h2,'h3 +TRANSITIONS='h0->'h1, +'h1->'h0, +'h2->'h0, +'h2->'h3, +'h3->'h0 +MODULE=DCache +CURRENT=release_state +NEXT=release_state +STATES='h0,'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h9 +TRANSITIONS='h0->'h2, +'h0->'h5, +'h1->'h0, +'h1->'h2, +'h1->'h5, +'h1->'h6, +'h2->'h0, +'h2->'h7, +'h3->'h0, +'h3->'h7, +'h4->'h0, +'h4->'h2, +'h4->'h5, +'h5->'h0, +'h5->'h2, +'h6->'h0, +'h6->'h2, +'h6->'h5, +'h7->'h0, +'h7->'h2, +'h7->'h5, +'h9->'h0, +'h9->'h2, +'h9->'h5, +'h9->'h6 +MODULE=MSHR +CURRENT=meta_state +NEXT=meta_state +STATES='h0,'h1,'h2,'h3 +TRANSITIONS='h0->'h1, +'h1->'h0, +'h2->'h0, +'h2->'h1, +'h2->'h3, +'h3->'h0, +'h3->'h1 diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml new file mode 100644 index 0000000..d35f28a Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml differ diff --git a/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/line.verilog.exclude.xml b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/line.verilog.exclude.xml new file mode 100644 index 0000000..871fb0a Binary files /dev/null and b/libpresifuzz_observers/test.vdb/snps/coverage/db/shape/line.verilog.exclude.xml differ diff --git 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