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module 'axi_intercon_2x64_128_bd' not found #832

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zacaric opened this issue Jan 13, 2025 · 2 comments
Open

module 'axi_intercon_2x64_128_bd' not found #832

zacaric opened this issue Jan 13, 2025 · 2 comments

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@zacaric
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zacaric commented Jan 13, 2025

Issue Description

I get the following error when building my custom OOT module with custom rfnoc blocks

ERROR: [Synth 8-439] module 'axi_intercon_2x64_128_bd' not found [/workspaces/rfnoc-my_oot/build/ip/xc7k410tffg900-2/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v:384]
ERROR: [Synth 8-6156] failed synthesizing module 'axi_intercon_2x64_128_bd_wrapper' [/workspaces/rfnoc-my_oot/build/ip/xc7k410tffg900-2/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v:12]
ERROR: [Synth 8-6156] failed synthesizing module 'x300_core' [/uhd/fpga/usrp3/top/x300/x300_core.v:10]
ERROR: [Synth 8-6156] failed synthesizing module 'x300' [/uhd/fpga/usrp3/top/x300/x300.v:20]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
[00:00:38] Current task: Synthesis +++ Current Phase: Starting
[00:00:38] Current task: Synthesis +++ Current Phase: Finished
[00:00:38] Process terminated. Status: Failure

Setup Details

UHD 4.7.0.0-210-ge75629c3 in a Ubuntu 22.04 docker image

Expected Behavior

Not to have this error

Actual Behaviour

I get this error

Steps to reproduce the problem

  1. Create new oot with rfnoc_modtool
  2. Copy gain example's yaml file
  3. Replaced the name gain with my block name
  4. Added xci files that I already made to rfnoc/my_oot/ip/<ip_name>/<ip_name>.xci
  5. Created Makefile.inc in rfnoc/my_oot/ip/<ip_name> and added the following (replacing <ip_name> with the name of my IP:
    THIS_IP_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
    
    <ip_name>_NAME = <ip_name>
    LIB_IP_<ip_name>_SRCS = $(IP_BUILD_DIR)/$(<ip_name>_NAME)/$(<ip_name>_NAME).xci
    
    LIB_IP_<ip_name>_OUTS = $(addprefix $(IP_BUILD_DIR)/$(<ip_name>_NAME)/, \
    $(<ip_name>_NAME).xci.out \
    synth/$(<ip_name>_NAME).vhd \
    )
    
    .INTERMEDIATE: LIB_IP_<ip_name>_TRGT
    $(LIB_IP_<ip_name>_SRCS) $(LIB_IP_<ip_name>_OUTS): LIB_IP_<ip_name>_TRGT
        @:
    
    # This include provides BUILD_VIVADO_IP
    include $(TOOLS_DIR)/make/viv_ip_builder.mak
    
    LIB_IP_<ip_name>_TRGT: $(THIS_IP_DIR)/$(<ip_name>_NAME).xci
    $(call BUILD_VIVADO_IP,$(<ip_name>_NAME),$(ARCH),$(PART_ID),$(THIS_IP_DIR)/..,$(IP_BUILD_DIR),0)
  6. Add the following to fpga/<oot_name>/CMakeLists.txt:
    install(
        DIRECTORY ip/
        DESTINATION ${GATEWARE_PKG_DATA_DIR}/ip
        COMPONENT gateware
     )
  7. Add the following in the rfnoc block yaml file (rfnoc/blocks/<block_name>.yml)
    fpga_includes:
      - include: "fpga/<oot_name>/rfnoc_block_<block_name>/Makefile.srcs"
        make_var: "$(RFNOC_BLOCK_<block_name>_SRCS)"
      - include: "fpga/<oot_name>/ip/<ip_name>/Makefile.inc"
        make_var: "$(LIB_IP_<ip_name>_SRCS)"
  8. Copied x310_rfnoc_image_core.yml from the gain example into the icores dir and replaced gain with the name of my block
  9. Added RFNOC_REGISTER_IMAGE_CORE(SRC x310_rfnoc_image_core.yml) to icores/CMakeLists.txt
  10. Installed the rfnoc block
  11. Ran the following commands to build the image:
    mkdir icore_build && cd icore_build
    rfnoc_image_builder -y ../icores/x310_rfnoc_image_core.yml -F /uhd/fpga -B . -E ./ip --save-project -j $(nproc) -p /tools/Xilinx/Vivado -I ../
  12. Got the error

Additional Information

@wordimont
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wordimont commented Jan 15, 2025

Just a thought, but sometimes this happens if a build gets killed or has an error in which the IP starts getting generated but isn't fully generated. Can you look in the build location, in the build-ip directory, and try deleting the directory for the axi_intercon_2x64_128_bd IP, then rebuild the FPGA? It should regenerate that directory with a fresh copy of the IP automatically. Also, look in the logs/console to see if there are any errors at the point where it generates axi_intercon_2x64_128_bd that might give a clue. I can't tell if the IP is missing for you or if it just can't find it for some reason.

@zacaric
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zacaric commented Jan 16, 2025

Can you look in the build location, in the build-ip directory, and try deleting the directory for the axi_intercon_2x64_128_bd IP, then rebuild the FPGA? It should regenerate that directory with a fresh copy of the IP automatically.

That didn't work. Got the same error.

Also, look in the logs/console to see if there are any errors at the point where it generates axi_intercon_2x64_128_bd that might give a clue.

Looking at the main build log file just gives me the same error.

Looking at the log file for axi_intercon_2x64_128_bd doesn't have any errors at all and seems to generate the files just fine. Although it doesn't generate an xci file and instead just creates a wrapper for the bd file. Not sure if it is also supposed to package it as an IP or not...

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